1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* QLogic qede NIC Driver 3 * Copyright (c) 2015-2017 QLogic Corporation 4 * Copyright (c) 2019-2020 Marvell International Ltd. 5 */ 6 7 #ifndef _QEDE_H_ 8 #define _QEDE_H_ 9 #include <linux/compiler.h> 10 #include <linux/version.h> 11 #include <linux/workqueue.h> 12 #include <linux/netdevice.h> 13 #include <linux/interrupt.h> 14 #include <linux/bitmap.h> 15 #include <linux/kernel.h> 16 #include <linux/mutex.h> 17 #include <linux/bpf.h> 18 #include <net/xdp.h> 19 #include <linux/qed/qede_rdma.h> 20 #include <linux/io.h> 21 #ifdef CONFIG_RFS_ACCEL 22 #include <linux/cpu_rmap.h> 23 #endif 24 #include <linux/qed/common_hsi.h> 25 #include <linux/qed/eth_common.h> 26 #include <linux/qed/qed_if.h> 27 #include <linux/qed/qed_chain.h> 28 #include <linux/qed/qed_eth_if.h> 29 30 #include <net/pkt_cls.h> 31 #include <net/tc_act/tc_gact.h> 32 33 #define QEDE_MAJOR_VERSION 8 34 #define QEDE_MINOR_VERSION 37 35 #define QEDE_REVISION_VERSION 0 36 #define QEDE_ENGINEERING_VERSION 20 37 #define DRV_MODULE_VERSION __stringify(QEDE_MAJOR_VERSION) "." \ 38 __stringify(QEDE_MINOR_VERSION) "." \ 39 __stringify(QEDE_REVISION_VERSION) "." \ 40 __stringify(QEDE_ENGINEERING_VERSION) 41 42 #define DRV_MODULE_SYM qede 43 44 struct qede_stats_common { 45 u64 no_buff_discards; 46 u64 packet_too_big_discard; 47 u64 ttl0_discard; 48 u64 rx_ucast_bytes; 49 u64 rx_mcast_bytes; 50 u64 rx_bcast_bytes; 51 u64 rx_ucast_pkts; 52 u64 rx_mcast_pkts; 53 u64 rx_bcast_pkts; 54 u64 mftag_filter_discards; 55 u64 mac_filter_discards; 56 u64 gft_filter_drop; 57 u64 tx_ucast_bytes; 58 u64 tx_mcast_bytes; 59 u64 tx_bcast_bytes; 60 u64 tx_ucast_pkts; 61 u64 tx_mcast_pkts; 62 u64 tx_bcast_pkts; 63 u64 tx_err_drop_pkts; 64 u64 coalesced_pkts; 65 u64 coalesced_events; 66 u64 coalesced_aborts_num; 67 u64 non_coalesced_pkts; 68 u64 coalesced_bytes; 69 u64 link_change_count; 70 u64 ptp_skip_txts; 71 72 /* port */ 73 u64 rx_64_byte_packets; 74 u64 rx_65_to_127_byte_packets; 75 u64 rx_128_to_255_byte_packets; 76 u64 rx_256_to_511_byte_packets; 77 u64 rx_512_to_1023_byte_packets; 78 u64 rx_1024_to_1518_byte_packets; 79 u64 rx_crc_errors; 80 u64 rx_mac_crtl_frames; 81 u64 rx_pause_frames; 82 u64 rx_pfc_frames; 83 u64 rx_align_errors; 84 u64 rx_carrier_errors; 85 u64 rx_oversize_packets; 86 u64 rx_jabbers; 87 u64 rx_undersize_packets; 88 u64 rx_fragments; 89 u64 tx_64_byte_packets; 90 u64 tx_65_to_127_byte_packets; 91 u64 tx_128_to_255_byte_packets; 92 u64 tx_256_to_511_byte_packets; 93 u64 tx_512_to_1023_byte_packets; 94 u64 tx_1024_to_1518_byte_packets; 95 u64 tx_pause_frames; 96 u64 tx_pfc_frames; 97 u64 brb_truncates; 98 u64 brb_discards; 99 u64 tx_mac_ctrl_frames; 100 }; 101 102 struct qede_stats_bb { 103 u64 rx_1519_to_1522_byte_packets; 104 u64 rx_1519_to_2047_byte_packets; 105 u64 rx_2048_to_4095_byte_packets; 106 u64 rx_4096_to_9216_byte_packets; 107 u64 rx_9217_to_16383_byte_packets; 108 u64 tx_1519_to_2047_byte_packets; 109 u64 tx_2048_to_4095_byte_packets; 110 u64 tx_4096_to_9216_byte_packets; 111 u64 tx_9217_to_16383_byte_packets; 112 u64 tx_lpi_entry_count; 113 u64 tx_total_collisions; 114 }; 115 116 struct qede_stats_ah { 117 u64 rx_1519_to_max_byte_packets; 118 u64 tx_1519_to_max_byte_packets; 119 }; 120 121 struct qede_stats { 122 struct qede_stats_common common; 123 124 union { 125 struct qede_stats_bb bb; 126 struct qede_stats_ah ah; 127 }; 128 }; 129 130 struct qede_vlan { 131 struct list_head list; 132 u16 vid; 133 bool configured; 134 }; 135 136 struct qede_rdma_dev { 137 struct qedr_dev *qedr_dev; 138 struct list_head entry; 139 struct list_head rdma_event_list; 140 struct workqueue_struct *rdma_wq; 141 struct kref refcnt; 142 struct completion event_comp; 143 bool exp_recovery; 144 }; 145 146 struct qede_ptp; 147 148 #define QEDE_RFS_MAX_FLTR 256 149 150 enum qede_flags_bit { 151 QEDE_FLAGS_IS_VF = 0, 152 QEDE_FLAGS_LINK_REQUESTED, 153 QEDE_FLAGS_PTP_TX_IN_PRORGESS, 154 QEDE_FLAGS_TX_TIMESTAMPING_EN 155 }; 156 157 #define QEDE_DUMP_MAX_ARGS 4 158 enum qede_dump_cmd { 159 QEDE_DUMP_CMD_NONE = 0, 160 QEDE_DUMP_CMD_NVM_CFG, 161 QEDE_DUMP_CMD_GRCDUMP, 162 QEDE_DUMP_CMD_MAX 163 }; 164 165 struct qede_dump_info { 166 enum qede_dump_cmd cmd; 167 u8 num_args; 168 u32 args[QEDE_DUMP_MAX_ARGS]; 169 }; 170 171 struct qede_coalesce { 172 bool isvalid; 173 u16 rxc; 174 u16 txc; 175 }; 176 177 struct qede_dev { 178 struct qed_dev *cdev; 179 struct net_device *ndev; 180 struct pci_dev *pdev; 181 struct devlink *devlink; 182 183 u32 dp_module; 184 u8 dp_level; 185 186 unsigned long flags; 187 #define IS_VF(edev) test_bit(QEDE_FLAGS_IS_VF, \ 188 &(edev)->flags) 189 190 const struct qed_eth_ops *ops; 191 struct qede_ptp *ptp; 192 u64 ptp_skip_txts; 193 194 struct qed_dev_eth_info dev_info; 195 #define QEDE_MAX_RSS_CNT(edev) ((edev)->dev_info.num_queues) 196 #define QEDE_MAX_TSS_CNT(edev) ((edev)->dev_info.num_queues) 197 #define QEDE_IS_BB(edev) \ 198 ((edev)->dev_info.common.dev_type == QED_DEV_TYPE_BB) 199 #define QEDE_IS_AH(edev) \ 200 ((edev)->dev_info.common.dev_type == QED_DEV_TYPE_AH) 201 202 struct qede_fastpath *fp_array; 203 struct qede_coalesce *coal_entry; 204 u8 req_num_tx; 205 u8 fp_num_tx; 206 u8 req_num_rx; 207 u8 fp_num_rx; 208 u16 req_queues; 209 u16 num_queues; 210 u16 total_xdp_queues; 211 212 #define QEDE_QUEUE_CNT(edev) ((edev)->num_queues) 213 #define QEDE_RSS_COUNT(edev) ((edev)->num_queues - (edev)->fp_num_tx) 214 #define QEDE_RX_QUEUE_IDX(edev, i) (i) 215 #define QEDE_TSS_COUNT(edev) ((edev)->num_queues - (edev)->fp_num_rx) 216 217 struct qed_int_info int_info; 218 219 /* Smaller private variant of the RTNL lock */ 220 struct mutex qede_lock; 221 u32 state; /* Protected by qede_lock */ 222 u16 rx_buf_size; 223 u32 rx_copybreak; 224 225 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 226 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8) 227 /* Max supported alignment is 256 (8 shift) 228 * minimal alignment shift 6 is optimal for 57xxx HW performance 229 */ 230 #define QEDE_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT)) 231 /* We assume skb_build() uses sizeof(struct skb_shared_info) bytes 232 * at the end of skb->data, to avoid wasting a full cache line. 233 * This reduces memory use (skb->truesize). 234 */ 235 #define QEDE_FW_RX_ALIGN_END \ 236 max_t(u64, 1UL << QEDE_RX_ALIGN_SHIFT, \ 237 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 238 239 struct qede_stats stats; 240 241 /* Bitfield to track initialized RSS params */ 242 u32 rss_params_inited; 243 #define QEDE_RSS_INDIR_INITED BIT(0) 244 #define QEDE_RSS_KEY_INITED BIT(1) 245 #define QEDE_RSS_CAPS_INITED BIT(2) 246 247 u16 rss_ind_table[128]; 248 u32 rss_key[10]; 249 u8 rss_caps; 250 251 /* Both must be a power of two */ 252 u16 q_num_rx_buffers; 253 u16 q_num_tx_buffers; 254 255 bool gro_disable; 256 257 struct list_head vlan_list; 258 u16 configured_vlans; 259 u16 non_configured_vlans; 260 bool accept_any_vlan; 261 262 struct delayed_work sp_task; 263 unsigned long sp_flags; 264 u16 vxlan_dst_port; 265 u16 geneve_dst_port; 266 267 struct qede_arfs *arfs; 268 bool wol_enabled; 269 270 struct qede_rdma_dev rdma_info; 271 272 struct bpf_prog *xdp_prog; 273 274 enum qed_hw_err_type last_err_type; 275 unsigned long err_flags; 276 #define QEDE_ERR_IS_HANDLED 31 277 #define QEDE_ERR_ATTN_CLR_EN 0 278 #define QEDE_ERR_GET_DBG_INFO 1 279 #define QEDE_ERR_IS_RECOVERABLE 2 280 #define QEDE_ERR_WARN 3 281 282 struct qede_dump_info dump_info; 283 }; 284 285 enum QEDE_STATE { 286 QEDE_STATE_CLOSED, 287 QEDE_STATE_OPEN, 288 QEDE_STATE_RECOVERY, 289 }; 290 291 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 292 293 #define MAX_NUM_TC 8 294 #define MAX_NUM_PRI 8 295 296 /* The driver supports the new build_skb() API: 297 * RX ring buffer contains pointer to kmalloc() data only, 298 * skb are built only after the frame was DMA-ed. 299 */ 300 struct sw_rx_data { 301 struct page *data; 302 dma_addr_t mapping; 303 unsigned int page_offset; 304 }; 305 306 enum qede_agg_state { 307 QEDE_AGG_STATE_NONE = 0, 308 QEDE_AGG_STATE_START = 1, 309 QEDE_AGG_STATE_ERROR = 2 310 }; 311 312 struct qede_agg_info { 313 /* rx_buf is a data buffer that can be placed / consumed from rx bd 314 * chain. It has two purposes: We will preallocate the data buffer 315 * for each aggregation when we open the interface and will place this 316 * buffer on the rx-bd-ring when we receive TPA_START. We don't want 317 * to be in a state where allocation fails, as we can't reuse the 318 * consumer buffer in the rx-chain since FW may still be writing to it 319 * (since header needs to be modified for TPA). 320 * The second purpose is to keep a pointer to the bd buffer during 321 * aggregation. 322 */ 323 struct sw_rx_data buffer; 324 struct sk_buff *skb; 325 326 /* We need some structs from the start cookie until termination */ 327 u16 vlan_tag; 328 329 bool tpa_start_fail; 330 u8 state; 331 u8 frag_id; 332 333 u8 tunnel_type; 334 }; 335 336 struct qede_rx_queue { 337 __le16 *hw_cons_ptr; 338 void __iomem *hw_rxq_prod_addr; 339 340 /* Required for the allocation of replacement buffers */ 341 struct device *dev; 342 343 struct bpf_prog *xdp_prog; 344 345 u16 sw_rx_cons; 346 u16 sw_rx_prod; 347 348 u16 filled_buffers; 349 u8 data_direction; 350 u8 rxq_id; 351 352 /* Used once per each NAPI run */ 353 u16 num_rx_buffers; 354 355 u16 rx_headroom; 356 357 u32 rx_buf_size; 358 u32 rx_buf_seg_size; 359 360 struct sw_rx_data *sw_rx_ring; 361 struct qed_chain rx_bd_ring; 362 struct qed_chain rx_comp_ring ____cacheline_aligned; 363 364 /* GRO */ 365 struct qede_agg_info tpa_info[ETH_TPA_MAX_AGGS_NUM]; 366 367 /* Used once per each NAPI run */ 368 u64 rcv_pkts; 369 370 u64 rx_hw_errors; 371 u64 rx_alloc_errors; 372 u64 rx_ip_frags; 373 374 u64 xdp_no_pass; 375 376 void *handle; 377 struct xdp_rxq_info xdp_rxq; 378 }; 379 380 union db_prod { 381 struct eth_db_data data; 382 u32 raw; 383 }; 384 385 struct sw_tx_bd { 386 struct sk_buff *skb; 387 u8 flags; 388 /* Set on the first BD descriptor when there is a split BD */ 389 #define QEDE_TSO_SPLIT_BD BIT(0) 390 }; 391 392 struct sw_tx_xdp { 393 struct page *page; 394 struct xdp_frame *xdpf; 395 dma_addr_t mapping; 396 }; 397 398 struct qede_tx_queue { 399 u8 is_xdp; 400 bool is_legacy; 401 u16 sw_tx_cons; 402 u16 sw_tx_prod; 403 u16 num_tx_buffers; /* Slowpath only */ 404 405 u64 xmit_pkts; 406 u64 stopped_cnt; 407 u64 tx_mem_alloc_err; 408 409 __le16 *hw_cons_ptr; 410 411 /* Needed for the mapping of packets */ 412 struct device *dev; 413 414 void __iomem *doorbell_addr; 415 union db_prod tx_db; 416 417 /* Spinlock for XDP queues in case of XDP_REDIRECT */ 418 spinlock_t xdp_tx_lock; 419 420 int index; /* Slowpath only */ 421 #define QEDE_TXQ_XDP_TO_IDX(edev, txq) ((txq)->index - \ 422 QEDE_MAX_TSS_CNT(edev)) 423 #define QEDE_TXQ_IDX_TO_XDP(edev, idx) ((idx) + QEDE_MAX_TSS_CNT(edev)) 424 #define QEDE_NDEV_TXQ_ID_TO_FP_ID(edev, idx) ((edev)->fp_num_rx + \ 425 ((idx) % QEDE_TSS_COUNT(edev))) 426 #define QEDE_NDEV_TXQ_ID_TO_TXQ_COS(edev, idx) ((idx) / QEDE_TSS_COUNT(edev)) 427 #define QEDE_TXQ_TO_NDEV_TXQ_ID(edev, txq) ((QEDE_TSS_COUNT(edev) * \ 428 (txq)->cos) + (txq)->index) 429 #define QEDE_NDEV_TXQ_ID_TO_TXQ(edev, idx) \ 430 (&((edev)->fp_array[QEDE_NDEV_TXQ_ID_TO_FP_ID(edev, idx)].txq \ 431 [QEDE_NDEV_TXQ_ID_TO_TXQ_COS(edev, idx)])) 432 #define QEDE_FP_TC0_TXQ(fp) (&((fp)->txq[0])) 433 434 /* Regular Tx requires skb + metadata for release purpose, 435 * while XDP requires the pages and the mapped address. 436 */ 437 union { 438 struct sw_tx_bd *skbs; 439 struct sw_tx_xdp *xdp; 440 } sw_tx_ring; 441 442 struct qed_chain tx_pbl; 443 444 /* Slowpath; Should be kept in end [unless missing padding] */ 445 void *handle; 446 u16 cos; 447 u16 ndev_txq_id; 448 }; 449 450 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr.hi), \ 451 le32_to_cpu((bd)->addr.lo)) 452 #define BD_SET_UNMAP_ADDR_LEN(bd, maddr, len) \ 453 do { \ 454 (bd)->addr.hi = cpu_to_le32(upper_32_bits(maddr)); \ 455 (bd)->addr.lo = cpu_to_le32(lower_32_bits(maddr)); \ 456 (bd)->nbytes = cpu_to_le16(len); \ 457 } while (0) 458 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 459 460 struct qede_fastpath { 461 struct qede_dev *edev; 462 463 u8 type; 464 #define QEDE_FASTPATH_TX BIT(0) 465 #define QEDE_FASTPATH_RX BIT(1) 466 #define QEDE_FASTPATH_XDP BIT(2) 467 #define QEDE_FASTPATH_COMBINED (QEDE_FASTPATH_TX | QEDE_FASTPATH_RX) 468 469 u8 id; 470 471 u8 xdp_xmit; 472 #define QEDE_XDP_TX BIT(0) 473 #define QEDE_XDP_REDIRECT BIT(1) 474 475 struct napi_struct napi; 476 struct qed_sb_info *sb_info; 477 struct qede_rx_queue *rxq; 478 struct qede_tx_queue *txq; 479 struct qede_tx_queue *xdp_tx; 480 481 char name[IFNAMSIZ + 8]; 482 }; 483 484 /* Debug print definitions */ 485 #define DP_NAME(edev) netdev_name((edev)->ndev) 486 487 #define XMIT_PLAIN 0 488 #define XMIT_L4_CSUM BIT(0) 489 #define XMIT_LSO BIT(1) 490 #define XMIT_ENC BIT(2) 491 #define XMIT_ENC_GSO_L4_CSUM BIT(3) 492 493 #define QEDE_CSUM_ERROR BIT(0) 494 #define QEDE_CSUM_UNNECESSARY BIT(1) 495 #define QEDE_TUNN_CSUM_UNNECESSARY BIT(2) 496 497 #define QEDE_SP_RECOVERY 0 498 #define QEDE_SP_RX_MODE 1 499 #define QEDE_SP_RSVD1 2 500 #define QEDE_SP_RSVD2 3 501 #define QEDE_SP_HW_ERR 4 502 #define QEDE_SP_ARFS_CONFIG 5 503 #define QEDE_SP_AER 7 504 505 #ifdef CONFIG_RFS_ACCEL 506 int qede_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 507 u16 rxq_index, u32 flow_id); 508 #define QEDE_SP_TASK_POLL_DELAY (5 * HZ) 509 #endif 510 511 void qede_process_arfs_filters(struct qede_dev *edev, bool free_fltr); 512 void qede_poll_for_freeing_arfs_filters(struct qede_dev *edev); 513 void qede_arfs_filter_op(void *dev, void *filter, u8 fw_rc); 514 void qede_free_arfs(struct qede_dev *edev); 515 int qede_alloc_arfs(struct qede_dev *edev); 516 int qede_add_cls_rule(struct qede_dev *edev, struct ethtool_rxnfc *info); 517 int qede_delete_flow_filter(struct qede_dev *edev, u64 cookie); 518 int qede_get_cls_rule_entry(struct qede_dev *edev, struct ethtool_rxnfc *cmd); 519 int qede_get_cls_rule_all(struct qede_dev *edev, struct ethtool_rxnfc *info, 520 u32 *rule_locs); 521 int qede_get_arfs_filter_count(struct qede_dev *edev); 522 523 struct qede_reload_args { 524 void (*func)(struct qede_dev *edev, struct qede_reload_args *args); 525 union { 526 netdev_features_t features; 527 struct bpf_prog *new_prog; 528 u16 mtu; 529 } u; 530 }; 531 532 /* Datapath functions definition */ 533 netdev_tx_t qede_start_xmit(struct sk_buff *skb, struct net_device *ndev); 534 int qede_xdp_transmit(struct net_device *dev, int n_frames, 535 struct xdp_frame **frames, u32 flags); 536 u16 qede_select_queue(struct net_device *dev, struct sk_buff *skb, 537 struct net_device *sb_dev); 538 netdev_features_t qede_features_check(struct sk_buff *skb, 539 struct net_device *dev, 540 netdev_features_t features); 541 int qede_alloc_rx_buffer(struct qede_rx_queue *rxq, bool allow_lazy); 542 int qede_free_tx_pkt(struct qede_dev *edev, 543 struct qede_tx_queue *txq, int *len); 544 int qede_poll(struct napi_struct *napi, int budget); 545 irqreturn_t qede_msix_fp_int(int irq, void *fp_cookie); 546 547 /* Filtering function definitions */ 548 void qede_force_mac(void *dev, u8 *mac, bool forced); 549 void qede_udp_ports_update(void *dev, u16 vxlan_port, u16 geneve_port); 550 int qede_set_mac_addr(struct net_device *ndev, void *p); 551 552 int qede_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid); 553 int qede_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid); 554 void qede_vlan_mark_nonconfigured(struct qede_dev *edev); 555 int qede_configure_vlan_filters(struct qede_dev *edev); 556 557 netdev_features_t qede_fix_features(struct net_device *dev, 558 netdev_features_t features); 559 int qede_set_features(struct net_device *dev, netdev_features_t features); 560 void qede_set_rx_mode(struct net_device *ndev); 561 void qede_config_rx_mode(struct net_device *ndev); 562 void qede_fill_rss_params(struct qede_dev *edev, 563 struct qed_update_vport_rss_params *rss, u8 *update); 564 565 void qede_udp_tunnel_add(struct net_device *dev, struct udp_tunnel_info *ti); 566 void qede_udp_tunnel_del(struct net_device *dev, struct udp_tunnel_info *ti); 567 568 int qede_xdp(struct net_device *dev, struct netdev_bpf *xdp); 569 570 #ifdef CONFIG_DCB 571 void qede_set_dcbnl_ops(struct net_device *ndev); 572 #endif 573 574 void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level); 575 void qede_set_ethtool_ops(struct net_device *netdev); 576 void qede_set_udp_tunnels(struct qede_dev *edev); 577 void qede_reload(struct qede_dev *edev, 578 struct qede_reload_args *args, bool is_locked); 579 int qede_change_mtu(struct net_device *dev, int new_mtu); 580 void qede_fill_by_demand_stats(struct qede_dev *edev); 581 void __qede_lock(struct qede_dev *edev); 582 void __qede_unlock(struct qede_dev *edev); 583 bool qede_has_rx_work(struct qede_rx_queue *rxq); 584 int qede_txq_has_work(struct qede_tx_queue *txq); 585 void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq, u8 count); 586 void qede_update_rx_prod(struct qede_dev *edev, struct qede_rx_queue *rxq); 587 int qede_add_tc_flower_fltr(struct qede_dev *edev, __be16 proto, 588 struct flow_cls_offload *f); 589 590 void qede_forced_speed_maps_init(void); 591 int qede_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal); 592 int qede_set_per_coalesce(struct net_device *dev, u32 queue, 593 struct ethtool_coalesce *coal); 594 595 #define RX_RING_SIZE_POW 13 596 #define RX_RING_SIZE ((u16)BIT(RX_RING_SIZE_POW)) 597 #define NUM_RX_BDS_MAX (RX_RING_SIZE - 1) 598 #define NUM_RX_BDS_MIN 128 599 #define NUM_RX_BDS_KDUMP_MIN 63 600 #define NUM_RX_BDS_DEF ((u16)BIT(10) - 1) 601 602 #define TX_RING_SIZE_POW 13 603 #define TX_RING_SIZE ((u16)BIT(TX_RING_SIZE_POW)) 604 #define NUM_TX_BDS_MAX (TX_RING_SIZE - 1) 605 #define NUM_TX_BDS_MIN 128 606 #define NUM_TX_BDS_KDUMP_MIN 63 607 #define NUM_TX_BDS_DEF NUM_TX_BDS_MAX 608 609 #define QEDE_MIN_PKT_LEN 64 610 #define QEDE_RX_HDR_SIZE 256 611 #define QEDE_MAX_JUMBO_PACKET_SIZE 9600 612 #define for_each_queue(i) for (i = 0; i < edev->num_queues; i++) 613 #define for_each_cos_in_txq(edev, var) \ 614 for ((var) = 0; (var) < (edev)->dev_info.num_tc; (var)++) 615 616 #endif /* _QEDE_H_ */ 617