1 /* QLogic qede NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #ifndef _QEDE_H_ 10 #define _QEDE_H_ 11 #include <linux/compiler.h> 12 #include <linux/version.h> 13 #include <linux/workqueue.h> 14 #include <linux/netdevice.h> 15 #include <linux/interrupt.h> 16 #include <linux/bitmap.h> 17 #include <linux/kernel.h> 18 #include <linux/mutex.h> 19 #include <linux/io.h> 20 #include <linux/qed/common_hsi.h> 21 #include <linux/qed/eth_common.h> 22 #include <linux/qed/qed_if.h> 23 #include <linux/qed/qed_chain.h> 24 #include <linux/qed/qed_eth_if.h> 25 26 #define QEDE_MAJOR_VERSION 8 27 #define QEDE_MINOR_VERSION 4 28 #define QEDE_REVISION_VERSION 0 29 #define QEDE_ENGINEERING_VERSION 0 30 #define DRV_MODULE_VERSION __stringify(QEDE_MAJOR_VERSION) "." \ 31 __stringify(QEDE_MINOR_VERSION) "." \ 32 __stringify(QEDE_REVISION_VERSION) "." \ 33 __stringify(QEDE_ENGINEERING_VERSION) 34 35 #define QEDE_ETH_INTERFACE_VERSION 300 36 37 #define DRV_MODULE_SYM qede 38 39 struct qede_stats { 40 u64 no_buff_discards; 41 u64 rx_ucast_bytes; 42 u64 rx_mcast_bytes; 43 u64 rx_bcast_bytes; 44 u64 rx_ucast_pkts; 45 u64 rx_mcast_pkts; 46 u64 rx_bcast_pkts; 47 u64 mftag_filter_discards; 48 u64 mac_filter_discards; 49 u64 tx_ucast_bytes; 50 u64 tx_mcast_bytes; 51 u64 tx_bcast_bytes; 52 u64 tx_ucast_pkts; 53 u64 tx_mcast_pkts; 54 u64 tx_bcast_pkts; 55 u64 tx_err_drop_pkts; 56 u64 coalesced_pkts; 57 u64 coalesced_events; 58 u64 coalesced_aborts_num; 59 u64 non_coalesced_pkts; 60 u64 coalesced_bytes; 61 62 /* port */ 63 u64 rx_64_byte_packets; 64 u64 rx_127_byte_packets; 65 u64 rx_255_byte_packets; 66 u64 rx_511_byte_packets; 67 u64 rx_1023_byte_packets; 68 u64 rx_1518_byte_packets; 69 u64 rx_1522_byte_packets; 70 u64 rx_2047_byte_packets; 71 u64 rx_4095_byte_packets; 72 u64 rx_9216_byte_packets; 73 u64 rx_16383_byte_packets; 74 u64 rx_crc_errors; 75 u64 rx_mac_crtl_frames; 76 u64 rx_pause_frames; 77 u64 rx_pfc_frames; 78 u64 rx_align_errors; 79 u64 rx_carrier_errors; 80 u64 rx_oversize_packets; 81 u64 rx_jabbers; 82 u64 rx_undersize_packets; 83 u64 rx_fragments; 84 u64 tx_64_byte_packets; 85 u64 tx_65_to_127_byte_packets; 86 u64 tx_128_to_255_byte_packets; 87 u64 tx_256_to_511_byte_packets; 88 u64 tx_512_to_1023_byte_packets; 89 u64 tx_1024_to_1518_byte_packets; 90 u64 tx_1519_to_2047_byte_packets; 91 u64 tx_2048_to_4095_byte_packets; 92 u64 tx_4096_to_9216_byte_packets; 93 u64 tx_9217_to_16383_byte_packets; 94 u64 tx_pause_frames; 95 u64 tx_pfc_frames; 96 u64 tx_lpi_entry_count; 97 u64 tx_total_collisions; 98 u64 brb_truncates; 99 u64 brb_discards; 100 u64 tx_mac_ctrl_frames; 101 }; 102 103 struct qede_dev { 104 struct qed_dev *cdev; 105 struct net_device *ndev; 106 struct pci_dev *pdev; 107 108 u32 dp_module; 109 u8 dp_level; 110 111 const struct qed_eth_ops *ops; 112 113 struct qed_dev_eth_info dev_info; 114 #define QEDE_MAX_RSS_CNT(edev) ((edev)->dev_info.num_queues) 115 #define QEDE_MAX_TSS_CNT(edev) ((edev)->dev_info.num_queues * \ 116 (edev)->dev_info.num_tc) 117 118 struct qede_fastpath *fp_array; 119 u16 num_rss; 120 u8 num_tc; 121 #define QEDE_RSS_CNT(edev) ((edev)->num_rss) 122 #define QEDE_TSS_CNT(edev) ((edev)->num_rss * \ 123 (edev)->num_tc) 124 #define QEDE_TSS_IDX(edev, txqidx) ((txqidx) % (edev)->num_rss) 125 #define QEDE_TC_IDX(edev, txqidx) ((txqidx) / (edev)->num_rss) 126 #define QEDE_TX_QUEUE(edev, txqidx) \ 127 (&(edev)->fp_array[QEDE_TSS_IDX((edev), (txqidx))].txqs[QEDE_TC_IDX( \ 128 (edev), (txqidx))]) 129 130 struct qed_int_info int_info; 131 unsigned char primary_mac[ETH_ALEN]; 132 133 /* Smaller private varaiant of the RTNL lock */ 134 struct mutex qede_lock; 135 u32 state; /* Protected by qede_lock */ 136 u16 rx_buf_size; 137 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 138 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8) 139 /* Max supported alignment is 256 (8 shift) 140 * minimal alignment shift 6 is optimal for 57xxx HW performance 141 */ 142 #define QEDE_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT)) 143 /* We assume skb_build() uses sizeof(struct skb_shared_info) bytes 144 * at the end of skb->data, to avoid wasting a full cache line. 145 * This reduces memory use (skb->truesize). 146 */ 147 #define QEDE_FW_RX_ALIGN_END \ 148 max_t(u64, 1UL << QEDE_RX_ALIGN_SHIFT, \ 149 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 150 151 struct qede_stats stats; 152 struct qed_update_vport_rss_params rss_params; 153 u16 q_num_rx_buffers; /* Must be a power of two */ 154 u16 q_num_tx_buffers; /* Must be a power of two */ 155 156 struct delayed_work sp_task; 157 unsigned long sp_flags; 158 }; 159 160 enum QEDE_STATE { 161 QEDE_STATE_CLOSED, 162 QEDE_STATE_OPEN, 163 }; 164 165 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 166 167 #define MAX_NUM_TC 8 168 #define MAX_NUM_PRI 8 169 170 /* The driver supports the new build_skb() API: 171 * RX ring buffer contains pointer to kmalloc() data only, 172 * skb are built only after the frame was DMA-ed. 173 */ 174 struct sw_rx_data { 175 u8 *data; 176 177 DEFINE_DMA_UNMAP_ADDR(mapping); 178 }; 179 180 struct qede_rx_queue { 181 __le16 *hw_cons_ptr; 182 struct sw_rx_data *sw_rx_ring; 183 u16 sw_rx_cons; 184 u16 sw_rx_prod; 185 struct qed_chain rx_bd_ring; 186 struct qed_chain rx_comp_ring; 187 void __iomem *hw_rxq_prod_addr; 188 189 int rx_buf_size; 190 191 u16 num_rx_buffers; 192 u16 rxq_id; 193 194 u64 rx_hw_errors; 195 u64 rx_alloc_errors; 196 }; 197 198 union db_prod { 199 struct eth_db_data data; 200 u32 raw; 201 }; 202 203 struct sw_tx_bd { 204 struct sk_buff *skb; 205 u8 flags; 206 /* Set on the first BD descriptor when there is a split BD */ 207 #define QEDE_TSO_SPLIT_BD BIT(0) 208 }; 209 210 struct qede_tx_queue { 211 int index; /* Queue index */ 212 __le16 *hw_cons_ptr; 213 struct sw_tx_bd *sw_tx_ring; 214 u16 sw_tx_cons; 215 u16 sw_tx_prod; 216 struct qed_chain tx_pbl; 217 void __iomem *doorbell_addr; 218 union db_prod tx_db; 219 220 u16 num_tx_buffers; 221 }; 222 223 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr.hi), \ 224 le32_to_cpu((bd)->addr.lo)) 225 #define BD_SET_UNMAP_ADDR_LEN(bd, maddr, len) \ 226 do { \ 227 (bd)->addr.hi = cpu_to_le32(upper_32_bits(maddr)); \ 228 (bd)->addr.lo = cpu_to_le32(lower_32_bits(maddr)); \ 229 (bd)->nbytes = cpu_to_le16(len); \ 230 } while (0) 231 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 232 233 struct qede_fastpath { 234 struct qede_dev *edev; 235 u8 rss_id; 236 struct napi_struct napi; 237 struct qed_sb_info *sb_info; 238 struct qede_rx_queue *rxq; 239 struct qede_tx_queue *txqs; 240 241 #define VEC_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 242 char name[VEC_NAME_SIZE]; 243 }; 244 245 /* Debug print definitions */ 246 #define DP_NAME(edev) ((edev)->ndev->name) 247 248 #define XMIT_PLAIN 0 249 #define XMIT_L4_CSUM BIT(0) 250 #define XMIT_LSO BIT(1) 251 #define XMIT_ENC BIT(2) 252 253 #define QEDE_CSUM_ERROR BIT(0) 254 #define QEDE_CSUM_UNNECESSARY BIT(1) 255 256 #define QEDE_SP_RX_MODE 1 257 258 union qede_reload_args { 259 u16 mtu; 260 }; 261 262 void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level); 263 void qede_set_ethtool_ops(struct net_device *netdev); 264 void qede_reload(struct qede_dev *edev, 265 void (*func)(struct qede_dev *edev, 266 union qede_reload_args *args), 267 union qede_reload_args *args); 268 int qede_change_mtu(struct net_device *dev, int new_mtu); 269 void qede_fill_by_demand_stats(struct qede_dev *edev); 270 271 #define RX_RING_SIZE_POW 13 272 #define RX_RING_SIZE BIT(RX_RING_SIZE_POW) 273 #define NUM_RX_BDS_MAX (RX_RING_SIZE - 1) 274 #define NUM_RX_BDS_MIN 128 275 #define NUM_RX_BDS_DEF NUM_RX_BDS_MAX 276 277 #define TX_RING_SIZE_POW 13 278 #define TX_RING_SIZE BIT(TX_RING_SIZE_POW) 279 #define NUM_TX_BDS_MAX (TX_RING_SIZE - 1) 280 #define NUM_TX_BDS_MIN 128 281 #define NUM_TX_BDS_DEF NUM_TX_BDS_MAX 282 283 #define for_each_rss(i) for (i = 0; i < edev->num_rss; i++) 284 285 #endif /* _QEDE_H_ */ 286