1 /* QLogic qede NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #ifndef _QEDE_H_ 10 #define _QEDE_H_ 11 #include <linux/compiler.h> 12 #include <linux/version.h> 13 #include <linux/workqueue.h> 14 #include <linux/netdevice.h> 15 #include <linux/interrupt.h> 16 #include <linux/bitmap.h> 17 #include <linux/kernel.h> 18 #include <linux/mutex.h> 19 #include <linux/bpf.h> 20 #include <linux/io.h> 21 #include <linux/qed/common_hsi.h> 22 #include <linux/qed/eth_common.h> 23 #include <linux/qed/qed_if.h> 24 #include <linux/qed/qed_chain.h> 25 #include <linux/qed/qed_eth_if.h> 26 27 #define QEDE_MAJOR_VERSION 8 28 #define QEDE_MINOR_VERSION 10 29 #define QEDE_REVISION_VERSION 9 30 #define QEDE_ENGINEERING_VERSION 20 31 #define DRV_MODULE_VERSION __stringify(QEDE_MAJOR_VERSION) "." \ 32 __stringify(QEDE_MINOR_VERSION) "." \ 33 __stringify(QEDE_REVISION_VERSION) "." \ 34 __stringify(QEDE_ENGINEERING_VERSION) 35 36 #define DRV_MODULE_SYM qede 37 38 struct qede_stats { 39 u64 no_buff_discards; 40 u64 packet_too_big_discard; 41 u64 ttl0_discard; 42 u64 rx_ucast_bytes; 43 u64 rx_mcast_bytes; 44 u64 rx_bcast_bytes; 45 u64 rx_ucast_pkts; 46 u64 rx_mcast_pkts; 47 u64 rx_bcast_pkts; 48 u64 mftag_filter_discards; 49 u64 mac_filter_discards; 50 u64 tx_ucast_bytes; 51 u64 tx_mcast_bytes; 52 u64 tx_bcast_bytes; 53 u64 tx_ucast_pkts; 54 u64 tx_mcast_pkts; 55 u64 tx_bcast_pkts; 56 u64 tx_err_drop_pkts; 57 u64 coalesced_pkts; 58 u64 coalesced_events; 59 u64 coalesced_aborts_num; 60 u64 non_coalesced_pkts; 61 u64 coalesced_bytes; 62 63 /* port */ 64 u64 rx_64_byte_packets; 65 u64 rx_65_to_127_byte_packets; 66 u64 rx_128_to_255_byte_packets; 67 u64 rx_256_to_511_byte_packets; 68 u64 rx_512_to_1023_byte_packets; 69 u64 rx_1024_to_1518_byte_packets; 70 u64 rx_1519_to_1522_byte_packets; 71 u64 rx_1519_to_2047_byte_packets; 72 u64 rx_2048_to_4095_byte_packets; 73 u64 rx_4096_to_9216_byte_packets; 74 u64 rx_9217_to_16383_byte_packets; 75 u64 rx_crc_errors; 76 u64 rx_mac_crtl_frames; 77 u64 rx_pause_frames; 78 u64 rx_pfc_frames; 79 u64 rx_align_errors; 80 u64 rx_carrier_errors; 81 u64 rx_oversize_packets; 82 u64 rx_jabbers; 83 u64 rx_undersize_packets; 84 u64 rx_fragments; 85 u64 tx_64_byte_packets; 86 u64 tx_65_to_127_byte_packets; 87 u64 tx_128_to_255_byte_packets; 88 u64 tx_256_to_511_byte_packets; 89 u64 tx_512_to_1023_byte_packets; 90 u64 tx_1024_to_1518_byte_packets; 91 u64 tx_1519_to_2047_byte_packets; 92 u64 tx_2048_to_4095_byte_packets; 93 u64 tx_4096_to_9216_byte_packets; 94 u64 tx_9217_to_16383_byte_packets; 95 u64 tx_pause_frames; 96 u64 tx_pfc_frames; 97 u64 tx_lpi_entry_count; 98 u64 tx_total_collisions; 99 u64 brb_truncates; 100 u64 brb_discards; 101 u64 tx_mac_ctrl_frames; 102 }; 103 104 struct qede_vlan { 105 struct list_head list; 106 u16 vid; 107 bool configured; 108 }; 109 110 struct qede_rdma_dev { 111 struct qedr_dev *qedr_dev; 112 struct list_head entry; 113 struct list_head roce_event_list; 114 struct workqueue_struct *roce_wq; 115 }; 116 117 struct qede_dev { 118 struct qed_dev *cdev; 119 struct net_device *ndev; 120 struct pci_dev *pdev; 121 122 u32 dp_module; 123 u8 dp_level; 124 125 u32 flags; 126 #define QEDE_FLAG_IS_VF BIT(0) 127 #define IS_VF(edev) (!!((edev)->flags & QEDE_FLAG_IS_VF)) 128 129 const struct qed_eth_ops *ops; 130 131 struct qed_dev_eth_info dev_info; 132 #define QEDE_MAX_RSS_CNT(edev) ((edev)->dev_info.num_queues) 133 #define QEDE_MAX_TSS_CNT(edev) ((edev)->dev_info.num_queues) 134 135 struct qede_fastpath *fp_array; 136 u8 req_num_tx; 137 u8 fp_num_tx; 138 u8 req_num_rx; 139 u8 fp_num_rx; 140 u16 req_queues; 141 u16 num_queues; 142 #define QEDE_QUEUE_CNT(edev) ((edev)->num_queues) 143 #define QEDE_RSS_COUNT(edev) ((edev)->num_queues - (edev)->fp_num_tx) 144 #define QEDE_TSS_COUNT(edev) ((edev)->num_queues - (edev)->fp_num_rx) 145 146 struct qed_int_info int_info; 147 unsigned char primary_mac[ETH_ALEN]; 148 149 /* Smaller private varaiant of the RTNL lock */ 150 struct mutex qede_lock; 151 u32 state; /* Protected by qede_lock */ 152 u16 rx_buf_size; 153 u32 rx_copybreak; 154 155 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 156 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8) 157 /* Max supported alignment is 256 (8 shift) 158 * minimal alignment shift 6 is optimal for 57xxx HW performance 159 */ 160 #define QEDE_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT)) 161 /* We assume skb_build() uses sizeof(struct skb_shared_info) bytes 162 * at the end of skb->data, to avoid wasting a full cache line. 163 * This reduces memory use (skb->truesize). 164 */ 165 #define QEDE_FW_RX_ALIGN_END \ 166 max_t(u64, 1UL << QEDE_RX_ALIGN_SHIFT, \ 167 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 168 169 struct qede_stats stats; 170 #define QEDE_RSS_INDIR_INITED BIT(0) 171 #define QEDE_RSS_KEY_INITED BIT(1) 172 #define QEDE_RSS_CAPS_INITED BIT(2) 173 u32 rss_params_inited; /* bit-field to track initialized rss params */ 174 struct qed_update_vport_rss_params rss_params; 175 u16 q_num_rx_buffers; /* Must be a power of two */ 176 u16 q_num_tx_buffers; /* Must be a power of two */ 177 178 bool gro_disable; 179 struct list_head vlan_list; 180 u16 configured_vlans; 181 u16 non_configured_vlans; 182 bool accept_any_vlan; 183 struct delayed_work sp_task; 184 unsigned long sp_flags; 185 u16 vxlan_dst_port; 186 u16 geneve_dst_port; 187 188 bool wol_enabled; 189 190 struct qede_rdma_dev rdma_info; 191 192 struct bpf_prog *xdp_prog; 193 }; 194 195 enum QEDE_STATE { 196 QEDE_STATE_CLOSED, 197 QEDE_STATE_OPEN, 198 }; 199 200 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 201 202 #define MAX_NUM_TC 8 203 #define MAX_NUM_PRI 8 204 205 /* The driver supports the new build_skb() API: 206 * RX ring buffer contains pointer to kmalloc() data only, 207 * skb are built only after the frame was DMA-ed. 208 */ 209 struct sw_rx_data { 210 struct page *data; 211 dma_addr_t mapping; 212 unsigned int page_offset; 213 }; 214 215 enum qede_agg_state { 216 QEDE_AGG_STATE_NONE = 0, 217 QEDE_AGG_STATE_START = 1, 218 QEDE_AGG_STATE_ERROR = 2 219 }; 220 221 struct qede_agg_info { 222 /* rx_buf is a data buffer that can be placed / consumed from rx bd 223 * chain. It has two purposes: We will preallocate the data buffer 224 * for each aggregation when we open the interface and will place this 225 * buffer on the rx-bd-ring when we receive TPA_START. We don't want 226 * to be in a state where allocation fails, as we can't reuse the 227 * consumer buffer in the rx-chain since FW may still be writing to it 228 * (since header needs to be modified for TPA). 229 * The second purpose is to keep a pointer to the bd buffer during 230 * aggregation. 231 */ 232 struct sw_rx_data buffer; 233 dma_addr_t buffer_mapping; 234 235 struct sk_buff *skb; 236 237 /* We need some structs from the start cookie until termination */ 238 u16 vlan_tag; 239 u16 start_cqe_bd_len; 240 u8 start_cqe_placement_offset; 241 242 u8 state; 243 u8 frag_id; 244 245 u8 tunnel_type; 246 }; 247 248 struct qede_rx_queue { 249 __le16 *hw_cons_ptr; 250 void __iomem *hw_rxq_prod_addr; 251 252 /* Required for the allocation of replacement buffers */ 253 struct device *dev; 254 255 struct bpf_prog *xdp_prog; 256 257 u16 sw_rx_cons; 258 u16 sw_rx_prod; 259 260 u16 num_rx_buffers; /* Slowpath */ 261 u8 data_direction; 262 u8 rxq_id; 263 264 u32 rx_buf_size; 265 u32 rx_buf_seg_size; 266 267 u64 rcv_pkts; 268 269 struct sw_rx_data *sw_rx_ring; 270 struct qed_chain rx_bd_ring; 271 struct qed_chain rx_comp_ring ____cacheline_aligned; 272 273 /* GRO */ 274 struct qede_agg_info tpa_info[ETH_TPA_MAX_AGGS_NUM]; 275 276 u64 rx_hw_errors; 277 u64 rx_alloc_errors; 278 u64 rx_ip_frags; 279 280 u64 xdp_no_pass; 281 282 void *handle; 283 }; 284 285 union db_prod { 286 struct eth_db_data data; 287 u32 raw; 288 }; 289 290 struct sw_tx_bd { 291 struct sk_buff *skb; 292 u8 flags; 293 /* Set on the first BD descriptor when there is a split BD */ 294 #define QEDE_TSO_SPLIT_BD BIT(0) 295 }; 296 297 struct qede_tx_queue { 298 u8 is_xdp; 299 bool is_legacy; 300 u16 sw_tx_cons; 301 u16 sw_tx_prod; 302 u16 num_tx_buffers; /* Slowpath only */ 303 304 u64 xmit_pkts; 305 u64 stopped_cnt; 306 307 __le16 *hw_cons_ptr; 308 309 /* Needed for the mapping of packets */ 310 struct device *dev; 311 312 void __iomem *doorbell_addr; 313 union db_prod tx_db; 314 int index; /* Slowpath only */ 315 #define QEDE_TXQ_XDP_TO_IDX(edev, txq) ((txq)->index - \ 316 QEDE_MAX_TSS_CNT(edev)) 317 #define QEDE_TXQ_IDX_TO_XDP(edev, idx) ((idx) + QEDE_MAX_TSS_CNT(edev)) 318 319 /* Regular Tx requires skb + metadata for release purpose, 320 * while XDP requires only the pages themselves. 321 */ 322 union { 323 struct sw_tx_bd *skbs; 324 struct page **pages; 325 } sw_tx_ring; 326 327 struct qed_chain tx_pbl; 328 329 /* Slowpath; Should be kept in end [unless missing padding] */ 330 void *handle; 331 }; 332 333 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr.hi), \ 334 le32_to_cpu((bd)->addr.lo)) 335 #define BD_SET_UNMAP_ADDR_LEN(bd, maddr, len) \ 336 do { \ 337 (bd)->addr.hi = cpu_to_le32(upper_32_bits(maddr)); \ 338 (bd)->addr.lo = cpu_to_le32(lower_32_bits(maddr)); \ 339 (bd)->nbytes = cpu_to_le16(len); \ 340 } while (0) 341 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 342 343 struct qede_fastpath { 344 struct qede_dev *edev; 345 #define QEDE_FASTPATH_TX BIT(0) 346 #define QEDE_FASTPATH_RX BIT(1) 347 #define QEDE_FASTPATH_XDP BIT(2) 348 #define QEDE_FASTPATH_COMBINED (QEDE_FASTPATH_TX | QEDE_FASTPATH_RX) 349 u8 type; 350 u8 id; 351 u8 xdp_xmit; 352 struct napi_struct napi; 353 struct qed_sb_info *sb_info; 354 struct qede_rx_queue *rxq; 355 struct qede_tx_queue *txq; 356 struct qede_tx_queue *xdp_tx; 357 358 #define VEC_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 359 char name[VEC_NAME_SIZE]; 360 }; 361 362 /* Debug print definitions */ 363 #define DP_NAME(edev) ((edev)->ndev->name) 364 365 #define XMIT_PLAIN 0 366 #define XMIT_L4_CSUM BIT(0) 367 #define XMIT_LSO BIT(1) 368 #define XMIT_ENC BIT(2) 369 #define XMIT_ENC_GSO_L4_CSUM BIT(3) 370 371 #define QEDE_CSUM_ERROR BIT(0) 372 #define QEDE_CSUM_UNNECESSARY BIT(1) 373 #define QEDE_TUNN_CSUM_UNNECESSARY BIT(2) 374 375 #define QEDE_SP_RX_MODE 1 376 #define QEDE_SP_VXLAN_PORT_CONFIG 2 377 #define QEDE_SP_GENEVE_PORT_CONFIG 3 378 379 struct qede_reload_args { 380 void (*func)(struct qede_dev *edev, struct qede_reload_args *args); 381 union { 382 netdev_features_t features; 383 struct bpf_prog *new_prog; 384 u16 mtu; 385 } u; 386 }; 387 388 #ifdef CONFIG_DCB 389 void qede_set_dcbnl_ops(struct net_device *ndev); 390 #endif 391 void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level); 392 void qede_set_ethtool_ops(struct net_device *netdev); 393 void qede_reload(struct qede_dev *edev, 394 struct qede_reload_args *args, bool is_locked); 395 int qede_change_mtu(struct net_device *dev, int new_mtu); 396 void qede_fill_by_demand_stats(struct qede_dev *edev); 397 void __qede_lock(struct qede_dev *edev); 398 void __qede_unlock(struct qede_dev *edev); 399 bool qede_has_rx_work(struct qede_rx_queue *rxq); 400 int qede_txq_has_work(struct qede_tx_queue *txq); 401 void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq, u8 count); 402 void qede_update_rx_prod(struct qede_dev *edev, struct qede_rx_queue *rxq); 403 404 #define RX_RING_SIZE_POW 13 405 #define RX_RING_SIZE ((u16)BIT(RX_RING_SIZE_POW)) 406 #define NUM_RX_BDS_MAX (RX_RING_SIZE - 1) 407 #define NUM_RX_BDS_MIN 128 408 #define NUM_RX_BDS_DEF ((u16)BIT(10) - 1) 409 410 #define TX_RING_SIZE_POW 13 411 #define TX_RING_SIZE ((u16)BIT(TX_RING_SIZE_POW)) 412 #define NUM_TX_BDS_MAX (TX_RING_SIZE - 1) 413 #define NUM_TX_BDS_MIN 128 414 #define NUM_TX_BDS_DEF NUM_TX_BDS_MAX 415 416 #define QEDE_MIN_PKT_LEN 64 417 #define QEDE_RX_HDR_SIZE 256 418 #define QEDE_MAX_JUMBO_PACKET_SIZE 9600 419 #define for_each_queue(i) for (i = 0; i < edev->num_queues; i++) 420 421 #endif /* _QEDE_H_ */ 422