1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/types.h> 34 #include <asm/byteorder.h> 35 #include <linux/bitops.h> 36 #include <linux/errno.h> 37 #include <linux/kernel.h> 38 #include <linux/string.h> 39 #include "qed.h" 40 #include <linux/qed/qed_chain.h> 41 #include "qed_cxt.h" 42 #include "qed_dcbx.h" 43 #include "qed_hsi.h" 44 #include "qed_hw.h" 45 #include "qed_int.h" 46 #include "qed_reg_addr.h" 47 #include "qed_sp.h" 48 #include "qed_sriov.h" 49 50 int qed_sp_init_request(struct qed_hwfn *p_hwfn, 51 struct qed_spq_entry **pp_ent, 52 u8 cmd, u8 protocol, struct qed_sp_init_data *p_data) 53 { 54 u32 opaque_cid = p_data->opaque_fid << 16 | p_data->cid; 55 struct qed_spq_entry *p_ent = NULL; 56 int rc; 57 58 if (!pp_ent) 59 return -ENOMEM; 60 61 rc = qed_spq_get_entry(p_hwfn, pp_ent); 62 63 if (rc) 64 return rc; 65 66 p_ent = *pp_ent; 67 68 p_ent->elem.hdr.cid = cpu_to_le32(opaque_cid); 69 p_ent->elem.hdr.cmd_id = cmd; 70 p_ent->elem.hdr.protocol_id = protocol; 71 72 p_ent->priority = QED_SPQ_PRIORITY_NORMAL; 73 p_ent->comp_mode = p_data->comp_mode; 74 p_ent->comp_done.done = 0; 75 76 switch (p_ent->comp_mode) { 77 case QED_SPQ_MODE_EBLOCK: 78 p_ent->comp_cb.cookie = &p_ent->comp_done; 79 break; 80 81 case QED_SPQ_MODE_BLOCK: 82 if (!p_data->p_comp_data) 83 return -EINVAL; 84 85 p_ent->comp_cb.cookie = p_data->p_comp_data->cookie; 86 break; 87 88 case QED_SPQ_MODE_CB: 89 if (!p_data->p_comp_data) 90 p_ent->comp_cb.function = NULL; 91 else 92 p_ent->comp_cb = *p_data->p_comp_data; 93 break; 94 95 default: 96 DP_NOTICE(p_hwfn, "Unknown SPQE completion mode %d\n", 97 p_ent->comp_mode); 98 return -EINVAL; 99 } 100 101 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, 102 "Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n", 103 opaque_cid, cmd, protocol, 104 (unsigned long)&p_ent->ramrod, 105 D_TRINE(p_ent->comp_mode, QED_SPQ_MODE_EBLOCK, 106 QED_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK", 107 "MODE_CB")); 108 109 memset(&p_ent->ramrod, 0, sizeof(p_ent->ramrod)); 110 111 return 0; 112 } 113 114 static enum tunnel_clss qed_tunn_clss_to_fw_clss(u8 type) 115 { 116 switch (type) { 117 case QED_TUNN_CLSS_MAC_VLAN: 118 return TUNNEL_CLSS_MAC_VLAN; 119 case QED_TUNN_CLSS_MAC_VNI: 120 return TUNNEL_CLSS_MAC_VNI; 121 case QED_TUNN_CLSS_INNER_MAC_VLAN: 122 return TUNNEL_CLSS_INNER_MAC_VLAN; 123 case QED_TUNN_CLSS_INNER_MAC_VNI: 124 return TUNNEL_CLSS_INNER_MAC_VNI; 125 case QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE: 126 return TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE; 127 default: 128 return TUNNEL_CLSS_MAC_VLAN; 129 } 130 } 131 132 static void 133 qed_set_pf_update_tunn_mode(struct qed_tunnel_info *p_tun, 134 struct qed_tunnel_info *p_src, bool b_pf_start) 135 { 136 if (p_src->vxlan.b_update_mode || b_pf_start) 137 p_tun->vxlan.b_mode_enabled = p_src->vxlan.b_mode_enabled; 138 139 if (p_src->l2_gre.b_update_mode || b_pf_start) 140 p_tun->l2_gre.b_mode_enabled = p_src->l2_gre.b_mode_enabled; 141 142 if (p_src->ip_gre.b_update_mode || b_pf_start) 143 p_tun->ip_gre.b_mode_enabled = p_src->ip_gre.b_mode_enabled; 144 145 if (p_src->l2_geneve.b_update_mode || b_pf_start) 146 p_tun->l2_geneve.b_mode_enabled = 147 p_src->l2_geneve.b_mode_enabled; 148 149 if (p_src->ip_geneve.b_update_mode || b_pf_start) 150 p_tun->ip_geneve.b_mode_enabled = 151 p_src->ip_geneve.b_mode_enabled; 152 } 153 154 static void qed_set_tunn_cls_info(struct qed_tunnel_info *p_tun, 155 struct qed_tunnel_info *p_src) 156 { 157 enum tunnel_clss type; 158 159 p_tun->b_update_rx_cls = p_src->b_update_rx_cls; 160 p_tun->b_update_tx_cls = p_src->b_update_tx_cls; 161 162 type = qed_tunn_clss_to_fw_clss(p_src->vxlan.tun_cls); 163 p_tun->vxlan.tun_cls = type; 164 type = qed_tunn_clss_to_fw_clss(p_src->l2_gre.tun_cls); 165 p_tun->l2_gre.tun_cls = type; 166 type = qed_tunn_clss_to_fw_clss(p_src->ip_gre.tun_cls); 167 p_tun->ip_gre.tun_cls = type; 168 type = qed_tunn_clss_to_fw_clss(p_src->l2_geneve.tun_cls); 169 p_tun->l2_geneve.tun_cls = type; 170 type = qed_tunn_clss_to_fw_clss(p_src->ip_geneve.tun_cls); 171 p_tun->ip_geneve.tun_cls = type; 172 } 173 174 static void qed_set_tunn_ports(struct qed_tunnel_info *p_tun, 175 struct qed_tunnel_info *p_src) 176 { 177 p_tun->geneve_port.b_update_port = p_src->geneve_port.b_update_port; 178 p_tun->vxlan_port.b_update_port = p_src->vxlan_port.b_update_port; 179 180 if (p_src->geneve_port.b_update_port) 181 p_tun->geneve_port.port = p_src->geneve_port.port; 182 183 if (p_src->vxlan_port.b_update_port) 184 p_tun->vxlan_port.port = p_src->vxlan_port.port; 185 } 186 187 static void 188 __qed_set_ramrod_tunnel_param(u8 *p_tunn_cls, u8 *p_enable_tx_clas, 189 struct qed_tunn_update_type *tun_type) 190 { 191 *p_tunn_cls = tun_type->tun_cls; 192 193 if (tun_type->b_mode_enabled) 194 *p_enable_tx_clas = 1; 195 } 196 197 static void 198 qed_set_ramrod_tunnel_param(u8 *p_tunn_cls, u8 *p_enable_tx_clas, 199 struct qed_tunn_update_type *tun_type, 200 u8 *p_update_port, __le16 *p_port, 201 struct qed_tunn_update_udp_port *p_udp_port) 202 { 203 __qed_set_ramrod_tunnel_param(p_tunn_cls, p_enable_tx_clas, tun_type); 204 if (p_udp_port->b_update_port) { 205 *p_update_port = 1; 206 *p_port = cpu_to_le16(p_udp_port->port); 207 } 208 } 209 210 static void 211 qed_tunn_set_pf_update_params(struct qed_hwfn *p_hwfn, 212 struct qed_tunnel_info *p_src, 213 struct pf_update_tunnel_config *p_tunn_cfg) 214 { 215 struct qed_tunnel_info *p_tun = &p_hwfn->cdev->tunnel; 216 217 qed_set_pf_update_tunn_mode(p_tun, p_src, false); 218 qed_set_tunn_cls_info(p_tun, p_src); 219 qed_set_tunn_ports(p_tun, p_src); 220 221 qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan, 222 &p_tunn_cfg->tx_enable_vxlan, 223 &p_tun->vxlan, 224 &p_tunn_cfg->set_vxlan_udp_port_flg, 225 &p_tunn_cfg->vxlan_udp_port, 226 &p_tun->vxlan_port); 227 228 qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve, 229 &p_tunn_cfg->tx_enable_l2geneve, 230 &p_tun->l2_geneve, 231 &p_tunn_cfg->set_geneve_udp_port_flg, 232 &p_tunn_cfg->geneve_udp_port, 233 &p_tun->geneve_port); 234 235 __qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve, 236 &p_tunn_cfg->tx_enable_ipgeneve, 237 &p_tun->ip_geneve); 238 239 __qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre, 240 &p_tunn_cfg->tx_enable_l2gre, 241 &p_tun->l2_gre); 242 243 __qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre, 244 &p_tunn_cfg->tx_enable_ipgre, 245 &p_tun->ip_gre); 246 247 p_tunn_cfg->update_rx_pf_clss = p_tun->b_update_rx_cls; 248 p_tunn_cfg->update_tx_pf_clss = p_tun->b_update_tx_cls; 249 } 250 251 static void qed_set_hw_tunn_mode(struct qed_hwfn *p_hwfn, 252 struct qed_ptt *p_ptt, 253 struct qed_tunnel_info *p_tun) 254 { 255 qed_set_gre_enable(p_hwfn, p_ptt, p_tun->l2_gre.b_mode_enabled, 256 p_tun->ip_gre.b_mode_enabled); 257 qed_set_vxlan_enable(p_hwfn, p_ptt, p_tun->vxlan.b_mode_enabled); 258 259 qed_set_geneve_enable(p_hwfn, p_ptt, p_tun->l2_geneve.b_mode_enabled, 260 p_tun->ip_geneve.b_mode_enabled); 261 } 262 263 static void qed_set_hw_tunn_mode_port(struct qed_hwfn *p_hwfn, 264 struct qed_tunnel_info *p_tunn) 265 { 266 if (p_tunn->vxlan_port.b_update_port) 267 qed_set_vxlan_dest_port(p_hwfn, p_hwfn->p_main_ptt, 268 p_tunn->vxlan_port.port); 269 270 if (p_tunn->geneve_port.b_update_port) 271 qed_set_geneve_dest_port(p_hwfn, p_hwfn->p_main_ptt, 272 p_tunn->geneve_port.port); 273 274 qed_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt, p_tunn); 275 } 276 277 static void 278 qed_tunn_set_pf_start_params(struct qed_hwfn *p_hwfn, 279 struct qed_tunnel_info *p_src, 280 struct pf_start_tunnel_config *p_tunn_cfg) 281 { 282 struct qed_tunnel_info *p_tun = &p_hwfn->cdev->tunnel; 283 284 if (!p_src) 285 return; 286 287 qed_set_pf_update_tunn_mode(p_tun, p_src, true); 288 qed_set_tunn_cls_info(p_tun, p_src); 289 qed_set_tunn_ports(p_tun, p_src); 290 291 qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan, 292 &p_tunn_cfg->tx_enable_vxlan, 293 &p_tun->vxlan, 294 &p_tunn_cfg->set_vxlan_udp_port_flg, 295 &p_tunn_cfg->vxlan_udp_port, 296 &p_tun->vxlan_port); 297 298 qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve, 299 &p_tunn_cfg->tx_enable_l2geneve, 300 &p_tun->l2_geneve, 301 &p_tunn_cfg->set_geneve_udp_port_flg, 302 &p_tunn_cfg->geneve_udp_port, 303 &p_tun->geneve_port); 304 305 __qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve, 306 &p_tunn_cfg->tx_enable_ipgeneve, 307 &p_tun->ip_geneve); 308 309 __qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre, 310 &p_tunn_cfg->tx_enable_l2gre, 311 &p_tun->l2_gre); 312 313 __qed_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre, 314 &p_tunn_cfg->tx_enable_ipgre, 315 &p_tun->ip_gre); 316 } 317 318 int qed_sp_pf_start(struct qed_hwfn *p_hwfn, 319 struct qed_tunnel_info *p_tunn, 320 enum qed_mf_mode mode, bool allow_npar_tx_switch) 321 { 322 struct pf_start_ramrod_data *p_ramrod = NULL; 323 u16 sb = qed_int_get_sp_sb_id(p_hwfn); 324 u8 sb_index = p_hwfn->p_eq->eq_sb_index; 325 struct qed_spq_entry *p_ent = NULL; 326 struct qed_sp_init_data init_data; 327 int rc = -EINVAL; 328 u8 page_cnt; 329 330 /* update initial eq producer */ 331 qed_eq_prod_update(p_hwfn, 332 qed_chain_get_prod_idx(&p_hwfn->p_eq->chain)); 333 334 memset(&init_data, 0, sizeof(init_data)); 335 init_data.cid = qed_spq_get_cid(p_hwfn); 336 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 337 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 338 339 rc = qed_sp_init_request(p_hwfn, &p_ent, 340 COMMON_RAMROD_PF_START, 341 PROTOCOLID_COMMON, &init_data); 342 if (rc) 343 return rc; 344 345 p_ramrod = &p_ent->ramrod.pf_start; 346 347 p_ramrod->event_ring_sb_id = cpu_to_le16(sb); 348 p_ramrod->event_ring_sb_index = sb_index; 349 p_ramrod->path_id = QED_PATH_ID(p_hwfn); 350 p_ramrod->dont_log_ramrods = 0; 351 p_ramrod->log_type_mask = cpu_to_le16(0xf); 352 353 switch (mode) { 354 case QED_MF_DEFAULT: 355 case QED_MF_NPAR: 356 p_ramrod->mf_mode = MF_NPAR; 357 break; 358 case QED_MF_OVLAN: 359 p_ramrod->mf_mode = MF_OVLAN; 360 break; 361 default: 362 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n"); 363 p_ramrod->mf_mode = MF_NPAR; 364 } 365 p_ramrod->outer_tag = p_hwfn->hw_info.ovlan; 366 367 /* Place EQ address in RAMROD */ 368 DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr, 369 p_hwfn->p_eq->chain.pbl_sp.p_phys_table); 370 page_cnt = (u8)qed_chain_get_page_cnt(&p_hwfn->p_eq->chain); 371 p_ramrod->event_ring_num_pages = page_cnt; 372 DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr, 373 p_hwfn->p_consq->chain.pbl_sp.p_phys_table); 374 375 qed_tunn_set_pf_start_params(p_hwfn, p_tunn, &p_ramrod->tunnel_config); 376 377 if (IS_MF_SI(p_hwfn)) 378 p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch; 379 380 switch (p_hwfn->hw_info.personality) { 381 case QED_PCI_ETH: 382 p_ramrod->personality = PERSONALITY_ETH; 383 break; 384 case QED_PCI_FCOE: 385 p_ramrod->personality = PERSONALITY_FCOE; 386 break; 387 case QED_PCI_ISCSI: 388 p_ramrod->personality = PERSONALITY_ISCSI; 389 break; 390 case QED_PCI_ETH_ROCE: 391 p_ramrod->personality = PERSONALITY_RDMA_AND_ETH; 392 break; 393 default: 394 DP_NOTICE(p_hwfn, "Unknown personality %d\n", 395 p_hwfn->hw_info.personality); 396 p_ramrod->personality = PERSONALITY_ETH; 397 } 398 399 if (p_hwfn->cdev->p_iov_info) { 400 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 401 402 p_ramrod->base_vf_id = (u8) p_iov->first_vf_in_pf; 403 p_ramrod->num_vfs = (u8) p_iov->total_vfs; 404 } 405 p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR; 406 p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR; 407 408 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, 409 "Setting event_ring_sb [id %04x index %02x], outer_tag [%d]\n", 410 sb, sb_index, p_ramrod->outer_tag); 411 412 rc = qed_spq_post(p_hwfn, p_ent, NULL); 413 414 if (p_tunn) 415 qed_set_hw_tunn_mode_port(p_hwfn, &p_hwfn->cdev->tunnel); 416 417 return rc; 418 } 419 420 int qed_sp_pf_update(struct qed_hwfn *p_hwfn) 421 { 422 struct qed_spq_entry *p_ent = NULL; 423 struct qed_sp_init_data init_data; 424 int rc = -EINVAL; 425 426 /* Get SPQ entry */ 427 memset(&init_data, 0, sizeof(init_data)); 428 init_data.cid = qed_spq_get_cid(p_hwfn); 429 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 430 init_data.comp_mode = QED_SPQ_MODE_CB; 431 432 rc = qed_sp_init_request(p_hwfn, &p_ent, 433 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON, 434 &init_data); 435 if (rc) 436 return rc; 437 438 qed_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results, 439 &p_ent->ramrod.pf_update); 440 441 return qed_spq_post(p_hwfn, p_ent, NULL); 442 } 443 444 /* Set pf update ramrod command params */ 445 int qed_sp_pf_update_tunn_cfg(struct qed_hwfn *p_hwfn, 446 struct qed_tunnel_info *p_tunn, 447 enum spq_mode comp_mode, 448 struct qed_spq_comp_cb *p_comp_data) 449 { 450 struct qed_spq_entry *p_ent = NULL; 451 struct qed_sp_init_data init_data; 452 int rc = -EINVAL; 453 454 if (IS_VF(p_hwfn->cdev)) 455 return qed_vf_pf_tunnel_param_update(p_hwfn, p_tunn); 456 457 if (!p_tunn) 458 return -EINVAL; 459 460 /* Get SPQ entry */ 461 memset(&init_data, 0, sizeof(init_data)); 462 init_data.cid = qed_spq_get_cid(p_hwfn); 463 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 464 init_data.comp_mode = comp_mode; 465 init_data.p_comp_data = p_comp_data; 466 467 rc = qed_sp_init_request(p_hwfn, &p_ent, 468 COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON, 469 &init_data); 470 if (rc) 471 return rc; 472 473 qed_tunn_set_pf_update_params(p_hwfn, p_tunn, 474 &p_ent->ramrod.pf_update.tunnel_config); 475 476 rc = qed_spq_post(p_hwfn, p_ent, NULL); 477 if (rc) 478 return rc; 479 480 qed_set_hw_tunn_mode_port(p_hwfn, &p_hwfn->cdev->tunnel); 481 482 return rc; 483 } 484 485 int qed_sp_pf_stop(struct qed_hwfn *p_hwfn) 486 { 487 struct qed_spq_entry *p_ent = NULL; 488 struct qed_sp_init_data init_data; 489 int rc = -EINVAL; 490 491 /* Get SPQ entry */ 492 memset(&init_data, 0, sizeof(init_data)); 493 init_data.cid = qed_spq_get_cid(p_hwfn); 494 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 495 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 496 497 rc = qed_sp_init_request(p_hwfn, &p_ent, 498 COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON, 499 &init_data); 500 if (rc) 501 return rc; 502 503 return qed_spq_post(p_hwfn, p_ent, NULL); 504 } 505 506 int qed_sp_heartbeat_ramrod(struct qed_hwfn *p_hwfn) 507 { 508 struct qed_spq_entry *p_ent = NULL; 509 struct qed_sp_init_data init_data; 510 int rc; 511 512 /* Get SPQ entry */ 513 memset(&init_data, 0, sizeof(init_data)); 514 init_data.cid = qed_spq_get_cid(p_hwfn); 515 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 516 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 517 518 rc = qed_sp_init_request(p_hwfn, &p_ent, 519 COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON, 520 &init_data); 521 if (rc) 522 return rc; 523 524 return qed_spq_post(p_hwfn, p_ent, NULL); 525 } 526