1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef REG_ADDR_H 34 #define REG_ADDR_H 35 36 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \ 37 0 38 39 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \ 40 0xfff << 0) 41 42 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \ 43 12 44 45 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \ 46 0xfff << 12) 47 48 #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \ 49 24 50 51 #define CDU_REG_CID_ADDR_PARAMS_NCIB ( \ 52 0xff << 24) 53 54 #define CDU_REG_SEGMENT0_PARAMS \ 55 0x580904UL 56 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK \ 57 (0xfff << 0) 58 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT \ 59 0 60 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE \ 61 (0xff << 16) 62 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT \ 63 16 64 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE \ 65 (0xff << 24) 66 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT \ 67 24 68 #define CDU_REG_SEGMENT1_PARAMS \ 69 0x580908UL 70 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK \ 71 (0xfff << 0) 72 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT \ 73 0 74 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE \ 75 (0xff << 16) 76 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT \ 77 16 78 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE \ 79 (0xff << 24) 80 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT \ 81 24 82 83 #define XSDM_REG_OPERATION_GEN \ 84 0xf80408UL 85 #define NIG_REG_RX_BRB_OUT_EN \ 86 0x500e18UL 87 #define NIG_REG_STORM_OUT_EN \ 88 0x500e08UL 89 #define PSWRQ2_REG_L2P_VALIDATE_VFID \ 90 0x240c50UL 91 #define PGLUE_B_REG_USE_CLIENTID_IN_TAG \ 92 0x2aae04UL 93 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \ 94 0x2aa16cUL 95 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \ 96 0x2aa118UL 97 #define PSWHST_REG_ZONE_PERMISSION_TABLE \ 98 0x2a0800UL 99 #define BAR0_MAP_REG_MSDM_RAM \ 100 0x1d00000UL 101 #define BAR0_MAP_REG_USDM_RAM \ 102 0x1d80000UL 103 #define BAR0_MAP_REG_PSDM_RAM \ 104 0x1f00000UL 105 #define BAR0_MAP_REG_TSDM_RAM \ 106 0x1c80000UL 107 #define BAR0_MAP_REG_XSDM_RAM \ 108 0x1e00000UL 109 #define BAR0_MAP_REG_YSDM_RAM \ 110 0x1e80000UL 111 #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \ 112 0x5011f4UL 113 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE \ 114 0x1f0164UL 115 #define PRS_REG_SEARCH_TCP \ 116 0x1f0400UL 117 #define PRS_REG_SEARCH_UDP \ 118 0x1f0404UL 119 #define PRS_REG_SEARCH_FCOE \ 120 0x1f0408UL 121 #define PRS_REG_SEARCH_ROCE \ 122 0x1f040cUL 123 #define PRS_REG_SEARCH_OPENFLOW \ 124 0x1f0434UL 125 #define PRS_REG_SEARCH_TAG1 \ 126 0x1f0444UL 127 #define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST \ 128 0x1f0a0cUL 129 #define PRS_REG_SEARCH_TCP_FIRST_FRAG \ 130 0x1f0410UL 131 #define TM_REG_PF_ENABLE_CONN \ 132 0x2c043cUL 133 #define TM_REG_PF_ENABLE_TASK \ 134 0x2c0444UL 135 #define TM_REG_PF_SCAN_ACTIVE_CONN \ 136 0x2c04fcUL 137 #define TM_REG_PF_SCAN_ACTIVE_TASK \ 138 0x2c0500UL 139 #define IGU_REG_LEADING_EDGE_LATCH \ 140 0x18082cUL 141 #define IGU_REG_TRAILING_EDGE_LATCH \ 142 0x180830UL 143 #define QM_REG_USG_CNT_PF_TX \ 144 0x2f2eacUL 145 #define QM_REG_USG_CNT_PF_OTHER \ 146 0x2f2eb0UL 147 #define DORQ_REG_PF_DB_ENABLE \ 148 0x100508UL 149 #define DORQ_REG_VF_USAGE_CNT \ 150 0x1009c4UL 151 #define QM_REG_PF_EN \ 152 0x2f2ea4UL 153 #define TCFC_REG_WEAK_ENABLE_VF \ 154 0x2d0704UL 155 #define TCFC_REG_STRONG_ENABLE_PF \ 156 0x2d0708UL 157 #define TCFC_REG_STRONG_ENABLE_VF \ 158 0x2d070cUL 159 #define CCFC_REG_WEAK_ENABLE_VF \ 160 0x2e0704UL 161 #define CCFC_REG_STRONG_ENABLE_PF \ 162 0x2e0708UL 163 #define PGLUE_B_REG_PGL_ADDR_88_F0 \ 164 0x2aa404UL 165 #define PGLUE_B_REG_PGL_ADDR_8C_F0 \ 166 0x2aa408UL 167 #define PGLUE_B_REG_PGL_ADDR_90_F0 \ 168 0x2aa40cUL 169 #define PGLUE_B_REG_PGL_ADDR_94_F0 \ 170 0x2aa410UL 171 #define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \ 172 0x2aa138UL 173 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \ 174 0x2aa174UL 175 #define MISC_REG_GEN_PURP_CR0 \ 176 0x008c80UL 177 #define MCP_REG_SCRATCH \ 178 0xe20000UL 179 #define CNIG_REG_NW_PORT_MODE_BB_B0 \ 180 0x218200UL 181 #define MISCS_REG_CHIP_NUM \ 182 0x00976cUL 183 #define MISCS_REG_CHIP_REV \ 184 0x009770UL 185 #define MISCS_REG_CMT_ENABLED_FOR_PAIR \ 186 0x00971cUL 187 #define MISCS_REG_CHIP_TEST_REG \ 188 0x009778UL 189 #define MISCS_REG_CHIP_METAL \ 190 0x009774UL 191 #define MISCS_REG_FUNCTION_HIDE \ 192 0x0096f0UL 193 #define BRB_REG_HEADER_SIZE \ 194 0x340804UL 195 #define BTB_REG_HEADER_SIZE \ 196 0xdb0804UL 197 #define CAU_REG_LONG_TIMEOUT_THRESHOLD \ 198 0x1c0708UL 199 #define CCFC_REG_ACTIVITY_COUNTER \ 200 0x2e8800UL 201 #define CCFC_REG_STRONG_ENABLE_VF \ 202 0x2e070cUL 203 #define CDU_REG_CID_ADDR_PARAMS \ 204 0x580900UL 205 #define DBG_REG_CLIENT_ENABLE \ 206 0x010004UL 207 #define DMAE_REG_INIT \ 208 0x00c000UL 209 #define DORQ_REG_IFEN \ 210 0x100040UL 211 #define DORQ_REG_DB_DROP_REASON \ 212 0x100a2cUL 213 #define DORQ_REG_DB_DROP_DETAILS \ 214 0x100a24UL 215 #define DORQ_REG_DB_DROP_DETAILS_ADDRESS \ 216 0x100a1cUL 217 #define GRC_REG_TIMEOUT_EN \ 218 0x050404UL 219 #define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \ 220 0x050054UL 221 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \ 222 0x05004cUL 223 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \ 224 0x050050UL 225 #define IGU_REG_BLOCK_CONFIGURATION \ 226 0x180040UL 227 #define MCM_REG_INIT \ 228 0x1200000UL 229 #define MCP2_REG_DBG_DWORD_ENABLE \ 230 0x052404UL 231 #define MISC_REG_PORT_MODE \ 232 0x008c00UL 233 #define MISCS_REG_CLK_100G_MODE \ 234 0x009070UL 235 #define MSDM_REG_ENABLE_IN1 \ 236 0xfc0004UL 237 #define MSEM_REG_ENABLE_IN \ 238 0x1800004UL 239 #define NIG_REG_CM_HDR \ 240 0x500840UL 241 #define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR \ 242 0x50196cUL 243 #define NIG_REG_LLH_CLS_TYPE_DUALMODE \ 244 0x501964UL 245 #define NIG_REG_LLH_FUNC_FILTER_VALUE \ 246 0x501a00UL 247 #define NIG_REG_LLH_FUNC_FILTER_VALUE_SIZE \ 248 32 249 #define NIG_REG_LLH_FUNC_FILTER_EN \ 250 0x501a80UL 251 #define NIG_REG_LLH_FUNC_FILTER_EN_SIZE \ 252 16 253 #define NIG_REG_LLH_FUNC_FILTER_MODE \ 254 0x501ac0UL 255 #define NIG_REG_LLH_FUNC_FILTER_MODE_SIZE \ 256 16 257 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE \ 258 0x501b00UL 259 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_SIZE \ 260 16 261 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL \ 262 0x501b40UL 263 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_SIZE \ 264 16 265 #define NCSI_REG_CONFIG \ 266 0x040200UL 267 #define PBF_REG_INIT \ 268 0xd80000UL 269 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 \ 270 0xd806c8UL 271 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 \ 272 0xd806ccUL 273 #define PTU_REG_ATC_INIT_ARRAY \ 274 0x560000UL 275 #define PCM_REG_INIT \ 276 0x1100000UL 277 #define PGLUE_B_REG_ADMIN_PER_PF_REGION \ 278 0x2a9000UL 279 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \ 280 0x2aa150UL 281 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \ 282 0x2aa144UL 283 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \ 284 0x2aa148UL 285 #define PGLUE_B_REG_TX_ERR_WR_DETAILS \ 286 0x2aa14cUL 287 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \ 288 0x2aa154UL 289 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \ 290 0x2aa158UL 291 #define PGLUE_B_REG_TX_ERR_RD_DETAILS \ 292 0x2aa15cUL 293 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \ 294 0x2aa160UL 295 #define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \ 296 0x2aa164UL 297 #define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \ 298 0x2aa54cUL 299 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \ 300 0x2aa544UL 301 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \ 302 0x2aa548UL 303 #define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \ 304 0x2aae74UL 305 #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \ 306 0x2aae78UL 307 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS \ 308 0x2aae7cUL 309 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \ 310 0x2aae80UL 311 #define PGLUE_B_REG_LATCHED_ERRORS_CLR \ 312 0x2aa3bcUL 313 #define PRM_REG_DISABLE_PRM \ 314 0x230000UL 315 #define PRS_REG_SOFT_RST \ 316 0x1f0000UL 317 #define PRS_REG_MSG_INFO \ 318 0x1f0a1cUL 319 #define PRS_REG_ROCE_DEST_QP_MAX_PF \ 320 0x1f0430UL 321 #define PRS_REG_USE_LIGHT_L2 \ 322 0x1f096cUL 323 #define PSDM_REG_ENABLE_IN1 \ 324 0xfa0004UL 325 #define PSEM_REG_ENABLE_IN \ 326 0x1600004UL 327 #define PSWRQ_REG_DBG_SELECT \ 328 0x280020UL 329 #define PSWRQ2_REG_CDUT_P_SIZE \ 330 0x24000cUL 331 #define PSWRQ2_REG_ILT_MEMORY \ 332 0x260000UL 333 #define PSWHST_REG_DISCARD_INTERNAL_WRITES \ 334 0x2a0040UL 335 #define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \ 336 0x29e050UL 337 #define PSWHST_REG_INCORRECT_ACCESS_VALID \ 338 0x2a0070UL 339 #define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \ 340 0x2a0074UL 341 #define PSWHST_REG_INCORRECT_ACCESS_DATA \ 342 0x2a0068UL 343 #define PSWHST_REG_INCORRECT_ACCESS_LENGTH \ 344 0x2a006cUL 345 #define PSWRD_REG_DBG_SELECT \ 346 0x29c040UL 347 #define PSWRD2_REG_CONF11 \ 348 0x29d064UL 349 #define PSWWR_REG_USDM_FULL_TH \ 350 0x29a040UL 351 #define PSWWR2_REG_CDU_FULL_TH2 \ 352 0x29b040UL 353 #define QM_REG_MAXPQSIZE_0 \ 354 0x2f0434UL 355 #define RSS_REG_RSS_INIT_EN \ 356 0x238804UL 357 #define RDIF_REG_STOP_ON_ERROR \ 358 0x300040UL 359 #define SRC_REG_SOFT_RST \ 360 0x23874cUL 361 #define TCFC_REG_ACTIVITY_COUNTER \ 362 0x2d8800UL 363 #define TCM_REG_INIT \ 364 0x1180000UL 365 #define TM_REG_PXP_READ_DATA_FIFO_INIT \ 366 0x2c0014UL 367 #define TSDM_REG_ENABLE_IN1 \ 368 0xfb0004UL 369 #define TSEM_REG_ENABLE_IN \ 370 0x1700004UL 371 #define TDIF_REG_STOP_ON_ERROR \ 372 0x310040UL 373 #define UCM_REG_INIT \ 374 0x1280000UL 375 #define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \ 376 0x051004UL 377 #define USDM_REG_ENABLE_IN1 \ 378 0xfd0004UL 379 #define USEM_REG_ENABLE_IN \ 380 0x1900004UL 381 #define XCM_REG_INIT \ 382 0x1000000UL 383 #define XSDM_REG_ENABLE_IN1 \ 384 0xf80004UL 385 #define XSEM_REG_ENABLE_IN \ 386 0x1400004UL 387 #define YCM_REG_INIT \ 388 0x1080000UL 389 #define YSDM_REG_ENABLE_IN1 \ 390 0xf90004UL 391 #define YSEM_REG_ENABLE_IN \ 392 0x1500004UL 393 #define XYLD_REG_SCBD_STRICT_PRIO \ 394 0x4c0000UL 395 #define TMLD_REG_SCBD_STRICT_PRIO \ 396 0x4d0000UL 397 #define MULD_REG_SCBD_STRICT_PRIO \ 398 0x4e0000UL 399 #define YULD_REG_SCBD_STRICT_PRIO \ 400 0x4c8000UL 401 #define MISC_REG_SHARED_MEM_ADDR \ 402 0x008c20UL 403 #define DMAE_REG_GO_C0 \ 404 0x00c048UL 405 #define DMAE_REG_GO_C1 \ 406 0x00c04cUL 407 #define DMAE_REG_GO_C2 \ 408 0x00c050UL 409 #define DMAE_REG_GO_C3 \ 410 0x00c054UL 411 #define DMAE_REG_GO_C4 \ 412 0x00c058UL 413 #define DMAE_REG_GO_C5 \ 414 0x00c05cUL 415 #define DMAE_REG_GO_C6 \ 416 0x00c060UL 417 #define DMAE_REG_GO_C7 \ 418 0x00c064UL 419 #define DMAE_REG_GO_C8 \ 420 0x00c068UL 421 #define DMAE_REG_GO_C9 \ 422 0x00c06cUL 423 #define DMAE_REG_GO_C10 \ 424 0x00c070UL 425 #define DMAE_REG_GO_C11 \ 426 0x00c074UL 427 #define DMAE_REG_GO_C12 \ 428 0x00c078UL 429 #define DMAE_REG_GO_C13 \ 430 0x00c07cUL 431 #define DMAE_REG_GO_C14 \ 432 0x00c080UL 433 #define DMAE_REG_GO_C15 \ 434 0x00c084UL 435 #define DMAE_REG_GO_C16 \ 436 0x00c088UL 437 #define DMAE_REG_GO_C17 \ 438 0x00c08cUL 439 #define DMAE_REG_GO_C18 \ 440 0x00c090UL 441 #define DMAE_REG_GO_C19 \ 442 0x00c094UL 443 #define DMAE_REG_GO_C20 \ 444 0x00c098UL 445 #define DMAE_REG_GO_C21 \ 446 0x00c09cUL 447 #define DMAE_REG_GO_C22 \ 448 0x00c0a0UL 449 #define DMAE_REG_GO_C23 \ 450 0x00c0a4UL 451 #define DMAE_REG_GO_C24 \ 452 0x00c0a8UL 453 #define DMAE_REG_GO_C25 \ 454 0x00c0acUL 455 #define DMAE_REG_GO_C26 \ 456 0x00c0b0UL 457 #define DMAE_REG_GO_C27 \ 458 0x00c0b4UL 459 #define DMAE_REG_GO_C28 \ 460 0x00c0b8UL 461 #define DMAE_REG_GO_C29 \ 462 0x00c0bcUL 463 #define DMAE_REG_GO_C30 \ 464 0x00c0c0UL 465 #define DMAE_REG_GO_C31 \ 466 0x00c0c4UL 467 #define DMAE_REG_CMD_MEM \ 468 0x00c800UL 469 #define QM_REG_MAXPQSIZETXSEL_0 \ 470 0x2f0440UL 471 #define QM_REG_SDMCMDREADY \ 472 0x2f1e10UL 473 #define QM_REG_SDMCMDADDR \ 474 0x2f1e04UL 475 #define QM_REG_SDMCMDDATALSB \ 476 0x2f1e08UL 477 #define QM_REG_SDMCMDDATAMSB \ 478 0x2f1e0cUL 479 #define QM_REG_SDMCMDGO \ 480 0x2f1e14UL 481 #define QM_REG_RLPFCRD \ 482 0x2f4d80UL 483 #define QM_REG_RLPFINCVAL \ 484 0x2f4c80UL 485 #define QM_REG_RLGLBLCRD \ 486 0x2f4400UL 487 #define QM_REG_RLGLBLINCVAL \ 488 0x2f3400UL 489 #define IGU_REG_ATTENTION_ENABLE \ 490 0x18083cUL 491 #define IGU_REG_ATTN_MSG_ADDR_L \ 492 0x180820UL 493 #define IGU_REG_ATTN_MSG_ADDR_H \ 494 0x180824UL 495 #define MISC_REG_AEU_GENERAL_ATTN_0 \ 496 0x008400UL 497 #define CAU_REG_SB_ADDR_MEMORY \ 498 0x1c8000UL 499 #define CAU_REG_SB_VAR_MEMORY \ 500 0x1c6000UL 501 #define CAU_REG_PI_MEMORY \ 502 0x1d0000UL 503 #define IGU_REG_PF_CONFIGURATION \ 504 0x180800UL 505 #define IGU_REG_VF_CONFIGURATION \ 506 0x180804UL 507 #define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \ 508 0x00849cUL 509 #define MISC_REG_AEU_AFTER_INVERT_1_IGU \ 510 0x0087b4UL 511 #define MISC_REG_AEU_MASK_ATTN_IGU \ 512 0x008494UL 513 #define IGU_REG_CLEANUP_STATUS_0 \ 514 0x180980UL 515 #define IGU_REG_CLEANUP_STATUS_1 \ 516 0x180a00UL 517 #define IGU_REG_CLEANUP_STATUS_2 \ 518 0x180a80UL 519 #define IGU_REG_CLEANUP_STATUS_3 \ 520 0x180b00UL 521 #define IGU_REG_CLEANUP_STATUS_4 \ 522 0x180b80UL 523 #define IGU_REG_COMMAND_REG_32LSB_DATA \ 524 0x180840UL 525 #define IGU_REG_COMMAND_REG_CTRL \ 526 0x180848UL 527 #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \ 528 0x1 << 1) 529 #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \ 530 0x1 << 0) 531 #define IGU_REG_MAPPING_MEMORY \ 532 0x184000UL 533 #define IGU_REG_STATISTIC_NUM_VF_MSG_SENT \ 534 0x180408UL 535 #define IGU_REG_WRITE_DONE_PENDING \ 536 0x180900UL 537 #define MISCS_REG_GENERIC_POR_0 \ 538 0x0096d4UL 539 #define MCP_REG_NVM_CFG4 \ 540 0xe0642cUL 541 #define MCP_REG_NVM_CFG4_FLASH_SIZE ( \ 542 0x7 << 0) 543 #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \ 544 0 545 #define MCP_REG_CPU_STATE \ 546 0xe05004UL 547 #define MCP_REG_CPU_EVENT_MASK \ 548 0xe05008UL 549 #define PGLUE_B_REG_PF_BAR0_SIZE \ 550 0x2aae60UL 551 #define PGLUE_B_REG_PF_BAR1_SIZE \ 552 0x2aae64UL 553 #define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL 554 #define PRS_REG_GRE_PROTOCOL 0x1f0734UL 555 #define PRS_REG_VXLAN_PORT 0x1f0738UL 556 #define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL 557 #define NIG_REG_ENC_TYPE_ENABLE 0x501058UL 558 559 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0) 560 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0 561 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE (0x1 << 1) 562 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1 563 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE (0x1 << 2) 564 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2 565 566 #define NIG_REG_VXLAN_CTRL 0x50105cUL 567 #define PBF_REG_VXLAN_PORT 0xd80518UL 568 #define PBF_REG_NGE_PORT 0xd8051cUL 569 #define PRS_REG_NGE_PORT 0x1f086cUL 570 #define NIG_REG_NGE_PORT 0x508b38UL 571 572 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL 573 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL 574 #define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL 575 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN 0x10092cUL 576 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN 0x100930UL 577 578 #define NIG_REG_NGE_IP_ENABLE 0x508b28UL 579 #define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL 580 #define NIG_REG_NGE_COMP_VER 0x508b30UL 581 #define PBF_REG_NGE_COMP_VER 0xd80524UL 582 #define PRS_REG_NGE_COMP_VER 0x1f0878UL 583 584 #define QM_REG_WFQPFWEIGHT 0x2f4e80UL 585 #define QM_REG_WFQVPWEIGHT 0x2fa000UL 586 587 #define PGLCS_REG_DBG_SELECT \ 588 0x001d14UL 589 #define PGLCS_REG_DBG_DWORD_ENABLE \ 590 0x001d18UL 591 #define PGLCS_REG_DBG_SHIFT \ 592 0x001d1cUL 593 #define PGLCS_REG_DBG_FORCE_VALID \ 594 0x001d20UL 595 #define PGLCS_REG_DBG_FORCE_FRAME \ 596 0x001d24UL 597 #define MISC_REG_RESET_PL_PDA_VMAIN_1 \ 598 0x008070UL 599 #define MISC_REG_RESET_PL_PDA_VMAIN_2 \ 600 0x008080UL 601 #define MISC_REG_RESET_PL_PDA_VAUX \ 602 0x008090UL 603 #define MISCS_REG_RESET_PL_UA \ 604 0x009050UL 605 #define MISCS_REG_RESET_PL_HV \ 606 0x009060UL 607 #define MISCS_REG_RESET_PL_HV_2 \ 608 0x009150UL 609 #define DMAE_REG_DBG_SELECT \ 610 0x00c510UL 611 #define DMAE_REG_DBG_DWORD_ENABLE \ 612 0x00c514UL 613 #define DMAE_REG_DBG_SHIFT \ 614 0x00c518UL 615 #define DMAE_REG_DBG_FORCE_VALID \ 616 0x00c51cUL 617 #define DMAE_REG_DBG_FORCE_FRAME \ 618 0x00c520UL 619 #define NCSI_REG_DBG_SELECT \ 620 0x040474UL 621 #define NCSI_REG_DBG_DWORD_ENABLE \ 622 0x040478UL 623 #define NCSI_REG_DBG_SHIFT \ 624 0x04047cUL 625 #define NCSI_REG_DBG_FORCE_VALID \ 626 0x040480UL 627 #define NCSI_REG_DBG_FORCE_FRAME \ 628 0x040484UL 629 #define GRC_REG_DBG_SELECT \ 630 0x0500a4UL 631 #define GRC_REG_DBG_DWORD_ENABLE \ 632 0x0500a8UL 633 #define GRC_REG_DBG_SHIFT \ 634 0x0500acUL 635 #define GRC_REG_DBG_FORCE_VALID \ 636 0x0500b0UL 637 #define GRC_REG_DBG_FORCE_FRAME \ 638 0x0500b4UL 639 #define UMAC_REG_DBG_SELECT \ 640 0x051094UL 641 #define UMAC_REG_DBG_DWORD_ENABLE \ 642 0x051098UL 643 #define UMAC_REG_DBG_SHIFT \ 644 0x05109cUL 645 #define UMAC_REG_DBG_FORCE_VALID \ 646 0x0510a0UL 647 #define UMAC_REG_DBG_FORCE_FRAME \ 648 0x0510a4UL 649 #define MCP2_REG_DBG_SELECT \ 650 0x052400UL 651 #define MCP2_REG_DBG_DWORD_ENABLE \ 652 0x052404UL 653 #define MCP2_REG_DBG_SHIFT \ 654 0x052408UL 655 #define MCP2_REG_DBG_FORCE_VALID \ 656 0x052440UL 657 #define MCP2_REG_DBG_FORCE_FRAME \ 658 0x052444UL 659 #define PCIE_REG_DBG_SELECT \ 660 0x0547e8UL 661 #define PCIE_REG_DBG_DWORD_ENABLE \ 662 0x0547ecUL 663 #define PCIE_REG_DBG_SHIFT \ 664 0x0547f0UL 665 #define PCIE_REG_DBG_FORCE_VALID \ 666 0x0547f4UL 667 #define PCIE_REG_DBG_FORCE_FRAME \ 668 0x0547f8UL 669 #define DORQ_REG_DBG_SELECT \ 670 0x100ad0UL 671 #define DORQ_REG_DBG_DWORD_ENABLE \ 672 0x100ad4UL 673 #define DORQ_REG_DBG_SHIFT \ 674 0x100ad8UL 675 #define DORQ_REG_DBG_FORCE_VALID \ 676 0x100adcUL 677 #define DORQ_REG_DBG_FORCE_FRAME \ 678 0x100ae0UL 679 #define IGU_REG_DBG_SELECT \ 680 0x181578UL 681 #define IGU_REG_DBG_DWORD_ENABLE \ 682 0x18157cUL 683 #define IGU_REG_DBG_SHIFT \ 684 0x181580UL 685 #define IGU_REG_DBG_FORCE_VALID \ 686 0x181584UL 687 #define IGU_REG_DBG_FORCE_FRAME \ 688 0x181588UL 689 #define CAU_REG_DBG_SELECT \ 690 0x1c0ea8UL 691 #define CAU_REG_DBG_DWORD_ENABLE \ 692 0x1c0eacUL 693 #define CAU_REG_DBG_SHIFT \ 694 0x1c0eb0UL 695 #define CAU_REG_DBG_FORCE_VALID \ 696 0x1c0eb4UL 697 #define CAU_REG_DBG_FORCE_FRAME \ 698 0x1c0eb8UL 699 #define PRS_REG_DBG_SELECT \ 700 0x1f0b6cUL 701 #define PRS_REG_DBG_DWORD_ENABLE \ 702 0x1f0b70UL 703 #define PRS_REG_DBG_SHIFT \ 704 0x1f0b74UL 705 #define PRS_REG_DBG_FORCE_VALID \ 706 0x1f0ba0UL 707 #define PRS_REG_DBG_FORCE_FRAME \ 708 0x1f0ba4UL 709 #define CNIG_REG_DBG_SELECT_K2 \ 710 0x218254UL 711 #define CNIG_REG_DBG_DWORD_ENABLE_K2 \ 712 0x218258UL 713 #define CNIG_REG_DBG_SHIFT_K2 \ 714 0x21825cUL 715 #define CNIG_REG_DBG_FORCE_VALID_K2 \ 716 0x218260UL 717 #define CNIG_REG_DBG_FORCE_FRAME_K2 \ 718 0x218264UL 719 #define PRM_REG_DBG_SELECT \ 720 0x2306a8UL 721 #define PRM_REG_DBG_DWORD_ENABLE \ 722 0x2306acUL 723 #define PRM_REG_DBG_SHIFT \ 724 0x2306b0UL 725 #define PRM_REG_DBG_FORCE_VALID \ 726 0x2306b4UL 727 #define PRM_REG_DBG_FORCE_FRAME \ 728 0x2306b8UL 729 #define SRC_REG_DBG_SELECT \ 730 0x238700UL 731 #define SRC_REG_DBG_DWORD_ENABLE \ 732 0x238704UL 733 #define SRC_REG_DBG_SHIFT \ 734 0x238708UL 735 #define SRC_REG_DBG_FORCE_VALID \ 736 0x23870cUL 737 #define SRC_REG_DBG_FORCE_FRAME \ 738 0x238710UL 739 #define RSS_REG_DBG_SELECT \ 740 0x238c4cUL 741 #define RSS_REG_DBG_DWORD_ENABLE \ 742 0x238c50UL 743 #define RSS_REG_DBG_SHIFT \ 744 0x238c54UL 745 #define RSS_REG_DBG_FORCE_VALID \ 746 0x238c58UL 747 #define RSS_REG_DBG_FORCE_FRAME \ 748 0x238c5cUL 749 #define RPB_REG_DBG_SELECT \ 750 0x23c728UL 751 #define RPB_REG_DBG_DWORD_ENABLE \ 752 0x23c72cUL 753 #define RPB_REG_DBG_SHIFT \ 754 0x23c730UL 755 #define RPB_REG_DBG_FORCE_VALID \ 756 0x23c734UL 757 #define RPB_REG_DBG_FORCE_FRAME \ 758 0x23c738UL 759 #define PSWRQ2_REG_DBG_SELECT \ 760 0x240100UL 761 #define PSWRQ2_REG_DBG_DWORD_ENABLE \ 762 0x240104UL 763 #define PSWRQ2_REG_DBG_SHIFT \ 764 0x240108UL 765 #define PSWRQ2_REG_DBG_FORCE_VALID \ 766 0x24010cUL 767 #define PSWRQ2_REG_DBG_FORCE_FRAME \ 768 0x240110UL 769 #define PSWRQ_REG_DBG_SELECT \ 770 0x280020UL 771 #define PSWRQ_REG_DBG_DWORD_ENABLE \ 772 0x280024UL 773 #define PSWRQ_REG_DBG_SHIFT \ 774 0x280028UL 775 #define PSWRQ_REG_DBG_FORCE_VALID \ 776 0x28002cUL 777 #define PSWRQ_REG_DBG_FORCE_FRAME \ 778 0x280030UL 779 #define PSWWR_REG_DBG_SELECT \ 780 0x29a084UL 781 #define PSWWR_REG_DBG_DWORD_ENABLE \ 782 0x29a088UL 783 #define PSWWR_REG_DBG_SHIFT \ 784 0x29a08cUL 785 #define PSWWR_REG_DBG_FORCE_VALID \ 786 0x29a090UL 787 #define PSWWR_REG_DBG_FORCE_FRAME \ 788 0x29a094UL 789 #define PSWRD_REG_DBG_SELECT \ 790 0x29c040UL 791 #define PSWRD_REG_DBG_DWORD_ENABLE \ 792 0x29c044UL 793 #define PSWRD_REG_DBG_SHIFT \ 794 0x29c048UL 795 #define PSWRD_REG_DBG_FORCE_VALID \ 796 0x29c04cUL 797 #define PSWRD_REG_DBG_FORCE_FRAME \ 798 0x29c050UL 799 #define PSWRD2_REG_DBG_SELECT \ 800 0x29d400UL 801 #define PSWRD2_REG_DBG_DWORD_ENABLE \ 802 0x29d404UL 803 #define PSWRD2_REG_DBG_SHIFT \ 804 0x29d408UL 805 #define PSWRD2_REG_DBG_FORCE_VALID \ 806 0x29d40cUL 807 #define PSWRD2_REG_DBG_FORCE_FRAME \ 808 0x29d410UL 809 #define PSWHST2_REG_DBG_SELECT \ 810 0x29e058UL 811 #define PSWHST2_REG_DBG_DWORD_ENABLE \ 812 0x29e05cUL 813 #define PSWHST2_REG_DBG_SHIFT \ 814 0x29e060UL 815 #define PSWHST2_REG_DBG_FORCE_VALID \ 816 0x29e064UL 817 #define PSWHST2_REG_DBG_FORCE_FRAME \ 818 0x29e068UL 819 #define PSWHST_REG_DBG_SELECT \ 820 0x2a0100UL 821 #define PSWHST_REG_DBG_DWORD_ENABLE \ 822 0x2a0104UL 823 #define PSWHST_REG_DBG_SHIFT \ 824 0x2a0108UL 825 #define PSWHST_REG_DBG_FORCE_VALID \ 826 0x2a010cUL 827 #define PSWHST_REG_DBG_FORCE_FRAME \ 828 0x2a0110UL 829 #define PGLUE_B_REG_DBG_SELECT \ 830 0x2a8400UL 831 #define PGLUE_B_REG_DBG_DWORD_ENABLE \ 832 0x2a8404UL 833 #define PGLUE_B_REG_DBG_SHIFT \ 834 0x2a8408UL 835 #define PGLUE_B_REG_DBG_FORCE_VALID \ 836 0x2a840cUL 837 #define PGLUE_B_REG_DBG_FORCE_FRAME \ 838 0x2a8410UL 839 #define TM_REG_DBG_SELECT \ 840 0x2c07a8UL 841 #define TM_REG_DBG_DWORD_ENABLE \ 842 0x2c07acUL 843 #define TM_REG_DBG_SHIFT \ 844 0x2c07b0UL 845 #define TM_REG_DBG_FORCE_VALID \ 846 0x2c07b4UL 847 #define TM_REG_DBG_FORCE_FRAME \ 848 0x2c07b8UL 849 #define TCFC_REG_DBG_SELECT \ 850 0x2d0500UL 851 #define TCFC_REG_DBG_DWORD_ENABLE \ 852 0x2d0504UL 853 #define TCFC_REG_DBG_SHIFT \ 854 0x2d0508UL 855 #define TCFC_REG_DBG_FORCE_VALID \ 856 0x2d050cUL 857 #define TCFC_REG_DBG_FORCE_FRAME \ 858 0x2d0510UL 859 #define CCFC_REG_DBG_SELECT \ 860 0x2e0500UL 861 #define CCFC_REG_DBG_DWORD_ENABLE \ 862 0x2e0504UL 863 #define CCFC_REG_DBG_SHIFT \ 864 0x2e0508UL 865 #define CCFC_REG_DBG_FORCE_VALID \ 866 0x2e050cUL 867 #define CCFC_REG_DBG_FORCE_FRAME \ 868 0x2e0510UL 869 #define QM_REG_DBG_SELECT \ 870 0x2f2e74UL 871 #define QM_REG_DBG_DWORD_ENABLE \ 872 0x2f2e78UL 873 #define QM_REG_DBG_SHIFT \ 874 0x2f2e7cUL 875 #define QM_REG_DBG_FORCE_VALID \ 876 0x2f2e80UL 877 #define QM_REG_DBG_FORCE_FRAME \ 878 0x2f2e84UL 879 #define RDIF_REG_DBG_SELECT \ 880 0x300500UL 881 #define RDIF_REG_DBG_DWORD_ENABLE \ 882 0x300504UL 883 #define RDIF_REG_DBG_SHIFT \ 884 0x300508UL 885 #define RDIF_REG_DBG_FORCE_VALID \ 886 0x30050cUL 887 #define RDIF_REG_DBG_FORCE_FRAME \ 888 0x300510UL 889 #define TDIF_REG_DBG_SELECT \ 890 0x310500UL 891 #define TDIF_REG_DBG_DWORD_ENABLE \ 892 0x310504UL 893 #define TDIF_REG_DBG_SHIFT \ 894 0x310508UL 895 #define TDIF_REG_DBG_FORCE_VALID \ 896 0x31050cUL 897 #define TDIF_REG_DBG_FORCE_FRAME \ 898 0x310510UL 899 #define BRB_REG_DBG_SELECT \ 900 0x340ed0UL 901 #define BRB_REG_DBG_DWORD_ENABLE \ 902 0x340ed4UL 903 #define BRB_REG_DBG_SHIFT \ 904 0x340ed8UL 905 #define BRB_REG_DBG_FORCE_VALID \ 906 0x340edcUL 907 #define BRB_REG_DBG_FORCE_FRAME \ 908 0x340ee0UL 909 #define XYLD_REG_DBG_SELECT \ 910 0x4c1600UL 911 #define XYLD_REG_DBG_DWORD_ENABLE \ 912 0x4c1604UL 913 #define XYLD_REG_DBG_SHIFT \ 914 0x4c1608UL 915 #define XYLD_REG_DBG_FORCE_VALID \ 916 0x4c160cUL 917 #define XYLD_REG_DBG_FORCE_FRAME \ 918 0x4c1610UL 919 #define YULD_REG_DBG_SELECT \ 920 0x4c9600UL 921 #define YULD_REG_DBG_DWORD_ENABLE \ 922 0x4c9604UL 923 #define YULD_REG_DBG_SHIFT \ 924 0x4c9608UL 925 #define YULD_REG_DBG_FORCE_VALID \ 926 0x4c960cUL 927 #define YULD_REG_DBG_FORCE_FRAME \ 928 0x4c9610UL 929 #define TMLD_REG_DBG_SELECT \ 930 0x4d1600UL 931 #define TMLD_REG_DBG_DWORD_ENABLE \ 932 0x4d1604UL 933 #define TMLD_REG_DBG_SHIFT \ 934 0x4d1608UL 935 #define TMLD_REG_DBG_FORCE_VALID \ 936 0x4d160cUL 937 #define TMLD_REG_DBG_FORCE_FRAME \ 938 0x4d1610UL 939 #define MULD_REG_DBG_SELECT \ 940 0x4e1600UL 941 #define MULD_REG_DBG_DWORD_ENABLE \ 942 0x4e1604UL 943 #define MULD_REG_DBG_SHIFT \ 944 0x4e1608UL 945 #define MULD_REG_DBG_FORCE_VALID \ 946 0x4e160cUL 947 #define MULD_REG_DBG_FORCE_FRAME \ 948 0x4e1610UL 949 #define NIG_REG_DBG_SELECT \ 950 0x502140UL 951 #define NIG_REG_DBG_DWORD_ENABLE \ 952 0x502144UL 953 #define NIG_REG_DBG_SHIFT \ 954 0x502148UL 955 #define NIG_REG_DBG_FORCE_VALID \ 956 0x50214cUL 957 #define NIG_REG_DBG_FORCE_FRAME \ 958 0x502150UL 959 #define BMB_REG_DBG_SELECT \ 960 0x540a7cUL 961 #define BMB_REG_DBG_DWORD_ENABLE \ 962 0x540a80UL 963 #define BMB_REG_DBG_SHIFT \ 964 0x540a84UL 965 #define BMB_REG_DBG_FORCE_VALID \ 966 0x540a88UL 967 #define BMB_REG_DBG_FORCE_FRAME \ 968 0x540a8cUL 969 #define PTU_REG_DBG_SELECT \ 970 0x560100UL 971 #define PTU_REG_DBG_DWORD_ENABLE \ 972 0x560104UL 973 #define PTU_REG_DBG_SHIFT \ 974 0x560108UL 975 #define PTU_REG_DBG_FORCE_VALID \ 976 0x56010cUL 977 #define PTU_REG_DBG_FORCE_FRAME \ 978 0x560110UL 979 #define CDU_REG_DBG_SELECT \ 980 0x580704UL 981 #define CDU_REG_DBG_DWORD_ENABLE \ 982 0x580708UL 983 #define CDU_REG_DBG_SHIFT \ 984 0x58070cUL 985 #define CDU_REG_DBG_FORCE_VALID \ 986 0x580710UL 987 #define CDU_REG_DBG_FORCE_FRAME \ 988 0x580714UL 989 #define WOL_REG_DBG_SELECT \ 990 0x600140UL 991 #define WOL_REG_DBG_DWORD_ENABLE \ 992 0x600144UL 993 #define WOL_REG_DBG_SHIFT \ 994 0x600148UL 995 #define WOL_REG_DBG_FORCE_VALID \ 996 0x60014cUL 997 #define WOL_REG_DBG_FORCE_FRAME \ 998 0x600150UL 999 #define BMBN_REG_DBG_SELECT \ 1000 0x610140UL 1001 #define BMBN_REG_DBG_DWORD_ENABLE \ 1002 0x610144UL 1003 #define BMBN_REG_DBG_SHIFT \ 1004 0x610148UL 1005 #define BMBN_REG_DBG_FORCE_VALID \ 1006 0x61014cUL 1007 #define BMBN_REG_DBG_FORCE_FRAME \ 1008 0x610150UL 1009 #define NWM_REG_DBG_SELECT \ 1010 0x8000ecUL 1011 #define NWM_REG_DBG_DWORD_ENABLE \ 1012 0x8000f0UL 1013 #define NWM_REG_DBG_SHIFT \ 1014 0x8000f4UL 1015 #define NWM_REG_DBG_FORCE_VALID \ 1016 0x8000f8UL 1017 #define NWM_REG_DBG_FORCE_FRAME \ 1018 0x8000fcUL 1019 #define PBF_REG_DBG_SELECT \ 1020 0xd80060UL 1021 #define PBF_REG_DBG_DWORD_ENABLE \ 1022 0xd80064UL 1023 #define PBF_REG_DBG_SHIFT \ 1024 0xd80068UL 1025 #define PBF_REG_DBG_FORCE_VALID \ 1026 0xd8006cUL 1027 #define PBF_REG_DBG_FORCE_FRAME \ 1028 0xd80070UL 1029 #define PBF_PB1_REG_DBG_SELECT \ 1030 0xda0728UL 1031 #define PBF_PB1_REG_DBG_DWORD_ENABLE \ 1032 0xda072cUL 1033 #define PBF_PB1_REG_DBG_SHIFT \ 1034 0xda0730UL 1035 #define PBF_PB1_REG_DBG_FORCE_VALID \ 1036 0xda0734UL 1037 #define PBF_PB1_REG_DBG_FORCE_FRAME \ 1038 0xda0738UL 1039 #define PBF_PB2_REG_DBG_SELECT \ 1040 0xda4728UL 1041 #define PBF_PB2_REG_DBG_DWORD_ENABLE \ 1042 0xda472cUL 1043 #define PBF_PB2_REG_DBG_SHIFT \ 1044 0xda4730UL 1045 #define PBF_PB2_REG_DBG_FORCE_VALID \ 1046 0xda4734UL 1047 #define PBF_PB2_REG_DBG_FORCE_FRAME \ 1048 0xda4738UL 1049 #define BTB_REG_DBG_SELECT \ 1050 0xdb08c8UL 1051 #define BTB_REG_DBG_DWORD_ENABLE \ 1052 0xdb08ccUL 1053 #define BTB_REG_DBG_SHIFT \ 1054 0xdb08d0UL 1055 #define BTB_REG_DBG_FORCE_VALID \ 1056 0xdb08d4UL 1057 #define BTB_REG_DBG_FORCE_FRAME \ 1058 0xdb08d8UL 1059 #define XSDM_REG_DBG_SELECT \ 1060 0xf80e28UL 1061 #define XSDM_REG_DBG_DWORD_ENABLE \ 1062 0xf80e2cUL 1063 #define XSDM_REG_DBG_SHIFT \ 1064 0xf80e30UL 1065 #define XSDM_REG_DBG_FORCE_VALID \ 1066 0xf80e34UL 1067 #define XSDM_REG_DBG_FORCE_FRAME \ 1068 0xf80e38UL 1069 #define YSDM_REG_DBG_SELECT \ 1070 0xf90e28UL 1071 #define YSDM_REG_DBG_DWORD_ENABLE \ 1072 0xf90e2cUL 1073 #define YSDM_REG_DBG_SHIFT \ 1074 0xf90e30UL 1075 #define YSDM_REG_DBG_FORCE_VALID \ 1076 0xf90e34UL 1077 #define YSDM_REG_DBG_FORCE_FRAME \ 1078 0xf90e38UL 1079 #define PSDM_REG_DBG_SELECT \ 1080 0xfa0e28UL 1081 #define PSDM_REG_DBG_DWORD_ENABLE \ 1082 0xfa0e2cUL 1083 #define PSDM_REG_DBG_SHIFT \ 1084 0xfa0e30UL 1085 #define PSDM_REG_DBG_FORCE_VALID \ 1086 0xfa0e34UL 1087 #define PSDM_REG_DBG_FORCE_FRAME \ 1088 0xfa0e38UL 1089 #define TSDM_REG_DBG_SELECT \ 1090 0xfb0e28UL 1091 #define TSDM_REG_DBG_DWORD_ENABLE \ 1092 0xfb0e2cUL 1093 #define TSDM_REG_DBG_SHIFT \ 1094 0xfb0e30UL 1095 #define TSDM_REG_DBG_FORCE_VALID \ 1096 0xfb0e34UL 1097 #define TSDM_REG_DBG_FORCE_FRAME \ 1098 0xfb0e38UL 1099 #define MSDM_REG_DBG_SELECT \ 1100 0xfc0e28UL 1101 #define MSDM_REG_DBG_DWORD_ENABLE \ 1102 0xfc0e2cUL 1103 #define MSDM_REG_DBG_SHIFT \ 1104 0xfc0e30UL 1105 #define MSDM_REG_DBG_FORCE_VALID \ 1106 0xfc0e34UL 1107 #define MSDM_REG_DBG_FORCE_FRAME \ 1108 0xfc0e38UL 1109 #define USDM_REG_DBG_SELECT \ 1110 0xfd0e28UL 1111 #define USDM_REG_DBG_DWORD_ENABLE \ 1112 0xfd0e2cUL 1113 #define USDM_REG_DBG_SHIFT \ 1114 0xfd0e30UL 1115 #define USDM_REG_DBG_FORCE_VALID \ 1116 0xfd0e34UL 1117 #define USDM_REG_DBG_FORCE_FRAME \ 1118 0xfd0e38UL 1119 #define XCM_REG_DBG_SELECT \ 1120 0x1000040UL 1121 #define XCM_REG_DBG_DWORD_ENABLE \ 1122 0x1000044UL 1123 #define XCM_REG_DBG_SHIFT \ 1124 0x1000048UL 1125 #define XCM_REG_DBG_FORCE_VALID \ 1126 0x100004cUL 1127 #define XCM_REG_DBG_FORCE_FRAME \ 1128 0x1000050UL 1129 #define YCM_REG_DBG_SELECT \ 1130 0x1080040UL 1131 #define YCM_REG_DBG_DWORD_ENABLE \ 1132 0x1080044UL 1133 #define YCM_REG_DBG_SHIFT \ 1134 0x1080048UL 1135 #define YCM_REG_DBG_FORCE_VALID \ 1136 0x108004cUL 1137 #define YCM_REG_DBG_FORCE_FRAME \ 1138 0x1080050UL 1139 #define PCM_REG_DBG_SELECT \ 1140 0x1100040UL 1141 #define PCM_REG_DBG_DWORD_ENABLE \ 1142 0x1100044UL 1143 #define PCM_REG_DBG_SHIFT \ 1144 0x1100048UL 1145 #define PCM_REG_DBG_FORCE_VALID \ 1146 0x110004cUL 1147 #define PCM_REG_DBG_FORCE_FRAME \ 1148 0x1100050UL 1149 #define TCM_REG_DBG_SELECT \ 1150 0x1180040UL 1151 #define TCM_REG_DBG_DWORD_ENABLE \ 1152 0x1180044UL 1153 #define TCM_REG_DBG_SHIFT \ 1154 0x1180048UL 1155 #define TCM_REG_DBG_FORCE_VALID \ 1156 0x118004cUL 1157 #define TCM_REG_DBG_FORCE_FRAME \ 1158 0x1180050UL 1159 #define MCM_REG_DBG_SELECT \ 1160 0x1200040UL 1161 #define MCM_REG_DBG_DWORD_ENABLE \ 1162 0x1200044UL 1163 #define MCM_REG_DBG_SHIFT \ 1164 0x1200048UL 1165 #define MCM_REG_DBG_FORCE_VALID \ 1166 0x120004cUL 1167 #define MCM_REG_DBG_FORCE_FRAME \ 1168 0x1200050UL 1169 #define UCM_REG_DBG_SELECT \ 1170 0x1280050UL 1171 #define UCM_REG_DBG_DWORD_ENABLE \ 1172 0x1280054UL 1173 #define UCM_REG_DBG_SHIFT \ 1174 0x1280058UL 1175 #define UCM_REG_DBG_FORCE_VALID \ 1176 0x128005cUL 1177 #define UCM_REG_DBG_FORCE_FRAME \ 1178 0x1280060UL 1179 #define XSEM_REG_DBG_SELECT \ 1180 0x1401528UL 1181 #define XSEM_REG_DBG_DWORD_ENABLE \ 1182 0x140152cUL 1183 #define XSEM_REG_DBG_SHIFT \ 1184 0x1401530UL 1185 #define XSEM_REG_DBG_FORCE_VALID \ 1186 0x1401534UL 1187 #define XSEM_REG_DBG_FORCE_FRAME \ 1188 0x1401538UL 1189 #define YSEM_REG_DBG_SELECT \ 1190 0x1501528UL 1191 #define YSEM_REG_DBG_DWORD_ENABLE \ 1192 0x150152cUL 1193 #define YSEM_REG_DBG_SHIFT \ 1194 0x1501530UL 1195 #define YSEM_REG_DBG_FORCE_VALID \ 1196 0x1501534UL 1197 #define YSEM_REG_DBG_FORCE_FRAME \ 1198 0x1501538UL 1199 #define PSEM_REG_DBG_SELECT \ 1200 0x1601528UL 1201 #define PSEM_REG_DBG_DWORD_ENABLE \ 1202 0x160152cUL 1203 #define PSEM_REG_DBG_SHIFT \ 1204 0x1601530UL 1205 #define PSEM_REG_DBG_FORCE_VALID \ 1206 0x1601534UL 1207 #define PSEM_REG_DBG_FORCE_FRAME \ 1208 0x1601538UL 1209 #define TSEM_REG_DBG_SELECT \ 1210 0x1701528UL 1211 #define TSEM_REG_DBG_DWORD_ENABLE \ 1212 0x170152cUL 1213 #define TSEM_REG_DBG_SHIFT \ 1214 0x1701530UL 1215 #define TSEM_REG_DBG_FORCE_VALID \ 1216 0x1701534UL 1217 #define TSEM_REG_DBG_FORCE_FRAME \ 1218 0x1701538UL 1219 #define MSEM_REG_DBG_SELECT \ 1220 0x1801528UL 1221 #define MSEM_REG_DBG_DWORD_ENABLE \ 1222 0x180152cUL 1223 #define MSEM_REG_DBG_SHIFT \ 1224 0x1801530UL 1225 #define MSEM_REG_DBG_FORCE_VALID \ 1226 0x1801534UL 1227 #define MSEM_REG_DBG_FORCE_FRAME \ 1228 0x1801538UL 1229 #define USEM_REG_DBG_SELECT \ 1230 0x1901528UL 1231 #define USEM_REG_DBG_DWORD_ENABLE \ 1232 0x190152cUL 1233 #define USEM_REG_DBG_SHIFT \ 1234 0x1901530UL 1235 #define USEM_REG_DBG_FORCE_VALID \ 1236 0x1901534UL 1237 #define USEM_REG_DBG_FORCE_FRAME \ 1238 0x1901538UL 1239 #define PCIE_REG_DBG_COMMON_SELECT \ 1240 0x054398UL 1241 #define PCIE_REG_DBG_COMMON_DWORD_ENABLE \ 1242 0x05439cUL 1243 #define PCIE_REG_DBG_COMMON_SHIFT \ 1244 0x0543a0UL 1245 #define PCIE_REG_DBG_COMMON_FORCE_VALID \ 1246 0x0543a4UL 1247 #define PCIE_REG_DBG_COMMON_FORCE_FRAME \ 1248 0x0543a8UL 1249 #define MISC_REG_RESET_PL_UA \ 1250 0x008050UL 1251 #define MISC_REG_RESET_PL_HV \ 1252 0x008060UL 1253 #define XCM_REG_CTX_RBC_ACCS \ 1254 0x1001800UL 1255 #define XCM_REG_AGG_CON_CTX \ 1256 0x1001804UL 1257 #define XCM_REG_SM_CON_CTX \ 1258 0x1001808UL 1259 #define YCM_REG_CTX_RBC_ACCS \ 1260 0x1081800UL 1261 #define YCM_REG_AGG_CON_CTX \ 1262 0x1081804UL 1263 #define YCM_REG_AGG_TASK_CTX \ 1264 0x1081808UL 1265 #define YCM_REG_SM_CON_CTX \ 1266 0x108180cUL 1267 #define YCM_REG_SM_TASK_CTX \ 1268 0x1081810UL 1269 #define PCM_REG_CTX_RBC_ACCS \ 1270 0x1101440UL 1271 #define PCM_REG_SM_CON_CTX \ 1272 0x1101444UL 1273 #define TCM_REG_CTX_RBC_ACCS \ 1274 0x11814c0UL 1275 #define TCM_REG_AGG_CON_CTX \ 1276 0x11814c4UL 1277 #define TCM_REG_AGG_TASK_CTX \ 1278 0x11814c8UL 1279 #define TCM_REG_SM_CON_CTX \ 1280 0x11814ccUL 1281 #define TCM_REG_SM_TASK_CTX \ 1282 0x11814d0UL 1283 #define MCM_REG_CTX_RBC_ACCS \ 1284 0x1201800UL 1285 #define MCM_REG_AGG_CON_CTX \ 1286 0x1201804UL 1287 #define MCM_REG_AGG_TASK_CTX \ 1288 0x1201808UL 1289 #define MCM_REG_SM_CON_CTX \ 1290 0x120180cUL 1291 #define MCM_REG_SM_TASK_CTX \ 1292 0x1201810UL 1293 #define UCM_REG_CTX_RBC_ACCS \ 1294 0x1281700UL 1295 #define UCM_REG_AGG_CON_CTX \ 1296 0x1281704UL 1297 #define UCM_REG_AGG_TASK_CTX \ 1298 0x1281708UL 1299 #define UCM_REG_SM_CON_CTX \ 1300 0x128170cUL 1301 #define UCM_REG_SM_TASK_CTX \ 1302 0x1281710UL 1303 #define XSEM_REG_SLOW_DBG_EMPTY \ 1304 0x1401140UL 1305 #define XSEM_REG_SYNC_DBG_EMPTY \ 1306 0x1401160UL 1307 #define XSEM_REG_SLOW_DBG_ACTIVE \ 1308 0x1401400UL 1309 #define XSEM_REG_SLOW_DBG_MODE \ 1310 0x1401404UL 1311 #define XSEM_REG_DBG_FRAME_MODE \ 1312 0x1401408UL 1313 #define XSEM_REG_DBG_MODE1_CFG \ 1314 0x1401420UL 1315 #define XSEM_REG_FAST_MEMORY \ 1316 0x1440000UL 1317 #define YSEM_REG_SYNC_DBG_EMPTY \ 1318 0x1501160UL 1319 #define YSEM_REG_SLOW_DBG_ACTIVE \ 1320 0x1501400UL 1321 #define YSEM_REG_SLOW_DBG_MODE \ 1322 0x1501404UL 1323 #define YSEM_REG_DBG_FRAME_MODE \ 1324 0x1501408UL 1325 #define YSEM_REG_DBG_MODE1_CFG \ 1326 0x1501420UL 1327 #define YSEM_REG_FAST_MEMORY \ 1328 0x1540000UL 1329 #define PSEM_REG_SLOW_DBG_EMPTY \ 1330 0x1601140UL 1331 #define PSEM_REG_SYNC_DBG_EMPTY \ 1332 0x1601160UL 1333 #define PSEM_REG_SLOW_DBG_ACTIVE \ 1334 0x1601400UL 1335 #define PSEM_REG_SLOW_DBG_MODE \ 1336 0x1601404UL 1337 #define PSEM_REG_DBG_FRAME_MODE \ 1338 0x1601408UL 1339 #define PSEM_REG_DBG_MODE1_CFG \ 1340 0x1601420UL 1341 #define PSEM_REG_FAST_MEMORY \ 1342 0x1640000UL 1343 #define TSEM_REG_SLOW_DBG_EMPTY \ 1344 0x1701140UL 1345 #define TSEM_REG_SYNC_DBG_EMPTY \ 1346 0x1701160UL 1347 #define TSEM_REG_SLOW_DBG_ACTIVE \ 1348 0x1701400UL 1349 #define TSEM_REG_SLOW_DBG_MODE \ 1350 0x1701404UL 1351 #define TSEM_REG_DBG_FRAME_MODE \ 1352 0x1701408UL 1353 #define TSEM_REG_DBG_MODE1_CFG \ 1354 0x1701420UL 1355 #define TSEM_REG_FAST_MEMORY \ 1356 0x1740000UL 1357 #define MSEM_REG_SLOW_DBG_EMPTY \ 1358 0x1801140UL 1359 #define MSEM_REG_SYNC_DBG_EMPTY \ 1360 0x1801160UL 1361 #define MSEM_REG_SLOW_DBG_ACTIVE \ 1362 0x1801400UL 1363 #define MSEM_REG_SLOW_DBG_MODE \ 1364 0x1801404UL 1365 #define MSEM_REG_DBG_FRAME_MODE \ 1366 0x1801408UL 1367 #define MSEM_REG_DBG_MODE1_CFG \ 1368 0x1801420UL 1369 #define MSEM_REG_FAST_MEMORY \ 1370 0x1840000UL 1371 #define USEM_REG_SLOW_DBG_EMPTY \ 1372 0x1901140UL 1373 #define USEM_REG_SYNC_DBG_EMPTY \ 1374 0x1901160UL 1375 #define USEM_REG_SLOW_DBG_ACTIVE \ 1376 0x1901400UL 1377 #define USEM_REG_SLOW_DBG_MODE \ 1378 0x1901404UL 1379 #define USEM_REG_DBG_FRAME_MODE \ 1380 0x1901408UL 1381 #define USEM_REG_DBG_MODE1_CFG \ 1382 0x1901420UL 1383 #define USEM_REG_FAST_MEMORY \ 1384 0x1940000UL 1385 #define SEM_FAST_REG_INT_RAM \ 1386 0x020000UL 1387 #define SEM_FAST_REG_INT_RAM_SIZE \ 1388 20480 1389 #define GRC_REG_TRACE_FIFO_VALID_DATA \ 1390 0x050064UL 1391 #define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW \ 1392 0x05040cUL 1393 #define GRC_REG_PROTECTION_OVERRIDE_WINDOW \ 1394 0x050500UL 1395 #define IGU_REG_ERROR_HANDLING_MEMORY \ 1396 0x181520UL 1397 #define MCP_REG_CPU_MODE \ 1398 0xe05000UL 1399 #define MCP_REG_CPU_MODE_SOFT_HALT \ 1400 (0x1 << 10) 1401 #define BRB_REG_BIG_RAM_ADDRESS \ 1402 0x340800UL 1403 #define BRB_REG_BIG_RAM_DATA \ 1404 0x341500UL 1405 #define SEM_FAST_REG_STALL_0 \ 1406 0x000488UL 1407 #define SEM_FAST_REG_STALLED \ 1408 0x000494UL 1409 #define BTB_REG_BIG_RAM_ADDRESS \ 1410 0xdb0800UL 1411 #define BTB_REG_BIG_RAM_DATA \ 1412 0xdb0c00UL 1413 #define BMB_REG_BIG_RAM_ADDRESS \ 1414 0x540800UL 1415 #define BMB_REG_BIG_RAM_DATA \ 1416 0x540f00UL 1417 #define SEM_FAST_REG_STORM_REG_FILE \ 1418 0x008000UL 1419 #define RSS_REG_RSS_RAM_ADDR \ 1420 0x238c30UL 1421 #define MISCS_REG_BLOCK_256B_EN \ 1422 0x009074UL 1423 #define MCP_REG_SCRATCH_SIZE \ 1424 57344 1425 #define MCP_REG_CPU_REG_FILE \ 1426 0xe05200UL 1427 #define MCP_REG_CPU_REG_FILE_SIZE \ 1428 32 1429 #define DBG_REG_DEBUG_TARGET \ 1430 0x01005cUL 1431 #define DBG_REG_FULL_MODE \ 1432 0x010060UL 1433 #define DBG_REG_CALENDAR_OUT_DATA \ 1434 0x010480UL 1435 #define GRC_REG_TRACE_FIFO \ 1436 0x050068UL 1437 #define IGU_REG_ERROR_HANDLING_DATA_VALID \ 1438 0x181530UL 1439 #define DBG_REG_DBG_BLOCK_ON \ 1440 0x010454UL 1441 #define DBG_REG_FRAMING_MODE \ 1442 0x010058UL 1443 #define SEM_FAST_REG_VFC_DATA_WR \ 1444 0x000b40UL 1445 #define SEM_FAST_REG_VFC_ADDR \ 1446 0x000b44UL 1447 #define SEM_FAST_REG_VFC_DATA_RD \ 1448 0x000b48UL 1449 #define RSS_REG_RSS_RAM_DATA \ 1450 0x238c20UL 1451 #define MISC_REG_BLOCK_256B_EN \ 1452 0x008c14UL 1453 #define NWS_REG_NWS_CMU \ 1454 0x720000UL 1455 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0 \ 1456 0x000680UL 1457 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8 \ 1458 0x000684UL 1459 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0 \ 1460 0x0006c0UL 1461 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8 \ 1462 0x0006c4UL 1463 #define MS_REG_MS_CMU \ 1464 0x6a4000UL 1465 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130 \ 1466 0x000208UL 1467 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132 \ 1468 0x000210UL 1469 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131 \ 1470 0x00020cUL 1471 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133 \ 1472 0x000214UL 1473 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130 \ 1474 0x000208UL 1475 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131 \ 1476 0x00020cUL 1477 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132 \ 1478 0x000210UL 1479 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133 \ 1480 0x000214UL 1481 #define PHY_PCIE_REG_PHY0 \ 1482 0x620000UL 1483 #define PHY_PCIE_REG_PHY1 \ 1484 0x624000UL 1485 #define NIG_REG_ROCE_DUPLICATE_TO_HOST 0x5088f0UL 1486 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN 0x1f0968UL 1487 #define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL 1488 #define DORQ_REG_PF_DPM_ENABLE 0x100510UL 1489 #define DORQ_REG_PF_ICID_BIT_SHIFT_NORM 0x100448UL 1490 #define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL 1491 #define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL 1492 #define NIG_REG_RX_PTP_EN 0x501900UL 1493 #define NIG_REG_TX_PTP_EN 0x501904UL 1494 #define NIG_REG_LLH_PTP_TO_HOST 0x501908UL 1495 #define NIG_REG_LLH_PTP_TO_MCP 0x50190cUL 1496 #define NIG_REG_PTP_SW_TXTSEN 0x501910UL 1497 #define NIG_REG_LLH_PTP_ETHERTYPE_1 0x501914UL 1498 #define NIG_REG_LLH_PTP_MAC_DA_2_LSB 0x501918UL 1499 #define NIG_REG_LLH_PTP_MAC_DA_2_MSB 0x50191cUL 1500 #define NIG_REG_LLH_PTP_PARAM_MASK 0x501920UL 1501 #define NIG_REG_LLH_PTP_RULE_MASK 0x501924UL 1502 #define NIG_REG_TX_LLH_PTP_PARAM_MASK 0x501928UL 1503 #define NIG_REG_TX_LLH_PTP_RULE_MASK 0x50192cUL 1504 #define NIG_REG_LLH_PTP_HOST_BUF_SEQID 0x501930UL 1505 #define NIG_REG_LLH_PTP_HOST_BUF_TS_LSB 0x501934UL 1506 #define NIG_REG_LLH_PTP_HOST_BUF_TS_MSB 0x501938UL 1507 #define NIG_REG_LLH_PTP_MCP_BUF_SEQID 0x50193cUL 1508 #define NIG_REG_LLH_PTP_MCP_BUF_TS_LSB 0x501940UL 1509 #define NIG_REG_LLH_PTP_MCP_BUF_TS_MSB 0x501944UL 1510 #define NIG_REG_TX_LLH_PTP_BUF_SEQID 0x501948UL 1511 #define NIG_REG_TX_LLH_PTP_BUF_TS_LSB 0x50194cUL 1512 #define NIG_REG_TX_LLH_PTP_BUF_TS_MSB 0x501950UL 1513 #define NIG_REG_RX_PTP_TS_MSB_ERR 0x501954UL 1514 #define NIG_REG_TX_PTP_TS_MSB_ERR 0x501958UL 1515 #define NIG_REG_TSGEN_SYNC_TIME_LSB 0x5088c0UL 1516 #define NIG_REG_TSGEN_SYNC_TIME_MSB 0x5088c4UL 1517 #define NIG_REG_TSGEN_RST_DRIFT_CNTR 0x5088d8UL 1518 #define NIG_REG_TSGEN_DRIFT_CNTR_CONF 0x5088dcUL 1519 #define NIG_REG_TS_OUTPUT_ENABLE_PDA 0x508870UL 1520 #define NIG_REG_TIMESYNC_GEN_REG_BB 0x500d00UL 1521 #define NIG_REG_TSGEN_FREE_CNT_VALUE_LSB 0x5088a8UL 1522 #define NIG_REG_TSGEN_FREE_CNT_VALUE_MSB 0x5088acUL 1523 #endif 1524