1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* QLogic qed NIC Driver 3 * Copyright (c) 2015-2017 QLogic Corporation 4 * Copyright (c) 2019-2020 Marvell International Ltd. 5 */ 6 7 #ifndef _QED_MCP_H 8 #define _QED_MCP_H 9 10 #include <linux/types.h> 11 #include <linux/delay.h> 12 #include <linux/slab.h> 13 #include <linux/spinlock.h> 14 #include <linux/qed/qed_fcoe_if.h> 15 #include "qed_hsi.h" 16 #include "qed_dev_api.h" 17 18 #define QED_MFW_REPORT_STR_SIZE 256 19 20 struct qed_mcp_link_speed_params { 21 bool autoneg; 22 23 u32 advertised_speeds; 24 #define QED_EXT_SPEED_MASK_RES 0x1 25 #define QED_EXT_SPEED_MASK_1G 0x2 26 #define QED_EXT_SPEED_MASK_10G 0x4 27 #define QED_EXT_SPEED_MASK_20G 0x8 28 #define QED_EXT_SPEED_MASK_25G 0x10 29 #define QED_EXT_SPEED_MASK_40G 0x20 30 #define QED_EXT_SPEED_MASK_50G_R 0x40 31 #define QED_EXT_SPEED_MASK_50G_R2 0x80 32 #define QED_EXT_SPEED_MASK_100G_R2 0x100 33 #define QED_EXT_SPEED_MASK_100G_R4 0x200 34 #define QED_EXT_SPEED_MASK_100G_P4 0x400 35 36 u32 forced_speed; /* In Mb/s */ 37 #define QED_EXT_SPEED_1G 0x1 38 #define QED_EXT_SPEED_10G 0x2 39 #define QED_EXT_SPEED_20G 0x4 40 #define QED_EXT_SPEED_25G 0x8 41 #define QED_EXT_SPEED_40G 0x10 42 #define QED_EXT_SPEED_50G_R 0x20 43 #define QED_EXT_SPEED_50G_R2 0x40 44 #define QED_EXT_SPEED_100G_R2 0x80 45 #define QED_EXT_SPEED_100G_R4 0x100 46 #define QED_EXT_SPEED_100G_P4 0x200 47 }; 48 49 struct qed_mcp_link_pause_params { 50 bool autoneg; 51 bool forced_rx; 52 bool forced_tx; 53 }; 54 55 enum qed_mcp_eee_mode { 56 QED_MCP_EEE_DISABLED, 57 QED_MCP_EEE_ENABLED, 58 QED_MCP_EEE_UNSUPPORTED 59 }; 60 61 struct qed_mcp_link_params { 62 struct qed_mcp_link_speed_params speed; 63 struct qed_mcp_link_pause_params pause; 64 u32 loopback_mode; 65 struct qed_link_eee_params eee; 66 u32 fec; 67 68 struct qed_mcp_link_speed_params ext_speed; 69 u32 ext_fec_mode; 70 }; 71 72 struct qed_mcp_link_capabilities { 73 u32 speed_capabilities; 74 bool default_speed_autoneg; 75 u32 fec_default; 76 enum qed_mcp_eee_mode default_eee; 77 u32 eee_lpi_timer; 78 u8 eee_speed_caps; 79 80 u32 default_ext_speed_caps; 81 u32 default_ext_autoneg; 82 u32 default_ext_speed; 83 u32 default_ext_fec; 84 }; 85 86 struct qed_mcp_link_state { 87 bool link_up; 88 u32 min_pf_rate; 89 90 /* Actual link speed in Mb/s */ 91 u32 line_speed; 92 93 /* PF max speed in Mb/s, deduced from line_speed 94 * according to PF max bandwidth configuration. 95 */ 96 u32 speed; 97 98 bool full_duplex; 99 bool an; 100 bool an_complete; 101 bool parallel_detection; 102 bool pfc_enabled; 103 104 u32 partner_adv_speed; 105 #define QED_LINK_PARTNER_SPEED_1G_HD BIT(0) 106 #define QED_LINK_PARTNER_SPEED_1G_FD BIT(1) 107 #define QED_LINK_PARTNER_SPEED_10G BIT(2) 108 #define QED_LINK_PARTNER_SPEED_20G BIT(3) 109 #define QED_LINK_PARTNER_SPEED_25G BIT(4) 110 #define QED_LINK_PARTNER_SPEED_40G BIT(5) 111 #define QED_LINK_PARTNER_SPEED_50G BIT(6) 112 #define QED_LINK_PARTNER_SPEED_100G BIT(7) 113 114 bool partner_tx_flow_ctrl_en; 115 bool partner_rx_flow_ctrl_en; 116 117 u8 partner_adv_pause; 118 #define QED_LINK_PARTNER_SYMMETRIC_PAUSE 0x1 119 #define QED_LINK_PARTNER_ASYMMETRIC_PAUSE 0x2 120 #define QED_LINK_PARTNER_BOTH_PAUSE 0x3 121 122 bool sfp_tx_fault; 123 bool eee_active; 124 u8 eee_adv_caps; 125 u8 eee_lp_adv_caps; 126 127 u32 fec_active; 128 }; 129 130 struct qed_mcp_function_info { 131 u8 pause_on_host; 132 133 enum qed_pci_personality protocol; 134 135 u8 bandwidth_min; 136 u8 bandwidth_max; 137 138 u8 mac[ETH_ALEN]; 139 140 u64 wwn_port; 141 u64 wwn_node; 142 143 #define QED_MCP_VLAN_UNSET (0xffff) 144 u16 ovlan; 145 146 u16 mtu; 147 }; 148 149 struct qed_mcp_nvm_common { 150 u32 offset; 151 u32 param; 152 u32 resp; 153 u32 cmd; 154 }; 155 156 struct qed_mcp_drv_version { 157 u32 version; 158 u8 name[MCP_DRV_VER_STR_SIZE - 4]; 159 }; 160 161 struct qed_mcp_lan_stats { 162 u64 ucast_rx_pkts; 163 u64 ucast_tx_pkts; 164 u32 fcs_err; 165 }; 166 167 struct qed_mcp_fcoe_stats { 168 u64 rx_pkts; 169 u64 tx_pkts; 170 u32 fcs_err; 171 u32 login_failure; 172 }; 173 174 struct qed_mcp_iscsi_stats { 175 u64 rx_pdus; 176 u64 tx_pdus; 177 u64 rx_bytes; 178 u64 tx_bytes; 179 }; 180 181 struct qed_mcp_rdma_stats { 182 u64 rx_pkts; 183 u64 tx_pkts; 184 u64 rx_bytes; 185 u64 tx_byts; 186 }; 187 188 enum qed_mcp_protocol_type { 189 QED_MCP_LAN_STATS, 190 QED_MCP_FCOE_STATS, 191 QED_MCP_ISCSI_STATS, 192 QED_MCP_RDMA_STATS 193 }; 194 195 union qed_mcp_protocol_stats { 196 struct qed_mcp_lan_stats lan_stats; 197 struct qed_mcp_fcoe_stats fcoe_stats; 198 struct qed_mcp_iscsi_stats iscsi_stats; 199 struct qed_mcp_rdma_stats rdma_stats; 200 }; 201 202 enum qed_ov_eswitch { 203 QED_OV_ESWITCH_NONE, 204 QED_OV_ESWITCH_VEB, 205 QED_OV_ESWITCH_VEPA 206 }; 207 208 enum qed_ov_client { 209 QED_OV_CLIENT_DRV, 210 QED_OV_CLIENT_USER, 211 QED_OV_CLIENT_VENDOR_SPEC 212 }; 213 214 enum qed_ov_driver_state { 215 QED_OV_DRIVER_STATE_NOT_LOADED, 216 QED_OV_DRIVER_STATE_DISABLED, 217 QED_OV_DRIVER_STATE_ACTIVE 218 }; 219 220 enum qed_ov_wol { 221 QED_OV_WOL_DEFAULT, 222 QED_OV_WOL_DISABLED, 223 QED_OV_WOL_ENABLED 224 }; 225 226 enum qed_mfw_tlv_type { 227 QED_MFW_TLV_GENERIC = 0x1, /* Core driver TLVs */ 228 QED_MFW_TLV_ETH = 0x2, /* L2 driver TLVs */ 229 QED_MFW_TLV_FCOE = 0x4, /* FCoE protocol TLVs */ 230 QED_MFW_TLV_ISCSI = 0x8, /* SCSI protocol TLVs */ 231 QED_MFW_TLV_MAX = 0x16, 232 }; 233 234 struct qed_mfw_tlv_generic { 235 #define QED_MFW_TLV_FLAGS_SIZE 2 236 struct { 237 u8 ipv4_csum_offload; 238 u8 lso_supported; 239 bool b_set; 240 } flags; 241 242 #define QED_MFW_TLV_MAC_COUNT 3 243 /* First entry for primary MAC, 2 secondary MACs possible */ 244 u8 mac[QED_MFW_TLV_MAC_COUNT][6]; 245 bool mac_set[QED_MFW_TLV_MAC_COUNT]; 246 247 u64 rx_frames; 248 bool rx_frames_set; 249 u64 rx_bytes; 250 bool rx_bytes_set; 251 u64 tx_frames; 252 bool tx_frames_set; 253 u64 tx_bytes; 254 bool tx_bytes_set; 255 }; 256 257 union qed_mfw_tlv_data { 258 struct qed_mfw_tlv_generic generic; 259 struct qed_mfw_tlv_eth eth; 260 struct qed_mfw_tlv_fcoe fcoe; 261 struct qed_mfw_tlv_iscsi iscsi; 262 }; 263 264 #define QED_NVM_CFG_OPTION_ALL BIT(0) 265 #define QED_NVM_CFG_OPTION_INIT BIT(1) 266 #define QED_NVM_CFG_OPTION_COMMIT BIT(2) 267 #define QED_NVM_CFG_OPTION_FREE BIT(3) 268 #define QED_NVM_CFG_OPTION_ENTITY_SEL BIT(4) 269 270 /** 271 * qed_mcp_get_link_params(): Returns the link params of the hw function. 272 * 273 * @p_hwfn: HW device data. 274 * 275 * Returns: Pointer to link params. 276 */ 277 struct qed_mcp_link_params *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn); 278 279 /** 280 * qed_mcp_get_link_state(): Return the link state of the hw function. 281 * 282 * @p_hwfn: HW device data. 283 * 284 * Returns: Pointer to link state. 285 */ 286 struct qed_mcp_link_state *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn); 287 288 /** 289 * qed_mcp_get_link_capabilities(): Return the link capabilities of the 290 * hw function. 291 * 292 * @p_hwfn: HW device data. 293 * 294 * Returns: Pointer to link capabilities. 295 */ 296 struct qed_mcp_link_capabilities 297 *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn); 298 299 /** 300 * qed_mcp_set_link(): Request the MFW to set the link according 301 * to 'link_input'. 302 * 303 * @p_hwfn: HW device data. 304 * @p_ptt: P_ptt. 305 * @b_up: Raise link if `true'. Reset link if `false'. 306 * 307 * Return: Int. 308 */ 309 int qed_mcp_set_link(struct qed_hwfn *p_hwfn, 310 struct qed_ptt *p_ptt, 311 bool b_up); 312 313 /** 314 * qed_mcp_get_mfw_ver(): Get the management firmware version value. 315 * 316 * @p_hwfn: HW device data. 317 * @p_ptt: P_ptt. 318 * @p_mfw_ver: MFW version value. 319 * @p_running_bundle_id: Image id in nvram; Optional. 320 * 321 * Return: Int - 0 - operation was successful. 322 */ 323 int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 324 struct qed_ptt *p_ptt, 325 u32 *p_mfw_ver, u32 *p_running_bundle_id); 326 327 /** 328 * qed_mcp_get_mbi_ver(): Get the MBI version value. 329 * 330 * @p_hwfn: HW device data. 331 * @p_ptt: P_ptt. 332 * @p_mbi_ver: A pointer to a variable to be filled with the MBI version. 333 * 334 * Return: Int - 0 - operation was successful. 335 */ 336 int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn, 337 struct qed_ptt *p_ptt, u32 *p_mbi_ver); 338 339 /** 340 * qed_mcp_get_media_type(): Get media type value of the port. 341 * 342 * @p_hwfn: HW device data. 343 * @p_ptt: P_ptt. 344 * @media_type: Media type value 345 * 346 * Return: Int - 0 - Operation was successul. 347 * -EBUSY - Operation failed 348 */ 349 int qed_mcp_get_media_type(struct qed_hwfn *p_hwfn, 350 struct qed_ptt *p_ptt, u32 *media_type); 351 352 /** 353 * qed_mcp_get_transceiver_data(): Get transceiver data of the port. 354 * 355 * @p_hwfn: HW device data. 356 * @p_ptt: P_ptt. 357 * @p_transceiver_state: Transceiver state. 358 * @p_tranceiver_type: Media type value. 359 * 360 * Return: Int - 0 - Operation was successul. 361 * -EBUSY - Operation failed 362 */ 363 int qed_mcp_get_transceiver_data(struct qed_hwfn *p_hwfn, 364 struct qed_ptt *p_ptt, 365 u32 *p_transceiver_state, 366 u32 *p_tranceiver_type); 367 368 /** 369 * qed_mcp_trans_speed_mask(): Get transceiver supported speed mask. 370 * 371 * @p_hwfn: HW device data. 372 * @p_ptt: P_ptt. 373 * @p_speed_mask: Bit mask of all supported speeds. 374 * 375 * Return: Int - 0 - Operation was successul. 376 * -EBUSY - Operation failed 377 */ 378 379 int qed_mcp_trans_speed_mask(struct qed_hwfn *p_hwfn, 380 struct qed_ptt *p_ptt, u32 *p_speed_mask); 381 382 /** 383 * qed_mcp_get_board_config(): Get board configuration. 384 * 385 * @p_hwfn: HW device data. 386 * @p_ptt: P_ptt. 387 * @p_board_config: Board config. 388 * 389 * Return: Int - 0 - Operation was successul. 390 * -EBUSY - Operation failed 391 */ 392 int qed_mcp_get_board_config(struct qed_hwfn *p_hwfn, 393 struct qed_ptt *p_ptt, u32 *p_board_config); 394 395 /** 396 * qed_mcp_cmd(): General function for sending commands to the MCP 397 * mailbox. It acquire mutex lock for the entire 398 * operation, from sending the request until the MCP 399 * response. Waiting for MCP response will be checked up 400 * to 5 seconds every 5ms. 401 * 402 * @p_hwfn: HW device data. 403 * @p_ptt: PTT required for register access. 404 * @cmd: command to be sent to the MCP. 405 * @param: Optional param 406 * @o_mcp_resp: The MCP response code (exclude sequence). 407 * @o_mcp_param: Optional parameter provided by the MCP 408 * response 409 * 410 * Return: Int - 0 - Operation was successul. 411 */ 412 int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 413 struct qed_ptt *p_ptt, 414 u32 cmd, 415 u32 param, 416 u32 *o_mcp_resp, 417 u32 *o_mcp_param); 418 419 /** 420 * qed_mcp_drain(): drains the nig, allowing completion to pass in 421 * case of pauses. 422 * (Should be called only from sleepable context) 423 * 424 * @p_hwfn: HW device data. 425 * @p_ptt: PTT required for register access. 426 * 427 * Return: Int. 428 */ 429 int qed_mcp_drain(struct qed_hwfn *p_hwfn, 430 struct qed_ptt *p_ptt); 431 432 /** 433 * qed_mcp_get_flash_size(): Get the flash size value. 434 * 435 * @p_hwfn: HW device data. 436 * @p_ptt: PTT required for register access. 437 * @p_flash_size: Flash size in bytes to be filled. 438 * 439 * Return: Int - 0 - Operation was successul. 440 */ 441 int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 442 struct qed_ptt *p_ptt, 443 u32 *p_flash_size); 444 445 /** 446 * qed_mcp_send_drv_version(): Send driver version to MFW. 447 * 448 * @p_hwfn: HW device data. 449 * @p_ptt: PTT required for register access. 450 * @p_ver: Version value. 451 * 452 * Return: Int - 0 - Operation was successul. 453 */ 454 int 455 qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 456 struct qed_ptt *p_ptt, 457 struct qed_mcp_drv_version *p_ver); 458 459 /** 460 * qed_get_process_kill_counter(): Read the MFW process kill counter. 461 * 462 * @p_hwfn: HW device data. 463 * @p_ptt: PTT required for register access. 464 * 465 * Return: u32. 466 */ 467 u32 qed_get_process_kill_counter(struct qed_hwfn *p_hwfn, 468 struct qed_ptt *p_ptt); 469 470 /** 471 * qed_start_recovery_process(): Trigger a recovery process. 472 * 473 * @p_hwfn: HW device data. 474 * @p_ptt: PTT required for register access. 475 * 476 * Return: Int. 477 */ 478 int qed_start_recovery_process(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 479 480 /** 481 * qed_recovery_prolog(): A recovery handler must call this function 482 * as its first step. 483 * It is assumed that the handler is not run from 484 * an interrupt context. 485 * 486 * @cdev: Qed dev pointer. 487 * 488 * Return: int. 489 */ 490 int qed_recovery_prolog(struct qed_dev *cdev); 491 492 /** 493 * qed_mcp_ov_update_current_config(): Notify MFW about the change in base 494 * device properties 495 * 496 * @p_hwfn: HW device data. 497 * @p_ptt: P_ptt. 498 * @client: Qed client type. 499 * 500 * Return: Int - 0 - Operation was successul. 501 */ 502 int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 503 struct qed_ptt *p_ptt, 504 enum qed_ov_client client); 505 506 /** 507 * qed_mcp_ov_update_driver_state(): Notify MFW about the driver state. 508 * 509 * @p_hwfn: HW device data. 510 * @p_ptt: P_ptt. 511 * @drv_state: Driver state. 512 * 513 * Return: Int - 0 - Operation was successul. 514 */ 515 int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 516 struct qed_ptt *p_ptt, 517 enum qed_ov_driver_state drv_state); 518 519 /** 520 * qed_mcp_ov_update_mtu(): Send MTU size to MFW. 521 * 522 * @p_hwfn: HW device data. 523 * @p_ptt: P_ptt. 524 * @mtu: MTU size. 525 * 526 * Return: Int - 0 - Operation was successul. 527 */ 528 int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 529 struct qed_ptt *p_ptt, u16 mtu); 530 531 /** 532 * qed_mcp_ov_update_mac(): Send MAC address to MFW. 533 * 534 * @p_hwfn: HW device data. 535 * @p_ptt: P_ptt. 536 * @mac: MAC address. 537 * 538 * Return: Int - 0 - Operation was successul. 539 */ 540 int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 541 struct qed_ptt *p_ptt, const u8 *mac); 542 543 /** 544 * qed_mcp_ov_update_wol(): Send WOL mode to MFW. 545 * 546 * @p_hwfn: HW device data. 547 * @p_ptt: P_ptt. 548 * @wol: WOL mode. 549 * 550 * Return: Int - 0 - Operation was successul. 551 */ 552 int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 553 struct qed_ptt *p_ptt, 554 enum qed_ov_wol wol); 555 556 /** 557 * qed_mcp_set_led(): Set LED status. 558 * 559 * @p_hwfn: HW device data. 560 * @p_ptt: P_ptt. 561 * @mode: LED mode. 562 * 563 * Return: Int - 0 - Operation was successul. 564 */ 565 int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 566 struct qed_ptt *p_ptt, 567 enum qed_led_mode mode); 568 569 /** 570 * qed_mcp_nvm_read(): Read from NVM. 571 * 572 * @cdev: Qed dev pointer. 573 * @addr: NVM offset. 574 * @p_buf: NVM read buffer. 575 * @len: Buffer len. 576 * 577 * Return: Int - 0 - Operation was successul. 578 */ 579 int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len); 580 581 /** 582 * qed_mcp_nvm_write(): Write to NVM. 583 * 584 * @cdev: Qed dev pointer. 585 * @addr: NVM offset. 586 * @cmd: NVM command. 587 * @p_buf: NVM write buffer. 588 * @len: Buffer len. 589 * 590 * Return: Int - 0 - Operation was successul. 591 */ 592 int qed_mcp_nvm_write(struct qed_dev *cdev, 593 u32 cmd, u32 addr, u8 *p_buf, u32 len); 594 595 /** 596 * qed_mcp_nvm_resp(): Check latest response. 597 * 598 * @cdev: Qed dev pointer. 599 * @p_buf: NVM write buffer. 600 * 601 * Return: Int - 0 - Operation was successul. 602 */ 603 int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf); 604 605 struct qed_nvm_image_att { 606 u32 start_addr; 607 u32 length; 608 }; 609 610 /** 611 * qed_mcp_get_nvm_image_att(): Allows reading a whole nvram image. 612 * 613 * @p_hwfn: HW device data. 614 * @image_id: Image to get attributes for. 615 * @p_image_att: Image attributes structure into which to fill data. 616 * 617 * Return: Int - 0 - Operation was successul. 618 */ 619 int 620 qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn, 621 enum qed_nvm_images image_id, 622 struct qed_nvm_image_att *p_image_att); 623 624 /** 625 * qed_mcp_get_nvm_image(): Allows reading a whole nvram image. 626 * 627 * @p_hwfn: HW device data. 628 * @image_id: image requested for reading. 629 * @p_buffer: allocated buffer into which to fill data. 630 * @buffer_len: length of the allocated buffer. 631 * 632 * Return: 0 if p_buffer now contains the nvram image. 633 */ 634 int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn, 635 enum qed_nvm_images image_id, 636 u8 *p_buffer, u32 buffer_len); 637 638 /** 639 * qed_mcp_bist_register_test(): Bist register test. 640 * 641 * @p_hwfn: HW device data. 642 * @p_ptt: PTT required for register access. 643 * 644 * Return: Int - 0 - Operation was successul. 645 */ 646 int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, 647 struct qed_ptt *p_ptt); 648 649 /** 650 * qed_mcp_bist_clock_test(): Bist clock test. 651 * 652 * @p_hwfn: HW device data. 653 * @p_ptt: PTT required for register access. 654 * 655 * Return: Int - 0 - Operation was successul. 656 */ 657 int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, 658 struct qed_ptt *p_ptt); 659 660 /** 661 * qed_mcp_bist_nvm_get_num_images(): Bist nvm test - get number of images. 662 * 663 * @p_hwfn: HW device data. 664 * @p_ptt: PTT required for register access. 665 * @num_images: number of images if operation was 666 * successful. 0 if not. 667 * 668 * Return: Int - 0 - Operation was successul. 669 */ 670 int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn, 671 struct qed_ptt *p_ptt, 672 u32 *num_images); 673 674 /** 675 * qed_mcp_bist_nvm_get_image_att(): Bist nvm test - get image attributes 676 * by index. 677 * 678 * @p_hwfn: HW device data. 679 * @p_ptt: PTT required for register access. 680 * @p_image_att: Attributes of image. 681 * @image_index: Index of image to get information for. 682 * 683 * Return: Int - 0 - Operation was successul. 684 */ 685 int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn, 686 struct qed_ptt *p_ptt, 687 struct bist_nvm_image_att *p_image_att, 688 u32 image_index); 689 690 /** 691 * qed_mfw_process_tlv_req(): Processes the TLV request from MFW i.e., 692 * get the required TLV info 693 * from the qed client and send it to the MFW. 694 * 695 * @p_hwfn: HW device data. 696 * @p_ptt: P_ptt. 697 * 698 * Return: 0 upon success. 699 */ 700 int qed_mfw_process_tlv_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 701 702 /** 703 * qed_mcp_send_raw_debug_data(): Send raw debug data to the MFW 704 * 705 * @p_hwfn: HW device data. 706 * @p_ptt: P_ptt. 707 * @p_buf: raw debug data buffer. 708 * @size: Buffer size. 709 * 710 * Return : Int. 711 */ 712 int 713 qed_mcp_send_raw_debug_data(struct qed_hwfn *p_hwfn, 714 struct qed_ptt *p_ptt, u8 *p_buf, u32 size); 715 716 /* Using hwfn number (and not pf_num) is required since in CMT mode, 717 * same pf_num may be used by two different hwfn 718 * TODO - this shouldn't really be in .h file, but until all fields 719 * required during hw-init will be placed in their correct place in shmem 720 * we need it in qed_dev.c [for readin the nvram reflection in shmem]. 721 */ 722 #define MCP_PF_ID_BY_REL(p_hwfn, rel_pfid) (QED_IS_BB((p_hwfn)->cdev) ? \ 723 ((rel_pfid) | \ 724 ((p_hwfn)->abs_pf_id & 1) << 3) : \ 725 rel_pfid) 726 #define MCP_PF_ID(p_hwfn) MCP_PF_ID_BY_REL(p_hwfn, (p_hwfn)->rel_pf_id) 727 728 struct qed_mcp_info { 729 /* List for mailbox commands which were sent and wait for a response */ 730 struct list_head cmd_list; 731 732 /* Spinlock used for protecting the access to the mailbox commands list 733 * and the sending of the commands. 734 */ 735 spinlock_t cmd_lock; 736 737 /* Flag to indicate whether sending a MFW mailbox command is blocked */ 738 bool b_block_cmd; 739 740 /* Spinlock used for syncing SW link-changes and link-changes 741 * originating from attention context. 742 */ 743 spinlock_t link_lock; 744 745 u32 public_base; 746 u32 drv_mb_addr; 747 u32 mfw_mb_addr; 748 u32 port_addr; 749 u16 drv_mb_seq; 750 u16 drv_pulse_seq; 751 struct qed_mcp_link_params link_input; 752 struct qed_mcp_link_state link_output; 753 struct qed_mcp_link_capabilities link_capabilities; 754 struct qed_mcp_function_info func_info; 755 u8 *mfw_mb_cur; 756 u8 *mfw_mb_shadow; 757 u16 mfw_mb_length; 758 u32 mcp_hist; 759 760 /* Capabilties negotiated with the MFW */ 761 u32 capabilities; 762 763 /* S/N for debug data mailbox commands */ 764 atomic_t dbg_data_seq; 765 }; 766 767 struct qed_mcp_mb_params { 768 u32 cmd; 769 u32 param; 770 void *p_data_src; 771 void *p_data_dst; 772 u8 data_src_size; 773 u8 data_dst_size; 774 u32 mcp_resp; 775 u32 mcp_param; 776 u32 flags; 777 #define QED_MB_FLAG_CAN_SLEEP (0x1 << 0) 778 #define QED_MB_FLAG_AVOID_BLOCK (0x1 << 1) 779 #define QED_MB_FLAGS_IS_SET(params, flag) \ 780 ({ typeof(params) __params = (params); \ 781 (__params && (__params->flags & QED_MB_FLAG_ ## flag)); }) 782 }; 783 784 struct qed_drv_tlv_hdr { 785 u8 tlv_type; 786 u8 tlv_length; /* In dwords - not including this header */ 787 u8 tlv_reserved; 788 #define QED_DRV_TLV_FLAGS_CHANGED 0x01 789 u8 tlv_flags; 790 }; 791 792 /** 793 * qed_mcp_is_ext_speed_supported() - Check if management firmware supports 794 * extended speeds. 795 * @p_hwfn: HW device data. 796 * 797 * Return: true if supported, false otherwise. 798 */ 799 static inline bool 800 qed_mcp_is_ext_speed_supported(const struct qed_hwfn *p_hwfn) 801 { 802 return !!(p_hwfn->mcp_info->capabilities & 803 FW_MB_PARAM_FEATURE_SUPPORT_EXT_SPEED_FEC_CONTROL); 804 } 805 806 /** 807 * qed_mcp_cmd_init(): Initialize the interface with the MCP. 808 * 809 * @p_hwfn: HW device data. 810 * @p_ptt: PTT required for register access. 811 * 812 * Return: Int. 813 */ 814 int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, 815 struct qed_ptt *p_ptt); 816 817 /** 818 * qed_mcp_cmd_port_init(): Initialize the port interface with the MCP 819 * 820 * @p_hwfn: HW device data. 821 * @p_ptt: P_ptt. 822 * 823 * Return: Void. 824 * 825 * Can only be called after `num_ports_in_engines' is set 826 */ 827 void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, 828 struct qed_ptt *p_ptt); 829 /** 830 * qed_mcp_free(): Releases resources allocated during the init process. 831 * 832 * @p_hwfn: HW function. 833 * 834 * Return: Int. 835 */ 836 837 int qed_mcp_free(struct qed_hwfn *p_hwfn); 838 839 /** 840 * qed_mcp_handle_events(): This function is called from the DPC context. 841 * After pointing PTT to the mfw mb, check for events sent by 842 * the MCP to the driver and ack them. In case a critical event 843 * detected, it will be handled here, otherwise the work will be 844 * queued to a sleepable work-queue. 845 * 846 * @p_hwfn: HW function. 847 * @p_ptt: PTT required for register access. 848 * 849 * Return: Int - 0 - Operation was successul. 850 */ 851 int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 852 struct qed_ptt *p_ptt); 853 854 enum qed_drv_role { 855 QED_DRV_ROLE_OS, 856 QED_DRV_ROLE_KDUMP, 857 }; 858 859 struct qed_load_req_params { 860 /* Input params */ 861 enum qed_drv_role drv_role; 862 u8 timeout_val; 863 bool avoid_eng_reset; 864 enum qed_override_force_load override_force_load; 865 866 /* Output params */ 867 u32 load_code; 868 }; 869 870 /** 871 * qed_mcp_load_req(): Sends a LOAD_REQ to the MFW, and in case the 872 * operation succeeds, returns whether this PF is 873 * the first on the engine/port or function. 874 * 875 * @p_hwfn: HW device data. 876 * @p_ptt: P_ptt. 877 * @p_params: Params. 878 * 879 * Return: Int - 0 - Operation was successul. 880 */ 881 int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 882 struct qed_ptt *p_ptt, 883 struct qed_load_req_params *p_params); 884 885 /** 886 * qed_mcp_load_done(): Sends a LOAD_DONE message to the MFW. 887 * 888 * @p_hwfn: HW device data. 889 * @p_ptt: P_ptt. 890 * 891 * Return: Int - 0 - Operation was successul. 892 */ 893 int qed_mcp_load_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 894 895 /** 896 * qed_mcp_unload_req(): Sends a UNLOAD_REQ message to the MFW. 897 * 898 * @p_hwfn: HW device data. 899 * @p_ptt: P_ptt. 900 * 901 * Return: Int - 0 - Operation was successul. 902 */ 903 int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 904 905 /** 906 * qed_mcp_unload_done(): Sends a UNLOAD_DONE message to the MFW 907 * 908 * @p_hwfn: HW device data. 909 * @p_ptt: P_ptt. 910 * 911 * Return: Int - 0 - Operation was successul. 912 */ 913 int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 914 915 /** 916 * qed_mcp_read_mb(): Read the MFW mailbox into Current buffer. 917 * 918 * @p_hwfn: HW device data. 919 * @p_ptt: P_ptt. 920 * 921 * Return: Void. 922 */ 923 void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, 924 struct qed_ptt *p_ptt); 925 926 /** 927 * qed_mcp_ack_vf_flr(): Ack to mfw that driver finished FLR process for VFs 928 * 929 * @p_hwfn: HW device data. 930 * @p_ptt: P_ptt. 931 * @vfs_to_ack: bit mask of all engine VFs for which the PF acks. 932 * 933 * Return: Int - 0 - Operation was successul. 934 */ 935 int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 936 struct qed_ptt *p_ptt, u32 *vfs_to_ack); 937 938 /** 939 * qed_mcp_fill_shmem_func_info(): Calls during init to read shmem of 940 * all function-related info. 941 * 942 * @p_hwfn: HW device data. 943 * @p_ptt: P_ptt. 944 * 945 * Return: 0 upon success. 946 */ 947 int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 948 struct qed_ptt *p_ptt); 949 950 /** 951 * qed_mcp_reset(): Reset the MCP using mailbox command. 952 * 953 * @p_hwfn: HW device data. 954 * @p_ptt: P_ptt. 955 * 956 * Return: 0 upon success. 957 */ 958 int qed_mcp_reset(struct qed_hwfn *p_hwfn, 959 struct qed_ptt *p_ptt); 960 961 /** 962 * qed_mcp_nvm_rd_cmd(): Sends an NVM read command request to the MFW to get 963 * a buffer. 964 * 965 * @p_hwfn: HW device data. 966 * @p_ptt: P_ptt. 967 * @cmd: (Command) DRV_MSG_CODE_NVM_GET_FILE_DATA or 968 * DRV_MSG_CODE_NVM_READ_NVRAM commands. 969 * @param: [0:23] - Offset [24:31] - Size. 970 * @o_mcp_resp: MCP response. 971 * @o_mcp_param: MCP response param. 972 * @o_txn_size: Buffer size output. 973 * @o_buf: Pointer to the buffer returned by the MFW. 974 * @b_can_sleep: Can sleep. 975 * 976 * Return: 0 upon success. 977 */ 978 int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 979 struct qed_ptt *p_ptt, 980 u32 cmd, 981 u32 param, 982 u32 *o_mcp_resp, 983 u32 *o_mcp_param, 984 u32 *o_txn_size, u32 *o_buf, bool b_can_sleep); 985 986 /** 987 * qed_mcp_phy_sfp_read(): Read from sfp. 988 * 989 * @p_hwfn: HW device data. 990 * @p_ptt: PTT required for register access. 991 * @port: transceiver port. 992 * @addr: I2C address. 993 * @offset: offset in sfp. 994 * @len: buffer length. 995 * @p_buf: buffer to read into. 996 * 997 * Return: Int - 0 - Operation was successul. 998 */ 999 int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 1000 u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf); 1001 1002 /** 1003 * qed_mcp_is_init(): indicates whether the MFW objects [under mcp_info] 1004 * are accessible 1005 * 1006 * @p_hwfn: HW device data. 1007 * 1008 * Return: true if MFW is running and mcp_info is initialized. 1009 */ 1010 bool qed_mcp_is_init(struct qed_hwfn *p_hwfn); 1011 1012 /** 1013 * qed_mcp_config_vf_msix(): Request MFW to configure MSI-X for a VF. 1014 * 1015 * @p_hwfn: HW device data. 1016 * @p_ptt: P_ptt. 1017 * @vf_id: absolute inside engine. 1018 * @num: number of entries to request. 1019 * 1020 * Return: Int. 1021 */ 1022 int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 1023 struct qed_ptt *p_ptt, u8 vf_id, u8 num); 1024 1025 /** 1026 * qed_mcp_halt(): Halt the MCP. 1027 * 1028 * @p_hwfn: HW device data. 1029 * @p_ptt: P_ptt. 1030 * 1031 * Return: 0 upon success. 1032 */ 1033 int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 1034 1035 /** 1036 * qed_mcp_resume: Wake up the MCP. 1037 * 1038 * @p_hwfn: HW device data. 1039 * @p_ptt: P_ptt. 1040 * 1041 * Return: 0 upon success. 1042 */ 1043 int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 1044 1045 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw); 1046 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw); 1047 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, 1048 struct qed_ptt *p_ptt, 1049 struct qed_mcp_link_state *p_link, 1050 u8 max_bw); 1051 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn, 1052 struct qed_ptt *p_ptt, 1053 struct qed_mcp_link_state *p_link, 1054 u8 min_bw); 1055 1056 int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 1057 struct qed_ptt *p_ptt, u32 mask_parities); 1058 1059 /* qed_mcp_mdump_get_retain(): Gets the mdump retained data from the MFW. 1060 * 1061 * @p_hwfn: HW device data. 1062 * @p_ptt: P_ptt. 1063 * @p_mdump_retain: mdump retain. 1064 * 1065 * Return: Int - 0 - Operation was successul. 1066 */ 1067 int 1068 qed_mcp_mdump_get_retain(struct qed_hwfn *p_hwfn, 1069 struct qed_ptt *p_ptt, 1070 struct mdump_retain_data_stc *p_mdump_retain); 1071 1072 /** 1073 * qed_mcp_set_resc_max_val(): Sets the MFW's max value for the given resource. 1074 * 1075 * @p_hwfn: HW device data. 1076 * @p_ptt: P_ptt. 1077 * @res_id: RES ID. 1078 * @resc_max_val: Resec max val. 1079 * @p_mcp_resp: MCP Resp 1080 * 1081 * Return: Int - 0 - Operation was successul. 1082 */ 1083 int 1084 qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn, 1085 struct qed_ptt *p_ptt, 1086 enum qed_resources res_id, 1087 u32 resc_max_val, u32 *p_mcp_resp); 1088 1089 /** 1090 * qed_mcp_get_resc_info(): Gets the MFW allocation info for the given 1091 * resource. 1092 * 1093 * @p_hwfn: HW device data. 1094 * @p_ptt: P_ptt. 1095 * @res_id: Res ID. 1096 * @p_mcp_resp: MCP resp. 1097 * @p_resc_num: Resc num. 1098 * @p_resc_start: Resc start. 1099 * 1100 * Return: Int - 0 - Operation was successul. 1101 */ 1102 int 1103 qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, 1104 struct qed_ptt *p_ptt, 1105 enum qed_resources res_id, 1106 u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start); 1107 1108 /** 1109 * qed_mcp_ov_update_eswitch(): Send eswitch mode to MFW. 1110 * 1111 * @p_hwfn: HW device data. 1112 * @p_ptt: P_ptt. 1113 * @eswitch: eswitch mode. 1114 * 1115 * Return: Int - 0 - Operation was successul. 1116 */ 1117 int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 1118 struct qed_ptt *p_ptt, 1119 enum qed_ov_eswitch eswitch); 1120 1121 #define QED_MCP_RESC_LOCK_MIN_VAL RESOURCE_DUMP 1122 #define QED_MCP_RESC_LOCK_MAX_VAL 31 1123 1124 enum qed_resc_lock { 1125 QED_RESC_LOCK_DBG_DUMP = QED_MCP_RESC_LOCK_MIN_VAL, 1126 QED_RESC_LOCK_PTP_PORT0, 1127 QED_RESC_LOCK_PTP_PORT1, 1128 QED_RESC_LOCK_PTP_PORT2, 1129 QED_RESC_LOCK_PTP_PORT3, 1130 QED_RESC_LOCK_RESC_ALLOC = QED_MCP_RESC_LOCK_MAX_VAL, 1131 QED_RESC_LOCK_RESC_INVALID 1132 }; 1133 1134 /** 1135 * qed_mcp_initiate_pf_flr(): Initiates PF FLR. 1136 * 1137 * @p_hwfn: HW device data. 1138 * @p_ptt: P_ptt. 1139 * 1140 * Return: Int - 0 - Operation was successul. 1141 */ 1142 int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 1143 struct qed_resc_lock_params { 1144 /* Resource number [valid values are 0..31] */ 1145 u8 resource; 1146 1147 /* Lock timeout value in seconds [default, none or 1..254] */ 1148 u8 timeout; 1149 #define QED_MCP_RESC_LOCK_TO_DEFAULT 0 1150 #define QED_MCP_RESC_LOCK_TO_NONE 255 1151 1152 /* Number of times to retry locking */ 1153 u8 retry_num; 1154 #define QED_MCP_RESC_LOCK_RETRY_CNT_DFLT 10 1155 1156 /* The interval in usec between retries */ 1157 u16 retry_interval; 1158 #define QED_MCP_RESC_LOCK_RETRY_VAL_DFLT 10000 1159 1160 /* Use sleep or delay between retries */ 1161 bool sleep_b4_retry; 1162 1163 /* Will be set as true if the resource is free and granted */ 1164 bool b_granted; 1165 1166 /* Will be filled with the resource owner. 1167 * [0..15 = PF0-15, 16 = MFW] 1168 */ 1169 u8 owner; 1170 }; 1171 1172 /** 1173 * qed_mcp_resc_lock(): Acquires MFW generic resource lock. 1174 * 1175 * @p_hwfn: HW device data. 1176 * @p_ptt: P_ptt. 1177 * @p_params: Params. 1178 * 1179 * Return: Int - 0 - Operation was successul. 1180 */ 1181 int 1182 qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 1183 struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params); 1184 1185 struct qed_resc_unlock_params { 1186 /* Resource number [valid values are 0..31] */ 1187 u8 resource; 1188 1189 /* Allow to release a resource even if belongs to another PF */ 1190 bool b_force; 1191 1192 /* Will be set as true if the resource is released */ 1193 bool b_released; 1194 }; 1195 1196 /** 1197 * qed_mcp_resc_unlock(): Releases MFW generic resource lock. 1198 * 1199 * @p_hwfn: HW device data. 1200 * @p_ptt: P_ptt. 1201 * @p_params: Params. 1202 * 1203 * Return: Int - 0 - Operation was successul. 1204 */ 1205 int 1206 qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn, 1207 struct qed_ptt *p_ptt, 1208 struct qed_resc_unlock_params *p_params); 1209 1210 /** 1211 * qed_mcp_resc_lock_default_init(): Default initialization for 1212 * lock/unlock resource structs. 1213 * 1214 * @p_lock: lock params struct to be initialized; Can be NULL. 1215 * @p_unlock: unlock params struct to be initialized; Can be NULL. 1216 * @resource: the requested resource. 1217 * @b_is_permanent: disable retries & aging when set. 1218 * 1219 * Return: Void. 1220 */ 1221 void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock, 1222 struct qed_resc_unlock_params *p_unlock, 1223 enum qed_resc_lock 1224 resource, bool b_is_permanent); 1225 1226 /** 1227 * qed_mcp_is_smart_an_supported(): Return whether management firmware 1228 * support smart AN 1229 * 1230 * @p_hwfn: HW device data. 1231 * 1232 * Return: bool true if feature is supported. 1233 */ 1234 bool qed_mcp_is_smart_an_supported(struct qed_hwfn *p_hwfn); 1235 1236 /** 1237 * qed_mcp_get_capabilities(): Learn of supported MFW features; 1238 * To be done during early init. 1239 * 1240 * @p_hwfn: HW device data. 1241 * @p_ptt: P_ptt. 1242 * 1243 * Return: Int. 1244 */ 1245 int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 1246 1247 /** 1248 * qed_mcp_set_capabilities(): Inform MFW of set of features supported 1249 * by driver. Should be done inside the content 1250 * of the LOAD_REQ. 1251 * 1252 * @p_hwfn: HW device data. 1253 * @p_ptt: P_ptt. 1254 * 1255 * Return: Int. 1256 */ 1257 int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 1258 1259 /** 1260 * qed_mcp_read_ufp_config(): Read ufp config from the shared memory. 1261 * 1262 * @p_hwfn: HW device data. 1263 * @p_ptt: P_ptt. 1264 * 1265 * Return: Void. 1266 */ 1267 void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 1268 1269 /** 1270 * qed_mcp_nvm_info_populate(): Populate the nvm info shadow in the given 1271 * hardware function. 1272 * 1273 * @p_hwfn: HW device data. 1274 * 1275 * Return: Int. 1276 */ 1277 int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn); 1278 1279 /** 1280 * qed_mcp_nvm_info_free(): Delete nvm info shadow in the given 1281 * hardware function. 1282 * 1283 * @p_hwfn: HW device data. 1284 * 1285 * Return: Void. 1286 */ 1287 void qed_mcp_nvm_info_free(struct qed_hwfn *p_hwfn); 1288 1289 /** 1290 * qed_mcp_get_engine_config(): Get the engine affinity configuration. 1291 * 1292 * @p_hwfn: HW device data. 1293 * @p_ptt: P_ptt. 1294 * 1295 * Return: Int. 1296 */ 1297 int qed_mcp_get_engine_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 1298 1299 /** 1300 * qed_mcp_get_ppfid_bitmap(): Get the PPFID bitmap. 1301 * 1302 * @p_hwfn: HW device data. 1303 * @p_ptt: P_ptt. 1304 * 1305 * Return: Int. 1306 */ 1307 int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 1308 1309 /** 1310 * qed_mcp_nvm_get_cfg(): Get NVM config attribute value. 1311 * 1312 * @p_hwfn: HW device data. 1313 * @p_ptt: P_ptt. 1314 * @option_id: Option ID. 1315 * @entity_id: Entity ID. 1316 * @flags: Flags. 1317 * @p_buf: Buf. 1318 * @p_len: Len. 1319 * 1320 * Return: Int. 1321 */ 1322 int qed_mcp_nvm_get_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 1323 u16 option_id, u8 entity_id, u16 flags, u8 *p_buf, 1324 u32 *p_len); 1325 1326 /** 1327 * qed_mcp_nvm_set_cfg(): Set NVM config attribute value. 1328 * 1329 * @p_hwfn: HW device data. 1330 * @p_ptt: P_ptt. 1331 * @option_id: Option ID. 1332 * @entity_id: Entity ID. 1333 * @flags: Flags. 1334 * @p_buf: Buf. 1335 * @len: Len. 1336 * 1337 * Return: Int. 1338 */ 1339 int qed_mcp_nvm_set_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 1340 u16 option_id, u8 entity_id, u16 flags, u8 *p_buf, 1341 u32 len); 1342 1343 /** 1344 * qed_mcp_is_esl_supported(): Return whether management firmware support ESL or not. 1345 * 1346 * @p_hwfn: hw function pointer 1347 * 1348 * Return: true if esl is supported, otherwise return false 1349 */ 1350 bool qed_mcp_is_esl_supported(struct qed_hwfn *p_hwfn); 1351 1352 /** 1353 * qed_mcp_get_esl_status(): Get enhanced system lockdown status 1354 * 1355 * @p_hwfn: hw function pointer 1356 * @p_ptt: ptt resource pointer 1357 * @active: ESL active status data pointer 1358 * 1359 * Return: 0 with esl status info on success, otherwise return error 1360 */ 1361 int qed_mcp_get_esl_status(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool *active); 1362 #endif 1363