1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #ifndef _QED_MCP_H 34fe56b9e6SYuval Mintz #define _QED_MCP_H 35fe56b9e6SYuval Mintz 36fe56b9e6SYuval Mintz #include <linux/types.h> 37fe56b9e6SYuval Mintz #include <linux/delay.h> 38fe56b9e6SYuval Mintz #include <linux/slab.h> 395529bad9STomer Tayar #include <linux/spinlock.h> 401e128c81SArun Easi #include <linux/qed/qed_fcoe_if.h> 41fe56b9e6SYuval Mintz #include "qed_hsi.h" 425d24bcf1STomer Tayar #include "qed_dev_api.h" 43fe56b9e6SYuval Mintz 44cc875c2eSYuval Mintz struct qed_mcp_link_speed_params { 45cc875c2eSYuval Mintz bool autoneg; 46cc875c2eSYuval Mintz u32 advertised_speeds; /* bitmask of DRV_SPEED_CAPABILITY */ 47cc875c2eSYuval Mintz u32 forced_speed; /* In Mb/s */ 48cc875c2eSYuval Mintz }; 49cc875c2eSYuval Mintz 50cc875c2eSYuval Mintz struct qed_mcp_link_pause_params { 51cc875c2eSYuval Mintz bool autoneg; 52cc875c2eSYuval Mintz bool forced_rx; 53cc875c2eSYuval Mintz bool forced_tx; 54cc875c2eSYuval Mintz }; 55cc875c2eSYuval Mintz 56645874e5SSudarsana Reddy Kalluru enum qed_mcp_eee_mode { 57645874e5SSudarsana Reddy Kalluru QED_MCP_EEE_DISABLED, 58645874e5SSudarsana Reddy Kalluru QED_MCP_EEE_ENABLED, 59645874e5SSudarsana Reddy Kalluru QED_MCP_EEE_UNSUPPORTED 60645874e5SSudarsana Reddy Kalluru }; 61645874e5SSudarsana Reddy Kalluru 62cc875c2eSYuval Mintz struct qed_mcp_link_params { 63cc875c2eSYuval Mintz struct qed_mcp_link_speed_params speed; 64cc875c2eSYuval Mintz struct qed_mcp_link_pause_params pause; 65cc875c2eSYuval Mintz u32 loopback_mode; 66645874e5SSudarsana Reddy Kalluru struct qed_link_eee_params eee; 67cc875c2eSYuval Mintz }; 68cc875c2eSYuval Mintz 69cc875c2eSYuval Mintz struct qed_mcp_link_capabilities { 70cc875c2eSYuval Mintz u32 speed_capabilities; 7134f9199cSsudarsana.kalluru@cavium.com bool default_speed_autoneg; 72645874e5SSudarsana Reddy Kalluru enum qed_mcp_eee_mode default_eee; 73645874e5SSudarsana Reddy Kalluru u32 eee_lpi_timer; 74645874e5SSudarsana Reddy Kalluru u8 eee_speed_caps; 75cc875c2eSYuval Mintz }; 76cc875c2eSYuval Mintz 77cc875c2eSYuval Mintz struct qed_mcp_link_state { 78cc875c2eSYuval Mintz bool link_up; 79cc875c2eSYuval Mintz 80a64b02d5SManish Chopra u32 min_pf_rate; 81a64b02d5SManish Chopra 824b01e519SManish Chopra /* Actual link speed in Mb/s */ 834b01e519SManish Chopra u32 line_speed; 844b01e519SManish Chopra 854b01e519SManish Chopra /* PF max speed in Mb/s, deduced from line_speed 864b01e519SManish Chopra * according to PF max bandwidth configuration. 874b01e519SManish Chopra */ 884b01e519SManish Chopra u32 speed; 89cc875c2eSYuval Mintz bool full_duplex; 90cc875c2eSYuval Mintz 91cc875c2eSYuval Mintz bool an; 92cc875c2eSYuval Mintz bool an_complete; 93cc875c2eSYuval Mintz bool parallel_detection; 94cc875c2eSYuval Mintz bool pfc_enabled; 95cc875c2eSYuval Mintz 96cc875c2eSYuval Mintz #define QED_LINK_PARTNER_SPEED_1G_HD BIT(0) 97cc875c2eSYuval Mintz #define QED_LINK_PARTNER_SPEED_1G_FD BIT(1) 98cc875c2eSYuval Mintz #define QED_LINK_PARTNER_SPEED_10G BIT(2) 99cc875c2eSYuval Mintz #define QED_LINK_PARTNER_SPEED_20G BIT(3) 100054c67d1SSudarsana Reddy Kalluru #define QED_LINK_PARTNER_SPEED_25G BIT(4) 101054c67d1SSudarsana Reddy Kalluru #define QED_LINK_PARTNER_SPEED_40G BIT(5) 102054c67d1SSudarsana Reddy Kalluru #define QED_LINK_PARTNER_SPEED_50G BIT(6) 103054c67d1SSudarsana Reddy Kalluru #define QED_LINK_PARTNER_SPEED_100G BIT(7) 104cc875c2eSYuval Mintz u32 partner_adv_speed; 105cc875c2eSYuval Mintz 106cc875c2eSYuval Mintz bool partner_tx_flow_ctrl_en; 107cc875c2eSYuval Mintz bool partner_rx_flow_ctrl_en; 108cc875c2eSYuval Mintz 109cc875c2eSYuval Mintz #define QED_LINK_PARTNER_SYMMETRIC_PAUSE (1) 110cc875c2eSYuval Mintz #define QED_LINK_PARTNER_ASYMMETRIC_PAUSE (2) 111cc875c2eSYuval Mintz #define QED_LINK_PARTNER_BOTH_PAUSE (3) 112cc875c2eSYuval Mintz u8 partner_adv_pause; 113cc875c2eSYuval Mintz 114cc875c2eSYuval Mintz bool sfp_tx_fault; 115645874e5SSudarsana Reddy Kalluru bool eee_active; 116645874e5SSudarsana Reddy Kalluru u8 eee_adv_caps; 117645874e5SSudarsana Reddy Kalluru u8 eee_lp_adv_caps; 118cc875c2eSYuval Mintz }; 119cc875c2eSYuval Mintz 120fe56b9e6SYuval Mintz struct qed_mcp_function_info { 121fe56b9e6SYuval Mintz u8 pause_on_host; 122fe56b9e6SYuval Mintz 123fe56b9e6SYuval Mintz enum qed_pci_personality protocol; 124fe56b9e6SYuval Mintz 125fe56b9e6SYuval Mintz u8 bandwidth_min; 126fe56b9e6SYuval Mintz u8 bandwidth_max; 127fe56b9e6SYuval Mintz 128fe56b9e6SYuval Mintz u8 mac[ETH_ALEN]; 129fe56b9e6SYuval Mintz 130fe56b9e6SYuval Mintz u64 wwn_port; 131fe56b9e6SYuval Mintz u64 wwn_node; 132fe56b9e6SYuval Mintz 133fe56b9e6SYuval Mintz #define QED_MCP_VLAN_UNSET (0xffff) 134fe56b9e6SYuval Mintz u16 ovlan; 1350fefbfbaSSudarsana Kalluru 1360fefbfbaSSudarsana Kalluru u16 mtu; 137fe56b9e6SYuval Mintz }; 138fe56b9e6SYuval Mintz 139fe56b9e6SYuval Mintz struct qed_mcp_nvm_common { 140fe56b9e6SYuval Mintz u32 offset; 141fe56b9e6SYuval Mintz u32 param; 142fe56b9e6SYuval Mintz u32 resp; 143fe56b9e6SYuval Mintz u32 cmd; 144fe56b9e6SYuval Mintz }; 145fe56b9e6SYuval Mintz 146fe56b9e6SYuval Mintz struct qed_mcp_drv_version { 147fe56b9e6SYuval Mintz u32 version; 148fe56b9e6SYuval Mintz u8 name[MCP_DRV_VER_STR_SIZE - 4]; 149fe56b9e6SYuval Mintz }; 150fe56b9e6SYuval Mintz 1516c754246SSudarsana Reddy Kalluru struct qed_mcp_lan_stats { 1526c754246SSudarsana Reddy Kalluru u64 ucast_rx_pkts; 1536c754246SSudarsana Reddy Kalluru u64 ucast_tx_pkts; 1546c754246SSudarsana Reddy Kalluru u32 fcs_err; 1556c754246SSudarsana Reddy Kalluru }; 1566c754246SSudarsana Reddy Kalluru 1576c754246SSudarsana Reddy Kalluru struct qed_mcp_fcoe_stats { 1586c754246SSudarsana Reddy Kalluru u64 rx_pkts; 1596c754246SSudarsana Reddy Kalluru u64 tx_pkts; 1606c754246SSudarsana Reddy Kalluru u32 fcs_err; 1616c754246SSudarsana Reddy Kalluru u32 login_failure; 1626c754246SSudarsana Reddy Kalluru }; 1636c754246SSudarsana Reddy Kalluru 1646c754246SSudarsana Reddy Kalluru struct qed_mcp_iscsi_stats { 1656c754246SSudarsana Reddy Kalluru u64 rx_pdus; 1666c754246SSudarsana Reddy Kalluru u64 tx_pdus; 1676c754246SSudarsana Reddy Kalluru u64 rx_bytes; 1686c754246SSudarsana Reddy Kalluru u64 tx_bytes; 1696c754246SSudarsana Reddy Kalluru }; 1706c754246SSudarsana Reddy Kalluru 1716c754246SSudarsana Reddy Kalluru struct qed_mcp_rdma_stats { 1726c754246SSudarsana Reddy Kalluru u64 rx_pkts; 1736c754246SSudarsana Reddy Kalluru u64 tx_pkts; 1746c754246SSudarsana Reddy Kalluru u64 rx_bytes; 1756c754246SSudarsana Reddy Kalluru u64 tx_byts; 1766c754246SSudarsana Reddy Kalluru }; 1776c754246SSudarsana Reddy Kalluru 1786c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type { 1796c754246SSudarsana Reddy Kalluru QED_MCP_LAN_STATS, 1806c754246SSudarsana Reddy Kalluru QED_MCP_FCOE_STATS, 1816c754246SSudarsana Reddy Kalluru QED_MCP_ISCSI_STATS, 1826c754246SSudarsana Reddy Kalluru QED_MCP_RDMA_STATS 1836c754246SSudarsana Reddy Kalluru }; 1846c754246SSudarsana Reddy Kalluru 1856c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats { 1866c754246SSudarsana Reddy Kalluru struct qed_mcp_lan_stats lan_stats; 1876c754246SSudarsana Reddy Kalluru struct qed_mcp_fcoe_stats fcoe_stats; 1886c754246SSudarsana Reddy Kalluru struct qed_mcp_iscsi_stats iscsi_stats; 1896c754246SSudarsana Reddy Kalluru struct qed_mcp_rdma_stats rdma_stats; 1906c754246SSudarsana Reddy Kalluru }; 1916c754246SSudarsana Reddy Kalluru 1920fefbfbaSSudarsana Kalluru enum qed_ov_eswitch { 1930fefbfbaSSudarsana Kalluru QED_OV_ESWITCH_NONE, 1940fefbfbaSSudarsana Kalluru QED_OV_ESWITCH_VEB, 1950fefbfbaSSudarsana Kalluru QED_OV_ESWITCH_VEPA 1960fefbfbaSSudarsana Kalluru }; 1970fefbfbaSSudarsana Kalluru 1980fefbfbaSSudarsana Kalluru enum qed_ov_client { 1990fefbfbaSSudarsana Kalluru QED_OV_CLIENT_DRV, 2000fefbfbaSSudarsana Kalluru QED_OV_CLIENT_USER, 2010fefbfbaSSudarsana Kalluru QED_OV_CLIENT_VENDOR_SPEC 2020fefbfbaSSudarsana Kalluru }; 2030fefbfbaSSudarsana Kalluru 2040fefbfbaSSudarsana Kalluru enum qed_ov_driver_state { 2050fefbfbaSSudarsana Kalluru QED_OV_DRIVER_STATE_NOT_LOADED, 2060fefbfbaSSudarsana Kalluru QED_OV_DRIVER_STATE_DISABLED, 2070fefbfbaSSudarsana Kalluru QED_OV_DRIVER_STATE_ACTIVE 2080fefbfbaSSudarsana Kalluru }; 2090fefbfbaSSudarsana Kalluru 2100fefbfbaSSudarsana Kalluru enum qed_ov_wol { 2110fefbfbaSSudarsana Kalluru QED_OV_WOL_DEFAULT, 2120fefbfbaSSudarsana Kalluru QED_OV_WOL_DISABLED, 2130fefbfbaSSudarsana Kalluru QED_OV_WOL_ENABLED 2140fefbfbaSSudarsana Kalluru }; 2150fefbfbaSSudarsana Kalluru 2162528c389SSudarsana Reddy Kalluru enum qed_mfw_tlv_type { 2172528c389SSudarsana Reddy Kalluru QED_MFW_TLV_GENERIC = 0x1, /* Core driver TLVs */ 2182528c389SSudarsana Reddy Kalluru QED_MFW_TLV_ETH = 0x2, /* L2 driver TLVs */ 219f240b688SSudarsana Reddy Kalluru QED_MFW_TLV_FCOE = 0x4, /* FCoE protocol TLVs */ 22077a509e4SSudarsana Reddy Kalluru QED_MFW_TLV_ISCSI = 0x8, /* SCSI protocol TLVs */ 22177a509e4SSudarsana Reddy Kalluru QED_MFW_TLV_MAX = 0x16, 2222528c389SSudarsana Reddy Kalluru }; 2232528c389SSudarsana Reddy Kalluru 2242528c389SSudarsana Reddy Kalluru struct qed_mfw_tlv_generic { 2252528c389SSudarsana Reddy Kalluru #define QED_MFW_TLV_FLAGS_SIZE 2 2262528c389SSudarsana Reddy Kalluru struct { 2272528c389SSudarsana Reddy Kalluru u8 ipv4_csum_offload; 2282528c389SSudarsana Reddy Kalluru u8 lso_supported; 2292528c389SSudarsana Reddy Kalluru bool b_set; 2302528c389SSudarsana Reddy Kalluru } flags; 2312528c389SSudarsana Reddy Kalluru 2322528c389SSudarsana Reddy Kalluru #define QED_MFW_TLV_MAC_COUNT 3 2332528c389SSudarsana Reddy Kalluru /* First entry for primary MAC, 2 secondary MACs possible */ 2342528c389SSudarsana Reddy Kalluru u8 mac[QED_MFW_TLV_MAC_COUNT][6]; 2352528c389SSudarsana Reddy Kalluru bool mac_set[QED_MFW_TLV_MAC_COUNT]; 2362528c389SSudarsana Reddy Kalluru 2372528c389SSudarsana Reddy Kalluru u64 rx_frames; 2382528c389SSudarsana Reddy Kalluru bool rx_frames_set; 2392528c389SSudarsana Reddy Kalluru u64 rx_bytes; 2402528c389SSudarsana Reddy Kalluru bool rx_bytes_set; 2412528c389SSudarsana Reddy Kalluru u64 tx_frames; 2422528c389SSudarsana Reddy Kalluru bool tx_frames_set; 2432528c389SSudarsana Reddy Kalluru u64 tx_bytes; 2442528c389SSudarsana Reddy Kalluru bool tx_bytes_set; 2452528c389SSudarsana Reddy Kalluru }; 2462528c389SSudarsana Reddy Kalluru 2472528c389SSudarsana Reddy Kalluru union qed_mfw_tlv_data { 2482528c389SSudarsana Reddy Kalluru struct qed_mfw_tlv_generic generic; 2492528c389SSudarsana Reddy Kalluru struct qed_mfw_tlv_eth eth; 250f240b688SSudarsana Reddy Kalluru struct qed_mfw_tlv_fcoe fcoe; 25177a509e4SSudarsana Reddy Kalluru struct qed_mfw_tlv_iscsi iscsi; 2522528c389SSudarsana Reddy Kalluru }; 2532528c389SSudarsana Reddy Kalluru 254fe56b9e6SYuval Mintz /** 255cc875c2eSYuval Mintz * @brief - returns the link params of the hw function 256cc875c2eSYuval Mintz * 257cc875c2eSYuval Mintz * @param p_hwfn 258cc875c2eSYuval Mintz * 259cc875c2eSYuval Mintz * @returns pointer to link params 260cc875c2eSYuval Mintz */ 261cc875c2eSYuval Mintz struct qed_mcp_link_params *qed_mcp_get_link_params(struct qed_hwfn *); 262cc875c2eSYuval Mintz 263cc875c2eSYuval Mintz /** 264cc875c2eSYuval Mintz * @brief - return the link state of the hw function 265cc875c2eSYuval Mintz * 266cc875c2eSYuval Mintz * @param p_hwfn 267cc875c2eSYuval Mintz * 268cc875c2eSYuval Mintz * @returns pointer to link state 269cc875c2eSYuval Mintz */ 270cc875c2eSYuval Mintz struct qed_mcp_link_state *qed_mcp_get_link_state(struct qed_hwfn *); 271cc875c2eSYuval Mintz 272cc875c2eSYuval Mintz /** 273cc875c2eSYuval Mintz * @brief - return the link capabilities of the hw function 274cc875c2eSYuval Mintz * 275cc875c2eSYuval Mintz * @param p_hwfn 276cc875c2eSYuval Mintz * 277cc875c2eSYuval Mintz * @returns pointer to link capabilities 278cc875c2eSYuval Mintz */ 279cc875c2eSYuval Mintz struct qed_mcp_link_capabilities 280cc875c2eSYuval Mintz *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn); 281cc875c2eSYuval Mintz 282cc875c2eSYuval Mintz /** 283cc875c2eSYuval Mintz * @brief Request the MFW to set the the link according to 'link_input'. 284cc875c2eSYuval Mintz * 285cc875c2eSYuval Mintz * @param p_hwfn 286cc875c2eSYuval Mintz * @param p_ptt 287cc875c2eSYuval Mintz * @param b_up - raise link if `true'. Reset link if `false'. 288cc875c2eSYuval Mintz * 289cc875c2eSYuval Mintz * @return int 290cc875c2eSYuval Mintz */ 291cc875c2eSYuval Mintz int qed_mcp_set_link(struct qed_hwfn *p_hwfn, 292cc875c2eSYuval Mintz struct qed_ptt *p_ptt, 293cc875c2eSYuval Mintz bool b_up); 294cc875c2eSYuval Mintz 295cc875c2eSYuval Mintz /** 296fe56b9e6SYuval Mintz * @brief Get the management firmware version value 297fe56b9e6SYuval Mintz * 2981408cc1fSYuval Mintz * @param p_hwfn 2991408cc1fSYuval Mintz * @param p_ptt 3001408cc1fSYuval Mintz * @param p_mfw_ver - mfw version value 3011408cc1fSYuval Mintz * @param p_running_bundle_id - image id in nvram; Optional. 302fe56b9e6SYuval Mintz * 3031408cc1fSYuval Mintz * @return int - 0 - operation was successful. 304fe56b9e6SYuval Mintz */ 3051408cc1fSYuval Mintz int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 3061408cc1fSYuval Mintz struct qed_ptt *p_ptt, 3071408cc1fSYuval Mintz u32 *p_mfw_ver, u32 *p_running_bundle_id); 308fe56b9e6SYuval Mintz 309fe56b9e6SYuval Mintz /** 310ae33666aSTomer Tayar * @brief Get the MBI version value 311ae33666aSTomer Tayar * 312ae33666aSTomer Tayar * @param p_hwfn 313ae33666aSTomer Tayar * @param p_ptt 314ae33666aSTomer Tayar * @param p_mbi_ver - A pointer to a variable to be filled with the MBI version. 315ae33666aSTomer Tayar * 316ae33666aSTomer Tayar * @return int - 0 - operation was successful. 317ae33666aSTomer Tayar */ 318ae33666aSTomer Tayar int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn, 319ae33666aSTomer Tayar struct qed_ptt *p_ptt, u32 *p_mbi_ver); 320ae33666aSTomer Tayar 321ae33666aSTomer Tayar /** 322cc875c2eSYuval Mintz * @brief Get media type value of the port. 323cc875c2eSYuval Mintz * 324cc875c2eSYuval Mintz * @param cdev - qed dev pointer 325cc875c2eSYuval Mintz * @param mfw_ver - media type value 326cc875c2eSYuval Mintz * 327cc875c2eSYuval Mintz * @return int - 328cc875c2eSYuval Mintz * 0 - Operation was successul. 329cc875c2eSYuval Mintz * -EBUSY - Operation failed 330cc875c2eSYuval Mintz */ 331cc875c2eSYuval Mintz int qed_mcp_get_media_type(struct qed_dev *cdev, 332cc875c2eSYuval Mintz u32 *media_type); 333cc875c2eSYuval Mintz 334cc875c2eSYuval Mintz /** 335fe56b9e6SYuval Mintz * @brief General function for sending commands to the MCP 336fe56b9e6SYuval Mintz * mailbox. It acquire mutex lock for the entire 337fe56b9e6SYuval Mintz * operation, from sending the request until the MCP 338fe56b9e6SYuval Mintz * response. Waiting for MCP response will be checked up 339fe56b9e6SYuval Mintz * to 5 seconds every 5ms. 340fe56b9e6SYuval Mintz * 341fe56b9e6SYuval Mintz * @param p_hwfn - hw function 342fe56b9e6SYuval Mintz * @param p_ptt - PTT required for register access 343fe56b9e6SYuval Mintz * @param cmd - command to be sent to the MCP. 344fe56b9e6SYuval Mintz * @param param - Optional param 345fe56b9e6SYuval Mintz * @param o_mcp_resp - The MCP response code (exclude sequence). 346fe56b9e6SYuval Mintz * @param o_mcp_param- Optional parameter provided by the MCP 347fe56b9e6SYuval Mintz * response 348fe56b9e6SYuval Mintz * @return int - 0 - operation 349fe56b9e6SYuval Mintz * was successul. 350fe56b9e6SYuval Mintz */ 351fe56b9e6SYuval Mintz int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 352fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 353fe56b9e6SYuval Mintz u32 cmd, 354fe56b9e6SYuval Mintz u32 param, 355fe56b9e6SYuval Mintz u32 *o_mcp_resp, 356fe56b9e6SYuval Mintz u32 *o_mcp_param); 357fe56b9e6SYuval Mintz 358fe56b9e6SYuval Mintz /** 359fe56b9e6SYuval Mintz * @brief - drains the nig, allowing completion to pass in case of pauses. 360fe56b9e6SYuval Mintz * (Should be called only from sleepable context) 361fe56b9e6SYuval Mintz * 362fe56b9e6SYuval Mintz * @param p_hwfn 363fe56b9e6SYuval Mintz * @param p_ptt 364fe56b9e6SYuval Mintz */ 365fe56b9e6SYuval Mintz int qed_mcp_drain(struct qed_hwfn *p_hwfn, 366fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 367fe56b9e6SYuval Mintz 368fe56b9e6SYuval Mintz /** 369cee4d264SManish Chopra * @brief Get the flash size value 370cee4d264SManish Chopra * 371cee4d264SManish Chopra * @param p_hwfn 372cee4d264SManish Chopra * @param p_ptt 373cee4d264SManish Chopra * @param p_flash_size - flash size in bytes to be filled. 374cee4d264SManish Chopra * 375cee4d264SManish Chopra * @return int - 0 - operation was successul. 376cee4d264SManish Chopra */ 377cee4d264SManish Chopra int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 378cee4d264SManish Chopra struct qed_ptt *p_ptt, 379cee4d264SManish Chopra u32 *p_flash_size); 380cee4d264SManish Chopra 381cee4d264SManish Chopra /** 382fe56b9e6SYuval Mintz * @brief Send driver version to MFW 383fe56b9e6SYuval Mintz * 384fe56b9e6SYuval Mintz * @param p_hwfn 385fe56b9e6SYuval Mintz * @param p_ptt 386fe56b9e6SYuval Mintz * @param version - Version value 387fe56b9e6SYuval Mintz * @param name - Protocol driver name 388fe56b9e6SYuval Mintz * 389fe56b9e6SYuval Mintz * @return int - 0 - operation was successul. 390fe56b9e6SYuval Mintz */ 391fe56b9e6SYuval Mintz int 392fe56b9e6SYuval Mintz qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 393fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 394fe56b9e6SYuval Mintz struct qed_mcp_drv_version *p_ver); 395fe56b9e6SYuval Mintz 39691420b83SSudarsana Kalluru /** 3970fefbfbaSSudarsana Kalluru * @brief Notify MFW about the change in base device properties 3980fefbfbaSSudarsana Kalluru * 3990fefbfbaSSudarsana Kalluru * @param p_hwfn 4000fefbfbaSSudarsana Kalluru * @param p_ptt 4010fefbfbaSSudarsana Kalluru * @param client - qed client type 4020fefbfbaSSudarsana Kalluru * 4030fefbfbaSSudarsana Kalluru * @return int - 0 - operation was successful. 4040fefbfbaSSudarsana Kalluru */ 4050fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 4060fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 4070fefbfbaSSudarsana Kalluru enum qed_ov_client client); 4080fefbfbaSSudarsana Kalluru 4090fefbfbaSSudarsana Kalluru /** 4100fefbfbaSSudarsana Kalluru * @brief Notify MFW about the driver state 4110fefbfbaSSudarsana Kalluru * 4120fefbfbaSSudarsana Kalluru * @param p_hwfn 4130fefbfbaSSudarsana Kalluru * @param p_ptt 4140fefbfbaSSudarsana Kalluru * @param drv_state - Driver state 4150fefbfbaSSudarsana Kalluru * 4160fefbfbaSSudarsana Kalluru * @return int - 0 - operation was successful. 4170fefbfbaSSudarsana Kalluru */ 4180fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 4190fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 4200fefbfbaSSudarsana Kalluru enum qed_ov_driver_state drv_state); 4210fefbfbaSSudarsana Kalluru 4220fefbfbaSSudarsana Kalluru /** 4230fefbfbaSSudarsana Kalluru * @brief Send MTU size to MFW 4240fefbfbaSSudarsana Kalluru * 4250fefbfbaSSudarsana Kalluru * @param p_hwfn 4260fefbfbaSSudarsana Kalluru * @param p_ptt 4270fefbfbaSSudarsana Kalluru * @param mtu - MTU size 4280fefbfbaSSudarsana Kalluru * 4290fefbfbaSSudarsana Kalluru * @return int - 0 - operation was successful. 4300fefbfbaSSudarsana Kalluru */ 4310fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 4320fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u16 mtu); 4330fefbfbaSSudarsana Kalluru 4340fefbfbaSSudarsana Kalluru /** 4350fefbfbaSSudarsana Kalluru * @brief Send MAC address to MFW 4360fefbfbaSSudarsana Kalluru * 4370fefbfbaSSudarsana Kalluru * @param p_hwfn 4380fefbfbaSSudarsana Kalluru * @param p_ptt 4390fefbfbaSSudarsana Kalluru * @param mac - MAC address 4400fefbfbaSSudarsana Kalluru * 4410fefbfbaSSudarsana Kalluru * @return int - 0 - operation was successful. 4420fefbfbaSSudarsana Kalluru */ 4430fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 4440fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u8 *mac); 4450fefbfbaSSudarsana Kalluru 4460fefbfbaSSudarsana Kalluru /** 4470fefbfbaSSudarsana Kalluru * @brief Send WOL mode to MFW 4480fefbfbaSSudarsana Kalluru * 4490fefbfbaSSudarsana Kalluru * @param p_hwfn 4500fefbfbaSSudarsana Kalluru * @param p_ptt 4510fefbfbaSSudarsana Kalluru * @param wol - WOL mode 4520fefbfbaSSudarsana Kalluru * 4530fefbfbaSSudarsana Kalluru * @return int - 0 - operation was successful. 4540fefbfbaSSudarsana Kalluru */ 4550fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 4560fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 4570fefbfbaSSudarsana Kalluru enum qed_ov_wol wol); 4580fefbfbaSSudarsana Kalluru 4590fefbfbaSSudarsana Kalluru /** 46091420b83SSudarsana Kalluru * @brief Set LED status 46191420b83SSudarsana Kalluru * 46291420b83SSudarsana Kalluru * @param p_hwfn 46391420b83SSudarsana Kalluru * @param p_ptt 46491420b83SSudarsana Kalluru * @param mode - LED mode 46591420b83SSudarsana Kalluru * 46691420b83SSudarsana Kalluru * @return int - 0 - operation was successful. 46791420b83SSudarsana Kalluru */ 46891420b83SSudarsana Kalluru int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 46991420b83SSudarsana Kalluru struct qed_ptt *p_ptt, 47091420b83SSudarsana Kalluru enum qed_led_mode mode); 47191420b83SSudarsana Kalluru 47203dc76caSSudarsana Reddy Kalluru /** 4737a4b21b7SMintz, Yuval * @brief Read from nvm 4747a4b21b7SMintz, Yuval * 4757a4b21b7SMintz, Yuval * @param cdev 4767a4b21b7SMintz, Yuval * @param addr - nvm offset 4777a4b21b7SMintz, Yuval * @param p_buf - nvm read buffer 4787a4b21b7SMintz, Yuval * @param len - buffer len 4797a4b21b7SMintz, Yuval * 4807a4b21b7SMintz, Yuval * @return int - 0 - operation was successful. 4817a4b21b7SMintz, Yuval */ 4827a4b21b7SMintz, Yuval int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len); 4837a4b21b7SMintz, Yuval 48462e4d438SSudarsana Reddy Kalluru /** 48562e4d438SSudarsana Reddy Kalluru * @brief Write to nvm 48662e4d438SSudarsana Reddy Kalluru * 48762e4d438SSudarsana Reddy Kalluru * @param cdev 48862e4d438SSudarsana Reddy Kalluru * @param addr - nvm offset 48962e4d438SSudarsana Reddy Kalluru * @param cmd - nvm command 49062e4d438SSudarsana Reddy Kalluru * @param p_buf - nvm write buffer 49162e4d438SSudarsana Reddy Kalluru * @param len - buffer len 49262e4d438SSudarsana Reddy Kalluru * 49362e4d438SSudarsana Reddy Kalluru * @return int - 0 - operation was successful. 49462e4d438SSudarsana Reddy Kalluru */ 49562e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_write(struct qed_dev *cdev, 49662e4d438SSudarsana Reddy Kalluru u32 cmd, u32 addr, u8 *p_buf, u32 len); 49762e4d438SSudarsana Reddy Kalluru 49862e4d438SSudarsana Reddy Kalluru /** 49962e4d438SSudarsana Reddy Kalluru * @brief Put file begin 50062e4d438SSudarsana Reddy Kalluru * 50162e4d438SSudarsana Reddy Kalluru * @param cdev 50262e4d438SSudarsana Reddy Kalluru * @param addr - nvm offset 50362e4d438SSudarsana Reddy Kalluru * 50462e4d438SSudarsana Reddy Kalluru * @return int - 0 - operation was successful. 50562e4d438SSudarsana Reddy Kalluru */ 50662e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_put_file_begin(struct qed_dev *cdev, u32 addr); 50762e4d438SSudarsana Reddy Kalluru 50862e4d438SSudarsana Reddy Kalluru /** 50962e4d438SSudarsana Reddy Kalluru * @brief Check latest response 51062e4d438SSudarsana Reddy Kalluru * 51162e4d438SSudarsana Reddy Kalluru * @param cdev 51262e4d438SSudarsana Reddy Kalluru * @param p_buf - nvm write buffer 51362e4d438SSudarsana Reddy Kalluru * 51462e4d438SSudarsana Reddy Kalluru * @return int - 0 - operation was successful. 51562e4d438SSudarsana Reddy Kalluru */ 51662e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf); 51762e4d438SSudarsana Reddy Kalluru 51820675b37SMintz, Yuval struct qed_nvm_image_att { 51920675b37SMintz, Yuval u32 start_addr; 52020675b37SMintz, Yuval u32 length; 52120675b37SMintz, Yuval }; 52220675b37SMintz, Yuval 52320675b37SMintz, Yuval /** 52420675b37SMintz, Yuval * @brief Allows reading a whole nvram image 52520675b37SMintz, Yuval * 52620675b37SMintz, Yuval * @param p_hwfn 5271ac4329aSDenis Bolotin * @param image_id - image to get attributes for 5281ac4329aSDenis Bolotin * @param p_image_att - image attributes structure into which to fill data 5291ac4329aSDenis Bolotin * 5301ac4329aSDenis Bolotin * @return int - 0 - operation was successful. 5311ac4329aSDenis Bolotin */ 5321ac4329aSDenis Bolotin int 5331ac4329aSDenis Bolotin qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn, 5341ac4329aSDenis Bolotin enum qed_nvm_images image_id, 5351ac4329aSDenis Bolotin struct qed_nvm_image_att *p_image_att); 5361ac4329aSDenis Bolotin 5371ac4329aSDenis Bolotin /** 5381ac4329aSDenis Bolotin * @brief Allows reading a whole nvram image 5391ac4329aSDenis Bolotin * 5401ac4329aSDenis Bolotin * @param p_hwfn 54120675b37SMintz, Yuval * @param image_id - image requested for reading 54220675b37SMintz, Yuval * @param p_buffer - allocated buffer into which to fill data 54320675b37SMintz, Yuval * @param buffer_len - length of the allocated buffer. 54420675b37SMintz, Yuval * 54520675b37SMintz, Yuval * @return 0 iff p_buffer now contains the nvram image. 54620675b37SMintz, Yuval */ 54720675b37SMintz, Yuval int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn, 54820675b37SMintz, Yuval enum qed_nvm_images image_id, 54920675b37SMintz, Yuval u8 *p_buffer, u32 buffer_len); 55020675b37SMintz, Yuval 5517a4b21b7SMintz, Yuval /** 55203dc76caSSudarsana Reddy Kalluru * @brief Bist register test 55303dc76caSSudarsana Reddy Kalluru * 55403dc76caSSudarsana Reddy Kalluru * @param p_hwfn - hw function 55503dc76caSSudarsana Reddy Kalluru * @param p_ptt - PTT required for register access 55603dc76caSSudarsana Reddy Kalluru * 55703dc76caSSudarsana Reddy Kalluru * @return int - 0 - operation was successful. 55803dc76caSSudarsana Reddy Kalluru */ 55903dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, 56003dc76caSSudarsana Reddy Kalluru struct qed_ptt *p_ptt); 56103dc76caSSudarsana Reddy Kalluru 56203dc76caSSudarsana Reddy Kalluru /** 56303dc76caSSudarsana Reddy Kalluru * @brief Bist clock test 56403dc76caSSudarsana Reddy Kalluru * 56503dc76caSSudarsana Reddy Kalluru * @param p_hwfn - hw function 56603dc76caSSudarsana Reddy Kalluru * @param p_ptt - PTT required for register access 56703dc76caSSudarsana Reddy Kalluru * 56803dc76caSSudarsana Reddy Kalluru * @return int - 0 - operation was successful. 56903dc76caSSudarsana Reddy Kalluru */ 57003dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, 57103dc76caSSudarsana Reddy Kalluru struct qed_ptt *p_ptt); 57203dc76caSSudarsana Reddy Kalluru 5737a4b21b7SMintz, Yuval /** 5747a4b21b7SMintz, Yuval * @brief Bist nvm test - get number of images 5757a4b21b7SMintz, Yuval * 5767a4b21b7SMintz, Yuval * @param p_hwfn - hw function 5777a4b21b7SMintz, Yuval * @param p_ptt - PTT required for register access 5787a4b21b7SMintz, Yuval * @param num_images - number of images if operation was 5797a4b21b7SMintz, Yuval * successful. 0 if not. 5807a4b21b7SMintz, Yuval * 5817a4b21b7SMintz, Yuval * @return int - 0 - operation was successful. 5827a4b21b7SMintz, Yuval */ 58343645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn, 5847a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 5857a4b21b7SMintz, Yuval u32 *num_images); 5867a4b21b7SMintz, Yuval 5877a4b21b7SMintz, Yuval /** 5887a4b21b7SMintz, Yuval * @brief Bist nvm test - get image attributes by index 5897a4b21b7SMintz, Yuval * 5907a4b21b7SMintz, Yuval * @param p_hwfn - hw function 5917a4b21b7SMintz, Yuval * @param p_ptt - PTT required for register access 5927a4b21b7SMintz, Yuval * @param p_image_att - Attributes of image 5937a4b21b7SMintz, Yuval * @param image_index - Index of image to get information for 5947a4b21b7SMintz, Yuval * 5957a4b21b7SMintz, Yuval * @return int - 0 - operation was successful. 5967a4b21b7SMintz, Yuval */ 59743645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn, 5987a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 5997a4b21b7SMintz, Yuval struct bist_nvm_image_att *p_image_att, 6007a4b21b7SMintz, Yuval u32 image_index); 6017a4b21b7SMintz, Yuval 6022528c389SSudarsana Reddy Kalluru /** 6032528c389SSudarsana Reddy Kalluru * @brief - Processes the TLV request from MFW i.e., get the required TLV info 6042528c389SSudarsana Reddy Kalluru * from the qed client and send it to the MFW. 6052528c389SSudarsana Reddy Kalluru * 6062528c389SSudarsana Reddy Kalluru * @param p_hwfn 6072528c389SSudarsana Reddy Kalluru * @param p_ptt 6082528c389SSudarsana Reddy Kalluru * 6092528c389SSudarsana Reddy Kalluru * @param return 0 upon success. 6102528c389SSudarsana Reddy Kalluru */ 6112528c389SSudarsana Reddy Kalluru int qed_mfw_process_tlv_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 6122528c389SSudarsana Reddy Kalluru 613fe56b9e6SYuval Mintz /* Using hwfn number (and not pf_num) is required since in CMT mode, 614fe56b9e6SYuval Mintz * same pf_num may be used by two different hwfn 615fe56b9e6SYuval Mintz * TODO - this shouldn't really be in .h file, but until all fields 616fe56b9e6SYuval Mintz * required during hw-init will be placed in their correct place in shmem 617fe56b9e6SYuval Mintz * we need it in qed_dev.c [for readin the nvram reflection in shmem]. 618fe56b9e6SYuval Mintz */ 619fe56b9e6SYuval Mintz #define MCP_PF_ID_BY_REL(p_hwfn, rel_pfid) (QED_IS_BB((p_hwfn)->cdev) ? \ 620fe56b9e6SYuval Mintz ((rel_pfid) | \ 621fe56b9e6SYuval Mintz ((p_hwfn)->abs_pf_id & 1) << 3) : \ 622fe56b9e6SYuval Mintz rel_pfid) 623fe56b9e6SYuval Mintz #define MCP_PF_ID(p_hwfn) MCP_PF_ID_BY_REL(p_hwfn, (p_hwfn)->rel_pf_id) 624fe56b9e6SYuval Mintz 625fe56b9e6SYuval Mintz #define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \ 62678cea9ffSTomer Tayar ((_p_hwfn)->cdev->num_ports_in_engine * \ 6279c79ddaaSMintz, Yuval qed_device_num_engines((_p_hwfn)->cdev))) 6289c79ddaaSMintz, Yuval 629fe56b9e6SYuval Mintz struct qed_mcp_info { 6304ed1eea8STomer Tayar /* List for mailbox commands which were sent and wait for a response */ 6314ed1eea8STomer Tayar struct list_head cmd_list; 6324ed1eea8STomer Tayar 6334ed1eea8STomer Tayar /* Spinlock used for protecting the access to the mailbox commands list 6344ed1eea8STomer Tayar * and the sending of the commands. 6354ed1eea8STomer Tayar */ 6364ed1eea8STomer Tayar spinlock_t cmd_lock; 63765ed2ffdSMintz, Yuval 63865ed2ffdSMintz, Yuval /* Spinlock used for syncing SW link-changes and link-changes 63965ed2ffdSMintz, Yuval * originating from attention context. 64065ed2ffdSMintz, Yuval */ 64165ed2ffdSMintz, Yuval spinlock_t link_lock; 6425529bad9STomer Tayar bool block_mb_sending; 643fe56b9e6SYuval Mintz u32 public_base; 644fe56b9e6SYuval Mintz u32 drv_mb_addr; 645fe56b9e6SYuval Mintz u32 mfw_mb_addr; 646fe56b9e6SYuval Mintz u32 port_addr; 647fe56b9e6SYuval Mintz u16 drv_mb_seq; 648fe56b9e6SYuval Mintz u16 drv_pulse_seq; 649cc875c2eSYuval Mintz struct qed_mcp_link_params link_input; 650cc875c2eSYuval Mintz struct qed_mcp_link_state link_output; 651cc875c2eSYuval Mintz struct qed_mcp_link_capabilities link_capabilities; 652fe56b9e6SYuval Mintz struct qed_mcp_function_info func_info; 653fe56b9e6SYuval Mintz u8 *mfw_mb_cur; 654fe56b9e6SYuval Mintz u8 *mfw_mb_shadow; 655fe56b9e6SYuval Mintz u16 mfw_mb_length; 6564ed1eea8STomer Tayar u32 mcp_hist; 657645874e5SSudarsana Reddy Kalluru 658645874e5SSudarsana Reddy Kalluru /* Capabilties negotiated with the MFW */ 659645874e5SSudarsana Reddy Kalluru u32 capabilities; 660fe56b9e6SYuval Mintz }; 661fe56b9e6SYuval Mintz 6625529bad9STomer Tayar struct qed_mcp_mb_params { 6635529bad9STomer Tayar u32 cmd; 6645529bad9STomer Tayar u32 param; 6652f67af8cSTomer Tayar void *p_data_src; 6662f67af8cSTomer Tayar u8 data_src_size; 6672f67af8cSTomer Tayar void *p_data_dst; 6682f67af8cSTomer Tayar u8 data_dst_size; 6695529bad9STomer Tayar u32 mcp_resp; 6705529bad9STomer Tayar u32 mcp_param; 6715529bad9STomer Tayar }; 6725529bad9STomer Tayar 6732528c389SSudarsana Reddy Kalluru struct qed_drv_tlv_hdr { 6742528c389SSudarsana Reddy Kalluru u8 tlv_type; 6752528c389SSudarsana Reddy Kalluru u8 tlv_length; /* In dwords - not including this header */ 6762528c389SSudarsana Reddy Kalluru u8 tlv_reserved; 6772528c389SSudarsana Reddy Kalluru #define QED_DRV_TLV_FLAGS_CHANGED 0x01 6782528c389SSudarsana Reddy Kalluru u8 tlv_flags; 6792528c389SSudarsana Reddy Kalluru }; 6802528c389SSudarsana Reddy Kalluru 681fe56b9e6SYuval Mintz /** 682fe56b9e6SYuval Mintz * @brief Initialize the interface with the MCP 683fe56b9e6SYuval Mintz * 684fe56b9e6SYuval Mintz * @param p_hwfn - HW func 685fe56b9e6SYuval Mintz * @param p_ptt - PTT required for register access 686fe56b9e6SYuval Mintz * 687fe56b9e6SYuval Mintz * @return int 688fe56b9e6SYuval Mintz */ 689fe56b9e6SYuval Mintz int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, 690fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 691fe56b9e6SYuval Mintz 692fe56b9e6SYuval Mintz /** 693fe56b9e6SYuval Mintz * @brief Initialize the port interface with the MCP 694fe56b9e6SYuval Mintz * 695fe56b9e6SYuval Mintz * @param p_hwfn 696fe56b9e6SYuval Mintz * @param p_ptt 697fe56b9e6SYuval Mintz * Can only be called after `num_ports_in_engines' is set 698fe56b9e6SYuval Mintz */ 699fe56b9e6SYuval Mintz void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, 700fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 701fe56b9e6SYuval Mintz /** 702fe56b9e6SYuval Mintz * @brief Releases resources allocated during the init process. 703fe56b9e6SYuval Mintz * 704fe56b9e6SYuval Mintz * @param p_hwfn - HW func 705fe56b9e6SYuval Mintz * @param p_ptt - PTT required for register access 706fe56b9e6SYuval Mintz * 707fe56b9e6SYuval Mintz * @return int 708fe56b9e6SYuval Mintz */ 709fe56b9e6SYuval Mintz 710fe56b9e6SYuval Mintz int qed_mcp_free(struct qed_hwfn *p_hwfn); 711fe56b9e6SYuval Mintz 712fe56b9e6SYuval Mintz /** 713cc875c2eSYuval Mintz * @brief This function is called from the DPC context. After 714cc875c2eSYuval Mintz * pointing PTT to the mfw mb, check for events sent by the MCP 715cc875c2eSYuval Mintz * to the driver and ack them. In case a critical event 716cc875c2eSYuval Mintz * detected, it will be handled here, otherwise the work will be 717cc875c2eSYuval Mintz * queued to a sleepable work-queue. 718cc875c2eSYuval Mintz * 719cc875c2eSYuval Mintz * @param p_hwfn - HW function 720cc875c2eSYuval Mintz * @param p_ptt - PTT required for register access 721cc875c2eSYuval Mintz * @return int - 0 - operation 722cc875c2eSYuval Mintz * was successul. 723cc875c2eSYuval Mintz */ 724cc875c2eSYuval Mintz int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 725cc875c2eSYuval Mintz struct qed_ptt *p_ptt); 726cc875c2eSYuval Mintz 7275d24bcf1STomer Tayar enum qed_drv_role { 7285d24bcf1STomer Tayar QED_DRV_ROLE_OS, 7295d24bcf1STomer Tayar QED_DRV_ROLE_KDUMP, 7305d24bcf1STomer Tayar }; 7315d24bcf1STomer Tayar 7325d24bcf1STomer Tayar struct qed_load_req_params { 7335d24bcf1STomer Tayar /* Input params */ 7345d24bcf1STomer Tayar enum qed_drv_role drv_role; 7355d24bcf1STomer Tayar u8 timeout_val; 7365d24bcf1STomer Tayar bool avoid_eng_reset; 7375d24bcf1STomer Tayar enum qed_override_force_load override_force_load; 7385d24bcf1STomer Tayar 7395d24bcf1STomer Tayar /* Output params */ 7405d24bcf1STomer Tayar u32 load_code; 7415d24bcf1STomer Tayar }; 7425d24bcf1STomer Tayar 743cc875c2eSYuval Mintz /** 7445d24bcf1STomer Tayar * @brief Sends a LOAD_REQ to the MFW, and in case the operation succeeds, 7455d24bcf1STomer Tayar * returns whether this PF is the first on the engine/port or function. 746fe56b9e6SYuval Mintz * 7475d24bcf1STomer Tayar * @param p_hwfn 7485d24bcf1STomer Tayar * @param p_ptt 7495d24bcf1STomer Tayar * @param p_params 7505d24bcf1STomer Tayar * 7515d24bcf1STomer Tayar * @return int - 0 - Operation was successful. 752fe56b9e6SYuval Mintz */ 753fe56b9e6SYuval Mintz int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 754fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 7555d24bcf1STomer Tayar struct qed_load_req_params *p_params); 756fe56b9e6SYuval Mintz 757fe56b9e6SYuval Mintz /** 7581226337aSTomer Tayar * @brief Sends a UNLOAD_REQ message to the MFW 7591226337aSTomer Tayar * 7601226337aSTomer Tayar * @param p_hwfn 7611226337aSTomer Tayar * @param p_ptt 7621226337aSTomer Tayar * 7631226337aSTomer Tayar * @return int - 0 - Operation was successful. 7641226337aSTomer Tayar */ 7651226337aSTomer Tayar int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 7661226337aSTomer Tayar 7671226337aSTomer Tayar /** 7681226337aSTomer Tayar * @brief Sends a UNLOAD_DONE message to the MFW 7691226337aSTomer Tayar * 7701226337aSTomer Tayar * @param p_hwfn 7711226337aSTomer Tayar * @param p_ptt 7721226337aSTomer Tayar * 7731226337aSTomer Tayar * @return int - 0 - Operation was successful. 7741226337aSTomer Tayar */ 7751226337aSTomer Tayar int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 7761226337aSTomer Tayar 7771226337aSTomer Tayar /** 778fe56b9e6SYuval Mintz * @brief Read the MFW mailbox into Current buffer. 779fe56b9e6SYuval Mintz * 780fe56b9e6SYuval Mintz * @param p_hwfn 781fe56b9e6SYuval Mintz * @param p_ptt 782fe56b9e6SYuval Mintz */ 783fe56b9e6SYuval Mintz void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, 784fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 785fe56b9e6SYuval Mintz 786fe56b9e6SYuval Mintz /** 7870b55e27dSYuval Mintz * @brief Ack to mfw that driver finished FLR process for VFs 7880b55e27dSYuval Mintz * 7890b55e27dSYuval Mintz * @param p_hwfn 7900b55e27dSYuval Mintz * @param p_ptt 7910b55e27dSYuval Mintz * @param vfs_to_ack - bit mask of all engine VFs for which the PF acks. 7920b55e27dSYuval Mintz * 7930b55e27dSYuval Mintz * @param return int - 0 upon success. 7940b55e27dSYuval Mintz */ 7950b55e27dSYuval Mintz int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 7960b55e27dSYuval Mintz struct qed_ptt *p_ptt, u32 *vfs_to_ack); 7970b55e27dSYuval Mintz 7980b55e27dSYuval Mintz /** 799fe56b9e6SYuval Mintz * @brief - calls during init to read shmem of all function-related info. 800fe56b9e6SYuval Mintz * 801fe56b9e6SYuval Mintz * @param p_hwfn 802fe56b9e6SYuval Mintz * 803fe56b9e6SYuval Mintz * @param return 0 upon success. 804fe56b9e6SYuval Mintz */ 805fe56b9e6SYuval Mintz int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 806fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 807fe56b9e6SYuval Mintz 808fe56b9e6SYuval Mintz /** 809fe56b9e6SYuval Mintz * @brief - Reset the MCP using mailbox command. 810fe56b9e6SYuval Mintz * 811fe56b9e6SYuval Mintz * @param p_hwfn 812fe56b9e6SYuval Mintz * @param p_ptt 813fe56b9e6SYuval Mintz * 814fe56b9e6SYuval Mintz * @param return 0 upon success. 815fe56b9e6SYuval Mintz */ 816fe56b9e6SYuval Mintz int qed_mcp_reset(struct qed_hwfn *p_hwfn, 817fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 818fe56b9e6SYuval Mintz 819fe56b9e6SYuval Mintz /** 8204102426fSTomer Tayar * @brief - Sends an NVM read command request to the MFW to get 8214102426fSTomer Tayar * a buffer. 8224102426fSTomer Tayar * 8234102426fSTomer Tayar * @param p_hwfn 8244102426fSTomer Tayar * @param p_ptt 8254102426fSTomer Tayar * @param cmd - Command: DRV_MSG_CODE_NVM_GET_FILE_DATA or 8264102426fSTomer Tayar * DRV_MSG_CODE_NVM_READ_NVRAM commands 8274102426fSTomer Tayar * @param param - [0:23] - Offset [24:31] - Size 8284102426fSTomer Tayar * @param o_mcp_resp - MCP response 8294102426fSTomer Tayar * @param o_mcp_param - MCP response param 8304102426fSTomer Tayar * @param o_txn_size - Buffer size output 8314102426fSTomer Tayar * @param o_buf - Pointer to the buffer returned by the MFW. 8324102426fSTomer Tayar * 8334102426fSTomer Tayar * @param return 0 upon success. 8344102426fSTomer Tayar */ 8354102426fSTomer Tayar int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 8364102426fSTomer Tayar struct qed_ptt *p_ptt, 8374102426fSTomer Tayar u32 cmd, 8384102426fSTomer Tayar u32 param, 8394102426fSTomer Tayar u32 *o_mcp_resp, 8404102426fSTomer Tayar u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf); 8414102426fSTomer Tayar 8424102426fSTomer Tayar /** 843*b51dab46SSudarsana Reddy Kalluru * @brief Read from sfp 844*b51dab46SSudarsana Reddy Kalluru * 845*b51dab46SSudarsana Reddy Kalluru * @param p_hwfn - hw function 846*b51dab46SSudarsana Reddy Kalluru * @param p_ptt - PTT required for register access 847*b51dab46SSudarsana Reddy Kalluru * @param port - transceiver port 848*b51dab46SSudarsana Reddy Kalluru * @param addr - I2C address 849*b51dab46SSudarsana Reddy Kalluru * @param offset - offset in sfp 850*b51dab46SSudarsana Reddy Kalluru * @param len - buffer length 851*b51dab46SSudarsana Reddy Kalluru * @param p_buf - buffer to read into 852*b51dab46SSudarsana Reddy Kalluru * 853*b51dab46SSudarsana Reddy Kalluru * @return int - 0 - operation was successful. 854*b51dab46SSudarsana Reddy Kalluru */ 855*b51dab46SSudarsana Reddy Kalluru int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 856*b51dab46SSudarsana Reddy Kalluru u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf); 857*b51dab46SSudarsana Reddy Kalluru 858*b51dab46SSudarsana Reddy Kalluru /** 859fe56b9e6SYuval Mintz * @brief indicates whether the MFW objects [under mcp_info] are accessible 860fe56b9e6SYuval Mintz * 861fe56b9e6SYuval Mintz * @param p_hwfn 862fe56b9e6SYuval Mintz * 863fe56b9e6SYuval Mintz * @return true iff MFW is running and mcp_info is initialized 864fe56b9e6SYuval Mintz */ 865fe56b9e6SYuval Mintz bool qed_mcp_is_init(struct qed_hwfn *p_hwfn); 8661408cc1fSYuval Mintz 8671408cc1fSYuval Mintz /** 8681408cc1fSYuval Mintz * @brief request MFW to configure MSI-X for a VF 8691408cc1fSYuval Mintz * 8701408cc1fSYuval Mintz * @param p_hwfn 8711408cc1fSYuval Mintz * @param p_ptt 8721408cc1fSYuval Mintz * @param vf_id - absolute inside engine 8731408cc1fSYuval Mintz * @param num_sbs - number of entries to request 8741408cc1fSYuval Mintz * 8751408cc1fSYuval Mintz * @return int 8761408cc1fSYuval Mintz */ 8771408cc1fSYuval Mintz int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 8781408cc1fSYuval Mintz struct qed_ptt *p_ptt, u8 vf_id, u8 num); 8791408cc1fSYuval Mintz 8804102426fSTomer Tayar /** 8814102426fSTomer Tayar * @brief - Halt the MCP. 8824102426fSTomer Tayar * 8834102426fSTomer Tayar * @param p_hwfn 8844102426fSTomer Tayar * @param p_ptt 8854102426fSTomer Tayar * 8864102426fSTomer Tayar * @param return 0 upon success. 8874102426fSTomer Tayar */ 8884102426fSTomer Tayar int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 8894102426fSTomer Tayar 8904102426fSTomer Tayar /** 8914102426fSTomer Tayar * @brief - Wake up the MCP. 8924102426fSTomer Tayar * 8934102426fSTomer Tayar * @param p_hwfn 8944102426fSTomer Tayar * @param p_ptt 8954102426fSTomer Tayar * 8964102426fSTomer Tayar * @param return 0 upon success. 8974102426fSTomer Tayar */ 8984102426fSTomer Tayar int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 8994102426fSTomer Tayar 900a64b02d5SManish Chopra int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw); 9014b01e519SManish Chopra int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw); 9024b01e519SManish Chopra int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, 9034b01e519SManish Chopra struct qed_ptt *p_ptt, 9044b01e519SManish Chopra struct qed_mcp_link_state *p_link, 9054b01e519SManish Chopra u8 max_bw); 906a64b02d5SManish Chopra int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn, 907a64b02d5SManish Chopra struct qed_ptt *p_ptt, 908a64b02d5SManish Chopra struct qed_mcp_link_state *p_link, 909a64b02d5SManish Chopra u8 min_bw); 910351a4dedSYuval Mintz 9114102426fSTomer Tayar int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 9124102426fSTomer Tayar struct qed_ptt *p_ptt, u32 mask_parities); 9134102426fSTomer Tayar 9140fefbfbaSSudarsana Kalluru /** 9159c8517c4STomer Tayar * @brief - Sets the MFW's max value for the given resource 9169c8517c4STomer Tayar * 9179c8517c4STomer Tayar * @param p_hwfn 9189c8517c4STomer Tayar * @param p_ptt 9199c8517c4STomer Tayar * @param res_id 9209c8517c4STomer Tayar * @param resc_max_val 9219c8517c4STomer Tayar * @param p_mcp_resp 9229c8517c4STomer Tayar * 9239c8517c4STomer Tayar * @return int - 0 - operation was successful. 9249c8517c4STomer Tayar */ 9259c8517c4STomer Tayar int 9269c8517c4STomer Tayar qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn, 9279c8517c4STomer Tayar struct qed_ptt *p_ptt, 9289c8517c4STomer Tayar enum qed_resources res_id, 9299c8517c4STomer Tayar u32 resc_max_val, u32 *p_mcp_resp); 9309c8517c4STomer Tayar 9319c8517c4STomer Tayar /** 9329c8517c4STomer Tayar * @brief - Gets the MFW allocation info for the given resource 9339c8517c4STomer Tayar * 9349c8517c4STomer Tayar * @param p_hwfn 9359c8517c4STomer Tayar * @param p_ptt 9369c8517c4STomer Tayar * @param res_id 9379c8517c4STomer Tayar * @param p_mcp_resp 9389c8517c4STomer Tayar * @param p_resc_num 9399c8517c4STomer Tayar * @param p_resc_start 9409c8517c4STomer Tayar * 9419c8517c4STomer Tayar * @return int - 0 - operation was successful. 9429c8517c4STomer Tayar */ 9439c8517c4STomer Tayar int 9449c8517c4STomer Tayar qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, 9459c8517c4STomer Tayar struct qed_ptt *p_ptt, 9469c8517c4STomer Tayar enum qed_resources res_id, 9479c8517c4STomer Tayar u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start); 9489c8517c4STomer Tayar 9499c8517c4STomer Tayar /** 9500fefbfbaSSudarsana Kalluru * @brief Send eswitch mode to MFW 9510fefbfbaSSudarsana Kalluru * 9520fefbfbaSSudarsana Kalluru * @param p_hwfn 9530fefbfbaSSudarsana Kalluru * @param p_ptt 9540fefbfbaSSudarsana Kalluru * @param eswitch - eswitch mode 9550fefbfbaSSudarsana Kalluru * 9560fefbfbaSSudarsana Kalluru * @return int - 0 - operation was successful. 9570fefbfbaSSudarsana Kalluru */ 9580fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 9590fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 9600fefbfbaSSudarsana Kalluru enum qed_ov_eswitch eswitch); 9610fefbfbaSSudarsana Kalluru 9629c8517c4STomer Tayar #define QED_MCP_RESC_LOCK_MIN_VAL RESOURCE_DUMP 9639c8517c4STomer Tayar #define QED_MCP_RESC_LOCK_MAX_VAL 31 9649c8517c4STomer Tayar 9659c8517c4STomer Tayar enum qed_resc_lock { 9669c8517c4STomer Tayar QED_RESC_LOCK_DBG_DUMP = QED_MCP_RESC_LOCK_MIN_VAL, 967db82f70eSsudarsana.kalluru@cavium.com QED_RESC_LOCK_PTP_PORT0, 968db82f70eSsudarsana.kalluru@cavium.com QED_RESC_LOCK_PTP_PORT1, 969db82f70eSsudarsana.kalluru@cavium.com QED_RESC_LOCK_PTP_PORT2, 970db82f70eSsudarsana.kalluru@cavium.com QED_RESC_LOCK_PTP_PORT3, 971f470f22cSsudarsana.kalluru@cavium.com QED_RESC_LOCK_RESC_ALLOC = QED_MCP_RESC_LOCK_MAX_VAL, 972f470f22cSsudarsana.kalluru@cavium.com QED_RESC_LOCK_RESC_INVALID 9739c8517c4STomer Tayar }; 97418a69e36SMintz, Yuval 97518a69e36SMintz, Yuval /** 97618a69e36SMintz, Yuval * @brief - Initiates PF FLR 97718a69e36SMintz, Yuval * 97818a69e36SMintz, Yuval * @param p_hwfn 97918a69e36SMintz, Yuval * @param p_ptt 98018a69e36SMintz, Yuval * 98118a69e36SMintz, Yuval * @return int - 0 - operation was successful. 98218a69e36SMintz, Yuval */ 98318a69e36SMintz, Yuval int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 98495691c9cSTomer Tayar struct qed_resc_lock_params { 98595691c9cSTomer Tayar /* Resource number [valid values are 0..31] */ 98695691c9cSTomer Tayar u8 resource; 98795691c9cSTomer Tayar 98895691c9cSTomer Tayar /* Lock timeout value in seconds [default, none or 1..254] */ 98995691c9cSTomer Tayar u8 timeout; 99095691c9cSTomer Tayar #define QED_MCP_RESC_LOCK_TO_DEFAULT 0 99195691c9cSTomer Tayar #define QED_MCP_RESC_LOCK_TO_NONE 255 99295691c9cSTomer Tayar 99395691c9cSTomer Tayar /* Number of times to retry locking */ 99495691c9cSTomer Tayar u8 retry_num; 995f470f22cSsudarsana.kalluru@cavium.com #define QED_MCP_RESC_LOCK_RETRY_CNT_DFLT 10 99695691c9cSTomer Tayar 99795691c9cSTomer Tayar /* The interval in usec between retries */ 99895691c9cSTomer Tayar u16 retry_interval; 999f470f22cSsudarsana.kalluru@cavium.com #define QED_MCP_RESC_LOCK_RETRY_VAL_DFLT 10000 100095691c9cSTomer Tayar 100195691c9cSTomer Tayar /* Use sleep or delay between retries */ 100295691c9cSTomer Tayar bool sleep_b4_retry; 100395691c9cSTomer Tayar 100495691c9cSTomer Tayar /* Will be set as true if the resource is free and granted */ 100595691c9cSTomer Tayar bool b_granted; 100695691c9cSTomer Tayar 100795691c9cSTomer Tayar /* Will be filled with the resource owner. 100895691c9cSTomer Tayar * [0..15 = PF0-15, 16 = MFW] 100995691c9cSTomer Tayar */ 101095691c9cSTomer Tayar u8 owner; 101195691c9cSTomer Tayar }; 101295691c9cSTomer Tayar 101395691c9cSTomer Tayar /** 101495691c9cSTomer Tayar * @brief Acquires MFW generic resource lock 101595691c9cSTomer Tayar * 101695691c9cSTomer Tayar * @param p_hwfn 101795691c9cSTomer Tayar * @param p_ptt 101895691c9cSTomer Tayar * @param p_params 101995691c9cSTomer Tayar * 102095691c9cSTomer Tayar * @return int - 0 - operation was successful. 102195691c9cSTomer Tayar */ 102295691c9cSTomer Tayar int 102395691c9cSTomer Tayar qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 102495691c9cSTomer Tayar struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params); 102595691c9cSTomer Tayar 102695691c9cSTomer Tayar struct qed_resc_unlock_params { 102795691c9cSTomer Tayar /* Resource number [valid values are 0..31] */ 102895691c9cSTomer Tayar u8 resource; 102995691c9cSTomer Tayar 103095691c9cSTomer Tayar /* Allow to release a resource even if belongs to another PF */ 103195691c9cSTomer Tayar bool b_force; 103295691c9cSTomer Tayar 103395691c9cSTomer Tayar /* Will be set as true if the resource is released */ 103495691c9cSTomer Tayar bool b_released; 103595691c9cSTomer Tayar }; 103695691c9cSTomer Tayar 103795691c9cSTomer Tayar /** 103895691c9cSTomer Tayar * @brief Releases MFW generic resource lock 103995691c9cSTomer Tayar * 104095691c9cSTomer Tayar * @param p_hwfn 104195691c9cSTomer Tayar * @param p_ptt 104295691c9cSTomer Tayar * @param p_params 104395691c9cSTomer Tayar * 104495691c9cSTomer Tayar * @return int - 0 - operation was successful. 104595691c9cSTomer Tayar */ 104695691c9cSTomer Tayar int 104795691c9cSTomer Tayar qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn, 104895691c9cSTomer Tayar struct qed_ptt *p_ptt, 104995691c9cSTomer Tayar struct qed_resc_unlock_params *p_params); 105095691c9cSTomer Tayar 1051f470f22cSsudarsana.kalluru@cavium.com /** 1052f470f22cSsudarsana.kalluru@cavium.com * @brief - default initialization for lock/unlock resource structs 1053f470f22cSsudarsana.kalluru@cavium.com * 1054f470f22cSsudarsana.kalluru@cavium.com * @param p_lock - lock params struct to be initialized; Can be NULL 1055f470f22cSsudarsana.kalluru@cavium.com * @param p_unlock - unlock params struct to be initialized; Can be NULL 1056f470f22cSsudarsana.kalluru@cavium.com * @param resource - the requested resource 1057f470f22cSsudarsana.kalluru@cavium.com * @paral b_is_permanent - disable retries & aging when set 1058f470f22cSsudarsana.kalluru@cavium.com */ 1059f470f22cSsudarsana.kalluru@cavium.com void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock, 1060f470f22cSsudarsana.kalluru@cavium.com struct qed_resc_unlock_params *p_unlock, 1061f470f22cSsudarsana.kalluru@cavium.com enum qed_resc_lock 1062f470f22cSsudarsana.kalluru@cavium.com resource, bool b_is_permanent); 1063645874e5SSudarsana Reddy Kalluru /** 1064645874e5SSudarsana Reddy Kalluru * @brief Learn of supported MFW features; To be done during early init 1065645874e5SSudarsana Reddy Kalluru * 1066645874e5SSudarsana Reddy Kalluru * @param p_hwfn 1067645874e5SSudarsana Reddy Kalluru * @param p_ptt 1068645874e5SSudarsana Reddy Kalluru */ 1069645874e5SSudarsana Reddy Kalluru int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 1070f470f22cSsudarsana.kalluru@cavium.com 1071645874e5SSudarsana Reddy Kalluru /** 1072645874e5SSudarsana Reddy Kalluru * @brief Inform MFW of set of features supported by driver. Should be done 1073645874e5SSudarsana Reddy Kalluru * inside the content of the LOAD_REQ. 1074645874e5SSudarsana Reddy Kalluru * 1075645874e5SSudarsana Reddy Kalluru * @param p_hwfn 1076645874e5SSudarsana Reddy Kalluru * @param p_ptt 1077645874e5SSudarsana Reddy Kalluru */ 1078645874e5SSudarsana Reddy Kalluru int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 107943645ce0SSudarsana Reddy Kalluru 108043645ce0SSudarsana Reddy Kalluru /** 1081cac6f691SSudarsana Reddy Kalluru * @brief Read ufp config from the shared memory. 1082cac6f691SSudarsana Reddy Kalluru * 1083cac6f691SSudarsana Reddy Kalluru * @param p_hwfn 1084cac6f691SSudarsana Reddy Kalluru * @param p_ptt 1085cac6f691SSudarsana Reddy Kalluru */ 1086cac6f691SSudarsana Reddy Kalluru void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 1087cac6f691SSudarsana Reddy Kalluru 1088cac6f691SSudarsana Reddy Kalluru /** 108943645ce0SSudarsana Reddy Kalluru * @brief Populate the nvm info shadow in the given hardware function 109043645ce0SSudarsana Reddy Kalluru * 109143645ce0SSudarsana Reddy Kalluru * @param p_hwfn 109243645ce0SSudarsana Reddy Kalluru */ 109343645ce0SSudarsana Reddy Kalluru int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn); 109443645ce0SSudarsana Reddy Kalluru 1095fe56b9e6SYuval Mintz #endif 1096