1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/types.h> 34 #include <asm/byteorder.h> 35 #include <linux/delay.h> 36 #include <linux/errno.h> 37 #include <linux/kernel.h> 38 #include <linux/slab.h> 39 #include <linux/spinlock.h> 40 #include <linux/string.h> 41 #include <linux/etherdevice.h> 42 #include "qed.h" 43 #include "qed_cxt.h" 44 #include "qed_dcbx.h" 45 #include "qed_hsi.h" 46 #include "qed_hw.h" 47 #include "qed_mcp.h" 48 #include "qed_reg_addr.h" 49 #include "qed_sriov.h" 50 51 #define QED_MCP_RESP_ITER_US 10 52 53 #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */ 54 #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */ 55 56 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ 57 qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \ 58 _val) 59 60 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ 61 qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset)) 62 63 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \ 64 DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \ 65 offsetof(struct public_drv_mb, _field), _val) 66 67 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \ 68 DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \ 69 offsetof(struct public_drv_mb, _field)) 70 71 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \ 72 DRV_ID_PDA_COMP_VER_SHIFT) 73 74 #define MCP_BYTES_PER_MBIT_SHIFT 17 75 76 bool qed_mcp_is_init(struct qed_hwfn *p_hwfn) 77 { 78 if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) 79 return false; 80 return true; 81 } 82 83 void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 84 { 85 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 86 PUBLIC_PORT); 87 u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr); 88 89 p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, 90 MFW_PORT(p_hwfn)); 91 DP_VERBOSE(p_hwfn, QED_MSG_SP, 92 "port_addr = 0x%x, port_id 0x%02x\n", 93 p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); 94 } 95 96 void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 97 { 98 u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); 99 u32 tmp, i; 100 101 if (!p_hwfn->mcp_info->public_base) 102 return; 103 104 for (i = 0; i < length; i++) { 105 tmp = qed_rd(p_hwfn, p_ptt, 106 p_hwfn->mcp_info->mfw_mb_addr + 107 (i << 2) + sizeof(u32)); 108 109 /* The MB data is actually BE; Need to force it to cpu */ 110 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] = 111 be32_to_cpu((__force __be32)tmp); 112 } 113 } 114 115 struct qed_mcp_cmd_elem { 116 struct list_head list; 117 struct qed_mcp_mb_params *p_mb_params; 118 u16 expected_seq_num; 119 bool b_is_completed; 120 }; 121 122 /* Must be called while cmd_lock is acquired */ 123 static struct qed_mcp_cmd_elem * 124 qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn, 125 struct qed_mcp_mb_params *p_mb_params, 126 u16 expected_seq_num) 127 { 128 struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 129 130 p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC); 131 if (!p_cmd_elem) 132 goto out; 133 134 p_cmd_elem->p_mb_params = p_mb_params; 135 p_cmd_elem->expected_seq_num = expected_seq_num; 136 list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list); 137 out: 138 return p_cmd_elem; 139 } 140 141 /* Must be called while cmd_lock is acquired */ 142 static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn, 143 struct qed_mcp_cmd_elem *p_cmd_elem) 144 { 145 list_del(&p_cmd_elem->list); 146 kfree(p_cmd_elem); 147 } 148 149 /* Must be called while cmd_lock is acquired */ 150 static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn, 151 u16 seq_num) 152 { 153 struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 154 155 list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) { 156 if (p_cmd_elem->expected_seq_num == seq_num) 157 return p_cmd_elem; 158 } 159 160 return NULL; 161 } 162 163 int qed_mcp_free(struct qed_hwfn *p_hwfn) 164 { 165 if (p_hwfn->mcp_info) { 166 struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp; 167 168 kfree(p_hwfn->mcp_info->mfw_mb_cur); 169 kfree(p_hwfn->mcp_info->mfw_mb_shadow); 170 171 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 172 list_for_each_entry_safe(p_cmd_elem, 173 p_tmp, 174 &p_hwfn->mcp_info->cmd_list, list) { 175 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 176 } 177 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 178 } 179 180 kfree(p_hwfn->mcp_info); 181 p_hwfn->mcp_info = NULL; 182 183 return 0; 184 } 185 186 /* Maximum of 1 sec to wait for the SHMEM ready indication */ 187 #define QED_MCP_SHMEM_RDY_MAX_RETRIES 20 188 #define QED_MCP_SHMEM_RDY_ITER_MS 50 189 190 static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 191 { 192 struct qed_mcp_info *p_info = p_hwfn->mcp_info; 193 u8 cnt = QED_MCP_SHMEM_RDY_MAX_RETRIES; 194 u8 msec = QED_MCP_SHMEM_RDY_ITER_MS; 195 u32 drv_mb_offsize, mfw_mb_offsize; 196 u32 mcp_pf_id = MCP_PF_ID(p_hwfn); 197 198 p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR); 199 if (!p_info->public_base) { 200 DP_NOTICE(p_hwfn, 201 "The address of the MCP scratch-pad is not configured\n"); 202 return -EINVAL; 203 } 204 205 p_info->public_base |= GRCBASE_MCP; 206 207 /* Get the MFW MB address and number of supported messages */ 208 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, 209 SECTION_OFFSIZE_ADDR(p_info->public_base, 210 PUBLIC_MFW_MB)); 211 p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id); 212 p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, 213 p_info->mfw_mb_addr + 214 offsetof(struct public_mfw_mb, 215 sup_msgs)); 216 217 /* The driver can notify that there was an MCP reset, and might read the 218 * SHMEM values before the MFW has completed initializing them. 219 * To avoid this, the "sup_msgs" field in the MFW mailbox is used as a 220 * data ready indication. 221 */ 222 while (!p_info->mfw_mb_length && --cnt) { 223 msleep(msec); 224 p_info->mfw_mb_length = 225 (u16)qed_rd(p_hwfn, p_ptt, 226 p_info->mfw_mb_addr + 227 offsetof(struct public_mfw_mb, sup_msgs)); 228 } 229 230 if (!cnt) { 231 DP_NOTICE(p_hwfn, 232 "Failed to get the SHMEM ready notification after %d msec\n", 233 QED_MCP_SHMEM_RDY_MAX_RETRIES * msec); 234 return -EBUSY; 235 } 236 237 /* Calculate the driver and MFW mailbox address */ 238 drv_mb_offsize = qed_rd(p_hwfn, p_ptt, 239 SECTION_OFFSIZE_ADDR(p_info->public_base, 240 PUBLIC_DRV_MB)); 241 p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id); 242 DP_VERBOSE(p_hwfn, QED_MSG_SP, 243 "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n", 244 drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id); 245 246 /* Get the current driver mailbox sequence before sending 247 * the first command 248 */ 249 p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 250 DRV_MSG_SEQ_NUMBER_MASK; 251 252 /* Get current FW pulse sequence */ 253 p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) & 254 DRV_PULSE_SEQ_MASK; 255 256 p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 257 258 return 0; 259 } 260 261 int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 262 { 263 struct qed_mcp_info *p_info; 264 u32 size; 265 266 /* Allocate mcp_info structure */ 267 p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL); 268 if (!p_hwfn->mcp_info) 269 goto err; 270 p_info = p_hwfn->mcp_info; 271 272 /* Initialize the MFW spinlock */ 273 spin_lock_init(&p_info->cmd_lock); 274 spin_lock_init(&p_info->link_lock); 275 276 INIT_LIST_HEAD(&p_info->cmd_list); 277 278 if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) { 279 DP_NOTICE(p_hwfn, "MCP is not initialized\n"); 280 /* Do not free mcp_info here, since public_base indicate that 281 * the MCP is not initialized 282 */ 283 return 0; 284 } 285 286 size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32); 287 p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL); 288 p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL); 289 if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow) 290 goto err; 291 292 return 0; 293 294 err: 295 qed_mcp_free(p_hwfn); 296 return -ENOMEM; 297 } 298 299 static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn, 300 struct qed_ptt *p_ptt) 301 { 302 u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 303 304 /* Use MCP history register to check if MCP reset occurred between init 305 * time and now. 306 */ 307 if (p_hwfn->mcp_info->mcp_hist != generic_por_0) { 308 DP_VERBOSE(p_hwfn, 309 QED_MSG_SP, 310 "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n", 311 p_hwfn->mcp_info->mcp_hist, generic_por_0); 312 313 qed_load_mcp_offsets(p_hwfn, p_ptt); 314 qed_mcp_cmd_port_init(p_hwfn, p_ptt); 315 } 316 } 317 318 int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 319 { 320 u32 org_mcp_reset_seq, seq, delay = QED_MCP_RESP_ITER_US, cnt = 0; 321 int rc = 0; 322 323 if (p_hwfn->mcp_info->b_block_cmd) { 324 DP_NOTICE(p_hwfn, 325 "The MFW is not responsive. Avoid sending MCP_RESET mailbox command.\n"); 326 return -EBUSY; 327 } 328 329 /* Ensure that only a single thread is accessing the mailbox */ 330 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 331 332 org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 333 334 /* Set drv command along with the updated sequence */ 335 qed_mcp_reread_offsets(p_hwfn, p_ptt); 336 seq = ++p_hwfn->mcp_info->drv_mb_seq; 337 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq)); 338 339 do { 340 /* Wait for MFW response */ 341 udelay(delay); 342 /* Give the FW up to 500 second (50*1000*10usec) */ 343 } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt, 344 MISCS_REG_GENERIC_POR_0)) && 345 (cnt++ < QED_MCP_RESET_RETRIES)); 346 347 if (org_mcp_reset_seq != 348 qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 349 DP_VERBOSE(p_hwfn, QED_MSG_SP, 350 "MCP was reset after %d usec\n", cnt * delay); 351 } else { 352 DP_ERR(p_hwfn, "Failed to reset MCP\n"); 353 rc = -EAGAIN; 354 } 355 356 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 357 358 return rc; 359 } 360 361 /* Must be called while cmd_lock is acquired */ 362 static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn) 363 { 364 struct qed_mcp_cmd_elem *p_cmd_elem; 365 366 /* There is at most one pending command at a certain time, and if it 367 * exists - it is placed at the HEAD of the list. 368 */ 369 if (!list_empty(&p_hwfn->mcp_info->cmd_list)) { 370 p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list, 371 struct qed_mcp_cmd_elem, list); 372 return !p_cmd_elem->b_is_completed; 373 } 374 375 return false; 376 } 377 378 /* Must be called while cmd_lock is acquired */ 379 static int 380 qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 381 { 382 struct qed_mcp_mb_params *p_mb_params; 383 struct qed_mcp_cmd_elem *p_cmd_elem; 384 u32 mcp_resp; 385 u16 seq_num; 386 387 mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header); 388 seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK); 389 390 /* Return if no new non-handled response has been received */ 391 if (seq_num != p_hwfn->mcp_info->drv_mb_seq) 392 return -EAGAIN; 393 394 p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num); 395 if (!p_cmd_elem) { 396 DP_ERR(p_hwfn, 397 "Failed to find a pending mailbox cmd that expects sequence number %d\n", 398 seq_num); 399 return -EINVAL; 400 } 401 402 p_mb_params = p_cmd_elem->p_mb_params; 403 404 /* Get the MFW response along with the sequence number */ 405 p_mb_params->mcp_resp = mcp_resp; 406 407 /* Get the MFW param */ 408 p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param); 409 410 /* Get the union data */ 411 if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) { 412 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 413 offsetof(struct public_drv_mb, 414 union_data); 415 qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst, 416 union_data_addr, p_mb_params->data_dst_size); 417 } 418 419 p_cmd_elem->b_is_completed = true; 420 421 return 0; 422 } 423 424 /* Must be called while cmd_lock is acquired */ 425 static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 426 struct qed_ptt *p_ptt, 427 struct qed_mcp_mb_params *p_mb_params, 428 u16 seq_num) 429 { 430 union drv_union_data union_data; 431 u32 union_data_addr; 432 433 /* Set the union data */ 434 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 435 offsetof(struct public_drv_mb, union_data); 436 memset(&union_data, 0, sizeof(union_data)); 437 if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size) 438 memcpy(&union_data, p_mb_params->p_data_src, 439 p_mb_params->data_src_size); 440 qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data, 441 sizeof(union_data)); 442 443 /* Set the drv param */ 444 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param); 445 446 /* Set the drv command along with the sequence number */ 447 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num)); 448 449 DP_VERBOSE(p_hwfn, QED_MSG_SP, 450 "MFW mailbox: command 0x%08x param 0x%08x\n", 451 (p_mb_params->cmd | seq_num), p_mb_params->param); 452 } 453 454 static void qed_mcp_cmd_set_blocking(struct qed_hwfn *p_hwfn, bool block_cmd) 455 { 456 p_hwfn->mcp_info->b_block_cmd = block_cmd; 457 458 DP_INFO(p_hwfn, "%s sending of mailbox commands to the MFW\n", 459 block_cmd ? "Block" : "Unblock"); 460 } 461 462 static void qed_mcp_print_cpu_info(struct qed_hwfn *p_hwfn, 463 struct qed_ptt *p_ptt) 464 { 465 u32 cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2; 466 u32 delay = QED_MCP_RESP_ITER_US; 467 468 cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 469 cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 470 cpu_pc_0 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 471 udelay(delay); 472 cpu_pc_1 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 473 udelay(delay); 474 cpu_pc_2 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 475 476 DP_NOTICE(p_hwfn, 477 "MCP CPU info: mode 0x%08x, state 0x%08x, pc {0x%08x, 0x%08x, 0x%08x}\n", 478 cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2); 479 } 480 481 static int 482 _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 483 struct qed_ptt *p_ptt, 484 struct qed_mcp_mb_params *p_mb_params, 485 u32 max_retries, u32 usecs) 486 { 487 u32 cnt = 0, msecs = DIV_ROUND_UP(usecs, 1000); 488 struct qed_mcp_cmd_elem *p_cmd_elem; 489 u16 seq_num; 490 int rc = 0; 491 492 /* Wait until the mailbox is non-occupied */ 493 do { 494 /* Exit the loop if there is no pending command, or if the 495 * pending command is completed during this iteration. 496 * The spinlock stays locked until the command is sent. 497 */ 498 499 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 500 501 if (!qed_mcp_has_pending_cmd(p_hwfn)) 502 break; 503 504 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 505 if (!rc) 506 break; 507 else if (rc != -EAGAIN) 508 goto err; 509 510 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 511 512 if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) 513 msleep(msecs); 514 else 515 udelay(usecs); 516 } while (++cnt < max_retries); 517 518 if (cnt >= max_retries) { 519 DP_NOTICE(p_hwfn, 520 "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n", 521 p_mb_params->cmd, p_mb_params->param); 522 return -EAGAIN; 523 } 524 525 /* Send the mailbox command */ 526 qed_mcp_reread_offsets(p_hwfn, p_ptt); 527 seq_num = ++p_hwfn->mcp_info->drv_mb_seq; 528 p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num); 529 if (!p_cmd_elem) { 530 rc = -ENOMEM; 531 goto err; 532 } 533 534 __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num); 535 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 536 537 /* Wait for the MFW response */ 538 do { 539 /* Exit the loop if the command is already completed, or if the 540 * command is completed during this iteration. 541 * The spinlock stays locked until the list element is removed. 542 */ 543 544 if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) 545 msleep(msecs); 546 else 547 udelay(usecs); 548 549 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 550 551 if (p_cmd_elem->b_is_completed) 552 break; 553 554 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 555 if (!rc) 556 break; 557 else if (rc != -EAGAIN) 558 goto err; 559 560 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 561 } while (++cnt < max_retries); 562 563 if (cnt >= max_retries) { 564 DP_NOTICE(p_hwfn, 565 "The MFW failed to respond to command 0x%08x [param 0x%08x].\n", 566 p_mb_params->cmd, p_mb_params->param); 567 qed_mcp_print_cpu_info(p_hwfn, p_ptt); 568 569 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 570 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 571 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 572 573 if (!QED_MB_FLAGS_IS_SET(p_mb_params, AVOID_BLOCK)) 574 qed_mcp_cmd_set_blocking(p_hwfn, true); 575 576 return -EAGAIN; 577 } 578 579 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 580 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 581 582 DP_VERBOSE(p_hwfn, 583 QED_MSG_SP, 584 "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n", 585 p_mb_params->mcp_resp, 586 p_mb_params->mcp_param, 587 (cnt * usecs) / 1000, (cnt * usecs) % 1000); 588 589 /* Clear the sequence number from the MFW response */ 590 p_mb_params->mcp_resp &= FW_MSG_CODE_MASK; 591 592 return 0; 593 594 err: 595 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 596 return rc; 597 } 598 599 static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 600 struct qed_ptt *p_ptt, 601 struct qed_mcp_mb_params *p_mb_params) 602 { 603 size_t union_data_size = sizeof(union drv_union_data); 604 u32 max_retries = QED_DRV_MB_MAX_RETRIES; 605 u32 usecs = QED_MCP_RESP_ITER_US; 606 607 /* MCP not initialized */ 608 if (!qed_mcp_is_init(p_hwfn)) { 609 DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 610 return -EBUSY; 611 } 612 613 if (p_hwfn->mcp_info->b_block_cmd) { 614 DP_NOTICE(p_hwfn, 615 "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n", 616 p_mb_params->cmd, p_mb_params->param); 617 return -EBUSY; 618 } 619 620 if (p_mb_params->data_src_size > union_data_size || 621 p_mb_params->data_dst_size > union_data_size) { 622 DP_ERR(p_hwfn, 623 "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n", 624 p_mb_params->data_src_size, 625 p_mb_params->data_dst_size, union_data_size); 626 return -EINVAL; 627 } 628 629 if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) { 630 max_retries = DIV_ROUND_UP(max_retries, 1000); 631 usecs *= 1000; 632 } 633 634 return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries, 635 usecs); 636 } 637 638 int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 639 struct qed_ptt *p_ptt, 640 u32 cmd, 641 u32 param, 642 u32 *o_mcp_resp, 643 u32 *o_mcp_param) 644 { 645 struct qed_mcp_mb_params mb_params; 646 int rc; 647 648 memset(&mb_params, 0, sizeof(mb_params)); 649 mb_params.cmd = cmd; 650 mb_params.param = param; 651 652 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 653 if (rc) 654 return rc; 655 656 *o_mcp_resp = mb_params.mcp_resp; 657 *o_mcp_param = mb_params.mcp_param; 658 659 return 0; 660 } 661 662 static int 663 qed_mcp_nvm_wr_cmd(struct qed_hwfn *p_hwfn, 664 struct qed_ptt *p_ptt, 665 u32 cmd, 666 u32 param, 667 u32 *o_mcp_resp, 668 u32 *o_mcp_param, u32 i_txn_size, u32 *i_buf) 669 { 670 struct qed_mcp_mb_params mb_params; 671 int rc; 672 673 memset(&mb_params, 0, sizeof(mb_params)); 674 mb_params.cmd = cmd; 675 mb_params.param = param; 676 mb_params.p_data_src = i_buf; 677 mb_params.data_src_size = (u8)i_txn_size; 678 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 679 if (rc) 680 return rc; 681 682 *o_mcp_resp = mb_params.mcp_resp; 683 *o_mcp_param = mb_params.mcp_param; 684 685 /* nvm_info needs to be updated */ 686 p_hwfn->nvm_info.valid = false; 687 688 return 0; 689 } 690 691 int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 692 struct qed_ptt *p_ptt, 693 u32 cmd, 694 u32 param, 695 u32 *o_mcp_resp, 696 u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf) 697 { 698 struct qed_mcp_mb_params mb_params; 699 u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 700 int rc; 701 702 memset(&mb_params, 0, sizeof(mb_params)); 703 mb_params.cmd = cmd; 704 mb_params.param = param; 705 mb_params.p_data_dst = raw_data; 706 707 /* Use the maximal value since the actual one is part of the response */ 708 mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN; 709 710 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 711 if (rc) 712 return rc; 713 714 *o_mcp_resp = mb_params.mcp_resp; 715 *o_mcp_param = mb_params.mcp_param; 716 717 *o_txn_size = *o_mcp_param; 718 memcpy(o_buf, raw_data, *o_txn_size); 719 720 return 0; 721 } 722 723 static bool 724 qed_mcp_can_force_load(u8 drv_role, 725 u8 exist_drv_role, 726 enum qed_override_force_load override_force_load) 727 { 728 bool can_force_load = false; 729 730 switch (override_force_load) { 731 case QED_OVERRIDE_FORCE_LOAD_ALWAYS: 732 can_force_load = true; 733 break; 734 case QED_OVERRIDE_FORCE_LOAD_NEVER: 735 can_force_load = false; 736 break; 737 default: 738 can_force_load = (drv_role == DRV_ROLE_OS && 739 exist_drv_role == DRV_ROLE_PREBOOT) || 740 (drv_role == DRV_ROLE_KDUMP && 741 exist_drv_role == DRV_ROLE_OS); 742 break; 743 } 744 745 return can_force_load; 746 } 747 748 static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn, 749 struct qed_ptt *p_ptt) 750 { 751 u32 resp = 0, param = 0; 752 int rc; 753 754 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0, 755 &resp, ¶m); 756 if (rc) 757 DP_NOTICE(p_hwfn, 758 "Failed to send cancel load request, rc = %d\n", rc); 759 760 return rc; 761 } 762 763 #define CONFIG_QEDE_BITMAP_IDX BIT(0) 764 #define CONFIG_QED_SRIOV_BITMAP_IDX BIT(1) 765 #define CONFIG_QEDR_BITMAP_IDX BIT(2) 766 #define CONFIG_QEDF_BITMAP_IDX BIT(4) 767 #define CONFIG_QEDI_BITMAP_IDX BIT(5) 768 #define CONFIG_QED_LL2_BITMAP_IDX BIT(6) 769 770 static u32 qed_get_config_bitmap(void) 771 { 772 u32 config_bitmap = 0x0; 773 774 if (IS_ENABLED(CONFIG_QEDE)) 775 config_bitmap |= CONFIG_QEDE_BITMAP_IDX; 776 777 if (IS_ENABLED(CONFIG_QED_SRIOV)) 778 config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX; 779 780 if (IS_ENABLED(CONFIG_QED_RDMA)) 781 config_bitmap |= CONFIG_QEDR_BITMAP_IDX; 782 783 if (IS_ENABLED(CONFIG_QED_FCOE)) 784 config_bitmap |= CONFIG_QEDF_BITMAP_IDX; 785 786 if (IS_ENABLED(CONFIG_QED_ISCSI)) 787 config_bitmap |= CONFIG_QEDI_BITMAP_IDX; 788 789 if (IS_ENABLED(CONFIG_QED_LL2)) 790 config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX; 791 792 return config_bitmap; 793 } 794 795 struct qed_load_req_in_params { 796 u8 hsi_ver; 797 #define QED_LOAD_REQ_HSI_VER_DEFAULT 0 798 #define QED_LOAD_REQ_HSI_VER_1 1 799 u32 drv_ver_0; 800 u32 drv_ver_1; 801 u32 fw_ver; 802 u8 drv_role; 803 u8 timeout_val; 804 u8 force_cmd; 805 bool avoid_eng_reset; 806 }; 807 808 struct qed_load_req_out_params { 809 u32 load_code; 810 u32 exist_drv_ver_0; 811 u32 exist_drv_ver_1; 812 u32 exist_fw_ver; 813 u8 exist_drv_role; 814 u8 mfw_hsi_ver; 815 bool drv_exists; 816 }; 817 818 static int 819 __qed_mcp_load_req(struct qed_hwfn *p_hwfn, 820 struct qed_ptt *p_ptt, 821 struct qed_load_req_in_params *p_in_params, 822 struct qed_load_req_out_params *p_out_params) 823 { 824 struct qed_mcp_mb_params mb_params; 825 struct load_req_stc load_req; 826 struct load_rsp_stc load_rsp; 827 u32 hsi_ver; 828 int rc; 829 830 memset(&load_req, 0, sizeof(load_req)); 831 load_req.drv_ver_0 = p_in_params->drv_ver_0; 832 load_req.drv_ver_1 = p_in_params->drv_ver_1; 833 load_req.fw_ver = p_in_params->fw_ver; 834 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role); 835 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO, 836 p_in_params->timeout_val); 837 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE, 838 p_in_params->force_cmd); 839 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0, 840 p_in_params->avoid_eng_reset); 841 842 hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ? 843 DRV_ID_MCP_HSI_VER_CURRENT : 844 (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT); 845 846 memset(&mb_params, 0, sizeof(mb_params)); 847 mb_params.cmd = DRV_MSG_CODE_LOAD_REQ; 848 mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type; 849 mb_params.p_data_src = &load_req; 850 mb_params.data_src_size = sizeof(load_req); 851 mb_params.p_data_dst = &load_rsp; 852 mb_params.data_dst_size = sizeof(load_rsp); 853 mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK; 854 855 DP_VERBOSE(p_hwfn, QED_MSG_SP, 856 "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n", 857 mb_params.param, 858 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW), 859 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE), 860 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER), 861 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER)); 862 863 if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) { 864 DP_VERBOSE(p_hwfn, QED_MSG_SP, 865 "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n", 866 load_req.drv_ver_0, 867 load_req.drv_ver_1, 868 load_req.fw_ver, 869 load_req.misc0, 870 QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE), 871 QED_MFW_GET_FIELD(load_req.misc0, 872 LOAD_REQ_LOCK_TO), 873 QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE), 874 QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0)); 875 } 876 877 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 878 if (rc) { 879 DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc); 880 return rc; 881 } 882 883 DP_VERBOSE(p_hwfn, QED_MSG_SP, 884 "Load Response: resp 0x%08x\n", mb_params.mcp_resp); 885 p_out_params->load_code = mb_params.mcp_resp; 886 887 if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 888 p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 889 DP_VERBOSE(p_hwfn, 890 QED_MSG_SP, 891 "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n", 892 load_rsp.drv_ver_0, 893 load_rsp.drv_ver_1, 894 load_rsp.fw_ver, 895 load_rsp.misc0, 896 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE), 897 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI), 898 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0)); 899 900 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0; 901 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1; 902 p_out_params->exist_fw_ver = load_rsp.fw_ver; 903 p_out_params->exist_drv_role = 904 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE); 905 p_out_params->mfw_hsi_ver = 906 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI); 907 p_out_params->drv_exists = 908 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) & 909 LOAD_RSP_FLAGS0_DRV_EXISTS; 910 } 911 912 return 0; 913 } 914 915 static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn, 916 enum qed_drv_role drv_role, 917 u8 *p_mfw_drv_role) 918 { 919 switch (drv_role) { 920 case QED_DRV_ROLE_OS: 921 *p_mfw_drv_role = DRV_ROLE_OS; 922 break; 923 case QED_DRV_ROLE_KDUMP: 924 *p_mfw_drv_role = DRV_ROLE_KDUMP; 925 break; 926 default: 927 DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role); 928 return -EINVAL; 929 } 930 931 return 0; 932 } 933 934 enum qed_load_req_force { 935 QED_LOAD_REQ_FORCE_NONE, 936 QED_LOAD_REQ_FORCE_PF, 937 QED_LOAD_REQ_FORCE_ALL, 938 }; 939 940 static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn, 941 942 enum qed_load_req_force force_cmd, 943 u8 *p_mfw_force_cmd) 944 { 945 switch (force_cmd) { 946 case QED_LOAD_REQ_FORCE_NONE: 947 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE; 948 break; 949 case QED_LOAD_REQ_FORCE_PF: 950 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF; 951 break; 952 case QED_LOAD_REQ_FORCE_ALL: 953 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL; 954 break; 955 } 956 } 957 958 int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 959 struct qed_ptt *p_ptt, 960 struct qed_load_req_params *p_params) 961 { 962 struct qed_load_req_out_params out_params; 963 struct qed_load_req_in_params in_params; 964 u8 mfw_drv_role, mfw_force_cmd; 965 int rc; 966 967 memset(&in_params, 0, sizeof(in_params)); 968 in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT; 969 in_params.drv_ver_0 = QED_VERSION; 970 in_params.drv_ver_1 = qed_get_config_bitmap(); 971 in_params.fw_ver = STORM_FW_VERSION; 972 rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role); 973 if (rc) 974 return rc; 975 976 in_params.drv_role = mfw_drv_role; 977 in_params.timeout_val = p_params->timeout_val; 978 qed_get_mfw_force_cmd(p_hwfn, 979 QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd); 980 981 in_params.force_cmd = mfw_force_cmd; 982 in_params.avoid_eng_reset = p_params->avoid_eng_reset; 983 984 memset(&out_params, 0, sizeof(out_params)); 985 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 986 if (rc) 987 return rc; 988 989 /* First handle cases where another load request should/might be sent: 990 * - MFW expects the old interface [HSI version = 1] 991 * - MFW responds that a force load request is required 992 */ 993 if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 994 DP_INFO(p_hwfn, 995 "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n"); 996 997 in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1; 998 memset(&out_params, 0, sizeof(out_params)); 999 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 1000 if (rc) 1001 return rc; 1002 } else if (out_params.load_code == 1003 FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) { 1004 if (qed_mcp_can_force_load(in_params.drv_role, 1005 out_params.exist_drv_role, 1006 p_params->override_force_load)) { 1007 DP_INFO(p_hwfn, 1008 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n", 1009 in_params.drv_role, in_params.fw_ver, 1010 in_params.drv_ver_0, in_params.drv_ver_1, 1011 out_params.exist_drv_role, 1012 out_params.exist_fw_ver, 1013 out_params.exist_drv_ver_0, 1014 out_params.exist_drv_ver_1); 1015 1016 qed_get_mfw_force_cmd(p_hwfn, 1017 QED_LOAD_REQ_FORCE_ALL, 1018 &mfw_force_cmd); 1019 1020 in_params.force_cmd = mfw_force_cmd; 1021 memset(&out_params, 0, sizeof(out_params)); 1022 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, 1023 &out_params); 1024 if (rc) 1025 return rc; 1026 } else { 1027 DP_NOTICE(p_hwfn, 1028 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n", 1029 in_params.drv_role, in_params.fw_ver, 1030 in_params.drv_ver_0, in_params.drv_ver_1, 1031 out_params.exist_drv_role, 1032 out_params.exist_fw_ver, 1033 out_params.exist_drv_ver_0, 1034 out_params.exist_drv_ver_1); 1035 DP_NOTICE(p_hwfn, 1036 "Avoid sending a force load request to prevent disruption of active PFs\n"); 1037 1038 qed_mcp_cancel_load_req(p_hwfn, p_ptt); 1039 return -EBUSY; 1040 } 1041 } 1042 1043 /* Now handle the other types of responses. 1044 * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not 1045 * expected here after the additional revised load requests were sent. 1046 */ 1047 switch (out_params.load_code) { 1048 case FW_MSG_CODE_DRV_LOAD_ENGINE: 1049 case FW_MSG_CODE_DRV_LOAD_PORT: 1050 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 1051 if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 1052 out_params.drv_exists) { 1053 /* The role and fw/driver version match, but the PF is 1054 * already loaded and has not been unloaded gracefully. 1055 */ 1056 DP_NOTICE(p_hwfn, 1057 "PF is already loaded\n"); 1058 return -EINVAL; 1059 } 1060 break; 1061 default: 1062 DP_NOTICE(p_hwfn, 1063 "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n", 1064 out_params.load_code); 1065 return -EBUSY; 1066 } 1067 1068 p_params->load_code = out_params.load_code; 1069 1070 return 0; 1071 } 1072 1073 int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1074 { 1075 struct qed_mcp_mb_params mb_params; 1076 u32 wol_param; 1077 1078 switch (p_hwfn->cdev->wol_config) { 1079 case QED_OV_WOL_DISABLED: 1080 wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED; 1081 break; 1082 case QED_OV_WOL_ENABLED: 1083 wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED; 1084 break; 1085 default: 1086 DP_NOTICE(p_hwfn, 1087 "Unknown WoL configuration %02x\n", 1088 p_hwfn->cdev->wol_config); 1089 /* Fallthrough */ 1090 case QED_OV_WOL_DEFAULT: 1091 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP; 1092 } 1093 1094 memset(&mb_params, 0, sizeof(mb_params)); 1095 mb_params.cmd = DRV_MSG_CODE_UNLOAD_REQ; 1096 mb_params.param = wol_param; 1097 mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK; 1098 1099 return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1100 } 1101 1102 int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1103 { 1104 struct qed_mcp_mb_params mb_params; 1105 struct mcp_mac wol_mac; 1106 1107 memset(&mb_params, 0, sizeof(mb_params)); 1108 mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE; 1109 1110 /* Set the primary MAC if WoL is enabled */ 1111 if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) { 1112 u8 *p_mac = p_hwfn->cdev->wol_mac; 1113 1114 memset(&wol_mac, 0, sizeof(wol_mac)); 1115 wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1]; 1116 wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 | 1117 p_mac[4] << 8 | p_mac[5]; 1118 1119 DP_VERBOSE(p_hwfn, 1120 (QED_MSG_SP | NETIF_MSG_IFDOWN), 1121 "Setting WoL MAC: %pM --> [%08x,%08x]\n", 1122 p_mac, wol_mac.mac_upper, wol_mac.mac_lower); 1123 1124 mb_params.p_data_src = &wol_mac; 1125 mb_params.data_src_size = sizeof(wol_mac); 1126 } 1127 1128 return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1129 } 1130 1131 static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn, 1132 struct qed_ptt *p_ptt) 1133 { 1134 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 1135 PUBLIC_PATH); 1136 u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 1137 u32 path_addr = SECTION_ADDR(mfw_path_offsize, 1138 QED_PATH_ID(p_hwfn)); 1139 u32 disabled_vfs[VF_MAX_STATIC / 32]; 1140 int i; 1141 1142 DP_VERBOSE(p_hwfn, 1143 QED_MSG_SP, 1144 "Reading Disabled VF information from [offset %08x], path_addr %08x\n", 1145 mfw_path_offsize, path_addr); 1146 1147 for (i = 0; i < (VF_MAX_STATIC / 32); i++) { 1148 disabled_vfs[i] = qed_rd(p_hwfn, p_ptt, 1149 path_addr + 1150 offsetof(struct public_path, 1151 mcp_vf_disabled) + 1152 sizeof(u32) * i); 1153 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 1154 "FLR-ed VFs [%08x,...,%08x] - %08x\n", 1155 i * 32, (i + 1) * 32 - 1, disabled_vfs[i]); 1156 } 1157 1158 if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs)) 1159 qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); 1160 } 1161 1162 int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 1163 struct qed_ptt *p_ptt, u32 *vfs_to_ack) 1164 { 1165 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 1166 PUBLIC_FUNC); 1167 u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr); 1168 u32 func_addr = SECTION_ADDR(mfw_func_offsize, 1169 MCP_PF_ID(p_hwfn)); 1170 struct qed_mcp_mb_params mb_params; 1171 int rc; 1172 int i; 1173 1174 for (i = 0; i < (VF_MAX_STATIC / 32); i++) 1175 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 1176 "Acking VFs [%08x,...,%08x] - %08x\n", 1177 i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]); 1178 1179 memset(&mb_params, 0, sizeof(mb_params)); 1180 mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE; 1181 mb_params.p_data_src = vfs_to_ack; 1182 mb_params.data_src_size = VF_MAX_STATIC / 8; 1183 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1184 if (rc) { 1185 DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n"); 1186 return -EBUSY; 1187 } 1188 1189 /* Clear the ACK bits */ 1190 for (i = 0; i < (VF_MAX_STATIC / 32); i++) 1191 qed_wr(p_hwfn, p_ptt, 1192 func_addr + 1193 offsetof(struct public_func, drv_ack_vf_disabled) + 1194 i * sizeof(u32), 0); 1195 1196 return rc; 1197 } 1198 1199 static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn, 1200 struct qed_ptt *p_ptt) 1201 { 1202 u32 transceiver_state; 1203 1204 transceiver_state = qed_rd(p_hwfn, p_ptt, 1205 p_hwfn->mcp_info->port_addr + 1206 offsetof(struct public_port, 1207 transceiver_data)); 1208 1209 DP_VERBOSE(p_hwfn, 1210 (NETIF_MSG_HW | QED_MSG_SP), 1211 "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n", 1212 transceiver_state, 1213 (u32)(p_hwfn->mcp_info->port_addr + 1214 offsetof(struct public_port, transceiver_data))); 1215 1216 transceiver_state = GET_FIELD(transceiver_state, 1217 ETH_TRANSCEIVER_STATE); 1218 1219 if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 1220 DP_NOTICE(p_hwfn, "Transceiver is present.\n"); 1221 else 1222 DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n"); 1223 } 1224 1225 static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn, 1226 struct qed_ptt *p_ptt, 1227 struct qed_mcp_link_state *p_link) 1228 { 1229 u32 eee_status, val; 1230 1231 p_link->eee_adv_caps = 0; 1232 p_link->eee_lp_adv_caps = 0; 1233 eee_status = qed_rd(p_hwfn, 1234 p_ptt, 1235 p_hwfn->mcp_info->port_addr + 1236 offsetof(struct public_port, eee_status)); 1237 p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT); 1238 val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET; 1239 if (val & EEE_1G_ADV) 1240 p_link->eee_adv_caps |= QED_EEE_1G_ADV; 1241 if (val & EEE_10G_ADV) 1242 p_link->eee_adv_caps |= QED_EEE_10G_ADV; 1243 val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET; 1244 if (val & EEE_1G_ADV) 1245 p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV; 1246 if (val & EEE_10G_ADV) 1247 p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV; 1248 } 1249 1250 static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn, 1251 struct qed_ptt *p_ptt, 1252 struct public_func *p_data, int pfid) 1253 { 1254 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 1255 PUBLIC_FUNC); 1256 u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 1257 u32 func_addr; 1258 u32 i, size; 1259 1260 func_addr = SECTION_ADDR(mfw_path_offsize, pfid); 1261 memset(p_data, 0, sizeof(*p_data)); 1262 1263 size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize)); 1264 for (i = 0; i < size / sizeof(u32); i++) 1265 ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt, 1266 func_addr + (i << 2)); 1267 return size; 1268 } 1269 1270 static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn, 1271 struct public_func *p_shmem_info) 1272 { 1273 struct qed_mcp_function_info *p_info; 1274 1275 p_info = &p_hwfn->mcp_info->func_info; 1276 1277 p_info->bandwidth_min = QED_MFW_GET_FIELD(p_shmem_info->config, 1278 FUNC_MF_CFG_MIN_BW); 1279 if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) { 1280 DP_INFO(p_hwfn, 1281 "bandwidth minimum out of bounds [%02x]. Set to 1\n", 1282 p_info->bandwidth_min); 1283 p_info->bandwidth_min = 1; 1284 } 1285 1286 p_info->bandwidth_max = QED_MFW_GET_FIELD(p_shmem_info->config, 1287 FUNC_MF_CFG_MAX_BW); 1288 if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) { 1289 DP_INFO(p_hwfn, 1290 "bandwidth maximum out of bounds [%02x]. Set to 100\n", 1291 p_info->bandwidth_max); 1292 p_info->bandwidth_max = 100; 1293 } 1294 } 1295 1296 static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn, 1297 struct qed_ptt *p_ptt, bool b_reset) 1298 { 1299 struct qed_mcp_link_state *p_link; 1300 u8 max_bw, min_bw; 1301 u32 status = 0; 1302 1303 /* Prevent SW/attentions from doing this at the same time */ 1304 spin_lock_bh(&p_hwfn->mcp_info->link_lock); 1305 1306 p_link = &p_hwfn->mcp_info->link_output; 1307 memset(p_link, 0, sizeof(*p_link)); 1308 if (!b_reset) { 1309 status = qed_rd(p_hwfn, p_ptt, 1310 p_hwfn->mcp_info->port_addr + 1311 offsetof(struct public_port, link_status)); 1312 DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP), 1313 "Received link update [0x%08x] from mfw [Addr 0x%x]\n", 1314 status, 1315 (u32)(p_hwfn->mcp_info->port_addr + 1316 offsetof(struct public_port, link_status))); 1317 } else { 1318 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1319 "Resetting link indications\n"); 1320 goto out; 1321 } 1322 1323 if (p_hwfn->b_drv_link_init) { 1324 /* Link indication with modern MFW arrives as per-PF 1325 * indication. 1326 */ 1327 if (p_hwfn->mcp_info->capabilities & 1328 FW_MB_PARAM_FEATURE_SUPPORT_VLINK) { 1329 struct public_func shmem_info; 1330 1331 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, 1332 MCP_PF_ID(p_hwfn)); 1333 p_link->link_up = !!(shmem_info.status & 1334 FUNC_STATUS_VIRTUAL_LINK_UP); 1335 qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1336 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1337 "Virtual link_up = %d\n", p_link->link_up); 1338 } else { 1339 p_link->link_up = !!(status & LINK_STATUS_LINK_UP); 1340 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1341 "Physical link_up = %d\n", p_link->link_up); 1342 } 1343 } else { 1344 p_link->link_up = false; 1345 } 1346 1347 p_link->full_duplex = true; 1348 switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) { 1349 case LINK_STATUS_SPEED_AND_DUPLEX_100G: 1350 p_link->speed = 100000; 1351 break; 1352 case LINK_STATUS_SPEED_AND_DUPLEX_50G: 1353 p_link->speed = 50000; 1354 break; 1355 case LINK_STATUS_SPEED_AND_DUPLEX_40G: 1356 p_link->speed = 40000; 1357 break; 1358 case LINK_STATUS_SPEED_AND_DUPLEX_25G: 1359 p_link->speed = 25000; 1360 break; 1361 case LINK_STATUS_SPEED_AND_DUPLEX_20G: 1362 p_link->speed = 20000; 1363 break; 1364 case LINK_STATUS_SPEED_AND_DUPLEX_10G: 1365 p_link->speed = 10000; 1366 break; 1367 case LINK_STATUS_SPEED_AND_DUPLEX_1000THD: 1368 p_link->full_duplex = false; 1369 /* Fall-through */ 1370 case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD: 1371 p_link->speed = 1000; 1372 break; 1373 default: 1374 p_link->speed = 0; 1375 p_link->link_up = 0; 1376 } 1377 1378 if (p_link->link_up && p_link->speed) 1379 p_link->line_speed = p_link->speed; 1380 else 1381 p_link->line_speed = 0; 1382 1383 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max; 1384 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min; 1385 1386 /* Max bandwidth configuration */ 1387 __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw); 1388 1389 /* Min bandwidth configuration */ 1390 __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw); 1391 qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt, 1392 p_link->min_pf_rate); 1393 1394 p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); 1395 p_link->an_complete = !!(status & 1396 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE); 1397 p_link->parallel_detection = !!(status & 1398 LINK_STATUS_PARALLEL_DETECTION_USED); 1399 p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED); 1400 1401 p_link->partner_adv_speed |= 1402 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ? 1403 QED_LINK_PARTNER_SPEED_1G_FD : 0; 1404 p_link->partner_adv_speed |= 1405 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ? 1406 QED_LINK_PARTNER_SPEED_1G_HD : 0; 1407 p_link->partner_adv_speed |= 1408 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ? 1409 QED_LINK_PARTNER_SPEED_10G : 0; 1410 p_link->partner_adv_speed |= 1411 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ? 1412 QED_LINK_PARTNER_SPEED_20G : 0; 1413 p_link->partner_adv_speed |= 1414 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ? 1415 QED_LINK_PARTNER_SPEED_25G : 0; 1416 p_link->partner_adv_speed |= 1417 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ? 1418 QED_LINK_PARTNER_SPEED_40G : 0; 1419 p_link->partner_adv_speed |= 1420 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ? 1421 QED_LINK_PARTNER_SPEED_50G : 0; 1422 p_link->partner_adv_speed |= 1423 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ? 1424 QED_LINK_PARTNER_SPEED_100G : 0; 1425 1426 p_link->partner_tx_flow_ctrl_en = 1427 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED); 1428 p_link->partner_rx_flow_ctrl_en = 1429 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 1430 1431 switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) { 1432 case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE: 1433 p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE; 1434 break; 1435 case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE: 1436 p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE; 1437 break; 1438 case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE: 1439 p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE; 1440 break; 1441 default: 1442 p_link->partner_adv_pause = 0; 1443 } 1444 1445 p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT); 1446 1447 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) 1448 qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link); 1449 1450 qed_link_update(p_hwfn); 1451 out: 1452 spin_unlock_bh(&p_hwfn->mcp_info->link_lock); 1453 } 1454 1455 int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up) 1456 { 1457 struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input; 1458 struct qed_mcp_mb_params mb_params; 1459 struct eth_phy_cfg phy_cfg; 1460 int rc = 0; 1461 u32 cmd; 1462 1463 /* Set the shmem configuration according to params */ 1464 memset(&phy_cfg, 0, sizeof(phy_cfg)); 1465 cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET; 1466 if (!params->speed.autoneg) 1467 phy_cfg.speed = params->speed.forced_speed; 1468 phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0; 1469 phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0; 1470 phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0; 1471 phy_cfg.adv_speed = params->speed.advertised_speeds; 1472 phy_cfg.loopback_mode = params->loopback_mode; 1473 1474 /* There are MFWs that share this capability regardless of whether 1475 * this is feasible or not. And given that at the very least adv_caps 1476 * would be set internally by qed, we want to make sure LFA would 1477 * still work. 1478 */ 1479 if ((p_hwfn->mcp_info->capabilities & 1480 FW_MB_PARAM_FEATURE_SUPPORT_EEE) && params->eee.enable) { 1481 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED; 1482 if (params->eee.tx_lpi_enable) 1483 phy_cfg.eee_cfg |= EEE_CFG_TX_LPI; 1484 if (params->eee.adv_caps & QED_EEE_1G_ADV) 1485 phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G; 1486 if (params->eee.adv_caps & QED_EEE_10G_ADV) 1487 phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G; 1488 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer << 1489 EEE_TX_TIMER_USEC_OFFSET) & 1490 EEE_TX_TIMER_USEC_MASK; 1491 } 1492 1493 p_hwfn->b_drv_link_init = b_up; 1494 1495 if (b_up) { 1496 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1497 "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n", 1498 phy_cfg.speed, 1499 phy_cfg.pause, 1500 phy_cfg.adv_speed, 1501 phy_cfg.loopback_mode, 1502 phy_cfg.feature_config_flags); 1503 } else { 1504 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1505 "Resetting link\n"); 1506 } 1507 1508 memset(&mb_params, 0, sizeof(mb_params)); 1509 mb_params.cmd = cmd; 1510 mb_params.p_data_src = &phy_cfg; 1511 mb_params.data_src_size = sizeof(phy_cfg); 1512 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1513 1514 /* if mcp fails to respond we must abort */ 1515 if (rc) { 1516 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1517 return rc; 1518 } 1519 1520 /* Mimic link-change attention, done for several reasons: 1521 * - On reset, there's no guarantee MFW would trigger 1522 * an attention. 1523 * - On initialization, older MFWs might not indicate link change 1524 * during LFA, so we'll never get an UP indication. 1525 */ 1526 qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up); 1527 1528 return 0; 1529 } 1530 1531 static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn, 1532 struct qed_ptt *p_ptt, 1533 enum MFW_DRV_MSG_TYPE type) 1534 { 1535 enum qed_mcp_protocol_type stats_type; 1536 union qed_mcp_protocol_stats stats; 1537 struct qed_mcp_mb_params mb_params; 1538 u32 hsi_param; 1539 1540 switch (type) { 1541 case MFW_DRV_MSG_GET_LAN_STATS: 1542 stats_type = QED_MCP_LAN_STATS; 1543 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN; 1544 break; 1545 case MFW_DRV_MSG_GET_FCOE_STATS: 1546 stats_type = QED_MCP_FCOE_STATS; 1547 hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE; 1548 break; 1549 case MFW_DRV_MSG_GET_ISCSI_STATS: 1550 stats_type = QED_MCP_ISCSI_STATS; 1551 hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI; 1552 break; 1553 case MFW_DRV_MSG_GET_RDMA_STATS: 1554 stats_type = QED_MCP_RDMA_STATS; 1555 hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA; 1556 break; 1557 default: 1558 DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type); 1559 return; 1560 } 1561 1562 qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats); 1563 1564 memset(&mb_params, 0, sizeof(mb_params)); 1565 mb_params.cmd = DRV_MSG_CODE_GET_STATS; 1566 mb_params.param = hsi_param; 1567 mb_params.p_data_src = &stats; 1568 mb_params.data_src_size = sizeof(stats); 1569 qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1570 } 1571 1572 static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1573 { 1574 struct qed_mcp_function_info *p_info; 1575 struct public_func shmem_info; 1576 u32 resp = 0, param = 0; 1577 1578 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1579 1580 qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1581 1582 p_info = &p_hwfn->mcp_info->func_info; 1583 1584 qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min); 1585 qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max); 1586 1587 /* Acknowledge the MFW */ 1588 qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp, 1589 ¶m); 1590 } 1591 1592 static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1593 { 1594 struct public_func shmem_info; 1595 u32 resp = 0, param = 0; 1596 1597 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1598 1599 p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag & 1600 FUNC_MF_CFG_OV_STAG_MASK; 1601 p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan; 1602 if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits)) { 1603 if (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET) { 1604 qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 1605 p_hwfn->hw_info.ovlan); 1606 qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 1); 1607 1608 /* Configure DB to add external vlan to EDPM packets */ 1609 qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 1); 1610 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 1611 p_hwfn->hw_info.ovlan); 1612 } else { 1613 qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 0); 1614 qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 0); 1615 qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 0); 1616 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 0); 1617 } 1618 1619 qed_sp_pf_update_stag(p_hwfn); 1620 } 1621 1622 DP_VERBOSE(p_hwfn, QED_MSG_SP, "ovlan = %d hw_mode = 0x%x\n", 1623 p_hwfn->mcp_info->func_info.ovlan, p_hwfn->hw_info.hw_mode); 1624 1625 /* Acknowledge the MFW */ 1626 qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0, 1627 &resp, ¶m); 1628 } 1629 1630 void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1631 { 1632 struct public_func shmem_info; 1633 u32 port_cfg, val; 1634 1635 if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits)) 1636 return; 1637 1638 memset(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info)); 1639 port_cfg = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1640 offsetof(struct public_port, oem_cfg_port)); 1641 val = (port_cfg & OEM_CFG_CHANNEL_TYPE_MASK) >> 1642 OEM_CFG_CHANNEL_TYPE_OFFSET; 1643 if (val != OEM_CFG_CHANNEL_TYPE_STAGGED) 1644 DP_NOTICE(p_hwfn, "Incorrect UFP Channel type %d\n", val); 1645 1646 val = (port_cfg & OEM_CFG_SCHED_TYPE_MASK) >> OEM_CFG_SCHED_TYPE_OFFSET; 1647 if (val == OEM_CFG_SCHED_TYPE_ETS) { 1648 p_hwfn->ufp_info.mode = QED_UFP_MODE_ETS; 1649 } else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW) { 1650 p_hwfn->ufp_info.mode = QED_UFP_MODE_VNIC_BW; 1651 } else { 1652 p_hwfn->ufp_info.mode = QED_UFP_MODE_UNKNOWN; 1653 DP_NOTICE(p_hwfn, "Unknown UFP scheduling mode %d\n", val); 1654 } 1655 1656 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1657 val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_TC_MASK) >> 1658 OEM_CFG_FUNC_TC_OFFSET; 1659 p_hwfn->ufp_info.tc = (u8)val; 1660 val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_HOST_PRI_CTRL_MASK) >> 1661 OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET; 1662 if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC) { 1663 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_VNIC; 1664 } else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS) { 1665 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_OS; 1666 } else { 1667 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_UNKNOWN; 1668 DP_NOTICE(p_hwfn, "Unknown Host priority control %d\n", val); 1669 } 1670 1671 DP_NOTICE(p_hwfn, 1672 "UFP shmem config: mode = %d tc = %d pri_type = %d\n", 1673 p_hwfn->ufp_info.mode, 1674 p_hwfn->ufp_info.tc, p_hwfn->ufp_info.pri_type); 1675 } 1676 1677 static int 1678 qed_mcp_handle_ufp_event(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1679 { 1680 qed_mcp_read_ufp_config(p_hwfn, p_ptt); 1681 1682 if (p_hwfn->ufp_info.mode == QED_UFP_MODE_VNIC_BW) { 1683 p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc; 1684 qed_hw_info_set_offload_tc(&p_hwfn->hw_info, 1685 p_hwfn->ufp_info.tc); 1686 1687 qed_qm_reconf(p_hwfn, p_ptt); 1688 } else if (p_hwfn->ufp_info.mode == QED_UFP_MODE_ETS) { 1689 /* Merge UFP TC with the dcbx TC data */ 1690 qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1691 QED_DCBX_OPERATIONAL_MIB); 1692 } else { 1693 DP_ERR(p_hwfn, "Invalid sched type, discard the UFP config\n"); 1694 return -EINVAL; 1695 } 1696 1697 /* update storm FW with negotiation results */ 1698 qed_sp_pf_update_ufp(p_hwfn); 1699 1700 /* update stag pcp value */ 1701 qed_sp_pf_update_stag(p_hwfn); 1702 1703 return 0; 1704 } 1705 1706 int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 1707 struct qed_ptt *p_ptt) 1708 { 1709 struct qed_mcp_info *info = p_hwfn->mcp_info; 1710 int rc = 0; 1711 bool found = false; 1712 u16 i; 1713 1714 DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n"); 1715 1716 /* Read Messages from MFW */ 1717 qed_mcp_read_mb(p_hwfn, p_ptt); 1718 1719 /* Compare current messages to old ones */ 1720 for (i = 0; i < info->mfw_mb_length; i++) { 1721 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i]) 1722 continue; 1723 1724 found = true; 1725 1726 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1727 "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n", 1728 i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]); 1729 1730 switch (i) { 1731 case MFW_DRV_MSG_LINK_CHANGE: 1732 qed_mcp_handle_link_change(p_hwfn, p_ptt, false); 1733 break; 1734 case MFW_DRV_MSG_VF_DISABLED: 1735 qed_mcp_handle_vf_flr(p_hwfn, p_ptt); 1736 break; 1737 case MFW_DRV_MSG_LLDP_DATA_UPDATED: 1738 qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1739 QED_DCBX_REMOTE_LLDP_MIB); 1740 break; 1741 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED: 1742 qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1743 QED_DCBX_REMOTE_MIB); 1744 break; 1745 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED: 1746 qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1747 QED_DCBX_OPERATIONAL_MIB); 1748 break; 1749 case MFW_DRV_MSG_OEM_CFG_UPDATE: 1750 qed_mcp_handle_ufp_event(p_hwfn, p_ptt); 1751 break; 1752 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE: 1753 qed_mcp_handle_transceiver_change(p_hwfn, p_ptt); 1754 break; 1755 case MFW_DRV_MSG_GET_LAN_STATS: 1756 case MFW_DRV_MSG_GET_FCOE_STATS: 1757 case MFW_DRV_MSG_GET_ISCSI_STATS: 1758 case MFW_DRV_MSG_GET_RDMA_STATS: 1759 qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i); 1760 break; 1761 case MFW_DRV_MSG_BW_UPDATE: 1762 qed_mcp_update_bw(p_hwfn, p_ptt); 1763 break; 1764 case MFW_DRV_MSG_S_TAG_UPDATE: 1765 qed_mcp_update_stag(p_hwfn, p_ptt); 1766 break; 1767 case MFW_DRV_MSG_GET_TLV_REQ: 1768 qed_mfw_tlv_req(p_hwfn); 1769 break; 1770 default: 1771 DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i); 1772 rc = -EINVAL; 1773 } 1774 } 1775 1776 /* ACK everything */ 1777 for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) { 1778 __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); 1779 1780 /* MFW expect answer in BE, so we force write in that format */ 1781 qed_wr(p_hwfn, p_ptt, 1782 info->mfw_mb_addr + sizeof(u32) + 1783 MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) * 1784 sizeof(u32) + i * sizeof(u32), 1785 (__force u32)val); 1786 } 1787 1788 if (!found) { 1789 DP_NOTICE(p_hwfn, 1790 "Received an MFW message indication but no new message!\n"); 1791 rc = -EINVAL; 1792 } 1793 1794 /* Copy the new mfw messages into the shadow */ 1795 memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length); 1796 1797 return rc; 1798 } 1799 1800 int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 1801 struct qed_ptt *p_ptt, 1802 u32 *p_mfw_ver, u32 *p_running_bundle_id) 1803 { 1804 u32 global_offsize; 1805 1806 if (IS_VF(p_hwfn->cdev)) { 1807 if (p_hwfn->vf_iov_info) { 1808 struct pfvf_acquire_resp_tlv *p_resp; 1809 1810 p_resp = &p_hwfn->vf_iov_info->acquire_resp; 1811 *p_mfw_ver = p_resp->pfdev_info.mfw_ver; 1812 return 0; 1813 } else { 1814 DP_VERBOSE(p_hwfn, 1815 QED_MSG_IOV, 1816 "VF requested MFW version prior to ACQUIRE\n"); 1817 return -EINVAL; 1818 } 1819 } 1820 1821 global_offsize = qed_rd(p_hwfn, p_ptt, 1822 SECTION_OFFSIZE_ADDR(p_hwfn-> 1823 mcp_info->public_base, 1824 PUBLIC_GLOBAL)); 1825 *p_mfw_ver = 1826 qed_rd(p_hwfn, p_ptt, 1827 SECTION_ADDR(global_offsize, 1828 0) + offsetof(struct public_global, mfw_ver)); 1829 1830 if (p_running_bundle_id != NULL) { 1831 *p_running_bundle_id = qed_rd(p_hwfn, p_ptt, 1832 SECTION_ADDR(global_offsize, 0) + 1833 offsetof(struct public_global, 1834 running_bundle_id)); 1835 } 1836 1837 return 0; 1838 } 1839 1840 int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn, 1841 struct qed_ptt *p_ptt, u32 *p_mbi_ver) 1842 { 1843 u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr; 1844 1845 if (IS_VF(p_hwfn->cdev)) 1846 return -EINVAL; 1847 1848 /* Read the address of the nvm_cfg */ 1849 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 1850 if (!nvm_cfg_addr) { 1851 DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 1852 return -EINVAL; 1853 } 1854 1855 /* Read the offset of nvm_cfg1 */ 1856 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 1857 1858 mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1859 offsetof(struct nvm_cfg1, glob) + 1860 offsetof(struct nvm_cfg1_glob, mbi_version); 1861 *p_mbi_ver = qed_rd(p_hwfn, p_ptt, 1862 mbi_ver_addr) & 1863 (NVM_CFG1_GLOB_MBI_VERSION_0_MASK | 1864 NVM_CFG1_GLOB_MBI_VERSION_1_MASK | 1865 NVM_CFG1_GLOB_MBI_VERSION_2_MASK); 1866 1867 return 0; 1868 } 1869 1870 int qed_mcp_get_media_type(struct qed_dev *cdev, u32 *p_media_type) 1871 { 1872 struct qed_hwfn *p_hwfn = &cdev->hwfns[0]; 1873 struct qed_ptt *p_ptt; 1874 1875 if (IS_VF(cdev)) 1876 return -EINVAL; 1877 1878 if (!qed_mcp_is_init(p_hwfn)) { 1879 DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 1880 return -EBUSY; 1881 } 1882 1883 *p_media_type = MEDIA_UNSPECIFIED; 1884 1885 p_ptt = qed_ptt_acquire(p_hwfn); 1886 if (!p_ptt) 1887 return -EBUSY; 1888 1889 *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1890 offsetof(struct public_port, media_type)); 1891 1892 qed_ptt_release(p_hwfn, p_ptt); 1893 1894 return 0; 1895 } 1896 1897 /* Old MFW has a global configuration for all PFs regarding RDMA support */ 1898 static void 1899 qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn, 1900 enum qed_pci_personality *p_proto) 1901 { 1902 /* There wasn't ever a legacy MFW that published iwarp. 1903 * So at this point, this is either plain l2 or RoCE. 1904 */ 1905 if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities)) 1906 *p_proto = QED_PCI_ETH_ROCE; 1907 else 1908 *p_proto = QED_PCI_ETH; 1909 1910 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 1911 "According to Legacy capabilities, L2 personality is %08x\n", 1912 (u32) *p_proto); 1913 } 1914 1915 static int 1916 qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn, 1917 struct qed_ptt *p_ptt, 1918 enum qed_pci_personality *p_proto) 1919 { 1920 u32 resp = 0, param = 0; 1921 int rc; 1922 1923 rc = qed_mcp_cmd(p_hwfn, p_ptt, 1924 DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, ¶m); 1925 if (rc) 1926 return rc; 1927 if (resp != FW_MSG_CODE_OK) { 1928 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 1929 "MFW lacks support for command; Returns %08x\n", 1930 resp); 1931 return -EINVAL; 1932 } 1933 1934 switch (param) { 1935 case FW_MB_PARAM_GET_PF_RDMA_NONE: 1936 *p_proto = QED_PCI_ETH; 1937 break; 1938 case FW_MB_PARAM_GET_PF_RDMA_ROCE: 1939 *p_proto = QED_PCI_ETH_ROCE; 1940 break; 1941 case FW_MB_PARAM_GET_PF_RDMA_IWARP: 1942 *p_proto = QED_PCI_ETH_IWARP; 1943 break; 1944 case FW_MB_PARAM_GET_PF_RDMA_BOTH: 1945 *p_proto = QED_PCI_ETH_RDMA; 1946 break; 1947 default: 1948 DP_NOTICE(p_hwfn, 1949 "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n", 1950 param); 1951 return -EINVAL; 1952 } 1953 1954 DP_VERBOSE(p_hwfn, 1955 NETIF_MSG_IFUP, 1956 "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n", 1957 (u32) *p_proto, resp, param); 1958 return 0; 1959 } 1960 1961 static int 1962 qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn, 1963 struct public_func *p_info, 1964 struct qed_ptt *p_ptt, 1965 enum qed_pci_personality *p_proto) 1966 { 1967 int rc = 0; 1968 1969 switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) { 1970 case FUNC_MF_CFG_PROTOCOL_ETHERNET: 1971 if (!IS_ENABLED(CONFIG_QED_RDMA)) 1972 *p_proto = QED_PCI_ETH; 1973 else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto)) 1974 qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto); 1975 break; 1976 case FUNC_MF_CFG_PROTOCOL_ISCSI: 1977 *p_proto = QED_PCI_ISCSI; 1978 break; 1979 case FUNC_MF_CFG_PROTOCOL_FCOE: 1980 *p_proto = QED_PCI_FCOE; 1981 break; 1982 case FUNC_MF_CFG_PROTOCOL_ROCE: 1983 DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n"); 1984 /* Fallthrough */ 1985 default: 1986 rc = -EINVAL; 1987 } 1988 1989 return rc; 1990 } 1991 1992 int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 1993 struct qed_ptt *p_ptt) 1994 { 1995 struct qed_mcp_function_info *info; 1996 struct public_func shmem_info; 1997 1998 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1999 info = &p_hwfn->mcp_info->func_info; 2000 2001 info->pause_on_host = (shmem_info.config & 2002 FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0; 2003 2004 if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt, 2005 &info->protocol)) { 2006 DP_ERR(p_hwfn, "Unknown personality %08x\n", 2007 (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK)); 2008 return -EINVAL; 2009 } 2010 2011 qed_read_pf_bandwidth(p_hwfn, &shmem_info); 2012 2013 if (shmem_info.mac_upper || shmem_info.mac_lower) { 2014 info->mac[0] = (u8)(shmem_info.mac_upper >> 8); 2015 info->mac[1] = (u8)(shmem_info.mac_upper); 2016 info->mac[2] = (u8)(shmem_info.mac_lower >> 24); 2017 info->mac[3] = (u8)(shmem_info.mac_lower >> 16); 2018 info->mac[4] = (u8)(shmem_info.mac_lower >> 8); 2019 info->mac[5] = (u8)(shmem_info.mac_lower); 2020 2021 /* Store primary MAC for later possible WoL */ 2022 memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN); 2023 } else { 2024 DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n"); 2025 } 2026 2027 info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower | 2028 (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32); 2029 info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower | 2030 (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32); 2031 2032 info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK); 2033 2034 info->mtu = (u16)shmem_info.mtu_size; 2035 2036 p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE; 2037 p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT; 2038 if (qed_mcp_is_init(p_hwfn)) { 2039 u32 resp = 0, param = 0; 2040 int rc; 2041 2042 rc = qed_mcp_cmd(p_hwfn, p_ptt, 2043 DRV_MSG_CODE_OS_WOL, 0, &resp, ¶m); 2044 if (rc) 2045 return rc; 2046 if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED) 2047 p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME; 2048 } 2049 2050 DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP), 2051 "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n", 2052 info->pause_on_host, info->protocol, 2053 info->bandwidth_min, info->bandwidth_max, 2054 info->mac[0], info->mac[1], info->mac[2], 2055 info->mac[3], info->mac[4], info->mac[5], 2056 info->wwn_port, info->wwn_node, 2057 info->ovlan, (u8)p_hwfn->hw_info.b_wol_support); 2058 2059 return 0; 2060 } 2061 2062 struct qed_mcp_link_params 2063 *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn) 2064 { 2065 if (!p_hwfn || !p_hwfn->mcp_info) 2066 return NULL; 2067 return &p_hwfn->mcp_info->link_input; 2068 } 2069 2070 struct qed_mcp_link_state 2071 *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn) 2072 { 2073 if (!p_hwfn || !p_hwfn->mcp_info) 2074 return NULL; 2075 return &p_hwfn->mcp_info->link_output; 2076 } 2077 2078 struct qed_mcp_link_capabilities 2079 *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn) 2080 { 2081 if (!p_hwfn || !p_hwfn->mcp_info) 2082 return NULL; 2083 return &p_hwfn->mcp_info->link_capabilities; 2084 } 2085 2086 int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2087 { 2088 u32 resp = 0, param = 0; 2089 int rc; 2090 2091 rc = qed_mcp_cmd(p_hwfn, p_ptt, 2092 DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m); 2093 2094 /* Wait for the drain to complete before returning */ 2095 msleep(1020); 2096 2097 return rc; 2098 } 2099 2100 int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 2101 struct qed_ptt *p_ptt, u32 *p_flash_size) 2102 { 2103 u32 flash_size; 2104 2105 if (IS_VF(p_hwfn->cdev)) 2106 return -EINVAL; 2107 2108 flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4); 2109 flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >> 2110 MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT; 2111 flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT)); 2112 2113 *p_flash_size = flash_size; 2114 2115 return 0; 2116 } 2117 2118 static int 2119 qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn, 2120 struct qed_ptt *p_ptt, u8 vf_id, u8 num) 2121 { 2122 u32 resp = 0, param = 0, rc_param = 0; 2123 int rc; 2124 2125 /* Only Leader can configure MSIX, and need to take CMT into account */ 2126 if (!IS_LEAD_HWFN(p_hwfn)) 2127 return 0; 2128 num *= p_hwfn->cdev->num_hwfns; 2129 2130 param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) & 2131 DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK; 2132 param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) & 2133 DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK; 2134 2135 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param, 2136 &resp, &rc_param); 2137 2138 if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) { 2139 DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id); 2140 rc = -EINVAL; 2141 } else { 2142 DP_VERBOSE(p_hwfn, QED_MSG_IOV, 2143 "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n", 2144 num, vf_id); 2145 } 2146 2147 return rc; 2148 } 2149 2150 static int 2151 qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn, 2152 struct qed_ptt *p_ptt, u8 num) 2153 { 2154 u32 resp = 0, param = num, rc_param = 0; 2155 int rc; 2156 2157 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX, 2158 param, &resp, &rc_param); 2159 2160 if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) { 2161 DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n"); 2162 rc = -EINVAL; 2163 } else { 2164 DP_VERBOSE(p_hwfn, QED_MSG_IOV, 2165 "Requested 0x%02x MSI-x interrupts for VFs\n", num); 2166 } 2167 2168 return rc; 2169 } 2170 2171 int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 2172 struct qed_ptt *p_ptt, u8 vf_id, u8 num) 2173 { 2174 if (QED_IS_BB(p_hwfn->cdev)) 2175 return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num); 2176 else 2177 return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num); 2178 } 2179 2180 int 2181 qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 2182 struct qed_ptt *p_ptt, 2183 struct qed_mcp_drv_version *p_ver) 2184 { 2185 struct qed_mcp_mb_params mb_params; 2186 struct drv_version_stc drv_version; 2187 __be32 val; 2188 u32 i; 2189 int rc; 2190 2191 memset(&drv_version, 0, sizeof(drv_version)); 2192 drv_version.version = p_ver->version; 2193 for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) { 2194 val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)])); 2195 *(__be32 *)&drv_version.name[i * sizeof(u32)] = val; 2196 } 2197 2198 memset(&mb_params, 0, sizeof(mb_params)); 2199 mb_params.cmd = DRV_MSG_CODE_SET_VERSION; 2200 mb_params.p_data_src = &drv_version; 2201 mb_params.data_src_size = sizeof(drv_version); 2202 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 2203 if (rc) 2204 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 2205 2206 return rc; 2207 } 2208 2209 /* A maximal 100 msec waiting time for the MCP to halt */ 2210 #define QED_MCP_HALT_SLEEP_MS 10 2211 #define QED_MCP_HALT_MAX_RETRIES 10 2212 2213 int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2214 { 2215 u32 resp = 0, param = 0, cpu_state, cnt = 0; 2216 int rc; 2217 2218 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp, 2219 ¶m); 2220 if (rc) { 2221 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 2222 return rc; 2223 } 2224 2225 do { 2226 msleep(QED_MCP_HALT_SLEEP_MS); 2227 cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 2228 if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) 2229 break; 2230 } while (++cnt < QED_MCP_HALT_MAX_RETRIES); 2231 2232 if (cnt == QED_MCP_HALT_MAX_RETRIES) { 2233 DP_NOTICE(p_hwfn, 2234 "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n", 2235 qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state); 2236 return -EBUSY; 2237 } 2238 2239 qed_mcp_cmd_set_blocking(p_hwfn, true); 2240 2241 return 0; 2242 } 2243 2244 #define QED_MCP_RESUME_SLEEP_MS 10 2245 2246 int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2247 { 2248 u32 cpu_mode, cpu_state; 2249 2250 qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff); 2251 2252 cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 2253 cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT; 2254 qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode); 2255 msleep(QED_MCP_RESUME_SLEEP_MS); 2256 cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 2257 2258 if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) { 2259 DP_NOTICE(p_hwfn, 2260 "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n", 2261 cpu_mode, cpu_state); 2262 return -EBUSY; 2263 } 2264 2265 qed_mcp_cmd_set_blocking(p_hwfn, false); 2266 2267 return 0; 2268 } 2269 2270 int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 2271 struct qed_ptt *p_ptt, 2272 enum qed_ov_client client) 2273 { 2274 u32 resp = 0, param = 0; 2275 u32 drv_mb_param; 2276 int rc; 2277 2278 switch (client) { 2279 case QED_OV_CLIENT_DRV: 2280 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS; 2281 break; 2282 case QED_OV_CLIENT_USER: 2283 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER; 2284 break; 2285 case QED_OV_CLIENT_VENDOR_SPEC: 2286 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC; 2287 break; 2288 default: 2289 DP_NOTICE(p_hwfn, "Invalid client type %d\n", client); 2290 return -EINVAL; 2291 } 2292 2293 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG, 2294 drv_mb_param, &resp, ¶m); 2295 if (rc) 2296 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 2297 2298 return rc; 2299 } 2300 2301 int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 2302 struct qed_ptt *p_ptt, 2303 enum qed_ov_driver_state drv_state) 2304 { 2305 u32 resp = 0, param = 0; 2306 u32 drv_mb_param; 2307 int rc; 2308 2309 switch (drv_state) { 2310 case QED_OV_DRIVER_STATE_NOT_LOADED: 2311 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED; 2312 break; 2313 case QED_OV_DRIVER_STATE_DISABLED: 2314 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED; 2315 break; 2316 case QED_OV_DRIVER_STATE_ACTIVE: 2317 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE; 2318 break; 2319 default: 2320 DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state); 2321 return -EINVAL; 2322 } 2323 2324 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE, 2325 drv_mb_param, &resp, ¶m); 2326 if (rc) 2327 DP_ERR(p_hwfn, "Failed to send driver state\n"); 2328 2329 return rc; 2330 } 2331 2332 int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 2333 struct qed_ptt *p_ptt, u16 mtu) 2334 { 2335 u32 resp = 0, param = 0; 2336 u32 drv_mb_param; 2337 int rc; 2338 2339 drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT; 2340 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU, 2341 drv_mb_param, &resp, ¶m); 2342 if (rc) 2343 DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc); 2344 2345 return rc; 2346 } 2347 2348 int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 2349 struct qed_ptt *p_ptt, u8 *mac) 2350 { 2351 struct qed_mcp_mb_params mb_params; 2352 u32 mfw_mac[2]; 2353 int rc; 2354 2355 memset(&mb_params, 0, sizeof(mb_params)); 2356 mb_params.cmd = DRV_MSG_CODE_SET_VMAC; 2357 mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC << 2358 DRV_MSG_CODE_VMAC_TYPE_SHIFT; 2359 mb_params.param |= MCP_PF_ID(p_hwfn); 2360 2361 /* MCP is BE, and on LE platforms PCI would swap access to SHMEM 2362 * in 32-bit granularity. 2363 * So the MAC has to be set in native order [and not byte order], 2364 * otherwise it would be read incorrectly by MFW after swap. 2365 */ 2366 mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3]; 2367 mfw_mac[1] = mac[4] << 24 | mac[5] << 16; 2368 2369 mb_params.p_data_src = (u8 *)mfw_mac; 2370 mb_params.data_src_size = 8; 2371 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 2372 if (rc) 2373 DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc); 2374 2375 /* Store primary MAC for later possible WoL */ 2376 memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN); 2377 2378 return rc; 2379 } 2380 2381 int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 2382 struct qed_ptt *p_ptt, enum qed_ov_wol wol) 2383 { 2384 u32 resp = 0, param = 0; 2385 u32 drv_mb_param; 2386 int rc; 2387 2388 if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) { 2389 DP_VERBOSE(p_hwfn, QED_MSG_SP, 2390 "Can't change WoL configuration when WoL isn't supported\n"); 2391 return -EINVAL; 2392 } 2393 2394 switch (wol) { 2395 case QED_OV_WOL_DEFAULT: 2396 drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT; 2397 break; 2398 case QED_OV_WOL_DISABLED: 2399 drv_mb_param = DRV_MB_PARAM_WOL_DISABLED; 2400 break; 2401 case QED_OV_WOL_ENABLED: 2402 drv_mb_param = DRV_MB_PARAM_WOL_ENABLED; 2403 break; 2404 default: 2405 DP_ERR(p_hwfn, "Invalid wol state %d\n", wol); 2406 return -EINVAL; 2407 } 2408 2409 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL, 2410 drv_mb_param, &resp, ¶m); 2411 if (rc) 2412 DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc); 2413 2414 /* Store the WoL update for a future unload */ 2415 p_hwfn->cdev->wol_config = (u8)wol; 2416 2417 return rc; 2418 } 2419 2420 int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 2421 struct qed_ptt *p_ptt, 2422 enum qed_ov_eswitch eswitch) 2423 { 2424 u32 resp = 0, param = 0; 2425 u32 drv_mb_param; 2426 int rc; 2427 2428 switch (eswitch) { 2429 case QED_OV_ESWITCH_NONE: 2430 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE; 2431 break; 2432 case QED_OV_ESWITCH_VEB: 2433 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB; 2434 break; 2435 case QED_OV_ESWITCH_VEPA: 2436 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA; 2437 break; 2438 default: 2439 DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch); 2440 return -EINVAL; 2441 } 2442 2443 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE, 2444 drv_mb_param, &resp, ¶m); 2445 if (rc) 2446 DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc); 2447 2448 return rc; 2449 } 2450 2451 int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 2452 struct qed_ptt *p_ptt, enum qed_led_mode mode) 2453 { 2454 u32 resp = 0, param = 0, drv_mb_param; 2455 int rc; 2456 2457 switch (mode) { 2458 case QED_LED_MODE_ON: 2459 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON; 2460 break; 2461 case QED_LED_MODE_OFF: 2462 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF; 2463 break; 2464 case QED_LED_MODE_RESTORE: 2465 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER; 2466 break; 2467 default: 2468 DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode); 2469 return -EINVAL; 2470 } 2471 2472 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE, 2473 drv_mb_param, &resp, ¶m); 2474 2475 return rc; 2476 } 2477 2478 int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 2479 struct qed_ptt *p_ptt, u32 mask_parities) 2480 { 2481 u32 resp = 0, param = 0; 2482 int rc; 2483 2484 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES, 2485 mask_parities, &resp, ¶m); 2486 2487 if (rc) { 2488 DP_ERR(p_hwfn, 2489 "MCP response failure for mask parities, aborting\n"); 2490 } else if (resp != FW_MSG_CODE_OK) { 2491 DP_ERR(p_hwfn, 2492 "MCP did not acknowledge mask parity request. Old MFW?\n"); 2493 rc = -EINVAL; 2494 } 2495 2496 return rc; 2497 } 2498 2499 int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len) 2500 { 2501 u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0; 2502 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2503 u32 resp = 0, resp_param = 0; 2504 struct qed_ptt *p_ptt; 2505 int rc = 0; 2506 2507 p_ptt = qed_ptt_acquire(p_hwfn); 2508 if (!p_ptt) 2509 return -EBUSY; 2510 2511 while (bytes_left > 0) { 2512 bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN); 2513 2514 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 2515 DRV_MSG_CODE_NVM_READ_NVRAM, 2516 addr + offset + 2517 (bytes_to_copy << 2518 DRV_MB_PARAM_NVM_LEN_OFFSET), 2519 &resp, &resp_param, 2520 &read_len, 2521 (u32 *)(p_buf + offset)); 2522 2523 if (rc || (resp != FW_MSG_CODE_NVM_OK)) { 2524 DP_NOTICE(cdev, "MCP command rc = %d\n", rc); 2525 break; 2526 } 2527 2528 /* This can be a lengthy process, and it's possible scheduler 2529 * isn't preemptable. Sleep a bit to prevent CPU hogging. 2530 */ 2531 if (bytes_left % 0x1000 < 2532 (bytes_left - read_len) % 0x1000) 2533 usleep_range(1000, 2000); 2534 2535 offset += read_len; 2536 bytes_left -= read_len; 2537 } 2538 2539 cdev->mcp_nvm_resp = resp; 2540 qed_ptt_release(p_hwfn, p_ptt); 2541 2542 return rc; 2543 } 2544 2545 int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf) 2546 { 2547 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2548 struct qed_ptt *p_ptt; 2549 2550 p_ptt = qed_ptt_acquire(p_hwfn); 2551 if (!p_ptt) 2552 return -EBUSY; 2553 2554 memcpy(p_buf, &cdev->mcp_nvm_resp, sizeof(cdev->mcp_nvm_resp)); 2555 qed_ptt_release(p_hwfn, p_ptt); 2556 2557 return 0; 2558 } 2559 2560 int qed_mcp_nvm_put_file_begin(struct qed_dev *cdev, u32 addr) 2561 { 2562 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2563 struct qed_ptt *p_ptt; 2564 u32 resp, param; 2565 int rc; 2566 2567 p_ptt = qed_ptt_acquire(p_hwfn); 2568 if (!p_ptt) 2569 return -EBUSY; 2570 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr, 2571 &resp, ¶m); 2572 cdev->mcp_nvm_resp = resp; 2573 qed_ptt_release(p_hwfn, p_ptt); 2574 2575 return rc; 2576 } 2577 2578 int qed_mcp_nvm_write(struct qed_dev *cdev, 2579 u32 cmd, u32 addr, u8 *p_buf, u32 len) 2580 { 2581 u32 buf_idx = 0, buf_size, nvm_cmd, nvm_offset, resp = 0, param; 2582 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2583 struct qed_ptt *p_ptt; 2584 int rc = -EINVAL; 2585 2586 p_ptt = qed_ptt_acquire(p_hwfn); 2587 if (!p_ptt) 2588 return -EBUSY; 2589 2590 switch (cmd) { 2591 case QED_PUT_FILE_DATA: 2592 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA; 2593 break; 2594 case QED_NVM_WRITE_NVRAM: 2595 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM; 2596 break; 2597 default: 2598 DP_NOTICE(p_hwfn, "Invalid nvm write command 0x%x\n", cmd); 2599 rc = -EINVAL; 2600 goto out; 2601 } 2602 2603 while (buf_idx < len) { 2604 buf_size = min_t(u32, (len - buf_idx), MCP_DRV_NVM_BUF_LEN); 2605 nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) | 2606 addr) + buf_idx; 2607 rc = qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset, 2608 &resp, ¶m, buf_size, 2609 (u32 *)&p_buf[buf_idx]); 2610 if (rc) { 2611 DP_NOTICE(cdev, "nvm write failed, rc = %d\n", rc); 2612 resp = FW_MSG_CODE_ERROR; 2613 break; 2614 } 2615 2616 if (resp != FW_MSG_CODE_OK && 2617 resp != FW_MSG_CODE_NVM_OK && 2618 resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) { 2619 DP_NOTICE(cdev, 2620 "nvm write failed, resp = 0x%08x\n", resp); 2621 rc = -EINVAL; 2622 break; 2623 } 2624 2625 /* This can be a lengthy process, and it's possible scheduler 2626 * isn't pre-emptable. Sleep a bit to prevent CPU hogging. 2627 */ 2628 if (buf_idx % 0x1000 > (buf_idx + buf_size) % 0x1000) 2629 usleep_range(1000, 2000); 2630 2631 buf_idx += buf_size; 2632 } 2633 2634 cdev->mcp_nvm_resp = resp; 2635 out: 2636 qed_ptt_release(p_hwfn, p_ptt); 2637 2638 return rc; 2639 } 2640 2641 int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2642 u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf) 2643 { 2644 u32 bytes_left, bytes_to_copy, buf_size, nvm_offset = 0; 2645 u32 resp, param; 2646 int rc; 2647 2648 nvm_offset |= (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) & 2649 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK; 2650 nvm_offset |= (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET) & 2651 DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK; 2652 2653 addr = offset; 2654 offset = 0; 2655 bytes_left = len; 2656 while (bytes_left > 0) { 2657 bytes_to_copy = min_t(u32, bytes_left, 2658 MAX_I2C_TRANSACTION_SIZE); 2659 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK | 2660 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK); 2661 nvm_offset |= ((addr + offset) << 2662 DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET) & 2663 DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK; 2664 nvm_offset |= (bytes_to_copy << 2665 DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET) & 2666 DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK; 2667 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 2668 DRV_MSG_CODE_TRANSCEIVER_READ, 2669 nvm_offset, &resp, ¶m, &buf_size, 2670 (u32 *)(p_buf + offset)); 2671 if (rc) { 2672 DP_NOTICE(p_hwfn, 2673 "Failed to send a transceiver read command to the MFW. rc = %d.\n", 2674 rc); 2675 return rc; 2676 } 2677 2678 if (resp == FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) 2679 return -ENODEV; 2680 else if (resp != FW_MSG_CODE_TRANSCEIVER_DIAG_OK) 2681 return -EINVAL; 2682 2683 offset += buf_size; 2684 bytes_left -= buf_size; 2685 } 2686 2687 return 0; 2688 } 2689 2690 int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2691 { 2692 u32 drv_mb_param = 0, rsp, param; 2693 int rc = 0; 2694 2695 drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST << 2696 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 2697 2698 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 2699 drv_mb_param, &rsp, ¶m); 2700 2701 if (rc) 2702 return rc; 2703 2704 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 2705 (param != DRV_MB_PARAM_BIST_RC_PASSED)) 2706 rc = -EAGAIN; 2707 2708 return rc; 2709 } 2710 2711 int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2712 { 2713 u32 drv_mb_param, rsp, param; 2714 int rc = 0; 2715 2716 drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST << 2717 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 2718 2719 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 2720 drv_mb_param, &rsp, ¶m); 2721 2722 if (rc) 2723 return rc; 2724 2725 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 2726 (param != DRV_MB_PARAM_BIST_RC_PASSED)) 2727 rc = -EAGAIN; 2728 2729 return rc; 2730 } 2731 2732 int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn, 2733 struct qed_ptt *p_ptt, 2734 u32 *num_images) 2735 { 2736 u32 drv_mb_param = 0, rsp; 2737 int rc = 0; 2738 2739 drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES << 2740 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 2741 2742 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 2743 drv_mb_param, &rsp, num_images); 2744 if (rc) 2745 return rc; 2746 2747 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK)) 2748 rc = -EINVAL; 2749 2750 return rc; 2751 } 2752 2753 int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn, 2754 struct qed_ptt *p_ptt, 2755 struct bist_nvm_image_att *p_image_att, 2756 u32 image_index) 2757 { 2758 u32 buf_size = 0, param, resp = 0, resp_param = 0; 2759 int rc; 2760 2761 param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX << 2762 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT; 2763 param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT; 2764 2765 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 2766 DRV_MSG_CODE_BIST_TEST, param, 2767 &resp, &resp_param, 2768 &buf_size, 2769 (u32 *)p_image_att); 2770 if (rc) 2771 return rc; 2772 2773 if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 2774 (p_image_att->return_code != 1)) 2775 rc = -EINVAL; 2776 2777 return rc; 2778 } 2779 2780 int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn) 2781 { 2782 struct qed_nvm_image_info nvm_info; 2783 struct qed_ptt *p_ptt; 2784 int rc; 2785 u32 i; 2786 2787 if (p_hwfn->nvm_info.valid) 2788 return 0; 2789 2790 p_ptt = qed_ptt_acquire(p_hwfn); 2791 if (!p_ptt) { 2792 DP_ERR(p_hwfn, "failed to acquire ptt\n"); 2793 return -EBUSY; 2794 } 2795 2796 /* Acquire from MFW the amount of available images */ 2797 nvm_info.num_images = 0; 2798 rc = qed_mcp_bist_nvm_get_num_images(p_hwfn, 2799 p_ptt, &nvm_info.num_images); 2800 if (rc == -EOPNOTSUPP) { 2801 DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n"); 2802 goto out; 2803 } else if (rc || !nvm_info.num_images) { 2804 DP_ERR(p_hwfn, "Failed getting number of images\n"); 2805 goto err0; 2806 } 2807 2808 nvm_info.image_att = kmalloc_array(nvm_info.num_images, 2809 sizeof(struct bist_nvm_image_att), 2810 GFP_KERNEL); 2811 if (!nvm_info.image_att) { 2812 rc = -ENOMEM; 2813 goto err0; 2814 } 2815 2816 /* Iterate over images and get their attributes */ 2817 for (i = 0; i < nvm_info.num_images; i++) { 2818 rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt, 2819 &nvm_info.image_att[i], i); 2820 if (rc) { 2821 DP_ERR(p_hwfn, 2822 "Failed getting image index %d attributes\n", i); 2823 goto err1; 2824 } 2825 2826 DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n", i, 2827 nvm_info.image_att[i].len); 2828 } 2829 out: 2830 /* Update hwfn's nvm_info */ 2831 if (nvm_info.num_images) { 2832 p_hwfn->nvm_info.num_images = nvm_info.num_images; 2833 kfree(p_hwfn->nvm_info.image_att); 2834 p_hwfn->nvm_info.image_att = nvm_info.image_att; 2835 p_hwfn->nvm_info.valid = true; 2836 } 2837 2838 qed_ptt_release(p_hwfn, p_ptt); 2839 return 0; 2840 2841 err1: 2842 kfree(nvm_info.image_att); 2843 err0: 2844 qed_ptt_release(p_hwfn, p_ptt); 2845 return rc; 2846 } 2847 2848 int 2849 qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn, 2850 enum qed_nvm_images image_id, 2851 struct qed_nvm_image_att *p_image_att) 2852 { 2853 enum nvm_image_type type; 2854 u32 i; 2855 2856 /* Translate image_id into MFW definitions */ 2857 switch (image_id) { 2858 case QED_NVM_IMAGE_ISCSI_CFG: 2859 type = NVM_TYPE_ISCSI_CFG; 2860 break; 2861 case QED_NVM_IMAGE_FCOE_CFG: 2862 type = NVM_TYPE_FCOE_CFG; 2863 break; 2864 case QED_NVM_IMAGE_NVM_CFG1: 2865 type = NVM_TYPE_NVM_CFG1; 2866 break; 2867 case QED_NVM_IMAGE_DEFAULT_CFG: 2868 type = NVM_TYPE_DEFAULT_CFG; 2869 break; 2870 case QED_NVM_IMAGE_NVM_META: 2871 type = NVM_TYPE_META; 2872 break; 2873 default: 2874 DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n", 2875 image_id); 2876 return -EINVAL; 2877 } 2878 2879 qed_mcp_nvm_info_populate(p_hwfn); 2880 for (i = 0; i < p_hwfn->nvm_info.num_images; i++) 2881 if (type == p_hwfn->nvm_info.image_att[i].image_type) 2882 break; 2883 if (i == p_hwfn->nvm_info.num_images) { 2884 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 2885 "Failed to find nvram image of type %08x\n", 2886 image_id); 2887 return -ENOENT; 2888 } 2889 2890 p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr; 2891 p_image_att->length = p_hwfn->nvm_info.image_att[i].len; 2892 2893 return 0; 2894 } 2895 2896 int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn, 2897 enum qed_nvm_images image_id, 2898 u8 *p_buffer, u32 buffer_len) 2899 { 2900 struct qed_nvm_image_att image_att; 2901 int rc; 2902 2903 memset(p_buffer, 0, buffer_len); 2904 2905 rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att); 2906 if (rc) 2907 return rc; 2908 2909 /* Validate sizes - both the image's and the supplied buffer's */ 2910 if (image_att.length <= 4) { 2911 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 2912 "Image [%d] is too small - only %d bytes\n", 2913 image_id, image_att.length); 2914 return -EINVAL; 2915 } 2916 2917 if (image_att.length > buffer_len) { 2918 DP_VERBOSE(p_hwfn, 2919 QED_MSG_STORAGE, 2920 "Image [%d] is too big - %08x bytes where only %08x are available\n", 2921 image_id, image_att.length, buffer_len); 2922 return -ENOMEM; 2923 } 2924 2925 return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr, 2926 p_buffer, image_att.length); 2927 } 2928 2929 static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id) 2930 { 2931 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID; 2932 2933 switch (res_id) { 2934 case QED_SB: 2935 mfw_res_id = RESOURCE_NUM_SB_E; 2936 break; 2937 case QED_L2_QUEUE: 2938 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E; 2939 break; 2940 case QED_VPORT: 2941 mfw_res_id = RESOURCE_NUM_VPORT_E; 2942 break; 2943 case QED_RSS_ENG: 2944 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E; 2945 break; 2946 case QED_PQ: 2947 mfw_res_id = RESOURCE_NUM_PQ_E; 2948 break; 2949 case QED_RL: 2950 mfw_res_id = RESOURCE_NUM_RL_E; 2951 break; 2952 case QED_MAC: 2953 case QED_VLAN: 2954 /* Each VFC resource can accommodate both a MAC and a VLAN */ 2955 mfw_res_id = RESOURCE_VFC_FILTER_E; 2956 break; 2957 case QED_ILT: 2958 mfw_res_id = RESOURCE_ILT_E; 2959 break; 2960 case QED_LL2_QUEUE: 2961 mfw_res_id = RESOURCE_LL2_QUEUE_E; 2962 break; 2963 case QED_RDMA_CNQ_RAM: 2964 case QED_CMDQS_CQS: 2965 /* CNQ/CMDQS are the same resource */ 2966 mfw_res_id = RESOURCE_CQS_E; 2967 break; 2968 case QED_RDMA_STATS_QUEUE: 2969 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E; 2970 break; 2971 case QED_BDQ: 2972 mfw_res_id = RESOURCE_BDQ_E; 2973 break; 2974 default: 2975 break; 2976 } 2977 2978 return mfw_res_id; 2979 } 2980 2981 #define QED_RESC_ALLOC_VERSION_MAJOR 2 2982 #define QED_RESC_ALLOC_VERSION_MINOR 0 2983 #define QED_RESC_ALLOC_VERSION \ 2984 ((QED_RESC_ALLOC_VERSION_MAJOR << \ 2985 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \ 2986 (QED_RESC_ALLOC_VERSION_MINOR << \ 2987 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT)) 2988 2989 struct qed_resc_alloc_in_params { 2990 u32 cmd; 2991 enum qed_resources res_id; 2992 u32 resc_max_val; 2993 }; 2994 2995 struct qed_resc_alloc_out_params { 2996 u32 mcp_resp; 2997 u32 mcp_param; 2998 u32 resc_num; 2999 u32 resc_start; 3000 u32 vf_resc_num; 3001 u32 vf_resc_start; 3002 u32 flags; 3003 }; 3004 3005 static int 3006 qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn, 3007 struct qed_ptt *p_ptt, 3008 struct qed_resc_alloc_in_params *p_in_params, 3009 struct qed_resc_alloc_out_params *p_out_params) 3010 { 3011 struct qed_mcp_mb_params mb_params; 3012 struct resource_info mfw_resc_info; 3013 int rc; 3014 3015 memset(&mfw_resc_info, 0, sizeof(mfw_resc_info)); 3016 3017 mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id); 3018 if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) { 3019 DP_ERR(p_hwfn, 3020 "Failed to match resource %d [%s] with the MFW resources\n", 3021 p_in_params->res_id, 3022 qed_hw_get_resc_name(p_in_params->res_id)); 3023 return -EINVAL; 3024 } 3025 3026 switch (p_in_params->cmd) { 3027 case DRV_MSG_SET_RESOURCE_VALUE_MSG: 3028 mfw_resc_info.size = p_in_params->resc_max_val; 3029 /* Fallthrough */ 3030 case DRV_MSG_GET_RESOURCE_ALLOC_MSG: 3031 break; 3032 default: 3033 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n", 3034 p_in_params->cmd); 3035 return -EINVAL; 3036 } 3037 3038 memset(&mb_params, 0, sizeof(mb_params)); 3039 mb_params.cmd = p_in_params->cmd; 3040 mb_params.param = QED_RESC_ALLOC_VERSION; 3041 mb_params.p_data_src = &mfw_resc_info; 3042 mb_params.data_src_size = sizeof(mfw_resc_info); 3043 mb_params.p_data_dst = mb_params.p_data_src; 3044 mb_params.data_dst_size = mb_params.data_src_size; 3045 3046 DP_VERBOSE(p_hwfn, 3047 QED_MSG_SP, 3048 "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n", 3049 p_in_params->cmd, 3050 p_in_params->res_id, 3051 qed_hw_get_resc_name(p_in_params->res_id), 3052 QED_MFW_GET_FIELD(mb_params.param, 3053 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 3054 QED_MFW_GET_FIELD(mb_params.param, 3055 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 3056 p_in_params->resc_max_val); 3057 3058 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 3059 if (rc) 3060 return rc; 3061 3062 p_out_params->mcp_resp = mb_params.mcp_resp; 3063 p_out_params->mcp_param = mb_params.mcp_param; 3064 p_out_params->resc_num = mfw_resc_info.size; 3065 p_out_params->resc_start = mfw_resc_info.offset; 3066 p_out_params->vf_resc_num = mfw_resc_info.vf_size; 3067 p_out_params->vf_resc_start = mfw_resc_info.vf_offset; 3068 p_out_params->flags = mfw_resc_info.flags; 3069 3070 DP_VERBOSE(p_hwfn, 3071 QED_MSG_SP, 3072 "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n", 3073 QED_MFW_GET_FIELD(p_out_params->mcp_param, 3074 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 3075 QED_MFW_GET_FIELD(p_out_params->mcp_param, 3076 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 3077 p_out_params->resc_num, 3078 p_out_params->resc_start, 3079 p_out_params->vf_resc_num, 3080 p_out_params->vf_resc_start, p_out_params->flags); 3081 3082 return 0; 3083 } 3084 3085 int 3086 qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn, 3087 struct qed_ptt *p_ptt, 3088 enum qed_resources res_id, 3089 u32 resc_max_val, u32 *p_mcp_resp) 3090 { 3091 struct qed_resc_alloc_out_params out_params; 3092 struct qed_resc_alloc_in_params in_params; 3093 int rc; 3094 3095 memset(&in_params, 0, sizeof(in_params)); 3096 in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG; 3097 in_params.res_id = res_id; 3098 in_params.resc_max_val = resc_max_val; 3099 memset(&out_params, 0, sizeof(out_params)); 3100 rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 3101 &out_params); 3102 if (rc) 3103 return rc; 3104 3105 *p_mcp_resp = out_params.mcp_resp; 3106 3107 return 0; 3108 } 3109 3110 int 3111 qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, 3112 struct qed_ptt *p_ptt, 3113 enum qed_resources res_id, 3114 u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start) 3115 { 3116 struct qed_resc_alloc_out_params out_params; 3117 struct qed_resc_alloc_in_params in_params; 3118 int rc; 3119 3120 memset(&in_params, 0, sizeof(in_params)); 3121 in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG; 3122 in_params.res_id = res_id; 3123 memset(&out_params, 0, sizeof(out_params)); 3124 rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 3125 &out_params); 3126 if (rc) 3127 return rc; 3128 3129 *p_mcp_resp = out_params.mcp_resp; 3130 3131 if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) { 3132 *p_resc_num = out_params.resc_num; 3133 *p_resc_start = out_params.resc_start; 3134 } 3135 3136 return 0; 3137 } 3138 3139 int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3140 { 3141 u32 mcp_resp, mcp_param; 3142 3143 return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0, 3144 &mcp_resp, &mcp_param); 3145 } 3146 3147 static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn, 3148 struct qed_ptt *p_ptt, 3149 u32 param, u32 *p_mcp_resp, u32 *p_mcp_param) 3150 { 3151 int rc; 3152 3153 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param, 3154 p_mcp_resp, p_mcp_param); 3155 if (rc) 3156 return rc; 3157 3158 if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 3159 DP_INFO(p_hwfn, 3160 "The resource command is unsupported by the MFW\n"); 3161 return -EINVAL; 3162 } 3163 3164 if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) { 3165 u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE); 3166 3167 DP_NOTICE(p_hwfn, 3168 "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n", 3169 param, opcode); 3170 return -EINVAL; 3171 } 3172 3173 return rc; 3174 } 3175 3176 static int 3177 __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 3178 struct qed_ptt *p_ptt, 3179 struct qed_resc_lock_params *p_params) 3180 { 3181 u32 param = 0, mcp_resp, mcp_param; 3182 u8 opcode; 3183 int rc; 3184 3185 switch (p_params->timeout) { 3186 case QED_MCP_RESC_LOCK_TO_DEFAULT: 3187 opcode = RESOURCE_OPCODE_REQ; 3188 p_params->timeout = 0; 3189 break; 3190 case QED_MCP_RESC_LOCK_TO_NONE: 3191 opcode = RESOURCE_OPCODE_REQ_WO_AGING; 3192 p_params->timeout = 0; 3193 break; 3194 default: 3195 opcode = RESOURCE_OPCODE_REQ_W_AGING; 3196 break; 3197 } 3198 3199 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 3200 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 3201 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout); 3202 3203 DP_VERBOSE(p_hwfn, 3204 QED_MSG_SP, 3205 "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n", 3206 param, p_params->timeout, opcode, p_params->resource); 3207 3208 /* Attempt to acquire the resource */ 3209 rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 3210 if (rc) 3211 return rc; 3212 3213 /* Analyze the response */ 3214 p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER); 3215 opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 3216 3217 DP_VERBOSE(p_hwfn, 3218 QED_MSG_SP, 3219 "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n", 3220 mcp_param, opcode, p_params->owner); 3221 3222 switch (opcode) { 3223 case RESOURCE_OPCODE_GNT: 3224 p_params->b_granted = true; 3225 break; 3226 case RESOURCE_OPCODE_BUSY: 3227 p_params->b_granted = false; 3228 break; 3229 default: 3230 DP_NOTICE(p_hwfn, 3231 "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n", 3232 mcp_param, opcode); 3233 return -EINVAL; 3234 } 3235 3236 return 0; 3237 } 3238 3239 int 3240 qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 3241 struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params) 3242 { 3243 u32 retry_cnt = 0; 3244 int rc; 3245 3246 do { 3247 /* No need for an interval before the first iteration */ 3248 if (retry_cnt) { 3249 if (p_params->sleep_b4_retry) { 3250 u16 retry_interval_in_ms = 3251 DIV_ROUND_UP(p_params->retry_interval, 3252 1000); 3253 3254 msleep(retry_interval_in_ms); 3255 } else { 3256 udelay(p_params->retry_interval); 3257 } 3258 } 3259 3260 rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params); 3261 if (rc) 3262 return rc; 3263 3264 if (p_params->b_granted) 3265 break; 3266 } while (retry_cnt++ < p_params->retry_num); 3267 3268 return 0; 3269 } 3270 3271 int 3272 qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn, 3273 struct qed_ptt *p_ptt, 3274 struct qed_resc_unlock_params *p_params) 3275 { 3276 u32 param = 0, mcp_resp, mcp_param; 3277 u8 opcode; 3278 int rc; 3279 3280 opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE 3281 : RESOURCE_OPCODE_RELEASE; 3282 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 3283 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 3284 3285 DP_VERBOSE(p_hwfn, QED_MSG_SP, 3286 "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n", 3287 param, opcode, p_params->resource); 3288 3289 /* Attempt to release the resource */ 3290 rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 3291 if (rc) 3292 return rc; 3293 3294 /* Analyze the response */ 3295 opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 3296 3297 DP_VERBOSE(p_hwfn, QED_MSG_SP, 3298 "Resource unlock response: mcp_param 0x%08x [opcode %d]\n", 3299 mcp_param, opcode); 3300 3301 switch (opcode) { 3302 case RESOURCE_OPCODE_RELEASED_PREVIOUS: 3303 DP_INFO(p_hwfn, 3304 "Resource unlock request for an already released resource [%d]\n", 3305 p_params->resource); 3306 /* Fallthrough */ 3307 case RESOURCE_OPCODE_RELEASED: 3308 p_params->b_released = true; 3309 break; 3310 case RESOURCE_OPCODE_WRONG_OWNER: 3311 p_params->b_released = false; 3312 break; 3313 default: 3314 DP_NOTICE(p_hwfn, 3315 "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n", 3316 mcp_param, opcode); 3317 return -EINVAL; 3318 } 3319 3320 return 0; 3321 } 3322 3323 void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock, 3324 struct qed_resc_unlock_params *p_unlock, 3325 enum qed_resc_lock 3326 resource, bool b_is_permanent) 3327 { 3328 if (p_lock) { 3329 memset(p_lock, 0, sizeof(*p_lock)); 3330 3331 /* Permanent resources don't require aging, and there's no 3332 * point in trying to acquire them more than once since it's 3333 * unexpected another entity would release them. 3334 */ 3335 if (b_is_permanent) { 3336 p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE; 3337 } else { 3338 p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT; 3339 p_lock->retry_interval = 3340 QED_MCP_RESC_LOCK_RETRY_VAL_DFLT; 3341 p_lock->sleep_b4_retry = true; 3342 } 3343 3344 p_lock->resource = resource; 3345 } 3346 3347 if (p_unlock) { 3348 memset(p_unlock, 0, sizeof(*p_unlock)); 3349 p_unlock->resource = resource; 3350 } 3351 } 3352 3353 int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3354 { 3355 u32 mcp_resp; 3356 int rc; 3357 3358 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT, 3359 0, &mcp_resp, &p_hwfn->mcp_info->capabilities); 3360 if (!rc) 3361 DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE), 3362 "MFW supported features: %08x\n", 3363 p_hwfn->mcp_info->capabilities); 3364 3365 return rc; 3366 } 3367 3368 int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3369 { 3370 u32 mcp_resp, mcp_param, features; 3371 3372 features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE | 3373 DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK; 3374 3375 return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT, 3376 features, &mcp_resp, &mcp_param); 3377 } 3378