1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/types.h> 34 #include <asm/byteorder.h> 35 #include <linux/delay.h> 36 #include <linux/errno.h> 37 #include <linux/kernel.h> 38 #include <linux/slab.h> 39 #include <linux/spinlock.h> 40 #include <linux/string.h> 41 #include <linux/etherdevice.h> 42 #include "qed.h" 43 #include "qed_cxt.h" 44 #include "qed_dcbx.h" 45 #include "qed_hsi.h" 46 #include "qed_hw.h" 47 #include "qed_mcp.h" 48 #include "qed_reg_addr.h" 49 #include "qed_sriov.h" 50 51 #define CHIP_MCP_RESP_ITER_US 10 52 53 #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */ 54 #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */ 55 56 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ 57 qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \ 58 _val) 59 60 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ 61 qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset)) 62 63 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \ 64 DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \ 65 offsetof(struct public_drv_mb, _field), _val) 66 67 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \ 68 DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \ 69 offsetof(struct public_drv_mb, _field)) 70 71 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \ 72 DRV_ID_PDA_COMP_VER_SHIFT) 73 74 #define MCP_BYTES_PER_MBIT_SHIFT 17 75 76 bool qed_mcp_is_init(struct qed_hwfn *p_hwfn) 77 { 78 if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) 79 return false; 80 return true; 81 } 82 83 void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 84 { 85 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 86 PUBLIC_PORT); 87 u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr); 88 89 p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, 90 MFW_PORT(p_hwfn)); 91 DP_VERBOSE(p_hwfn, QED_MSG_SP, 92 "port_addr = 0x%x, port_id 0x%02x\n", 93 p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); 94 } 95 96 void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 97 { 98 u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); 99 u32 tmp, i; 100 101 if (!p_hwfn->mcp_info->public_base) 102 return; 103 104 for (i = 0; i < length; i++) { 105 tmp = qed_rd(p_hwfn, p_ptt, 106 p_hwfn->mcp_info->mfw_mb_addr + 107 (i << 2) + sizeof(u32)); 108 109 /* The MB data is actually BE; Need to force it to cpu */ 110 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] = 111 be32_to_cpu((__force __be32)tmp); 112 } 113 } 114 115 struct qed_mcp_cmd_elem { 116 struct list_head list; 117 struct qed_mcp_mb_params *p_mb_params; 118 u16 expected_seq_num; 119 bool b_is_completed; 120 }; 121 122 /* Must be called while cmd_lock is acquired */ 123 static struct qed_mcp_cmd_elem * 124 qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn, 125 struct qed_mcp_mb_params *p_mb_params, 126 u16 expected_seq_num) 127 { 128 struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 129 130 p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC); 131 if (!p_cmd_elem) 132 goto out; 133 134 p_cmd_elem->p_mb_params = p_mb_params; 135 p_cmd_elem->expected_seq_num = expected_seq_num; 136 list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list); 137 out: 138 return p_cmd_elem; 139 } 140 141 /* Must be called while cmd_lock is acquired */ 142 static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn, 143 struct qed_mcp_cmd_elem *p_cmd_elem) 144 { 145 list_del(&p_cmd_elem->list); 146 kfree(p_cmd_elem); 147 } 148 149 /* Must be called while cmd_lock is acquired */ 150 static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn, 151 u16 seq_num) 152 { 153 struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 154 155 list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) { 156 if (p_cmd_elem->expected_seq_num == seq_num) 157 return p_cmd_elem; 158 } 159 160 return NULL; 161 } 162 163 int qed_mcp_free(struct qed_hwfn *p_hwfn) 164 { 165 if (p_hwfn->mcp_info) { 166 struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp; 167 168 kfree(p_hwfn->mcp_info->mfw_mb_cur); 169 kfree(p_hwfn->mcp_info->mfw_mb_shadow); 170 171 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 172 list_for_each_entry_safe(p_cmd_elem, 173 p_tmp, 174 &p_hwfn->mcp_info->cmd_list, list) { 175 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 176 } 177 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 178 } 179 180 kfree(p_hwfn->mcp_info); 181 p_hwfn->mcp_info = NULL; 182 183 return 0; 184 } 185 186 static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 187 { 188 struct qed_mcp_info *p_info = p_hwfn->mcp_info; 189 u32 drv_mb_offsize, mfw_mb_offsize; 190 u32 mcp_pf_id = MCP_PF_ID(p_hwfn); 191 192 p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR); 193 if (!p_info->public_base) 194 return 0; 195 196 p_info->public_base |= GRCBASE_MCP; 197 198 /* Calculate the driver and MFW mailbox address */ 199 drv_mb_offsize = qed_rd(p_hwfn, p_ptt, 200 SECTION_OFFSIZE_ADDR(p_info->public_base, 201 PUBLIC_DRV_MB)); 202 p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id); 203 DP_VERBOSE(p_hwfn, QED_MSG_SP, 204 "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n", 205 drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id); 206 207 /* Set the MFW MB address */ 208 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, 209 SECTION_OFFSIZE_ADDR(p_info->public_base, 210 PUBLIC_MFW_MB)); 211 p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id); 212 p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, p_info->mfw_mb_addr); 213 214 /* Get the current driver mailbox sequence before sending 215 * the first command 216 */ 217 p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 218 DRV_MSG_SEQ_NUMBER_MASK; 219 220 /* Get current FW pulse sequence */ 221 p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) & 222 DRV_PULSE_SEQ_MASK; 223 224 p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 225 226 return 0; 227 } 228 229 int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 230 { 231 struct qed_mcp_info *p_info; 232 u32 size; 233 234 /* Allocate mcp_info structure */ 235 p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL); 236 if (!p_hwfn->mcp_info) 237 goto err; 238 p_info = p_hwfn->mcp_info; 239 240 /* Initialize the MFW spinlock */ 241 spin_lock_init(&p_info->cmd_lock); 242 spin_lock_init(&p_info->link_lock); 243 244 INIT_LIST_HEAD(&p_info->cmd_list); 245 246 if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) { 247 DP_NOTICE(p_hwfn, "MCP is not initialized\n"); 248 /* Do not free mcp_info here, since public_base indicate that 249 * the MCP is not initialized 250 */ 251 return 0; 252 } 253 254 size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32); 255 p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL); 256 p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL); 257 if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow) 258 goto err; 259 260 return 0; 261 262 err: 263 qed_mcp_free(p_hwfn); 264 return -ENOMEM; 265 } 266 267 static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn, 268 struct qed_ptt *p_ptt) 269 { 270 u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 271 272 /* Use MCP history register to check if MCP reset occurred between init 273 * time and now. 274 */ 275 if (p_hwfn->mcp_info->mcp_hist != generic_por_0) { 276 DP_VERBOSE(p_hwfn, 277 QED_MSG_SP, 278 "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n", 279 p_hwfn->mcp_info->mcp_hist, generic_por_0); 280 281 qed_load_mcp_offsets(p_hwfn, p_ptt); 282 qed_mcp_cmd_port_init(p_hwfn, p_ptt); 283 } 284 } 285 286 int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 287 { 288 u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0; 289 int rc = 0; 290 291 /* Ensure that only a single thread is accessing the mailbox */ 292 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 293 294 org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 295 296 /* Set drv command along with the updated sequence */ 297 qed_mcp_reread_offsets(p_hwfn, p_ptt); 298 seq = ++p_hwfn->mcp_info->drv_mb_seq; 299 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq)); 300 301 do { 302 /* Wait for MFW response */ 303 udelay(delay); 304 /* Give the FW up to 500 second (50*1000*10usec) */ 305 } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt, 306 MISCS_REG_GENERIC_POR_0)) && 307 (cnt++ < QED_MCP_RESET_RETRIES)); 308 309 if (org_mcp_reset_seq != 310 qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 311 DP_VERBOSE(p_hwfn, QED_MSG_SP, 312 "MCP was reset after %d usec\n", cnt * delay); 313 } else { 314 DP_ERR(p_hwfn, "Failed to reset MCP\n"); 315 rc = -EAGAIN; 316 } 317 318 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 319 320 return rc; 321 } 322 323 /* Must be called while cmd_lock is acquired */ 324 static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn) 325 { 326 struct qed_mcp_cmd_elem *p_cmd_elem; 327 328 /* There is at most one pending command at a certain time, and if it 329 * exists - it is placed at the HEAD of the list. 330 */ 331 if (!list_empty(&p_hwfn->mcp_info->cmd_list)) { 332 p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list, 333 struct qed_mcp_cmd_elem, list); 334 return !p_cmd_elem->b_is_completed; 335 } 336 337 return false; 338 } 339 340 /* Must be called while cmd_lock is acquired */ 341 static int 342 qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 343 { 344 struct qed_mcp_mb_params *p_mb_params; 345 struct qed_mcp_cmd_elem *p_cmd_elem; 346 u32 mcp_resp; 347 u16 seq_num; 348 349 mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header); 350 seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK); 351 352 /* Return if no new non-handled response has been received */ 353 if (seq_num != p_hwfn->mcp_info->drv_mb_seq) 354 return -EAGAIN; 355 356 p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num); 357 if (!p_cmd_elem) { 358 DP_ERR(p_hwfn, 359 "Failed to find a pending mailbox cmd that expects sequence number %d\n", 360 seq_num); 361 return -EINVAL; 362 } 363 364 p_mb_params = p_cmd_elem->p_mb_params; 365 366 /* Get the MFW response along with the sequence number */ 367 p_mb_params->mcp_resp = mcp_resp; 368 369 /* Get the MFW param */ 370 p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param); 371 372 /* Get the union data */ 373 if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) { 374 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 375 offsetof(struct public_drv_mb, 376 union_data); 377 qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst, 378 union_data_addr, p_mb_params->data_dst_size); 379 } 380 381 p_cmd_elem->b_is_completed = true; 382 383 return 0; 384 } 385 386 /* Must be called while cmd_lock is acquired */ 387 static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 388 struct qed_ptt *p_ptt, 389 struct qed_mcp_mb_params *p_mb_params, 390 u16 seq_num) 391 { 392 union drv_union_data union_data; 393 u32 union_data_addr; 394 395 /* Set the union data */ 396 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 397 offsetof(struct public_drv_mb, union_data); 398 memset(&union_data, 0, sizeof(union_data)); 399 if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size) 400 memcpy(&union_data, p_mb_params->p_data_src, 401 p_mb_params->data_src_size); 402 qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data, 403 sizeof(union_data)); 404 405 /* Set the drv param */ 406 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param); 407 408 /* Set the drv command along with the sequence number */ 409 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num)); 410 411 DP_VERBOSE(p_hwfn, QED_MSG_SP, 412 "MFW mailbox: command 0x%08x param 0x%08x\n", 413 (p_mb_params->cmd | seq_num), p_mb_params->param); 414 } 415 416 static int 417 _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 418 struct qed_ptt *p_ptt, 419 struct qed_mcp_mb_params *p_mb_params, 420 u32 max_retries, u32 delay) 421 { 422 struct qed_mcp_cmd_elem *p_cmd_elem; 423 u32 cnt = 0; 424 u16 seq_num; 425 int rc = 0; 426 427 /* Wait until the mailbox is non-occupied */ 428 do { 429 /* Exit the loop if there is no pending command, or if the 430 * pending command is completed during this iteration. 431 * The spinlock stays locked until the command is sent. 432 */ 433 434 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 435 436 if (!qed_mcp_has_pending_cmd(p_hwfn)) 437 break; 438 439 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 440 if (!rc) 441 break; 442 else if (rc != -EAGAIN) 443 goto err; 444 445 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 446 udelay(delay); 447 } while (++cnt < max_retries); 448 449 if (cnt >= max_retries) { 450 DP_NOTICE(p_hwfn, 451 "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n", 452 p_mb_params->cmd, p_mb_params->param); 453 return -EAGAIN; 454 } 455 456 /* Send the mailbox command */ 457 qed_mcp_reread_offsets(p_hwfn, p_ptt); 458 seq_num = ++p_hwfn->mcp_info->drv_mb_seq; 459 p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num); 460 if (!p_cmd_elem) { 461 rc = -ENOMEM; 462 goto err; 463 } 464 465 __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num); 466 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 467 468 /* Wait for the MFW response */ 469 do { 470 /* Exit the loop if the command is already completed, or if the 471 * command is completed during this iteration. 472 * The spinlock stays locked until the list element is removed. 473 */ 474 475 udelay(delay); 476 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 477 478 if (p_cmd_elem->b_is_completed) 479 break; 480 481 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 482 if (!rc) 483 break; 484 else if (rc != -EAGAIN) 485 goto err; 486 487 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 488 } while (++cnt < max_retries); 489 490 if (cnt >= max_retries) { 491 DP_NOTICE(p_hwfn, 492 "The MFW failed to respond to command 0x%08x [param 0x%08x].\n", 493 p_mb_params->cmd, p_mb_params->param); 494 495 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 496 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 497 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 498 499 return -EAGAIN; 500 } 501 502 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 503 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 504 505 DP_VERBOSE(p_hwfn, 506 QED_MSG_SP, 507 "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n", 508 p_mb_params->mcp_resp, 509 p_mb_params->mcp_param, 510 (cnt * delay) / 1000, (cnt * delay) % 1000); 511 512 /* Clear the sequence number from the MFW response */ 513 p_mb_params->mcp_resp &= FW_MSG_CODE_MASK; 514 515 return 0; 516 517 err: 518 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 519 return rc; 520 } 521 522 static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 523 struct qed_ptt *p_ptt, 524 struct qed_mcp_mb_params *p_mb_params) 525 { 526 size_t union_data_size = sizeof(union drv_union_data); 527 u32 max_retries = QED_DRV_MB_MAX_RETRIES; 528 u32 delay = CHIP_MCP_RESP_ITER_US; 529 530 /* MCP not initialized */ 531 if (!qed_mcp_is_init(p_hwfn)) { 532 DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 533 return -EBUSY; 534 } 535 536 if (p_mb_params->data_src_size > union_data_size || 537 p_mb_params->data_dst_size > union_data_size) { 538 DP_ERR(p_hwfn, 539 "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n", 540 p_mb_params->data_src_size, 541 p_mb_params->data_dst_size, union_data_size); 542 return -EINVAL; 543 } 544 545 return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries, 546 delay); 547 } 548 549 int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 550 struct qed_ptt *p_ptt, 551 u32 cmd, 552 u32 param, 553 u32 *o_mcp_resp, 554 u32 *o_mcp_param) 555 { 556 struct qed_mcp_mb_params mb_params; 557 int rc; 558 559 memset(&mb_params, 0, sizeof(mb_params)); 560 mb_params.cmd = cmd; 561 mb_params.param = param; 562 563 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 564 if (rc) 565 return rc; 566 567 *o_mcp_resp = mb_params.mcp_resp; 568 *o_mcp_param = mb_params.mcp_param; 569 570 return 0; 571 } 572 573 int qed_mcp_nvm_wr_cmd(struct qed_hwfn *p_hwfn, 574 struct qed_ptt *p_ptt, 575 u32 cmd, 576 u32 param, 577 u32 *o_mcp_resp, 578 u32 *o_mcp_param, u32 i_txn_size, u32 *i_buf) 579 { 580 struct qed_mcp_mb_params mb_params; 581 int rc; 582 583 memset(&mb_params, 0, sizeof(mb_params)); 584 mb_params.cmd = cmd; 585 mb_params.param = param; 586 mb_params.p_data_src = i_buf; 587 mb_params.data_src_size = (u8)i_txn_size; 588 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 589 if (rc) 590 return rc; 591 592 *o_mcp_resp = mb_params.mcp_resp; 593 *o_mcp_param = mb_params.mcp_param; 594 595 return 0; 596 } 597 598 int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 599 struct qed_ptt *p_ptt, 600 u32 cmd, 601 u32 param, 602 u32 *o_mcp_resp, 603 u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf) 604 { 605 struct qed_mcp_mb_params mb_params; 606 u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 607 int rc; 608 609 memset(&mb_params, 0, sizeof(mb_params)); 610 mb_params.cmd = cmd; 611 mb_params.param = param; 612 mb_params.p_data_dst = raw_data; 613 614 /* Use the maximal value since the actual one is part of the response */ 615 mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN; 616 617 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 618 if (rc) 619 return rc; 620 621 *o_mcp_resp = mb_params.mcp_resp; 622 *o_mcp_param = mb_params.mcp_param; 623 624 *o_txn_size = *o_mcp_param; 625 memcpy(o_buf, raw_data, *o_txn_size); 626 627 return 0; 628 } 629 630 static bool 631 qed_mcp_can_force_load(u8 drv_role, 632 u8 exist_drv_role, 633 enum qed_override_force_load override_force_load) 634 { 635 bool can_force_load = false; 636 637 switch (override_force_load) { 638 case QED_OVERRIDE_FORCE_LOAD_ALWAYS: 639 can_force_load = true; 640 break; 641 case QED_OVERRIDE_FORCE_LOAD_NEVER: 642 can_force_load = false; 643 break; 644 default: 645 can_force_load = (drv_role == DRV_ROLE_OS && 646 exist_drv_role == DRV_ROLE_PREBOOT) || 647 (drv_role == DRV_ROLE_KDUMP && 648 exist_drv_role == DRV_ROLE_OS); 649 break; 650 } 651 652 return can_force_load; 653 } 654 655 static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn, 656 struct qed_ptt *p_ptt) 657 { 658 u32 resp = 0, param = 0; 659 int rc; 660 661 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0, 662 &resp, ¶m); 663 if (rc) 664 DP_NOTICE(p_hwfn, 665 "Failed to send cancel load request, rc = %d\n", rc); 666 667 return rc; 668 } 669 670 #define CONFIG_QEDE_BITMAP_IDX BIT(0) 671 #define CONFIG_QED_SRIOV_BITMAP_IDX BIT(1) 672 #define CONFIG_QEDR_BITMAP_IDX BIT(2) 673 #define CONFIG_QEDF_BITMAP_IDX BIT(4) 674 #define CONFIG_QEDI_BITMAP_IDX BIT(5) 675 #define CONFIG_QED_LL2_BITMAP_IDX BIT(6) 676 677 static u32 qed_get_config_bitmap(void) 678 { 679 u32 config_bitmap = 0x0; 680 681 if (IS_ENABLED(CONFIG_QEDE)) 682 config_bitmap |= CONFIG_QEDE_BITMAP_IDX; 683 684 if (IS_ENABLED(CONFIG_QED_SRIOV)) 685 config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX; 686 687 if (IS_ENABLED(CONFIG_QED_RDMA)) 688 config_bitmap |= CONFIG_QEDR_BITMAP_IDX; 689 690 if (IS_ENABLED(CONFIG_QED_FCOE)) 691 config_bitmap |= CONFIG_QEDF_BITMAP_IDX; 692 693 if (IS_ENABLED(CONFIG_QED_ISCSI)) 694 config_bitmap |= CONFIG_QEDI_BITMAP_IDX; 695 696 if (IS_ENABLED(CONFIG_QED_LL2)) 697 config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX; 698 699 return config_bitmap; 700 } 701 702 struct qed_load_req_in_params { 703 u8 hsi_ver; 704 #define QED_LOAD_REQ_HSI_VER_DEFAULT 0 705 #define QED_LOAD_REQ_HSI_VER_1 1 706 u32 drv_ver_0; 707 u32 drv_ver_1; 708 u32 fw_ver; 709 u8 drv_role; 710 u8 timeout_val; 711 u8 force_cmd; 712 bool avoid_eng_reset; 713 }; 714 715 struct qed_load_req_out_params { 716 u32 load_code; 717 u32 exist_drv_ver_0; 718 u32 exist_drv_ver_1; 719 u32 exist_fw_ver; 720 u8 exist_drv_role; 721 u8 mfw_hsi_ver; 722 bool drv_exists; 723 }; 724 725 static int 726 __qed_mcp_load_req(struct qed_hwfn *p_hwfn, 727 struct qed_ptt *p_ptt, 728 struct qed_load_req_in_params *p_in_params, 729 struct qed_load_req_out_params *p_out_params) 730 { 731 struct qed_mcp_mb_params mb_params; 732 struct load_req_stc load_req; 733 struct load_rsp_stc load_rsp; 734 u32 hsi_ver; 735 int rc; 736 737 memset(&load_req, 0, sizeof(load_req)); 738 load_req.drv_ver_0 = p_in_params->drv_ver_0; 739 load_req.drv_ver_1 = p_in_params->drv_ver_1; 740 load_req.fw_ver = p_in_params->fw_ver; 741 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role); 742 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO, 743 p_in_params->timeout_val); 744 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE, 745 p_in_params->force_cmd); 746 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0, 747 p_in_params->avoid_eng_reset); 748 749 hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ? 750 DRV_ID_MCP_HSI_VER_CURRENT : 751 (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT); 752 753 memset(&mb_params, 0, sizeof(mb_params)); 754 mb_params.cmd = DRV_MSG_CODE_LOAD_REQ; 755 mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type; 756 mb_params.p_data_src = &load_req; 757 mb_params.data_src_size = sizeof(load_req); 758 mb_params.p_data_dst = &load_rsp; 759 mb_params.data_dst_size = sizeof(load_rsp); 760 761 DP_VERBOSE(p_hwfn, QED_MSG_SP, 762 "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n", 763 mb_params.param, 764 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW), 765 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE), 766 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER), 767 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER)); 768 769 if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) { 770 DP_VERBOSE(p_hwfn, QED_MSG_SP, 771 "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n", 772 load_req.drv_ver_0, 773 load_req.drv_ver_1, 774 load_req.fw_ver, 775 load_req.misc0, 776 QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE), 777 QED_MFW_GET_FIELD(load_req.misc0, 778 LOAD_REQ_LOCK_TO), 779 QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE), 780 QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0)); 781 } 782 783 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 784 if (rc) { 785 DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc); 786 return rc; 787 } 788 789 DP_VERBOSE(p_hwfn, QED_MSG_SP, 790 "Load Response: resp 0x%08x\n", mb_params.mcp_resp); 791 p_out_params->load_code = mb_params.mcp_resp; 792 793 if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 794 p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 795 DP_VERBOSE(p_hwfn, 796 QED_MSG_SP, 797 "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n", 798 load_rsp.drv_ver_0, 799 load_rsp.drv_ver_1, 800 load_rsp.fw_ver, 801 load_rsp.misc0, 802 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE), 803 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI), 804 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0)); 805 806 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0; 807 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1; 808 p_out_params->exist_fw_ver = load_rsp.fw_ver; 809 p_out_params->exist_drv_role = 810 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE); 811 p_out_params->mfw_hsi_ver = 812 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI); 813 p_out_params->drv_exists = 814 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) & 815 LOAD_RSP_FLAGS0_DRV_EXISTS; 816 } 817 818 return 0; 819 } 820 821 static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn, 822 enum qed_drv_role drv_role, 823 u8 *p_mfw_drv_role) 824 { 825 switch (drv_role) { 826 case QED_DRV_ROLE_OS: 827 *p_mfw_drv_role = DRV_ROLE_OS; 828 break; 829 case QED_DRV_ROLE_KDUMP: 830 *p_mfw_drv_role = DRV_ROLE_KDUMP; 831 break; 832 default: 833 DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role); 834 return -EINVAL; 835 } 836 837 return 0; 838 } 839 840 enum qed_load_req_force { 841 QED_LOAD_REQ_FORCE_NONE, 842 QED_LOAD_REQ_FORCE_PF, 843 QED_LOAD_REQ_FORCE_ALL, 844 }; 845 846 static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn, 847 848 enum qed_load_req_force force_cmd, 849 u8 *p_mfw_force_cmd) 850 { 851 switch (force_cmd) { 852 case QED_LOAD_REQ_FORCE_NONE: 853 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE; 854 break; 855 case QED_LOAD_REQ_FORCE_PF: 856 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF; 857 break; 858 case QED_LOAD_REQ_FORCE_ALL: 859 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL; 860 break; 861 } 862 } 863 864 int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 865 struct qed_ptt *p_ptt, 866 struct qed_load_req_params *p_params) 867 { 868 struct qed_load_req_out_params out_params; 869 struct qed_load_req_in_params in_params; 870 u8 mfw_drv_role, mfw_force_cmd; 871 int rc; 872 873 memset(&in_params, 0, sizeof(in_params)); 874 in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT; 875 in_params.drv_ver_0 = QED_VERSION; 876 in_params.drv_ver_1 = qed_get_config_bitmap(); 877 in_params.fw_ver = STORM_FW_VERSION; 878 rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role); 879 if (rc) 880 return rc; 881 882 in_params.drv_role = mfw_drv_role; 883 in_params.timeout_val = p_params->timeout_val; 884 qed_get_mfw_force_cmd(p_hwfn, 885 QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd); 886 887 in_params.force_cmd = mfw_force_cmd; 888 in_params.avoid_eng_reset = p_params->avoid_eng_reset; 889 890 memset(&out_params, 0, sizeof(out_params)); 891 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 892 if (rc) 893 return rc; 894 895 /* First handle cases where another load request should/might be sent: 896 * - MFW expects the old interface [HSI version = 1] 897 * - MFW responds that a force load request is required 898 */ 899 if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 900 DP_INFO(p_hwfn, 901 "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n"); 902 903 in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1; 904 memset(&out_params, 0, sizeof(out_params)); 905 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 906 if (rc) 907 return rc; 908 } else if (out_params.load_code == 909 FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) { 910 if (qed_mcp_can_force_load(in_params.drv_role, 911 out_params.exist_drv_role, 912 p_params->override_force_load)) { 913 DP_INFO(p_hwfn, 914 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n", 915 in_params.drv_role, in_params.fw_ver, 916 in_params.drv_ver_0, in_params.drv_ver_1, 917 out_params.exist_drv_role, 918 out_params.exist_fw_ver, 919 out_params.exist_drv_ver_0, 920 out_params.exist_drv_ver_1); 921 922 qed_get_mfw_force_cmd(p_hwfn, 923 QED_LOAD_REQ_FORCE_ALL, 924 &mfw_force_cmd); 925 926 in_params.force_cmd = mfw_force_cmd; 927 memset(&out_params, 0, sizeof(out_params)); 928 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, 929 &out_params); 930 if (rc) 931 return rc; 932 } else { 933 DP_NOTICE(p_hwfn, 934 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n", 935 in_params.drv_role, in_params.fw_ver, 936 in_params.drv_ver_0, in_params.drv_ver_1, 937 out_params.exist_drv_role, 938 out_params.exist_fw_ver, 939 out_params.exist_drv_ver_0, 940 out_params.exist_drv_ver_1); 941 DP_NOTICE(p_hwfn, 942 "Avoid sending a force load request to prevent disruption of active PFs\n"); 943 944 qed_mcp_cancel_load_req(p_hwfn, p_ptt); 945 return -EBUSY; 946 } 947 } 948 949 /* Now handle the other types of responses. 950 * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not 951 * expected here after the additional revised load requests were sent. 952 */ 953 switch (out_params.load_code) { 954 case FW_MSG_CODE_DRV_LOAD_ENGINE: 955 case FW_MSG_CODE_DRV_LOAD_PORT: 956 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 957 if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 958 out_params.drv_exists) { 959 /* The role and fw/driver version match, but the PF is 960 * already loaded and has not been unloaded gracefully. 961 */ 962 DP_NOTICE(p_hwfn, 963 "PF is already loaded\n"); 964 return -EINVAL; 965 } 966 break; 967 default: 968 DP_NOTICE(p_hwfn, 969 "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n", 970 out_params.load_code); 971 return -EBUSY; 972 } 973 974 p_params->load_code = out_params.load_code; 975 976 return 0; 977 } 978 979 int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 980 { 981 u32 wol_param, mcp_resp, mcp_param; 982 983 switch (p_hwfn->cdev->wol_config) { 984 case QED_OV_WOL_DISABLED: 985 wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED; 986 break; 987 case QED_OV_WOL_ENABLED: 988 wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED; 989 break; 990 default: 991 DP_NOTICE(p_hwfn, 992 "Unknown WoL configuration %02x\n", 993 p_hwfn->cdev->wol_config); 994 /* Fallthrough */ 995 case QED_OV_WOL_DEFAULT: 996 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP; 997 } 998 999 return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param, 1000 &mcp_resp, &mcp_param); 1001 } 1002 1003 int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1004 { 1005 struct qed_mcp_mb_params mb_params; 1006 struct mcp_mac wol_mac; 1007 1008 memset(&mb_params, 0, sizeof(mb_params)); 1009 mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE; 1010 1011 /* Set the primary MAC if WoL is enabled */ 1012 if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) { 1013 u8 *p_mac = p_hwfn->cdev->wol_mac; 1014 1015 memset(&wol_mac, 0, sizeof(wol_mac)); 1016 wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1]; 1017 wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 | 1018 p_mac[4] << 8 | p_mac[5]; 1019 1020 DP_VERBOSE(p_hwfn, 1021 (QED_MSG_SP | NETIF_MSG_IFDOWN), 1022 "Setting WoL MAC: %pM --> [%08x,%08x]\n", 1023 p_mac, wol_mac.mac_upper, wol_mac.mac_lower); 1024 1025 mb_params.p_data_src = &wol_mac; 1026 mb_params.data_src_size = sizeof(wol_mac); 1027 } 1028 1029 return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1030 } 1031 1032 static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn, 1033 struct qed_ptt *p_ptt) 1034 { 1035 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 1036 PUBLIC_PATH); 1037 u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 1038 u32 path_addr = SECTION_ADDR(mfw_path_offsize, 1039 QED_PATH_ID(p_hwfn)); 1040 u32 disabled_vfs[VF_MAX_STATIC / 32]; 1041 int i; 1042 1043 DP_VERBOSE(p_hwfn, 1044 QED_MSG_SP, 1045 "Reading Disabled VF information from [offset %08x], path_addr %08x\n", 1046 mfw_path_offsize, path_addr); 1047 1048 for (i = 0; i < (VF_MAX_STATIC / 32); i++) { 1049 disabled_vfs[i] = qed_rd(p_hwfn, p_ptt, 1050 path_addr + 1051 offsetof(struct public_path, 1052 mcp_vf_disabled) + 1053 sizeof(u32) * i); 1054 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 1055 "FLR-ed VFs [%08x,...,%08x] - %08x\n", 1056 i * 32, (i + 1) * 32 - 1, disabled_vfs[i]); 1057 } 1058 1059 if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs)) 1060 qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); 1061 } 1062 1063 int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 1064 struct qed_ptt *p_ptt, u32 *vfs_to_ack) 1065 { 1066 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 1067 PUBLIC_FUNC); 1068 u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr); 1069 u32 func_addr = SECTION_ADDR(mfw_func_offsize, 1070 MCP_PF_ID(p_hwfn)); 1071 struct qed_mcp_mb_params mb_params; 1072 int rc; 1073 int i; 1074 1075 for (i = 0; i < (VF_MAX_STATIC / 32); i++) 1076 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 1077 "Acking VFs [%08x,...,%08x] - %08x\n", 1078 i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]); 1079 1080 memset(&mb_params, 0, sizeof(mb_params)); 1081 mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE; 1082 mb_params.p_data_src = vfs_to_ack; 1083 mb_params.data_src_size = VF_MAX_STATIC / 8; 1084 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1085 if (rc) { 1086 DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n"); 1087 return -EBUSY; 1088 } 1089 1090 /* Clear the ACK bits */ 1091 for (i = 0; i < (VF_MAX_STATIC / 32); i++) 1092 qed_wr(p_hwfn, p_ptt, 1093 func_addr + 1094 offsetof(struct public_func, drv_ack_vf_disabled) + 1095 i * sizeof(u32), 0); 1096 1097 return rc; 1098 } 1099 1100 static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn, 1101 struct qed_ptt *p_ptt) 1102 { 1103 u32 transceiver_state; 1104 1105 transceiver_state = qed_rd(p_hwfn, p_ptt, 1106 p_hwfn->mcp_info->port_addr + 1107 offsetof(struct public_port, 1108 transceiver_data)); 1109 1110 DP_VERBOSE(p_hwfn, 1111 (NETIF_MSG_HW | QED_MSG_SP), 1112 "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n", 1113 transceiver_state, 1114 (u32)(p_hwfn->mcp_info->port_addr + 1115 offsetof(struct public_port, transceiver_data))); 1116 1117 transceiver_state = GET_FIELD(transceiver_state, 1118 ETH_TRANSCEIVER_STATE); 1119 1120 if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 1121 DP_NOTICE(p_hwfn, "Transceiver is present.\n"); 1122 else 1123 DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n"); 1124 } 1125 1126 static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn, 1127 struct qed_ptt *p_ptt, 1128 struct qed_mcp_link_state *p_link) 1129 { 1130 u32 eee_status, val; 1131 1132 p_link->eee_adv_caps = 0; 1133 p_link->eee_lp_adv_caps = 0; 1134 eee_status = qed_rd(p_hwfn, 1135 p_ptt, 1136 p_hwfn->mcp_info->port_addr + 1137 offsetof(struct public_port, eee_status)); 1138 p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT); 1139 val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET; 1140 if (val & EEE_1G_ADV) 1141 p_link->eee_adv_caps |= QED_EEE_1G_ADV; 1142 if (val & EEE_10G_ADV) 1143 p_link->eee_adv_caps |= QED_EEE_10G_ADV; 1144 val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET; 1145 if (val & EEE_1G_ADV) 1146 p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV; 1147 if (val & EEE_10G_ADV) 1148 p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV; 1149 } 1150 1151 static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn, 1152 struct qed_ptt *p_ptt, bool b_reset) 1153 { 1154 struct qed_mcp_link_state *p_link; 1155 u8 max_bw, min_bw; 1156 u32 status = 0; 1157 1158 /* Prevent SW/attentions from doing this at the same time */ 1159 spin_lock_bh(&p_hwfn->mcp_info->link_lock); 1160 1161 p_link = &p_hwfn->mcp_info->link_output; 1162 memset(p_link, 0, sizeof(*p_link)); 1163 if (!b_reset) { 1164 status = qed_rd(p_hwfn, p_ptt, 1165 p_hwfn->mcp_info->port_addr + 1166 offsetof(struct public_port, link_status)); 1167 DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP), 1168 "Received link update [0x%08x] from mfw [Addr 0x%x]\n", 1169 status, 1170 (u32)(p_hwfn->mcp_info->port_addr + 1171 offsetof(struct public_port, link_status))); 1172 } else { 1173 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1174 "Resetting link indications\n"); 1175 goto out; 1176 } 1177 1178 if (p_hwfn->b_drv_link_init) 1179 p_link->link_up = !!(status & LINK_STATUS_LINK_UP); 1180 else 1181 p_link->link_up = false; 1182 1183 p_link->full_duplex = true; 1184 switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) { 1185 case LINK_STATUS_SPEED_AND_DUPLEX_100G: 1186 p_link->speed = 100000; 1187 break; 1188 case LINK_STATUS_SPEED_AND_DUPLEX_50G: 1189 p_link->speed = 50000; 1190 break; 1191 case LINK_STATUS_SPEED_AND_DUPLEX_40G: 1192 p_link->speed = 40000; 1193 break; 1194 case LINK_STATUS_SPEED_AND_DUPLEX_25G: 1195 p_link->speed = 25000; 1196 break; 1197 case LINK_STATUS_SPEED_AND_DUPLEX_20G: 1198 p_link->speed = 20000; 1199 break; 1200 case LINK_STATUS_SPEED_AND_DUPLEX_10G: 1201 p_link->speed = 10000; 1202 break; 1203 case LINK_STATUS_SPEED_AND_DUPLEX_1000THD: 1204 p_link->full_duplex = false; 1205 /* Fall-through */ 1206 case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD: 1207 p_link->speed = 1000; 1208 break; 1209 default: 1210 p_link->speed = 0; 1211 } 1212 1213 if (p_link->link_up && p_link->speed) 1214 p_link->line_speed = p_link->speed; 1215 else 1216 p_link->line_speed = 0; 1217 1218 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max; 1219 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min; 1220 1221 /* Max bandwidth configuration */ 1222 __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw); 1223 1224 /* Min bandwidth configuration */ 1225 __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw); 1226 qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt, 1227 p_link->min_pf_rate); 1228 1229 p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); 1230 p_link->an_complete = !!(status & 1231 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE); 1232 p_link->parallel_detection = !!(status & 1233 LINK_STATUS_PARALLEL_DETECTION_USED); 1234 p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED); 1235 1236 p_link->partner_adv_speed |= 1237 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ? 1238 QED_LINK_PARTNER_SPEED_1G_FD : 0; 1239 p_link->partner_adv_speed |= 1240 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ? 1241 QED_LINK_PARTNER_SPEED_1G_HD : 0; 1242 p_link->partner_adv_speed |= 1243 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ? 1244 QED_LINK_PARTNER_SPEED_10G : 0; 1245 p_link->partner_adv_speed |= 1246 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ? 1247 QED_LINK_PARTNER_SPEED_20G : 0; 1248 p_link->partner_adv_speed |= 1249 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ? 1250 QED_LINK_PARTNER_SPEED_25G : 0; 1251 p_link->partner_adv_speed |= 1252 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ? 1253 QED_LINK_PARTNER_SPEED_40G : 0; 1254 p_link->partner_adv_speed |= 1255 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ? 1256 QED_LINK_PARTNER_SPEED_50G : 0; 1257 p_link->partner_adv_speed |= 1258 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ? 1259 QED_LINK_PARTNER_SPEED_100G : 0; 1260 1261 p_link->partner_tx_flow_ctrl_en = 1262 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED); 1263 p_link->partner_rx_flow_ctrl_en = 1264 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 1265 1266 switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) { 1267 case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE: 1268 p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE; 1269 break; 1270 case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE: 1271 p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE; 1272 break; 1273 case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE: 1274 p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE; 1275 break; 1276 default: 1277 p_link->partner_adv_pause = 0; 1278 } 1279 1280 p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT); 1281 1282 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) 1283 qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link); 1284 1285 qed_link_update(p_hwfn); 1286 out: 1287 spin_unlock_bh(&p_hwfn->mcp_info->link_lock); 1288 } 1289 1290 int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up) 1291 { 1292 struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input; 1293 struct qed_mcp_mb_params mb_params; 1294 struct eth_phy_cfg phy_cfg; 1295 int rc = 0; 1296 u32 cmd; 1297 1298 /* Set the shmem configuration according to params */ 1299 memset(&phy_cfg, 0, sizeof(phy_cfg)); 1300 cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET; 1301 if (!params->speed.autoneg) 1302 phy_cfg.speed = params->speed.forced_speed; 1303 phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0; 1304 phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0; 1305 phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0; 1306 phy_cfg.adv_speed = params->speed.advertised_speeds; 1307 phy_cfg.loopback_mode = params->loopback_mode; 1308 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) { 1309 if (params->eee.enable) 1310 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED; 1311 if (params->eee.tx_lpi_enable) 1312 phy_cfg.eee_cfg |= EEE_CFG_TX_LPI; 1313 if (params->eee.adv_caps & QED_EEE_1G_ADV) 1314 phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G; 1315 if (params->eee.adv_caps & QED_EEE_10G_ADV) 1316 phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G; 1317 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer << 1318 EEE_TX_TIMER_USEC_OFFSET) & 1319 EEE_TX_TIMER_USEC_MASK; 1320 } 1321 1322 p_hwfn->b_drv_link_init = b_up; 1323 1324 if (b_up) { 1325 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1326 "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n", 1327 phy_cfg.speed, 1328 phy_cfg.pause, 1329 phy_cfg.adv_speed, 1330 phy_cfg.loopback_mode, 1331 phy_cfg.feature_config_flags); 1332 } else { 1333 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1334 "Resetting link\n"); 1335 } 1336 1337 memset(&mb_params, 0, sizeof(mb_params)); 1338 mb_params.cmd = cmd; 1339 mb_params.p_data_src = &phy_cfg; 1340 mb_params.data_src_size = sizeof(phy_cfg); 1341 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1342 1343 /* if mcp fails to respond we must abort */ 1344 if (rc) { 1345 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1346 return rc; 1347 } 1348 1349 /* Mimic link-change attention, done for several reasons: 1350 * - On reset, there's no guarantee MFW would trigger 1351 * an attention. 1352 * - On initialization, older MFWs might not indicate link change 1353 * during LFA, so we'll never get an UP indication. 1354 */ 1355 qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up); 1356 1357 return 0; 1358 } 1359 1360 static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn, 1361 struct qed_ptt *p_ptt, 1362 enum MFW_DRV_MSG_TYPE type) 1363 { 1364 enum qed_mcp_protocol_type stats_type; 1365 union qed_mcp_protocol_stats stats; 1366 struct qed_mcp_mb_params mb_params; 1367 u32 hsi_param; 1368 1369 switch (type) { 1370 case MFW_DRV_MSG_GET_LAN_STATS: 1371 stats_type = QED_MCP_LAN_STATS; 1372 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN; 1373 break; 1374 case MFW_DRV_MSG_GET_FCOE_STATS: 1375 stats_type = QED_MCP_FCOE_STATS; 1376 hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE; 1377 break; 1378 case MFW_DRV_MSG_GET_ISCSI_STATS: 1379 stats_type = QED_MCP_ISCSI_STATS; 1380 hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI; 1381 break; 1382 case MFW_DRV_MSG_GET_RDMA_STATS: 1383 stats_type = QED_MCP_RDMA_STATS; 1384 hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA; 1385 break; 1386 default: 1387 DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type); 1388 return; 1389 } 1390 1391 qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats); 1392 1393 memset(&mb_params, 0, sizeof(mb_params)); 1394 mb_params.cmd = DRV_MSG_CODE_GET_STATS; 1395 mb_params.param = hsi_param; 1396 mb_params.p_data_src = &stats; 1397 mb_params.data_src_size = sizeof(stats); 1398 qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1399 } 1400 1401 static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn, 1402 struct public_func *p_shmem_info) 1403 { 1404 struct qed_mcp_function_info *p_info; 1405 1406 p_info = &p_hwfn->mcp_info->func_info; 1407 1408 p_info->bandwidth_min = (p_shmem_info->config & 1409 FUNC_MF_CFG_MIN_BW_MASK) >> 1410 FUNC_MF_CFG_MIN_BW_SHIFT; 1411 if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) { 1412 DP_INFO(p_hwfn, 1413 "bandwidth minimum out of bounds [%02x]. Set to 1\n", 1414 p_info->bandwidth_min); 1415 p_info->bandwidth_min = 1; 1416 } 1417 1418 p_info->bandwidth_max = (p_shmem_info->config & 1419 FUNC_MF_CFG_MAX_BW_MASK) >> 1420 FUNC_MF_CFG_MAX_BW_SHIFT; 1421 if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) { 1422 DP_INFO(p_hwfn, 1423 "bandwidth maximum out of bounds [%02x]. Set to 100\n", 1424 p_info->bandwidth_max); 1425 p_info->bandwidth_max = 100; 1426 } 1427 } 1428 1429 static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn, 1430 struct qed_ptt *p_ptt, 1431 struct public_func *p_data, int pfid) 1432 { 1433 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 1434 PUBLIC_FUNC); 1435 u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 1436 u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid); 1437 u32 i, size; 1438 1439 memset(p_data, 0, sizeof(*p_data)); 1440 1441 size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize)); 1442 for (i = 0; i < size / sizeof(u32); i++) 1443 ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt, 1444 func_addr + (i << 2)); 1445 return size; 1446 } 1447 1448 static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1449 { 1450 struct qed_mcp_function_info *p_info; 1451 struct public_func shmem_info; 1452 u32 resp = 0, param = 0; 1453 1454 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1455 1456 qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1457 1458 p_info = &p_hwfn->mcp_info->func_info; 1459 1460 qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min); 1461 qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max); 1462 1463 /* Acknowledge the MFW */ 1464 qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp, 1465 ¶m); 1466 } 1467 1468 static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1469 { 1470 struct public_func shmem_info; 1471 u32 resp = 0, param = 0; 1472 1473 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1474 1475 p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag & 1476 FUNC_MF_CFG_OV_STAG_MASK; 1477 p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan; 1478 if ((p_hwfn->hw_info.hw_mode & BIT(MODE_MF_SD)) && 1479 (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET)) { 1480 qed_wr(p_hwfn, p_ptt, 1481 NIG_REG_LLH_FUNC_TAG_VALUE, p_hwfn->hw_info.ovlan); 1482 qed_sp_pf_update_stag(p_hwfn); 1483 } 1484 1485 /* Acknowledge the MFW */ 1486 qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0, 1487 &resp, ¶m); 1488 } 1489 1490 void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1491 { 1492 struct public_func shmem_info; 1493 u32 port_cfg, val; 1494 1495 if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits)) 1496 return; 1497 1498 memset(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info)); 1499 port_cfg = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1500 offsetof(struct public_port, oem_cfg_port)); 1501 val = (port_cfg & OEM_CFG_CHANNEL_TYPE_MASK) >> 1502 OEM_CFG_CHANNEL_TYPE_OFFSET; 1503 if (val != OEM_CFG_CHANNEL_TYPE_STAGGED) 1504 DP_NOTICE(p_hwfn, "Incorrect UFP Channel type %d\n", val); 1505 1506 val = (port_cfg & OEM_CFG_SCHED_TYPE_MASK) >> OEM_CFG_SCHED_TYPE_OFFSET; 1507 if (val == OEM_CFG_SCHED_TYPE_ETS) { 1508 p_hwfn->ufp_info.mode = QED_UFP_MODE_ETS; 1509 } else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW) { 1510 p_hwfn->ufp_info.mode = QED_UFP_MODE_VNIC_BW; 1511 } else { 1512 p_hwfn->ufp_info.mode = QED_UFP_MODE_UNKNOWN; 1513 DP_NOTICE(p_hwfn, "Unknown UFP scheduling mode %d\n", val); 1514 } 1515 1516 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1517 val = (port_cfg & OEM_CFG_FUNC_TC_MASK) >> OEM_CFG_FUNC_TC_OFFSET; 1518 p_hwfn->ufp_info.tc = (u8)val; 1519 val = (port_cfg & OEM_CFG_FUNC_HOST_PRI_CTRL_MASK) >> 1520 OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET; 1521 if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC) { 1522 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_VNIC; 1523 } else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS) { 1524 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_OS; 1525 } else { 1526 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_UNKNOWN; 1527 DP_NOTICE(p_hwfn, "Unknown Host priority control %d\n", val); 1528 } 1529 1530 DP_NOTICE(p_hwfn, 1531 "UFP shmem config: mode = %d tc = %d pri_type = %d\n", 1532 p_hwfn->ufp_info.mode, 1533 p_hwfn->ufp_info.tc, p_hwfn->ufp_info.pri_type); 1534 } 1535 1536 static int 1537 qed_mcp_handle_ufp_event(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1538 { 1539 qed_mcp_read_ufp_config(p_hwfn, p_ptt); 1540 1541 if (p_hwfn->ufp_info.mode == QED_UFP_MODE_VNIC_BW) { 1542 p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc; 1543 p_hwfn->hw_info.offload_tc = p_hwfn->ufp_info.tc; 1544 1545 qed_qm_reconf(p_hwfn, p_ptt); 1546 } else if (p_hwfn->ufp_info.mode == QED_UFP_MODE_ETS) { 1547 /* Merge UFP TC with the dcbx TC data */ 1548 qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1549 QED_DCBX_OPERATIONAL_MIB); 1550 } else { 1551 DP_ERR(p_hwfn, "Invalid sched type, discard the UFP config\n"); 1552 return -EINVAL; 1553 } 1554 1555 /* update storm FW with negotiation results */ 1556 qed_sp_pf_update_ufp(p_hwfn); 1557 1558 /* update stag pcp value */ 1559 qed_sp_pf_update_stag(p_hwfn); 1560 1561 return 0; 1562 } 1563 1564 int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 1565 struct qed_ptt *p_ptt) 1566 { 1567 struct qed_mcp_info *info = p_hwfn->mcp_info; 1568 int rc = 0; 1569 bool found = false; 1570 u16 i; 1571 1572 DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n"); 1573 1574 /* Read Messages from MFW */ 1575 qed_mcp_read_mb(p_hwfn, p_ptt); 1576 1577 /* Compare current messages to old ones */ 1578 for (i = 0; i < info->mfw_mb_length; i++) { 1579 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i]) 1580 continue; 1581 1582 found = true; 1583 1584 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1585 "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n", 1586 i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]); 1587 1588 switch (i) { 1589 case MFW_DRV_MSG_LINK_CHANGE: 1590 qed_mcp_handle_link_change(p_hwfn, p_ptt, false); 1591 break; 1592 case MFW_DRV_MSG_VF_DISABLED: 1593 qed_mcp_handle_vf_flr(p_hwfn, p_ptt); 1594 break; 1595 case MFW_DRV_MSG_LLDP_DATA_UPDATED: 1596 qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1597 QED_DCBX_REMOTE_LLDP_MIB); 1598 break; 1599 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED: 1600 qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1601 QED_DCBX_REMOTE_MIB); 1602 break; 1603 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED: 1604 qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1605 QED_DCBX_OPERATIONAL_MIB); 1606 break; 1607 case MFW_DRV_MSG_OEM_CFG_UPDATE: 1608 qed_mcp_handle_ufp_event(p_hwfn, p_ptt); 1609 break; 1610 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE: 1611 qed_mcp_handle_transceiver_change(p_hwfn, p_ptt); 1612 break; 1613 case MFW_DRV_MSG_GET_LAN_STATS: 1614 case MFW_DRV_MSG_GET_FCOE_STATS: 1615 case MFW_DRV_MSG_GET_ISCSI_STATS: 1616 case MFW_DRV_MSG_GET_RDMA_STATS: 1617 qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i); 1618 break; 1619 case MFW_DRV_MSG_BW_UPDATE: 1620 qed_mcp_update_bw(p_hwfn, p_ptt); 1621 break; 1622 case MFW_DRV_MSG_S_TAG_UPDATE: 1623 qed_mcp_update_stag(p_hwfn, p_ptt); 1624 break; 1625 break; 1626 default: 1627 DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i); 1628 rc = -EINVAL; 1629 } 1630 } 1631 1632 /* ACK everything */ 1633 for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) { 1634 __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); 1635 1636 /* MFW expect answer in BE, so we force write in that format */ 1637 qed_wr(p_hwfn, p_ptt, 1638 info->mfw_mb_addr + sizeof(u32) + 1639 MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) * 1640 sizeof(u32) + i * sizeof(u32), 1641 (__force u32)val); 1642 } 1643 1644 if (!found) { 1645 DP_NOTICE(p_hwfn, 1646 "Received an MFW message indication but no new message!\n"); 1647 rc = -EINVAL; 1648 } 1649 1650 /* Copy the new mfw messages into the shadow */ 1651 memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length); 1652 1653 return rc; 1654 } 1655 1656 int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 1657 struct qed_ptt *p_ptt, 1658 u32 *p_mfw_ver, u32 *p_running_bundle_id) 1659 { 1660 u32 global_offsize; 1661 1662 if (IS_VF(p_hwfn->cdev)) { 1663 if (p_hwfn->vf_iov_info) { 1664 struct pfvf_acquire_resp_tlv *p_resp; 1665 1666 p_resp = &p_hwfn->vf_iov_info->acquire_resp; 1667 *p_mfw_ver = p_resp->pfdev_info.mfw_ver; 1668 return 0; 1669 } else { 1670 DP_VERBOSE(p_hwfn, 1671 QED_MSG_IOV, 1672 "VF requested MFW version prior to ACQUIRE\n"); 1673 return -EINVAL; 1674 } 1675 } 1676 1677 global_offsize = qed_rd(p_hwfn, p_ptt, 1678 SECTION_OFFSIZE_ADDR(p_hwfn-> 1679 mcp_info->public_base, 1680 PUBLIC_GLOBAL)); 1681 *p_mfw_ver = 1682 qed_rd(p_hwfn, p_ptt, 1683 SECTION_ADDR(global_offsize, 1684 0) + offsetof(struct public_global, mfw_ver)); 1685 1686 if (p_running_bundle_id != NULL) { 1687 *p_running_bundle_id = qed_rd(p_hwfn, p_ptt, 1688 SECTION_ADDR(global_offsize, 0) + 1689 offsetof(struct public_global, 1690 running_bundle_id)); 1691 } 1692 1693 return 0; 1694 } 1695 1696 int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn, 1697 struct qed_ptt *p_ptt, u32 *p_mbi_ver) 1698 { 1699 u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr; 1700 1701 if (IS_VF(p_hwfn->cdev)) 1702 return -EINVAL; 1703 1704 /* Read the address of the nvm_cfg */ 1705 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 1706 if (!nvm_cfg_addr) { 1707 DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 1708 return -EINVAL; 1709 } 1710 1711 /* Read the offset of nvm_cfg1 */ 1712 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 1713 1714 mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1715 offsetof(struct nvm_cfg1, glob) + 1716 offsetof(struct nvm_cfg1_glob, mbi_version); 1717 *p_mbi_ver = qed_rd(p_hwfn, p_ptt, 1718 mbi_ver_addr) & 1719 (NVM_CFG1_GLOB_MBI_VERSION_0_MASK | 1720 NVM_CFG1_GLOB_MBI_VERSION_1_MASK | 1721 NVM_CFG1_GLOB_MBI_VERSION_2_MASK); 1722 1723 return 0; 1724 } 1725 1726 int qed_mcp_get_media_type(struct qed_dev *cdev, u32 *p_media_type) 1727 { 1728 struct qed_hwfn *p_hwfn = &cdev->hwfns[0]; 1729 struct qed_ptt *p_ptt; 1730 1731 if (IS_VF(cdev)) 1732 return -EINVAL; 1733 1734 if (!qed_mcp_is_init(p_hwfn)) { 1735 DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 1736 return -EBUSY; 1737 } 1738 1739 *p_media_type = MEDIA_UNSPECIFIED; 1740 1741 p_ptt = qed_ptt_acquire(p_hwfn); 1742 if (!p_ptt) 1743 return -EBUSY; 1744 1745 *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1746 offsetof(struct public_port, media_type)); 1747 1748 qed_ptt_release(p_hwfn, p_ptt); 1749 1750 return 0; 1751 } 1752 1753 /* Old MFW has a global configuration for all PFs regarding RDMA support */ 1754 static void 1755 qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn, 1756 enum qed_pci_personality *p_proto) 1757 { 1758 /* There wasn't ever a legacy MFW that published iwarp. 1759 * So at this point, this is either plain l2 or RoCE. 1760 */ 1761 if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities)) 1762 *p_proto = QED_PCI_ETH_ROCE; 1763 else 1764 *p_proto = QED_PCI_ETH; 1765 1766 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 1767 "According to Legacy capabilities, L2 personality is %08x\n", 1768 (u32) *p_proto); 1769 } 1770 1771 static int 1772 qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn, 1773 struct qed_ptt *p_ptt, 1774 enum qed_pci_personality *p_proto) 1775 { 1776 u32 resp = 0, param = 0; 1777 int rc; 1778 1779 rc = qed_mcp_cmd(p_hwfn, p_ptt, 1780 DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, ¶m); 1781 if (rc) 1782 return rc; 1783 if (resp != FW_MSG_CODE_OK) { 1784 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 1785 "MFW lacks support for command; Returns %08x\n", 1786 resp); 1787 return -EINVAL; 1788 } 1789 1790 switch (param) { 1791 case FW_MB_PARAM_GET_PF_RDMA_NONE: 1792 *p_proto = QED_PCI_ETH; 1793 break; 1794 case FW_MB_PARAM_GET_PF_RDMA_ROCE: 1795 *p_proto = QED_PCI_ETH_ROCE; 1796 break; 1797 case FW_MB_PARAM_GET_PF_RDMA_IWARP: 1798 *p_proto = QED_PCI_ETH_IWARP; 1799 break; 1800 case FW_MB_PARAM_GET_PF_RDMA_BOTH: 1801 *p_proto = QED_PCI_ETH_RDMA; 1802 break; 1803 default: 1804 DP_NOTICE(p_hwfn, 1805 "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n", 1806 param); 1807 return -EINVAL; 1808 } 1809 1810 DP_VERBOSE(p_hwfn, 1811 NETIF_MSG_IFUP, 1812 "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n", 1813 (u32) *p_proto, resp, param); 1814 return 0; 1815 } 1816 1817 static int 1818 qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn, 1819 struct public_func *p_info, 1820 struct qed_ptt *p_ptt, 1821 enum qed_pci_personality *p_proto) 1822 { 1823 int rc = 0; 1824 1825 switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) { 1826 case FUNC_MF_CFG_PROTOCOL_ETHERNET: 1827 if (!IS_ENABLED(CONFIG_QED_RDMA)) 1828 *p_proto = QED_PCI_ETH; 1829 else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto)) 1830 qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto); 1831 break; 1832 case FUNC_MF_CFG_PROTOCOL_ISCSI: 1833 *p_proto = QED_PCI_ISCSI; 1834 break; 1835 case FUNC_MF_CFG_PROTOCOL_FCOE: 1836 *p_proto = QED_PCI_FCOE; 1837 break; 1838 case FUNC_MF_CFG_PROTOCOL_ROCE: 1839 DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n"); 1840 /* Fallthrough */ 1841 default: 1842 rc = -EINVAL; 1843 } 1844 1845 return rc; 1846 } 1847 1848 int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 1849 struct qed_ptt *p_ptt) 1850 { 1851 struct qed_mcp_function_info *info; 1852 struct public_func shmem_info; 1853 1854 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1855 info = &p_hwfn->mcp_info->func_info; 1856 1857 info->pause_on_host = (shmem_info.config & 1858 FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0; 1859 1860 if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt, 1861 &info->protocol)) { 1862 DP_ERR(p_hwfn, "Unknown personality %08x\n", 1863 (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK)); 1864 return -EINVAL; 1865 } 1866 1867 qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1868 1869 if (shmem_info.mac_upper || shmem_info.mac_lower) { 1870 info->mac[0] = (u8)(shmem_info.mac_upper >> 8); 1871 info->mac[1] = (u8)(shmem_info.mac_upper); 1872 info->mac[2] = (u8)(shmem_info.mac_lower >> 24); 1873 info->mac[3] = (u8)(shmem_info.mac_lower >> 16); 1874 info->mac[4] = (u8)(shmem_info.mac_lower >> 8); 1875 info->mac[5] = (u8)(shmem_info.mac_lower); 1876 1877 /* Store primary MAC for later possible WoL */ 1878 memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN); 1879 } else { 1880 DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n"); 1881 } 1882 1883 info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower | 1884 (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32); 1885 info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower | 1886 (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32); 1887 1888 info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK); 1889 1890 info->mtu = (u16)shmem_info.mtu_size; 1891 1892 p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE; 1893 p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT; 1894 if (qed_mcp_is_init(p_hwfn)) { 1895 u32 resp = 0, param = 0; 1896 int rc; 1897 1898 rc = qed_mcp_cmd(p_hwfn, p_ptt, 1899 DRV_MSG_CODE_OS_WOL, 0, &resp, ¶m); 1900 if (rc) 1901 return rc; 1902 if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED) 1903 p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME; 1904 } 1905 1906 DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP), 1907 "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n", 1908 info->pause_on_host, info->protocol, 1909 info->bandwidth_min, info->bandwidth_max, 1910 info->mac[0], info->mac[1], info->mac[2], 1911 info->mac[3], info->mac[4], info->mac[5], 1912 info->wwn_port, info->wwn_node, 1913 info->ovlan, (u8)p_hwfn->hw_info.b_wol_support); 1914 1915 return 0; 1916 } 1917 1918 struct qed_mcp_link_params 1919 *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn) 1920 { 1921 if (!p_hwfn || !p_hwfn->mcp_info) 1922 return NULL; 1923 return &p_hwfn->mcp_info->link_input; 1924 } 1925 1926 struct qed_mcp_link_state 1927 *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn) 1928 { 1929 if (!p_hwfn || !p_hwfn->mcp_info) 1930 return NULL; 1931 return &p_hwfn->mcp_info->link_output; 1932 } 1933 1934 struct qed_mcp_link_capabilities 1935 *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn) 1936 { 1937 if (!p_hwfn || !p_hwfn->mcp_info) 1938 return NULL; 1939 return &p_hwfn->mcp_info->link_capabilities; 1940 } 1941 1942 int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1943 { 1944 u32 resp = 0, param = 0; 1945 int rc; 1946 1947 rc = qed_mcp_cmd(p_hwfn, p_ptt, 1948 DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m); 1949 1950 /* Wait for the drain to complete before returning */ 1951 msleep(1020); 1952 1953 return rc; 1954 } 1955 1956 int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 1957 struct qed_ptt *p_ptt, u32 *p_flash_size) 1958 { 1959 u32 flash_size; 1960 1961 if (IS_VF(p_hwfn->cdev)) 1962 return -EINVAL; 1963 1964 flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4); 1965 flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >> 1966 MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT; 1967 flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT)); 1968 1969 *p_flash_size = flash_size; 1970 1971 return 0; 1972 } 1973 1974 static int 1975 qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn, 1976 struct qed_ptt *p_ptt, u8 vf_id, u8 num) 1977 { 1978 u32 resp = 0, param = 0, rc_param = 0; 1979 int rc; 1980 1981 /* Only Leader can configure MSIX, and need to take CMT into account */ 1982 if (!IS_LEAD_HWFN(p_hwfn)) 1983 return 0; 1984 num *= p_hwfn->cdev->num_hwfns; 1985 1986 param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) & 1987 DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK; 1988 param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) & 1989 DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK; 1990 1991 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param, 1992 &resp, &rc_param); 1993 1994 if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) { 1995 DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id); 1996 rc = -EINVAL; 1997 } else { 1998 DP_VERBOSE(p_hwfn, QED_MSG_IOV, 1999 "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n", 2000 num, vf_id); 2001 } 2002 2003 return rc; 2004 } 2005 2006 static int 2007 qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn, 2008 struct qed_ptt *p_ptt, u8 num) 2009 { 2010 u32 resp = 0, param = num, rc_param = 0; 2011 int rc; 2012 2013 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX, 2014 param, &resp, &rc_param); 2015 2016 if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) { 2017 DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n"); 2018 rc = -EINVAL; 2019 } else { 2020 DP_VERBOSE(p_hwfn, QED_MSG_IOV, 2021 "Requested 0x%02x MSI-x interrupts for VFs\n", num); 2022 } 2023 2024 return rc; 2025 } 2026 2027 int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 2028 struct qed_ptt *p_ptt, u8 vf_id, u8 num) 2029 { 2030 if (QED_IS_BB(p_hwfn->cdev)) 2031 return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num); 2032 else 2033 return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num); 2034 } 2035 2036 int 2037 qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 2038 struct qed_ptt *p_ptt, 2039 struct qed_mcp_drv_version *p_ver) 2040 { 2041 struct qed_mcp_mb_params mb_params; 2042 struct drv_version_stc drv_version; 2043 __be32 val; 2044 u32 i; 2045 int rc; 2046 2047 memset(&drv_version, 0, sizeof(drv_version)); 2048 drv_version.version = p_ver->version; 2049 for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) { 2050 val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)])); 2051 *(__be32 *)&drv_version.name[i * sizeof(u32)] = val; 2052 } 2053 2054 memset(&mb_params, 0, sizeof(mb_params)); 2055 mb_params.cmd = DRV_MSG_CODE_SET_VERSION; 2056 mb_params.p_data_src = &drv_version; 2057 mb_params.data_src_size = sizeof(drv_version); 2058 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 2059 if (rc) 2060 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 2061 2062 return rc; 2063 } 2064 2065 int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2066 { 2067 u32 resp = 0, param = 0; 2068 int rc; 2069 2070 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp, 2071 ¶m); 2072 if (rc) 2073 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 2074 2075 return rc; 2076 } 2077 2078 int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2079 { 2080 u32 value, cpu_mode; 2081 2082 qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff); 2083 2084 value = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 2085 value &= ~MCP_REG_CPU_MODE_SOFT_HALT; 2086 qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value); 2087 cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 2088 2089 return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -EAGAIN : 0; 2090 } 2091 2092 int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 2093 struct qed_ptt *p_ptt, 2094 enum qed_ov_client client) 2095 { 2096 u32 resp = 0, param = 0; 2097 u32 drv_mb_param; 2098 int rc; 2099 2100 switch (client) { 2101 case QED_OV_CLIENT_DRV: 2102 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS; 2103 break; 2104 case QED_OV_CLIENT_USER: 2105 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER; 2106 break; 2107 case QED_OV_CLIENT_VENDOR_SPEC: 2108 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC; 2109 break; 2110 default: 2111 DP_NOTICE(p_hwfn, "Invalid client type %d\n", client); 2112 return -EINVAL; 2113 } 2114 2115 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG, 2116 drv_mb_param, &resp, ¶m); 2117 if (rc) 2118 DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 2119 2120 return rc; 2121 } 2122 2123 int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 2124 struct qed_ptt *p_ptt, 2125 enum qed_ov_driver_state drv_state) 2126 { 2127 u32 resp = 0, param = 0; 2128 u32 drv_mb_param; 2129 int rc; 2130 2131 switch (drv_state) { 2132 case QED_OV_DRIVER_STATE_NOT_LOADED: 2133 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED; 2134 break; 2135 case QED_OV_DRIVER_STATE_DISABLED: 2136 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED; 2137 break; 2138 case QED_OV_DRIVER_STATE_ACTIVE: 2139 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE; 2140 break; 2141 default: 2142 DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state); 2143 return -EINVAL; 2144 } 2145 2146 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE, 2147 drv_mb_param, &resp, ¶m); 2148 if (rc) 2149 DP_ERR(p_hwfn, "Failed to send driver state\n"); 2150 2151 return rc; 2152 } 2153 2154 int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 2155 struct qed_ptt *p_ptt, u16 mtu) 2156 { 2157 u32 resp = 0, param = 0; 2158 u32 drv_mb_param; 2159 int rc; 2160 2161 drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT; 2162 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU, 2163 drv_mb_param, &resp, ¶m); 2164 if (rc) 2165 DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc); 2166 2167 return rc; 2168 } 2169 2170 int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 2171 struct qed_ptt *p_ptt, u8 *mac) 2172 { 2173 struct qed_mcp_mb_params mb_params; 2174 u32 mfw_mac[2]; 2175 int rc; 2176 2177 memset(&mb_params, 0, sizeof(mb_params)); 2178 mb_params.cmd = DRV_MSG_CODE_SET_VMAC; 2179 mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC << 2180 DRV_MSG_CODE_VMAC_TYPE_SHIFT; 2181 mb_params.param |= MCP_PF_ID(p_hwfn); 2182 2183 /* MCP is BE, and on LE platforms PCI would swap access to SHMEM 2184 * in 32-bit granularity. 2185 * So the MAC has to be set in native order [and not byte order], 2186 * otherwise it would be read incorrectly by MFW after swap. 2187 */ 2188 mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3]; 2189 mfw_mac[1] = mac[4] << 24 | mac[5] << 16; 2190 2191 mb_params.p_data_src = (u8 *)mfw_mac; 2192 mb_params.data_src_size = 8; 2193 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 2194 if (rc) 2195 DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc); 2196 2197 /* Store primary MAC for later possible WoL */ 2198 memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN); 2199 2200 return rc; 2201 } 2202 2203 int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 2204 struct qed_ptt *p_ptt, enum qed_ov_wol wol) 2205 { 2206 u32 resp = 0, param = 0; 2207 u32 drv_mb_param; 2208 int rc; 2209 2210 if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) { 2211 DP_VERBOSE(p_hwfn, QED_MSG_SP, 2212 "Can't change WoL configuration when WoL isn't supported\n"); 2213 return -EINVAL; 2214 } 2215 2216 switch (wol) { 2217 case QED_OV_WOL_DEFAULT: 2218 drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT; 2219 break; 2220 case QED_OV_WOL_DISABLED: 2221 drv_mb_param = DRV_MB_PARAM_WOL_DISABLED; 2222 break; 2223 case QED_OV_WOL_ENABLED: 2224 drv_mb_param = DRV_MB_PARAM_WOL_ENABLED; 2225 break; 2226 default: 2227 DP_ERR(p_hwfn, "Invalid wol state %d\n", wol); 2228 return -EINVAL; 2229 } 2230 2231 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL, 2232 drv_mb_param, &resp, ¶m); 2233 if (rc) 2234 DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc); 2235 2236 /* Store the WoL update for a future unload */ 2237 p_hwfn->cdev->wol_config = (u8)wol; 2238 2239 return rc; 2240 } 2241 2242 int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 2243 struct qed_ptt *p_ptt, 2244 enum qed_ov_eswitch eswitch) 2245 { 2246 u32 resp = 0, param = 0; 2247 u32 drv_mb_param; 2248 int rc; 2249 2250 switch (eswitch) { 2251 case QED_OV_ESWITCH_NONE: 2252 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE; 2253 break; 2254 case QED_OV_ESWITCH_VEB: 2255 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB; 2256 break; 2257 case QED_OV_ESWITCH_VEPA: 2258 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA; 2259 break; 2260 default: 2261 DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch); 2262 return -EINVAL; 2263 } 2264 2265 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE, 2266 drv_mb_param, &resp, ¶m); 2267 if (rc) 2268 DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc); 2269 2270 return rc; 2271 } 2272 2273 int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 2274 struct qed_ptt *p_ptt, enum qed_led_mode mode) 2275 { 2276 u32 resp = 0, param = 0, drv_mb_param; 2277 int rc; 2278 2279 switch (mode) { 2280 case QED_LED_MODE_ON: 2281 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON; 2282 break; 2283 case QED_LED_MODE_OFF: 2284 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF; 2285 break; 2286 case QED_LED_MODE_RESTORE: 2287 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER; 2288 break; 2289 default: 2290 DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode); 2291 return -EINVAL; 2292 } 2293 2294 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE, 2295 drv_mb_param, &resp, ¶m); 2296 2297 return rc; 2298 } 2299 2300 int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 2301 struct qed_ptt *p_ptt, u32 mask_parities) 2302 { 2303 u32 resp = 0, param = 0; 2304 int rc; 2305 2306 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES, 2307 mask_parities, &resp, ¶m); 2308 2309 if (rc) { 2310 DP_ERR(p_hwfn, 2311 "MCP response failure for mask parities, aborting\n"); 2312 } else if (resp != FW_MSG_CODE_OK) { 2313 DP_ERR(p_hwfn, 2314 "MCP did not acknowledge mask parity request. Old MFW?\n"); 2315 rc = -EINVAL; 2316 } 2317 2318 return rc; 2319 } 2320 2321 int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len) 2322 { 2323 u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0; 2324 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2325 u32 resp = 0, resp_param = 0; 2326 struct qed_ptt *p_ptt; 2327 int rc = 0; 2328 2329 p_ptt = qed_ptt_acquire(p_hwfn); 2330 if (!p_ptt) 2331 return -EBUSY; 2332 2333 while (bytes_left > 0) { 2334 bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN); 2335 2336 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 2337 DRV_MSG_CODE_NVM_READ_NVRAM, 2338 addr + offset + 2339 (bytes_to_copy << 2340 DRV_MB_PARAM_NVM_LEN_OFFSET), 2341 &resp, &resp_param, 2342 &read_len, 2343 (u32 *)(p_buf + offset)); 2344 2345 if (rc || (resp != FW_MSG_CODE_NVM_OK)) { 2346 DP_NOTICE(cdev, "MCP command rc = %d\n", rc); 2347 break; 2348 } 2349 2350 /* This can be a lengthy process, and it's possible scheduler 2351 * isn't preemptable. Sleep a bit to prevent CPU hogging. 2352 */ 2353 if (bytes_left % 0x1000 < 2354 (bytes_left - read_len) % 0x1000) 2355 usleep_range(1000, 2000); 2356 2357 offset += read_len; 2358 bytes_left -= read_len; 2359 } 2360 2361 cdev->mcp_nvm_resp = resp; 2362 qed_ptt_release(p_hwfn, p_ptt); 2363 2364 return rc; 2365 } 2366 2367 int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf) 2368 { 2369 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2370 struct qed_ptt *p_ptt; 2371 2372 p_ptt = qed_ptt_acquire(p_hwfn); 2373 if (!p_ptt) 2374 return -EBUSY; 2375 2376 memcpy(p_buf, &cdev->mcp_nvm_resp, sizeof(cdev->mcp_nvm_resp)); 2377 qed_ptt_release(p_hwfn, p_ptt); 2378 2379 return 0; 2380 } 2381 2382 int qed_mcp_nvm_put_file_begin(struct qed_dev *cdev, u32 addr) 2383 { 2384 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2385 struct qed_ptt *p_ptt; 2386 u32 resp, param; 2387 int rc; 2388 2389 p_ptt = qed_ptt_acquire(p_hwfn); 2390 if (!p_ptt) 2391 return -EBUSY; 2392 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr, 2393 &resp, ¶m); 2394 cdev->mcp_nvm_resp = resp; 2395 qed_ptt_release(p_hwfn, p_ptt); 2396 2397 return rc; 2398 } 2399 2400 int qed_mcp_nvm_write(struct qed_dev *cdev, 2401 u32 cmd, u32 addr, u8 *p_buf, u32 len) 2402 { 2403 u32 buf_idx = 0, buf_size, nvm_cmd, nvm_offset, resp = 0, param; 2404 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2405 struct qed_ptt *p_ptt; 2406 int rc = -EINVAL; 2407 2408 p_ptt = qed_ptt_acquire(p_hwfn); 2409 if (!p_ptt) 2410 return -EBUSY; 2411 2412 switch (cmd) { 2413 case QED_PUT_FILE_DATA: 2414 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA; 2415 break; 2416 case QED_NVM_WRITE_NVRAM: 2417 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM; 2418 break; 2419 default: 2420 DP_NOTICE(p_hwfn, "Invalid nvm write command 0x%x\n", cmd); 2421 rc = -EINVAL; 2422 goto out; 2423 } 2424 2425 while (buf_idx < len) { 2426 buf_size = min_t(u32, (len - buf_idx), MCP_DRV_NVM_BUF_LEN); 2427 nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) | 2428 addr) + buf_idx; 2429 rc = qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset, 2430 &resp, ¶m, buf_size, 2431 (u32 *)&p_buf[buf_idx]); 2432 if (rc) { 2433 DP_NOTICE(cdev, "nvm write failed, rc = %d\n", rc); 2434 resp = FW_MSG_CODE_ERROR; 2435 break; 2436 } 2437 2438 if (resp != FW_MSG_CODE_OK && 2439 resp != FW_MSG_CODE_NVM_OK && 2440 resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) { 2441 DP_NOTICE(cdev, 2442 "nvm write failed, resp = 0x%08x\n", resp); 2443 rc = -EINVAL; 2444 break; 2445 } 2446 2447 /* This can be a lengthy process, and it's possible scheduler 2448 * isn't pre-emptable. Sleep a bit to prevent CPU hogging. 2449 */ 2450 if (buf_idx % 0x1000 > (buf_idx + buf_size) % 0x1000) 2451 usleep_range(1000, 2000); 2452 2453 buf_idx += buf_size; 2454 } 2455 2456 cdev->mcp_nvm_resp = resp; 2457 out: 2458 qed_ptt_release(p_hwfn, p_ptt); 2459 2460 return rc; 2461 } 2462 2463 int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2464 { 2465 u32 drv_mb_param = 0, rsp, param; 2466 int rc = 0; 2467 2468 drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST << 2469 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 2470 2471 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 2472 drv_mb_param, &rsp, ¶m); 2473 2474 if (rc) 2475 return rc; 2476 2477 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 2478 (param != DRV_MB_PARAM_BIST_RC_PASSED)) 2479 rc = -EAGAIN; 2480 2481 return rc; 2482 } 2483 2484 int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2485 { 2486 u32 drv_mb_param, rsp, param; 2487 int rc = 0; 2488 2489 drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST << 2490 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 2491 2492 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 2493 drv_mb_param, &rsp, ¶m); 2494 2495 if (rc) 2496 return rc; 2497 2498 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 2499 (param != DRV_MB_PARAM_BIST_RC_PASSED)) 2500 rc = -EAGAIN; 2501 2502 return rc; 2503 } 2504 2505 int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn, 2506 struct qed_ptt *p_ptt, 2507 u32 *num_images) 2508 { 2509 u32 drv_mb_param = 0, rsp; 2510 int rc = 0; 2511 2512 drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES << 2513 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 2514 2515 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 2516 drv_mb_param, &rsp, num_images); 2517 if (rc) 2518 return rc; 2519 2520 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK)) 2521 rc = -EINVAL; 2522 2523 return rc; 2524 } 2525 2526 int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn, 2527 struct qed_ptt *p_ptt, 2528 struct bist_nvm_image_att *p_image_att, 2529 u32 image_index) 2530 { 2531 u32 buf_size = 0, param, resp = 0, resp_param = 0; 2532 int rc; 2533 2534 param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX << 2535 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT; 2536 param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT; 2537 2538 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 2539 DRV_MSG_CODE_BIST_TEST, param, 2540 &resp, &resp_param, 2541 &buf_size, 2542 (u32 *)p_image_att); 2543 if (rc) 2544 return rc; 2545 2546 if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 2547 (p_image_att->return_code != 1)) 2548 rc = -EINVAL; 2549 2550 return rc; 2551 } 2552 2553 int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn) 2554 { 2555 struct qed_nvm_image_info *nvm_info = &p_hwfn->nvm_info; 2556 struct qed_ptt *p_ptt; 2557 int rc; 2558 u32 i; 2559 2560 p_ptt = qed_ptt_acquire(p_hwfn); 2561 if (!p_ptt) { 2562 DP_ERR(p_hwfn, "failed to acquire ptt\n"); 2563 return -EBUSY; 2564 } 2565 2566 /* Acquire from MFW the amount of available images */ 2567 nvm_info->num_images = 0; 2568 rc = qed_mcp_bist_nvm_get_num_images(p_hwfn, 2569 p_ptt, &nvm_info->num_images); 2570 if (rc == -EOPNOTSUPP) { 2571 DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n"); 2572 goto out; 2573 } else if (rc || !nvm_info->num_images) { 2574 DP_ERR(p_hwfn, "Failed getting number of images\n"); 2575 goto err0; 2576 } 2577 2578 nvm_info->image_att = kmalloc(nvm_info->num_images * 2579 sizeof(struct bist_nvm_image_att), 2580 GFP_KERNEL); 2581 if (!nvm_info->image_att) { 2582 rc = -ENOMEM; 2583 goto err0; 2584 } 2585 2586 /* Iterate over images and get their attributes */ 2587 for (i = 0; i < nvm_info->num_images; i++) { 2588 rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt, 2589 &nvm_info->image_att[i], i); 2590 if (rc) { 2591 DP_ERR(p_hwfn, 2592 "Failed getting image index %d attributes\n", i); 2593 goto err1; 2594 } 2595 2596 DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n", i, 2597 nvm_info->image_att[i].len); 2598 } 2599 out: 2600 qed_ptt_release(p_hwfn, p_ptt); 2601 return 0; 2602 2603 err1: 2604 kfree(nvm_info->image_att); 2605 err0: 2606 qed_ptt_release(p_hwfn, p_ptt); 2607 return rc; 2608 } 2609 2610 int 2611 qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn, 2612 enum qed_nvm_images image_id, 2613 struct qed_nvm_image_att *p_image_att) 2614 { 2615 enum nvm_image_type type; 2616 u32 i; 2617 2618 /* Translate image_id into MFW definitions */ 2619 switch (image_id) { 2620 case QED_NVM_IMAGE_ISCSI_CFG: 2621 type = NVM_TYPE_ISCSI_CFG; 2622 break; 2623 case QED_NVM_IMAGE_FCOE_CFG: 2624 type = NVM_TYPE_FCOE_CFG; 2625 break; 2626 case QED_NVM_IMAGE_NVM_CFG1: 2627 type = NVM_TYPE_NVM_CFG1; 2628 break; 2629 case QED_NVM_IMAGE_DEFAULT_CFG: 2630 type = NVM_TYPE_DEFAULT_CFG; 2631 break; 2632 case QED_NVM_IMAGE_NVM_META: 2633 type = NVM_TYPE_META; 2634 break; 2635 default: 2636 DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n", 2637 image_id); 2638 return -EINVAL; 2639 } 2640 2641 for (i = 0; i < p_hwfn->nvm_info.num_images; i++) 2642 if (type == p_hwfn->nvm_info.image_att[i].image_type) 2643 break; 2644 if (i == p_hwfn->nvm_info.num_images) { 2645 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 2646 "Failed to find nvram image of type %08x\n", 2647 image_id); 2648 return -ENOENT; 2649 } 2650 2651 p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr; 2652 p_image_att->length = p_hwfn->nvm_info.image_att[i].len; 2653 2654 return 0; 2655 } 2656 2657 int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn, 2658 enum qed_nvm_images image_id, 2659 u8 *p_buffer, u32 buffer_len) 2660 { 2661 struct qed_nvm_image_att image_att; 2662 int rc; 2663 2664 memset(p_buffer, 0, buffer_len); 2665 2666 rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att); 2667 if (rc) 2668 return rc; 2669 2670 /* Validate sizes - both the image's and the supplied buffer's */ 2671 if (image_att.length <= 4) { 2672 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 2673 "Image [%d] is too small - only %d bytes\n", 2674 image_id, image_att.length); 2675 return -EINVAL; 2676 } 2677 2678 if (image_att.length > buffer_len) { 2679 DP_VERBOSE(p_hwfn, 2680 QED_MSG_STORAGE, 2681 "Image [%d] is too big - %08x bytes where only %08x are available\n", 2682 image_id, image_att.length, buffer_len); 2683 return -ENOMEM; 2684 } 2685 2686 return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr, 2687 p_buffer, image_att.length); 2688 } 2689 2690 static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id) 2691 { 2692 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID; 2693 2694 switch (res_id) { 2695 case QED_SB: 2696 mfw_res_id = RESOURCE_NUM_SB_E; 2697 break; 2698 case QED_L2_QUEUE: 2699 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E; 2700 break; 2701 case QED_VPORT: 2702 mfw_res_id = RESOURCE_NUM_VPORT_E; 2703 break; 2704 case QED_RSS_ENG: 2705 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E; 2706 break; 2707 case QED_PQ: 2708 mfw_res_id = RESOURCE_NUM_PQ_E; 2709 break; 2710 case QED_RL: 2711 mfw_res_id = RESOURCE_NUM_RL_E; 2712 break; 2713 case QED_MAC: 2714 case QED_VLAN: 2715 /* Each VFC resource can accommodate both a MAC and a VLAN */ 2716 mfw_res_id = RESOURCE_VFC_FILTER_E; 2717 break; 2718 case QED_ILT: 2719 mfw_res_id = RESOURCE_ILT_E; 2720 break; 2721 case QED_LL2_QUEUE: 2722 mfw_res_id = RESOURCE_LL2_QUEUE_E; 2723 break; 2724 case QED_RDMA_CNQ_RAM: 2725 case QED_CMDQS_CQS: 2726 /* CNQ/CMDQS are the same resource */ 2727 mfw_res_id = RESOURCE_CQS_E; 2728 break; 2729 case QED_RDMA_STATS_QUEUE: 2730 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E; 2731 break; 2732 case QED_BDQ: 2733 mfw_res_id = RESOURCE_BDQ_E; 2734 break; 2735 default: 2736 break; 2737 } 2738 2739 return mfw_res_id; 2740 } 2741 2742 #define QED_RESC_ALLOC_VERSION_MAJOR 2 2743 #define QED_RESC_ALLOC_VERSION_MINOR 0 2744 #define QED_RESC_ALLOC_VERSION \ 2745 ((QED_RESC_ALLOC_VERSION_MAJOR << \ 2746 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \ 2747 (QED_RESC_ALLOC_VERSION_MINOR << \ 2748 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT)) 2749 2750 struct qed_resc_alloc_in_params { 2751 u32 cmd; 2752 enum qed_resources res_id; 2753 u32 resc_max_val; 2754 }; 2755 2756 struct qed_resc_alloc_out_params { 2757 u32 mcp_resp; 2758 u32 mcp_param; 2759 u32 resc_num; 2760 u32 resc_start; 2761 u32 vf_resc_num; 2762 u32 vf_resc_start; 2763 u32 flags; 2764 }; 2765 2766 static int 2767 qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn, 2768 struct qed_ptt *p_ptt, 2769 struct qed_resc_alloc_in_params *p_in_params, 2770 struct qed_resc_alloc_out_params *p_out_params) 2771 { 2772 struct qed_mcp_mb_params mb_params; 2773 struct resource_info mfw_resc_info; 2774 int rc; 2775 2776 memset(&mfw_resc_info, 0, sizeof(mfw_resc_info)); 2777 2778 mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id); 2779 if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) { 2780 DP_ERR(p_hwfn, 2781 "Failed to match resource %d [%s] with the MFW resources\n", 2782 p_in_params->res_id, 2783 qed_hw_get_resc_name(p_in_params->res_id)); 2784 return -EINVAL; 2785 } 2786 2787 switch (p_in_params->cmd) { 2788 case DRV_MSG_SET_RESOURCE_VALUE_MSG: 2789 mfw_resc_info.size = p_in_params->resc_max_val; 2790 /* Fallthrough */ 2791 case DRV_MSG_GET_RESOURCE_ALLOC_MSG: 2792 break; 2793 default: 2794 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n", 2795 p_in_params->cmd); 2796 return -EINVAL; 2797 } 2798 2799 memset(&mb_params, 0, sizeof(mb_params)); 2800 mb_params.cmd = p_in_params->cmd; 2801 mb_params.param = QED_RESC_ALLOC_VERSION; 2802 mb_params.p_data_src = &mfw_resc_info; 2803 mb_params.data_src_size = sizeof(mfw_resc_info); 2804 mb_params.p_data_dst = mb_params.p_data_src; 2805 mb_params.data_dst_size = mb_params.data_src_size; 2806 2807 DP_VERBOSE(p_hwfn, 2808 QED_MSG_SP, 2809 "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n", 2810 p_in_params->cmd, 2811 p_in_params->res_id, 2812 qed_hw_get_resc_name(p_in_params->res_id), 2813 QED_MFW_GET_FIELD(mb_params.param, 2814 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 2815 QED_MFW_GET_FIELD(mb_params.param, 2816 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 2817 p_in_params->resc_max_val); 2818 2819 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 2820 if (rc) 2821 return rc; 2822 2823 p_out_params->mcp_resp = mb_params.mcp_resp; 2824 p_out_params->mcp_param = mb_params.mcp_param; 2825 p_out_params->resc_num = mfw_resc_info.size; 2826 p_out_params->resc_start = mfw_resc_info.offset; 2827 p_out_params->vf_resc_num = mfw_resc_info.vf_size; 2828 p_out_params->vf_resc_start = mfw_resc_info.vf_offset; 2829 p_out_params->flags = mfw_resc_info.flags; 2830 2831 DP_VERBOSE(p_hwfn, 2832 QED_MSG_SP, 2833 "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n", 2834 QED_MFW_GET_FIELD(p_out_params->mcp_param, 2835 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 2836 QED_MFW_GET_FIELD(p_out_params->mcp_param, 2837 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 2838 p_out_params->resc_num, 2839 p_out_params->resc_start, 2840 p_out_params->vf_resc_num, 2841 p_out_params->vf_resc_start, p_out_params->flags); 2842 2843 return 0; 2844 } 2845 2846 int 2847 qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn, 2848 struct qed_ptt *p_ptt, 2849 enum qed_resources res_id, 2850 u32 resc_max_val, u32 *p_mcp_resp) 2851 { 2852 struct qed_resc_alloc_out_params out_params; 2853 struct qed_resc_alloc_in_params in_params; 2854 int rc; 2855 2856 memset(&in_params, 0, sizeof(in_params)); 2857 in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG; 2858 in_params.res_id = res_id; 2859 in_params.resc_max_val = resc_max_val; 2860 memset(&out_params, 0, sizeof(out_params)); 2861 rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 2862 &out_params); 2863 if (rc) 2864 return rc; 2865 2866 *p_mcp_resp = out_params.mcp_resp; 2867 2868 return 0; 2869 } 2870 2871 int 2872 qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, 2873 struct qed_ptt *p_ptt, 2874 enum qed_resources res_id, 2875 u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start) 2876 { 2877 struct qed_resc_alloc_out_params out_params; 2878 struct qed_resc_alloc_in_params in_params; 2879 int rc; 2880 2881 memset(&in_params, 0, sizeof(in_params)); 2882 in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG; 2883 in_params.res_id = res_id; 2884 memset(&out_params, 0, sizeof(out_params)); 2885 rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 2886 &out_params); 2887 if (rc) 2888 return rc; 2889 2890 *p_mcp_resp = out_params.mcp_resp; 2891 2892 if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) { 2893 *p_resc_num = out_params.resc_num; 2894 *p_resc_start = out_params.resc_start; 2895 } 2896 2897 return 0; 2898 } 2899 2900 int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2901 { 2902 u32 mcp_resp, mcp_param; 2903 2904 return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0, 2905 &mcp_resp, &mcp_param); 2906 } 2907 2908 static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn, 2909 struct qed_ptt *p_ptt, 2910 u32 param, u32 *p_mcp_resp, u32 *p_mcp_param) 2911 { 2912 int rc; 2913 2914 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param, 2915 p_mcp_resp, p_mcp_param); 2916 if (rc) 2917 return rc; 2918 2919 if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 2920 DP_INFO(p_hwfn, 2921 "The resource command is unsupported by the MFW\n"); 2922 return -EINVAL; 2923 } 2924 2925 if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) { 2926 u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE); 2927 2928 DP_NOTICE(p_hwfn, 2929 "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n", 2930 param, opcode); 2931 return -EINVAL; 2932 } 2933 2934 return rc; 2935 } 2936 2937 int 2938 __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 2939 struct qed_ptt *p_ptt, 2940 struct qed_resc_lock_params *p_params) 2941 { 2942 u32 param = 0, mcp_resp, mcp_param; 2943 u8 opcode; 2944 int rc; 2945 2946 switch (p_params->timeout) { 2947 case QED_MCP_RESC_LOCK_TO_DEFAULT: 2948 opcode = RESOURCE_OPCODE_REQ; 2949 p_params->timeout = 0; 2950 break; 2951 case QED_MCP_RESC_LOCK_TO_NONE: 2952 opcode = RESOURCE_OPCODE_REQ_WO_AGING; 2953 p_params->timeout = 0; 2954 break; 2955 default: 2956 opcode = RESOURCE_OPCODE_REQ_W_AGING; 2957 break; 2958 } 2959 2960 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 2961 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 2962 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout); 2963 2964 DP_VERBOSE(p_hwfn, 2965 QED_MSG_SP, 2966 "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n", 2967 param, p_params->timeout, opcode, p_params->resource); 2968 2969 /* Attempt to acquire the resource */ 2970 rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 2971 if (rc) 2972 return rc; 2973 2974 /* Analyze the response */ 2975 p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER); 2976 opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 2977 2978 DP_VERBOSE(p_hwfn, 2979 QED_MSG_SP, 2980 "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n", 2981 mcp_param, opcode, p_params->owner); 2982 2983 switch (opcode) { 2984 case RESOURCE_OPCODE_GNT: 2985 p_params->b_granted = true; 2986 break; 2987 case RESOURCE_OPCODE_BUSY: 2988 p_params->b_granted = false; 2989 break; 2990 default: 2991 DP_NOTICE(p_hwfn, 2992 "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n", 2993 mcp_param, opcode); 2994 return -EINVAL; 2995 } 2996 2997 return 0; 2998 } 2999 3000 int 3001 qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 3002 struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params) 3003 { 3004 u32 retry_cnt = 0; 3005 int rc; 3006 3007 do { 3008 /* No need for an interval before the first iteration */ 3009 if (retry_cnt) { 3010 if (p_params->sleep_b4_retry) { 3011 u16 retry_interval_in_ms = 3012 DIV_ROUND_UP(p_params->retry_interval, 3013 1000); 3014 3015 msleep(retry_interval_in_ms); 3016 } else { 3017 udelay(p_params->retry_interval); 3018 } 3019 } 3020 3021 rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params); 3022 if (rc) 3023 return rc; 3024 3025 if (p_params->b_granted) 3026 break; 3027 } while (retry_cnt++ < p_params->retry_num); 3028 3029 return 0; 3030 } 3031 3032 int 3033 qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn, 3034 struct qed_ptt *p_ptt, 3035 struct qed_resc_unlock_params *p_params) 3036 { 3037 u32 param = 0, mcp_resp, mcp_param; 3038 u8 opcode; 3039 int rc; 3040 3041 opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE 3042 : RESOURCE_OPCODE_RELEASE; 3043 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 3044 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 3045 3046 DP_VERBOSE(p_hwfn, QED_MSG_SP, 3047 "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n", 3048 param, opcode, p_params->resource); 3049 3050 /* Attempt to release the resource */ 3051 rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 3052 if (rc) 3053 return rc; 3054 3055 /* Analyze the response */ 3056 opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 3057 3058 DP_VERBOSE(p_hwfn, QED_MSG_SP, 3059 "Resource unlock response: mcp_param 0x%08x [opcode %d]\n", 3060 mcp_param, opcode); 3061 3062 switch (opcode) { 3063 case RESOURCE_OPCODE_RELEASED_PREVIOUS: 3064 DP_INFO(p_hwfn, 3065 "Resource unlock request for an already released resource [%d]\n", 3066 p_params->resource); 3067 /* Fallthrough */ 3068 case RESOURCE_OPCODE_RELEASED: 3069 p_params->b_released = true; 3070 break; 3071 case RESOURCE_OPCODE_WRONG_OWNER: 3072 p_params->b_released = false; 3073 break; 3074 default: 3075 DP_NOTICE(p_hwfn, 3076 "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n", 3077 mcp_param, opcode); 3078 return -EINVAL; 3079 } 3080 3081 return 0; 3082 } 3083 3084 void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock, 3085 struct qed_resc_unlock_params *p_unlock, 3086 enum qed_resc_lock 3087 resource, bool b_is_permanent) 3088 { 3089 if (p_lock) { 3090 memset(p_lock, 0, sizeof(*p_lock)); 3091 3092 /* Permanent resources don't require aging, and there's no 3093 * point in trying to acquire them more than once since it's 3094 * unexpected another entity would release them. 3095 */ 3096 if (b_is_permanent) { 3097 p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE; 3098 } else { 3099 p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT; 3100 p_lock->retry_interval = 3101 QED_MCP_RESC_LOCK_RETRY_VAL_DFLT; 3102 p_lock->sleep_b4_retry = true; 3103 } 3104 3105 p_lock->resource = resource; 3106 } 3107 3108 if (p_unlock) { 3109 memset(p_unlock, 0, sizeof(*p_unlock)); 3110 p_unlock->resource = resource; 3111 } 3112 } 3113 3114 int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3115 { 3116 u32 mcp_resp; 3117 int rc; 3118 3119 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT, 3120 0, &mcp_resp, &p_hwfn->mcp_info->capabilities); 3121 if (!rc) 3122 DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE), 3123 "MFW supported features: %08x\n", 3124 p_hwfn->mcp_info->capabilities); 3125 3126 return rc; 3127 } 3128 3129 int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3130 { 3131 u32 mcp_resp, mcp_param, features; 3132 3133 features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE; 3134 3135 return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT, 3136 features, &mcp_resp, &mcp_param); 3137 } 3138