1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #include <linux/stddef.h> 10 #include <linux/pci.h> 11 #include <linux/kernel.h> 12 #include <linux/slab.h> 13 #include <linux/version.h> 14 #include <linux/delay.h> 15 #include <asm/byteorder.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/string.h> 18 #include <linux/module.h> 19 #include <linux/interrupt.h> 20 #include <linux/workqueue.h> 21 #include <linux/ethtool.h> 22 #include <linux/etherdevice.h> 23 #include <linux/vmalloc.h> 24 #include <linux/qed/qed_if.h> 25 #include <linux/qed/qed_ll2_if.h> 26 27 #include "qed.h" 28 #include "qed_sriov.h" 29 #include "qed_sp.h" 30 #include "qed_dev_api.h" 31 #include "qed_ll2.h" 32 #include "qed_mcp.h" 33 #include "qed_hw.h" 34 #include "qed_selftest.h" 35 36 #define QED_ROCE_QPS (8192) 37 #define QED_ROCE_DPIS (8) 38 39 static char version[] = 40 "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n"; 41 42 MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module"); 43 MODULE_LICENSE("GPL"); 44 MODULE_VERSION(DRV_MODULE_VERSION); 45 46 #define FW_FILE_VERSION \ 47 __stringify(FW_MAJOR_VERSION) "." \ 48 __stringify(FW_MINOR_VERSION) "." \ 49 __stringify(FW_REVISION_VERSION) "." \ 50 __stringify(FW_ENGINEERING_VERSION) 51 52 #define QED_FW_FILE_NAME \ 53 "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin" 54 55 MODULE_FIRMWARE(QED_FW_FILE_NAME); 56 57 static int __init qed_init(void) 58 { 59 pr_info("%s", version); 60 61 return 0; 62 } 63 64 static void __exit qed_cleanup(void) 65 { 66 pr_notice("qed_cleanup called\n"); 67 } 68 69 module_init(qed_init); 70 module_exit(qed_cleanup); 71 72 /* Check if the DMA controller on the machine can properly handle the DMA 73 * addressing required by the device. 74 */ 75 static int qed_set_coherency_mask(struct qed_dev *cdev) 76 { 77 struct device *dev = &cdev->pdev->dev; 78 79 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 80 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 81 DP_NOTICE(cdev, 82 "Can't request 64-bit consistent allocations\n"); 83 return -EIO; 84 } 85 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 86 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n"); 87 return -EIO; 88 } 89 90 return 0; 91 } 92 93 static void qed_free_pci(struct qed_dev *cdev) 94 { 95 struct pci_dev *pdev = cdev->pdev; 96 97 if (cdev->doorbells) 98 iounmap(cdev->doorbells); 99 if (cdev->regview) 100 iounmap(cdev->regview); 101 if (atomic_read(&pdev->enable_cnt) == 1) 102 pci_release_regions(pdev); 103 104 pci_disable_device(pdev); 105 } 106 107 #define PCI_REVISION_ID_ERROR_VAL 0xff 108 109 /* Performs PCI initializations as well as initializing PCI-related parameters 110 * in the device structrue. Returns 0 in case of success. 111 */ 112 static int qed_init_pci(struct qed_dev *cdev, struct pci_dev *pdev) 113 { 114 u8 rev_id; 115 int rc; 116 117 cdev->pdev = pdev; 118 119 rc = pci_enable_device(pdev); 120 if (rc) { 121 DP_NOTICE(cdev, "Cannot enable PCI device\n"); 122 goto err0; 123 } 124 125 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 126 DP_NOTICE(cdev, "No memory region found in bar #0\n"); 127 rc = -EIO; 128 goto err1; 129 } 130 131 if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 132 DP_NOTICE(cdev, "No memory region found in bar #2\n"); 133 rc = -EIO; 134 goto err1; 135 } 136 137 if (atomic_read(&pdev->enable_cnt) == 1) { 138 rc = pci_request_regions(pdev, "qed"); 139 if (rc) { 140 DP_NOTICE(cdev, 141 "Failed to request PCI memory resources\n"); 142 goto err1; 143 } 144 pci_set_master(pdev); 145 pci_save_state(pdev); 146 } 147 148 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); 149 if (rev_id == PCI_REVISION_ID_ERROR_VAL) { 150 DP_NOTICE(cdev, 151 "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n", 152 rev_id); 153 rc = -ENODEV; 154 goto err2; 155 } 156 if (!pci_is_pcie(pdev)) { 157 DP_NOTICE(cdev, "The bus is not PCI Express\n"); 158 rc = -EIO; 159 goto err2; 160 } 161 162 cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 163 if (IS_PF(cdev) && !cdev->pci_params.pm_cap) 164 DP_NOTICE(cdev, "Cannot find power management capability\n"); 165 166 rc = qed_set_coherency_mask(cdev); 167 if (rc) 168 goto err2; 169 170 cdev->pci_params.mem_start = pci_resource_start(pdev, 0); 171 cdev->pci_params.mem_end = pci_resource_end(pdev, 0); 172 cdev->pci_params.irq = pdev->irq; 173 174 cdev->regview = pci_ioremap_bar(pdev, 0); 175 if (!cdev->regview) { 176 DP_NOTICE(cdev, "Cannot map register space, aborting\n"); 177 rc = -ENOMEM; 178 goto err2; 179 } 180 181 if (IS_PF(cdev)) { 182 cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2); 183 cdev->db_size = pci_resource_len(cdev->pdev, 2); 184 cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size); 185 if (!cdev->doorbells) { 186 DP_NOTICE(cdev, "Cannot map doorbell space\n"); 187 return -ENOMEM; 188 } 189 } 190 191 return 0; 192 193 err2: 194 pci_release_regions(pdev); 195 err1: 196 pci_disable_device(pdev); 197 err0: 198 return rc; 199 } 200 201 int qed_fill_dev_info(struct qed_dev *cdev, 202 struct qed_dev_info *dev_info) 203 { 204 struct qed_ptt *ptt; 205 206 memset(dev_info, 0, sizeof(struct qed_dev_info)); 207 208 dev_info->num_hwfns = cdev->num_hwfns; 209 dev_info->pci_mem_start = cdev->pci_params.mem_start; 210 dev_info->pci_mem_end = cdev->pci_params.mem_end; 211 dev_info->pci_irq = cdev->pci_params.irq; 212 dev_info->rdma_supported = (cdev->hwfns[0].hw_info.personality == 213 QED_PCI_ETH_ROCE); 214 dev_info->is_mf_default = IS_MF_DEFAULT(&cdev->hwfns[0]); 215 ether_addr_copy(dev_info->hw_mac, cdev->hwfns[0].hw_info.hw_mac_addr); 216 217 if (IS_PF(cdev)) { 218 dev_info->fw_major = FW_MAJOR_VERSION; 219 dev_info->fw_minor = FW_MINOR_VERSION; 220 dev_info->fw_rev = FW_REVISION_VERSION; 221 dev_info->fw_eng = FW_ENGINEERING_VERSION; 222 dev_info->mf_mode = cdev->mf_mode; 223 dev_info->tx_switching = true; 224 225 if (QED_LEADING_HWFN(cdev)->hw_info.b_wol_support == 226 QED_WOL_SUPPORT_PME) 227 dev_info->wol_support = true; 228 } else { 229 qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major, 230 &dev_info->fw_minor, &dev_info->fw_rev, 231 &dev_info->fw_eng); 232 } 233 234 if (IS_PF(cdev)) { 235 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev)); 236 if (ptt) { 237 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt, 238 &dev_info->mfw_rev, NULL); 239 240 qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt, 241 &dev_info->flash_size); 242 243 qed_ptt_release(QED_LEADING_HWFN(cdev), ptt); 244 } 245 } else { 246 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL, 247 &dev_info->mfw_rev, NULL); 248 } 249 250 dev_info->mtu = QED_LEADING_HWFN(cdev)->hw_info.mtu; 251 252 return 0; 253 } 254 255 static void qed_free_cdev(struct qed_dev *cdev) 256 { 257 kfree((void *)cdev); 258 } 259 260 static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev) 261 { 262 struct qed_dev *cdev; 263 264 cdev = kzalloc(sizeof(*cdev), GFP_KERNEL); 265 if (!cdev) 266 return cdev; 267 268 qed_init_struct(cdev); 269 270 return cdev; 271 } 272 273 /* Sets the requested power state */ 274 static int qed_set_power_state(struct qed_dev *cdev, pci_power_t state) 275 { 276 if (!cdev) 277 return -ENODEV; 278 279 DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n"); 280 return 0; 281 } 282 283 /* probing */ 284 static struct qed_dev *qed_probe(struct pci_dev *pdev, 285 struct qed_probe_params *params) 286 { 287 struct qed_dev *cdev; 288 int rc; 289 290 cdev = qed_alloc_cdev(pdev); 291 if (!cdev) 292 goto err0; 293 294 cdev->protocol = params->protocol; 295 296 if (params->is_vf) 297 cdev->b_is_vf = true; 298 299 qed_init_dp(cdev, params->dp_module, params->dp_level); 300 301 rc = qed_init_pci(cdev, pdev); 302 if (rc) { 303 DP_ERR(cdev, "init pci failed\n"); 304 goto err1; 305 } 306 DP_INFO(cdev, "PCI init completed successfully\n"); 307 308 rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT); 309 if (rc) { 310 DP_ERR(cdev, "hw prepare failed\n"); 311 goto err2; 312 } 313 314 DP_INFO(cdev, "qed_probe completed successffuly\n"); 315 316 return cdev; 317 318 err2: 319 qed_free_pci(cdev); 320 err1: 321 qed_free_cdev(cdev); 322 err0: 323 return NULL; 324 } 325 326 static void qed_remove(struct qed_dev *cdev) 327 { 328 if (!cdev) 329 return; 330 331 qed_hw_remove(cdev); 332 333 qed_free_pci(cdev); 334 335 qed_set_power_state(cdev, PCI_D3hot); 336 337 qed_free_cdev(cdev); 338 } 339 340 static void qed_disable_msix(struct qed_dev *cdev) 341 { 342 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 343 pci_disable_msix(cdev->pdev); 344 kfree(cdev->int_params.msix_table); 345 } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) { 346 pci_disable_msi(cdev->pdev); 347 } 348 349 memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param)); 350 } 351 352 static int qed_enable_msix(struct qed_dev *cdev, 353 struct qed_int_params *int_params) 354 { 355 int i, rc, cnt; 356 357 cnt = int_params->in.num_vectors; 358 359 for (i = 0; i < cnt; i++) 360 int_params->msix_table[i].entry = i; 361 362 rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table, 363 int_params->in.min_msix_cnt, cnt); 364 if (rc < cnt && rc >= int_params->in.min_msix_cnt && 365 (rc % cdev->num_hwfns)) { 366 pci_disable_msix(cdev->pdev); 367 368 /* If fastpath is initialized, we need at least one interrupt 369 * per hwfn [and the slow path interrupts]. New requested number 370 * should be a multiple of the number of hwfns. 371 */ 372 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns; 373 DP_NOTICE(cdev, 374 "Trying to enable MSI-X with less vectors (%d out of %d)\n", 375 cnt, int_params->in.num_vectors); 376 rc = pci_enable_msix_exact(cdev->pdev, int_params->msix_table, 377 cnt); 378 if (!rc) 379 rc = cnt; 380 } 381 382 if (rc > 0) { 383 /* MSI-x configuration was achieved */ 384 int_params->out.int_mode = QED_INT_MODE_MSIX; 385 int_params->out.num_vectors = rc; 386 rc = 0; 387 } else { 388 DP_NOTICE(cdev, 389 "Failed to enable MSI-X [Requested %d vectors][rc %d]\n", 390 cnt, rc); 391 } 392 393 return rc; 394 } 395 396 /* This function outputs the int mode and the number of enabled msix vector */ 397 static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode) 398 { 399 struct qed_int_params *int_params = &cdev->int_params; 400 struct msix_entry *tbl; 401 int rc = 0, cnt; 402 403 switch (int_params->in.int_mode) { 404 case QED_INT_MODE_MSIX: 405 /* Allocate MSIX table */ 406 cnt = int_params->in.num_vectors; 407 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL); 408 if (!int_params->msix_table) { 409 rc = -ENOMEM; 410 goto out; 411 } 412 413 /* Enable MSIX */ 414 rc = qed_enable_msix(cdev, int_params); 415 if (!rc) 416 goto out; 417 418 DP_NOTICE(cdev, "Failed to enable MSI-X\n"); 419 kfree(int_params->msix_table); 420 if (force_mode) 421 goto out; 422 /* Fallthrough */ 423 424 case QED_INT_MODE_MSI: 425 if (cdev->num_hwfns == 1) { 426 rc = pci_enable_msi(cdev->pdev); 427 if (!rc) { 428 int_params->out.int_mode = QED_INT_MODE_MSI; 429 goto out; 430 } 431 432 DP_NOTICE(cdev, "Failed to enable MSI\n"); 433 if (force_mode) 434 goto out; 435 } 436 /* Fallthrough */ 437 438 case QED_INT_MODE_INTA: 439 int_params->out.int_mode = QED_INT_MODE_INTA; 440 rc = 0; 441 goto out; 442 default: 443 DP_NOTICE(cdev, "Unknown int_mode value %d\n", 444 int_params->in.int_mode); 445 rc = -EINVAL; 446 } 447 448 out: 449 if (!rc) 450 DP_INFO(cdev, "Using %s interrupts\n", 451 int_params->out.int_mode == QED_INT_MODE_INTA ? 452 "INTa" : int_params->out.int_mode == QED_INT_MODE_MSI ? 453 "MSI" : "MSIX"); 454 cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE; 455 456 return rc; 457 } 458 459 static void qed_simd_handler_config(struct qed_dev *cdev, void *token, 460 int index, void(*handler)(void *)) 461 { 462 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 463 int relative_idx = index / cdev->num_hwfns; 464 465 hwfn->simd_proto_handler[relative_idx].func = handler; 466 hwfn->simd_proto_handler[relative_idx].token = token; 467 } 468 469 static void qed_simd_handler_clean(struct qed_dev *cdev, int index) 470 { 471 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 472 int relative_idx = index / cdev->num_hwfns; 473 474 memset(&hwfn->simd_proto_handler[relative_idx], 0, 475 sizeof(struct qed_simd_fp_handler)); 476 } 477 478 static irqreturn_t qed_msix_sp_int(int irq, void *tasklet) 479 { 480 tasklet_schedule((struct tasklet_struct *)tasklet); 481 return IRQ_HANDLED; 482 } 483 484 static irqreturn_t qed_single_int(int irq, void *dev_instance) 485 { 486 struct qed_dev *cdev = (struct qed_dev *)dev_instance; 487 struct qed_hwfn *hwfn; 488 irqreturn_t rc = IRQ_NONE; 489 u64 status; 490 int i, j; 491 492 for (i = 0; i < cdev->num_hwfns; i++) { 493 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]); 494 495 if (!status) 496 continue; 497 498 hwfn = &cdev->hwfns[i]; 499 500 /* Slowpath interrupt */ 501 if (unlikely(status & 0x1)) { 502 tasklet_schedule(hwfn->sp_dpc); 503 status &= ~0x1; 504 rc = IRQ_HANDLED; 505 } 506 507 /* Fastpath interrupts */ 508 for (j = 0; j < 64; j++) { 509 if ((0x2ULL << j) & status) { 510 hwfn->simd_proto_handler[j].func( 511 hwfn->simd_proto_handler[j].token); 512 status &= ~(0x2ULL << j); 513 rc = IRQ_HANDLED; 514 } 515 } 516 517 if (unlikely(status)) 518 DP_VERBOSE(hwfn, NETIF_MSG_INTR, 519 "got an unknown interrupt status 0x%llx\n", 520 status); 521 } 522 523 return rc; 524 } 525 526 int qed_slowpath_irq_req(struct qed_hwfn *hwfn) 527 { 528 struct qed_dev *cdev = hwfn->cdev; 529 u32 int_mode; 530 int rc = 0; 531 u8 id; 532 533 int_mode = cdev->int_params.out.int_mode; 534 if (int_mode == QED_INT_MODE_MSIX) { 535 id = hwfn->my_id; 536 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x", 537 id, cdev->pdev->bus->number, 538 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id); 539 rc = request_irq(cdev->int_params.msix_table[id].vector, 540 qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc); 541 } else { 542 unsigned long flags = 0; 543 544 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x", 545 cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn), 546 PCI_FUNC(cdev->pdev->devfn)); 547 548 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA) 549 flags |= IRQF_SHARED; 550 551 rc = request_irq(cdev->pdev->irq, qed_single_int, 552 flags, cdev->name, cdev); 553 } 554 555 if (rc) 556 DP_NOTICE(cdev, "request_irq failed, rc = %d\n", rc); 557 else 558 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP), 559 "Requested slowpath %s\n", 560 (int_mode == QED_INT_MODE_MSIX) ? "MSI-X" : "IRQ"); 561 562 return rc; 563 } 564 565 static void qed_slowpath_irq_free(struct qed_dev *cdev) 566 { 567 int i; 568 569 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 570 for_each_hwfn(cdev, i) { 571 if (!cdev->hwfns[i].b_int_requested) 572 break; 573 synchronize_irq(cdev->int_params.msix_table[i].vector); 574 free_irq(cdev->int_params.msix_table[i].vector, 575 cdev->hwfns[i].sp_dpc); 576 } 577 } else { 578 if (QED_LEADING_HWFN(cdev)->b_int_requested) 579 free_irq(cdev->pdev->irq, cdev); 580 } 581 qed_int_disable_post_isr_release(cdev); 582 } 583 584 static int qed_nic_stop(struct qed_dev *cdev) 585 { 586 int i, rc; 587 588 rc = qed_hw_stop(cdev); 589 590 for (i = 0; i < cdev->num_hwfns; i++) { 591 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 592 593 if (p_hwfn->b_sp_dpc_enabled) { 594 tasklet_disable(p_hwfn->sp_dpc); 595 p_hwfn->b_sp_dpc_enabled = false; 596 DP_VERBOSE(cdev, NETIF_MSG_IFDOWN, 597 "Disabled sp taskelt [hwfn %d] at %p\n", 598 i, p_hwfn->sp_dpc); 599 } 600 } 601 602 qed_dbg_pf_exit(cdev); 603 604 return rc; 605 } 606 607 static int qed_nic_reset(struct qed_dev *cdev) 608 { 609 int rc; 610 611 rc = qed_hw_reset(cdev); 612 if (rc) 613 return rc; 614 615 qed_resc_free(cdev); 616 617 return 0; 618 } 619 620 static int qed_nic_setup(struct qed_dev *cdev) 621 { 622 int rc, i; 623 624 /* Determine if interface is going to require LL2 */ 625 if (QED_LEADING_HWFN(cdev)->hw_info.personality != QED_PCI_ETH) { 626 for (i = 0; i < cdev->num_hwfns; i++) { 627 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 628 629 p_hwfn->using_ll2 = true; 630 } 631 } 632 633 rc = qed_resc_alloc(cdev); 634 if (rc) 635 return rc; 636 637 DP_INFO(cdev, "Allocated qed resources\n"); 638 639 qed_resc_setup(cdev); 640 641 return rc; 642 } 643 644 static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt) 645 { 646 int limit = 0; 647 648 /* Mark the fastpath as free/used */ 649 cdev->int_params.fp_initialized = cnt ? true : false; 650 651 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) 652 limit = cdev->num_hwfns * 63; 653 else if (cdev->int_params.fp_msix_cnt) 654 limit = cdev->int_params.fp_msix_cnt; 655 656 if (!limit) 657 return -ENOMEM; 658 659 return min_t(int, cnt, limit); 660 } 661 662 static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info) 663 { 664 memset(info, 0, sizeof(struct qed_int_info)); 665 666 if (!cdev->int_params.fp_initialized) { 667 DP_INFO(cdev, 668 "Protocol driver requested interrupt information, but its support is not yet configured\n"); 669 return -EINVAL; 670 } 671 672 /* Need to expose only MSI-X information; Single IRQ is handled solely 673 * by qed. 674 */ 675 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 676 int msix_base = cdev->int_params.fp_msix_base; 677 678 info->msix_cnt = cdev->int_params.fp_msix_cnt; 679 info->msix = &cdev->int_params.msix_table[msix_base]; 680 } 681 682 return 0; 683 } 684 685 static int qed_slowpath_setup_int(struct qed_dev *cdev, 686 enum qed_int_mode int_mode) 687 { 688 struct qed_sb_cnt_info sb_cnt_info; 689 int num_l2_queues = 0; 690 int rc; 691 int i; 692 693 if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 694 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 695 return -EINVAL; 696 } 697 698 memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 699 cdev->int_params.in.int_mode = int_mode; 700 for_each_hwfn(cdev, i) { 701 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); 702 qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info); 703 cdev->int_params.in.num_vectors += sb_cnt_info.sb_cnt; 704 cdev->int_params.in.num_vectors++; /* slowpath */ 705 } 706 707 /* We want a minimum of one slowpath and one fastpath vector per hwfn */ 708 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2; 709 710 rc = qed_set_int_mode(cdev, false); 711 if (rc) { 712 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n"); 713 return rc; 714 } 715 716 cdev->int_params.fp_msix_base = cdev->num_hwfns; 717 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors - 718 cdev->num_hwfns; 719 720 if (!IS_ENABLED(CONFIG_QED_RDMA)) 721 return 0; 722 723 for_each_hwfn(cdev, i) 724 num_l2_queues += FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE); 725 726 DP_VERBOSE(cdev, QED_MSG_RDMA, 727 "cdev->int_params.fp_msix_cnt=%d num_l2_queues=%d\n", 728 cdev->int_params.fp_msix_cnt, num_l2_queues); 729 730 if (cdev->int_params.fp_msix_cnt > num_l2_queues) { 731 cdev->int_params.rdma_msix_cnt = 732 (cdev->int_params.fp_msix_cnt - num_l2_queues) 733 / cdev->num_hwfns; 734 cdev->int_params.rdma_msix_base = 735 cdev->int_params.fp_msix_base + num_l2_queues; 736 cdev->int_params.fp_msix_cnt = num_l2_queues; 737 } else { 738 cdev->int_params.rdma_msix_cnt = 0; 739 } 740 741 DP_VERBOSE(cdev, QED_MSG_RDMA, "roce_msix_cnt=%d roce_msix_base=%d\n", 742 cdev->int_params.rdma_msix_cnt, 743 cdev->int_params.rdma_msix_base); 744 745 return 0; 746 } 747 748 static int qed_slowpath_vf_setup_int(struct qed_dev *cdev) 749 { 750 int rc; 751 752 memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 753 cdev->int_params.in.int_mode = QED_INT_MODE_MSIX; 754 755 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), 756 &cdev->int_params.in.num_vectors); 757 if (cdev->num_hwfns > 1) { 758 u8 vectors = 0; 759 760 qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors); 761 cdev->int_params.in.num_vectors += vectors; 762 } 763 764 /* We want a minimum of one fastpath vector per vf hwfn */ 765 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns; 766 767 rc = qed_set_int_mode(cdev, true); 768 if (rc) 769 return rc; 770 771 cdev->int_params.fp_msix_base = 0; 772 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors; 773 774 return 0; 775 } 776 777 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len, 778 u8 *input_buf, u32 max_size, u8 *unzip_buf) 779 { 780 int rc; 781 782 p_hwfn->stream->next_in = input_buf; 783 p_hwfn->stream->avail_in = input_len; 784 p_hwfn->stream->next_out = unzip_buf; 785 p_hwfn->stream->avail_out = max_size; 786 787 rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS); 788 789 if (rc != Z_OK) { 790 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n", 791 rc); 792 return 0; 793 } 794 795 rc = zlib_inflate(p_hwfn->stream, Z_FINISH); 796 zlib_inflateEnd(p_hwfn->stream); 797 798 if (rc != Z_OK && rc != Z_STREAM_END) { 799 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n", 800 p_hwfn->stream->msg, rc); 801 return 0; 802 } 803 804 return p_hwfn->stream->total_out / 4; 805 } 806 807 static int qed_alloc_stream_mem(struct qed_dev *cdev) 808 { 809 int i; 810 void *workspace; 811 812 for_each_hwfn(cdev, i) { 813 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 814 815 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL); 816 if (!p_hwfn->stream) 817 return -ENOMEM; 818 819 workspace = vzalloc(zlib_inflate_workspacesize()); 820 if (!workspace) 821 return -ENOMEM; 822 p_hwfn->stream->workspace = workspace; 823 } 824 825 return 0; 826 } 827 828 static void qed_free_stream_mem(struct qed_dev *cdev) 829 { 830 int i; 831 832 for_each_hwfn(cdev, i) { 833 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 834 835 if (!p_hwfn->stream) 836 return; 837 838 vfree(p_hwfn->stream->workspace); 839 kfree(p_hwfn->stream); 840 } 841 } 842 843 static void qed_update_pf_params(struct qed_dev *cdev, 844 struct qed_pf_params *params) 845 { 846 int i; 847 848 if (IS_ENABLED(CONFIG_QED_RDMA)) { 849 params->rdma_pf_params.num_qps = QED_ROCE_QPS; 850 params->rdma_pf_params.min_dpis = QED_ROCE_DPIS; 851 /* divide by 3 the MRs to avoid MF ILT overflow */ 852 params->rdma_pf_params.num_mrs = RDMA_MAX_TIDS; 853 params->rdma_pf_params.gl_pi = QED_ROCE_PROTOCOL_INDEX; 854 } 855 856 for (i = 0; i < cdev->num_hwfns; i++) { 857 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 858 859 p_hwfn->pf_params = *params; 860 } 861 } 862 863 static int qed_slowpath_start(struct qed_dev *cdev, 864 struct qed_slowpath_params *params) 865 { 866 struct qed_tunn_start_params tunn_info; 867 struct qed_mcp_drv_version drv_version; 868 const u8 *data = NULL; 869 struct qed_hwfn *hwfn; 870 int rc = -EINVAL; 871 872 if (qed_iov_wq_start(cdev)) 873 goto err; 874 875 if (IS_PF(cdev)) { 876 rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME, 877 &cdev->pdev->dev); 878 if (rc) { 879 DP_NOTICE(cdev, 880 "Failed to find fw file - /lib/firmware/%s\n", 881 QED_FW_FILE_NAME); 882 goto err; 883 } 884 } 885 886 cdev->rx_coalesce_usecs = QED_DEFAULT_RX_USECS; 887 rc = qed_nic_setup(cdev); 888 if (rc) 889 goto err; 890 891 if (IS_PF(cdev)) 892 rc = qed_slowpath_setup_int(cdev, params->int_mode); 893 else 894 rc = qed_slowpath_vf_setup_int(cdev); 895 if (rc) 896 goto err1; 897 898 if (IS_PF(cdev)) { 899 /* Allocate stream for unzipping */ 900 rc = qed_alloc_stream_mem(cdev); 901 if (rc) 902 goto err2; 903 904 /* First Dword used to diffrentiate between various sources */ 905 data = cdev->firmware->data + sizeof(u32); 906 907 qed_dbg_pf_init(cdev); 908 } 909 910 memset(&tunn_info, 0, sizeof(tunn_info)); 911 tunn_info.tunn_mode |= 1 << QED_MODE_VXLAN_TUNN | 912 1 << QED_MODE_L2GRE_TUNN | 913 1 << QED_MODE_IPGRE_TUNN | 914 1 << QED_MODE_L2GENEVE_TUNN | 915 1 << QED_MODE_IPGENEVE_TUNN; 916 917 tunn_info.tunn_clss_vxlan = QED_TUNN_CLSS_MAC_VLAN; 918 tunn_info.tunn_clss_l2gre = QED_TUNN_CLSS_MAC_VLAN; 919 tunn_info.tunn_clss_ipgre = QED_TUNN_CLSS_MAC_VLAN; 920 921 /* Start the slowpath */ 922 rc = qed_hw_init(cdev, &tunn_info, true, 923 cdev->int_params.out.int_mode, 924 true, data); 925 if (rc) 926 goto err2; 927 928 DP_INFO(cdev, 929 "HW initialization and function start completed successfully\n"); 930 931 /* Allocate LL2 interface if needed */ 932 if (QED_LEADING_HWFN(cdev)->using_ll2) { 933 rc = qed_ll2_alloc_if(cdev); 934 if (rc) 935 goto err3; 936 } 937 if (IS_PF(cdev)) { 938 hwfn = QED_LEADING_HWFN(cdev); 939 drv_version.version = (params->drv_major << 24) | 940 (params->drv_minor << 16) | 941 (params->drv_rev << 8) | 942 (params->drv_eng); 943 strlcpy(drv_version.name, params->name, 944 MCP_DRV_VER_STR_SIZE - 4); 945 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt, 946 &drv_version); 947 if (rc) { 948 DP_NOTICE(cdev, "Failed sending drv version command\n"); 949 return rc; 950 } 951 } 952 953 qed_reset_vport_stats(cdev); 954 955 return 0; 956 957 err3: 958 qed_hw_stop(cdev); 959 err2: 960 qed_hw_timers_stop_all(cdev); 961 if (IS_PF(cdev)) 962 qed_slowpath_irq_free(cdev); 963 qed_free_stream_mem(cdev); 964 qed_disable_msix(cdev); 965 err1: 966 qed_resc_free(cdev); 967 err: 968 if (IS_PF(cdev)) 969 release_firmware(cdev->firmware); 970 971 qed_iov_wq_stop(cdev, false); 972 973 return rc; 974 } 975 976 static int qed_slowpath_stop(struct qed_dev *cdev) 977 { 978 if (!cdev) 979 return -ENODEV; 980 981 qed_ll2_dealloc_if(cdev); 982 983 if (IS_PF(cdev)) { 984 qed_free_stream_mem(cdev); 985 if (IS_QED_ETH_IF(cdev)) 986 qed_sriov_disable(cdev, true); 987 988 qed_nic_stop(cdev); 989 qed_slowpath_irq_free(cdev); 990 } 991 992 qed_disable_msix(cdev); 993 qed_nic_reset(cdev); 994 995 qed_iov_wq_stop(cdev, true); 996 997 if (IS_PF(cdev)) 998 release_firmware(cdev->firmware); 999 1000 return 0; 1001 } 1002 1003 static void qed_set_id(struct qed_dev *cdev, char name[NAME_SIZE], 1004 char ver_str[VER_SIZE]) 1005 { 1006 int i; 1007 1008 memcpy(cdev->name, name, NAME_SIZE); 1009 for_each_hwfn(cdev, i) 1010 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i); 1011 1012 memcpy(cdev->ver_str, ver_str, VER_SIZE); 1013 cdev->drv_type = DRV_ID_DRV_TYPE_LINUX; 1014 } 1015 1016 static u32 qed_sb_init(struct qed_dev *cdev, 1017 struct qed_sb_info *sb_info, 1018 void *sb_virt_addr, 1019 dma_addr_t sb_phy_addr, u16 sb_id, 1020 enum qed_sb_type type) 1021 { 1022 struct qed_hwfn *p_hwfn; 1023 int hwfn_index; 1024 u16 rel_sb_id; 1025 u8 n_hwfns; 1026 u32 rc; 1027 1028 /* RoCE uses single engine and CMT uses two engines. When using both 1029 * we force only a single engine. Storage uses only engine 0 too. 1030 */ 1031 if (type == QED_SB_TYPE_L2_QUEUE) 1032 n_hwfns = cdev->num_hwfns; 1033 else 1034 n_hwfns = 1; 1035 1036 hwfn_index = sb_id % n_hwfns; 1037 p_hwfn = &cdev->hwfns[hwfn_index]; 1038 rel_sb_id = sb_id / n_hwfns; 1039 1040 DP_VERBOSE(cdev, NETIF_MSG_INTR, 1041 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 1042 hwfn_index, rel_sb_id, sb_id); 1043 1044 rc = qed_int_sb_init(p_hwfn, p_hwfn->p_main_ptt, sb_info, 1045 sb_virt_addr, sb_phy_addr, rel_sb_id); 1046 1047 return rc; 1048 } 1049 1050 static u32 qed_sb_release(struct qed_dev *cdev, 1051 struct qed_sb_info *sb_info, u16 sb_id) 1052 { 1053 struct qed_hwfn *p_hwfn; 1054 int hwfn_index; 1055 u16 rel_sb_id; 1056 u32 rc; 1057 1058 hwfn_index = sb_id % cdev->num_hwfns; 1059 p_hwfn = &cdev->hwfns[hwfn_index]; 1060 rel_sb_id = sb_id / cdev->num_hwfns; 1061 1062 DP_VERBOSE(cdev, NETIF_MSG_INTR, 1063 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 1064 hwfn_index, rel_sb_id, sb_id); 1065 1066 rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id); 1067 1068 return rc; 1069 } 1070 1071 static bool qed_can_link_change(struct qed_dev *cdev) 1072 { 1073 return true; 1074 } 1075 1076 static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params) 1077 { 1078 struct qed_hwfn *hwfn; 1079 struct qed_mcp_link_params *link_params; 1080 struct qed_ptt *ptt; 1081 int rc; 1082 1083 if (!cdev) 1084 return -ENODEV; 1085 1086 if (IS_VF(cdev)) 1087 return 0; 1088 1089 /* The link should be set only once per PF */ 1090 hwfn = &cdev->hwfns[0]; 1091 1092 ptt = qed_ptt_acquire(hwfn); 1093 if (!ptt) 1094 return -EBUSY; 1095 1096 link_params = qed_mcp_get_link_params(hwfn); 1097 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG) 1098 link_params->speed.autoneg = params->autoneg; 1099 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) { 1100 link_params->speed.advertised_speeds = 0; 1101 if ((params->adv_speeds & QED_LM_1000baseT_Half_BIT) || 1102 (params->adv_speeds & QED_LM_1000baseT_Full_BIT)) 1103 link_params->speed.advertised_speeds |= 1104 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 1105 if (params->adv_speeds & QED_LM_10000baseKR_Full_BIT) 1106 link_params->speed.advertised_speeds |= 1107 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 1108 if (params->adv_speeds & QED_LM_25000baseKR_Full_BIT) 1109 link_params->speed.advertised_speeds |= 1110 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 1111 if (params->adv_speeds & QED_LM_40000baseLR4_Full_BIT) 1112 link_params->speed.advertised_speeds |= 1113 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G; 1114 if (params->adv_speeds & QED_LM_50000baseKR2_Full_BIT) 1115 link_params->speed.advertised_speeds |= 1116 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G; 1117 if (params->adv_speeds & QED_LM_100000baseKR4_Full_BIT) 1118 link_params->speed.advertised_speeds |= 1119 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G; 1120 } 1121 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED) 1122 link_params->speed.forced_speed = params->forced_speed; 1123 if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) { 1124 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) 1125 link_params->pause.autoneg = true; 1126 else 1127 link_params->pause.autoneg = false; 1128 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE) 1129 link_params->pause.forced_rx = true; 1130 else 1131 link_params->pause.forced_rx = false; 1132 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE) 1133 link_params->pause.forced_tx = true; 1134 else 1135 link_params->pause.forced_tx = false; 1136 } 1137 if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) { 1138 switch (params->loopback_mode) { 1139 case QED_LINK_LOOPBACK_INT_PHY: 1140 link_params->loopback_mode = ETH_LOOPBACK_INT_PHY; 1141 break; 1142 case QED_LINK_LOOPBACK_EXT_PHY: 1143 link_params->loopback_mode = ETH_LOOPBACK_EXT_PHY; 1144 break; 1145 case QED_LINK_LOOPBACK_EXT: 1146 link_params->loopback_mode = ETH_LOOPBACK_EXT; 1147 break; 1148 case QED_LINK_LOOPBACK_MAC: 1149 link_params->loopback_mode = ETH_LOOPBACK_MAC; 1150 break; 1151 default: 1152 link_params->loopback_mode = ETH_LOOPBACK_NONE; 1153 break; 1154 } 1155 } 1156 1157 rc = qed_mcp_set_link(hwfn, ptt, params->link_up); 1158 1159 qed_ptt_release(hwfn, ptt); 1160 1161 return rc; 1162 } 1163 1164 static int qed_get_port_type(u32 media_type) 1165 { 1166 int port_type; 1167 1168 switch (media_type) { 1169 case MEDIA_SFPP_10G_FIBER: 1170 case MEDIA_SFP_1G_FIBER: 1171 case MEDIA_XFP_FIBER: 1172 case MEDIA_MODULE_FIBER: 1173 case MEDIA_KR: 1174 port_type = PORT_FIBRE; 1175 break; 1176 case MEDIA_DA_TWINAX: 1177 port_type = PORT_DA; 1178 break; 1179 case MEDIA_BASE_T: 1180 port_type = PORT_TP; 1181 break; 1182 case MEDIA_NOT_PRESENT: 1183 port_type = PORT_NONE; 1184 break; 1185 case MEDIA_UNSPECIFIED: 1186 default: 1187 port_type = PORT_OTHER; 1188 break; 1189 } 1190 return port_type; 1191 } 1192 1193 static int qed_get_link_data(struct qed_hwfn *hwfn, 1194 struct qed_mcp_link_params *params, 1195 struct qed_mcp_link_state *link, 1196 struct qed_mcp_link_capabilities *link_caps) 1197 { 1198 void *p; 1199 1200 if (!IS_PF(hwfn->cdev)) { 1201 qed_vf_get_link_params(hwfn, params); 1202 qed_vf_get_link_state(hwfn, link); 1203 qed_vf_get_link_caps(hwfn, link_caps); 1204 1205 return 0; 1206 } 1207 1208 p = qed_mcp_get_link_params(hwfn); 1209 if (!p) 1210 return -ENXIO; 1211 memcpy(params, p, sizeof(*params)); 1212 1213 p = qed_mcp_get_link_state(hwfn); 1214 if (!p) 1215 return -ENXIO; 1216 memcpy(link, p, sizeof(*link)); 1217 1218 p = qed_mcp_get_link_capabilities(hwfn); 1219 if (!p) 1220 return -ENXIO; 1221 memcpy(link_caps, p, sizeof(*link_caps)); 1222 1223 return 0; 1224 } 1225 1226 static void qed_fill_link(struct qed_hwfn *hwfn, 1227 struct qed_link_output *if_link) 1228 { 1229 struct qed_mcp_link_params params; 1230 struct qed_mcp_link_state link; 1231 struct qed_mcp_link_capabilities link_caps; 1232 u32 media_type; 1233 1234 memset(if_link, 0, sizeof(*if_link)); 1235 1236 /* Prepare source inputs */ 1237 if (qed_get_link_data(hwfn, ¶ms, &link, &link_caps)) { 1238 dev_warn(&hwfn->cdev->pdev->dev, "no link data available\n"); 1239 return; 1240 } 1241 1242 /* Set the link parameters to pass to protocol driver */ 1243 if (link.link_up) 1244 if_link->link_up = true; 1245 1246 /* TODO - at the moment assume supported and advertised speed equal */ 1247 if_link->supported_caps = QED_LM_FIBRE_BIT; 1248 if (params.speed.autoneg) 1249 if_link->supported_caps |= QED_LM_Autoneg_BIT; 1250 if (params.pause.autoneg || 1251 (params.pause.forced_rx && params.pause.forced_tx)) 1252 if_link->supported_caps |= QED_LM_Asym_Pause_BIT; 1253 if (params.pause.autoneg || params.pause.forced_rx || 1254 params.pause.forced_tx) 1255 if_link->supported_caps |= QED_LM_Pause_BIT; 1256 1257 if_link->advertised_caps = if_link->supported_caps; 1258 if (params.speed.advertised_speeds & 1259 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1260 if_link->advertised_caps |= QED_LM_1000baseT_Half_BIT | 1261 QED_LM_1000baseT_Full_BIT; 1262 if (params.speed.advertised_speeds & 1263 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1264 if_link->advertised_caps |= QED_LM_10000baseKR_Full_BIT; 1265 if (params.speed.advertised_speeds & 1266 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1267 if_link->advertised_caps |= QED_LM_25000baseKR_Full_BIT; 1268 if (params.speed.advertised_speeds & 1269 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1270 if_link->advertised_caps |= QED_LM_40000baseLR4_Full_BIT; 1271 if (params.speed.advertised_speeds & 1272 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1273 if_link->advertised_caps |= QED_LM_50000baseKR2_Full_BIT; 1274 if (params.speed.advertised_speeds & 1275 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1276 if_link->advertised_caps |= QED_LM_100000baseKR4_Full_BIT; 1277 1278 if (link_caps.speed_capabilities & 1279 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1280 if_link->supported_caps |= QED_LM_1000baseT_Half_BIT | 1281 QED_LM_1000baseT_Full_BIT; 1282 if (link_caps.speed_capabilities & 1283 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1284 if_link->supported_caps |= QED_LM_10000baseKR_Full_BIT; 1285 if (link_caps.speed_capabilities & 1286 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1287 if_link->supported_caps |= QED_LM_25000baseKR_Full_BIT; 1288 if (link_caps.speed_capabilities & 1289 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1290 if_link->supported_caps |= QED_LM_40000baseLR4_Full_BIT; 1291 if (link_caps.speed_capabilities & 1292 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1293 if_link->supported_caps |= QED_LM_50000baseKR2_Full_BIT; 1294 if (link_caps.speed_capabilities & 1295 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1296 if_link->supported_caps |= QED_LM_100000baseKR4_Full_BIT; 1297 1298 if (link.link_up) 1299 if_link->speed = link.speed; 1300 1301 /* TODO - fill duplex properly */ 1302 if_link->duplex = DUPLEX_FULL; 1303 qed_mcp_get_media_type(hwfn->cdev, &media_type); 1304 if_link->port = qed_get_port_type(media_type); 1305 1306 if_link->autoneg = params.speed.autoneg; 1307 1308 if (params.pause.autoneg) 1309 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 1310 if (params.pause.forced_rx) 1311 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE; 1312 if (params.pause.forced_tx) 1313 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE; 1314 1315 /* Link partner capabilities */ 1316 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_HD) 1317 if_link->lp_caps |= QED_LM_1000baseT_Half_BIT; 1318 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_FD) 1319 if_link->lp_caps |= QED_LM_1000baseT_Full_BIT; 1320 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_10G) 1321 if_link->lp_caps |= QED_LM_10000baseKR_Full_BIT; 1322 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_25G) 1323 if_link->lp_caps |= QED_LM_25000baseKR_Full_BIT; 1324 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_40G) 1325 if_link->lp_caps |= QED_LM_40000baseLR4_Full_BIT; 1326 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_50G) 1327 if_link->lp_caps |= QED_LM_50000baseKR2_Full_BIT; 1328 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_100G) 1329 if_link->lp_caps |= QED_LM_100000baseKR4_Full_BIT; 1330 1331 if (link.an_complete) 1332 if_link->lp_caps |= QED_LM_Autoneg_BIT; 1333 1334 if (link.partner_adv_pause) 1335 if_link->lp_caps |= QED_LM_Pause_BIT; 1336 if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE || 1337 link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE) 1338 if_link->lp_caps |= QED_LM_Asym_Pause_BIT; 1339 } 1340 1341 static void qed_get_current_link(struct qed_dev *cdev, 1342 struct qed_link_output *if_link) 1343 { 1344 int i; 1345 1346 qed_fill_link(&cdev->hwfns[0], if_link); 1347 1348 for_each_hwfn(cdev, i) 1349 qed_inform_vf_link_state(&cdev->hwfns[i]); 1350 } 1351 1352 void qed_link_update(struct qed_hwfn *hwfn) 1353 { 1354 void *cookie = hwfn->cdev->ops_cookie; 1355 struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common; 1356 struct qed_link_output if_link; 1357 1358 qed_fill_link(hwfn, &if_link); 1359 qed_inform_vf_link_state(hwfn); 1360 1361 if (IS_LEAD_HWFN(hwfn) && cookie) 1362 op->link_update(cookie, &if_link); 1363 } 1364 1365 static int qed_drain(struct qed_dev *cdev) 1366 { 1367 struct qed_hwfn *hwfn; 1368 struct qed_ptt *ptt; 1369 int i, rc; 1370 1371 if (IS_VF(cdev)) 1372 return 0; 1373 1374 for_each_hwfn(cdev, i) { 1375 hwfn = &cdev->hwfns[i]; 1376 ptt = qed_ptt_acquire(hwfn); 1377 if (!ptt) { 1378 DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n"); 1379 return -EBUSY; 1380 } 1381 rc = qed_mcp_drain(hwfn, ptt); 1382 if (rc) 1383 return rc; 1384 qed_ptt_release(hwfn, ptt); 1385 } 1386 1387 return 0; 1388 } 1389 1390 static void qed_get_coalesce(struct qed_dev *cdev, u16 *rx_coal, u16 *tx_coal) 1391 { 1392 *rx_coal = cdev->rx_coalesce_usecs; 1393 *tx_coal = cdev->tx_coalesce_usecs; 1394 } 1395 1396 static int qed_set_coalesce(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal, 1397 u8 qid, u16 sb_id) 1398 { 1399 struct qed_hwfn *hwfn; 1400 struct qed_ptt *ptt; 1401 int hwfn_index; 1402 int status = 0; 1403 1404 hwfn_index = qid % cdev->num_hwfns; 1405 hwfn = &cdev->hwfns[hwfn_index]; 1406 ptt = qed_ptt_acquire(hwfn); 1407 if (!ptt) 1408 return -EAGAIN; 1409 1410 status = qed_set_rxq_coalesce(hwfn, ptt, rx_coal, 1411 qid / cdev->num_hwfns, sb_id); 1412 if (status) 1413 goto out; 1414 status = qed_set_txq_coalesce(hwfn, ptt, tx_coal, 1415 qid / cdev->num_hwfns, sb_id); 1416 out: 1417 qed_ptt_release(hwfn, ptt); 1418 1419 return status; 1420 } 1421 1422 static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode) 1423 { 1424 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 1425 struct qed_ptt *ptt; 1426 int status = 0; 1427 1428 ptt = qed_ptt_acquire(hwfn); 1429 if (!ptt) 1430 return -EAGAIN; 1431 1432 status = qed_mcp_set_led(hwfn, ptt, mode); 1433 1434 qed_ptt_release(hwfn, ptt); 1435 1436 return status; 1437 } 1438 1439 static int qed_update_wol(struct qed_dev *cdev, bool enabled) 1440 { 1441 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 1442 struct qed_ptt *ptt; 1443 int rc = 0; 1444 1445 if (IS_VF(cdev)) 1446 return 0; 1447 1448 ptt = qed_ptt_acquire(hwfn); 1449 if (!ptt) 1450 return -EAGAIN; 1451 1452 rc = qed_mcp_ov_update_wol(hwfn, ptt, enabled ? QED_OV_WOL_ENABLED 1453 : QED_OV_WOL_DISABLED); 1454 if (rc) 1455 goto out; 1456 rc = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV); 1457 1458 out: 1459 qed_ptt_release(hwfn, ptt); 1460 return rc; 1461 } 1462 1463 static int qed_update_drv_state(struct qed_dev *cdev, bool active) 1464 { 1465 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 1466 struct qed_ptt *ptt; 1467 int status = 0; 1468 1469 if (IS_VF(cdev)) 1470 return 0; 1471 1472 ptt = qed_ptt_acquire(hwfn); 1473 if (!ptt) 1474 return -EAGAIN; 1475 1476 status = qed_mcp_ov_update_driver_state(hwfn, ptt, active ? 1477 QED_OV_DRIVER_STATE_ACTIVE : 1478 QED_OV_DRIVER_STATE_DISABLED); 1479 1480 qed_ptt_release(hwfn, ptt); 1481 1482 return status; 1483 } 1484 1485 static int qed_update_mac(struct qed_dev *cdev, u8 *mac) 1486 { 1487 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 1488 struct qed_ptt *ptt; 1489 int status = 0; 1490 1491 if (IS_VF(cdev)) 1492 return 0; 1493 1494 ptt = qed_ptt_acquire(hwfn); 1495 if (!ptt) 1496 return -EAGAIN; 1497 1498 status = qed_mcp_ov_update_mac(hwfn, ptt, mac); 1499 if (status) 1500 goto out; 1501 1502 status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV); 1503 1504 out: 1505 qed_ptt_release(hwfn, ptt); 1506 return status; 1507 } 1508 1509 static int qed_update_mtu(struct qed_dev *cdev, u16 mtu) 1510 { 1511 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 1512 struct qed_ptt *ptt; 1513 int status = 0; 1514 1515 if (IS_VF(cdev)) 1516 return 0; 1517 1518 ptt = qed_ptt_acquire(hwfn); 1519 if (!ptt) 1520 return -EAGAIN; 1521 1522 status = qed_mcp_ov_update_mtu(hwfn, ptt, mtu); 1523 if (status) 1524 goto out; 1525 1526 status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV); 1527 1528 out: 1529 qed_ptt_release(hwfn, ptt); 1530 return status; 1531 } 1532 1533 static struct qed_selftest_ops qed_selftest_ops_pass = { 1534 .selftest_memory = &qed_selftest_memory, 1535 .selftest_interrupt = &qed_selftest_interrupt, 1536 .selftest_register = &qed_selftest_register, 1537 .selftest_clock = &qed_selftest_clock, 1538 .selftest_nvram = &qed_selftest_nvram, 1539 }; 1540 1541 const struct qed_common_ops qed_common_ops_pass = { 1542 .selftest = &qed_selftest_ops_pass, 1543 .probe = &qed_probe, 1544 .remove = &qed_remove, 1545 .set_power_state = &qed_set_power_state, 1546 .set_id = &qed_set_id, 1547 .update_pf_params = &qed_update_pf_params, 1548 .slowpath_start = &qed_slowpath_start, 1549 .slowpath_stop = &qed_slowpath_stop, 1550 .set_fp_int = &qed_set_int_fp, 1551 .get_fp_int = &qed_get_int_fp, 1552 .sb_init = &qed_sb_init, 1553 .sb_release = &qed_sb_release, 1554 .simd_handler_config = &qed_simd_handler_config, 1555 .simd_handler_clean = &qed_simd_handler_clean, 1556 .can_link_change = &qed_can_link_change, 1557 .set_link = &qed_set_link, 1558 .get_link = &qed_get_current_link, 1559 .drain = &qed_drain, 1560 .update_msglvl = &qed_init_dp, 1561 .dbg_all_data = &qed_dbg_all_data, 1562 .dbg_all_data_size = &qed_dbg_all_data_size, 1563 .chain_alloc = &qed_chain_alloc, 1564 .chain_free = &qed_chain_free, 1565 .get_coalesce = &qed_get_coalesce, 1566 .set_coalesce = &qed_set_coalesce, 1567 .set_led = &qed_set_led, 1568 .update_drv_state = &qed_update_drv_state, 1569 .update_mac = &qed_update_mac, 1570 .update_mtu = &qed_update_mtu, 1571 .update_wol = &qed_update_wol, 1572 }; 1573 1574 void qed_get_protocol_stats(struct qed_dev *cdev, 1575 enum qed_mcp_protocol_type type, 1576 union qed_mcp_protocol_stats *stats) 1577 { 1578 struct qed_eth_stats eth_stats; 1579 1580 memset(stats, 0, sizeof(*stats)); 1581 1582 switch (type) { 1583 case QED_MCP_LAN_STATS: 1584 qed_get_vport_stats(cdev, ð_stats); 1585 stats->lan_stats.ucast_rx_pkts = eth_stats.rx_ucast_pkts; 1586 stats->lan_stats.ucast_tx_pkts = eth_stats.tx_ucast_pkts; 1587 stats->lan_stats.fcs_err = -1; 1588 break; 1589 default: 1590 DP_ERR(cdev, "Invalid protocol type = %d\n", type); 1591 return; 1592 } 1593 } 1594