1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 /* QLogic qed NIC Driver 3 * Copyright (c) 2015-2017 QLogic Corporation 4 * Copyright (c) 2019-2020 Marvell International Ltd. 5 */ 6 7 #include <linux/types.h> 8 #include <asm/byteorder.h> 9 #include <linux/io.h> 10 #include <linux/bitops.h> 11 #include <linux/delay.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/errno.h> 14 #include <linux/interrupt.h> 15 #include <linux/kernel.h> 16 #include <linux/pci.h> 17 #include <linux/slab.h> 18 #include <linux/string.h> 19 #include "qed.h" 20 #include "qed_hsi.h" 21 #include "qed_hw.h" 22 #include "qed_init_ops.h" 23 #include "qed_int.h" 24 #include "qed_mcp.h" 25 #include "qed_reg_addr.h" 26 #include "qed_sp.h" 27 #include "qed_sriov.h" 28 #include "qed_vf.h" 29 30 struct qed_pi_info { 31 qed_int_comp_cb_t comp_cb; 32 void *cookie; 33 }; 34 35 struct qed_sb_sp_info { 36 struct qed_sb_info sb_info; 37 38 /* per protocol index data */ 39 struct qed_pi_info pi_info_arr[PIS_PER_SB_E4]; 40 }; 41 42 enum qed_attention_type { 43 QED_ATTN_TYPE_ATTN, 44 QED_ATTN_TYPE_PARITY, 45 }; 46 47 #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \ 48 ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn) 49 50 struct aeu_invert_reg_bit { 51 char bit_name[30]; 52 53 #define ATTENTION_PARITY (1 << 0) 54 55 #define ATTENTION_LENGTH_MASK (0x00000ff0) 56 #define ATTENTION_LENGTH_SHIFT (4) 57 #define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \ 58 ATTENTION_LENGTH_SHIFT) 59 #define ATTENTION_SINGLE BIT(ATTENTION_LENGTH_SHIFT) 60 #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY) 61 #define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \ 62 ATTENTION_PARITY) 63 64 /* Multiple bits start with this offset */ 65 #define ATTENTION_OFFSET_MASK (0x000ff000) 66 #define ATTENTION_OFFSET_SHIFT (12) 67 68 #define ATTENTION_BB_MASK (0x00700000) 69 #define ATTENTION_BB_SHIFT (20) 70 #define ATTENTION_BB(value) (value << ATTENTION_BB_SHIFT) 71 #define ATTENTION_BB_DIFFERENT BIT(23) 72 73 #define ATTENTION_CLEAR_ENABLE BIT(28) 74 unsigned int flags; 75 76 /* Callback to call if attention will be triggered */ 77 int (*cb)(struct qed_hwfn *p_hwfn); 78 79 enum block_id block_index; 80 }; 81 82 struct aeu_invert_reg { 83 struct aeu_invert_reg_bit bits[32]; 84 }; 85 86 #define MAX_ATTN_GRPS (8) 87 #define NUM_ATTN_REGS (9) 88 89 /* Specific HW attention callbacks */ 90 static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn) 91 { 92 u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE); 93 94 /* This might occur on certain instances; Log it once then mask it */ 95 DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n", 96 tmp); 97 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 98 0xffffffff); 99 100 return 0; 101 } 102 103 #define QED_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1) 104 #define ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1) 105 #define ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0) 106 #define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0xf) 107 #define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1) 108 #define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x1) 109 #define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5) 110 #define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0xff) 111 #define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6) 112 #define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0xf) 113 #define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14) 114 #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0xff) 115 #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18) 116 static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn) 117 { 118 u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 119 PSWHST_REG_INCORRECT_ACCESS_VALID); 120 121 if (tmp & QED_PSWHST_ATTENTION_INCORRECT_ACCESS) { 122 u32 addr, data, length; 123 124 addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 125 PSWHST_REG_INCORRECT_ACCESS_ADDRESS); 126 data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 127 PSWHST_REG_INCORRECT_ACCESS_DATA); 128 length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 129 PSWHST_REG_INCORRECT_ACCESS_LENGTH); 130 131 DP_INFO(p_hwfn->cdev, 132 "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n", 133 addr, length, 134 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_PF_ID), 135 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_VF_ID), 136 (u8) GET_FIELD(data, 137 ATTENTION_INCORRECT_ACCESS_VF_VALID), 138 (u8) GET_FIELD(data, 139 ATTENTION_INCORRECT_ACCESS_CLIENT), 140 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_WR), 141 (u8) GET_FIELD(data, 142 ATTENTION_INCORRECT_ACCESS_BYTE_EN), 143 data); 144 } 145 146 return 0; 147 } 148 149 #define QED_GRC_ATTENTION_VALID_BIT (1 << 0) 150 #define QED_GRC_ATTENTION_ADDRESS_MASK (0x7fffff) 151 #define QED_GRC_ATTENTION_ADDRESS_SHIFT (0) 152 #define QED_GRC_ATTENTION_RDWR_BIT (1 << 23) 153 #define QED_GRC_ATTENTION_MASTER_MASK (0xf) 154 #define QED_GRC_ATTENTION_MASTER_SHIFT (24) 155 #define QED_GRC_ATTENTION_PF_MASK (0xf) 156 #define QED_GRC_ATTENTION_PF_SHIFT (0) 157 #define QED_GRC_ATTENTION_VF_MASK (0xff) 158 #define QED_GRC_ATTENTION_VF_SHIFT (4) 159 #define QED_GRC_ATTENTION_PRIV_MASK (0x3) 160 #define QED_GRC_ATTENTION_PRIV_SHIFT (14) 161 #define QED_GRC_ATTENTION_PRIV_VF (0) 162 static const char *attn_master_to_str(u8 master) 163 { 164 switch (master) { 165 case 1: return "PXP"; 166 case 2: return "MCP"; 167 case 3: return "MSDM"; 168 case 4: return "PSDM"; 169 case 5: return "YSDM"; 170 case 6: return "USDM"; 171 case 7: return "TSDM"; 172 case 8: return "XSDM"; 173 case 9: return "DBU"; 174 case 10: return "DMAE"; 175 default: 176 return "Unknown"; 177 } 178 } 179 180 static int qed_grc_attn_cb(struct qed_hwfn *p_hwfn) 181 { 182 u32 tmp, tmp2; 183 184 /* We've already cleared the timeout interrupt register, so we learn 185 * of interrupts via the validity register 186 */ 187 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 188 GRC_REG_TIMEOUT_ATTN_ACCESS_VALID); 189 if (!(tmp & QED_GRC_ATTENTION_VALID_BIT)) 190 goto out; 191 192 /* Read the GRC timeout information */ 193 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 194 GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0); 195 tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 196 GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1); 197 198 DP_INFO(p_hwfn->cdev, 199 "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n", 200 tmp2, tmp, 201 (tmp & QED_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from", 202 GET_FIELD(tmp, QED_GRC_ATTENTION_ADDRESS) << 2, 203 attn_master_to_str(GET_FIELD(tmp, QED_GRC_ATTENTION_MASTER)), 204 GET_FIELD(tmp2, QED_GRC_ATTENTION_PF), 205 (GET_FIELD(tmp2, QED_GRC_ATTENTION_PRIV) == 206 QED_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant)", 207 GET_FIELD(tmp2, QED_GRC_ATTENTION_VF)); 208 209 out: 210 /* Regardles of anything else, clean the validity bit */ 211 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 212 GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0); 213 return 0; 214 } 215 216 #define PGLUE_ATTENTION_VALID (1 << 29) 217 #define PGLUE_ATTENTION_RD_VALID (1 << 26) 218 #define PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf) 219 #define PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20) 220 #define PGLUE_ATTENTION_DETAILS_VF_VALID_MASK (0x1) 221 #define PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT (19) 222 #define PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff) 223 #define PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24) 224 #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK (0x1) 225 #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT (21) 226 #define PGLUE_ATTENTION_DETAILS2_BME_MASK (0x1) 227 #define PGLUE_ATTENTION_DETAILS2_BME_SHIFT (22) 228 #define PGLUE_ATTENTION_DETAILS2_FID_EN_MASK (0x1) 229 #define PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT (23) 230 #define PGLUE_ATTENTION_ICPL_VALID (1 << 23) 231 #define PGLUE_ATTENTION_ZLR_VALID (1 << 25) 232 #define PGLUE_ATTENTION_ILT_VALID (1 << 23) 233 234 int qed_pglueb_rbc_attn_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 235 bool hw_init) 236 { 237 char msg[256]; 238 u32 tmp; 239 240 tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS2); 241 if (tmp & PGLUE_ATTENTION_VALID) { 242 u32 addr_lo, addr_hi, details; 243 244 addr_lo = qed_rd(p_hwfn, p_ptt, 245 PGLUE_B_REG_TX_ERR_WR_ADD_31_0); 246 addr_hi = qed_rd(p_hwfn, p_ptt, 247 PGLUE_B_REG_TX_ERR_WR_ADD_63_32); 248 details = qed_rd(p_hwfn, p_ptt, 249 PGLUE_B_REG_TX_ERR_WR_DETAILS); 250 251 snprintf(msg, sizeof(msg), 252 "Illegal write by chip to [%08x:%08x] blocked.\n" 253 "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 254 "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]", 255 addr_hi, addr_lo, details, 256 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 257 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 258 !!GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VF_VALID), 259 tmp, 260 !!GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_WAS_ERR), 261 !!GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_BME), 262 !!GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_FID_EN)); 263 264 if (hw_init) 265 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "%s\n", msg); 266 else 267 DP_NOTICE(p_hwfn, "%s\n", msg); 268 } 269 270 tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS2); 271 if (tmp & PGLUE_ATTENTION_RD_VALID) { 272 u32 addr_lo, addr_hi, details; 273 274 addr_lo = qed_rd(p_hwfn, p_ptt, 275 PGLUE_B_REG_TX_ERR_RD_ADD_31_0); 276 addr_hi = qed_rd(p_hwfn, p_ptt, 277 PGLUE_B_REG_TX_ERR_RD_ADD_63_32); 278 details = qed_rd(p_hwfn, p_ptt, 279 PGLUE_B_REG_TX_ERR_RD_DETAILS); 280 281 DP_NOTICE(p_hwfn, 282 "Illegal read by chip from [%08x:%08x] blocked.\n" 283 "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 284 "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 285 addr_hi, addr_lo, details, 286 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 287 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 288 GET_FIELD(details, 289 PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 290 tmp, 291 GET_FIELD(tmp, 292 PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0, 293 GET_FIELD(tmp, 294 PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 295 GET_FIELD(tmp, 296 PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0); 297 } 298 299 tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL); 300 if (tmp & PGLUE_ATTENTION_ICPL_VALID) { 301 snprintf(msg, sizeof(msg), "ICPL error - %08x", tmp); 302 303 if (hw_init) 304 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "%s\n", msg); 305 else 306 DP_NOTICE(p_hwfn, "%s\n", msg); 307 } 308 309 tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS); 310 if (tmp & PGLUE_ATTENTION_ZLR_VALID) { 311 u32 addr_hi, addr_lo; 312 313 addr_lo = qed_rd(p_hwfn, p_ptt, 314 PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0); 315 addr_hi = qed_rd(p_hwfn, p_ptt, 316 PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32); 317 318 DP_NOTICE(p_hwfn, "ZLR error - %08x [Address %08x:%08x]\n", 319 tmp, addr_hi, addr_lo); 320 } 321 322 tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_DETAILS2); 323 if (tmp & PGLUE_ATTENTION_ILT_VALID) { 324 u32 addr_hi, addr_lo, details; 325 326 addr_lo = qed_rd(p_hwfn, p_ptt, 327 PGLUE_B_REG_VF_ILT_ERR_ADD_31_0); 328 addr_hi = qed_rd(p_hwfn, p_ptt, 329 PGLUE_B_REG_VF_ILT_ERR_ADD_63_32); 330 details = qed_rd(p_hwfn, p_ptt, 331 PGLUE_B_REG_VF_ILT_ERR_DETAILS); 332 333 DP_NOTICE(p_hwfn, 334 "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n", 335 details, tmp, addr_hi, addr_lo); 336 } 337 338 /* Clear the indications */ 339 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_LATCHED_ERRORS_CLR, BIT(2)); 340 341 return 0; 342 } 343 344 static int qed_pglueb_rbc_attn_cb(struct qed_hwfn *p_hwfn) 345 { 346 return qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt, false); 347 } 348 349 static int qed_fw_assertion(struct qed_hwfn *p_hwfn) 350 { 351 qed_hw_err_notify(p_hwfn, p_hwfn->p_dpc_ptt, QED_HW_ERR_FW_ASSERT, 352 "FW assertion!\n"); 353 354 return -EINVAL; 355 } 356 357 static int qed_general_attention_35(struct qed_hwfn *p_hwfn) 358 { 359 DP_INFO(p_hwfn, "General attention 35!\n"); 360 361 return 0; 362 } 363 364 #define QED_DORQ_ATTENTION_REASON_MASK (0xfffff) 365 #define QED_DORQ_ATTENTION_OPAQUE_MASK (0xffff) 366 #define QED_DORQ_ATTENTION_OPAQUE_SHIFT (0x0) 367 #define QED_DORQ_ATTENTION_SIZE_MASK (0x7f) 368 #define QED_DORQ_ATTENTION_SIZE_SHIFT (16) 369 370 #define QED_DB_REC_COUNT 1000 371 #define QED_DB_REC_INTERVAL 100 372 373 static int qed_db_rec_flush_queue(struct qed_hwfn *p_hwfn, 374 struct qed_ptt *p_ptt) 375 { 376 u32 count = QED_DB_REC_COUNT; 377 u32 usage = 1; 378 379 /* Flush any pending (e)dpms as they may never arrive */ 380 qed_wr(p_hwfn, p_ptt, DORQ_REG_DPM_FORCE_ABORT, 0x1); 381 382 /* wait for usage to zero or count to run out. This is necessary since 383 * EDPM doorbell transactions can take multiple 64b cycles, and as such 384 * can "split" over the pci. Possibly, the doorbell drop can happen with 385 * half an EDPM in the queue and other half dropped. Another EDPM 386 * doorbell to the same address (from doorbell recovery mechanism or 387 * from the doorbelling entity) could have first half dropped and second 388 * half interpreted as continuation of the first. To prevent such 389 * malformed doorbells from reaching the device, flush the queue before 390 * releasing the overflow sticky indication. 391 */ 392 while (count-- && usage) { 393 usage = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_USAGE_CNT); 394 udelay(QED_DB_REC_INTERVAL); 395 } 396 397 /* should have been depleted by now */ 398 if (usage) { 399 DP_NOTICE(p_hwfn->cdev, 400 "DB recovery: doorbell usage failed to zero after %d usec. usage was %x\n", 401 QED_DB_REC_INTERVAL * QED_DB_REC_COUNT, usage); 402 return -EBUSY; 403 } 404 405 return 0; 406 } 407 408 int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 409 { 410 u32 attn_ovfl, cur_ovfl; 411 int rc; 412 413 attn_ovfl = test_and_clear_bit(QED_OVERFLOW_BIT, 414 &p_hwfn->db_recovery_info.overflow); 415 cur_ovfl = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY); 416 if (!cur_ovfl && !attn_ovfl) 417 return 0; 418 419 DP_NOTICE(p_hwfn, "PF Overflow sticky: attn %u current %u\n", 420 attn_ovfl, cur_ovfl); 421 422 if (cur_ovfl && !p_hwfn->db_bar_no_edpm) { 423 rc = qed_db_rec_flush_queue(p_hwfn, p_ptt); 424 if (rc) 425 return rc; 426 } 427 428 /* Release overflow sticky indication (stop silently dropping everything) */ 429 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0); 430 431 /* Repeat all last doorbells (doorbell drop recovery) */ 432 qed_db_recovery_execute(p_hwfn); 433 434 return 0; 435 } 436 437 static void qed_dorq_attn_overflow(struct qed_hwfn *p_hwfn) 438 { 439 struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt; 440 u32 overflow; 441 int rc; 442 443 overflow = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY); 444 if (!overflow) 445 goto out; 446 447 /* Run PF doorbell recovery in next periodic handler */ 448 set_bit(QED_OVERFLOW_BIT, &p_hwfn->db_recovery_info.overflow); 449 450 if (!p_hwfn->db_bar_no_edpm) { 451 rc = qed_db_rec_flush_queue(p_hwfn, p_ptt); 452 if (rc) 453 goto out; 454 } 455 456 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0); 457 out: 458 /* Schedule the handler even if overflow was not detected */ 459 qed_periodic_db_rec_start(p_hwfn); 460 } 461 462 static int qed_dorq_attn_int_sts(struct qed_hwfn *p_hwfn) 463 { 464 u32 int_sts, first_drop_reason, details, address, all_drops_reason; 465 struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt; 466 467 int_sts = qed_rd(p_hwfn, p_ptt, DORQ_REG_INT_STS); 468 if (int_sts == 0xdeadbeaf) { 469 DP_NOTICE(p_hwfn->cdev, 470 "DORQ is being reset, skipping int_sts handler\n"); 471 472 return 0; 473 } 474 475 /* int_sts may be zero since all PFs were interrupted for doorbell 476 * overflow but another one already handled it. Can abort here. If 477 * This PF also requires overflow recovery we will be interrupted again. 478 * The masked almost full indication may also be set. Ignoring. 479 */ 480 if (!(int_sts & ~DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) 481 return 0; 482 483 DP_NOTICE(p_hwfn->cdev, "DORQ attention. int_sts was %x\n", int_sts); 484 485 /* check if db_drop or overflow happened */ 486 if (int_sts & (DORQ_REG_INT_STS_DB_DROP | 487 DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR)) { 488 /* Obtain data about db drop/overflow */ 489 first_drop_reason = qed_rd(p_hwfn, p_ptt, 490 DORQ_REG_DB_DROP_REASON) & 491 QED_DORQ_ATTENTION_REASON_MASK; 492 details = qed_rd(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS); 493 address = qed_rd(p_hwfn, p_ptt, 494 DORQ_REG_DB_DROP_DETAILS_ADDRESS); 495 all_drops_reason = qed_rd(p_hwfn, p_ptt, 496 DORQ_REG_DB_DROP_DETAILS_REASON); 497 498 /* Log info */ 499 DP_NOTICE(p_hwfn->cdev, 500 "Doorbell drop occurred\n" 501 "Address\t\t0x%08x\t(second BAR address)\n" 502 "FID\t\t0x%04x\t\t(Opaque FID)\n" 503 "Size\t\t0x%04x\t\t(in bytes)\n" 504 "1st drop reason\t0x%08x\t(details on first drop since last handling)\n" 505 "Sticky reasons\t0x%08x\t(all drop reasons since last handling)\n", 506 address, 507 GET_FIELD(details, QED_DORQ_ATTENTION_OPAQUE), 508 GET_FIELD(details, QED_DORQ_ATTENTION_SIZE) * 4, 509 first_drop_reason, all_drops_reason); 510 511 /* Clear the doorbell drop details and prepare for next drop */ 512 qed_wr(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS_REL, 0); 513 514 /* Mark interrupt as handled (note: even if drop was due to a different 515 * reason than overflow we mark as handled) 516 */ 517 qed_wr(p_hwfn, 518 p_ptt, 519 DORQ_REG_INT_STS_WR, 520 DORQ_REG_INT_STS_DB_DROP | 521 DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR); 522 523 /* If there are no indications other than drop indications, success */ 524 if ((int_sts & ~(DORQ_REG_INT_STS_DB_DROP | 525 DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR | 526 DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) == 0) 527 return 0; 528 } 529 530 /* Some other indication was present - non recoverable */ 531 DP_INFO(p_hwfn, "DORQ fatal attention\n"); 532 533 return -EINVAL; 534 } 535 536 static int qed_dorq_attn_cb(struct qed_hwfn *p_hwfn) 537 { 538 if (p_hwfn->cdev->recov_in_prog) 539 return 0; 540 541 p_hwfn->db_recovery_info.dorq_attn = true; 542 qed_dorq_attn_overflow(p_hwfn); 543 544 return qed_dorq_attn_int_sts(p_hwfn); 545 } 546 547 static void qed_dorq_attn_handler(struct qed_hwfn *p_hwfn) 548 { 549 if (p_hwfn->db_recovery_info.dorq_attn) 550 goto out; 551 552 /* Call DORQ callback if the attention was missed */ 553 qed_dorq_attn_cb(p_hwfn); 554 out: 555 p_hwfn->db_recovery_info.dorq_attn = false; 556 } 557 558 /* Instead of major changes to the data-structure, we have a some 'special' 559 * identifiers for sources that changed meaning between adapters. 560 */ 561 enum aeu_invert_reg_special_type { 562 AEU_INVERT_REG_SPECIAL_CNIG_0, 563 AEU_INVERT_REG_SPECIAL_CNIG_1, 564 AEU_INVERT_REG_SPECIAL_CNIG_2, 565 AEU_INVERT_REG_SPECIAL_CNIG_3, 566 AEU_INVERT_REG_SPECIAL_MAX, 567 }; 568 569 static struct aeu_invert_reg_bit 570 aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = { 571 {"CNIG port 0", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 572 {"CNIG port 1", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 573 {"CNIG port 2", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 574 {"CNIG port 3", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 575 }; 576 577 /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */ 578 static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = { 579 { 580 { /* After Invert 1 */ 581 {"GPIO0 function%d", 582 (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 583 } 584 }, 585 586 { 587 { /* After Invert 2 */ 588 {"PGLUE config_space", ATTENTION_SINGLE, 589 NULL, MAX_BLOCK_ID}, 590 {"PGLUE misc_flr", ATTENTION_SINGLE, 591 NULL, MAX_BLOCK_ID}, 592 {"PGLUE B RBC", ATTENTION_PAR_INT, 593 qed_pglueb_rbc_attn_cb, BLOCK_PGLUE_B}, 594 {"PGLUE misc_mctp", ATTENTION_SINGLE, 595 NULL, MAX_BLOCK_ID}, 596 {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 597 {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 598 {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 599 {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) | 600 (1 << ATTENTION_OFFSET_SHIFT), 601 NULL, MAX_BLOCK_ID}, 602 {"PCIE glue/PXP VPD %d", 603 (16 << ATTENTION_LENGTH_SHIFT), NULL, BLOCK_PGLCS}, 604 } 605 }, 606 607 { 608 { /* After Invert 3 */ 609 {"General Attention %d", 610 (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 611 } 612 }, 613 614 { 615 { /* After Invert 4 */ 616 {"General Attention 32", ATTENTION_SINGLE | 617 ATTENTION_CLEAR_ENABLE, qed_fw_assertion, 618 MAX_BLOCK_ID}, 619 {"General Attention %d", 620 (2 << ATTENTION_LENGTH_SHIFT) | 621 (33 << ATTENTION_OFFSET_SHIFT), NULL, MAX_BLOCK_ID}, 622 {"General Attention 35", ATTENTION_SINGLE | 623 ATTENTION_CLEAR_ENABLE, qed_general_attention_35, 624 MAX_BLOCK_ID}, 625 {"NWS Parity", 626 ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 627 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0), 628 NULL, BLOCK_NWS}, 629 {"NWS Interrupt", 630 ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 631 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1), 632 NULL, BLOCK_NWS}, 633 {"NWM Parity", 634 ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 635 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2), 636 NULL, BLOCK_NWM}, 637 {"NWM Interrupt", 638 ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 639 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3), 640 NULL, BLOCK_NWM}, 641 {"MCP CPU", ATTENTION_SINGLE, 642 qed_mcp_attn_cb, MAX_BLOCK_ID}, 643 {"MCP Watchdog timer", ATTENTION_SINGLE, 644 NULL, MAX_BLOCK_ID}, 645 {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 646 {"AVS stop status ready", ATTENTION_SINGLE, 647 NULL, MAX_BLOCK_ID}, 648 {"MSTAT", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 649 {"MSTAT per-path", ATTENTION_PAR_INT, 650 NULL, MAX_BLOCK_ID}, 651 {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), 652 NULL, MAX_BLOCK_ID}, 653 {"NIG", ATTENTION_PAR_INT, NULL, BLOCK_NIG}, 654 {"BMB/OPTE/MCP", ATTENTION_PAR_INT, NULL, BLOCK_BMB}, 655 {"BTB", ATTENTION_PAR_INT, NULL, BLOCK_BTB}, 656 {"BRB", ATTENTION_PAR_INT, NULL, BLOCK_BRB}, 657 {"PRS", ATTENTION_PAR_INT, NULL, BLOCK_PRS}, 658 } 659 }, 660 661 { 662 { /* After Invert 5 */ 663 {"SRC", ATTENTION_PAR_INT, NULL, BLOCK_SRC}, 664 {"PB Client1", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB1}, 665 {"PB Client2", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB2}, 666 {"RPB", ATTENTION_PAR_INT, NULL, BLOCK_RPB}, 667 {"PBF", ATTENTION_PAR_INT, NULL, BLOCK_PBF}, 668 {"QM", ATTENTION_PAR_INT, NULL, BLOCK_QM}, 669 {"TM", ATTENTION_PAR_INT, NULL, BLOCK_TM}, 670 {"MCM", ATTENTION_PAR_INT, NULL, BLOCK_MCM}, 671 {"MSDM", ATTENTION_PAR_INT, NULL, BLOCK_MSDM}, 672 {"MSEM", ATTENTION_PAR_INT, NULL, BLOCK_MSEM}, 673 {"PCM", ATTENTION_PAR_INT, NULL, BLOCK_PCM}, 674 {"PSDM", ATTENTION_PAR_INT, NULL, BLOCK_PSDM}, 675 {"PSEM", ATTENTION_PAR_INT, NULL, BLOCK_PSEM}, 676 {"TCM", ATTENTION_PAR_INT, NULL, BLOCK_TCM}, 677 {"TSDM", ATTENTION_PAR_INT, NULL, BLOCK_TSDM}, 678 {"TSEM", ATTENTION_PAR_INT, NULL, BLOCK_TSEM}, 679 } 680 }, 681 682 { 683 { /* After Invert 6 */ 684 {"UCM", ATTENTION_PAR_INT, NULL, BLOCK_UCM}, 685 {"USDM", ATTENTION_PAR_INT, NULL, BLOCK_USDM}, 686 {"USEM", ATTENTION_PAR_INT, NULL, BLOCK_USEM}, 687 {"XCM", ATTENTION_PAR_INT, NULL, BLOCK_XCM}, 688 {"XSDM", ATTENTION_PAR_INT, NULL, BLOCK_XSDM}, 689 {"XSEM", ATTENTION_PAR_INT, NULL, BLOCK_XSEM}, 690 {"YCM", ATTENTION_PAR_INT, NULL, BLOCK_YCM}, 691 {"YSDM", ATTENTION_PAR_INT, NULL, BLOCK_YSDM}, 692 {"YSEM", ATTENTION_PAR_INT, NULL, BLOCK_YSEM}, 693 {"XYLD", ATTENTION_PAR_INT, NULL, BLOCK_XYLD}, 694 {"TMLD", ATTENTION_PAR_INT, NULL, BLOCK_TMLD}, 695 {"MYLD", ATTENTION_PAR_INT, NULL, BLOCK_MULD}, 696 {"YULD", ATTENTION_PAR_INT, NULL, BLOCK_YULD}, 697 {"DORQ", ATTENTION_PAR_INT, 698 qed_dorq_attn_cb, BLOCK_DORQ}, 699 {"DBG", ATTENTION_PAR_INT, NULL, BLOCK_DBG}, 700 {"IPC", ATTENTION_PAR_INT, NULL, BLOCK_IPC}, 701 } 702 }, 703 704 { 705 { /* After Invert 7 */ 706 {"CCFC", ATTENTION_PAR_INT, NULL, BLOCK_CCFC}, 707 {"CDU", ATTENTION_PAR_INT, NULL, BLOCK_CDU}, 708 {"DMAE", ATTENTION_PAR_INT, NULL, BLOCK_DMAE}, 709 {"IGU", ATTENTION_PAR_INT, NULL, BLOCK_IGU}, 710 {"ATC", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 711 {"CAU", ATTENTION_PAR_INT, NULL, BLOCK_CAU}, 712 {"PTU", ATTENTION_PAR_INT, NULL, BLOCK_PTU}, 713 {"PRM", ATTENTION_PAR_INT, NULL, BLOCK_PRM}, 714 {"TCFC", ATTENTION_PAR_INT, NULL, BLOCK_TCFC}, 715 {"RDIF", ATTENTION_PAR_INT, NULL, BLOCK_RDIF}, 716 {"TDIF", ATTENTION_PAR_INT, NULL, BLOCK_TDIF}, 717 {"RSS", ATTENTION_PAR_INT, NULL, BLOCK_RSS}, 718 {"MISC", ATTENTION_PAR_INT, NULL, BLOCK_MISC}, 719 {"MISCS", ATTENTION_PAR_INT, NULL, BLOCK_MISCS}, 720 {"PCIE", ATTENTION_PAR, NULL, BLOCK_PCIE}, 721 {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS}, 722 {"PSWRQ", ATTENTION_PAR_INT, NULL, BLOCK_PSWRQ}, 723 } 724 }, 725 726 { 727 { /* After Invert 8 */ 728 {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, 729 NULL, BLOCK_PSWRQ2}, 730 {"PSWWR", ATTENTION_PAR_INT, NULL, BLOCK_PSWWR}, 731 {"PSWWR (pci_clk)", ATTENTION_PAR_INT, 732 NULL, BLOCK_PSWWR2}, 733 {"PSWRD", ATTENTION_PAR_INT, NULL, BLOCK_PSWRD}, 734 {"PSWRD (pci_clk)", ATTENTION_PAR_INT, 735 NULL, BLOCK_PSWRD2}, 736 {"PSWHST", ATTENTION_PAR_INT, 737 qed_pswhst_attn_cb, BLOCK_PSWHST}, 738 {"PSWHST (pci_clk)", ATTENTION_PAR_INT, 739 NULL, BLOCK_PSWHST2}, 740 {"GRC", ATTENTION_PAR_INT, 741 qed_grc_attn_cb, BLOCK_GRC}, 742 {"CPMU", ATTENTION_PAR_INT, NULL, BLOCK_CPMU}, 743 {"NCSI", ATTENTION_PAR_INT, NULL, BLOCK_NCSI}, 744 {"MSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 745 {"PSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 746 {"TSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 747 {"USEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 748 {"XSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 749 {"YSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 750 {"pxp_misc_mps", ATTENTION_PAR, NULL, BLOCK_PGLCS}, 751 {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, 752 NULL, BLOCK_PGLCS}, 753 {"PERST_B assertion", ATTENTION_SINGLE, 754 NULL, MAX_BLOCK_ID}, 755 {"PERST_B deassertion", ATTENTION_SINGLE, 756 NULL, MAX_BLOCK_ID}, 757 {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), 758 NULL, MAX_BLOCK_ID}, 759 } 760 }, 761 762 { 763 { /* After Invert 9 */ 764 {"MCP Latched memory", ATTENTION_PAR, 765 NULL, MAX_BLOCK_ID}, 766 {"MCP Latched scratchpad cache", ATTENTION_SINGLE, 767 NULL, MAX_BLOCK_ID}, 768 {"MCP Latched ump_tx", ATTENTION_PAR, 769 NULL, MAX_BLOCK_ID}, 770 {"MCP Latched scratchpad", ATTENTION_PAR, 771 NULL, MAX_BLOCK_ID}, 772 {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), 773 NULL, MAX_BLOCK_ID}, 774 } 775 }, 776 }; 777 778 static struct aeu_invert_reg_bit * 779 qed_int_aeu_translate(struct qed_hwfn *p_hwfn, 780 struct aeu_invert_reg_bit *p_bit) 781 { 782 if (!QED_IS_BB(p_hwfn->cdev)) 783 return p_bit; 784 785 if (!(p_bit->flags & ATTENTION_BB_DIFFERENT)) 786 return p_bit; 787 788 return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >> 789 ATTENTION_BB_SHIFT]; 790 } 791 792 static bool qed_int_is_parity_flag(struct qed_hwfn *p_hwfn, 793 struct aeu_invert_reg_bit *p_bit) 794 { 795 return !!(qed_int_aeu_translate(p_hwfn, p_bit)->flags & 796 ATTENTION_PARITY); 797 } 798 799 #define ATTN_STATE_BITS (0xfff) 800 #define ATTN_BITS_MASKABLE (0x3ff) 801 struct qed_sb_attn_info { 802 /* Virtual & Physical address of the SB */ 803 struct atten_status_block *sb_attn; 804 dma_addr_t sb_phys; 805 806 /* Last seen running index */ 807 u16 index; 808 809 /* A mask of the AEU bits resulting in a parity error */ 810 u32 parity_mask[NUM_ATTN_REGS]; 811 812 /* A pointer to the attention description structure */ 813 struct aeu_invert_reg *p_aeu_desc; 814 815 /* Previously asserted attentions, which are still unasserted */ 816 u16 known_attn; 817 818 /* Cleanup address for the link's general hw attention */ 819 u32 mfw_attn_addr; 820 }; 821 822 static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn, 823 struct qed_sb_attn_info *p_sb_desc) 824 { 825 u16 rc = 0, index; 826 827 index = le16_to_cpu(p_sb_desc->sb_attn->sb_index); 828 if (p_sb_desc->index != index) { 829 p_sb_desc->index = index; 830 rc = QED_SB_ATT_IDX; 831 } 832 833 return rc; 834 } 835 836 /** 837 * qed_int_assertion() - Handle asserted attention bits. 838 * 839 * @p_hwfn: HW device data. 840 * @asserted_bits: Newly asserted bits. 841 * 842 * Return: Zero value. 843 */ 844 static int qed_int_assertion(struct qed_hwfn *p_hwfn, u16 asserted_bits) 845 { 846 struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 847 u32 igu_mask; 848 849 /* Mask the source of the attention in the IGU */ 850 igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 851 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n", 852 igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE)); 853 igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE); 854 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask); 855 856 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 857 "inner known ATTN state: 0x%04x --> 0x%04x\n", 858 sb_attn_sw->known_attn, 859 sb_attn_sw->known_attn | asserted_bits); 860 sb_attn_sw->known_attn |= asserted_bits; 861 862 /* Handle MCP events */ 863 if (asserted_bits & 0x100) { 864 qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt); 865 /* Clean the MCP attention */ 866 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 867 sb_attn_sw->mfw_attn_addr, 0); 868 } 869 870 DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 871 GTT_BAR0_MAP_REG_IGU_CMD + 872 ((IGU_CMD_ATTN_BIT_SET_UPPER - 873 IGU_CMD_INT_ACK_BASE) << 3), 874 (u32)asserted_bits); 875 876 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n", 877 asserted_bits); 878 879 return 0; 880 } 881 882 static void qed_int_attn_print(struct qed_hwfn *p_hwfn, 883 enum block_id id, 884 enum dbg_attn_type type, bool b_clear) 885 { 886 struct dbg_attn_block_result attn_results; 887 enum dbg_status status; 888 889 memset(&attn_results, 0, sizeof(attn_results)); 890 891 status = qed_dbg_read_attn(p_hwfn, p_hwfn->p_dpc_ptt, id, type, 892 b_clear, &attn_results); 893 if (status != DBG_STATUS_OK) 894 DP_NOTICE(p_hwfn, 895 "Failed to parse attention information [status: %s]\n", 896 qed_dbg_get_status_str(status)); 897 else 898 qed_dbg_parse_attn(p_hwfn, &attn_results); 899 } 900 901 /** 902 * qed_int_deassertion_aeu_bit() - Handles the effects of a single 903 * cause of the attention. 904 * 905 * @p_hwfn: HW device data. 906 * @p_aeu: Descriptor of an AEU bit which caused the attention. 907 * @aeu_en_reg: Register offset of the AEU enable reg. which configured 908 * this bit to this group. 909 * @p_bit_name: AEU bit description for logging purposes. 910 * @bitmask: Index of this bit in the aeu_en_reg. 911 * 912 * Return: Zero on success, negative errno otherwise. 913 */ 914 static int 915 qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn, 916 struct aeu_invert_reg_bit *p_aeu, 917 u32 aeu_en_reg, 918 const char *p_bit_name, u32 bitmask) 919 { 920 bool b_fatal = false; 921 int rc = -EINVAL; 922 u32 val; 923 924 DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n", 925 p_bit_name, bitmask); 926 927 /* Call callback before clearing the interrupt status */ 928 if (p_aeu->cb) { 929 DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n", 930 p_bit_name); 931 rc = p_aeu->cb(p_hwfn); 932 } 933 934 if (rc) 935 b_fatal = true; 936 937 /* Print HW block interrupt registers */ 938 if (p_aeu->block_index != MAX_BLOCK_ID) 939 qed_int_attn_print(p_hwfn, p_aeu->block_index, 940 ATTN_TYPE_INTERRUPT, !b_fatal); 941 942 /* Reach assertion if attention is fatal */ 943 if (b_fatal) 944 qed_hw_err_notify(p_hwfn, p_hwfn->p_dpc_ptt, QED_HW_ERR_HW_ATTN, 945 "`%s': Fatal attention\n", 946 p_bit_name); 947 else /* If the attention is benign, no need to prevent it */ 948 goto out; 949 950 /* Prevent this Attention from being asserted in the future */ 951 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 952 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask)); 953 DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n", 954 p_bit_name); 955 956 out: 957 return rc; 958 } 959 960 /** 961 * qed_int_deassertion_parity() - Handle a single parity AEU source. 962 * 963 * @p_hwfn: HW device data. 964 * @p_aeu: Descriptor of an AEU bit which caused the parity. 965 * @aeu_en_reg: Address of the AEU enable register. 966 * @bit_index: Index (0-31) of an AEU bit. 967 */ 968 static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn, 969 struct aeu_invert_reg_bit *p_aeu, 970 u32 aeu_en_reg, u8 bit_index) 971 { 972 u32 block_id = p_aeu->block_index, mask, val; 973 974 DP_NOTICE(p_hwfn->cdev, 975 "%s parity attention is set [address 0x%08x, bit %d]\n", 976 p_aeu->bit_name, aeu_en_reg, bit_index); 977 978 if (block_id != MAX_BLOCK_ID) { 979 qed_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false); 980 981 /* In BB, there's a single parity bit for several blocks */ 982 if (block_id == BLOCK_BTB) { 983 qed_int_attn_print(p_hwfn, BLOCK_OPTE, 984 ATTN_TYPE_PARITY, false); 985 qed_int_attn_print(p_hwfn, BLOCK_MCP, 986 ATTN_TYPE_PARITY, false); 987 } 988 } 989 990 /* Prevent this parity error from being re-asserted */ 991 mask = ~BIT(bit_index); 992 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 993 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask); 994 DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n", 995 p_aeu->bit_name); 996 } 997 998 /** 999 * qed_int_deassertion() - Handle deassertion of previously asserted 1000 * attentions. 1001 * 1002 * @p_hwfn: HW device data. 1003 * @deasserted_bits: newly deasserted bits. 1004 * 1005 * Return: Zero value. 1006 */ 1007 static int qed_int_deassertion(struct qed_hwfn *p_hwfn, 1008 u16 deasserted_bits) 1009 { 1010 struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 1011 u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en; 1012 u8 i, j, k, bit_idx; 1013 int rc = 0; 1014 1015 /* Read the attention registers in the AEU */ 1016 for (i = 0; i < NUM_ATTN_REGS; i++) { 1017 aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1018 MISC_REG_AEU_AFTER_INVERT_1_IGU + 1019 i * 0x4); 1020 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1021 "Deasserted bits [%d]: %08x\n", 1022 i, aeu_inv_arr[i]); 1023 } 1024 1025 /* Find parity attentions first */ 1026 for (i = 0; i < NUM_ATTN_REGS; i++) { 1027 struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i]; 1028 u32 parities; 1029 1030 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32); 1031 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 1032 1033 /* Skip register in which no parity bit is currently set */ 1034 parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en; 1035 if (!parities) 1036 continue; 1037 1038 for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 1039 struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j]; 1040 1041 if (qed_int_is_parity_flag(p_hwfn, p_bit) && 1042 !!(parities & BIT(bit_idx))) 1043 qed_int_deassertion_parity(p_hwfn, p_bit, 1044 aeu_en, bit_idx); 1045 1046 bit_idx += ATTENTION_LENGTH(p_bit->flags); 1047 } 1048 } 1049 1050 /* Find non-parity cause for attention and act */ 1051 for (k = 0; k < MAX_ATTN_GRPS; k++) { 1052 struct aeu_invert_reg_bit *p_aeu; 1053 1054 /* Handle only groups whose attention is currently deasserted */ 1055 if (!(deasserted_bits & (1 << k))) 1056 continue; 1057 1058 for (i = 0; i < NUM_ATTN_REGS; i++) { 1059 u32 bits; 1060 1061 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + 1062 i * sizeof(u32) + 1063 k * sizeof(u32) * NUM_ATTN_REGS; 1064 1065 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 1066 bits = aeu_inv_arr[i] & en; 1067 1068 /* Skip if no bit from this group is currently set */ 1069 if (!bits) 1070 continue; 1071 1072 /* Find all set bits from current register which belong 1073 * to current group, making them responsible for the 1074 * previous assertion. 1075 */ 1076 for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 1077 long unsigned int bitmask; 1078 u8 bit, bit_len; 1079 1080 p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j]; 1081 p_aeu = qed_int_aeu_translate(p_hwfn, p_aeu); 1082 1083 bit = bit_idx; 1084 bit_len = ATTENTION_LENGTH(p_aeu->flags); 1085 if (qed_int_is_parity_flag(p_hwfn, p_aeu)) { 1086 /* Skip Parity */ 1087 bit++; 1088 bit_len--; 1089 } 1090 1091 bitmask = bits & (((1 << bit_len) - 1) << bit); 1092 bitmask >>= bit; 1093 1094 if (bitmask) { 1095 u32 flags = p_aeu->flags; 1096 char bit_name[30]; 1097 u8 num; 1098 1099 num = (u8)find_first_bit(&bitmask, 1100 bit_len); 1101 1102 /* Some bits represent more than a 1103 * a single interrupt. Correctly print 1104 * their name. 1105 */ 1106 if (ATTENTION_LENGTH(flags) > 2 || 1107 ((flags & ATTENTION_PAR_INT) && 1108 ATTENTION_LENGTH(flags) > 1)) 1109 snprintf(bit_name, 30, 1110 p_aeu->bit_name, num); 1111 else 1112 strlcpy(bit_name, 1113 p_aeu->bit_name, 30); 1114 1115 /* We now need to pass bitmask in its 1116 * correct position. 1117 */ 1118 bitmask <<= bit; 1119 1120 /* Handle source of the attention */ 1121 qed_int_deassertion_aeu_bit(p_hwfn, 1122 p_aeu, 1123 aeu_en, 1124 bit_name, 1125 bitmask); 1126 } 1127 1128 bit_idx += ATTENTION_LENGTH(p_aeu->flags); 1129 } 1130 } 1131 } 1132 1133 /* Handle missed DORQ attention */ 1134 qed_dorq_attn_handler(p_hwfn); 1135 1136 /* Clear IGU indication for the deasserted bits */ 1137 DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 1138 GTT_BAR0_MAP_REG_IGU_CMD + 1139 ((IGU_CMD_ATTN_BIT_CLR_UPPER - 1140 IGU_CMD_INT_ACK_BASE) << 3), 1141 ~((u32)deasserted_bits)); 1142 1143 /* Unmask deasserted attentions in IGU */ 1144 aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 1145 aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE); 1146 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask); 1147 1148 /* Clear deassertion from inner state */ 1149 sb_attn_sw->known_attn &= ~deasserted_bits; 1150 1151 return rc; 1152 } 1153 1154 static int qed_int_attentions(struct qed_hwfn *p_hwfn) 1155 { 1156 struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn; 1157 struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn; 1158 u32 attn_bits = 0, attn_acks = 0; 1159 u16 asserted_bits, deasserted_bits; 1160 __le16 index; 1161 int rc = 0; 1162 1163 /* Read current attention bits/acks - safeguard against attentions 1164 * by guaranting work on a synchronized timeframe 1165 */ 1166 do { 1167 index = p_sb_attn->sb_index; 1168 /* finish reading index before the loop condition */ 1169 dma_rmb(); 1170 attn_bits = le32_to_cpu(p_sb_attn->atten_bits); 1171 attn_acks = le32_to_cpu(p_sb_attn->atten_ack); 1172 } while (index != p_sb_attn->sb_index); 1173 p_sb_attn->sb_index = index; 1174 1175 /* Attention / Deassertion are meaningful (and in correct state) 1176 * only when they differ and consistent with known state - deassertion 1177 * when previous attention & current ack, and assertion when current 1178 * attention with no previous attention 1179 */ 1180 asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) & 1181 ~p_sb_attn_sw->known_attn; 1182 deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) & 1183 p_sb_attn_sw->known_attn; 1184 1185 if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) { 1186 DP_INFO(p_hwfn, 1187 "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n", 1188 index, attn_bits, attn_acks, asserted_bits, 1189 deasserted_bits, p_sb_attn_sw->known_attn); 1190 } else if (asserted_bits == 0x100) { 1191 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1192 "MFW indication via attention\n"); 1193 } else { 1194 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1195 "MFW indication [deassertion]\n"); 1196 } 1197 1198 if (asserted_bits) { 1199 rc = qed_int_assertion(p_hwfn, asserted_bits); 1200 if (rc) 1201 return rc; 1202 } 1203 1204 if (deasserted_bits) 1205 rc = qed_int_deassertion(p_hwfn, deasserted_bits); 1206 1207 return rc; 1208 } 1209 1210 static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn, 1211 void __iomem *igu_addr, u32 ack_cons) 1212 { 1213 u32 igu_ack; 1214 1215 igu_ack = ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 1216 (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 1217 (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 1218 (IGU_SEG_ACCESS_ATTN << 1219 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 1220 1221 DIRECT_REG_WR(igu_addr, igu_ack); 1222 1223 /* Both segments (interrupts & acks) are written to same place address; 1224 * Need to guarantee all commands will be received (in-order) by HW. 1225 */ 1226 barrier(); 1227 } 1228 1229 void qed_int_sp_dpc(struct tasklet_struct *t) 1230 { 1231 struct qed_hwfn *p_hwfn = from_tasklet(p_hwfn, t, sp_dpc); 1232 struct qed_pi_info *pi_info = NULL; 1233 struct qed_sb_attn_info *sb_attn; 1234 struct qed_sb_info *sb_info; 1235 int arr_size; 1236 u16 rc = 0; 1237 1238 if (!p_hwfn->p_sp_sb) { 1239 DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n"); 1240 return; 1241 } 1242 1243 sb_info = &p_hwfn->p_sp_sb->sb_info; 1244 arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr); 1245 if (!sb_info) { 1246 DP_ERR(p_hwfn->cdev, 1247 "Status block is NULL - cannot ack interrupts\n"); 1248 return; 1249 } 1250 1251 if (!p_hwfn->p_sb_attn) { 1252 DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn"); 1253 return; 1254 } 1255 sb_attn = p_hwfn->p_sb_attn; 1256 1257 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n", 1258 p_hwfn, p_hwfn->my_id); 1259 1260 /* Disable ack for def status block. Required both for msix + 1261 * inta in non-mask mode, in inta does no harm. 1262 */ 1263 qed_sb_ack(sb_info, IGU_INT_DISABLE, 0); 1264 1265 /* Gather Interrupts/Attentions information */ 1266 if (!sb_info->sb_virt) { 1267 DP_ERR(p_hwfn->cdev, 1268 "Interrupt Status block is NULL - cannot check for new interrupts!\n"); 1269 } else { 1270 u32 tmp_index = sb_info->sb_ack; 1271 1272 rc = qed_sb_update_sb_idx(sb_info); 1273 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1274 "Interrupt indices: 0x%08x --> 0x%08x\n", 1275 tmp_index, sb_info->sb_ack); 1276 } 1277 1278 if (!sb_attn || !sb_attn->sb_attn) { 1279 DP_ERR(p_hwfn->cdev, 1280 "Attentions Status block is NULL - cannot check for new attentions!\n"); 1281 } else { 1282 u16 tmp_index = sb_attn->index; 1283 1284 rc |= qed_attn_update_idx(p_hwfn, sb_attn); 1285 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1286 "Attention indices: 0x%08x --> 0x%08x\n", 1287 tmp_index, sb_attn->index); 1288 } 1289 1290 /* Check if we expect interrupts at this time. if not just ack them */ 1291 if (!(rc & QED_SB_EVENT_MASK)) { 1292 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1293 return; 1294 } 1295 1296 /* Check the validity of the DPC ptt. If not ack interrupts and fail */ 1297 if (!p_hwfn->p_dpc_ptt) { 1298 DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n"); 1299 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1300 return; 1301 } 1302 1303 if (rc & QED_SB_ATT_IDX) 1304 qed_int_attentions(p_hwfn); 1305 1306 if (rc & QED_SB_IDX) { 1307 int pi; 1308 1309 /* Look for a free index */ 1310 for (pi = 0; pi < arr_size; pi++) { 1311 pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi]; 1312 if (pi_info->comp_cb) 1313 pi_info->comp_cb(p_hwfn, pi_info->cookie); 1314 } 1315 } 1316 1317 if (sb_attn && (rc & QED_SB_ATT_IDX)) 1318 /* This should be done before the interrupts are enabled, 1319 * since otherwise a new attention will be generated. 1320 */ 1321 qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index); 1322 1323 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1324 } 1325 1326 static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn) 1327 { 1328 struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn; 1329 1330 if (!p_sb) 1331 return; 1332 1333 if (p_sb->sb_attn) 1334 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1335 SB_ATTN_ALIGNED_SIZE(p_hwfn), 1336 p_sb->sb_attn, p_sb->sb_phys); 1337 kfree(p_sb); 1338 p_hwfn->p_sb_attn = NULL; 1339 } 1340 1341 static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn, 1342 struct qed_ptt *p_ptt) 1343 { 1344 struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 1345 1346 memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn)); 1347 1348 sb_info->index = 0; 1349 sb_info->known_attn = 0; 1350 1351 /* Configure Attention Status Block in IGU */ 1352 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L, 1353 lower_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1354 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H, 1355 upper_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1356 } 1357 1358 static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn, 1359 struct qed_ptt *p_ptt, 1360 void *sb_virt_addr, dma_addr_t sb_phy_addr) 1361 { 1362 struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 1363 int i, j, k; 1364 1365 sb_info->sb_attn = sb_virt_addr; 1366 sb_info->sb_phys = sb_phy_addr; 1367 1368 /* Set the pointer to the AEU descriptors */ 1369 sb_info->p_aeu_desc = aeu_descs; 1370 1371 /* Calculate Parity Masks */ 1372 memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS); 1373 for (i = 0; i < NUM_ATTN_REGS; i++) { 1374 /* j is array index, k is bit index */ 1375 for (j = 0, k = 0; k < 32; j++) { 1376 struct aeu_invert_reg_bit *p_aeu; 1377 1378 p_aeu = &aeu_descs[i].bits[j]; 1379 if (qed_int_is_parity_flag(p_hwfn, p_aeu)) 1380 sb_info->parity_mask[i] |= 1 << k; 1381 1382 k += ATTENTION_LENGTH(p_aeu->flags); 1383 } 1384 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1385 "Attn Mask [Reg %d]: 0x%08x\n", 1386 i, sb_info->parity_mask[i]); 1387 } 1388 1389 /* Set the address of cleanup for the mcp attention */ 1390 sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) + 1391 MISC_REG_AEU_GENERAL_ATTN_0; 1392 1393 qed_int_sb_attn_setup(p_hwfn, p_ptt); 1394 } 1395 1396 static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn, 1397 struct qed_ptt *p_ptt) 1398 { 1399 struct qed_dev *cdev = p_hwfn->cdev; 1400 struct qed_sb_attn_info *p_sb; 1401 dma_addr_t p_phys = 0; 1402 void *p_virt; 1403 1404 /* SB struct */ 1405 p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 1406 if (!p_sb) 1407 return -ENOMEM; 1408 1409 /* SB ring */ 1410 p_virt = dma_alloc_coherent(&cdev->pdev->dev, 1411 SB_ATTN_ALIGNED_SIZE(p_hwfn), 1412 &p_phys, GFP_KERNEL); 1413 1414 if (!p_virt) { 1415 kfree(p_sb); 1416 return -ENOMEM; 1417 } 1418 1419 /* Attention setup */ 1420 p_hwfn->p_sb_attn = p_sb; 1421 qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys); 1422 1423 return 0; 1424 } 1425 1426 /* coalescing timeout = timeset << (timer_res + 1) */ 1427 #define QED_CAU_DEF_RX_USECS 24 1428 #define QED_CAU_DEF_TX_USECS 48 1429 1430 void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 1431 struct cau_sb_entry *p_sb_entry, 1432 u8 pf_id, u16 vf_number, u8 vf_valid) 1433 { 1434 struct qed_dev *cdev = p_hwfn->cdev; 1435 u32 cau_state, params = 0, data = 0; 1436 u8 timer_res; 1437 1438 memset(p_sb_entry, 0, sizeof(*p_sb_entry)); 1439 1440 SET_FIELD(params, CAU_SB_ENTRY_PF_NUMBER, pf_id); 1441 SET_FIELD(params, CAU_SB_ENTRY_VF_NUMBER, vf_number); 1442 SET_FIELD(params, CAU_SB_ENTRY_VF_VALID, vf_valid); 1443 SET_FIELD(params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F); 1444 SET_FIELD(params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F); 1445 1446 cau_state = CAU_HC_DISABLE_STATE; 1447 1448 if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1449 cau_state = CAU_HC_ENABLE_STATE; 1450 if (!cdev->rx_coalesce_usecs) 1451 cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS; 1452 if (!cdev->tx_coalesce_usecs) 1453 cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS; 1454 } 1455 1456 /* Coalesce = (timeset << timer-res), timeset is 7bit wide */ 1457 if (cdev->rx_coalesce_usecs <= 0x7F) 1458 timer_res = 0; 1459 else if (cdev->rx_coalesce_usecs <= 0xFF) 1460 timer_res = 1; 1461 else 1462 timer_res = 2; 1463 1464 SET_FIELD(params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 1465 1466 if (cdev->tx_coalesce_usecs <= 0x7F) 1467 timer_res = 0; 1468 else if (cdev->tx_coalesce_usecs <= 0xFF) 1469 timer_res = 1; 1470 else 1471 timer_res = 2; 1472 1473 SET_FIELD(params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 1474 p_sb_entry->params = cpu_to_le32(params); 1475 1476 SET_FIELD(data, CAU_SB_ENTRY_STATE0, cau_state); 1477 SET_FIELD(data, CAU_SB_ENTRY_STATE1, cau_state); 1478 p_sb_entry->data = cpu_to_le32(data); 1479 } 1480 1481 static void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn, 1482 struct qed_ptt *p_ptt, 1483 u16 igu_sb_id, 1484 u32 pi_index, 1485 enum qed_coalescing_fsm coalescing_fsm, 1486 u8 timeset) 1487 { 1488 u32 sb_offset, pi_offset; 1489 u32 prod = 0; 1490 1491 if (IS_VF(p_hwfn->cdev)) 1492 return; 1493 1494 SET_FIELD(prod, CAU_PI_ENTRY_PI_TIMESET, timeset); 1495 if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE) 1496 SET_FIELD(prod, CAU_PI_ENTRY_FSM_SEL, 0); 1497 else 1498 SET_FIELD(prod, CAU_PI_ENTRY_FSM_SEL, 1); 1499 1500 sb_offset = igu_sb_id * PIS_PER_SB_E4; 1501 pi_offset = sb_offset + pi_index; 1502 1503 if (p_hwfn->hw_init_done) 1504 qed_wr(p_hwfn, p_ptt, 1505 CAU_REG_PI_MEMORY + pi_offset * sizeof(u32), prod); 1506 else 1507 STORE_RT_REG(p_hwfn, CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset, 1508 prod); 1509 } 1510 1511 void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 1512 struct qed_ptt *p_ptt, 1513 dma_addr_t sb_phys, 1514 u16 igu_sb_id, u16 vf_number, u8 vf_valid) 1515 { 1516 struct cau_sb_entry sb_entry; 1517 1518 qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id, 1519 vf_number, vf_valid); 1520 1521 if (p_hwfn->hw_init_done) { 1522 /* Wide-bus, initialize via DMAE */ 1523 u64 phys_addr = (u64)sb_phys; 1524 1525 qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr, 1526 CAU_REG_SB_ADDR_MEMORY + 1527 igu_sb_id * sizeof(u64), 2, NULL); 1528 qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry, 1529 CAU_REG_SB_VAR_MEMORY + 1530 igu_sb_id * sizeof(u64), 2, NULL); 1531 } else { 1532 /* Initialize Status Block Address */ 1533 STORE_RT_REG_AGG(p_hwfn, 1534 CAU_REG_SB_ADDR_MEMORY_RT_OFFSET + 1535 igu_sb_id * 2, 1536 sb_phys); 1537 1538 STORE_RT_REG_AGG(p_hwfn, 1539 CAU_REG_SB_VAR_MEMORY_RT_OFFSET + 1540 igu_sb_id * 2, 1541 sb_entry); 1542 } 1543 1544 /* Configure pi coalescing if set */ 1545 if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1546 u8 num_tc = p_hwfn->hw_info.num_hw_tc; 1547 u8 timeset, timer_res; 1548 u8 i; 1549 1550 /* timeset = (coalesce >> timer-res), timeset is 7bit wide */ 1551 if (p_hwfn->cdev->rx_coalesce_usecs <= 0x7F) 1552 timer_res = 0; 1553 else if (p_hwfn->cdev->rx_coalesce_usecs <= 0xFF) 1554 timer_res = 1; 1555 else 1556 timer_res = 2; 1557 timeset = (u8)(p_hwfn->cdev->rx_coalesce_usecs >> timer_res); 1558 qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI, 1559 QED_COAL_RX_STATE_MACHINE, timeset); 1560 1561 if (p_hwfn->cdev->tx_coalesce_usecs <= 0x7F) 1562 timer_res = 0; 1563 else if (p_hwfn->cdev->tx_coalesce_usecs <= 0xFF) 1564 timer_res = 1; 1565 else 1566 timer_res = 2; 1567 timeset = (u8)(p_hwfn->cdev->tx_coalesce_usecs >> timer_res); 1568 for (i = 0; i < num_tc; i++) { 1569 qed_int_cau_conf_pi(p_hwfn, p_ptt, 1570 igu_sb_id, TX_PI(i), 1571 QED_COAL_TX_STATE_MACHINE, 1572 timeset); 1573 } 1574 } 1575 } 1576 1577 void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 1578 struct qed_ptt *p_ptt, struct qed_sb_info *sb_info) 1579 { 1580 /* zero status block and ack counter */ 1581 sb_info->sb_ack = 0; 1582 memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1583 1584 if (IS_PF(p_hwfn->cdev)) 1585 qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys, 1586 sb_info->igu_sb_id, 0, 0); 1587 } 1588 1589 struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn, bool b_is_pf) 1590 { 1591 struct qed_igu_block *p_block; 1592 u16 igu_id; 1593 1594 for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 1595 igu_id++) { 1596 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; 1597 1598 if (!(p_block->status & QED_IGU_STATUS_VALID) || 1599 !(p_block->status & QED_IGU_STATUS_FREE)) 1600 continue; 1601 1602 if (!!(p_block->status & QED_IGU_STATUS_PF) == b_is_pf) 1603 return p_block; 1604 } 1605 1606 return NULL; 1607 } 1608 1609 static u16 qed_get_pf_igu_sb_id(struct qed_hwfn *p_hwfn, u16 vector_id) 1610 { 1611 struct qed_igu_block *p_block; 1612 u16 igu_id; 1613 1614 for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 1615 igu_id++) { 1616 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; 1617 1618 if (!(p_block->status & QED_IGU_STATUS_VALID) || 1619 !p_block->is_pf || 1620 p_block->vector_number != vector_id) 1621 continue; 1622 1623 return igu_id; 1624 } 1625 1626 return QED_SB_INVALID_IDX; 1627 } 1628 1629 u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id) 1630 { 1631 u16 igu_sb_id; 1632 1633 /* Assuming continuous set of IGU SBs dedicated for given PF */ 1634 if (sb_id == QED_SP_SB_ID) 1635 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id; 1636 else if (IS_PF(p_hwfn->cdev)) 1637 igu_sb_id = qed_get_pf_igu_sb_id(p_hwfn, sb_id + 1); 1638 else 1639 igu_sb_id = qed_vf_get_igu_sb_id(p_hwfn, sb_id); 1640 1641 if (sb_id == QED_SP_SB_ID) 1642 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1643 "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id); 1644 else 1645 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1646 "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id); 1647 1648 return igu_sb_id; 1649 } 1650 1651 int qed_int_sb_init(struct qed_hwfn *p_hwfn, 1652 struct qed_ptt *p_ptt, 1653 struct qed_sb_info *sb_info, 1654 void *sb_virt_addr, dma_addr_t sb_phy_addr, u16 sb_id) 1655 { 1656 sb_info->sb_virt = sb_virt_addr; 1657 sb_info->sb_phys = sb_phy_addr; 1658 1659 sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id); 1660 1661 if (sb_id != QED_SP_SB_ID) { 1662 if (IS_PF(p_hwfn->cdev)) { 1663 struct qed_igu_info *p_info; 1664 struct qed_igu_block *p_block; 1665 1666 p_info = p_hwfn->hw_info.p_igu_info; 1667 p_block = &p_info->entry[sb_info->igu_sb_id]; 1668 1669 p_block->sb_info = sb_info; 1670 p_block->status &= ~QED_IGU_STATUS_FREE; 1671 p_info->usage.free_cnt--; 1672 } else { 1673 qed_vf_set_sb_info(p_hwfn, sb_id, sb_info); 1674 } 1675 } 1676 1677 sb_info->cdev = p_hwfn->cdev; 1678 1679 /* The igu address will hold the absolute address that needs to be 1680 * written to for a specific status block 1681 */ 1682 if (IS_PF(p_hwfn->cdev)) { 1683 sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 1684 GTT_BAR0_MAP_REG_IGU_CMD + 1685 (sb_info->igu_sb_id << 3); 1686 } else { 1687 sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 1688 PXP_VF_BAR0_START_IGU + 1689 ((IGU_CMD_INT_ACK_BASE + 1690 sb_info->igu_sb_id) << 3); 1691 } 1692 1693 sb_info->flags |= QED_SB_INFO_INIT; 1694 1695 qed_int_sb_setup(p_hwfn, p_ptt, sb_info); 1696 1697 return 0; 1698 } 1699 1700 int qed_int_sb_release(struct qed_hwfn *p_hwfn, 1701 struct qed_sb_info *sb_info, u16 sb_id) 1702 { 1703 struct qed_igu_block *p_block; 1704 struct qed_igu_info *p_info; 1705 1706 if (!sb_info) 1707 return 0; 1708 1709 /* zero status block and ack counter */ 1710 sb_info->sb_ack = 0; 1711 memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1712 1713 if (IS_VF(p_hwfn->cdev)) { 1714 qed_vf_set_sb_info(p_hwfn, sb_id, NULL); 1715 return 0; 1716 } 1717 1718 p_info = p_hwfn->hw_info.p_igu_info; 1719 p_block = &p_info->entry[sb_info->igu_sb_id]; 1720 1721 /* Vector 0 is reserved to Default SB */ 1722 if (!p_block->vector_number) { 1723 DP_ERR(p_hwfn, "Do Not free sp sb using this function"); 1724 return -EINVAL; 1725 } 1726 1727 /* Lose reference to client's SB info, and fix counters */ 1728 p_block->sb_info = NULL; 1729 p_block->status |= QED_IGU_STATUS_FREE; 1730 p_info->usage.free_cnt++; 1731 1732 return 0; 1733 } 1734 1735 static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn) 1736 { 1737 struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb; 1738 1739 if (!p_sb) 1740 return; 1741 1742 if (p_sb->sb_info.sb_virt) 1743 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1744 SB_ALIGNED_SIZE(p_hwfn), 1745 p_sb->sb_info.sb_virt, 1746 p_sb->sb_info.sb_phys); 1747 kfree(p_sb); 1748 p_hwfn->p_sp_sb = NULL; 1749 } 1750 1751 static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1752 { 1753 struct qed_sb_sp_info *p_sb; 1754 dma_addr_t p_phys = 0; 1755 void *p_virt; 1756 1757 /* SB struct */ 1758 p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 1759 if (!p_sb) 1760 return -ENOMEM; 1761 1762 /* SB ring */ 1763 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1764 SB_ALIGNED_SIZE(p_hwfn), 1765 &p_phys, GFP_KERNEL); 1766 if (!p_virt) { 1767 kfree(p_sb); 1768 return -ENOMEM; 1769 } 1770 1771 /* Status Block setup */ 1772 p_hwfn->p_sp_sb = p_sb; 1773 qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt, 1774 p_phys, QED_SP_SB_ID); 1775 1776 memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr)); 1777 1778 return 0; 1779 } 1780 1781 int qed_int_register_cb(struct qed_hwfn *p_hwfn, 1782 qed_int_comp_cb_t comp_cb, 1783 void *cookie, u8 *sb_idx, __le16 **p_fw_cons) 1784 { 1785 struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 1786 int rc = -ENOMEM; 1787 u8 pi; 1788 1789 /* Look for a free index */ 1790 for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) { 1791 if (p_sp_sb->pi_info_arr[pi].comp_cb) 1792 continue; 1793 1794 p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb; 1795 p_sp_sb->pi_info_arr[pi].cookie = cookie; 1796 *sb_idx = pi; 1797 *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi]; 1798 rc = 0; 1799 break; 1800 } 1801 1802 return rc; 1803 } 1804 1805 int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi) 1806 { 1807 struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 1808 1809 if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL) 1810 return -ENOMEM; 1811 1812 p_sp_sb->pi_info_arr[pi].comp_cb = NULL; 1813 p_sp_sb->pi_info_arr[pi].cookie = NULL; 1814 1815 return 0; 1816 } 1817 1818 u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn) 1819 { 1820 return p_hwfn->p_sp_sb->sb_info.igu_sb_id; 1821 } 1822 1823 void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 1824 struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 1825 { 1826 u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN; 1827 1828 p_hwfn->cdev->int_mode = int_mode; 1829 switch (p_hwfn->cdev->int_mode) { 1830 case QED_INT_MODE_INTA: 1831 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN; 1832 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1833 break; 1834 1835 case QED_INT_MODE_MSI: 1836 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1837 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1838 break; 1839 1840 case QED_INT_MODE_MSIX: 1841 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1842 break; 1843 case QED_INT_MODE_POLL: 1844 break; 1845 } 1846 1847 qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf); 1848 } 1849 1850 static void qed_int_igu_enable_attn(struct qed_hwfn *p_hwfn, 1851 struct qed_ptt *p_ptt) 1852 { 1853 1854 /* Configure AEU signal change to produce attentions */ 1855 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0); 1856 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff); 1857 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff); 1858 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff); 1859 1860 /* Unmask AEU signals toward IGU */ 1861 qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff); 1862 } 1863 1864 int 1865 qed_int_igu_enable(struct qed_hwfn *p_hwfn, 1866 struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 1867 { 1868 int rc = 0; 1869 1870 qed_int_igu_enable_attn(p_hwfn, p_ptt); 1871 1872 if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) { 1873 rc = qed_slowpath_irq_req(p_hwfn); 1874 if (rc) { 1875 DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n"); 1876 return -EINVAL; 1877 } 1878 p_hwfn->b_int_requested = true; 1879 } 1880 /* Enable interrupt Generation */ 1881 qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode); 1882 p_hwfn->b_int_enabled = 1; 1883 1884 return rc; 1885 } 1886 1887 void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1888 { 1889 p_hwfn->b_int_enabled = 0; 1890 1891 if (IS_VF(p_hwfn->cdev)) 1892 return; 1893 1894 qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0); 1895 } 1896 1897 #define IGU_CLEANUP_SLEEP_LENGTH (1000) 1898 static void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn, 1899 struct qed_ptt *p_ptt, 1900 u16 igu_sb_id, 1901 bool cleanup_set, u16 opaque_fid) 1902 { 1903 u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0; 1904 u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id; 1905 u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH; 1906 1907 /* Set the data field */ 1908 SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0); 1909 SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0); 1910 SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET); 1911 1912 /* Set the control register */ 1913 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr); 1914 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid); 1915 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR); 1916 1917 qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data); 1918 1919 barrier(); 1920 1921 qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl); 1922 1923 /* calculate where to read the status bit from */ 1924 sb_bit = 1 << (igu_sb_id % 32); 1925 sb_bit_addr = igu_sb_id / 32 * sizeof(u32); 1926 1927 sb_bit_addr += IGU_REG_CLEANUP_STATUS_0; 1928 1929 /* Now wait for the command to complete */ 1930 do { 1931 val = qed_rd(p_hwfn, p_ptt, sb_bit_addr); 1932 1933 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0)) 1934 break; 1935 1936 usleep_range(5000, 10000); 1937 } while (--sleep_cnt); 1938 1939 if (!sleep_cnt) 1940 DP_NOTICE(p_hwfn, 1941 "Timeout waiting for clear status 0x%08x [for sb %d]\n", 1942 val, igu_sb_id); 1943 } 1944 1945 void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 1946 struct qed_ptt *p_ptt, 1947 u16 igu_sb_id, u16 opaque, bool b_set) 1948 { 1949 struct qed_igu_block *p_block; 1950 int pi, i; 1951 1952 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; 1953 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1954 "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n", 1955 igu_sb_id, 1956 p_block->function_id, 1957 p_block->is_pf, p_block->vector_number); 1958 1959 /* Set */ 1960 if (b_set) 1961 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque); 1962 1963 /* Clear */ 1964 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque); 1965 1966 /* Wait for the IGU SB to cleanup */ 1967 for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) { 1968 u32 val; 1969 1970 val = qed_rd(p_hwfn, p_ptt, 1971 IGU_REG_WRITE_DONE_PENDING + 1972 ((igu_sb_id / 32) * 4)); 1973 if (val & BIT((igu_sb_id % 32))) 1974 usleep_range(10, 20); 1975 else 1976 break; 1977 } 1978 if (i == IGU_CLEANUP_SLEEP_LENGTH) 1979 DP_NOTICE(p_hwfn, 1980 "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n", 1981 igu_sb_id); 1982 1983 /* Clear the CAU for the SB */ 1984 for (pi = 0; pi < 12; pi++) 1985 qed_wr(p_hwfn, p_ptt, 1986 CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0); 1987 } 1988 1989 void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 1990 struct qed_ptt *p_ptt, 1991 bool b_set, bool b_slowpath) 1992 { 1993 struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 1994 struct qed_igu_block *p_block; 1995 u16 igu_sb_id = 0; 1996 u32 val = 0; 1997 1998 val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION); 1999 val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN; 2000 val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN; 2001 qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val); 2002 2003 for (igu_sb_id = 0; 2004 igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 2005 p_block = &p_info->entry[igu_sb_id]; 2006 2007 if (!(p_block->status & QED_IGU_STATUS_VALID) || 2008 !p_block->is_pf || 2009 (p_block->status & QED_IGU_STATUS_DSB)) 2010 continue; 2011 2012 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id, 2013 p_hwfn->hw_info.opaque_fid, 2014 b_set); 2015 } 2016 2017 if (b_slowpath) 2018 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, 2019 p_info->igu_dsb_id, 2020 p_hwfn->hw_info.opaque_fid, 2021 b_set); 2022 } 2023 2024 int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2025 { 2026 struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 2027 struct qed_igu_block *p_block; 2028 int pf_sbs, vf_sbs; 2029 u16 igu_sb_id; 2030 u32 val, rval; 2031 2032 if (!RESC_NUM(p_hwfn, QED_SB)) { 2033 p_info->b_allow_pf_vf_change = false; 2034 } else { 2035 /* Use the numbers the MFW have provided - 2036 * don't forget MFW accounts for the default SB as well. 2037 */ 2038 p_info->b_allow_pf_vf_change = true; 2039 2040 if (p_info->usage.cnt != RESC_NUM(p_hwfn, QED_SB) - 1) { 2041 DP_INFO(p_hwfn, 2042 "MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n", 2043 RESC_NUM(p_hwfn, QED_SB) - 1, 2044 p_info->usage.cnt); 2045 p_info->usage.cnt = RESC_NUM(p_hwfn, QED_SB) - 1; 2046 } 2047 2048 if (IS_PF_SRIOV(p_hwfn)) { 2049 u16 vfs = p_hwfn->cdev->p_iov_info->total_vfs; 2050 2051 if (vfs != p_info->usage.iov_cnt) 2052 DP_VERBOSE(p_hwfn, 2053 NETIF_MSG_INTR, 2054 "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n", 2055 p_info->usage.iov_cnt, vfs); 2056 2057 /* At this point we know how many SBs we have totally 2058 * in IGU + number of PF SBs. So we can validate that 2059 * we'd have sufficient for VF. 2060 */ 2061 if (vfs > p_info->usage.free_cnt + 2062 p_info->usage.free_cnt_iov - p_info->usage.cnt) { 2063 DP_NOTICE(p_hwfn, 2064 "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n", 2065 p_info->usage.free_cnt + 2066 p_info->usage.free_cnt_iov, 2067 p_info->usage.cnt, vfs); 2068 return -EINVAL; 2069 } 2070 2071 /* Currently cap the number of VFs SBs by the 2072 * number of VFs. 2073 */ 2074 p_info->usage.iov_cnt = vfs; 2075 } 2076 } 2077 2078 /* Mark all SBs as free, now in the right PF/VFs division */ 2079 p_info->usage.free_cnt = p_info->usage.cnt; 2080 p_info->usage.free_cnt_iov = p_info->usage.iov_cnt; 2081 p_info->usage.orig = p_info->usage.cnt; 2082 p_info->usage.iov_orig = p_info->usage.iov_cnt; 2083 2084 /* We now proceed to re-configure the IGU cam to reflect the initial 2085 * configuration. We can start with the Default SB. 2086 */ 2087 pf_sbs = p_info->usage.cnt; 2088 vf_sbs = p_info->usage.iov_cnt; 2089 2090 for (igu_sb_id = p_info->igu_dsb_id; 2091 igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 2092 p_block = &p_info->entry[igu_sb_id]; 2093 val = 0; 2094 2095 if (!(p_block->status & QED_IGU_STATUS_VALID)) 2096 continue; 2097 2098 if (p_block->status & QED_IGU_STATUS_DSB) { 2099 p_block->function_id = p_hwfn->rel_pf_id; 2100 p_block->is_pf = 1; 2101 p_block->vector_number = 0; 2102 p_block->status = QED_IGU_STATUS_VALID | 2103 QED_IGU_STATUS_PF | 2104 QED_IGU_STATUS_DSB; 2105 } else if (pf_sbs) { 2106 pf_sbs--; 2107 p_block->function_id = p_hwfn->rel_pf_id; 2108 p_block->is_pf = 1; 2109 p_block->vector_number = p_info->usage.cnt - pf_sbs; 2110 p_block->status = QED_IGU_STATUS_VALID | 2111 QED_IGU_STATUS_PF | 2112 QED_IGU_STATUS_FREE; 2113 } else if (vf_sbs) { 2114 p_block->function_id = 2115 p_hwfn->cdev->p_iov_info->first_vf_in_pf + 2116 p_info->usage.iov_cnt - vf_sbs; 2117 p_block->is_pf = 0; 2118 p_block->vector_number = 0; 2119 p_block->status = QED_IGU_STATUS_VALID | 2120 QED_IGU_STATUS_FREE; 2121 vf_sbs--; 2122 } else { 2123 p_block->function_id = 0; 2124 p_block->is_pf = 0; 2125 p_block->vector_number = 0; 2126 } 2127 2128 SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER, 2129 p_block->function_id); 2130 SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf); 2131 SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER, 2132 p_block->vector_number); 2133 2134 /* VF entries would be enabled when VF is initializaed */ 2135 SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf); 2136 2137 rval = qed_rd(p_hwfn, p_ptt, 2138 IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id); 2139 2140 if (rval != val) { 2141 qed_wr(p_hwfn, p_ptt, 2142 IGU_REG_MAPPING_MEMORY + 2143 sizeof(u32) * igu_sb_id, val); 2144 2145 DP_VERBOSE(p_hwfn, 2146 NETIF_MSG_INTR, 2147 "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n", 2148 igu_sb_id, 2149 p_block->function_id, 2150 p_block->is_pf, 2151 p_block->vector_number, rval, val); 2152 } 2153 } 2154 2155 return 0; 2156 } 2157 2158 static void qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn, 2159 struct qed_ptt *p_ptt, u16 igu_sb_id) 2160 { 2161 u32 val = qed_rd(p_hwfn, p_ptt, 2162 IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id); 2163 struct qed_igu_block *p_block; 2164 2165 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; 2166 2167 /* Fill the block information */ 2168 p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER); 2169 p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID); 2170 p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER); 2171 p_block->igu_sb_id = igu_sb_id; 2172 } 2173 2174 int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2175 { 2176 struct qed_igu_info *p_igu_info; 2177 struct qed_igu_block *p_block; 2178 u32 min_vf = 0, max_vf = 0; 2179 u16 igu_sb_id; 2180 2181 p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL); 2182 if (!p_hwfn->hw_info.p_igu_info) 2183 return -ENOMEM; 2184 2185 p_igu_info = p_hwfn->hw_info.p_igu_info; 2186 2187 /* Distinguish between existent and non-existent default SB */ 2188 p_igu_info->igu_dsb_id = QED_SB_INVALID_IDX; 2189 2190 /* Find the range of VF ids whose SB belong to this PF */ 2191 if (p_hwfn->cdev->p_iov_info) { 2192 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 2193 2194 min_vf = p_iov->first_vf_in_pf; 2195 max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs; 2196 } 2197 2198 for (igu_sb_id = 0; 2199 igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 2200 /* Read current entry; Notice it might not belong to this PF */ 2201 qed_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id); 2202 p_block = &p_igu_info->entry[igu_sb_id]; 2203 2204 if ((p_block->is_pf) && 2205 (p_block->function_id == p_hwfn->rel_pf_id)) { 2206 p_block->status = QED_IGU_STATUS_PF | 2207 QED_IGU_STATUS_VALID | 2208 QED_IGU_STATUS_FREE; 2209 2210 if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX) 2211 p_igu_info->usage.cnt++; 2212 } else if (!(p_block->is_pf) && 2213 (p_block->function_id >= min_vf) && 2214 (p_block->function_id < max_vf)) { 2215 /* Available for VFs of this PF */ 2216 p_block->status = QED_IGU_STATUS_VALID | 2217 QED_IGU_STATUS_FREE; 2218 2219 if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX) 2220 p_igu_info->usage.iov_cnt++; 2221 } 2222 2223 /* Mark the First entry belonging to the PF or its VFs 2224 * as the default SB [we'll reset IGU prior to first usage]. 2225 */ 2226 if ((p_block->status & QED_IGU_STATUS_VALID) && 2227 (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX)) { 2228 p_igu_info->igu_dsb_id = igu_sb_id; 2229 p_block->status |= QED_IGU_STATUS_DSB; 2230 } 2231 2232 /* limit number of prints by having each PF print only its 2233 * entries with the exception of PF0 which would print 2234 * everything. 2235 */ 2236 if ((p_block->status & QED_IGU_STATUS_VALID) || 2237 (p_hwfn->abs_pf_id == 0)) { 2238 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2239 "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n", 2240 igu_sb_id, p_block->function_id, 2241 p_block->is_pf, p_block->vector_number); 2242 } 2243 } 2244 2245 if (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX) { 2246 DP_NOTICE(p_hwfn, 2247 "IGU CAM returned invalid values igu_dsb_id=0x%x\n", 2248 p_igu_info->igu_dsb_id); 2249 return -EINVAL; 2250 } 2251 2252 /* All non default SB are considered free at this point */ 2253 p_igu_info->usage.free_cnt = p_igu_info->usage.cnt; 2254 p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt; 2255 2256 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2257 "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n", 2258 p_igu_info->igu_dsb_id, 2259 p_igu_info->usage.cnt, p_igu_info->usage.iov_cnt); 2260 2261 return 0; 2262 } 2263 2264 /** 2265 * qed_int_igu_init_rt() - Initialize IGU runtime registers. 2266 * 2267 * @p_hwfn: HW device data. 2268 */ 2269 void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn) 2270 { 2271 u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN; 2272 2273 STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf); 2274 } 2275 2276 u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn) 2277 { 2278 u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - 2279 IGU_CMD_INT_ACK_BASE; 2280 u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - 2281 IGU_CMD_INT_ACK_BASE; 2282 u32 intr_status_hi = 0, intr_status_lo = 0; 2283 u64 intr_status = 0; 2284 2285 intr_status_lo = REG_RD(p_hwfn, 2286 GTT_BAR0_MAP_REG_IGU_CMD + 2287 lsb_igu_cmd_addr * 8); 2288 intr_status_hi = REG_RD(p_hwfn, 2289 GTT_BAR0_MAP_REG_IGU_CMD + 2290 msb_igu_cmd_addr * 8); 2291 intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo; 2292 2293 return intr_status; 2294 } 2295 2296 static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn) 2297 { 2298 tasklet_setup(&p_hwfn->sp_dpc, qed_int_sp_dpc); 2299 p_hwfn->b_sp_dpc_enabled = true; 2300 } 2301 2302 int qed_int_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2303 { 2304 int rc = 0; 2305 2306 rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt); 2307 if (rc) 2308 return rc; 2309 2310 rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt); 2311 2312 return rc; 2313 } 2314 2315 void qed_int_free(struct qed_hwfn *p_hwfn) 2316 { 2317 qed_int_sp_sb_free(p_hwfn); 2318 qed_int_sb_attn_free(p_hwfn); 2319 } 2320 2321 void qed_int_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2322 { 2323 qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info); 2324 qed_int_sb_attn_setup(p_hwfn, p_ptt); 2325 qed_int_sp_dpc_setup(p_hwfn); 2326 } 2327 2328 void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 2329 struct qed_sb_cnt_info *p_sb_cnt_info) 2330 { 2331 struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info; 2332 2333 if (!info || !p_sb_cnt_info) 2334 return; 2335 2336 memcpy(p_sb_cnt_info, &info->usage, sizeof(*p_sb_cnt_info)); 2337 } 2338 2339 void qed_int_disable_post_isr_release(struct qed_dev *cdev) 2340 { 2341 int i; 2342 2343 for_each_hwfn(cdev, i) 2344 cdev->hwfns[i].b_int_requested = false; 2345 } 2346 2347 void qed_int_attn_clr_enable(struct qed_dev *cdev, bool clr_enable) 2348 { 2349 cdev->attn_clr_en = clr_enable; 2350 } 2351 2352 int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2353 u8 timer_res, u16 sb_id, bool tx) 2354 { 2355 struct cau_sb_entry sb_entry; 2356 u32 params; 2357 int rc; 2358 2359 if (!p_hwfn->hw_init_done) { 2360 DP_ERR(p_hwfn, "hardware not initialized yet\n"); 2361 return -EINVAL; 2362 } 2363 2364 rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + 2365 sb_id * sizeof(u64), 2366 (u64)(uintptr_t)&sb_entry, 2, NULL); 2367 if (rc) { 2368 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); 2369 return rc; 2370 } 2371 2372 params = le32_to_cpu(sb_entry.params); 2373 2374 if (tx) 2375 SET_FIELD(params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 2376 else 2377 SET_FIELD(params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 2378 2379 sb_entry.params = cpu_to_le32(params); 2380 2381 rc = qed_dmae_host2grc(p_hwfn, p_ptt, 2382 (u64)(uintptr_t)&sb_entry, 2383 CAU_REG_SB_VAR_MEMORY + 2384 sb_id * sizeof(u64), 2, NULL); 2385 if (rc) { 2386 DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc); 2387 return rc; 2388 } 2389 2390 return rc; 2391 } 2392