1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2fe56b9e6SYuval Mintz * Copyright (c) 2015 QLogic Corporation 3fe56b9e6SYuval Mintz * 4fe56b9e6SYuval Mintz * This software is available under the terms of the GNU General Public License 5fe56b9e6SYuval Mintz * (GPL) Version 2, available from the file COPYING in the main directory of 6fe56b9e6SYuval Mintz * this source tree. 7fe56b9e6SYuval Mintz */ 8fe56b9e6SYuval Mintz 9fe56b9e6SYuval Mintz #include <linux/types.h> 10fe56b9e6SYuval Mintz #include <linux/io.h> 11fe56b9e6SYuval Mintz #include <linux/delay.h> 12fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 13fe56b9e6SYuval Mintz #include <linux/errno.h> 14fe56b9e6SYuval Mintz #include <linux/kernel.h> 15fe56b9e6SYuval Mintz #include <linux/list.h> 16fe56b9e6SYuval Mintz #include <linux/mutex.h> 17fe56b9e6SYuval Mintz #include <linux/pci.h> 18fe56b9e6SYuval Mintz #include <linux/slab.h> 19fe56b9e6SYuval Mintz #include <linux/spinlock.h> 20fe56b9e6SYuval Mintz #include <linux/string.h> 21fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h> 22fe56b9e6SYuval Mintz #include "qed.h" 23fe56b9e6SYuval Mintz #include "qed_hsi.h" 24fe56b9e6SYuval Mintz #include "qed_hw.h" 25fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 261408cc1fSYuval Mintz #include "qed_sriov.h" 27fe56b9e6SYuval Mintz 28fe56b9e6SYuval Mintz #define QED_BAR_ACQUIRE_TIMEOUT 1000 29fe56b9e6SYuval Mintz 30fe56b9e6SYuval Mintz /* Invalid values */ 31fe56b9e6SYuval Mintz #define QED_BAR_INVALID_OFFSET (cpu_to_le32(-1)) 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz struct qed_ptt { 34fe56b9e6SYuval Mintz struct list_head list_entry; 35fe56b9e6SYuval Mintz unsigned int idx; 36fe56b9e6SYuval Mintz struct pxp_ptt_entry pxp; 37fe56b9e6SYuval Mintz }; 38fe56b9e6SYuval Mintz 39fe56b9e6SYuval Mintz struct qed_ptt_pool { 40fe56b9e6SYuval Mintz struct list_head free_list; 41fe56b9e6SYuval Mintz spinlock_t lock; /* ptt synchronized access */ 42fe56b9e6SYuval Mintz struct qed_ptt ptts[PXP_EXTERNAL_BAR_PF_WINDOW_NUM]; 43fe56b9e6SYuval Mintz }; 44fe56b9e6SYuval Mintz 45fe56b9e6SYuval Mintz int qed_ptt_pool_alloc(struct qed_hwfn *p_hwfn) 46fe56b9e6SYuval Mintz { 47*1a635e48SYuval Mintz struct qed_ptt_pool *p_pool = kmalloc(sizeof(*p_pool), GFP_KERNEL); 48fe56b9e6SYuval Mintz int i; 49fe56b9e6SYuval Mintz 50fe56b9e6SYuval Mintz if (!p_pool) 51fe56b9e6SYuval Mintz return -ENOMEM; 52fe56b9e6SYuval Mintz 53fe56b9e6SYuval Mintz INIT_LIST_HEAD(&p_pool->free_list); 54fe56b9e6SYuval Mintz for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) { 55fe56b9e6SYuval Mintz p_pool->ptts[i].idx = i; 56fe56b9e6SYuval Mintz p_pool->ptts[i].pxp.offset = QED_BAR_INVALID_OFFSET; 57fe56b9e6SYuval Mintz p_pool->ptts[i].pxp.pretend.control = 0; 58fe56b9e6SYuval Mintz if (i >= RESERVED_PTT_MAX) 59fe56b9e6SYuval Mintz list_add(&p_pool->ptts[i].list_entry, 60fe56b9e6SYuval Mintz &p_pool->free_list); 61fe56b9e6SYuval Mintz } 62fe56b9e6SYuval Mintz 63fe56b9e6SYuval Mintz p_hwfn->p_ptt_pool = p_pool; 64fe56b9e6SYuval Mintz spin_lock_init(&p_pool->lock); 65fe56b9e6SYuval Mintz 66fe56b9e6SYuval Mintz return 0; 67fe56b9e6SYuval Mintz } 68fe56b9e6SYuval Mintz 69fe56b9e6SYuval Mintz void qed_ptt_invalidate(struct qed_hwfn *p_hwfn) 70fe56b9e6SYuval Mintz { 71fe56b9e6SYuval Mintz struct qed_ptt *p_ptt; 72fe56b9e6SYuval Mintz int i; 73fe56b9e6SYuval Mintz 74fe56b9e6SYuval Mintz for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) { 75fe56b9e6SYuval Mintz p_ptt = &p_hwfn->p_ptt_pool->ptts[i]; 76fe56b9e6SYuval Mintz p_ptt->pxp.offset = QED_BAR_INVALID_OFFSET; 77fe56b9e6SYuval Mintz } 78fe56b9e6SYuval Mintz } 79fe56b9e6SYuval Mintz 80fe56b9e6SYuval Mintz void qed_ptt_pool_free(struct qed_hwfn *p_hwfn) 81fe56b9e6SYuval Mintz { 82fe56b9e6SYuval Mintz kfree(p_hwfn->p_ptt_pool); 83fe56b9e6SYuval Mintz p_hwfn->p_ptt_pool = NULL; 84fe56b9e6SYuval Mintz } 85fe56b9e6SYuval Mintz 86fe56b9e6SYuval Mintz struct qed_ptt *qed_ptt_acquire(struct qed_hwfn *p_hwfn) 87fe56b9e6SYuval Mintz { 88fe56b9e6SYuval Mintz struct qed_ptt *p_ptt; 89fe56b9e6SYuval Mintz unsigned int i; 90fe56b9e6SYuval Mintz 91fe56b9e6SYuval Mintz /* Take the free PTT from the list */ 92fe56b9e6SYuval Mintz for (i = 0; i < QED_BAR_ACQUIRE_TIMEOUT; i++) { 93fe56b9e6SYuval Mintz spin_lock_bh(&p_hwfn->p_ptt_pool->lock); 94fe56b9e6SYuval Mintz 95fe56b9e6SYuval Mintz if (!list_empty(&p_hwfn->p_ptt_pool->free_list)) { 96fe56b9e6SYuval Mintz p_ptt = list_first_entry(&p_hwfn->p_ptt_pool->free_list, 97fe56b9e6SYuval Mintz struct qed_ptt, list_entry); 98fe56b9e6SYuval Mintz list_del(&p_ptt->list_entry); 99fe56b9e6SYuval Mintz 100fe56b9e6SYuval Mintz spin_unlock_bh(&p_hwfn->p_ptt_pool->lock); 101fe56b9e6SYuval Mintz 102fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 103fe56b9e6SYuval Mintz "allocated ptt %d\n", p_ptt->idx); 104fe56b9e6SYuval Mintz return p_ptt; 105fe56b9e6SYuval Mintz } 106fe56b9e6SYuval Mintz 107fe56b9e6SYuval Mintz spin_unlock_bh(&p_hwfn->p_ptt_pool->lock); 108fe56b9e6SYuval Mintz usleep_range(1000, 2000); 109fe56b9e6SYuval Mintz } 110fe56b9e6SYuval Mintz 111fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "PTT acquire timeout - failed to allocate PTT\n"); 112fe56b9e6SYuval Mintz return NULL; 113fe56b9e6SYuval Mintz } 114fe56b9e6SYuval Mintz 115*1a635e48SYuval Mintz void qed_ptt_release(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 116fe56b9e6SYuval Mintz { 117fe56b9e6SYuval Mintz spin_lock_bh(&p_hwfn->p_ptt_pool->lock); 118fe56b9e6SYuval Mintz list_add(&p_ptt->list_entry, &p_hwfn->p_ptt_pool->free_list); 119fe56b9e6SYuval Mintz spin_unlock_bh(&p_hwfn->p_ptt_pool->lock); 120fe56b9e6SYuval Mintz } 121fe56b9e6SYuval Mintz 122*1a635e48SYuval Mintz u32 qed_ptt_get_hw_addr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 123fe56b9e6SYuval Mintz { 124fe56b9e6SYuval Mintz /* The HW is using DWORDS and we need to translate it to Bytes */ 125fe56b9e6SYuval Mintz return le32_to_cpu(p_ptt->pxp.offset) << 2; 126fe56b9e6SYuval Mintz } 127fe56b9e6SYuval Mintz 128fe56b9e6SYuval Mintz static u32 qed_ptt_config_addr(struct qed_ptt *p_ptt) 129fe56b9e6SYuval Mintz { 130fe56b9e6SYuval Mintz return PXP_PF_WINDOW_ADMIN_PER_PF_START + 131fe56b9e6SYuval Mintz p_ptt->idx * sizeof(struct pxp_ptt_entry); 132fe56b9e6SYuval Mintz } 133fe56b9e6SYuval Mintz 134fe56b9e6SYuval Mintz u32 qed_ptt_get_bar_addr(struct qed_ptt *p_ptt) 135fe56b9e6SYuval Mintz { 136fe56b9e6SYuval Mintz return PXP_EXTERNAL_BAR_PF_WINDOW_START + 137fe56b9e6SYuval Mintz p_ptt->idx * PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE; 138fe56b9e6SYuval Mintz } 139fe56b9e6SYuval Mintz 140fe56b9e6SYuval Mintz void qed_ptt_set_win(struct qed_hwfn *p_hwfn, 141*1a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 new_hw_addr) 142fe56b9e6SYuval Mintz { 143fe56b9e6SYuval Mintz u32 prev_hw_addr; 144fe56b9e6SYuval Mintz 145fe56b9e6SYuval Mintz prev_hw_addr = qed_ptt_get_hw_addr(p_hwfn, p_ptt); 146fe56b9e6SYuval Mintz 147fe56b9e6SYuval Mintz if (new_hw_addr == prev_hw_addr) 148fe56b9e6SYuval Mintz return; 149fe56b9e6SYuval Mintz 150fe56b9e6SYuval Mintz /* Update PTT entery in admin window */ 151fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 152fe56b9e6SYuval Mintz "Updating PTT entry %d to offset 0x%x\n", 153fe56b9e6SYuval Mintz p_ptt->idx, new_hw_addr); 154fe56b9e6SYuval Mintz 155fe56b9e6SYuval Mintz /* The HW is using DWORDS and the address is in Bytes */ 156fe56b9e6SYuval Mintz p_ptt->pxp.offset = cpu_to_le32(new_hw_addr >> 2); 157fe56b9e6SYuval Mintz 158fe56b9e6SYuval Mintz REG_WR(p_hwfn, 159fe56b9e6SYuval Mintz qed_ptt_config_addr(p_ptt) + 160fe56b9e6SYuval Mintz offsetof(struct pxp_ptt_entry, offset), 161fe56b9e6SYuval Mintz le32_to_cpu(p_ptt->pxp.offset)); 162fe56b9e6SYuval Mintz } 163fe56b9e6SYuval Mintz 164fe56b9e6SYuval Mintz static u32 qed_set_ptt(struct qed_hwfn *p_hwfn, 165*1a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 hw_addr) 166fe56b9e6SYuval Mintz { 167fe56b9e6SYuval Mintz u32 win_hw_addr = qed_ptt_get_hw_addr(p_hwfn, p_ptt); 168fe56b9e6SYuval Mintz u32 offset; 169fe56b9e6SYuval Mintz 170fe56b9e6SYuval Mintz offset = hw_addr - win_hw_addr; 171fe56b9e6SYuval Mintz 172fe56b9e6SYuval Mintz /* Verify the address is within the window */ 173fe56b9e6SYuval Mintz if (hw_addr < win_hw_addr || 174fe56b9e6SYuval Mintz offset >= PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) { 175fe56b9e6SYuval Mintz qed_ptt_set_win(p_hwfn, p_ptt, hw_addr); 176fe56b9e6SYuval Mintz offset = 0; 177fe56b9e6SYuval Mintz } 178fe56b9e6SYuval Mintz 179fe56b9e6SYuval Mintz return qed_ptt_get_bar_addr(p_ptt) + offset; 180fe56b9e6SYuval Mintz } 181fe56b9e6SYuval Mintz 182fe56b9e6SYuval Mintz struct qed_ptt *qed_get_reserved_ptt(struct qed_hwfn *p_hwfn, 183fe56b9e6SYuval Mintz enum reserved_ptts ptt_idx) 184fe56b9e6SYuval Mintz { 185fe56b9e6SYuval Mintz if (ptt_idx >= RESERVED_PTT_MAX) { 186fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 187fe56b9e6SYuval Mintz "Requested PTT %d is out of range\n", ptt_idx); 188fe56b9e6SYuval Mintz return NULL; 189fe56b9e6SYuval Mintz } 190fe56b9e6SYuval Mintz 191fe56b9e6SYuval Mintz return &p_hwfn->p_ptt_pool->ptts[ptt_idx]; 192fe56b9e6SYuval Mintz } 193fe56b9e6SYuval Mintz 194fe56b9e6SYuval Mintz void qed_wr(struct qed_hwfn *p_hwfn, 195fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 196fe56b9e6SYuval Mintz u32 hw_addr, u32 val) 197fe56b9e6SYuval Mintz { 198fe56b9e6SYuval Mintz u32 bar_addr = qed_set_ptt(p_hwfn, p_ptt, hw_addr); 199fe56b9e6SYuval Mintz 200fe56b9e6SYuval Mintz REG_WR(p_hwfn, bar_addr, val); 201fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 202fe56b9e6SYuval Mintz "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n", 203fe56b9e6SYuval Mintz bar_addr, hw_addr, val); 204fe56b9e6SYuval Mintz } 205fe56b9e6SYuval Mintz 206fe56b9e6SYuval Mintz u32 qed_rd(struct qed_hwfn *p_hwfn, 207fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 208fe56b9e6SYuval Mintz u32 hw_addr) 209fe56b9e6SYuval Mintz { 210fe56b9e6SYuval Mintz u32 bar_addr = qed_set_ptt(p_hwfn, p_ptt, hw_addr); 211fe56b9e6SYuval Mintz u32 val = REG_RD(p_hwfn, bar_addr); 212fe56b9e6SYuval Mintz 213fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 214fe56b9e6SYuval Mintz "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n", 215fe56b9e6SYuval Mintz bar_addr, hw_addr, val); 216fe56b9e6SYuval Mintz 217fe56b9e6SYuval Mintz return val; 218fe56b9e6SYuval Mintz } 219fe56b9e6SYuval Mintz 220fe56b9e6SYuval Mintz static void qed_memcpy_hw(struct qed_hwfn *p_hwfn, 221fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 222*1a635e48SYuval Mintz void *addr, u32 hw_addr, size_t n, bool to_device) 223fe56b9e6SYuval Mintz { 224fe56b9e6SYuval Mintz u32 dw_count, *host_addr, hw_offset; 225fe56b9e6SYuval Mintz size_t quota, done = 0; 226fe56b9e6SYuval Mintz u32 __iomem *reg_addr; 227fe56b9e6SYuval Mintz 228fe56b9e6SYuval Mintz while (done < n) { 229fe56b9e6SYuval Mintz quota = min_t(size_t, n - done, 230fe56b9e6SYuval Mintz PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE); 231fe56b9e6SYuval Mintz 2321408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) { 233fe56b9e6SYuval Mintz qed_ptt_set_win(p_hwfn, p_ptt, hw_addr + done); 234fe56b9e6SYuval Mintz hw_offset = qed_ptt_get_bar_addr(p_ptt); 2351408cc1fSYuval Mintz } else { 2361408cc1fSYuval Mintz hw_offset = hw_addr + done; 2371408cc1fSYuval Mintz } 238fe56b9e6SYuval Mintz 239fe56b9e6SYuval Mintz dw_count = quota / 4; 240fe56b9e6SYuval Mintz host_addr = (u32 *)((u8 *)addr + done); 241fe56b9e6SYuval Mintz reg_addr = (u32 __iomem *)REG_ADDR(p_hwfn, hw_offset); 242fe56b9e6SYuval Mintz if (to_device) 243fe56b9e6SYuval Mintz while (dw_count--) 244fe56b9e6SYuval Mintz DIRECT_REG_WR(reg_addr++, *host_addr++); 245fe56b9e6SYuval Mintz else 246fe56b9e6SYuval Mintz while (dw_count--) 247fe56b9e6SYuval Mintz *host_addr++ = DIRECT_REG_RD(reg_addr++); 248fe56b9e6SYuval Mintz 249fe56b9e6SYuval Mintz done += quota; 250fe56b9e6SYuval Mintz } 251fe56b9e6SYuval Mintz } 252fe56b9e6SYuval Mintz 253fe56b9e6SYuval Mintz void qed_memcpy_from(struct qed_hwfn *p_hwfn, 254*1a635e48SYuval Mintz struct qed_ptt *p_ptt, void *dest, u32 hw_addr, size_t n) 255fe56b9e6SYuval Mintz { 256fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 257fe56b9e6SYuval Mintz "hw_addr 0x%x, dest %p hw_addr 0x%x, size %lu\n", 258fe56b9e6SYuval Mintz hw_addr, dest, hw_addr, (unsigned long)n); 259fe56b9e6SYuval Mintz 260fe56b9e6SYuval Mintz qed_memcpy_hw(p_hwfn, p_ptt, dest, hw_addr, n, false); 261fe56b9e6SYuval Mintz } 262fe56b9e6SYuval Mintz 263fe56b9e6SYuval Mintz void qed_memcpy_to(struct qed_hwfn *p_hwfn, 264*1a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 hw_addr, void *src, size_t n) 265fe56b9e6SYuval Mintz { 266fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 267fe56b9e6SYuval Mintz "hw_addr 0x%x, hw_addr 0x%x, src %p size %lu\n", 268fe56b9e6SYuval Mintz hw_addr, hw_addr, src, (unsigned long)n); 269fe56b9e6SYuval Mintz 270fe56b9e6SYuval Mintz qed_memcpy_hw(p_hwfn, p_ptt, src, hw_addr, n, true); 271fe56b9e6SYuval Mintz } 272fe56b9e6SYuval Mintz 273*1a635e48SYuval Mintz void qed_fid_pretend(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 fid) 274fe56b9e6SYuval Mintz { 275fe56b9e6SYuval Mintz u16 control = 0; 276fe56b9e6SYuval Mintz 277fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1); 278fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1); 279fe56b9e6SYuval Mintz 280fe56b9e6SYuval Mintz /* Every pretend undos previous pretends, including 281fe56b9e6SYuval Mintz * previous port pretend. 282fe56b9e6SYuval Mintz */ 283fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0); 284fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0); 285fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); 286fe56b9e6SYuval Mintz 287fe56b9e6SYuval Mintz if (!GET_FIELD(fid, PXP_CONCRETE_FID_VFVALID)) 288fe56b9e6SYuval Mintz fid = GET_FIELD(fid, PXP_CONCRETE_FID_PFID); 289fe56b9e6SYuval Mintz 290fe56b9e6SYuval Mintz p_ptt->pxp.pretend.control = cpu_to_le16(control); 291fe56b9e6SYuval Mintz p_ptt->pxp.pretend.fid.concrete_fid.fid = cpu_to_le16(fid); 292fe56b9e6SYuval Mintz 293fe56b9e6SYuval Mintz REG_WR(p_hwfn, 294fe56b9e6SYuval Mintz qed_ptt_config_addr(p_ptt) + 295fe56b9e6SYuval Mintz offsetof(struct pxp_ptt_entry, pretend), 296fe56b9e6SYuval Mintz *(u32 *)&p_ptt->pxp.pretend); 297fe56b9e6SYuval Mintz } 298fe56b9e6SYuval Mintz 299fe56b9e6SYuval Mintz void qed_port_pretend(struct qed_hwfn *p_hwfn, 300*1a635e48SYuval Mintz struct qed_ptt *p_ptt, u8 port_id) 301fe56b9e6SYuval Mintz { 302fe56b9e6SYuval Mintz u16 control = 0; 303fe56b9e6SYuval Mintz 304fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id); 305fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1); 306fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); 307fe56b9e6SYuval Mintz 308fe56b9e6SYuval Mintz p_ptt->pxp.pretend.control = cpu_to_le16(control); 309fe56b9e6SYuval Mintz 310fe56b9e6SYuval Mintz REG_WR(p_hwfn, 311fe56b9e6SYuval Mintz qed_ptt_config_addr(p_ptt) + 312fe56b9e6SYuval Mintz offsetof(struct pxp_ptt_entry, pretend), 313fe56b9e6SYuval Mintz *(u32 *)&p_ptt->pxp.pretend); 314fe56b9e6SYuval Mintz } 315fe56b9e6SYuval Mintz 316*1a635e48SYuval Mintz void qed_port_unpretend(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 317fe56b9e6SYuval Mintz { 318fe56b9e6SYuval Mintz u16 control = 0; 319fe56b9e6SYuval Mintz 320fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0); 321fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0); 322fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); 323fe56b9e6SYuval Mintz 324fe56b9e6SYuval Mintz p_ptt->pxp.pretend.control = cpu_to_le16(control); 325fe56b9e6SYuval Mintz 326fe56b9e6SYuval Mintz REG_WR(p_hwfn, 327fe56b9e6SYuval Mintz qed_ptt_config_addr(p_ptt) + 328fe56b9e6SYuval Mintz offsetof(struct pxp_ptt_entry, pretend), 329fe56b9e6SYuval Mintz *(u32 *)&p_ptt->pxp.pretend); 330fe56b9e6SYuval Mintz } 331fe56b9e6SYuval Mintz 33232a47e72SYuval Mintz u32 qed_vfid_to_concrete(struct qed_hwfn *p_hwfn, u8 vfid) 33332a47e72SYuval Mintz { 33432a47e72SYuval Mintz u32 concrete_fid = 0; 33532a47e72SYuval Mintz 33632a47e72SYuval Mintz SET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID, p_hwfn->rel_pf_id); 33732a47e72SYuval Mintz SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID, vfid); 33832a47e72SYuval Mintz SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID, 1); 33932a47e72SYuval Mintz 34032a47e72SYuval Mintz return concrete_fid; 34132a47e72SYuval Mintz } 34232a47e72SYuval Mintz 343fe56b9e6SYuval Mintz /* DMAE */ 344fe56b9e6SYuval Mintz static void qed_dmae_opcode(struct qed_hwfn *p_hwfn, 345fe56b9e6SYuval Mintz const u8 is_src_type_grc, 346fe56b9e6SYuval Mintz const u8 is_dst_type_grc, 347fe56b9e6SYuval Mintz struct qed_dmae_params *p_params) 348fe56b9e6SYuval Mintz { 34937bff2b9SYuval Mintz u16 opcode_b = 0; 350fe56b9e6SYuval Mintz u32 opcode = 0; 351fe56b9e6SYuval Mintz 352fe56b9e6SYuval Mintz /* Whether the source is the PCIe or the GRC. 353fe56b9e6SYuval Mintz * 0- The source is the PCIe 354fe56b9e6SYuval Mintz * 1- The source is the GRC. 355fe56b9e6SYuval Mintz */ 356fe56b9e6SYuval Mintz opcode |= (is_src_type_grc ? DMAE_CMD_SRC_MASK_GRC 357fe56b9e6SYuval Mintz : DMAE_CMD_SRC_MASK_PCIE) << 358fe56b9e6SYuval Mintz DMAE_CMD_SRC_SHIFT; 359fe56b9e6SYuval Mintz opcode |= ((p_hwfn->rel_pf_id & DMAE_CMD_SRC_PF_ID_MASK) << 360fe56b9e6SYuval Mintz DMAE_CMD_SRC_PF_ID_SHIFT); 361fe56b9e6SYuval Mintz 362fe56b9e6SYuval Mintz /* The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */ 363fe56b9e6SYuval Mintz opcode |= (is_dst_type_grc ? DMAE_CMD_DST_MASK_GRC 364fe56b9e6SYuval Mintz : DMAE_CMD_DST_MASK_PCIE) << 365fe56b9e6SYuval Mintz DMAE_CMD_DST_SHIFT; 366fe56b9e6SYuval Mintz opcode |= ((p_hwfn->rel_pf_id & DMAE_CMD_DST_PF_ID_MASK) << 367fe56b9e6SYuval Mintz DMAE_CMD_DST_PF_ID_SHIFT); 368fe56b9e6SYuval Mintz 369fe56b9e6SYuval Mintz /* Whether to write a completion word to the completion destination: 370fe56b9e6SYuval Mintz * 0-Do not write a completion word 371fe56b9e6SYuval Mintz * 1-Write the completion word 372fe56b9e6SYuval Mintz */ 373fe56b9e6SYuval Mintz opcode |= (DMAE_CMD_COMP_WORD_EN_MASK << DMAE_CMD_COMP_WORD_EN_SHIFT); 374fe56b9e6SYuval Mintz opcode |= (DMAE_CMD_SRC_ADDR_RESET_MASK << 375fe56b9e6SYuval Mintz DMAE_CMD_SRC_ADDR_RESET_SHIFT); 376fe56b9e6SYuval Mintz 377fe56b9e6SYuval Mintz if (p_params->flags & QED_DMAE_FLAG_COMPLETION_DST) 378fe56b9e6SYuval Mintz opcode |= (1 << DMAE_CMD_COMP_FUNC_SHIFT); 379fe56b9e6SYuval Mintz 380fe56b9e6SYuval Mintz opcode |= (DMAE_CMD_ENDIANITY << DMAE_CMD_ENDIANITY_MODE_SHIFT); 381fe56b9e6SYuval Mintz 382fe56b9e6SYuval Mintz opcode |= ((p_hwfn->port_id) << DMAE_CMD_PORT_ID_SHIFT); 383fe56b9e6SYuval Mintz 384fe56b9e6SYuval Mintz /* reset source address in next go */ 385fe56b9e6SYuval Mintz opcode |= (DMAE_CMD_SRC_ADDR_RESET_MASK << 386fe56b9e6SYuval Mintz DMAE_CMD_SRC_ADDR_RESET_SHIFT); 387fe56b9e6SYuval Mintz 388fe56b9e6SYuval Mintz /* reset dest address in next go */ 389fe56b9e6SYuval Mintz opcode |= (DMAE_CMD_DST_ADDR_RESET_MASK << 390fe56b9e6SYuval Mintz DMAE_CMD_DST_ADDR_RESET_SHIFT); 391fe56b9e6SYuval Mintz 39237bff2b9SYuval Mintz /* SRC/DST VFID: all 1's - pf, otherwise VF id */ 39337bff2b9SYuval Mintz if (p_params->flags & QED_DMAE_FLAG_VF_SRC) { 39437bff2b9SYuval Mintz opcode |= 1 << DMAE_CMD_SRC_VF_ID_VALID_SHIFT; 39537bff2b9SYuval Mintz opcode_b |= p_params->src_vfid << DMAE_CMD_SRC_VF_ID_SHIFT; 39637bff2b9SYuval Mintz } else { 39737bff2b9SYuval Mintz opcode_b |= DMAE_CMD_SRC_VF_ID_MASK << 39837bff2b9SYuval Mintz DMAE_CMD_SRC_VF_ID_SHIFT; 39937bff2b9SYuval Mintz } 400fe56b9e6SYuval Mintz 40137bff2b9SYuval Mintz if (p_params->flags & QED_DMAE_FLAG_VF_DST) { 40237bff2b9SYuval Mintz opcode |= 1 << DMAE_CMD_DST_VF_ID_VALID_SHIFT; 40337bff2b9SYuval Mintz opcode_b |= p_params->dst_vfid << DMAE_CMD_DST_VF_ID_SHIFT; 40437bff2b9SYuval Mintz } else { 40537bff2b9SYuval Mintz opcode_b |= DMAE_CMD_DST_VF_ID_MASK << DMAE_CMD_DST_VF_ID_SHIFT; 40637bff2b9SYuval Mintz } 407fe56b9e6SYuval Mintz 408fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_dmae_cmd->opcode = cpu_to_le32(opcode); 40937bff2b9SYuval Mintz p_hwfn->dmae_info.p_dmae_cmd->opcode_b = cpu_to_le16(opcode_b); 410fe56b9e6SYuval Mintz } 411fe56b9e6SYuval Mintz 412fe56b9e6SYuval Mintz u32 qed_dmae_idx_to_go_cmd(u8 idx) 413fe56b9e6SYuval Mintz { 414fe56b9e6SYuval Mintz /* All the DMAE 'go' registers form an array in internal memory */ 415fe56b9e6SYuval Mintz return DMAE_REG_GO_C0 + (idx << 2); 416fe56b9e6SYuval Mintz } 417fe56b9e6SYuval Mintz 418*1a635e48SYuval Mintz static int qed_dmae_post_command(struct qed_hwfn *p_hwfn, 419fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 420fe56b9e6SYuval Mintz { 421*1a635e48SYuval Mintz struct dmae_cmd *p_command = p_hwfn->dmae_info.p_dmae_cmd; 422fe56b9e6SYuval Mintz u8 idx_cmd = p_hwfn->dmae_info.channel, i; 423fe56b9e6SYuval Mintz int qed_status = 0; 424fe56b9e6SYuval Mintz 425fe56b9e6SYuval Mintz /* verify address is not NULL */ 426*1a635e48SYuval Mintz if ((((!p_command->dst_addr_lo) && (!p_command->dst_addr_hi)) || 427*1a635e48SYuval Mintz ((!p_command->src_addr_lo) && (!p_command->src_addr_hi)))) { 428fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 429fe56b9e6SYuval Mintz "source or destination address 0 idx_cmd=%d\n" 430fe56b9e6SYuval Mintz "opcode = [0x%08x,0x%04x] len=0x%x src=0x%x:%x dst=0x%x:%x\n", 431fe56b9e6SYuval Mintz idx_cmd, 432*1a635e48SYuval Mintz le32_to_cpu(p_command->opcode), 433*1a635e48SYuval Mintz le16_to_cpu(p_command->opcode_b), 434*1a635e48SYuval Mintz le16_to_cpu(p_command->length_dw), 435*1a635e48SYuval Mintz le32_to_cpu(p_command->src_addr_hi), 436*1a635e48SYuval Mintz le32_to_cpu(p_command->src_addr_lo), 437*1a635e48SYuval Mintz le32_to_cpu(p_command->dst_addr_hi), 438*1a635e48SYuval Mintz le32_to_cpu(p_command->dst_addr_lo)); 439fe56b9e6SYuval Mintz 440fe56b9e6SYuval Mintz return -EINVAL; 441fe56b9e6SYuval Mintz } 442fe56b9e6SYuval Mintz 443fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, 444fe56b9e6SYuval Mintz NETIF_MSG_HW, 445fe56b9e6SYuval Mintz "Posting DMAE command [idx %d]: opcode = [0x%08x,0x%04x] len=0x%x src=0x%x:%x dst=0x%x:%x\n", 446fe56b9e6SYuval Mintz idx_cmd, 447*1a635e48SYuval Mintz le32_to_cpu(p_command->opcode), 448*1a635e48SYuval Mintz le16_to_cpu(p_command->opcode_b), 449*1a635e48SYuval Mintz le16_to_cpu(p_command->length_dw), 450*1a635e48SYuval Mintz le32_to_cpu(p_command->src_addr_hi), 451*1a635e48SYuval Mintz le32_to_cpu(p_command->src_addr_lo), 452*1a635e48SYuval Mintz le32_to_cpu(p_command->dst_addr_hi), 453*1a635e48SYuval Mintz le32_to_cpu(p_command->dst_addr_lo)); 454fe56b9e6SYuval Mintz 455fe56b9e6SYuval Mintz /* Copy the command to DMAE - need to do it before every call 456fe56b9e6SYuval Mintz * for source/dest address no reset. 457fe56b9e6SYuval Mintz * The first 9 DWs are the command registers, the 10 DW is the 458fe56b9e6SYuval Mintz * GO register, and the rest are result registers 459fe56b9e6SYuval Mintz * (which are read only by the client). 460fe56b9e6SYuval Mintz */ 461fe56b9e6SYuval Mintz for (i = 0; i < DMAE_CMD_SIZE; i++) { 462fe56b9e6SYuval Mintz u32 data = (i < DMAE_CMD_SIZE_TO_FILL) ? 463*1a635e48SYuval Mintz *(((u32 *)p_command) + i) : 0; 464fe56b9e6SYuval Mintz 465fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 466fe56b9e6SYuval Mintz DMAE_REG_CMD_MEM + 467fe56b9e6SYuval Mintz (idx_cmd * DMAE_CMD_SIZE * sizeof(u32)) + 468fe56b9e6SYuval Mintz (i * sizeof(u32)), data); 469fe56b9e6SYuval Mintz } 470fe56b9e6SYuval Mintz 471*1a635e48SYuval Mintz qed_wr(p_hwfn, p_ptt, qed_dmae_idx_to_go_cmd(idx_cmd), DMAE_GO_VALUE); 472fe56b9e6SYuval Mintz 473fe56b9e6SYuval Mintz return qed_status; 474fe56b9e6SYuval Mintz } 475fe56b9e6SYuval Mintz 476fe56b9e6SYuval Mintz int qed_dmae_info_alloc(struct qed_hwfn *p_hwfn) 477fe56b9e6SYuval Mintz { 478fe56b9e6SYuval Mintz dma_addr_t *p_addr = &p_hwfn->dmae_info.completion_word_phys_addr; 479fe56b9e6SYuval Mintz struct dmae_cmd **p_cmd = &p_hwfn->dmae_info.p_dmae_cmd; 480fe56b9e6SYuval Mintz u32 **p_buff = &p_hwfn->dmae_info.p_intermediate_buffer; 481fe56b9e6SYuval Mintz u32 **p_comp = &p_hwfn->dmae_info.p_completion_word; 482fe56b9e6SYuval Mintz 483fe56b9e6SYuval Mintz *p_comp = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 484*1a635e48SYuval Mintz sizeof(u32), p_addr, GFP_KERNEL); 485fe56b9e6SYuval Mintz if (!*p_comp) { 486fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed to allocate `p_completion_word'\n"); 487fe56b9e6SYuval Mintz goto err; 488fe56b9e6SYuval Mintz } 489fe56b9e6SYuval Mintz 490fe56b9e6SYuval Mintz p_addr = &p_hwfn->dmae_info.dmae_cmd_phys_addr; 491fe56b9e6SYuval Mintz *p_cmd = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 492fe56b9e6SYuval Mintz sizeof(struct dmae_cmd), 493fe56b9e6SYuval Mintz p_addr, GFP_KERNEL); 494fe56b9e6SYuval Mintz if (!*p_cmd) { 495fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed to allocate `struct dmae_cmd'\n"); 496fe56b9e6SYuval Mintz goto err; 497fe56b9e6SYuval Mintz } 498fe56b9e6SYuval Mintz 499fe56b9e6SYuval Mintz p_addr = &p_hwfn->dmae_info.intermediate_buffer_phys_addr; 500fe56b9e6SYuval Mintz *p_buff = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 501fe56b9e6SYuval Mintz sizeof(u32) * DMAE_MAX_RW_SIZE, 502fe56b9e6SYuval Mintz p_addr, GFP_KERNEL); 503fe56b9e6SYuval Mintz if (!*p_buff) { 504fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed to allocate `intermediate_buffer'\n"); 505fe56b9e6SYuval Mintz goto err; 506fe56b9e6SYuval Mintz } 507fe56b9e6SYuval Mintz 508fe56b9e6SYuval Mintz p_hwfn->dmae_info.channel = p_hwfn->rel_pf_id; 509fe56b9e6SYuval Mintz 510fe56b9e6SYuval Mintz return 0; 511fe56b9e6SYuval Mintz err: 512fe56b9e6SYuval Mintz qed_dmae_info_free(p_hwfn); 513fe56b9e6SYuval Mintz return -ENOMEM; 514fe56b9e6SYuval Mintz } 515fe56b9e6SYuval Mintz 516fe56b9e6SYuval Mintz void qed_dmae_info_free(struct qed_hwfn *p_hwfn) 517fe56b9e6SYuval Mintz { 518fe56b9e6SYuval Mintz dma_addr_t p_phys; 519fe56b9e6SYuval Mintz 520fe56b9e6SYuval Mintz /* Just make sure no one is in the middle */ 521fe56b9e6SYuval Mintz mutex_lock(&p_hwfn->dmae_info.mutex); 522fe56b9e6SYuval Mintz 523fe56b9e6SYuval Mintz if (p_hwfn->dmae_info.p_completion_word) { 524fe56b9e6SYuval Mintz p_phys = p_hwfn->dmae_info.completion_word_phys_addr; 525fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 526fe56b9e6SYuval Mintz sizeof(u32), 527*1a635e48SYuval Mintz p_hwfn->dmae_info.p_completion_word, p_phys); 528fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_completion_word = NULL; 529fe56b9e6SYuval Mintz } 530fe56b9e6SYuval Mintz 531fe56b9e6SYuval Mintz if (p_hwfn->dmae_info.p_dmae_cmd) { 532fe56b9e6SYuval Mintz p_phys = p_hwfn->dmae_info.dmae_cmd_phys_addr; 533fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 534fe56b9e6SYuval Mintz sizeof(struct dmae_cmd), 535*1a635e48SYuval Mintz p_hwfn->dmae_info.p_dmae_cmd, p_phys); 536fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_dmae_cmd = NULL; 537fe56b9e6SYuval Mintz } 538fe56b9e6SYuval Mintz 539fe56b9e6SYuval Mintz if (p_hwfn->dmae_info.p_intermediate_buffer) { 540fe56b9e6SYuval Mintz p_phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr; 541fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 542fe56b9e6SYuval Mintz sizeof(u32) * DMAE_MAX_RW_SIZE, 543fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_intermediate_buffer, 544fe56b9e6SYuval Mintz p_phys); 545fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_intermediate_buffer = NULL; 546fe56b9e6SYuval Mintz } 547fe56b9e6SYuval Mintz 548fe56b9e6SYuval Mintz mutex_unlock(&p_hwfn->dmae_info.mutex); 549fe56b9e6SYuval Mintz } 550fe56b9e6SYuval Mintz 551fe56b9e6SYuval Mintz static int qed_dmae_operation_wait(struct qed_hwfn *p_hwfn) 552fe56b9e6SYuval Mintz { 553*1a635e48SYuval Mintz u32 wait_cnt_limit = 10000, wait_cnt = 0; 554fe56b9e6SYuval Mintz int qed_status = 0; 555fe56b9e6SYuval Mintz 556fe56b9e6SYuval Mintz barrier(); 557fe56b9e6SYuval Mintz while (*p_hwfn->dmae_info.p_completion_word != DMAE_COMPLETION_VAL) { 558fe56b9e6SYuval Mintz udelay(DMAE_MIN_WAIT_TIME); 559fe56b9e6SYuval Mintz if (++wait_cnt > wait_cnt_limit) { 560fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn->cdev, 561fe56b9e6SYuval Mintz "Timed-out waiting for operation to complete. Completion word is 0x%08x expected 0x%08x.\n", 562fe56b9e6SYuval Mintz *p_hwfn->dmae_info.p_completion_word, 563fe56b9e6SYuval Mintz DMAE_COMPLETION_VAL); 564fe56b9e6SYuval Mintz qed_status = -EBUSY; 565fe56b9e6SYuval Mintz break; 566fe56b9e6SYuval Mintz } 567fe56b9e6SYuval Mintz 568fe56b9e6SYuval Mintz /* to sync the completion_word since we are not 569fe56b9e6SYuval Mintz * using the volatile keyword for p_completion_word 570fe56b9e6SYuval Mintz */ 571fe56b9e6SYuval Mintz barrier(); 572fe56b9e6SYuval Mintz } 573fe56b9e6SYuval Mintz 574fe56b9e6SYuval Mintz if (qed_status == 0) 575fe56b9e6SYuval Mintz *p_hwfn->dmae_info.p_completion_word = 0; 576fe56b9e6SYuval Mintz 577fe56b9e6SYuval Mintz return qed_status; 578fe56b9e6SYuval Mintz } 579fe56b9e6SYuval Mintz 580fe56b9e6SYuval Mintz static int qed_dmae_execute_sub_operation(struct qed_hwfn *p_hwfn, 581fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 582fe56b9e6SYuval Mintz u64 src_addr, 583fe56b9e6SYuval Mintz u64 dst_addr, 584fe56b9e6SYuval Mintz u8 src_type, 585fe56b9e6SYuval Mintz u8 dst_type, 586*1a635e48SYuval Mintz u32 length_dw) 587fe56b9e6SYuval Mintz { 588fe56b9e6SYuval Mintz dma_addr_t phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr; 589fe56b9e6SYuval Mintz struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd; 590fe56b9e6SYuval Mintz int qed_status = 0; 591fe56b9e6SYuval Mintz 592fe56b9e6SYuval Mintz switch (src_type) { 593fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_GRC: 594fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_HOST_PHYS: 595fe56b9e6SYuval Mintz cmd->src_addr_hi = cpu_to_le32(upper_32_bits(src_addr)); 596fe56b9e6SYuval Mintz cmd->src_addr_lo = cpu_to_le32(lower_32_bits(src_addr)); 597fe56b9e6SYuval Mintz break; 598fe56b9e6SYuval Mintz /* for virtual source addresses we use the intermediate buffer. */ 599fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_HOST_VIRT: 600fe56b9e6SYuval Mintz cmd->src_addr_hi = cpu_to_le32(upper_32_bits(phys)); 601fe56b9e6SYuval Mintz cmd->src_addr_lo = cpu_to_le32(lower_32_bits(phys)); 602fe56b9e6SYuval Mintz memcpy(&p_hwfn->dmae_info.p_intermediate_buffer[0], 603fe56b9e6SYuval Mintz (void *)(uintptr_t)src_addr, 604*1a635e48SYuval Mintz length_dw * sizeof(u32)); 605fe56b9e6SYuval Mintz break; 606fe56b9e6SYuval Mintz default: 607fe56b9e6SYuval Mintz return -EINVAL; 608fe56b9e6SYuval Mintz } 609fe56b9e6SYuval Mintz 610fe56b9e6SYuval Mintz switch (dst_type) { 611fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_GRC: 612fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_HOST_PHYS: 613fe56b9e6SYuval Mintz cmd->dst_addr_hi = cpu_to_le32(upper_32_bits(dst_addr)); 614fe56b9e6SYuval Mintz cmd->dst_addr_lo = cpu_to_le32(lower_32_bits(dst_addr)); 615fe56b9e6SYuval Mintz break; 616fe56b9e6SYuval Mintz /* for virtual source addresses we use the intermediate buffer. */ 617fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_HOST_VIRT: 618fe56b9e6SYuval Mintz cmd->dst_addr_hi = cpu_to_le32(upper_32_bits(phys)); 619fe56b9e6SYuval Mintz cmd->dst_addr_lo = cpu_to_le32(lower_32_bits(phys)); 620fe56b9e6SYuval Mintz break; 621fe56b9e6SYuval Mintz default: 622fe56b9e6SYuval Mintz return -EINVAL; 623fe56b9e6SYuval Mintz } 624fe56b9e6SYuval Mintz 625*1a635e48SYuval Mintz cmd->length_dw = cpu_to_le16((u16)length_dw); 626fe56b9e6SYuval Mintz 627fe56b9e6SYuval Mintz qed_dmae_post_command(p_hwfn, p_ptt); 628fe56b9e6SYuval Mintz 629fe56b9e6SYuval Mintz qed_status = qed_dmae_operation_wait(p_hwfn); 630fe56b9e6SYuval Mintz 631fe56b9e6SYuval Mintz if (qed_status) { 632fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 633fe56b9e6SYuval Mintz "qed_dmae_host2grc: Wait Failed. source_addr 0x%llx, grc_addr 0x%llx, size_in_dwords 0x%x\n", 634*1a635e48SYuval Mintz src_addr, dst_addr, length_dw); 635fe56b9e6SYuval Mintz return qed_status; 636fe56b9e6SYuval Mintz } 637fe56b9e6SYuval Mintz 638fe56b9e6SYuval Mintz if (dst_type == QED_DMAE_ADDRESS_HOST_VIRT) 639fe56b9e6SYuval Mintz memcpy((void *)(uintptr_t)(dst_addr), 640fe56b9e6SYuval Mintz &p_hwfn->dmae_info.p_intermediate_buffer[0], 641*1a635e48SYuval Mintz length_dw * sizeof(u32)); 642fe56b9e6SYuval Mintz 643fe56b9e6SYuval Mintz return 0; 644fe56b9e6SYuval Mintz } 645fe56b9e6SYuval Mintz 646fe56b9e6SYuval Mintz static int qed_dmae_execute_command(struct qed_hwfn *p_hwfn, 647fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 648fe56b9e6SYuval Mintz u64 src_addr, u64 dst_addr, 649fe56b9e6SYuval Mintz u8 src_type, u8 dst_type, 650fe56b9e6SYuval Mintz u32 size_in_dwords, 651fe56b9e6SYuval Mintz struct qed_dmae_params *p_params) 652fe56b9e6SYuval Mintz { 653fe56b9e6SYuval Mintz dma_addr_t phys = p_hwfn->dmae_info.completion_word_phys_addr; 654fe56b9e6SYuval Mintz u16 length_cur = 0, i = 0, cnt_split = 0, length_mod = 0; 655fe56b9e6SYuval Mintz struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd; 656fe56b9e6SYuval Mintz u64 src_addr_split = 0, dst_addr_split = 0; 657fe56b9e6SYuval Mintz u16 length_limit = DMAE_MAX_RW_SIZE; 658fe56b9e6SYuval Mintz int qed_status = 0; 659fe56b9e6SYuval Mintz u32 offset = 0; 660fe56b9e6SYuval Mintz 661fe56b9e6SYuval Mintz qed_dmae_opcode(p_hwfn, 662fe56b9e6SYuval Mintz (src_type == QED_DMAE_ADDRESS_GRC), 663fe56b9e6SYuval Mintz (dst_type == QED_DMAE_ADDRESS_GRC), 664fe56b9e6SYuval Mintz p_params); 665fe56b9e6SYuval Mintz 666fe56b9e6SYuval Mintz cmd->comp_addr_lo = cpu_to_le32(lower_32_bits(phys)); 667fe56b9e6SYuval Mintz cmd->comp_addr_hi = cpu_to_le32(upper_32_bits(phys)); 668fe56b9e6SYuval Mintz cmd->comp_val = cpu_to_le32(DMAE_COMPLETION_VAL); 669fe56b9e6SYuval Mintz 670fe56b9e6SYuval Mintz /* Check if the grc_addr is valid like < MAX_GRC_OFFSET */ 671fe56b9e6SYuval Mintz cnt_split = size_in_dwords / length_limit; 672fe56b9e6SYuval Mintz length_mod = size_in_dwords % length_limit; 673fe56b9e6SYuval Mintz 674fe56b9e6SYuval Mintz src_addr_split = src_addr; 675fe56b9e6SYuval Mintz dst_addr_split = dst_addr; 676fe56b9e6SYuval Mintz 677fe56b9e6SYuval Mintz for (i = 0; i <= cnt_split; i++) { 678fe56b9e6SYuval Mintz offset = length_limit * i; 679fe56b9e6SYuval Mintz 680fe56b9e6SYuval Mintz if (!(p_params->flags & QED_DMAE_FLAG_RW_REPL_SRC)) { 681fe56b9e6SYuval Mintz if (src_type == QED_DMAE_ADDRESS_GRC) 682fe56b9e6SYuval Mintz src_addr_split = src_addr + offset; 683fe56b9e6SYuval Mintz else 684fe56b9e6SYuval Mintz src_addr_split = src_addr + (offset * 4); 685fe56b9e6SYuval Mintz } 686fe56b9e6SYuval Mintz 687fe56b9e6SYuval Mintz if (dst_type == QED_DMAE_ADDRESS_GRC) 688fe56b9e6SYuval Mintz dst_addr_split = dst_addr + offset; 689fe56b9e6SYuval Mintz else 690fe56b9e6SYuval Mintz dst_addr_split = dst_addr + (offset * 4); 691fe56b9e6SYuval Mintz 692fe56b9e6SYuval Mintz length_cur = (cnt_split == i) ? length_mod : length_limit; 693fe56b9e6SYuval Mintz 694fe56b9e6SYuval Mintz /* might be zero on last iteration */ 695fe56b9e6SYuval Mintz if (!length_cur) 696fe56b9e6SYuval Mintz continue; 697fe56b9e6SYuval Mintz 698fe56b9e6SYuval Mintz qed_status = qed_dmae_execute_sub_operation(p_hwfn, 699fe56b9e6SYuval Mintz p_ptt, 700fe56b9e6SYuval Mintz src_addr_split, 701fe56b9e6SYuval Mintz dst_addr_split, 702fe56b9e6SYuval Mintz src_type, 703fe56b9e6SYuval Mintz dst_type, 704fe56b9e6SYuval Mintz length_cur); 705fe56b9e6SYuval Mintz if (qed_status) { 706fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 707fe56b9e6SYuval Mintz "qed_dmae_execute_sub_operation Failed with error 0x%x. source_addr 0x%llx, destination addr 0x%llx, size_in_dwords 0x%x\n", 708*1a635e48SYuval Mintz qed_status, src_addr, dst_addr, length_cur); 709fe56b9e6SYuval Mintz break; 710fe56b9e6SYuval Mintz } 711fe56b9e6SYuval Mintz } 712fe56b9e6SYuval Mintz 713fe56b9e6SYuval Mintz return qed_status; 714fe56b9e6SYuval Mintz } 715fe56b9e6SYuval Mintz 716fe56b9e6SYuval Mintz int qed_dmae_host2grc(struct qed_hwfn *p_hwfn, 717fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 718*1a635e48SYuval Mintz u64 source_addr, u32 grc_addr, u32 size_in_dwords, u32 flags) 719fe56b9e6SYuval Mintz { 720fe56b9e6SYuval Mintz u32 grc_addr_in_dw = grc_addr / sizeof(u32); 721fe56b9e6SYuval Mintz struct qed_dmae_params params; 722fe56b9e6SYuval Mintz int rc; 723fe56b9e6SYuval Mintz 724fe56b9e6SYuval Mintz memset(¶ms, 0, sizeof(struct qed_dmae_params)); 725fe56b9e6SYuval Mintz params.flags = flags; 726fe56b9e6SYuval Mintz 727fe56b9e6SYuval Mintz mutex_lock(&p_hwfn->dmae_info.mutex); 728fe56b9e6SYuval Mintz 729fe56b9e6SYuval Mintz rc = qed_dmae_execute_command(p_hwfn, p_ptt, source_addr, 730fe56b9e6SYuval Mintz grc_addr_in_dw, 731fe56b9e6SYuval Mintz QED_DMAE_ADDRESS_HOST_VIRT, 732fe56b9e6SYuval Mintz QED_DMAE_ADDRESS_GRC, 733fe56b9e6SYuval Mintz size_in_dwords, ¶ms); 734fe56b9e6SYuval Mintz 735fe56b9e6SYuval Mintz mutex_unlock(&p_hwfn->dmae_info.mutex); 736fe56b9e6SYuval Mintz 737fe56b9e6SYuval Mintz return rc; 738fe56b9e6SYuval Mintz } 739fe56b9e6SYuval Mintz 740*1a635e48SYuval Mintz int qed_dmae_grc2host(struct qed_hwfn *p_hwfn, 741*1a635e48SYuval Mintz struct qed_ptt *p_ptt, 742*1a635e48SYuval Mintz u32 grc_addr, 743722003acSSudarsana Reddy Kalluru dma_addr_t dest_addr, u32 size_in_dwords, u32 flags) 744722003acSSudarsana Reddy Kalluru { 745722003acSSudarsana Reddy Kalluru u32 grc_addr_in_dw = grc_addr / sizeof(u32); 746722003acSSudarsana Reddy Kalluru struct qed_dmae_params params; 747722003acSSudarsana Reddy Kalluru int rc; 748722003acSSudarsana Reddy Kalluru 749722003acSSudarsana Reddy Kalluru memset(¶ms, 0, sizeof(struct qed_dmae_params)); 750722003acSSudarsana Reddy Kalluru params.flags = flags; 751722003acSSudarsana Reddy Kalluru 752722003acSSudarsana Reddy Kalluru mutex_lock(&p_hwfn->dmae_info.mutex); 753722003acSSudarsana Reddy Kalluru 754722003acSSudarsana Reddy Kalluru rc = qed_dmae_execute_command(p_hwfn, p_ptt, grc_addr_in_dw, 755722003acSSudarsana Reddy Kalluru dest_addr, QED_DMAE_ADDRESS_GRC, 756722003acSSudarsana Reddy Kalluru QED_DMAE_ADDRESS_HOST_VIRT, 757722003acSSudarsana Reddy Kalluru size_in_dwords, ¶ms); 758722003acSSudarsana Reddy Kalluru 759722003acSSudarsana Reddy Kalluru mutex_unlock(&p_hwfn->dmae_info.mutex); 760722003acSSudarsana Reddy Kalluru 761722003acSSudarsana Reddy Kalluru return rc; 762722003acSSudarsana Reddy Kalluru } 763722003acSSudarsana Reddy Kalluru 764*1a635e48SYuval Mintz int qed_dmae_host2host(struct qed_hwfn *p_hwfn, 76537bff2b9SYuval Mintz struct qed_ptt *p_ptt, 76637bff2b9SYuval Mintz dma_addr_t source_addr, 76737bff2b9SYuval Mintz dma_addr_t dest_addr, 76837bff2b9SYuval Mintz u32 size_in_dwords, struct qed_dmae_params *p_params) 76937bff2b9SYuval Mintz { 77037bff2b9SYuval Mintz int rc; 77137bff2b9SYuval Mintz 77237bff2b9SYuval Mintz mutex_lock(&(p_hwfn->dmae_info.mutex)); 77337bff2b9SYuval Mintz 77437bff2b9SYuval Mintz rc = qed_dmae_execute_command(p_hwfn, p_ptt, source_addr, 77537bff2b9SYuval Mintz dest_addr, 77637bff2b9SYuval Mintz QED_DMAE_ADDRESS_HOST_PHYS, 77737bff2b9SYuval Mintz QED_DMAE_ADDRESS_HOST_PHYS, 77837bff2b9SYuval Mintz size_in_dwords, p_params); 77937bff2b9SYuval Mintz 78037bff2b9SYuval Mintz mutex_unlock(&(p_hwfn->dmae_info.mutex)); 78137bff2b9SYuval Mintz 78237bff2b9SYuval Mintz return rc; 78337bff2b9SYuval Mintz } 78437bff2b9SYuval Mintz 785fe56b9e6SYuval Mintz u16 qed_get_qm_pq(struct qed_hwfn *p_hwfn, 786dbb799c3SYuval Mintz enum protocol_type proto, union qed_qm_pq_params *p_params) 787fe56b9e6SYuval Mintz { 788fe56b9e6SYuval Mintz u16 pq_id = 0; 789fe56b9e6SYuval Mintz 790dbb799c3SYuval Mintz if ((proto == PROTOCOLID_CORE || 791dbb799c3SYuval Mintz proto == PROTOCOLID_ETH || 792dbb799c3SYuval Mintz proto == PROTOCOLID_ISCSI || 793dbb799c3SYuval Mintz proto == PROTOCOLID_ROCE) && !p_params) { 794fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 795dbb799c3SYuval Mintz "Protocol %d received NULL PQ params\n", proto); 796fe56b9e6SYuval Mintz return 0; 797fe56b9e6SYuval Mintz } 798fe56b9e6SYuval Mintz 799fe56b9e6SYuval Mintz switch (proto) { 800fe56b9e6SYuval Mintz case PROTOCOLID_CORE: 801fe56b9e6SYuval Mintz if (p_params->core.tc == LB_TC) 802fe56b9e6SYuval Mintz pq_id = p_hwfn->qm_info.pure_lb_pq; 803dbb799c3SYuval Mintz else if (p_params->core.tc == OOO_LB_TC) 804dbb799c3SYuval Mintz pq_id = p_hwfn->qm_info.ooo_pq; 805fe56b9e6SYuval Mintz else 806fe56b9e6SYuval Mintz pq_id = p_hwfn->qm_info.offload_pq; 807fe56b9e6SYuval Mintz break; 808fe56b9e6SYuval Mintz case PROTOCOLID_ETH: 809fe56b9e6SYuval Mintz pq_id = p_params->eth.tc; 8101408cc1fSYuval Mintz if (p_params->eth.is_vf) 8111408cc1fSYuval Mintz pq_id += p_hwfn->qm_info.vf_queues_offset + 8121408cc1fSYuval Mintz p_params->eth.vf_id; 813fe56b9e6SYuval Mintz break; 814dbb799c3SYuval Mintz case PROTOCOLID_ISCSI: 815dbb799c3SYuval Mintz if (p_params->iscsi.q_idx == 1) 816dbb799c3SYuval Mintz pq_id = p_hwfn->qm_info.pure_ack_pq; 817dbb799c3SYuval Mintz break; 818dbb799c3SYuval Mintz case PROTOCOLID_ROCE: 819dbb799c3SYuval Mintz if (p_params->roce.dcqcn) 820dbb799c3SYuval Mintz pq_id = p_params->roce.qpid; 821dbb799c3SYuval Mintz else 822dbb799c3SYuval Mintz pq_id = p_hwfn->qm_info.offload_pq; 823dbb799c3SYuval Mintz if (pq_id > p_hwfn->qm_info.num_pf_rls) 824dbb799c3SYuval Mintz pq_id = p_hwfn->qm_info.offload_pq; 825dbb799c3SYuval Mintz break; 826fe56b9e6SYuval Mintz default: 827fe56b9e6SYuval Mintz pq_id = 0; 828fe56b9e6SYuval Mintz } 829fe56b9e6SYuval Mintz 830fe56b9e6SYuval Mintz pq_id = CM_TX_PQ_BASE + pq_id + RESC_START(p_hwfn, QED_PQ); 831fe56b9e6SYuval Mintz 832fe56b9e6SYuval Mintz return pq_id; 833fe56b9e6SYuval Mintz } 834