1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #include <linux/types.h> 10 #include <asm/byteorder.h> 11 #include <linux/io.h> 12 #include <linux/delay.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/errno.h> 15 #include <linux/kernel.h> 16 #include <linux/mutex.h> 17 #include <linux/pci.h> 18 #include <linux/slab.h> 19 #include <linux/string.h> 20 #include <linux/vmalloc.h> 21 #include <linux/etherdevice.h> 22 #include <linux/qed/qed_chain.h> 23 #include <linux/qed/qed_if.h> 24 #include "qed.h" 25 #include "qed_cxt.h" 26 #include "qed_dcbx.h" 27 #include "qed_dev_api.h" 28 #include "qed_hsi.h" 29 #include "qed_hw.h" 30 #include "qed_init_ops.h" 31 #include "qed_int.h" 32 #include "qed_mcp.h" 33 #include "qed_reg_addr.h" 34 #include "qed_sp.h" 35 #include "qed_sriov.h" 36 #include "qed_vf.h" 37 38 static DEFINE_SPINLOCK(qm_lock); 39 40 /* API common to all protocols */ 41 enum BAR_ID { 42 BAR_ID_0, /* used for GRC */ 43 BAR_ID_1 /* Used for doorbells */ 44 }; 45 46 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, enum BAR_ID bar_id) 47 { 48 u32 bar_reg = (bar_id == BAR_ID_0 ? 49 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); 50 u32 val; 51 52 if (IS_VF(p_hwfn->cdev)) 53 return 1 << 17; 54 55 val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg); 56 if (val) 57 return 1 << (val + 15); 58 59 /* Old MFW initialized above registered only conditionally */ 60 if (p_hwfn->cdev->num_hwfns > 1) { 61 DP_INFO(p_hwfn, 62 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n"); 63 return BAR_ID_0 ? 256 * 1024 : 512 * 1024; 64 } else { 65 DP_INFO(p_hwfn, 66 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n"); 67 return 512 * 1024; 68 } 69 } 70 71 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level) 72 { 73 u32 i; 74 75 cdev->dp_level = dp_level; 76 cdev->dp_module = dp_module; 77 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 78 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 79 80 p_hwfn->dp_level = dp_level; 81 p_hwfn->dp_module = dp_module; 82 } 83 } 84 85 void qed_init_struct(struct qed_dev *cdev) 86 { 87 u8 i; 88 89 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 90 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 91 92 p_hwfn->cdev = cdev; 93 p_hwfn->my_id = i; 94 p_hwfn->b_active = false; 95 96 mutex_init(&p_hwfn->dmae_info.mutex); 97 } 98 99 /* hwfn 0 is always active */ 100 cdev->hwfns[0].b_active = true; 101 102 /* set the default cache alignment to 128 */ 103 cdev->cache_shift = 7; 104 } 105 106 static void qed_qm_info_free(struct qed_hwfn *p_hwfn) 107 { 108 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 109 110 kfree(qm_info->qm_pq_params); 111 qm_info->qm_pq_params = NULL; 112 kfree(qm_info->qm_vport_params); 113 qm_info->qm_vport_params = NULL; 114 kfree(qm_info->qm_port_params); 115 qm_info->qm_port_params = NULL; 116 kfree(qm_info->wfq_data); 117 qm_info->wfq_data = NULL; 118 } 119 120 void qed_resc_free(struct qed_dev *cdev) 121 { 122 int i; 123 124 if (IS_VF(cdev)) 125 return; 126 127 kfree(cdev->fw_data); 128 cdev->fw_data = NULL; 129 130 kfree(cdev->reset_stats); 131 132 for_each_hwfn(cdev, i) { 133 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 134 135 kfree(p_hwfn->p_tx_cids); 136 p_hwfn->p_tx_cids = NULL; 137 kfree(p_hwfn->p_rx_cids); 138 p_hwfn->p_rx_cids = NULL; 139 } 140 141 for_each_hwfn(cdev, i) { 142 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 143 144 qed_cxt_mngr_free(p_hwfn); 145 qed_qm_info_free(p_hwfn); 146 qed_spq_free(p_hwfn); 147 qed_eq_free(p_hwfn, p_hwfn->p_eq); 148 qed_consq_free(p_hwfn, p_hwfn->p_consq); 149 qed_int_free(p_hwfn); 150 qed_iov_free(p_hwfn); 151 qed_dmae_info_free(p_hwfn); 152 qed_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info); 153 } 154 } 155 156 static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable) 157 { 158 u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0; 159 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 160 struct init_qm_port_params *p_qm_port; 161 bool init_rdma_offload_pq = false; 162 bool init_pure_ack_pq = false; 163 bool init_ooo_pq = false; 164 u16 num_pqs, multi_cos_tcs = 1; 165 u8 pf_wfq = qm_info->pf_wfq; 166 u32 pf_rl = qm_info->pf_rl; 167 u16 num_pf_rls = 0; 168 u16 num_vfs = 0; 169 170 #ifdef CONFIG_QED_SRIOV 171 if (p_hwfn->cdev->p_iov_info) 172 num_vfs = p_hwfn->cdev->p_iov_info->total_vfs; 173 #endif 174 memset(qm_info, 0, sizeof(*qm_info)); 175 176 num_pqs = multi_cos_tcs + num_vfs + 1; /* The '1' is for pure-LB */ 177 num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT); 178 179 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) { 180 num_pqs++; /* for RoCE queue */ 181 init_rdma_offload_pq = true; 182 /* we subtract num_vfs because each require a rate limiter, 183 * and one default rate limiter 184 */ 185 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn) 186 num_pf_rls = RESC_NUM(p_hwfn, QED_RL) - num_vfs - 1; 187 188 num_pqs += num_pf_rls; 189 qm_info->num_pf_rls = (u8) num_pf_rls; 190 } 191 192 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 193 num_pqs += 2; /* for iSCSI pure-ACK / OOO queue */ 194 init_pure_ack_pq = true; 195 init_ooo_pq = true; 196 } 197 198 /* Sanity checking that setup requires legal number of resources */ 199 if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) { 200 DP_ERR(p_hwfn, 201 "Need too many Physical queues - 0x%04x when only %04x are available\n", 202 num_pqs, RESC_NUM(p_hwfn, QED_PQ)); 203 return -EINVAL; 204 } 205 206 /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete. 207 */ 208 qm_info->qm_pq_params = kcalloc(num_pqs, 209 sizeof(struct init_qm_pq_params), 210 b_sleepable ? GFP_KERNEL : GFP_ATOMIC); 211 if (!qm_info->qm_pq_params) 212 goto alloc_err; 213 214 qm_info->qm_vport_params = kcalloc(num_vports, 215 sizeof(struct init_qm_vport_params), 216 b_sleepable ? GFP_KERNEL 217 : GFP_ATOMIC); 218 if (!qm_info->qm_vport_params) 219 goto alloc_err; 220 221 qm_info->qm_port_params = kcalloc(MAX_NUM_PORTS, 222 sizeof(struct init_qm_port_params), 223 b_sleepable ? GFP_KERNEL 224 : GFP_ATOMIC); 225 if (!qm_info->qm_port_params) 226 goto alloc_err; 227 228 qm_info->wfq_data = kcalloc(num_vports, sizeof(struct qed_wfq_data), 229 b_sleepable ? GFP_KERNEL : GFP_ATOMIC); 230 if (!qm_info->wfq_data) 231 goto alloc_err; 232 233 vport_id = (u8)RESC_START(p_hwfn, QED_VPORT); 234 235 /* First init rate limited queues */ 236 for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) { 237 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++; 238 qm_info->qm_pq_params[curr_queue].tc_id = 239 p_hwfn->hw_info.non_offload_tc; 240 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 241 qm_info->qm_pq_params[curr_queue].rl_valid = 1; 242 } 243 244 /* First init per-TC PQs */ 245 for (i = 0; i < multi_cos_tcs; i++) { 246 struct init_qm_pq_params *params = 247 &qm_info->qm_pq_params[curr_queue++]; 248 249 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE || 250 p_hwfn->hw_info.personality == QED_PCI_ETH) { 251 params->vport_id = vport_id; 252 params->tc_id = p_hwfn->hw_info.non_offload_tc; 253 params->wrr_group = 1; 254 } else { 255 params->vport_id = vport_id; 256 params->tc_id = p_hwfn->hw_info.offload_tc; 257 params->wrr_group = 1; 258 } 259 } 260 261 /* Then init pure-LB PQ */ 262 qm_info->pure_lb_pq = curr_queue; 263 qm_info->qm_pq_params[curr_queue].vport_id = 264 (u8) RESC_START(p_hwfn, QED_VPORT); 265 qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC; 266 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 267 curr_queue++; 268 269 qm_info->offload_pq = 0; 270 if (init_rdma_offload_pq) { 271 qm_info->offload_pq = curr_queue; 272 qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 273 qm_info->qm_pq_params[curr_queue].tc_id = 274 p_hwfn->hw_info.offload_tc; 275 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 276 curr_queue++; 277 } 278 279 if (init_pure_ack_pq) { 280 qm_info->pure_ack_pq = curr_queue; 281 qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 282 qm_info->qm_pq_params[curr_queue].tc_id = 283 p_hwfn->hw_info.offload_tc; 284 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 285 curr_queue++; 286 } 287 288 if (init_ooo_pq) { 289 qm_info->ooo_pq = curr_queue; 290 qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 291 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC; 292 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 293 curr_queue++; 294 } 295 296 /* Then init per-VF PQs */ 297 vf_offset = curr_queue; 298 for (i = 0; i < num_vfs; i++) { 299 /* First vport is used by the PF */ 300 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1; 301 qm_info->qm_pq_params[curr_queue].tc_id = 302 p_hwfn->hw_info.non_offload_tc; 303 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 304 qm_info->qm_pq_params[curr_queue].rl_valid = 1; 305 curr_queue++; 306 } 307 308 qm_info->vf_queues_offset = vf_offset; 309 qm_info->num_pqs = num_pqs; 310 qm_info->num_vports = num_vports; 311 312 /* Initialize qm port parameters */ 313 num_ports = p_hwfn->cdev->num_ports_in_engines; 314 for (i = 0; i < num_ports; i++) { 315 p_qm_port = &qm_info->qm_port_params[i]; 316 p_qm_port->active = 1; 317 if (num_ports == 4) 318 p_qm_port->active_phys_tcs = 0x7; 319 else 320 p_qm_port->active_phys_tcs = 0x9f; 321 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports; 322 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports; 323 } 324 325 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS; 326 327 qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ); 328 329 qm_info->num_vf_pqs = num_vfs; 330 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT); 331 332 for (i = 0; i < qm_info->num_vports; i++) 333 qm_info->qm_vport_params[i].vport_wfq = 1; 334 335 qm_info->vport_rl_en = 1; 336 qm_info->vport_wfq_en = 1; 337 qm_info->pf_rl = pf_rl; 338 qm_info->pf_wfq = pf_wfq; 339 340 return 0; 341 342 alloc_err: 343 qed_qm_info_free(p_hwfn); 344 return -ENOMEM; 345 } 346 347 /* This function reconfigures the QM pf on the fly. 348 * For this purpose we: 349 * 1. reconfigure the QM database 350 * 2. set new values to runtime arrat 351 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM 352 * 4. activate init tool in QM_PF stage 353 * 5. send an sdm_qm_cmd through rbc interface to release the QM 354 */ 355 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 356 { 357 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 358 bool b_rc; 359 int rc; 360 361 /* qm_info is allocated in qed_init_qm_info() which is already called 362 * from qed_resc_alloc() or previous call of qed_qm_reconf(). 363 * The allocated size may change each init, so we free it before next 364 * allocation. 365 */ 366 qed_qm_info_free(p_hwfn); 367 368 /* initialize qed's qm data structure */ 369 rc = qed_init_qm_info(p_hwfn, false); 370 if (rc) 371 return rc; 372 373 /* stop PF's qm queues */ 374 spin_lock_bh(&qm_lock); 375 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true, 376 qm_info->start_pq, qm_info->num_pqs); 377 spin_unlock_bh(&qm_lock); 378 if (!b_rc) 379 return -EINVAL; 380 381 /* clear the QM_PF runtime phase leftovers from previous init */ 382 qed_init_clear_rt_data(p_hwfn); 383 384 /* prepare QM portion of runtime array */ 385 qed_qm_init_pf(p_hwfn); 386 387 /* activate init tool on runtime array */ 388 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id, 389 p_hwfn->hw_info.hw_mode); 390 if (rc) 391 return rc; 392 393 /* start PF's qm queues */ 394 spin_lock_bh(&qm_lock); 395 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true, 396 qm_info->start_pq, qm_info->num_pqs); 397 spin_unlock_bh(&qm_lock); 398 if (!b_rc) 399 return -EINVAL; 400 401 return 0; 402 } 403 404 int qed_resc_alloc(struct qed_dev *cdev) 405 { 406 struct qed_consq *p_consq; 407 struct qed_eq *p_eq; 408 int i, rc = 0; 409 410 if (IS_VF(cdev)) 411 return rc; 412 413 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL); 414 if (!cdev->fw_data) 415 return -ENOMEM; 416 417 /* Allocate Memory for the Queue->CID mapping */ 418 for_each_hwfn(cdev, i) { 419 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 420 int tx_size = sizeof(struct qed_hw_cid_data) * 421 RESC_NUM(p_hwfn, QED_L2_QUEUE); 422 int rx_size = sizeof(struct qed_hw_cid_data) * 423 RESC_NUM(p_hwfn, QED_L2_QUEUE); 424 425 p_hwfn->p_tx_cids = kzalloc(tx_size, GFP_KERNEL); 426 if (!p_hwfn->p_tx_cids) 427 goto alloc_no_mem; 428 429 p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL); 430 if (!p_hwfn->p_rx_cids) 431 goto alloc_no_mem; 432 } 433 434 for_each_hwfn(cdev, i) { 435 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 436 u32 n_eqes, num_cons; 437 438 /* First allocate the context manager structure */ 439 rc = qed_cxt_mngr_alloc(p_hwfn); 440 if (rc) 441 goto alloc_err; 442 443 /* Set the HW cid/tid numbers (in the contest manager) 444 * Must be done prior to any further computations. 445 */ 446 rc = qed_cxt_set_pf_params(p_hwfn); 447 if (rc) 448 goto alloc_err; 449 450 /* Prepare and process QM requirements */ 451 rc = qed_init_qm_info(p_hwfn, true); 452 if (rc) 453 goto alloc_err; 454 455 /* Compute the ILT client partition */ 456 rc = qed_cxt_cfg_ilt_compute(p_hwfn); 457 if (rc) 458 goto alloc_err; 459 460 /* CID map / ILT shadow table / T2 461 * The talbes sizes are determined by the computations above 462 */ 463 rc = qed_cxt_tables_alloc(p_hwfn); 464 if (rc) 465 goto alloc_err; 466 467 /* SPQ, must follow ILT because initializes SPQ context */ 468 rc = qed_spq_alloc(p_hwfn); 469 if (rc) 470 goto alloc_err; 471 472 /* SP status block allocation */ 473 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn, 474 RESERVED_PTT_DPC); 475 476 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt); 477 if (rc) 478 goto alloc_err; 479 480 rc = qed_iov_alloc(p_hwfn); 481 if (rc) 482 goto alloc_err; 483 484 /* EQ */ 485 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain); 486 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) { 487 num_cons = qed_cxt_get_proto_cid_count(p_hwfn, 488 PROTOCOLID_ROCE, 489 0) * 2; 490 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB; 491 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 492 num_cons = 493 qed_cxt_get_proto_cid_count(p_hwfn, 494 PROTOCOLID_ISCSI, 0); 495 n_eqes += 2 * num_cons; 496 } 497 498 if (n_eqes > 0xFFFF) { 499 DP_ERR(p_hwfn, 500 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n", 501 n_eqes, 0xFFFF); 502 rc = -EINVAL; 503 goto alloc_err; 504 } 505 506 p_eq = qed_eq_alloc(p_hwfn, (u16) n_eqes); 507 if (!p_eq) 508 goto alloc_no_mem; 509 p_hwfn->p_eq = p_eq; 510 511 p_consq = qed_consq_alloc(p_hwfn); 512 if (!p_consq) 513 goto alloc_no_mem; 514 p_hwfn->p_consq = p_consq; 515 516 /* DMA info initialization */ 517 rc = qed_dmae_info_alloc(p_hwfn); 518 if (rc) 519 goto alloc_err; 520 521 /* DCBX initialization */ 522 rc = qed_dcbx_info_alloc(p_hwfn); 523 if (rc) 524 goto alloc_err; 525 } 526 527 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL); 528 if (!cdev->reset_stats) 529 goto alloc_no_mem; 530 531 return 0; 532 533 alloc_no_mem: 534 rc = -ENOMEM; 535 alloc_err: 536 qed_resc_free(cdev); 537 return rc; 538 } 539 540 void qed_resc_setup(struct qed_dev *cdev) 541 { 542 int i; 543 544 if (IS_VF(cdev)) 545 return; 546 547 for_each_hwfn(cdev, i) { 548 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 549 550 qed_cxt_mngr_setup(p_hwfn); 551 qed_spq_setup(p_hwfn); 552 qed_eq_setup(p_hwfn, p_hwfn->p_eq); 553 qed_consq_setup(p_hwfn, p_hwfn->p_consq); 554 555 /* Read shadow of current MFW mailbox */ 556 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); 557 memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 558 p_hwfn->mcp_info->mfw_mb_cur, 559 p_hwfn->mcp_info->mfw_mb_length); 560 561 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt); 562 563 qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt); 564 } 565 } 566 567 #define FINAL_CLEANUP_POLL_CNT (100) 568 #define FINAL_CLEANUP_POLL_TIME (10) 569 int qed_final_cleanup(struct qed_hwfn *p_hwfn, 570 struct qed_ptt *p_ptt, u16 id, bool is_vf) 571 { 572 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; 573 int rc = -EBUSY; 574 575 addr = GTT_BAR0_MAP_REG_USDM_RAM + 576 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id); 577 578 if (is_vf) 579 id += 0x10; 580 581 command |= X_FINAL_CLEANUP_AGG_INT << 582 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; 583 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; 584 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; 585 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; 586 587 /* Make sure notification is not set before initiating final cleanup */ 588 if (REG_RD(p_hwfn, addr)) { 589 DP_NOTICE(p_hwfn, 590 "Unexpected; Found final cleanup notification before initiating final cleanup\n"); 591 REG_WR(p_hwfn, addr, 0); 592 } 593 594 DP_VERBOSE(p_hwfn, QED_MSG_IOV, 595 "Sending final cleanup for PFVF[%d] [Command %08x\n]", 596 id, command); 597 598 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command); 599 600 /* Poll until completion */ 601 while (!REG_RD(p_hwfn, addr) && count--) 602 msleep(FINAL_CLEANUP_POLL_TIME); 603 604 if (REG_RD(p_hwfn, addr)) 605 rc = 0; 606 else 607 DP_NOTICE(p_hwfn, 608 "Failed to receive FW final cleanup notification\n"); 609 610 /* Cleanup afterwards */ 611 REG_WR(p_hwfn, addr, 0); 612 613 return rc; 614 } 615 616 static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn) 617 { 618 int hw_mode = 0; 619 620 hw_mode = (1 << MODE_BB_B0); 621 622 switch (p_hwfn->cdev->num_ports_in_engines) { 623 case 1: 624 hw_mode |= 1 << MODE_PORTS_PER_ENG_1; 625 break; 626 case 2: 627 hw_mode |= 1 << MODE_PORTS_PER_ENG_2; 628 break; 629 case 4: 630 hw_mode |= 1 << MODE_PORTS_PER_ENG_4; 631 break; 632 default: 633 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n", 634 p_hwfn->cdev->num_ports_in_engines); 635 return; 636 } 637 638 switch (p_hwfn->cdev->mf_mode) { 639 case QED_MF_DEFAULT: 640 case QED_MF_NPAR: 641 hw_mode |= 1 << MODE_MF_SI; 642 break; 643 case QED_MF_OVLAN: 644 hw_mode |= 1 << MODE_MF_SD; 645 break; 646 default: 647 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n"); 648 hw_mode |= 1 << MODE_MF_SI; 649 } 650 651 hw_mode |= 1 << MODE_ASIC; 652 653 if (p_hwfn->cdev->num_hwfns > 1) 654 hw_mode |= 1 << MODE_100G; 655 656 p_hwfn->hw_info.hw_mode = hw_mode; 657 658 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP), 659 "Configuring function for hw_mode: 0x%08x\n", 660 p_hwfn->hw_info.hw_mode); 661 } 662 663 /* Init run time data for all PFs on an engine. */ 664 static void qed_init_cau_rt_data(struct qed_dev *cdev) 665 { 666 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; 667 int i, sb_id; 668 669 for_each_hwfn(cdev, i) { 670 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 671 struct qed_igu_info *p_igu_info; 672 struct qed_igu_block *p_block; 673 struct cau_sb_entry sb_entry; 674 675 p_igu_info = p_hwfn->hw_info.p_igu_info; 676 677 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev); 678 sb_id++) { 679 p_block = &p_igu_info->igu_map.igu_blocks[sb_id]; 680 if (!p_block->is_pf) 681 continue; 682 683 qed_init_cau_sb_entry(p_hwfn, &sb_entry, 684 p_block->function_id, 0, 0); 685 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry); 686 } 687 } 688 } 689 690 static int qed_hw_init_common(struct qed_hwfn *p_hwfn, 691 struct qed_ptt *p_ptt, int hw_mode) 692 { 693 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 694 struct qed_qm_common_rt_init_params params; 695 struct qed_dev *cdev = p_hwfn->cdev; 696 u16 num_pfs, pf_id; 697 u32 concrete_fid; 698 int rc = 0; 699 u8 vf_id; 700 701 qed_init_cau_rt_data(cdev); 702 703 /* Program GTT windows */ 704 qed_gtt_init(p_hwfn); 705 706 if (p_hwfn->mcp_info) { 707 if (p_hwfn->mcp_info->func_info.bandwidth_max) 708 qm_info->pf_rl_en = 1; 709 if (p_hwfn->mcp_info->func_info.bandwidth_min) 710 qm_info->pf_wfq_en = 1; 711 } 712 713 memset(¶ms, 0, sizeof(params)); 714 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines; 715 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; 716 params.pf_rl_en = qm_info->pf_rl_en; 717 params.pf_wfq_en = qm_info->pf_wfq_en; 718 params.vport_rl_en = qm_info->vport_rl_en; 719 params.vport_wfq_en = qm_info->vport_wfq_en; 720 params.port_params = qm_info->qm_port_params; 721 722 qed_qm_common_rt_init(p_hwfn, ¶ms); 723 724 qed_cxt_hw_init_common(p_hwfn); 725 726 /* Close gate from NIG to BRB/Storm; By default they are open, but 727 * we close them to prevent NIG from passing data to reset blocks. 728 * Should have been done in the ENGINE phase, but init-tool lacks 729 * proper port-pretend capabilities. 730 */ 731 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); 732 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); 733 qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1); 734 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); 735 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); 736 qed_port_unpretend(p_hwfn, p_ptt); 737 738 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode); 739 if (rc) 740 return rc; 741 742 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); 743 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); 744 745 if (QED_IS_BB(p_hwfn->cdev)) { 746 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev); 747 for (pf_id = 0; pf_id < num_pfs; pf_id++) { 748 qed_fid_pretend(p_hwfn, p_ptt, pf_id); 749 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 750 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 751 } 752 /* pretend to original PF */ 753 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 754 } 755 756 for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) { 757 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id); 758 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid); 759 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1); 760 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0); 761 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1); 762 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0); 763 } 764 /* pretend to original PF */ 765 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 766 767 return rc; 768 } 769 770 static int qed_hw_init_port(struct qed_hwfn *p_hwfn, 771 struct qed_ptt *p_ptt, int hw_mode) 772 { 773 return qed_init_run(p_hwfn, p_ptt, PHASE_PORT, 774 p_hwfn->port_id, hw_mode); 775 } 776 777 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, 778 struct qed_ptt *p_ptt, 779 struct qed_tunn_start_params *p_tunn, 780 int hw_mode, 781 bool b_hw_start, 782 enum qed_int_mode int_mode, 783 bool allow_npar_tx_switch) 784 { 785 u8 rel_pf_id = p_hwfn->rel_pf_id; 786 int rc = 0; 787 788 if (p_hwfn->mcp_info) { 789 struct qed_mcp_function_info *p_info; 790 791 p_info = &p_hwfn->mcp_info->func_info; 792 if (p_info->bandwidth_min) 793 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; 794 795 /* Update rate limit once we'll actually have a link */ 796 p_hwfn->qm_info.pf_rl = 100000; 797 } 798 799 qed_cxt_hw_init_pf(p_hwfn); 800 801 qed_int_igu_init_rt(p_hwfn); 802 803 /* Set VLAN in NIG if needed */ 804 if (hw_mode & BIT(MODE_MF_SD)) { 805 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n"); 806 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); 807 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, 808 p_hwfn->hw_info.ovlan); 809 } 810 811 /* Enable classification by MAC if needed */ 812 if (hw_mode & BIT(MODE_MF_SI)) { 813 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 814 "Configuring TAGMAC_CLS_TYPE\n"); 815 STORE_RT_REG(p_hwfn, 816 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1); 817 } 818 819 /* Protocl Configuration */ 820 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 821 (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0); 822 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0); 823 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); 824 825 /* Cleanup chip from previous driver if such remains exist */ 826 rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false); 827 if (rc) 828 return rc; 829 830 /* PF Init sequence */ 831 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); 832 if (rc) 833 return rc; 834 835 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ 836 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); 837 if (rc) 838 return rc; 839 840 /* Pure runtime initializations - directly to the HW */ 841 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); 842 843 if (b_hw_start) { 844 /* enable interrupts */ 845 qed_int_igu_enable(p_hwfn, p_ptt, int_mode); 846 847 /* send function start command */ 848 rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode, 849 allow_npar_tx_switch); 850 if (rc) 851 DP_NOTICE(p_hwfn, "Function start ramrod failed\n"); 852 } 853 return rc; 854 } 855 856 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn, 857 struct qed_ptt *p_ptt, 858 u8 enable) 859 { 860 u32 delay_idx = 0, val, set_val = enable ? 1 : 0; 861 862 /* Change PF in PXP */ 863 qed_wr(p_hwfn, p_ptt, 864 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); 865 866 /* wait until value is set - try for 1 second every 50us */ 867 for (delay_idx = 0; delay_idx < 20000; delay_idx++) { 868 val = qed_rd(p_hwfn, p_ptt, 869 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 870 if (val == set_val) 871 break; 872 873 usleep_range(50, 60); 874 } 875 876 if (val != set_val) { 877 DP_NOTICE(p_hwfn, 878 "PFID_ENABLE_MASTER wasn't changed after a second\n"); 879 return -EAGAIN; 880 } 881 882 return 0; 883 } 884 885 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn, 886 struct qed_ptt *p_main_ptt) 887 { 888 /* Read shadow of current MFW mailbox */ 889 qed_mcp_read_mb(p_hwfn, p_main_ptt); 890 memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 891 p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length); 892 } 893 894 int qed_hw_init(struct qed_dev *cdev, 895 struct qed_tunn_start_params *p_tunn, 896 bool b_hw_start, 897 enum qed_int_mode int_mode, 898 bool allow_npar_tx_switch, 899 const u8 *bin_fw_data) 900 { 901 u32 load_code, param; 902 int rc, mfw_rc, i; 903 904 if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 905 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 906 return -EINVAL; 907 } 908 909 if (IS_PF(cdev)) { 910 rc = qed_init_fw_data(cdev, bin_fw_data); 911 if (rc) 912 return rc; 913 } 914 915 for_each_hwfn(cdev, i) { 916 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 917 918 if (IS_VF(cdev)) { 919 p_hwfn->b_int_enabled = 1; 920 continue; 921 } 922 923 /* Enable DMAE in PXP */ 924 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true); 925 926 qed_calc_hw_mode(p_hwfn); 927 928 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code); 929 if (rc) { 930 DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n"); 931 return rc; 932 } 933 934 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); 935 936 DP_VERBOSE(p_hwfn, QED_MSG_SP, 937 "Load request was sent. Resp:0x%x, Load code: 0x%x\n", 938 rc, load_code); 939 940 p_hwfn->first_on_engine = (load_code == 941 FW_MSG_CODE_DRV_LOAD_ENGINE); 942 943 switch (load_code) { 944 case FW_MSG_CODE_DRV_LOAD_ENGINE: 945 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, 946 p_hwfn->hw_info.hw_mode); 947 if (rc) 948 break; 949 /* Fall into */ 950 case FW_MSG_CODE_DRV_LOAD_PORT: 951 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, 952 p_hwfn->hw_info.hw_mode); 953 if (rc) 954 break; 955 956 /* Fall into */ 957 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 958 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, 959 p_tunn, p_hwfn->hw_info.hw_mode, 960 b_hw_start, int_mode, 961 allow_npar_tx_switch); 962 break; 963 default: 964 rc = -EINVAL; 965 break; 966 } 967 968 if (rc) 969 DP_NOTICE(p_hwfn, 970 "init phase failed for loadcode 0x%x (rc %d)\n", 971 load_code, rc); 972 973 /* ACK mfw regardless of success or failure of initialization */ 974 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 975 DRV_MSG_CODE_LOAD_DONE, 976 0, &load_code, ¶m); 977 if (rc) 978 return rc; 979 if (mfw_rc) { 980 DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n"); 981 return mfw_rc; 982 } 983 984 /* send DCBX attention request command */ 985 DP_VERBOSE(p_hwfn, 986 QED_MSG_DCB, 987 "sending phony dcbx set command to trigger DCBx attention handling\n"); 988 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 989 DRV_MSG_CODE_SET_DCBX, 990 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, 991 &load_code, ¶m); 992 if (mfw_rc) { 993 DP_NOTICE(p_hwfn, 994 "Failed to send DCBX attention request\n"); 995 return mfw_rc; 996 } 997 998 p_hwfn->hw_init_done = true; 999 } 1000 1001 return 0; 1002 } 1003 1004 #define QED_HW_STOP_RETRY_LIMIT (10) 1005 static void qed_hw_timers_stop(struct qed_dev *cdev, 1006 struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1007 { 1008 int i; 1009 1010 /* close timers */ 1011 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); 1012 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); 1013 1014 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) { 1015 if ((!qed_rd(p_hwfn, p_ptt, 1016 TM_REG_PF_SCAN_ACTIVE_CONN)) && 1017 (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK))) 1018 break; 1019 1020 /* Dependent on number of connection/tasks, possibly 1021 * 1ms sleep is required between polls 1022 */ 1023 usleep_range(1000, 2000); 1024 } 1025 1026 if (i < QED_HW_STOP_RETRY_LIMIT) 1027 return; 1028 1029 DP_NOTICE(p_hwfn, 1030 "Timers linear scans are not over [Connection %02x Tasks %02x]\n", 1031 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN), 1032 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)); 1033 } 1034 1035 void qed_hw_timers_stop_all(struct qed_dev *cdev) 1036 { 1037 int j; 1038 1039 for_each_hwfn(cdev, j) { 1040 struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 1041 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 1042 1043 qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 1044 } 1045 } 1046 1047 int qed_hw_stop(struct qed_dev *cdev) 1048 { 1049 int rc = 0, t_rc; 1050 int j; 1051 1052 for_each_hwfn(cdev, j) { 1053 struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 1054 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 1055 1056 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n"); 1057 1058 if (IS_VF(cdev)) { 1059 qed_vf_pf_int_cleanup(p_hwfn); 1060 continue; 1061 } 1062 1063 /* mark the hw as uninitialized... */ 1064 p_hwfn->hw_init_done = false; 1065 1066 rc = qed_sp_pf_stop(p_hwfn); 1067 if (rc) 1068 DP_NOTICE(p_hwfn, 1069 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n"); 1070 1071 qed_wr(p_hwfn, p_ptt, 1072 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1073 1074 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1075 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1076 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1077 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1078 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1079 1080 qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 1081 1082 /* Disable Attention Generation */ 1083 qed_int_igu_disable_int(p_hwfn, p_ptt); 1084 1085 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); 1086 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); 1087 1088 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); 1089 1090 /* Need to wait 1ms to guarantee SBs are cleared */ 1091 usleep_range(1000, 2000); 1092 } 1093 1094 if (IS_PF(cdev)) { 1095 /* Disable DMAE in PXP - in CMT, this should only be done for 1096 * first hw-function, and only after all transactions have 1097 * stopped for all active hw-functions. 1098 */ 1099 t_rc = qed_change_pci_hwfn(&cdev->hwfns[0], 1100 cdev->hwfns[0].p_main_ptt, false); 1101 if (t_rc != 0) 1102 rc = t_rc; 1103 } 1104 1105 return rc; 1106 } 1107 1108 void qed_hw_stop_fastpath(struct qed_dev *cdev) 1109 { 1110 int j; 1111 1112 for_each_hwfn(cdev, j) { 1113 struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 1114 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 1115 1116 if (IS_VF(cdev)) { 1117 qed_vf_pf_int_cleanup(p_hwfn); 1118 continue; 1119 } 1120 1121 DP_VERBOSE(p_hwfn, 1122 NETIF_MSG_IFDOWN, "Shutting down the fastpath\n"); 1123 1124 qed_wr(p_hwfn, p_ptt, 1125 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1126 1127 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1128 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1129 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1130 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1131 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1132 1133 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); 1134 1135 /* Need to wait 1ms to guarantee SBs are cleared */ 1136 usleep_range(1000, 2000); 1137 } 1138 } 1139 1140 void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn) 1141 { 1142 if (IS_VF(p_hwfn->cdev)) 1143 return; 1144 1145 /* Re-open incoming traffic */ 1146 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1147 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); 1148 } 1149 1150 static int qed_reg_assert(struct qed_hwfn *p_hwfn, 1151 struct qed_ptt *p_ptt, u32 reg, bool expected) 1152 { 1153 u32 assert_val = qed_rd(p_hwfn, p_ptt, reg); 1154 1155 if (assert_val != expected) { 1156 DP_NOTICE(p_hwfn, "Value at address 0x%08x != 0x%08x\n", 1157 reg, expected); 1158 return -EINVAL; 1159 } 1160 1161 return 0; 1162 } 1163 1164 int qed_hw_reset(struct qed_dev *cdev) 1165 { 1166 int rc = 0; 1167 u32 unload_resp, unload_param; 1168 int i; 1169 1170 for_each_hwfn(cdev, i) { 1171 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1172 1173 if (IS_VF(cdev)) { 1174 rc = qed_vf_pf_reset(p_hwfn); 1175 if (rc) 1176 return rc; 1177 continue; 1178 } 1179 1180 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n"); 1181 1182 /* Check for incorrect states */ 1183 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt, 1184 QM_REG_USG_CNT_PF_TX, 0); 1185 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt, 1186 QM_REG_USG_CNT_PF_OTHER, 0); 1187 1188 /* Disable PF in HW blocks */ 1189 qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0); 1190 qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0); 1191 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1192 TCFC_REG_STRONG_ENABLE_PF, 0); 1193 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1194 CCFC_REG_STRONG_ENABLE_PF, 0); 1195 1196 /* Send unload command to MCP */ 1197 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1198 DRV_MSG_CODE_UNLOAD_REQ, 1199 DRV_MB_PARAM_UNLOAD_WOL_MCP, 1200 &unload_resp, &unload_param); 1201 if (rc) { 1202 DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n"); 1203 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE; 1204 } 1205 1206 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1207 DRV_MSG_CODE_UNLOAD_DONE, 1208 0, &unload_resp, &unload_param); 1209 if (rc) { 1210 DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n"); 1211 return rc; 1212 } 1213 } 1214 1215 return rc; 1216 } 1217 1218 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ 1219 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn) 1220 { 1221 qed_ptt_pool_free(p_hwfn); 1222 kfree(p_hwfn->hw_info.p_igu_info); 1223 } 1224 1225 /* Setup bar access */ 1226 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn) 1227 { 1228 /* clear indirect access */ 1229 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0); 1230 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0); 1231 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0); 1232 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0); 1233 1234 /* Clean Previous errors if such exist */ 1235 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1236 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id); 1237 1238 /* enable internal target-read */ 1239 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1240 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1241 } 1242 1243 static void get_function_id(struct qed_hwfn *p_hwfn) 1244 { 1245 /* ME Register */ 1246 p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn, 1247 PXP_PF_ME_OPAQUE_ADDR); 1248 1249 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); 1250 1251 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; 1252 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 1253 PXP_CONCRETE_FID_PFID); 1254 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 1255 PXP_CONCRETE_FID_PORT); 1256 1257 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 1258 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n", 1259 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid); 1260 } 1261 1262 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn) 1263 { 1264 u32 *feat_num = p_hwfn->hw_info.feat_num; 1265 int num_features = 1; 1266 1267 feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) / 1268 num_features, 1269 RESC_NUM(p_hwfn, QED_L2_QUEUE)); 1270 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 1271 "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n", 1272 feat_num[QED_PF_L2_QUE], RESC_NUM(p_hwfn, QED_SB), 1273 num_features); 1274 } 1275 1276 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn) 1277 { 1278 u8 enabled_func_idx = p_hwfn->enabled_func_idx; 1279 u32 *resc_start = p_hwfn->hw_info.resc_start; 1280 u8 num_funcs = p_hwfn->num_funcs_on_engine; 1281 u32 *resc_num = p_hwfn->hw_info.resc_num; 1282 struct qed_sb_cnt_info sb_cnt_info; 1283 int i, max_vf_vlan_filters; 1284 1285 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); 1286 1287 #ifdef CONFIG_QED_SRIOV 1288 max_vf_vlan_filters = QED_ETH_MAX_VF_NUM_VLAN_FILTERS; 1289 #else 1290 max_vf_vlan_filters = 0; 1291 #endif 1292 1293 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info); 1294 1295 resc_num[QED_SB] = min_t(u32, 1296 (MAX_SB_PER_PATH_BB / num_funcs), 1297 sb_cnt_info.sb_cnt); 1298 resc_num[QED_L2_QUEUE] = MAX_NUM_L2_QUEUES_BB / num_funcs; 1299 resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs; 1300 resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs; 1301 resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs; 1302 resc_num[QED_RL] = min_t(u32, 64, resc_num[QED_VPORT]); 1303 resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs; 1304 resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) / 1305 num_funcs; 1306 resc_num[QED_ILT] = PXP_NUM_ILT_RECORDS_BB / num_funcs; 1307 1308 for (i = 0; i < QED_MAX_RESC; i++) 1309 resc_start[i] = resc_num[i] * enabled_func_idx; 1310 1311 /* Sanity for ILT */ 1312 if (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB) { 1313 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n", 1314 RESC_START(p_hwfn, QED_ILT), 1315 RESC_END(p_hwfn, QED_ILT) - 1); 1316 return -EINVAL; 1317 } 1318 1319 qed_hw_set_feat(p_hwfn); 1320 1321 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 1322 "The numbers for each resource are:\n" 1323 "SB = %d start = %d\n" 1324 "L2_QUEUE = %d start = %d\n" 1325 "VPORT = %d start = %d\n" 1326 "PQ = %d start = %d\n" 1327 "RL = %d start = %d\n" 1328 "MAC = %d start = %d\n" 1329 "VLAN = %d start = %d\n" 1330 "ILT = %d start = %d\n", 1331 p_hwfn->hw_info.resc_num[QED_SB], 1332 p_hwfn->hw_info.resc_start[QED_SB], 1333 p_hwfn->hw_info.resc_num[QED_L2_QUEUE], 1334 p_hwfn->hw_info.resc_start[QED_L2_QUEUE], 1335 p_hwfn->hw_info.resc_num[QED_VPORT], 1336 p_hwfn->hw_info.resc_start[QED_VPORT], 1337 p_hwfn->hw_info.resc_num[QED_PQ], 1338 p_hwfn->hw_info.resc_start[QED_PQ], 1339 p_hwfn->hw_info.resc_num[QED_RL], 1340 p_hwfn->hw_info.resc_start[QED_RL], 1341 p_hwfn->hw_info.resc_num[QED_MAC], 1342 p_hwfn->hw_info.resc_start[QED_MAC], 1343 p_hwfn->hw_info.resc_num[QED_VLAN], 1344 p_hwfn->hw_info.resc_start[QED_VLAN], 1345 p_hwfn->hw_info.resc_num[QED_ILT], 1346 p_hwfn->hw_info.resc_start[QED_ILT]); 1347 1348 return 0; 1349 } 1350 1351 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1352 { 1353 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg; 1354 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities; 1355 struct qed_mcp_link_params *link; 1356 1357 /* Read global nvm_cfg address */ 1358 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 1359 1360 /* Verify MCP has initialized it */ 1361 if (!nvm_cfg_addr) { 1362 DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 1363 return -EINVAL; 1364 } 1365 1366 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ 1367 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 1368 1369 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1370 offsetof(struct nvm_cfg1, glob) + 1371 offsetof(struct nvm_cfg1_glob, core_cfg); 1372 1373 core_cfg = qed_rd(p_hwfn, p_ptt, addr); 1374 1375 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> 1376 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { 1377 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G: 1378 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G; 1379 break; 1380 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G: 1381 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G; 1382 break; 1383 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G: 1384 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G; 1385 break; 1386 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F: 1387 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F; 1388 break; 1389 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E: 1390 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E; 1391 break; 1392 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G: 1393 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G; 1394 break; 1395 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G: 1396 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G; 1397 break; 1398 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G: 1399 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G; 1400 break; 1401 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G: 1402 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G; 1403 break; 1404 default: 1405 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg); 1406 break; 1407 } 1408 1409 /* Read default link configuration */ 1410 link = &p_hwfn->mcp_info->link_input; 1411 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1412 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 1413 link_temp = qed_rd(p_hwfn, p_ptt, 1414 port_cfg_addr + 1415 offsetof(struct nvm_cfg1_port, speed_cap_mask)); 1416 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; 1417 link->speed.advertised_speeds = link_temp; 1418 1419 link_temp = link->speed.advertised_speeds; 1420 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp; 1421 1422 link_temp = qed_rd(p_hwfn, p_ptt, 1423 port_cfg_addr + 1424 offsetof(struct nvm_cfg1_port, link_settings)); 1425 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> 1426 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { 1427 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: 1428 link->speed.autoneg = true; 1429 break; 1430 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: 1431 link->speed.forced_speed = 1000; 1432 break; 1433 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: 1434 link->speed.forced_speed = 10000; 1435 break; 1436 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: 1437 link->speed.forced_speed = 25000; 1438 break; 1439 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: 1440 link->speed.forced_speed = 40000; 1441 break; 1442 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: 1443 link->speed.forced_speed = 50000; 1444 break; 1445 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G: 1446 link->speed.forced_speed = 100000; 1447 break; 1448 default: 1449 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp); 1450 } 1451 1452 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK; 1453 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET; 1454 link->pause.autoneg = !!(link_temp & 1455 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); 1456 link->pause.forced_rx = !!(link_temp & 1457 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); 1458 link->pause.forced_tx = !!(link_temp & 1459 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); 1460 link->loopback_mode = 0; 1461 1462 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1463 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n", 1464 link->speed.forced_speed, link->speed.advertised_speeds, 1465 link->speed.autoneg, link->pause.autoneg); 1466 1467 /* Read Multi-function information from shmem */ 1468 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1469 offsetof(struct nvm_cfg1, glob) + 1470 offsetof(struct nvm_cfg1_glob, generic_cont0); 1471 1472 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr); 1473 1474 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> 1475 NVM_CFG1_GLOB_MF_MODE_OFFSET; 1476 1477 switch (mf_mode) { 1478 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: 1479 p_hwfn->cdev->mf_mode = QED_MF_OVLAN; 1480 break; 1481 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: 1482 p_hwfn->cdev->mf_mode = QED_MF_NPAR; 1483 break; 1484 case NVM_CFG1_GLOB_MF_MODE_DEFAULT: 1485 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT; 1486 break; 1487 } 1488 DP_INFO(p_hwfn, "Multi function mode is %08x\n", 1489 p_hwfn->cdev->mf_mode); 1490 1491 /* Read Multi-function information from shmem */ 1492 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1493 offsetof(struct nvm_cfg1, glob) + 1494 offsetof(struct nvm_cfg1_glob, device_capabilities); 1495 1496 device_capabilities = qed_rd(p_hwfn, p_ptt, addr); 1497 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) 1498 __set_bit(QED_DEV_CAP_ETH, 1499 &p_hwfn->hw_info.device_capabilities); 1500 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI) 1501 __set_bit(QED_DEV_CAP_ISCSI, 1502 &p_hwfn->hw_info.device_capabilities); 1503 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE) 1504 __set_bit(QED_DEV_CAP_ROCE, 1505 &p_hwfn->hw_info.device_capabilities); 1506 1507 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt); 1508 } 1509 1510 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1511 { 1512 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id; 1513 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask; 1514 1515 num_funcs = MAX_NUM_PFS_BB; 1516 1517 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values 1518 * in the other bits are selected. 1519 * Bits 1-15 are for functions 1-15, respectively, and their value is 1520 * '0' only for enabled functions (function 0 always exists and 1521 * enabled). 1522 * In case of CMT, only the "even" functions are enabled, and thus the 1523 * number of functions for both hwfns is learnt from the same bits. 1524 */ 1525 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE); 1526 1527 if (reg_function_hide & 0x1) { 1528 if (QED_PATH_ID(p_hwfn) && p_hwfn->cdev->num_hwfns == 1) { 1529 num_funcs = 0; 1530 eng_mask = 0xaaaa; 1531 } else { 1532 num_funcs = 1; 1533 eng_mask = 0x5554; 1534 } 1535 1536 /* Get the number of the enabled functions on the engine */ 1537 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask; 1538 while (tmp) { 1539 if (tmp & 0x1) 1540 num_funcs++; 1541 tmp >>= 0x1; 1542 } 1543 1544 /* Get the PF index within the enabled functions */ 1545 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1; 1546 tmp = reg_function_hide & eng_mask & low_pfs_mask; 1547 while (tmp) { 1548 if (tmp & 0x1) 1549 enabled_func_idx--; 1550 tmp >>= 0x1; 1551 } 1552 } 1553 1554 p_hwfn->num_funcs_on_engine = num_funcs; 1555 p_hwfn->enabled_func_idx = enabled_func_idx; 1556 1557 DP_VERBOSE(p_hwfn, 1558 NETIF_MSG_PROBE, 1559 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n", 1560 p_hwfn->rel_pf_id, 1561 p_hwfn->abs_pf_id, 1562 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine); 1563 } 1564 1565 static int 1566 qed_get_hw_info(struct qed_hwfn *p_hwfn, 1567 struct qed_ptt *p_ptt, 1568 enum qed_pci_personality personality) 1569 { 1570 u32 port_mode; 1571 int rc; 1572 1573 /* Since all information is common, only first hwfns should do this */ 1574 if (IS_LEAD_HWFN(p_hwfn)) { 1575 rc = qed_iov_hw_info(p_hwfn); 1576 if (rc) 1577 return rc; 1578 } 1579 1580 /* Read the port mode */ 1581 port_mode = qed_rd(p_hwfn, p_ptt, 1582 CNIG_REG_NW_PORT_MODE_BB_B0); 1583 1584 if (port_mode < 3) { 1585 p_hwfn->cdev->num_ports_in_engines = 1; 1586 } else if (port_mode <= 5) { 1587 p_hwfn->cdev->num_ports_in_engines = 2; 1588 } else { 1589 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n", 1590 p_hwfn->cdev->num_ports_in_engines); 1591 1592 /* Default num_ports_in_engines to something */ 1593 p_hwfn->cdev->num_ports_in_engines = 1; 1594 } 1595 1596 qed_hw_get_nvm_info(p_hwfn, p_ptt); 1597 1598 rc = qed_int_igu_read_cam(p_hwfn, p_ptt); 1599 if (rc) 1600 return rc; 1601 1602 if (qed_mcp_is_init(p_hwfn)) 1603 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr, 1604 p_hwfn->mcp_info->func_info.mac); 1605 else 1606 eth_random_addr(p_hwfn->hw_info.hw_mac_addr); 1607 1608 if (qed_mcp_is_init(p_hwfn)) { 1609 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET) 1610 p_hwfn->hw_info.ovlan = 1611 p_hwfn->mcp_info->func_info.ovlan; 1612 1613 qed_mcp_cmd_port_init(p_hwfn, p_ptt); 1614 } 1615 1616 if (qed_mcp_is_init(p_hwfn)) { 1617 enum qed_pci_personality protocol; 1618 1619 protocol = p_hwfn->mcp_info->func_info.protocol; 1620 p_hwfn->hw_info.personality = protocol; 1621 } 1622 1623 qed_get_num_funcs(p_hwfn, p_ptt); 1624 1625 return qed_hw_get_resc(p_hwfn); 1626 } 1627 1628 static int qed_get_dev_info(struct qed_dev *cdev) 1629 { 1630 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 1631 u32 tmp; 1632 1633 /* Read Vendor Id / Device Id */ 1634 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id); 1635 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id); 1636 1637 cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, 1638 MISCS_REG_CHIP_NUM); 1639 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, 1640 MISCS_REG_CHIP_REV); 1641 MASK_FIELD(CHIP_REV, cdev->chip_rev); 1642 1643 cdev->type = QED_DEV_TYPE_BB; 1644 /* Learn number of HW-functions */ 1645 tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt, 1646 MISCS_REG_CMT_ENABLED_FOR_PAIR); 1647 1648 if (tmp & (1 << p_hwfn->rel_pf_id)) { 1649 DP_NOTICE(cdev->hwfns, "device in CMT mode\n"); 1650 cdev->num_hwfns = 2; 1651 } else { 1652 cdev->num_hwfns = 1; 1653 } 1654 1655 cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt, 1656 MISCS_REG_CHIP_TEST_REG) >> 4; 1657 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id); 1658 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, 1659 MISCS_REG_CHIP_METAL); 1660 MASK_FIELD(CHIP_METAL, cdev->chip_metal); 1661 1662 DP_INFO(cdev->hwfns, 1663 "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n", 1664 cdev->chip_num, cdev->chip_rev, 1665 cdev->chip_bond_id, cdev->chip_metal); 1666 1667 if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) { 1668 DP_NOTICE(cdev->hwfns, 1669 "The chip type/rev (BB A0) is not supported!\n"); 1670 return -EINVAL; 1671 } 1672 1673 return 0; 1674 } 1675 1676 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn, 1677 void __iomem *p_regview, 1678 void __iomem *p_doorbells, 1679 enum qed_pci_personality personality) 1680 { 1681 int rc = 0; 1682 1683 /* Split PCI bars evenly between hwfns */ 1684 p_hwfn->regview = p_regview; 1685 p_hwfn->doorbells = p_doorbells; 1686 1687 if (IS_VF(p_hwfn->cdev)) 1688 return qed_vf_hw_prepare(p_hwfn); 1689 1690 /* Validate that chip access is feasible */ 1691 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { 1692 DP_ERR(p_hwfn, 1693 "Reading the ME register returns all Fs; Preventing further chip access\n"); 1694 return -EINVAL; 1695 } 1696 1697 get_function_id(p_hwfn); 1698 1699 /* Allocate PTT pool */ 1700 rc = qed_ptt_pool_alloc(p_hwfn); 1701 if (rc) 1702 goto err0; 1703 1704 /* Allocate the main PTT */ 1705 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); 1706 1707 /* First hwfn learns basic information, e.g., number of hwfns */ 1708 if (!p_hwfn->my_id) { 1709 rc = qed_get_dev_info(p_hwfn->cdev); 1710 if (rc) 1711 goto err1; 1712 } 1713 1714 qed_hw_hwfn_prepare(p_hwfn); 1715 1716 /* Initialize MCP structure */ 1717 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); 1718 if (rc) { 1719 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n"); 1720 goto err1; 1721 } 1722 1723 /* Read the device configuration information from the HW and SHMEM */ 1724 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality); 1725 if (rc) { 1726 DP_NOTICE(p_hwfn, "Failed to get HW information\n"); 1727 goto err2; 1728 } 1729 1730 /* Allocate the init RT array and initialize the init-ops engine */ 1731 rc = qed_init_alloc(p_hwfn); 1732 if (rc) 1733 goto err2; 1734 1735 return rc; 1736 err2: 1737 if (IS_LEAD_HWFN(p_hwfn)) 1738 qed_iov_free_hw_info(p_hwfn->cdev); 1739 qed_mcp_free(p_hwfn); 1740 err1: 1741 qed_hw_hwfn_free(p_hwfn); 1742 err0: 1743 return rc; 1744 } 1745 1746 int qed_hw_prepare(struct qed_dev *cdev, 1747 int personality) 1748 { 1749 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 1750 int rc; 1751 1752 /* Store the precompiled init data ptrs */ 1753 if (IS_PF(cdev)) 1754 qed_init_iro_array(cdev); 1755 1756 /* Initialize the first hwfn - will learn number of hwfns */ 1757 rc = qed_hw_prepare_single(p_hwfn, 1758 cdev->regview, 1759 cdev->doorbells, personality); 1760 if (rc) 1761 return rc; 1762 1763 personality = p_hwfn->hw_info.personality; 1764 1765 /* Initialize the rest of the hwfns */ 1766 if (cdev->num_hwfns > 1) { 1767 void __iomem *p_regview, *p_doorbell; 1768 u8 __iomem *addr; 1769 1770 /* adjust bar offset for second engine */ 1771 addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2; 1772 p_regview = addr; 1773 1774 /* adjust doorbell bar offset for second engine */ 1775 addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2; 1776 p_doorbell = addr; 1777 1778 /* prepare second hw function */ 1779 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview, 1780 p_doorbell, personality); 1781 1782 /* in case of error, need to free the previously 1783 * initiliazed hwfn 0. 1784 */ 1785 if (rc) { 1786 if (IS_PF(cdev)) { 1787 qed_init_free(p_hwfn); 1788 qed_mcp_free(p_hwfn); 1789 qed_hw_hwfn_free(p_hwfn); 1790 } 1791 } 1792 } 1793 1794 return rc; 1795 } 1796 1797 void qed_hw_remove(struct qed_dev *cdev) 1798 { 1799 int i; 1800 1801 for_each_hwfn(cdev, i) { 1802 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1803 1804 if (IS_VF(cdev)) { 1805 qed_vf_pf_release(p_hwfn); 1806 continue; 1807 } 1808 1809 qed_init_free(p_hwfn); 1810 qed_hw_hwfn_free(p_hwfn); 1811 qed_mcp_free(p_hwfn); 1812 } 1813 1814 qed_iov_free_hw_info(cdev); 1815 } 1816 1817 static void qed_chain_free_next_ptr(struct qed_dev *cdev, 1818 struct qed_chain *p_chain) 1819 { 1820 void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL; 1821 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0; 1822 struct qed_chain_next *p_next; 1823 u32 size, i; 1824 1825 if (!p_virt) 1826 return; 1827 1828 size = p_chain->elem_size * p_chain->usable_per_page; 1829 1830 for (i = 0; i < p_chain->page_cnt; i++) { 1831 if (!p_virt) 1832 break; 1833 1834 p_next = (struct qed_chain_next *)((u8 *)p_virt + size); 1835 p_virt_next = p_next->next_virt; 1836 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys); 1837 1838 dma_free_coherent(&cdev->pdev->dev, 1839 QED_CHAIN_PAGE_SIZE, p_virt, p_phys); 1840 1841 p_virt = p_virt_next; 1842 p_phys = p_phys_next; 1843 } 1844 } 1845 1846 static void qed_chain_free_single(struct qed_dev *cdev, 1847 struct qed_chain *p_chain) 1848 { 1849 if (!p_chain->p_virt_addr) 1850 return; 1851 1852 dma_free_coherent(&cdev->pdev->dev, 1853 QED_CHAIN_PAGE_SIZE, 1854 p_chain->p_virt_addr, p_chain->p_phys_addr); 1855 } 1856 1857 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain) 1858 { 1859 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl; 1860 u32 page_cnt = p_chain->page_cnt, i, pbl_size; 1861 u8 *p_pbl_virt = p_chain->pbl.p_virt_table; 1862 1863 if (!pp_virt_addr_tbl) 1864 return; 1865 1866 if (!p_chain->pbl.p_virt_table) 1867 goto out; 1868 1869 for (i = 0; i < page_cnt; i++) { 1870 if (!pp_virt_addr_tbl[i]) 1871 break; 1872 1873 dma_free_coherent(&cdev->pdev->dev, 1874 QED_CHAIN_PAGE_SIZE, 1875 pp_virt_addr_tbl[i], 1876 *(dma_addr_t *)p_pbl_virt); 1877 1878 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 1879 } 1880 1881 pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 1882 dma_free_coherent(&cdev->pdev->dev, 1883 pbl_size, 1884 p_chain->pbl.p_virt_table, p_chain->pbl.p_phys_table); 1885 out: 1886 vfree(p_chain->pbl.pp_virt_addr_tbl); 1887 } 1888 1889 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain) 1890 { 1891 switch (p_chain->mode) { 1892 case QED_CHAIN_MODE_NEXT_PTR: 1893 qed_chain_free_next_ptr(cdev, p_chain); 1894 break; 1895 case QED_CHAIN_MODE_SINGLE: 1896 qed_chain_free_single(cdev, p_chain); 1897 break; 1898 case QED_CHAIN_MODE_PBL: 1899 qed_chain_free_pbl(cdev, p_chain); 1900 break; 1901 } 1902 } 1903 1904 static int 1905 qed_chain_alloc_sanity_check(struct qed_dev *cdev, 1906 enum qed_chain_cnt_type cnt_type, 1907 size_t elem_size, u32 page_cnt) 1908 { 1909 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt; 1910 1911 /* The actual chain size can be larger than the maximal possible value 1912 * after rounding up the requested elements number to pages, and after 1913 * taking into acount the unusuable elements (next-ptr elements). 1914 * The size of a "u16" chain can be (U16_MAX + 1) since the chain 1915 * size/capacity fields are of a u32 type. 1916 */ 1917 if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 && 1918 chain_size > 0x10000) || 1919 (cnt_type == QED_CHAIN_CNT_TYPE_U32 && 1920 chain_size > 0x100000000ULL)) { 1921 DP_NOTICE(cdev, 1922 "The actual chain size (0x%llx) is larger than the maximal possible value\n", 1923 chain_size); 1924 return -EINVAL; 1925 } 1926 1927 return 0; 1928 } 1929 1930 static int 1931 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain) 1932 { 1933 void *p_virt = NULL, *p_virt_prev = NULL; 1934 dma_addr_t p_phys = 0; 1935 u32 i; 1936 1937 for (i = 0; i < p_chain->page_cnt; i++) { 1938 p_virt = dma_alloc_coherent(&cdev->pdev->dev, 1939 QED_CHAIN_PAGE_SIZE, 1940 &p_phys, GFP_KERNEL); 1941 if (!p_virt) 1942 return -ENOMEM; 1943 1944 if (i == 0) { 1945 qed_chain_init_mem(p_chain, p_virt, p_phys); 1946 qed_chain_reset(p_chain); 1947 } else { 1948 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 1949 p_virt, p_phys); 1950 } 1951 1952 p_virt_prev = p_virt; 1953 } 1954 /* Last page's next element should point to the beginning of the 1955 * chain. 1956 */ 1957 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 1958 p_chain->p_virt_addr, 1959 p_chain->p_phys_addr); 1960 1961 return 0; 1962 } 1963 1964 static int 1965 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain) 1966 { 1967 dma_addr_t p_phys = 0; 1968 void *p_virt = NULL; 1969 1970 p_virt = dma_alloc_coherent(&cdev->pdev->dev, 1971 QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL); 1972 if (!p_virt) 1973 return -ENOMEM; 1974 1975 qed_chain_init_mem(p_chain, p_virt, p_phys); 1976 qed_chain_reset(p_chain); 1977 1978 return 0; 1979 } 1980 1981 static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain) 1982 { 1983 u32 page_cnt = p_chain->page_cnt, size, i; 1984 dma_addr_t p_phys = 0, p_pbl_phys = 0; 1985 void **pp_virt_addr_tbl = NULL; 1986 u8 *p_pbl_virt = NULL; 1987 void *p_virt = NULL; 1988 1989 size = page_cnt * sizeof(*pp_virt_addr_tbl); 1990 pp_virt_addr_tbl = vzalloc(size); 1991 if (!pp_virt_addr_tbl) 1992 return -ENOMEM; 1993 1994 /* The allocation of the PBL table is done with its full size, since it 1995 * is expected to be successive. 1996 * qed_chain_init_pbl_mem() is called even in a case of an allocation 1997 * failure, since pp_virt_addr_tbl was previously allocated, and it 1998 * should be saved to allow its freeing during the error flow. 1999 */ 2000 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 2001 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev, 2002 size, &p_pbl_phys, GFP_KERNEL); 2003 qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, 2004 pp_virt_addr_tbl); 2005 if (!p_pbl_virt) 2006 return -ENOMEM; 2007 2008 for (i = 0; i < page_cnt; i++) { 2009 p_virt = dma_alloc_coherent(&cdev->pdev->dev, 2010 QED_CHAIN_PAGE_SIZE, 2011 &p_phys, GFP_KERNEL); 2012 if (!p_virt) 2013 return -ENOMEM; 2014 2015 if (i == 0) { 2016 qed_chain_init_mem(p_chain, p_virt, p_phys); 2017 qed_chain_reset(p_chain); 2018 } 2019 2020 /* Fill the PBL table with the physical address of the page */ 2021 *(dma_addr_t *)p_pbl_virt = p_phys; 2022 /* Keep the virtual address of the page */ 2023 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt; 2024 2025 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 2026 } 2027 2028 return 0; 2029 } 2030 2031 int qed_chain_alloc(struct qed_dev *cdev, 2032 enum qed_chain_use_mode intended_use, 2033 enum qed_chain_mode mode, 2034 enum qed_chain_cnt_type cnt_type, 2035 u32 num_elems, size_t elem_size, struct qed_chain *p_chain) 2036 { 2037 u32 page_cnt; 2038 int rc = 0; 2039 2040 if (mode == QED_CHAIN_MODE_SINGLE) 2041 page_cnt = 1; 2042 else 2043 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode); 2044 2045 rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt); 2046 if (rc) { 2047 DP_NOTICE(cdev, 2048 "Cannot allocate a chain with the given arguments:\n"); 2049 DP_NOTICE(cdev, 2050 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n", 2051 intended_use, mode, cnt_type, num_elems, elem_size); 2052 return rc; 2053 } 2054 2055 qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use, 2056 mode, cnt_type); 2057 2058 switch (mode) { 2059 case QED_CHAIN_MODE_NEXT_PTR: 2060 rc = qed_chain_alloc_next_ptr(cdev, p_chain); 2061 break; 2062 case QED_CHAIN_MODE_SINGLE: 2063 rc = qed_chain_alloc_single(cdev, p_chain); 2064 break; 2065 case QED_CHAIN_MODE_PBL: 2066 rc = qed_chain_alloc_pbl(cdev, p_chain); 2067 break; 2068 } 2069 if (rc) 2070 goto nomem; 2071 2072 return 0; 2073 2074 nomem: 2075 qed_chain_free(cdev, p_chain); 2076 return rc; 2077 } 2078 2079 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id) 2080 { 2081 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) { 2082 u16 min, max; 2083 2084 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE); 2085 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE); 2086 DP_NOTICE(p_hwfn, 2087 "l2_queue id [%d] is not valid, available indices [%d - %d]\n", 2088 src_id, min, max); 2089 2090 return -EINVAL; 2091 } 2092 2093 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id; 2094 2095 return 0; 2096 } 2097 2098 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 2099 { 2100 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) { 2101 u8 min, max; 2102 2103 min = (u8)RESC_START(p_hwfn, QED_VPORT); 2104 max = min + RESC_NUM(p_hwfn, QED_VPORT); 2105 DP_NOTICE(p_hwfn, 2106 "vport id [%d] is not valid, available indices [%d - %d]\n", 2107 src_id, min, max); 2108 2109 return -EINVAL; 2110 } 2111 2112 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id; 2113 2114 return 0; 2115 } 2116 2117 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 2118 { 2119 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) { 2120 u8 min, max; 2121 2122 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG); 2123 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG); 2124 DP_NOTICE(p_hwfn, 2125 "rss_eng id [%d] is not valid, available indices [%d - %d]\n", 2126 src_id, min, max); 2127 2128 return -EINVAL; 2129 } 2130 2131 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id; 2132 2133 return 0; 2134 } 2135 2136 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2137 u32 hw_addr, void *p_eth_qzone, 2138 size_t eth_qzone_size, u8 timeset) 2139 { 2140 struct coalescing_timeset *p_coal_timeset; 2141 2142 if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) { 2143 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n"); 2144 return -EINVAL; 2145 } 2146 2147 p_coal_timeset = p_eth_qzone; 2148 memset(p_coal_timeset, 0, eth_qzone_size); 2149 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset); 2150 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1); 2151 qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size); 2152 2153 return 0; 2154 } 2155 2156 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2157 u16 coalesce, u8 qid, u16 sb_id) 2158 { 2159 struct ustorm_eth_queue_zone eth_qzone; 2160 u8 timeset, timer_res; 2161 u16 fw_qid = 0; 2162 u32 address; 2163 int rc; 2164 2165 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 2166 if (coalesce <= 0x7F) { 2167 timer_res = 0; 2168 } else if (coalesce <= 0xFF) { 2169 timer_res = 1; 2170 } else if (coalesce <= 0x1FF) { 2171 timer_res = 2; 2172 } else { 2173 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 2174 return -EINVAL; 2175 } 2176 timeset = (u8)(coalesce >> timer_res); 2177 2178 rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid); 2179 if (rc) 2180 return rc; 2181 2182 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false); 2183 if (rc) 2184 goto out; 2185 2186 address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid); 2187 2188 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 2189 sizeof(struct ustorm_eth_queue_zone), timeset); 2190 if (rc) 2191 goto out; 2192 2193 p_hwfn->cdev->rx_coalesce_usecs = coalesce; 2194 out: 2195 return rc; 2196 } 2197 2198 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2199 u16 coalesce, u8 qid, u16 sb_id) 2200 { 2201 struct xstorm_eth_queue_zone eth_qzone; 2202 u8 timeset, timer_res; 2203 u16 fw_qid = 0; 2204 u32 address; 2205 int rc; 2206 2207 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 2208 if (coalesce <= 0x7F) { 2209 timer_res = 0; 2210 } else if (coalesce <= 0xFF) { 2211 timer_res = 1; 2212 } else if (coalesce <= 0x1FF) { 2213 timer_res = 2; 2214 } else { 2215 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 2216 return -EINVAL; 2217 } 2218 timeset = (u8)(coalesce >> timer_res); 2219 2220 rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid); 2221 if (rc) 2222 return rc; 2223 2224 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true); 2225 if (rc) 2226 goto out; 2227 2228 address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid); 2229 2230 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 2231 sizeof(struct xstorm_eth_queue_zone), timeset); 2232 if (rc) 2233 goto out; 2234 2235 p_hwfn->cdev->tx_coalesce_usecs = coalesce; 2236 out: 2237 return rc; 2238 } 2239 2240 /* Calculate final WFQ values for all vports and configure them. 2241 * After this configuration each vport will have 2242 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT) 2243 */ 2244 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 2245 struct qed_ptt *p_ptt, 2246 u32 min_pf_rate) 2247 { 2248 struct init_qm_vport_params *vport_params; 2249 int i; 2250 2251 vport_params = p_hwfn->qm_info.qm_vport_params; 2252 2253 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 2254 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 2255 2256 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) / 2257 min_pf_rate; 2258 qed_init_vport_wfq(p_hwfn, p_ptt, 2259 vport_params[i].first_tx_pq_id, 2260 vport_params[i].vport_wfq); 2261 } 2262 } 2263 2264 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn, 2265 u32 min_pf_rate) 2266 2267 { 2268 int i; 2269 2270 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) 2271 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1; 2272 } 2273 2274 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 2275 struct qed_ptt *p_ptt, 2276 u32 min_pf_rate) 2277 { 2278 struct init_qm_vport_params *vport_params; 2279 int i; 2280 2281 vport_params = p_hwfn->qm_info.qm_vport_params; 2282 2283 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 2284 qed_init_wfq_default_param(p_hwfn, min_pf_rate); 2285 qed_init_vport_wfq(p_hwfn, p_ptt, 2286 vport_params[i].first_tx_pq_id, 2287 vport_params[i].vport_wfq); 2288 } 2289 } 2290 2291 /* This function performs several validations for WFQ 2292 * configuration and required min rate for a given vport 2293 * 1. req_rate must be greater than one percent of min_pf_rate. 2294 * 2. req_rate should not cause other vports [not configured for WFQ explicitly] 2295 * rates to get less than one percent of min_pf_rate. 2296 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate. 2297 */ 2298 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn, 2299 u16 vport_id, u32 req_rate, u32 min_pf_rate) 2300 { 2301 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0; 2302 int non_requested_count = 0, req_count = 0, i, num_vports; 2303 2304 num_vports = p_hwfn->qm_info.num_vports; 2305 2306 /* Accounting for the vports which are configured for WFQ explicitly */ 2307 for (i = 0; i < num_vports; i++) { 2308 u32 tmp_speed; 2309 2310 if ((i != vport_id) && 2311 p_hwfn->qm_info.wfq_data[i].configured) { 2312 req_count++; 2313 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 2314 total_req_min_rate += tmp_speed; 2315 } 2316 } 2317 2318 /* Include current vport data as well */ 2319 req_count++; 2320 total_req_min_rate += req_rate; 2321 non_requested_count = num_vports - req_count; 2322 2323 if (req_rate < min_pf_rate / QED_WFQ_UNIT) { 2324 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2325 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 2326 vport_id, req_rate, min_pf_rate); 2327 return -EINVAL; 2328 } 2329 2330 if (num_vports > QED_WFQ_UNIT) { 2331 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2332 "Number of vports is greater than %d\n", 2333 QED_WFQ_UNIT); 2334 return -EINVAL; 2335 } 2336 2337 if (total_req_min_rate > min_pf_rate) { 2338 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2339 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", 2340 total_req_min_rate, min_pf_rate); 2341 return -EINVAL; 2342 } 2343 2344 total_left_rate = min_pf_rate - total_req_min_rate; 2345 2346 left_rate_per_vp = total_left_rate / non_requested_count; 2347 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) { 2348 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2349 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 2350 left_rate_per_vp, min_pf_rate); 2351 return -EINVAL; 2352 } 2353 2354 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate; 2355 p_hwfn->qm_info.wfq_data[vport_id].configured = true; 2356 2357 for (i = 0; i < num_vports; i++) { 2358 if (p_hwfn->qm_info.wfq_data[i].configured) 2359 continue; 2360 2361 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp; 2362 } 2363 2364 return 0; 2365 } 2366 2367 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn, 2368 struct qed_ptt *p_ptt, u16 vp_id, u32 rate) 2369 { 2370 struct qed_mcp_link_state *p_link; 2371 int rc = 0; 2372 2373 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output; 2374 2375 if (!p_link->min_pf_rate) { 2376 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate; 2377 p_hwfn->qm_info.wfq_data[vp_id].configured = true; 2378 return rc; 2379 } 2380 2381 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate); 2382 2383 if (!rc) 2384 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, 2385 p_link->min_pf_rate); 2386 else 2387 DP_NOTICE(p_hwfn, 2388 "Validation failed while configuring min rate\n"); 2389 2390 return rc; 2391 } 2392 2393 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn, 2394 struct qed_ptt *p_ptt, 2395 u32 min_pf_rate) 2396 { 2397 bool use_wfq = false; 2398 int rc = 0; 2399 u16 i; 2400 2401 /* Validate all pre configured vports for wfq */ 2402 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 2403 u32 rate; 2404 2405 if (!p_hwfn->qm_info.wfq_data[i].configured) 2406 continue; 2407 2408 rate = p_hwfn->qm_info.wfq_data[i].min_speed; 2409 use_wfq = true; 2410 2411 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate); 2412 if (rc) { 2413 DP_NOTICE(p_hwfn, 2414 "WFQ validation failed while configuring min rate\n"); 2415 break; 2416 } 2417 } 2418 2419 if (!rc && use_wfq) 2420 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 2421 else 2422 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 2423 2424 return rc; 2425 } 2426 2427 /* Main API for qed clients to configure vport min rate. 2428 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)] 2429 * rate - Speed in Mbps needs to be assigned to a given vport. 2430 */ 2431 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate) 2432 { 2433 int i, rc = -EINVAL; 2434 2435 /* Currently not supported; Might change in future */ 2436 if (cdev->num_hwfns > 1) { 2437 DP_NOTICE(cdev, 2438 "WFQ configuration is not supported for this device\n"); 2439 return rc; 2440 } 2441 2442 for_each_hwfn(cdev, i) { 2443 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2444 struct qed_ptt *p_ptt; 2445 2446 p_ptt = qed_ptt_acquire(p_hwfn); 2447 if (!p_ptt) 2448 return -EBUSY; 2449 2450 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate); 2451 2452 if (rc) { 2453 qed_ptt_release(p_hwfn, p_ptt); 2454 return rc; 2455 } 2456 2457 qed_ptt_release(p_hwfn, p_ptt); 2458 } 2459 2460 return rc; 2461 } 2462 2463 /* API to configure WFQ from mcp link change */ 2464 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate) 2465 { 2466 int i; 2467 2468 if (cdev->num_hwfns > 1) { 2469 DP_VERBOSE(cdev, 2470 NETIF_MSG_LINK, 2471 "WFQ configuration is not supported for this device\n"); 2472 return; 2473 } 2474 2475 for_each_hwfn(cdev, i) { 2476 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2477 2478 __qed_configure_vp_wfq_on_link_change(p_hwfn, 2479 p_hwfn->p_dpc_ptt, 2480 min_pf_rate); 2481 } 2482 } 2483 2484 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, 2485 struct qed_ptt *p_ptt, 2486 struct qed_mcp_link_state *p_link, 2487 u8 max_bw) 2488 { 2489 int rc = 0; 2490 2491 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw; 2492 2493 if (!p_link->line_speed && (max_bw != 100)) 2494 return rc; 2495 2496 p_link->speed = (p_link->line_speed * max_bw) / 100; 2497 p_hwfn->qm_info.pf_rl = p_link->speed; 2498 2499 /* Since the limiter also affects Tx-switched traffic, we don't want it 2500 * to limit such traffic in case there's no actual limit. 2501 * In that case, set limit to imaginary high boundary. 2502 */ 2503 if (max_bw == 100) 2504 p_hwfn->qm_info.pf_rl = 100000; 2505 2506 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 2507 p_hwfn->qm_info.pf_rl); 2508 2509 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2510 "Configured MAX bandwidth to be %08x Mb/sec\n", 2511 p_link->speed); 2512 2513 return rc; 2514 } 2515 2516 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */ 2517 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw) 2518 { 2519 int i, rc = -EINVAL; 2520 2521 if (max_bw < 1 || max_bw > 100) { 2522 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n"); 2523 return rc; 2524 } 2525 2526 for_each_hwfn(cdev, i) { 2527 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2528 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 2529 struct qed_mcp_link_state *p_link; 2530 struct qed_ptt *p_ptt; 2531 2532 p_link = &p_lead->mcp_info->link_output; 2533 2534 p_ptt = qed_ptt_acquire(p_hwfn); 2535 if (!p_ptt) 2536 return -EBUSY; 2537 2538 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, 2539 p_link, max_bw); 2540 2541 qed_ptt_release(p_hwfn, p_ptt); 2542 2543 if (rc) 2544 break; 2545 } 2546 2547 return rc; 2548 } 2549 2550 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn, 2551 struct qed_ptt *p_ptt, 2552 struct qed_mcp_link_state *p_link, 2553 u8 min_bw) 2554 { 2555 int rc = 0; 2556 2557 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw; 2558 p_hwfn->qm_info.pf_wfq = min_bw; 2559 2560 if (!p_link->line_speed) 2561 return rc; 2562 2563 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100; 2564 2565 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw); 2566 2567 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2568 "Configured MIN bandwidth to be %d Mb/sec\n", 2569 p_link->min_pf_rate); 2570 2571 return rc; 2572 } 2573 2574 /* Main API to configure PF min bandwidth where bw range is [1-100] */ 2575 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw) 2576 { 2577 int i, rc = -EINVAL; 2578 2579 if (min_bw < 1 || min_bw > 100) { 2580 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n"); 2581 return rc; 2582 } 2583 2584 for_each_hwfn(cdev, i) { 2585 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2586 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 2587 struct qed_mcp_link_state *p_link; 2588 struct qed_ptt *p_ptt; 2589 2590 p_link = &p_lead->mcp_info->link_output; 2591 2592 p_ptt = qed_ptt_acquire(p_hwfn); 2593 if (!p_ptt) 2594 return -EBUSY; 2595 2596 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, 2597 p_link, min_bw); 2598 if (rc) { 2599 qed_ptt_release(p_hwfn, p_ptt); 2600 return rc; 2601 } 2602 2603 if (p_link->min_pf_rate) { 2604 u32 min_rate = p_link->min_pf_rate; 2605 2606 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn, 2607 p_ptt, 2608 min_rate); 2609 } 2610 2611 qed_ptt_release(p_hwfn, p_ptt); 2612 } 2613 2614 return rc; 2615 } 2616 2617 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2618 { 2619 struct qed_mcp_link_state *p_link; 2620 2621 p_link = &p_hwfn->mcp_info->link_output; 2622 2623 if (p_link->min_pf_rate) 2624 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, 2625 p_link->min_pf_rate); 2626 2627 memset(p_hwfn->qm_info.wfq_data, 0, 2628 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports); 2629 } 2630