1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 /* QLogic qed NIC Driver 3 * Copyright (c) 2015-2017 QLogic Corporation 4 * Copyright (c) 2019-2020 Marvell International Ltd. 5 */ 6 7 #include <linux/types.h> 8 #include <asm/byteorder.h> 9 #include <linux/io.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/errno.h> 13 #include <linux/kernel.h> 14 #include <linux/mutex.h> 15 #include <linux/pci.h> 16 #include <linux/slab.h> 17 #include <linux/string.h> 18 #include <linux/vmalloc.h> 19 #include <linux/etherdevice.h> 20 #include <linux/qed/qed_chain.h> 21 #include <linux/qed/qed_if.h> 22 #include "qed.h" 23 #include "qed_cxt.h" 24 #include "qed_dcbx.h" 25 #include "qed_dev_api.h" 26 #include "qed_fcoe.h" 27 #include "qed_hsi.h" 28 #include "qed_iro_hsi.h" 29 #include "qed_hw.h" 30 #include "qed_init_ops.h" 31 #include "qed_int.h" 32 #include "qed_iscsi.h" 33 #include "qed_ll2.h" 34 #include "qed_mcp.h" 35 #include "qed_ooo.h" 36 #include "qed_reg_addr.h" 37 #include "qed_sp.h" 38 #include "qed_sriov.h" 39 #include "qed_vf.h" 40 #include "qed_rdma.h" 41 #include "qed_nvmetcp.h" 42 43 static DEFINE_SPINLOCK(qm_lock); 44 45 /******************** Doorbell Recovery *******************/ 46 /* The doorbell recovery mechanism consists of a list of entries which represent 47 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each 48 * entity needs to register with the mechanism and provide the parameters 49 * describing it's doorbell, including a location where last used doorbell data 50 * can be found. The doorbell execute function will traverse the list and 51 * doorbell all of the registered entries. 52 */ 53 struct qed_db_recovery_entry { 54 struct list_head list_entry; 55 void __iomem *db_addr; 56 void *db_data; 57 enum qed_db_rec_width db_width; 58 enum qed_db_rec_space db_space; 59 u8 hwfn_idx; 60 }; 61 62 /* Display a single doorbell recovery entry */ 63 static void qed_db_recovery_dp_entry(struct qed_hwfn *p_hwfn, 64 struct qed_db_recovery_entry *db_entry, 65 char *action) 66 { 67 DP_VERBOSE(p_hwfn, 68 QED_MSG_SPQ, 69 "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n", 70 action, 71 db_entry, 72 db_entry->db_addr, 73 db_entry->db_data, 74 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b", 75 db_entry->db_space == DB_REC_USER ? "user" : "kernel", 76 db_entry->hwfn_idx); 77 } 78 79 /* Doorbell address sanity (address within doorbell bar range) */ 80 static bool qed_db_rec_sanity(struct qed_dev *cdev, 81 void __iomem *db_addr, 82 enum qed_db_rec_width db_width, 83 void *db_data) 84 { 85 u32 width = (db_width == DB_REC_WIDTH_32B) ? 32 : 64; 86 87 /* Make sure doorbell address is within the doorbell bar */ 88 if (db_addr < cdev->doorbells || 89 (u8 __iomem *)db_addr + width > 90 (u8 __iomem *)cdev->doorbells + cdev->db_size) { 91 WARN(true, 92 "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n", 93 db_addr, 94 cdev->doorbells, 95 (u8 __iomem *)cdev->doorbells + cdev->db_size); 96 return false; 97 } 98 99 /* ake sure doorbell data pointer is not null */ 100 if (!db_data) { 101 WARN(true, "Illegal doorbell data pointer: %p", db_data); 102 return false; 103 } 104 105 return true; 106 } 107 108 /* Find hwfn according to the doorbell address */ 109 static struct qed_hwfn *qed_db_rec_find_hwfn(struct qed_dev *cdev, 110 void __iomem *db_addr) 111 { 112 struct qed_hwfn *p_hwfn; 113 114 /* In CMT doorbell bar is split down the middle between engine 0 and enigne 1 */ 115 if (cdev->num_hwfns > 1) 116 p_hwfn = db_addr < cdev->hwfns[1].doorbells ? 117 &cdev->hwfns[0] : &cdev->hwfns[1]; 118 else 119 p_hwfn = QED_LEADING_HWFN(cdev); 120 121 return p_hwfn; 122 } 123 124 /* Add a new entry to the doorbell recovery mechanism */ 125 int qed_db_recovery_add(struct qed_dev *cdev, 126 void __iomem *db_addr, 127 void *db_data, 128 enum qed_db_rec_width db_width, 129 enum qed_db_rec_space db_space) 130 { 131 struct qed_db_recovery_entry *db_entry; 132 struct qed_hwfn *p_hwfn; 133 134 /* Shortcircuit VFs, for now */ 135 if (IS_VF(cdev)) { 136 DP_VERBOSE(cdev, 137 QED_MSG_IOV, "db recovery - skipping VF doorbell\n"); 138 return 0; 139 } 140 141 /* Sanitize doorbell address */ 142 if (!qed_db_rec_sanity(cdev, db_addr, db_width, db_data)) 143 return -EINVAL; 144 145 /* Obtain hwfn from doorbell address */ 146 p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr); 147 148 /* Create entry */ 149 db_entry = kzalloc(sizeof(*db_entry), GFP_KERNEL); 150 if (!db_entry) { 151 DP_NOTICE(cdev, "Failed to allocate a db recovery entry\n"); 152 return -ENOMEM; 153 } 154 155 /* Populate entry */ 156 db_entry->db_addr = db_addr; 157 db_entry->db_data = db_data; 158 db_entry->db_width = db_width; 159 db_entry->db_space = db_space; 160 db_entry->hwfn_idx = p_hwfn->my_id; 161 162 /* Display */ 163 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Adding"); 164 165 /* Protect the list */ 166 spin_lock_bh(&p_hwfn->db_recovery_info.lock); 167 list_add_tail(&db_entry->list_entry, &p_hwfn->db_recovery_info.list); 168 spin_unlock_bh(&p_hwfn->db_recovery_info.lock); 169 170 return 0; 171 } 172 173 /* Remove an entry from the doorbell recovery mechanism */ 174 int qed_db_recovery_del(struct qed_dev *cdev, 175 void __iomem *db_addr, void *db_data) 176 { 177 struct qed_db_recovery_entry *db_entry = NULL; 178 struct qed_hwfn *p_hwfn; 179 int rc = -EINVAL; 180 181 /* Shortcircuit VFs, for now */ 182 if (IS_VF(cdev)) { 183 DP_VERBOSE(cdev, 184 QED_MSG_IOV, "db recovery - skipping VF doorbell\n"); 185 return 0; 186 } 187 188 /* Obtain hwfn from doorbell address */ 189 p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr); 190 191 /* Protect the list */ 192 spin_lock_bh(&p_hwfn->db_recovery_info.lock); 193 list_for_each_entry(db_entry, 194 &p_hwfn->db_recovery_info.list, list_entry) { 195 /* search according to db_data addr since db_addr is not unique (roce) */ 196 if (db_entry->db_data == db_data) { 197 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Deleting"); 198 list_del(&db_entry->list_entry); 199 rc = 0; 200 break; 201 } 202 } 203 204 spin_unlock_bh(&p_hwfn->db_recovery_info.lock); 205 206 if (rc == -EINVAL) 207 208 DP_NOTICE(p_hwfn, 209 "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n", 210 db_data, db_addr); 211 else 212 kfree(db_entry); 213 214 return rc; 215 } 216 217 /* Initialize the doorbell recovery mechanism */ 218 static int qed_db_recovery_setup(struct qed_hwfn *p_hwfn) 219 { 220 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Setting up db recovery\n"); 221 222 /* Make sure db_size was set in cdev */ 223 if (!p_hwfn->cdev->db_size) { 224 DP_ERR(p_hwfn->cdev, "db_size not set\n"); 225 return -EINVAL; 226 } 227 228 INIT_LIST_HEAD(&p_hwfn->db_recovery_info.list); 229 spin_lock_init(&p_hwfn->db_recovery_info.lock); 230 p_hwfn->db_recovery_info.db_recovery_counter = 0; 231 232 return 0; 233 } 234 235 /* Destroy the doorbell recovery mechanism */ 236 static void qed_db_recovery_teardown(struct qed_hwfn *p_hwfn) 237 { 238 struct qed_db_recovery_entry *db_entry = NULL; 239 240 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Tearing down db recovery\n"); 241 if (!list_empty(&p_hwfn->db_recovery_info.list)) { 242 DP_VERBOSE(p_hwfn, 243 QED_MSG_SPQ, 244 "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n"); 245 while (!list_empty(&p_hwfn->db_recovery_info.list)) { 246 db_entry = 247 list_first_entry(&p_hwfn->db_recovery_info.list, 248 struct qed_db_recovery_entry, 249 list_entry); 250 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Purging"); 251 list_del(&db_entry->list_entry); 252 kfree(db_entry); 253 } 254 } 255 p_hwfn->db_recovery_info.db_recovery_counter = 0; 256 } 257 258 /* Ring the doorbell of a single doorbell recovery entry */ 259 static void qed_db_recovery_ring(struct qed_hwfn *p_hwfn, 260 struct qed_db_recovery_entry *db_entry) 261 { 262 /* Print according to width */ 263 if (db_entry->db_width == DB_REC_WIDTH_32B) { 264 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, 265 "ringing doorbell address %p data %x\n", 266 db_entry->db_addr, 267 *(u32 *)db_entry->db_data); 268 } else { 269 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, 270 "ringing doorbell address %p data %llx\n", 271 db_entry->db_addr, 272 *(u64 *)(db_entry->db_data)); 273 } 274 275 /* Sanity */ 276 if (!qed_db_rec_sanity(p_hwfn->cdev, db_entry->db_addr, 277 db_entry->db_width, db_entry->db_data)) 278 return; 279 280 /* Flush the write combined buffer. Since there are multiple doorbelling 281 * entities using the same address, if we don't flush, a transaction 282 * could be lost. 283 */ 284 wmb(); 285 286 /* Ring the doorbell */ 287 if (db_entry->db_width == DB_REC_WIDTH_32B) 288 DIRECT_REG_WR(db_entry->db_addr, 289 *(u32 *)(db_entry->db_data)); 290 else 291 DIRECT_REG_WR64(db_entry->db_addr, 292 *(u64 *)(db_entry->db_data)); 293 294 /* Flush the write combined buffer. Next doorbell may come from a 295 * different entity to the same address... 296 */ 297 wmb(); 298 } 299 300 /* Traverse the doorbell recovery entry list and ring all the doorbells */ 301 void qed_db_recovery_execute(struct qed_hwfn *p_hwfn) 302 { 303 struct qed_db_recovery_entry *db_entry = NULL; 304 305 DP_NOTICE(p_hwfn, "Executing doorbell recovery. Counter was %d\n", 306 p_hwfn->db_recovery_info.db_recovery_counter); 307 308 /* Track amount of times recovery was executed */ 309 p_hwfn->db_recovery_info.db_recovery_counter++; 310 311 /* Protect the list */ 312 spin_lock_bh(&p_hwfn->db_recovery_info.lock); 313 list_for_each_entry(db_entry, 314 &p_hwfn->db_recovery_info.list, list_entry) 315 qed_db_recovery_ring(p_hwfn, db_entry); 316 spin_unlock_bh(&p_hwfn->db_recovery_info.lock); 317 } 318 319 /******************** Doorbell Recovery end ****************/ 320 321 /********************************** NIG LLH ***********************************/ 322 323 enum qed_llh_filter_type { 324 QED_LLH_FILTER_TYPE_MAC, 325 QED_LLH_FILTER_TYPE_PROTOCOL, 326 }; 327 328 struct qed_llh_mac_filter { 329 u8 addr[ETH_ALEN]; 330 }; 331 332 struct qed_llh_protocol_filter { 333 enum qed_llh_prot_filter_type_t type; 334 u16 source_port_or_eth_type; 335 u16 dest_port; 336 }; 337 338 union qed_llh_filter { 339 struct qed_llh_mac_filter mac; 340 struct qed_llh_protocol_filter protocol; 341 }; 342 343 struct qed_llh_filter_info { 344 bool b_enabled; 345 u32 ref_cnt; 346 enum qed_llh_filter_type type; 347 union qed_llh_filter filter; 348 }; 349 350 struct qed_llh_info { 351 /* Number of LLH filters banks */ 352 u8 num_ppfid; 353 354 #define MAX_NUM_PPFID 8 355 u8 ppfid_array[MAX_NUM_PPFID]; 356 357 /* Array of filters arrays: 358 * "num_ppfid" elements of filters banks, where each is an array of 359 * "NIG_REG_LLH_FUNC_FILTER_EN_SIZE" filters. 360 */ 361 struct qed_llh_filter_info **pp_filters; 362 }; 363 364 static void qed_llh_free(struct qed_dev *cdev) 365 { 366 struct qed_llh_info *p_llh_info = cdev->p_llh_info; 367 u32 i; 368 369 if (p_llh_info) { 370 if (p_llh_info->pp_filters) 371 for (i = 0; i < p_llh_info->num_ppfid; i++) 372 kfree(p_llh_info->pp_filters[i]); 373 374 kfree(p_llh_info->pp_filters); 375 } 376 377 kfree(p_llh_info); 378 cdev->p_llh_info = NULL; 379 } 380 381 static int qed_llh_alloc(struct qed_dev *cdev) 382 { 383 struct qed_llh_info *p_llh_info; 384 u32 size, i; 385 386 p_llh_info = kzalloc(sizeof(*p_llh_info), GFP_KERNEL); 387 if (!p_llh_info) 388 return -ENOMEM; 389 cdev->p_llh_info = p_llh_info; 390 391 for (i = 0; i < MAX_NUM_PPFID; i++) { 392 if (!(cdev->ppfid_bitmap & (0x1 << i))) 393 continue; 394 395 p_llh_info->ppfid_array[p_llh_info->num_ppfid] = i; 396 DP_VERBOSE(cdev, QED_MSG_SP, "ppfid_array[%d] = %u\n", 397 p_llh_info->num_ppfid, i); 398 p_llh_info->num_ppfid++; 399 } 400 401 size = p_llh_info->num_ppfid * sizeof(*p_llh_info->pp_filters); 402 p_llh_info->pp_filters = kzalloc(size, GFP_KERNEL); 403 if (!p_llh_info->pp_filters) 404 return -ENOMEM; 405 406 size = NIG_REG_LLH_FUNC_FILTER_EN_SIZE * 407 sizeof(**p_llh_info->pp_filters); 408 for (i = 0; i < p_llh_info->num_ppfid; i++) { 409 p_llh_info->pp_filters[i] = kzalloc(size, GFP_KERNEL); 410 if (!p_llh_info->pp_filters[i]) 411 return -ENOMEM; 412 } 413 414 return 0; 415 } 416 417 static int qed_llh_shadow_sanity(struct qed_dev *cdev, 418 u8 ppfid, u8 filter_idx, const char *action) 419 { 420 struct qed_llh_info *p_llh_info = cdev->p_llh_info; 421 422 if (ppfid >= p_llh_info->num_ppfid) { 423 DP_NOTICE(cdev, 424 "LLH shadow [%s]: using ppfid %d while only %d ppfids are available\n", 425 action, ppfid, p_llh_info->num_ppfid); 426 return -EINVAL; 427 } 428 429 if (filter_idx >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 430 DP_NOTICE(cdev, 431 "LLH shadow [%s]: using filter_idx %d while only %d filters are available\n", 432 action, filter_idx, NIG_REG_LLH_FUNC_FILTER_EN_SIZE); 433 return -EINVAL; 434 } 435 436 return 0; 437 } 438 439 #define QED_LLH_INVALID_FILTER_IDX 0xff 440 441 static int 442 qed_llh_shadow_search_filter(struct qed_dev *cdev, 443 u8 ppfid, 444 union qed_llh_filter *p_filter, u8 *p_filter_idx) 445 { 446 struct qed_llh_info *p_llh_info = cdev->p_llh_info; 447 struct qed_llh_filter_info *p_filters; 448 int rc; 449 u8 i; 450 451 rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "search"); 452 if (rc) 453 return rc; 454 455 *p_filter_idx = QED_LLH_INVALID_FILTER_IDX; 456 457 p_filters = p_llh_info->pp_filters[ppfid]; 458 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 459 if (!memcmp(p_filter, &p_filters[i].filter, 460 sizeof(*p_filter))) { 461 *p_filter_idx = i; 462 break; 463 } 464 } 465 466 return 0; 467 } 468 469 static int 470 qed_llh_shadow_get_free_idx(struct qed_dev *cdev, u8 ppfid, u8 *p_filter_idx) 471 { 472 struct qed_llh_info *p_llh_info = cdev->p_llh_info; 473 struct qed_llh_filter_info *p_filters; 474 int rc; 475 u8 i; 476 477 rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "get_free_idx"); 478 if (rc) 479 return rc; 480 481 *p_filter_idx = QED_LLH_INVALID_FILTER_IDX; 482 483 p_filters = p_llh_info->pp_filters[ppfid]; 484 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 485 if (!p_filters[i].b_enabled) { 486 *p_filter_idx = i; 487 break; 488 } 489 } 490 491 return 0; 492 } 493 494 static int 495 __qed_llh_shadow_add_filter(struct qed_dev *cdev, 496 u8 ppfid, 497 u8 filter_idx, 498 enum qed_llh_filter_type type, 499 union qed_llh_filter *p_filter, u32 *p_ref_cnt) 500 { 501 struct qed_llh_info *p_llh_info = cdev->p_llh_info; 502 struct qed_llh_filter_info *p_filters; 503 int rc; 504 505 rc = qed_llh_shadow_sanity(cdev, ppfid, filter_idx, "add"); 506 if (rc) 507 return rc; 508 509 p_filters = p_llh_info->pp_filters[ppfid]; 510 if (!p_filters[filter_idx].ref_cnt) { 511 p_filters[filter_idx].b_enabled = true; 512 p_filters[filter_idx].type = type; 513 memcpy(&p_filters[filter_idx].filter, p_filter, 514 sizeof(p_filters[filter_idx].filter)); 515 } 516 517 *p_ref_cnt = ++p_filters[filter_idx].ref_cnt; 518 519 return 0; 520 } 521 522 static int 523 qed_llh_shadow_add_filter(struct qed_dev *cdev, 524 u8 ppfid, 525 enum qed_llh_filter_type type, 526 union qed_llh_filter *p_filter, 527 u8 *p_filter_idx, u32 *p_ref_cnt) 528 { 529 int rc; 530 531 /* Check if the same filter already exist */ 532 rc = qed_llh_shadow_search_filter(cdev, ppfid, p_filter, p_filter_idx); 533 if (rc) 534 return rc; 535 536 /* Find a new entry in case of a new filter */ 537 if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) { 538 rc = qed_llh_shadow_get_free_idx(cdev, ppfid, p_filter_idx); 539 if (rc) 540 return rc; 541 } 542 543 /* No free entry was found */ 544 if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) { 545 DP_NOTICE(cdev, 546 "Failed to find an empty LLH filter to utilize [ppfid %d]\n", 547 ppfid); 548 return -EINVAL; 549 } 550 551 return __qed_llh_shadow_add_filter(cdev, ppfid, *p_filter_idx, type, 552 p_filter, p_ref_cnt); 553 } 554 555 static int 556 __qed_llh_shadow_remove_filter(struct qed_dev *cdev, 557 u8 ppfid, u8 filter_idx, u32 *p_ref_cnt) 558 { 559 struct qed_llh_info *p_llh_info = cdev->p_llh_info; 560 struct qed_llh_filter_info *p_filters; 561 int rc; 562 563 rc = qed_llh_shadow_sanity(cdev, ppfid, filter_idx, "remove"); 564 if (rc) 565 return rc; 566 567 p_filters = p_llh_info->pp_filters[ppfid]; 568 if (!p_filters[filter_idx].ref_cnt) { 569 DP_NOTICE(cdev, 570 "LLH shadow: trying to remove a filter with ref_cnt=0\n"); 571 return -EINVAL; 572 } 573 574 *p_ref_cnt = --p_filters[filter_idx].ref_cnt; 575 if (!p_filters[filter_idx].ref_cnt) 576 memset(&p_filters[filter_idx], 577 0, sizeof(p_filters[filter_idx])); 578 579 return 0; 580 } 581 582 static int 583 qed_llh_shadow_remove_filter(struct qed_dev *cdev, 584 u8 ppfid, 585 union qed_llh_filter *p_filter, 586 u8 *p_filter_idx, u32 *p_ref_cnt) 587 { 588 int rc; 589 590 rc = qed_llh_shadow_search_filter(cdev, ppfid, p_filter, p_filter_idx); 591 if (rc) 592 return rc; 593 594 /* No matching filter was found */ 595 if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) { 596 DP_NOTICE(cdev, "Failed to find a filter in the LLH shadow\n"); 597 return -EINVAL; 598 } 599 600 return __qed_llh_shadow_remove_filter(cdev, ppfid, *p_filter_idx, 601 p_ref_cnt); 602 } 603 604 static int qed_llh_abs_ppfid(struct qed_dev *cdev, u8 ppfid, u8 *p_abs_ppfid) 605 { 606 struct qed_llh_info *p_llh_info = cdev->p_llh_info; 607 608 if (ppfid >= p_llh_info->num_ppfid) { 609 DP_NOTICE(cdev, 610 "ppfid %d is not valid, available indices are 0..%d\n", 611 ppfid, p_llh_info->num_ppfid - 1); 612 *p_abs_ppfid = 0; 613 return -EINVAL; 614 } 615 616 *p_abs_ppfid = p_llh_info->ppfid_array[ppfid]; 617 618 return 0; 619 } 620 621 static int 622 qed_llh_set_engine_affin(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 623 { 624 struct qed_dev *cdev = p_hwfn->cdev; 625 enum qed_eng eng; 626 u8 ppfid; 627 int rc; 628 629 rc = qed_mcp_get_engine_config(p_hwfn, p_ptt); 630 if (rc != 0 && rc != -EOPNOTSUPP) { 631 DP_NOTICE(p_hwfn, 632 "Failed to get the engine affinity configuration\n"); 633 return rc; 634 } 635 636 /* RoCE PF is bound to a single engine */ 637 if (QED_IS_ROCE_PERSONALITY(p_hwfn)) { 638 eng = cdev->fir_affin ? QED_ENG1 : QED_ENG0; 639 rc = qed_llh_set_roce_affinity(cdev, eng); 640 if (rc) { 641 DP_NOTICE(cdev, 642 "Failed to set the RoCE engine affinity\n"); 643 return rc; 644 } 645 646 DP_VERBOSE(cdev, 647 QED_MSG_SP, 648 "LLH: Set the engine affinity of RoCE packets as %d\n", 649 eng); 650 } 651 652 /* Storage PF is bound to a single engine while L2 PF uses both */ 653 if (QED_IS_FCOE_PERSONALITY(p_hwfn) || QED_IS_ISCSI_PERSONALITY(p_hwfn) || 654 QED_IS_NVMETCP_PERSONALITY(p_hwfn)) 655 eng = cdev->fir_affin ? QED_ENG1 : QED_ENG0; 656 else /* L2_PERSONALITY */ 657 eng = QED_BOTH_ENG; 658 659 for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) { 660 rc = qed_llh_set_ppfid_affinity(cdev, ppfid, eng); 661 if (rc) { 662 DP_NOTICE(cdev, 663 "Failed to set the engine affinity of ppfid %d\n", 664 ppfid); 665 return rc; 666 } 667 } 668 669 DP_VERBOSE(cdev, QED_MSG_SP, 670 "LLH: Set the engine affinity of non-RoCE packets as %d\n", 671 eng); 672 673 return 0; 674 } 675 676 static int qed_llh_hw_init_pf(struct qed_hwfn *p_hwfn, 677 struct qed_ptt *p_ptt) 678 { 679 struct qed_dev *cdev = p_hwfn->cdev; 680 u8 ppfid, abs_ppfid; 681 int rc; 682 683 for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) { 684 u32 addr; 685 686 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 687 if (rc) 688 return rc; 689 690 addr = NIG_REG_LLH_PPFID2PFID_TBL_0 + abs_ppfid * 0x4; 691 qed_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id); 692 } 693 694 if (test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits) && 695 !QED_IS_FCOE_PERSONALITY(p_hwfn)) { 696 rc = qed_llh_add_mac_filter(cdev, 0, 697 p_hwfn->hw_info.hw_mac_addr); 698 if (rc) 699 DP_NOTICE(cdev, 700 "Failed to add an LLH filter with the primary MAC\n"); 701 } 702 703 if (QED_IS_CMT(cdev)) { 704 rc = qed_llh_set_engine_affin(p_hwfn, p_ptt); 705 if (rc) 706 return rc; 707 } 708 709 return 0; 710 } 711 712 u8 qed_llh_get_num_ppfid(struct qed_dev *cdev) 713 { 714 return cdev->p_llh_info->num_ppfid; 715 } 716 717 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_MASK 0x3 718 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_SHIFT 0 719 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_MASK 0x3 720 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_SHIFT 2 721 722 int qed_llh_set_ppfid_affinity(struct qed_dev *cdev, u8 ppfid, enum qed_eng eng) 723 { 724 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 725 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 726 u32 addr, val, eng_sel; 727 u8 abs_ppfid; 728 int rc = 0; 729 730 if (!p_ptt) 731 return -EAGAIN; 732 733 if (!QED_IS_CMT(cdev)) 734 goto out; 735 736 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 737 if (rc) 738 goto out; 739 740 switch (eng) { 741 case QED_ENG0: 742 eng_sel = 0; 743 break; 744 case QED_ENG1: 745 eng_sel = 1; 746 break; 747 case QED_BOTH_ENG: 748 eng_sel = 2; 749 break; 750 default: 751 DP_NOTICE(cdev, "Invalid affinity value for ppfid [%d]\n", eng); 752 rc = -EINVAL; 753 goto out; 754 } 755 756 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4; 757 val = qed_rd(p_hwfn, p_ptt, addr); 758 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE, eng_sel); 759 qed_wr(p_hwfn, p_ptt, addr, val); 760 761 /* The iWARP affinity is set as the affinity of ppfid 0 */ 762 if (!ppfid && QED_IS_IWARP_PERSONALITY(p_hwfn)) 763 cdev->iwarp_affin = (eng == QED_ENG1) ? 1 : 0; 764 out: 765 qed_ptt_release(p_hwfn, p_ptt); 766 767 return rc; 768 } 769 770 int qed_llh_set_roce_affinity(struct qed_dev *cdev, enum qed_eng eng) 771 { 772 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 773 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 774 u32 addr, val, eng_sel; 775 u8 ppfid, abs_ppfid; 776 int rc = 0; 777 778 if (!p_ptt) 779 return -EAGAIN; 780 781 if (!QED_IS_CMT(cdev)) 782 goto out; 783 784 switch (eng) { 785 case QED_ENG0: 786 eng_sel = 0; 787 break; 788 case QED_ENG1: 789 eng_sel = 1; 790 break; 791 case QED_BOTH_ENG: 792 eng_sel = 2; 793 qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL, 794 0xf); /* QP bit 15 */ 795 break; 796 default: 797 DP_NOTICE(cdev, "Invalid affinity value for RoCE [%d]\n", eng); 798 rc = -EINVAL; 799 goto out; 800 } 801 802 for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) { 803 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 804 if (rc) 805 goto out; 806 807 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4; 808 val = qed_rd(p_hwfn, p_ptt, addr); 809 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_ROCE, eng_sel); 810 qed_wr(p_hwfn, p_ptt, addr, val); 811 } 812 out: 813 qed_ptt_release(p_hwfn, p_ptt); 814 815 return rc; 816 } 817 818 struct qed_llh_filter_details { 819 u64 value; 820 u32 mode; 821 u32 protocol_type; 822 u32 hdr_sel; 823 u32 enable; 824 }; 825 826 static int 827 qed_llh_access_filter(struct qed_hwfn *p_hwfn, 828 struct qed_ptt *p_ptt, 829 u8 abs_ppfid, 830 u8 filter_idx, 831 struct qed_llh_filter_details *p_details) 832 { 833 struct qed_dmae_params params = {0}; 834 u32 addr; 835 u8 pfid; 836 int rc; 837 838 /* The NIG/LLH registers that are accessed in this function have only 16 839 * rows which are exposed to a PF. I.e. only the 16 filters of its 840 * default ppfid. Accessing filters of other ppfids requires pretending 841 * to another PFs. 842 * The calculation of PPFID->PFID in AH is based on the relative index 843 * of a PF on its port. 844 * For BB the pfid is actually the abs_ppfid. 845 */ 846 if (QED_IS_BB(p_hwfn->cdev)) 847 pfid = abs_ppfid; 848 else 849 pfid = abs_ppfid * p_hwfn->cdev->num_ports_in_engine + 850 MFW_PORT(p_hwfn); 851 852 /* Filter enable - should be done first when removing a filter */ 853 if (!p_details->enable) { 854 qed_fid_pretend(p_hwfn, p_ptt, 855 pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT); 856 857 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4; 858 qed_wr(p_hwfn, p_ptt, addr, p_details->enable); 859 860 qed_fid_pretend(p_hwfn, p_ptt, 861 p_hwfn->rel_pf_id << 862 PXP_PRETEND_CONCRETE_FID_PFID_SHIFT); 863 } 864 865 /* Filter value */ 866 addr = NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * filter_idx * 0x4; 867 868 SET_FIELD(params.flags, QED_DMAE_PARAMS_DST_PF_VALID, 0x1); 869 params.dst_pfid = pfid; 870 rc = qed_dmae_host2grc(p_hwfn, 871 p_ptt, 872 (u64)(uintptr_t)&p_details->value, 873 addr, 2 /* size_in_dwords */, 874 ¶ms); 875 if (rc) 876 return rc; 877 878 qed_fid_pretend(p_hwfn, p_ptt, 879 pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT); 880 881 /* Filter mode */ 882 addr = NIG_REG_LLH_FUNC_FILTER_MODE + filter_idx * 0x4; 883 qed_wr(p_hwfn, p_ptt, addr, p_details->mode); 884 885 /* Filter protocol type */ 886 addr = NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + filter_idx * 0x4; 887 qed_wr(p_hwfn, p_ptt, addr, p_details->protocol_type); 888 889 /* Filter header select */ 890 addr = NIG_REG_LLH_FUNC_FILTER_HDR_SEL + filter_idx * 0x4; 891 qed_wr(p_hwfn, p_ptt, addr, p_details->hdr_sel); 892 893 /* Filter enable - should be done last when adding a filter */ 894 if (p_details->enable) { 895 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4; 896 qed_wr(p_hwfn, p_ptt, addr, p_details->enable); 897 } 898 899 qed_fid_pretend(p_hwfn, p_ptt, 900 p_hwfn->rel_pf_id << 901 PXP_PRETEND_CONCRETE_FID_PFID_SHIFT); 902 903 return 0; 904 } 905 906 static int 907 qed_llh_add_filter(struct qed_hwfn *p_hwfn, 908 struct qed_ptt *p_ptt, 909 u8 abs_ppfid, 910 u8 filter_idx, u8 filter_prot_type, u32 high, u32 low) 911 { 912 struct qed_llh_filter_details filter_details; 913 914 filter_details.enable = 1; 915 filter_details.value = ((u64)high << 32) | low; 916 filter_details.hdr_sel = 0; 917 filter_details.protocol_type = filter_prot_type; 918 /* Mode: 0: MAC-address classification 1: protocol classification */ 919 filter_details.mode = filter_prot_type ? 1 : 0; 920 921 return qed_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx, 922 &filter_details); 923 } 924 925 static int 926 qed_llh_remove_filter(struct qed_hwfn *p_hwfn, 927 struct qed_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx) 928 { 929 struct qed_llh_filter_details filter_details = {0}; 930 931 return qed_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx, 932 &filter_details); 933 } 934 935 int qed_llh_add_mac_filter(struct qed_dev *cdev, 936 u8 ppfid, const u8 mac_addr[ETH_ALEN]) 937 { 938 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 939 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 940 union qed_llh_filter filter = {}; 941 u8 filter_idx, abs_ppfid = 0; 942 u32 high, low, ref_cnt; 943 int rc = 0; 944 945 if (!p_ptt) 946 return -EAGAIN; 947 948 if (!test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits)) 949 goto out; 950 951 memcpy(filter.mac.addr, mac_addr, ETH_ALEN); 952 rc = qed_llh_shadow_add_filter(cdev, ppfid, 953 QED_LLH_FILTER_TYPE_MAC, 954 &filter, &filter_idx, &ref_cnt); 955 if (rc) 956 goto err; 957 958 /* Configure the LLH only in case of a new the filter */ 959 if (ref_cnt == 1) { 960 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 961 if (rc) 962 goto err; 963 964 high = mac_addr[1] | (mac_addr[0] << 8); 965 low = mac_addr[5] | (mac_addr[4] << 8) | (mac_addr[3] << 16) | 966 (mac_addr[2] << 24); 967 rc = qed_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx, 968 0, high, low); 969 if (rc) 970 goto err; 971 } 972 973 DP_VERBOSE(cdev, 974 QED_MSG_SP, 975 "LLH: Added MAC filter [%pM] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n", 976 mac_addr, ppfid, abs_ppfid, filter_idx, ref_cnt); 977 978 goto out; 979 980 err: DP_NOTICE(cdev, 981 "LLH: Failed to add MAC filter [%pM] to ppfid %hhd\n", 982 mac_addr, ppfid); 983 out: 984 qed_ptt_release(p_hwfn, p_ptt); 985 986 return rc; 987 } 988 989 static int 990 qed_llh_protocol_filter_stringify(struct qed_dev *cdev, 991 enum qed_llh_prot_filter_type_t type, 992 u16 source_port_or_eth_type, 993 u16 dest_port, u8 *str, size_t str_len) 994 { 995 switch (type) { 996 case QED_LLH_FILTER_ETHERTYPE: 997 snprintf(str, str_len, "Ethertype 0x%04x", 998 source_port_or_eth_type); 999 break; 1000 case QED_LLH_FILTER_TCP_SRC_PORT: 1001 snprintf(str, str_len, "TCP src port 0x%04x", 1002 source_port_or_eth_type); 1003 break; 1004 case QED_LLH_FILTER_UDP_SRC_PORT: 1005 snprintf(str, str_len, "UDP src port 0x%04x", 1006 source_port_or_eth_type); 1007 break; 1008 case QED_LLH_FILTER_TCP_DEST_PORT: 1009 snprintf(str, str_len, "TCP dst port 0x%04x", dest_port); 1010 break; 1011 case QED_LLH_FILTER_UDP_DEST_PORT: 1012 snprintf(str, str_len, "UDP dst port 0x%04x", dest_port); 1013 break; 1014 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 1015 snprintf(str, str_len, "TCP src/dst ports 0x%04x/0x%04x", 1016 source_port_or_eth_type, dest_port); 1017 break; 1018 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 1019 snprintf(str, str_len, "UDP src/dst ports 0x%04x/0x%04x", 1020 source_port_or_eth_type, dest_port); 1021 break; 1022 default: 1023 DP_NOTICE(cdev, 1024 "Non valid LLH protocol filter type %d\n", type); 1025 return -EINVAL; 1026 } 1027 1028 return 0; 1029 } 1030 1031 static int 1032 qed_llh_protocol_filter_to_hilo(struct qed_dev *cdev, 1033 enum qed_llh_prot_filter_type_t type, 1034 u16 source_port_or_eth_type, 1035 u16 dest_port, u32 *p_high, u32 *p_low) 1036 { 1037 *p_high = 0; 1038 *p_low = 0; 1039 1040 switch (type) { 1041 case QED_LLH_FILTER_ETHERTYPE: 1042 *p_high = source_port_or_eth_type; 1043 break; 1044 case QED_LLH_FILTER_TCP_SRC_PORT: 1045 case QED_LLH_FILTER_UDP_SRC_PORT: 1046 *p_low = source_port_or_eth_type << 16; 1047 break; 1048 case QED_LLH_FILTER_TCP_DEST_PORT: 1049 case QED_LLH_FILTER_UDP_DEST_PORT: 1050 *p_low = dest_port; 1051 break; 1052 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 1053 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 1054 *p_low = (source_port_or_eth_type << 16) | dest_port; 1055 break; 1056 default: 1057 DP_NOTICE(cdev, 1058 "Non valid LLH protocol filter type %d\n", type); 1059 return -EINVAL; 1060 } 1061 1062 return 0; 1063 } 1064 1065 int 1066 qed_llh_add_protocol_filter(struct qed_dev *cdev, 1067 u8 ppfid, 1068 enum qed_llh_prot_filter_type_t type, 1069 u16 source_port_or_eth_type, u16 dest_port) 1070 { 1071 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 1072 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 1073 u8 filter_idx, abs_ppfid, str[32], type_bitmap; 1074 union qed_llh_filter filter = {}; 1075 u32 high, low, ref_cnt; 1076 int rc = 0; 1077 1078 if (!p_ptt) 1079 return -EAGAIN; 1080 1081 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits)) 1082 goto out; 1083 1084 rc = qed_llh_protocol_filter_stringify(cdev, type, 1085 source_port_or_eth_type, 1086 dest_port, str, sizeof(str)); 1087 if (rc) 1088 goto err; 1089 1090 filter.protocol.type = type; 1091 filter.protocol.source_port_or_eth_type = source_port_or_eth_type; 1092 filter.protocol.dest_port = dest_port; 1093 rc = qed_llh_shadow_add_filter(cdev, 1094 ppfid, 1095 QED_LLH_FILTER_TYPE_PROTOCOL, 1096 &filter, &filter_idx, &ref_cnt); 1097 if (rc) 1098 goto err; 1099 1100 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 1101 if (rc) 1102 goto err; 1103 1104 /* Configure the LLH only in case of a new the filter */ 1105 if (ref_cnt == 1) { 1106 rc = qed_llh_protocol_filter_to_hilo(cdev, type, 1107 source_port_or_eth_type, 1108 dest_port, &high, &low); 1109 if (rc) 1110 goto err; 1111 1112 type_bitmap = 0x1 << type; 1113 rc = qed_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, 1114 filter_idx, type_bitmap, high, low); 1115 if (rc) 1116 goto err; 1117 } 1118 1119 DP_VERBOSE(cdev, 1120 QED_MSG_SP, 1121 "LLH: Added protocol filter [%s] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n", 1122 str, ppfid, abs_ppfid, filter_idx, ref_cnt); 1123 1124 goto out; 1125 1126 err: DP_NOTICE(p_hwfn, 1127 "LLH: Failed to add protocol filter [%s] to ppfid %hhd\n", 1128 str, ppfid); 1129 out: 1130 qed_ptt_release(p_hwfn, p_ptt); 1131 1132 return rc; 1133 } 1134 1135 void qed_llh_remove_mac_filter(struct qed_dev *cdev, 1136 u8 ppfid, u8 mac_addr[ETH_ALEN]) 1137 { 1138 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 1139 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 1140 union qed_llh_filter filter = {}; 1141 u8 filter_idx, abs_ppfid; 1142 int rc = 0; 1143 u32 ref_cnt; 1144 1145 if (!p_ptt) 1146 return; 1147 1148 if (!test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits)) 1149 goto out; 1150 1151 if (QED_IS_NVMETCP_PERSONALITY(p_hwfn)) 1152 return; 1153 1154 ether_addr_copy(filter.mac.addr, mac_addr); 1155 rc = qed_llh_shadow_remove_filter(cdev, ppfid, &filter, &filter_idx, 1156 &ref_cnt); 1157 if (rc) 1158 goto err; 1159 1160 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 1161 if (rc) 1162 goto err; 1163 1164 /* Remove from the LLH in case the filter is not in use */ 1165 if (!ref_cnt) { 1166 rc = qed_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid, 1167 filter_idx); 1168 if (rc) 1169 goto err; 1170 } 1171 1172 DP_VERBOSE(cdev, 1173 QED_MSG_SP, 1174 "LLH: Removed MAC filter [%pM] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n", 1175 mac_addr, ppfid, abs_ppfid, filter_idx, ref_cnt); 1176 1177 goto out; 1178 1179 err: DP_NOTICE(cdev, 1180 "LLH: Failed to remove MAC filter [%pM] from ppfid %hhd\n", 1181 mac_addr, ppfid); 1182 out: 1183 qed_ptt_release(p_hwfn, p_ptt); 1184 } 1185 1186 void qed_llh_remove_protocol_filter(struct qed_dev *cdev, 1187 u8 ppfid, 1188 enum qed_llh_prot_filter_type_t type, 1189 u16 source_port_or_eth_type, u16 dest_port) 1190 { 1191 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 1192 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 1193 u8 filter_idx, abs_ppfid, str[32]; 1194 union qed_llh_filter filter = {}; 1195 int rc = 0; 1196 u32 ref_cnt; 1197 1198 if (!p_ptt) 1199 return; 1200 1201 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits)) 1202 goto out; 1203 1204 rc = qed_llh_protocol_filter_stringify(cdev, type, 1205 source_port_or_eth_type, 1206 dest_port, str, sizeof(str)); 1207 if (rc) 1208 goto err; 1209 1210 filter.protocol.type = type; 1211 filter.protocol.source_port_or_eth_type = source_port_or_eth_type; 1212 filter.protocol.dest_port = dest_port; 1213 rc = qed_llh_shadow_remove_filter(cdev, ppfid, &filter, &filter_idx, 1214 &ref_cnt); 1215 if (rc) 1216 goto err; 1217 1218 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 1219 if (rc) 1220 goto err; 1221 1222 /* Remove from the LLH in case the filter is not in use */ 1223 if (!ref_cnt) { 1224 rc = qed_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid, 1225 filter_idx); 1226 if (rc) 1227 goto err; 1228 } 1229 1230 DP_VERBOSE(cdev, 1231 QED_MSG_SP, 1232 "LLH: Removed protocol filter [%s] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n", 1233 str, ppfid, abs_ppfid, filter_idx, ref_cnt); 1234 1235 goto out; 1236 1237 err: DP_NOTICE(cdev, 1238 "LLH: Failed to remove protocol filter [%s] from ppfid %hhd\n", 1239 str, ppfid); 1240 out: 1241 qed_ptt_release(p_hwfn, p_ptt); 1242 } 1243 1244 /******************************* NIG LLH - End ********************************/ 1245 1246 #define QED_MIN_DPIS (4) 1247 #define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS) 1248 1249 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, 1250 struct qed_ptt *p_ptt, enum BAR_ID bar_id) 1251 { 1252 u32 bar_reg = (bar_id == BAR_ID_0 ? 1253 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); 1254 u32 val; 1255 1256 if (IS_VF(p_hwfn->cdev)) 1257 return qed_vf_hw_bar_size(p_hwfn, bar_id); 1258 1259 val = qed_rd(p_hwfn, p_ptt, bar_reg); 1260 if (val) 1261 return 1 << (val + 15); 1262 1263 /* Old MFW initialized above registered only conditionally */ 1264 if (p_hwfn->cdev->num_hwfns > 1) { 1265 DP_INFO(p_hwfn, 1266 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n"); 1267 return BAR_ID_0 ? 256 * 1024 : 512 * 1024; 1268 } else { 1269 DP_INFO(p_hwfn, 1270 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n"); 1271 return 512 * 1024; 1272 } 1273 } 1274 1275 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level) 1276 { 1277 u32 i; 1278 1279 cdev->dp_level = dp_level; 1280 cdev->dp_module = dp_module; 1281 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 1282 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1283 1284 p_hwfn->dp_level = dp_level; 1285 p_hwfn->dp_module = dp_module; 1286 } 1287 } 1288 1289 void qed_init_struct(struct qed_dev *cdev) 1290 { 1291 u8 i; 1292 1293 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 1294 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1295 1296 p_hwfn->cdev = cdev; 1297 p_hwfn->my_id = i; 1298 p_hwfn->b_active = false; 1299 1300 mutex_init(&p_hwfn->dmae_info.mutex); 1301 } 1302 1303 /* hwfn 0 is always active */ 1304 cdev->hwfns[0].b_active = true; 1305 1306 /* set the default cache alignment to 128 */ 1307 cdev->cache_shift = 7; 1308 } 1309 1310 static void qed_qm_info_free(struct qed_hwfn *p_hwfn) 1311 { 1312 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1313 1314 kfree(qm_info->qm_pq_params); 1315 qm_info->qm_pq_params = NULL; 1316 kfree(qm_info->qm_vport_params); 1317 qm_info->qm_vport_params = NULL; 1318 kfree(qm_info->qm_port_params); 1319 qm_info->qm_port_params = NULL; 1320 kfree(qm_info->wfq_data); 1321 qm_info->wfq_data = NULL; 1322 } 1323 1324 static void qed_dbg_user_data_free(struct qed_hwfn *p_hwfn) 1325 { 1326 kfree(p_hwfn->dbg_user_info); 1327 p_hwfn->dbg_user_info = NULL; 1328 } 1329 1330 void qed_resc_free(struct qed_dev *cdev) 1331 { 1332 struct qed_rdma_info *rdma_info; 1333 struct qed_hwfn *p_hwfn; 1334 int i; 1335 1336 if (IS_VF(cdev)) { 1337 for_each_hwfn(cdev, i) 1338 qed_l2_free(&cdev->hwfns[i]); 1339 return; 1340 } 1341 1342 kfree(cdev->fw_data); 1343 cdev->fw_data = NULL; 1344 1345 kfree(cdev->reset_stats); 1346 cdev->reset_stats = NULL; 1347 1348 qed_llh_free(cdev); 1349 1350 for_each_hwfn(cdev, i) { 1351 p_hwfn = cdev->hwfns + i; 1352 rdma_info = p_hwfn->p_rdma_info; 1353 1354 qed_cxt_mngr_free(p_hwfn); 1355 qed_qm_info_free(p_hwfn); 1356 qed_spq_free(p_hwfn); 1357 qed_eq_free(p_hwfn); 1358 qed_consq_free(p_hwfn); 1359 qed_int_free(p_hwfn); 1360 #ifdef CONFIG_QED_LL2 1361 qed_ll2_free(p_hwfn); 1362 #endif 1363 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 1364 qed_fcoe_free(p_hwfn); 1365 1366 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 1367 qed_iscsi_free(p_hwfn); 1368 qed_ooo_free(p_hwfn); 1369 } 1370 1371 if (p_hwfn->hw_info.personality == QED_PCI_NVMETCP) { 1372 qed_nvmetcp_free(p_hwfn); 1373 qed_ooo_free(p_hwfn); 1374 } 1375 1376 if (QED_IS_RDMA_PERSONALITY(p_hwfn) && rdma_info) { 1377 qed_spq_unregister_async_cb(p_hwfn, rdma_info->proto); 1378 qed_rdma_info_free(p_hwfn); 1379 } 1380 1381 qed_spq_unregister_async_cb(p_hwfn, PROTOCOLID_COMMON); 1382 qed_iov_free(p_hwfn); 1383 qed_l2_free(p_hwfn); 1384 qed_dmae_info_free(p_hwfn); 1385 qed_dcbx_info_free(p_hwfn); 1386 qed_dbg_user_data_free(p_hwfn); 1387 qed_fw_overlay_mem_free(p_hwfn, &p_hwfn->fw_overlay_mem); 1388 1389 /* Destroy doorbell recovery mechanism */ 1390 qed_db_recovery_teardown(p_hwfn); 1391 } 1392 } 1393 1394 /******************** QM initialization *******************/ 1395 #define ACTIVE_TCS_BMAP 0x9f 1396 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf 1397 1398 /* determines the physical queue flags for a given PF. */ 1399 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn) 1400 { 1401 u32 flags; 1402 1403 /* common flags */ 1404 flags = PQ_FLAGS_LB; 1405 1406 /* feature flags */ 1407 if (IS_QED_SRIOV(p_hwfn->cdev)) 1408 flags |= PQ_FLAGS_VFS; 1409 1410 /* protocol flags */ 1411 switch (p_hwfn->hw_info.personality) { 1412 case QED_PCI_ETH: 1413 flags |= PQ_FLAGS_MCOS; 1414 break; 1415 case QED_PCI_FCOE: 1416 flags |= PQ_FLAGS_OFLD; 1417 break; 1418 case QED_PCI_ISCSI: 1419 case QED_PCI_NVMETCP: 1420 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD; 1421 break; 1422 case QED_PCI_ETH_ROCE: 1423 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT; 1424 if (IS_QED_MULTI_TC_ROCE(p_hwfn)) 1425 flags |= PQ_FLAGS_MTC; 1426 break; 1427 case QED_PCI_ETH_IWARP: 1428 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO | 1429 PQ_FLAGS_OFLD; 1430 break; 1431 default: 1432 DP_ERR(p_hwfn, 1433 "unknown personality %d\n", p_hwfn->hw_info.personality); 1434 return 0; 1435 } 1436 1437 return flags; 1438 } 1439 1440 /* Getters for resource amounts necessary for qm initialization */ 1441 static u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn) 1442 { 1443 return p_hwfn->hw_info.num_hw_tc; 1444 } 1445 1446 static u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn) 1447 { 1448 return IS_QED_SRIOV(p_hwfn->cdev) ? 1449 p_hwfn->cdev->p_iov_info->total_vfs : 0; 1450 } 1451 1452 static u8 qed_init_qm_get_num_mtc_tcs(struct qed_hwfn *p_hwfn) 1453 { 1454 u32 pq_flags = qed_get_pq_flags(p_hwfn); 1455 1456 if (!(PQ_FLAGS_MTC & pq_flags)) 1457 return 1; 1458 1459 return qed_init_qm_get_num_tcs(p_hwfn); 1460 } 1461 1462 #define NUM_DEFAULT_RLS 1 1463 1464 static u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn) 1465 { 1466 u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn); 1467 1468 /* num RLs can't exceed resource amount of rls or vports */ 1469 num_pf_rls = (u16)min_t(u32, RESC_NUM(p_hwfn, QED_RL), 1470 RESC_NUM(p_hwfn, QED_VPORT)); 1471 1472 /* Make sure after we reserve there's something left */ 1473 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) 1474 return 0; 1475 1476 /* subtract rls necessary for VFs and one default one for the PF */ 1477 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS; 1478 1479 return num_pf_rls; 1480 } 1481 1482 static u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn) 1483 { 1484 u32 pq_flags = qed_get_pq_flags(p_hwfn); 1485 1486 /* all pqs share the same vport, except for vfs and pf_rl pqs */ 1487 return (!!(PQ_FLAGS_RLS & pq_flags)) * 1488 qed_init_qm_get_num_pf_rls(p_hwfn) + 1489 (!!(PQ_FLAGS_VFS & pq_flags)) * 1490 qed_init_qm_get_num_vfs(p_hwfn) + 1; 1491 } 1492 1493 /* calc amount of PQs according to the requested flags */ 1494 static u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn) 1495 { 1496 u32 pq_flags = qed_get_pq_flags(p_hwfn); 1497 1498 return (!!(PQ_FLAGS_RLS & pq_flags)) * 1499 qed_init_qm_get_num_pf_rls(p_hwfn) + 1500 (!!(PQ_FLAGS_MCOS & pq_flags)) * 1501 qed_init_qm_get_num_tcs(p_hwfn) + 1502 (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) + 1503 (!!(PQ_FLAGS_ACK & pq_flags)) + 1504 (!!(PQ_FLAGS_OFLD & pq_flags)) * 1505 qed_init_qm_get_num_mtc_tcs(p_hwfn) + 1506 (!!(PQ_FLAGS_LLT & pq_flags)) * 1507 qed_init_qm_get_num_mtc_tcs(p_hwfn) + 1508 (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn); 1509 } 1510 1511 /* initialize the top level QM params */ 1512 static void qed_init_qm_params(struct qed_hwfn *p_hwfn) 1513 { 1514 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1515 bool four_port; 1516 1517 /* pq and vport bases for this PF */ 1518 qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ); 1519 qm_info->start_vport = (u8)RESC_START(p_hwfn, QED_VPORT); 1520 1521 /* rate limiting and weighted fair queueing are always enabled */ 1522 qm_info->vport_rl_en = true; 1523 qm_info->vport_wfq_en = true; 1524 1525 /* TC config is different for AH 4 port */ 1526 four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2; 1527 1528 /* in AH 4 port we have fewer TCs per port */ 1529 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 : 1530 NUM_OF_PHYS_TCS; 1531 1532 /* unless MFW indicated otherwise, ooo_tc == 3 for 1533 * AH 4-port and 4 otherwise. 1534 */ 1535 if (!qm_info->ooo_tc) 1536 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC : 1537 DCBX_TCP_OOO_TC; 1538 } 1539 1540 /* initialize qm vport params */ 1541 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn) 1542 { 1543 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1544 u8 i; 1545 1546 /* all vports participate in weighted fair queueing */ 1547 for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++) 1548 qm_info->qm_vport_params[i].wfq = 1; 1549 } 1550 1551 /* initialize qm port params */ 1552 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn) 1553 { 1554 /* Initialize qm port parameters */ 1555 u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine; 1556 struct qed_dev *cdev = p_hwfn->cdev; 1557 1558 /* indicate how ooo and high pri traffic is dealt with */ 1559 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ? 1560 ACTIVE_TCS_BMAP_4PORT_K2 : 1561 ACTIVE_TCS_BMAP; 1562 1563 for (i = 0; i < num_ports; i++) { 1564 struct init_qm_port_params *p_qm_port = 1565 &p_hwfn->qm_info.qm_port_params[i]; 1566 u16 pbf_max_cmd_lines; 1567 1568 p_qm_port->active = 1; 1569 p_qm_port->active_phys_tcs = active_phys_tcs; 1570 pbf_max_cmd_lines = (u16)NUM_OF_PBF_CMD_LINES(cdev); 1571 p_qm_port->num_pbf_cmd_lines = pbf_max_cmd_lines / num_ports; 1572 p_qm_port->num_btb_blocks = NUM_OF_BTB_BLOCKS(cdev) / num_ports; 1573 } 1574 } 1575 1576 /* Reset the params which must be reset for qm init. QM init may be called as 1577 * a result of flows other than driver load (e.g. dcbx renegotiation). Other 1578 * params may be affected by the init but would simply recalculate to the same 1579 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not 1580 * affected as these amounts stay the same. 1581 */ 1582 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn) 1583 { 1584 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1585 1586 qm_info->num_pqs = 0; 1587 qm_info->num_vports = 0; 1588 qm_info->num_pf_rls = 0; 1589 qm_info->num_vf_pqs = 0; 1590 qm_info->first_vf_pq = 0; 1591 qm_info->first_mcos_pq = 0; 1592 qm_info->first_rl_pq = 0; 1593 } 1594 1595 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn) 1596 { 1597 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1598 1599 qm_info->num_vports++; 1600 1601 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn)) 1602 DP_ERR(p_hwfn, 1603 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n", 1604 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn)); 1605 } 1606 1607 /* initialize a single pq and manage qm_info resources accounting. 1608 * The pq_init_flags param determines whether the PQ is rate limited 1609 * (for VF or PF) and whether a new vport is allocated to the pq or not 1610 * (i.e. vport will be shared). 1611 */ 1612 1613 /* flags for pq init */ 1614 #define PQ_INIT_SHARE_VPORT BIT(0) 1615 #define PQ_INIT_PF_RL BIT(1) 1616 #define PQ_INIT_VF_RL BIT(2) 1617 1618 /* defines for pq init */ 1619 #define PQ_INIT_DEFAULT_WRR_GROUP 1 1620 #define PQ_INIT_DEFAULT_TC 0 1621 1622 void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc) 1623 { 1624 p_info->offload_tc = tc; 1625 p_info->offload_tc_set = true; 1626 } 1627 1628 static bool qed_is_offload_tc_set(struct qed_hwfn *p_hwfn) 1629 { 1630 return p_hwfn->hw_info.offload_tc_set; 1631 } 1632 1633 static u32 qed_get_offload_tc(struct qed_hwfn *p_hwfn) 1634 { 1635 if (qed_is_offload_tc_set(p_hwfn)) 1636 return p_hwfn->hw_info.offload_tc; 1637 1638 return PQ_INIT_DEFAULT_TC; 1639 } 1640 1641 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn, 1642 struct qed_qm_info *qm_info, 1643 u8 tc, u32 pq_init_flags) 1644 { 1645 u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn); 1646 1647 if (pq_idx > max_pq) 1648 DP_ERR(p_hwfn, 1649 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq); 1650 1651 /* init pq params */ 1652 qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id; 1653 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport + 1654 qm_info->num_vports; 1655 qm_info->qm_pq_params[pq_idx].tc_id = tc; 1656 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP; 1657 qm_info->qm_pq_params[pq_idx].rl_valid = 1658 (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL); 1659 1660 /* qm params accounting */ 1661 qm_info->num_pqs++; 1662 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT)) 1663 qm_info->num_vports++; 1664 1665 if (pq_init_flags & PQ_INIT_PF_RL) 1666 qm_info->num_pf_rls++; 1667 1668 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn)) 1669 DP_ERR(p_hwfn, 1670 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n", 1671 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn)); 1672 1673 if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn)) 1674 DP_ERR(p_hwfn, 1675 "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n", 1676 qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn)); 1677 } 1678 1679 /* get pq index according to PQ_FLAGS */ 1680 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn, 1681 unsigned long pq_flags) 1682 { 1683 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1684 1685 /* Can't have multiple flags set here */ 1686 if (bitmap_weight(&pq_flags, 1687 sizeof(pq_flags) * BITS_PER_BYTE) > 1) { 1688 DP_ERR(p_hwfn, "requested multiple pq flags 0x%lx\n", pq_flags); 1689 goto err; 1690 } 1691 1692 if (!(qed_get_pq_flags(p_hwfn) & pq_flags)) { 1693 DP_ERR(p_hwfn, "pq flag 0x%lx is not set\n", pq_flags); 1694 goto err; 1695 } 1696 1697 switch (pq_flags) { 1698 case PQ_FLAGS_RLS: 1699 return &qm_info->first_rl_pq; 1700 case PQ_FLAGS_MCOS: 1701 return &qm_info->first_mcos_pq; 1702 case PQ_FLAGS_LB: 1703 return &qm_info->pure_lb_pq; 1704 case PQ_FLAGS_OOO: 1705 return &qm_info->ooo_pq; 1706 case PQ_FLAGS_ACK: 1707 return &qm_info->pure_ack_pq; 1708 case PQ_FLAGS_OFLD: 1709 return &qm_info->first_ofld_pq; 1710 case PQ_FLAGS_LLT: 1711 return &qm_info->first_llt_pq; 1712 case PQ_FLAGS_VFS: 1713 return &qm_info->first_vf_pq; 1714 default: 1715 goto err; 1716 } 1717 1718 err: 1719 return &qm_info->start_pq; 1720 } 1721 1722 /* save pq index in qm info */ 1723 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn, 1724 u32 pq_flags, u16 pq_val) 1725 { 1726 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags); 1727 1728 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val; 1729 } 1730 1731 /* get tx pq index, with the PQ TX base already set (ready for context init) */ 1732 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags) 1733 { 1734 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags); 1735 1736 return *base_pq_idx + CM_TX_PQ_BASE; 1737 } 1738 1739 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc) 1740 { 1741 u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn); 1742 1743 if (max_tc == 0) { 1744 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n", 1745 PQ_FLAGS_MCOS); 1746 return p_hwfn->qm_info.start_pq; 1747 } 1748 1749 if (tc > max_tc) 1750 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc); 1751 1752 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc); 1753 } 1754 1755 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf) 1756 { 1757 u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn); 1758 1759 if (max_vf == 0) { 1760 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n", 1761 PQ_FLAGS_VFS); 1762 return p_hwfn->qm_info.start_pq; 1763 } 1764 1765 if (vf > max_vf) 1766 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf); 1767 1768 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf); 1769 } 1770 1771 u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc) 1772 { 1773 u16 first_ofld_pq, pq_offset; 1774 1775 first_ofld_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD); 1776 pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ? 1777 tc : PQ_INIT_DEFAULT_TC; 1778 1779 return first_ofld_pq + pq_offset; 1780 } 1781 1782 u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc) 1783 { 1784 u16 first_llt_pq, pq_offset; 1785 1786 first_llt_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LLT); 1787 pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ? 1788 tc : PQ_INIT_DEFAULT_TC; 1789 1790 return first_llt_pq + pq_offset; 1791 } 1792 1793 /* Functions for creating specific types of pqs */ 1794 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn) 1795 { 1796 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1797 1798 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB)) 1799 return; 1800 1801 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs); 1802 qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT); 1803 } 1804 1805 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn) 1806 { 1807 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1808 1809 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO)) 1810 return; 1811 1812 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs); 1813 qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT); 1814 } 1815 1816 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn) 1817 { 1818 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1819 1820 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK)) 1821 return; 1822 1823 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs); 1824 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn), 1825 PQ_INIT_SHARE_VPORT); 1826 } 1827 1828 static void qed_init_qm_mtc_pqs(struct qed_hwfn *p_hwfn) 1829 { 1830 u8 num_tcs = qed_init_qm_get_num_mtc_tcs(p_hwfn); 1831 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1832 u8 tc; 1833 1834 /* override pq's TC if offload TC is set */ 1835 for (tc = 0; tc < num_tcs; tc++) 1836 qed_init_qm_pq(p_hwfn, qm_info, 1837 qed_is_offload_tc_set(p_hwfn) ? 1838 p_hwfn->hw_info.offload_tc : tc, 1839 PQ_INIT_SHARE_VPORT); 1840 } 1841 1842 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn) 1843 { 1844 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1845 1846 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD)) 1847 return; 1848 1849 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs); 1850 qed_init_qm_mtc_pqs(p_hwfn); 1851 } 1852 1853 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn) 1854 { 1855 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1856 1857 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT)) 1858 return; 1859 1860 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs); 1861 qed_init_qm_mtc_pqs(p_hwfn); 1862 } 1863 1864 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn) 1865 { 1866 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1867 u8 tc_idx; 1868 1869 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS)) 1870 return; 1871 1872 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs); 1873 for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++) 1874 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT); 1875 } 1876 1877 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn) 1878 { 1879 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1880 u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn); 1881 1882 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS)) 1883 return; 1884 1885 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs); 1886 qm_info->num_vf_pqs = num_vfs; 1887 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) 1888 qed_init_qm_pq(p_hwfn, 1889 qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL); 1890 } 1891 1892 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn) 1893 { 1894 u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn); 1895 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1896 1897 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS)) 1898 return; 1899 1900 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs); 1901 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++) 1902 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn), 1903 PQ_INIT_PF_RL); 1904 } 1905 1906 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn) 1907 { 1908 /* rate limited pqs, must come first (FW assumption) */ 1909 qed_init_qm_rl_pqs(p_hwfn); 1910 1911 /* pqs for multi cos */ 1912 qed_init_qm_mcos_pqs(p_hwfn); 1913 1914 /* pure loopback pq */ 1915 qed_init_qm_lb_pq(p_hwfn); 1916 1917 /* out of order pq */ 1918 qed_init_qm_ooo_pq(p_hwfn); 1919 1920 /* pure ack pq */ 1921 qed_init_qm_pure_ack_pq(p_hwfn); 1922 1923 /* pq for offloaded protocol */ 1924 qed_init_qm_offload_pq(p_hwfn); 1925 1926 /* low latency pq */ 1927 qed_init_qm_low_latency_pq(p_hwfn); 1928 1929 /* done sharing vports */ 1930 qed_init_qm_advance_vport(p_hwfn); 1931 1932 /* pqs for vfs */ 1933 qed_init_qm_vf_pqs(p_hwfn); 1934 } 1935 1936 /* compare values of getters against resources amounts */ 1937 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn) 1938 { 1939 if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) { 1940 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n"); 1941 return -EINVAL; 1942 } 1943 1944 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ)) 1945 return 0; 1946 1947 if (QED_IS_ROCE_PERSONALITY(p_hwfn)) { 1948 p_hwfn->hw_info.multi_tc_roce_en = false; 1949 DP_NOTICE(p_hwfn, 1950 "multi-tc roce was disabled to reduce requested amount of pqs\n"); 1951 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ)) 1952 return 0; 1953 } 1954 1955 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n"); 1956 return -EINVAL; 1957 } 1958 1959 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn) 1960 { 1961 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1962 struct init_qm_vport_params *vport; 1963 struct init_qm_port_params *port; 1964 struct init_qm_pq_params *pq; 1965 int i, tc; 1966 1967 /* top level params */ 1968 DP_VERBOSE(p_hwfn, 1969 NETIF_MSG_HW, 1970 "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, llt_pq %d, pure_ack_pq %d\n", 1971 qm_info->start_pq, 1972 qm_info->start_vport, 1973 qm_info->pure_lb_pq, 1974 qm_info->first_ofld_pq, 1975 qm_info->first_llt_pq, 1976 qm_info->pure_ack_pq); 1977 DP_VERBOSE(p_hwfn, 1978 NETIF_MSG_HW, 1979 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n", 1980 qm_info->ooo_pq, 1981 qm_info->first_vf_pq, 1982 qm_info->num_pqs, 1983 qm_info->num_vf_pqs, 1984 qm_info->num_vports, qm_info->max_phys_tcs_per_port); 1985 DP_VERBOSE(p_hwfn, 1986 NETIF_MSG_HW, 1987 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n", 1988 qm_info->pf_rl_en, 1989 qm_info->pf_wfq_en, 1990 qm_info->vport_rl_en, 1991 qm_info->vport_wfq_en, 1992 qm_info->pf_wfq, 1993 qm_info->pf_rl, 1994 qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn)); 1995 1996 /* port table */ 1997 for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) { 1998 port = &(qm_info->qm_port_params[i]); 1999 DP_VERBOSE(p_hwfn, 2000 NETIF_MSG_HW, 2001 "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n", 2002 i, 2003 port->active, 2004 port->active_phys_tcs, 2005 port->num_pbf_cmd_lines, 2006 port->num_btb_blocks, port->reserved); 2007 } 2008 2009 /* vport table */ 2010 for (i = 0; i < qm_info->num_vports; i++) { 2011 vport = &(qm_info->qm_vport_params[i]); 2012 DP_VERBOSE(p_hwfn, 2013 NETIF_MSG_HW, 2014 "vport idx %d, wfq %d, first_tx_pq_id [ ", 2015 qm_info->start_vport + i, vport->wfq); 2016 for (tc = 0; tc < NUM_OF_TCS; tc++) 2017 DP_VERBOSE(p_hwfn, 2018 NETIF_MSG_HW, 2019 "%d ", vport->first_tx_pq_id[tc]); 2020 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n"); 2021 } 2022 2023 /* pq table */ 2024 for (i = 0; i < qm_info->num_pqs; i++) { 2025 pq = &(qm_info->qm_pq_params[i]); 2026 DP_VERBOSE(p_hwfn, 2027 NETIF_MSG_HW, 2028 "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d rl_id %d\n", 2029 qm_info->start_pq + i, 2030 pq->port_id, 2031 pq->vport_id, 2032 pq->tc_id, pq->wrr_group, pq->rl_valid, pq->rl_id); 2033 } 2034 } 2035 2036 static void qed_init_qm_info(struct qed_hwfn *p_hwfn) 2037 { 2038 /* reset params required for init run */ 2039 qed_init_qm_reset_params(p_hwfn); 2040 2041 /* init QM top level params */ 2042 qed_init_qm_params(p_hwfn); 2043 2044 /* init QM port params */ 2045 qed_init_qm_port_params(p_hwfn); 2046 2047 /* init QM vport params */ 2048 qed_init_qm_vport_params(p_hwfn); 2049 2050 /* init QM physical queue params */ 2051 qed_init_qm_pq_params(p_hwfn); 2052 2053 /* display all that init */ 2054 qed_dp_init_qm_params(p_hwfn); 2055 } 2056 2057 /* This function reconfigures the QM pf on the fly. 2058 * For this purpose we: 2059 * 1. reconfigure the QM database 2060 * 2. set new values to runtime array 2061 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM 2062 * 4. activate init tool in QM_PF stage 2063 * 5. send an sdm_qm_cmd through rbc interface to release the QM 2064 */ 2065 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2066 { 2067 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 2068 bool b_rc; 2069 int rc; 2070 2071 /* initialize qed's qm data structure */ 2072 qed_init_qm_info(p_hwfn); 2073 2074 /* stop PF's qm queues */ 2075 spin_lock_bh(&qm_lock); 2076 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true, 2077 qm_info->start_pq, qm_info->num_pqs); 2078 spin_unlock_bh(&qm_lock); 2079 if (!b_rc) 2080 return -EINVAL; 2081 2082 /* prepare QM portion of runtime array */ 2083 qed_qm_init_pf(p_hwfn, p_ptt, false); 2084 2085 /* activate init tool on runtime array */ 2086 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id, 2087 p_hwfn->hw_info.hw_mode); 2088 if (rc) 2089 return rc; 2090 2091 /* start PF's qm queues */ 2092 spin_lock_bh(&qm_lock); 2093 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true, 2094 qm_info->start_pq, qm_info->num_pqs); 2095 spin_unlock_bh(&qm_lock); 2096 if (!b_rc) 2097 return -EINVAL; 2098 2099 return 0; 2100 } 2101 2102 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn) 2103 { 2104 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 2105 int rc; 2106 2107 rc = qed_init_qm_sanity(p_hwfn); 2108 if (rc) 2109 goto alloc_err; 2110 2111 qm_info->qm_pq_params = kcalloc(qed_init_qm_get_num_pqs(p_hwfn), 2112 sizeof(*qm_info->qm_pq_params), 2113 GFP_KERNEL); 2114 if (!qm_info->qm_pq_params) 2115 goto alloc_err; 2116 2117 qm_info->qm_vport_params = kcalloc(qed_init_qm_get_num_vports(p_hwfn), 2118 sizeof(*qm_info->qm_vport_params), 2119 GFP_KERNEL); 2120 if (!qm_info->qm_vport_params) 2121 goto alloc_err; 2122 2123 qm_info->qm_port_params = kcalloc(p_hwfn->cdev->num_ports_in_engine, 2124 sizeof(*qm_info->qm_port_params), 2125 GFP_KERNEL); 2126 if (!qm_info->qm_port_params) 2127 goto alloc_err; 2128 2129 qm_info->wfq_data = kcalloc(qed_init_qm_get_num_vports(p_hwfn), 2130 sizeof(*qm_info->wfq_data), 2131 GFP_KERNEL); 2132 if (!qm_info->wfq_data) 2133 goto alloc_err; 2134 2135 return 0; 2136 2137 alloc_err: 2138 DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n"); 2139 qed_qm_info_free(p_hwfn); 2140 return -ENOMEM; 2141 } 2142 2143 int qed_resc_alloc(struct qed_dev *cdev) 2144 { 2145 u32 rdma_tasks, excess_tasks; 2146 u32 line_count; 2147 int i, rc = 0; 2148 2149 if (IS_VF(cdev)) { 2150 for_each_hwfn(cdev, i) { 2151 rc = qed_l2_alloc(&cdev->hwfns[i]); 2152 if (rc) 2153 return rc; 2154 } 2155 return rc; 2156 } 2157 2158 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL); 2159 if (!cdev->fw_data) 2160 return -ENOMEM; 2161 2162 for_each_hwfn(cdev, i) { 2163 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2164 u32 n_eqes, num_cons; 2165 2166 /* Initialize the doorbell recovery mechanism */ 2167 rc = qed_db_recovery_setup(p_hwfn); 2168 if (rc) 2169 goto alloc_err; 2170 2171 /* First allocate the context manager structure */ 2172 rc = qed_cxt_mngr_alloc(p_hwfn); 2173 if (rc) 2174 goto alloc_err; 2175 2176 /* Set the HW cid/tid numbers (in the contest manager) 2177 * Must be done prior to any further computations. 2178 */ 2179 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS); 2180 if (rc) 2181 goto alloc_err; 2182 2183 rc = qed_alloc_qm_data(p_hwfn); 2184 if (rc) 2185 goto alloc_err; 2186 2187 /* init qm info */ 2188 qed_init_qm_info(p_hwfn); 2189 2190 /* Compute the ILT client partition */ 2191 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count); 2192 if (rc) { 2193 DP_NOTICE(p_hwfn, 2194 "too many ILT lines; re-computing with less lines\n"); 2195 /* In case there are not enough ILT lines we reduce the 2196 * number of RDMA tasks and re-compute. 2197 */ 2198 excess_tasks = 2199 qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count); 2200 if (!excess_tasks) 2201 goto alloc_err; 2202 2203 rdma_tasks = RDMA_MAX_TIDS - excess_tasks; 2204 rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks); 2205 if (rc) 2206 goto alloc_err; 2207 2208 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count); 2209 if (rc) { 2210 DP_ERR(p_hwfn, 2211 "failed ILT compute. Requested too many lines: %u\n", 2212 line_count); 2213 2214 goto alloc_err; 2215 } 2216 } 2217 2218 /* CID map / ILT shadow table / T2 2219 * The table sizes are determined by the computations above 2220 */ 2221 rc = qed_cxt_tables_alloc(p_hwfn); 2222 if (rc) 2223 goto alloc_err; 2224 2225 /* SPQ, must follow ILT because initializes SPQ context */ 2226 rc = qed_spq_alloc(p_hwfn); 2227 if (rc) 2228 goto alloc_err; 2229 2230 /* SP status block allocation */ 2231 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn, 2232 RESERVED_PTT_DPC); 2233 2234 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt); 2235 if (rc) 2236 goto alloc_err; 2237 2238 rc = qed_iov_alloc(p_hwfn); 2239 if (rc) 2240 goto alloc_err; 2241 2242 /* EQ */ 2243 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain); 2244 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) { 2245 u32 n_srq = qed_cxt_get_total_srq_count(p_hwfn); 2246 enum protocol_type rdma_proto; 2247 2248 if (QED_IS_ROCE_PERSONALITY(p_hwfn)) 2249 rdma_proto = PROTOCOLID_ROCE; 2250 else 2251 rdma_proto = PROTOCOLID_IWARP; 2252 2253 num_cons = qed_cxt_get_proto_cid_count(p_hwfn, 2254 rdma_proto, 2255 NULL) * 2; 2256 /* EQ should be able to get events from all SRQ's 2257 * at the same time 2258 */ 2259 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB + n_srq; 2260 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI || 2261 p_hwfn->hw_info.personality == QED_PCI_NVMETCP) { 2262 num_cons = 2263 qed_cxt_get_proto_cid_count(p_hwfn, 2264 PROTOCOLID_TCP_ULP, 2265 NULL); 2266 n_eqes += 2 * num_cons; 2267 } 2268 2269 if (n_eqes > 0xFFFF) { 2270 DP_ERR(p_hwfn, 2271 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n", 2272 n_eqes, 0xFFFF); 2273 goto alloc_no_mem; 2274 } 2275 2276 rc = qed_eq_alloc(p_hwfn, (u16)n_eqes); 2277 if (rc) 2278 goto alloc_err; 2279 2280 rc = qed_consq_alloc(p_hwfn); 2281 if (rc) 2282 goto alloc_err; 2283 2284 rc = qed_l2_alloc(p_hwfn); 2285 if (rc) 2286 goto alloc_err; 2287 2288 #ifdef CONFIG_QED_LL2 2289 if (p_hwfn->using_ll2) { 2290 rc = qed_ll2_alloc(p_hwfn); 2291 if (rc) 2292 goto alloc_err; 2293 } 2294 #endif 2295 2296 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) { 2297 rc = qed_fcoe_alloc(p_hwfn); 2298 if (rc) 2299 goto alloc_err; 2300 } 2301 2302 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 2303 rc = qed_iscsi_alloc(p_hwfn); 2304 if (rc) 2305 goto alloc_err; 2306 rc = qed_ooo_alloc(p_hwfn); 2307 if (rc) 2308 goto alloc_err; 2309 } 2310 2311 if (p_hwfn->hw_info.personality == QED_PCI_NVMETCP) { 2312 rc = qed_nvmetcp_alloc(p_hwfn); 2313 if (rc) 2314 goto alloc_err; 2315 rc = qed_ooo_alloc(p_hwfn); 2316 if (rc) 2317 goto alloc_err; 2318 } 2319 2320 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) { 2321 rc = qed_rdma_info_alloc(p_hwfn); 2322 if (rc) 2323 goto alloc_err; 2324 } 2325 2326 /* DMA info initialization */ 2327 rc = qed_dmae_info_alloc(p_hwfn); 2328 if (rc) 2329 goto alloc_err; 2330 2331 /* DCBX initialization */ 2332 rc = qed_dcbx_info_alloc(p_hwfn); 2333 if (rc) 2334 goto alloc_err; 2335 2336 rc = qed_dbg_alloc_user_data(p_hwfn, &p_hwfn->dbg_user_info); 2337 if (rc) 2338 goto alloc_err; 2339 } 2340 2341 rc = qed_llh_alloc(cdev); 2342 if (rc) { 2343 DP_NOTICE(cdev, 2344 "Failed to allocate memory for the llh_info structure\n"); 2345 goto alloc_err; 2346 } 2347 2348 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL); 2349 if (!cdev->reset_stats) 2350 goto alloc_no_mem; 2351 2352 return 0; 2353 2354 alloc_no_mem: 2355 rc = -ENOMEM; 2356 alloc_err: 2357 qed_resc_free(cdev); 2358 return rc; 2359 } 2360 2361 static int qed_fw_err_handler(struct qed_hwfn *p_hwfn, 2362 u8 opcode, 2363 u16 echo, 2364 union event_ring_data *data, u8 fw_return_code) 2365 { 2366 if (fw_return_code != COMMON_ERR_CODE_ERROR) 2367 goto eqe_unexpected; 2368 2369 if (data->err_data.recovery_scope == ERR_SCOPE_FUNC && 2370 le16_to_cpu(data->err_data.entity_id) >= MAX_NUM_PFS) { 2371 qed_sriov_vfpf_malicious(p_hwfn, &data->err_data); 2372 return 0; 2373 } 2374 2375 eqe_unexpected: 2376 DP_ERR(p_hwfn, 2377 "Skipping unexpected eqe 0x%02x, FW return code 0x%x, echo 0x%x\n", 2378 opcode, fw_return_code, echo); 2379 return -EINVAL; 2380 } 2381 2382 static int qed_common_eqe_event(struct qed_hwfn *p_hwfn, 2383 u8 opcode, 2384 __le16 echo, 2385 union event_ring_data *data, 2386 u8 fw_return_code) 2387 { 2388 switch (opcode) { 2389 case COMMON_EVENT_VF_PF_CHANNEL: 2390 case COMMON_EVENT_VF_FLR: 2391 return qed_sriov_eqe_event(p_hwfn, opcode, echo, data, 2392 fw_return_code); 2393 case COMMON_EVENT_FW_ERROR: 2394 return qed_fw_err_handler(p_hwfn, opcode, 2395 le16_to_cpu(echo), data, 2396 fw_return_code); 2397 default: 2398 DP_INFO(p_hwfn->cdev, "Unknown eqe event 0x%02x, echo 0x%x\n", 2399 opcode, echo); 2400 return -EINVAL; 2401 } 2402 } 2403 2404 void qed_resc_setup(struct qed_dev *cdev) 2405 { 2406 int i; 2407 2408 if (IS_VF(cdev)) { 2409 for_each_hwfn(cdev, i) 2410 qed_l2_setup(&cdev->hwfns[i]); 2411 return; 2412 } 2413 2414 for_each_hwfn(cdev, i) { 2415 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2416 2417 qed_cxt_mngr_setup(p_hwfn); 2418 qed_spq_setup(p_hwfn); 2419 qed_eq_setup(p_hwfn); 2420 qed_consq_setup(p_hwfn); 2421 2422 /* Read shadow of current MFW mailbox */ 2423 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); 2424 memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 2425 p_hwfn->mcp_info->mfw_mb_cur, 2426 p_hwfn->mcp_info->mfw_mb_length); 2427 2428 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt); 2429 2430 qed_l2_setup(p_hwfn); 2431 qed_iov_setup(p_hwfn); 2432 qed_spq_register_async_cb(p_hwfn, PROTOCOLID_COMMON, 2433 qed_common_eqe_event); 2434 #ifdef CONFIG_QED_LL2 2435 if (p_hwfn->using_ll2) 2436 qed_ll2_setup(p_hwfn); 2437 #endif 2438 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 2439 qed_fcoe_setup(p_hwfn); 2440 2441 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 2442 qed_iscsi_setup(p_hwfn); 2443 qed_ooo_setup(p_hwfn); 2444 } 2445 2446 if (p_hwfn->hw_info.personality == QED_PCI_NVMETCP) { 2447 qed_nvmetcp_setup(p_hwfn); 2448 qed_ooo_setup(p_hwfn); 2449 } 2450 } 2451 } 2452 2453 #define FINAL_CLEANUP_POLL_CNT (100) 2454 #define FINAL_CLEANUP_POLL_TIME (10) 2455 int qed_final_cleanup(struct qed_hwfn *p_hwfn, 2456 struct qed_ptt *p_ptt, u16 id, bool is_vf) 2457 { 2458 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; 2459 int rc = -EBUSY; 2460 2461 addr = GET_GTT_REG_ADDR(GTT_BAR0_MAP_REG_USDM_RAM, 2462 USTORM_FLR_FINAL_ACK, p_hwfn->rel_pf_id); 2463 if (is_vf) 2464 id += 0x10; 2465 2466 command |= X_FINAL_CLEANUP_AGG_INT << 2467 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; 2468 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; 2469 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; 2470 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; 2471 2472 /* Make sure notification is not set before initiating final cleanup */ 2473 if (REG_RD(p_hwfn, addr)) { 2474 DP_NOTICE(p_hwfn, 2475 "Unexpected; Found final cleanup notification before initiating final cleanup\n"); 2476 REG_WR(p_hwfn, addr, 0); 2477 } 2478 2479 DP_VERBOSE(p_hwfn, QED_MSG_IOV, 2480 "Sending final cleanup for PFVF[%d] [Command %08x]\n", 2481 id, command); 2482 2483 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command); 2484 2485 /* Poll until completion */ 2486 while (!REG_RD(p_hwfn, addr) && count--) 2487 msleep(FINAL_CLEANUP_POLL_TIME); 2488 2489 if (REG_RD(p_hwfn, addr)) 2490 rc = 0; 2491 else 2492 DP_NOTICE(p_hwfn, 2493 "Failed to receive FW final cleanup notification\n"); 2494 2495 /* Cleanup afterwards */ 2496 REG_WR(p_hwfn, addr, 0); 2497 2498 return rc; 2499 } 2500 2501 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn) 2502 { 2503 int hw_mode = 0; 2504 2505 if (QED_IS_BB_B0(p_hwfn->cdev)) { 2506 hw_mode |= 1 << MODE_BB; 2507 } else if (QED_IS_AH(p_hwfn->cdev)) { 2508 hw_mode |= 1 << MODE_K2; 2509 } else { 2510 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n", 2511 p_hwfn->cdev->type); 2512 return -EINVAL; 2513 } 2514 2515 switch (p_hwfn->cdev->num_ports_in_engine) { 2516 case 1: 2517 hw_mode |= 1 << MODE_PORTS_PER_ENG_1; 2518 break; 2519 case 2: 2520 hw_mode |= 1 << MODE_PORTS_PER_ENG_2; 2521 break; 2522 case 4: 2523 hw_mode |= 1 << MODE_PORTS_PER_ENG_4; 2524 break; 2525 default: 2526 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n", 2527 p_hwfn->cdev->num_ports_in_engine); 2528 return -EINVAL; 2529 } 2530 2531 if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits)) 2532 hw_mode |= 1 << MODE_MF_SD; 2533 else 2534 hw_mode |= 1 << MODE_MF_SI; 2535 2536 hw_mode |= 1 << MODE_ASIC; 2537 2538 if (p_hwfn->cdev->num_hwfns > 1) 2539 hw_mode |= 1 << MODE_100G; 2540 2541 p_hwfn->hw_info.hw_mode = hw_mode; 2542 2543 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP), 2544 "Configuring function for hw_mode: 0x%08x\n", 2545 p_hwfn->hw_info.hw_mode); 2546 2547 return 0; 2548 } 2549 2550 /* Init run time data for all PFs on an engine. */ 2551 static void qed_init_cau_rt_data(struct qed_dev *cdev) 2552 { 2553 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; 2554 int i, igu_sb_id; 2555 2556 for_each_hwfn(cdev, i) { 2557 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2558 struct qed_igu_info *p_igu_info; 2559 struct qed_igu_block *p_block; 2560 struct cau_sb_entry sb_entry; 2561 2562 p_igu_info = p_hwfn->hw_info.p_igu_info; 2563 2564 for (igu_sb_id = 0; 2565 igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) { 2566 p_block = &p_igu_info->entry[igu_sb_id]; 2567 2568 if (!p_block->is_pf) 2569 continue; 2570 2571 qed_init_cau_sb_entry(p_hwfn, &sb_entry, 2572 p_block->function_id, 0, 0); 2573 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2, 2574 sb_entry); 2575 } 2576 } 2577 } 2578 2579 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn, 2580 struct qed_ptt *p_ptt) 2581 { 2582 u32 val, wr_mbs, cache_line_size; 2583 2584 val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0); 2585 switch (val) { 2586 case 0: 2587 wr_mbs = 128; 2588 break; 2589 case 1: 2590 wr_mbs = 256; 2591 break; 2592 case 2: 2593 wr_mbs = 512; 2594 break; 2595 default: 2596 DP_INFO(p_hwfn, 2597 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n", 2598 val); 2599 return; 2600 } 2601 2602 cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs); 2603 switch (cache_line_size) { 2604 case 32: 2605 val = 0; 2606 break; 2607 case 64: 2608 val = 1; 2609 break; 2610 case 128: 2611 val = 2; 2612 break; 2613 case 256: 2614 val = 3; 2615 break; 2616 default: 2617 DP_INFO(p_hwfn, 2618 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n", 2619 cache_line_size); 2620 } 2621 2622 if (wr_mbs < L1_CACHE_BYTES) 2623 DP_INFO(p_hwfn, 2624 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n", 2625 L1_CACHE_BYTES, wr_mbs); 2626 2627 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val); 2628 if (val > 0) { 2629 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val); 2630 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val); 2631 } 2632 } 2633 2634 static int qed_hw_init_common(struct qed_hwfn *p_hwfn, 2635 struct qed_ptt *p_ptt, int hw_mode) 2636 { 2637 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 2638 struct qed_qm_common_rt_init_params *params; 2639 struct qed_dev *cdev = p_hwfn->cdev; 2640 u8 vf_id, max_num_vfs; 2641 u16 num_pfs, pf_id; 2642 u32 concrete_fid; 2643 int rc = 0; 2644 2645 params = kzalloc(sizeof(*params), GFP_KERNEL); 2646 if (!params) { 2647 DP_NOTICE(p_hwfn->cdev, 2648 "Failed to allocate common init params\n"); 2649 2650 return -ENOMEM; 2651 } 2652 2653 qed_init_cau_rt_data(cdev); 2654 2655 /* Program GTT windows */ 2656 qed_gtt_init(p_hwfn); 2657 2658 if (p_hwfn->mcp_info) { 2659 if (p_hwfn->mcp_info->func_info.bandwidth_max) 2660 qm_info->pf_rl_en = true; 2661 if (p_hwfn->mcp_info->func_info.bandwidth_min) 2662 qm_info->pf_wfq_en = true; 2663 } 2664 2665 params->max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine; 2666 params->max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; 2667 params->pf_rl_en = qm_info->pf_rl_en; 2668 params->pf_wfq_en = qm_info->pf_wfq_en; 2669 params->global_rl_en = qm_info->vport_rl_en; 2670 params->vport_wfq_en = qm_info->vport_wfq_en; 2671 params->port_params = qm_info->qm_port_params; 2672 2673 qed_qm_common_rt_init(p_hwfn, params); 2674 2675 qed_cxt_hw_init_common(p_hwfn); 2676 2677 qed_init_cache_line_size(p_hwfn, p_ptt); 2678 2679 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode); 2680 if (rc) 2681 goto out; 2682 2683 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); 2684 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); 2685 2686 if (QED_IS_BB(p_hwfn->cdev)) { 2687 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev); 2688 for (pf_id = 0; pf_id < num_pfs; pf_id++) { 2689 qed_fid_pretend(p_hwfn, p_ptt, pf_id); 2690 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 2691 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 2692 } 2693 /* pretend to original PF */ 2694 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 2695 } 2696 2697 max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB; 2698 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) { 2699 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id); 2700 qed_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid); 2701 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1); 2702 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0); 2703 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1); 2704 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0); 2705 } 2706 /* pretend to original PF */ 2707 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 2708 2709 out: 2710 kfree(params); 2711 2712 return rc; 2713 } 2714 2715 static int 2716 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn, 2717 struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus) 2718 { 2719 u32 dpi_bit_shift, dpi_count, dpi_page_size; 2720 u32 min_dpis; 2721 u32 n_wids; 2722 2723 /* Calculate DPI size */ 2724 n_wids = max_t(u32, QED_MIN_WIDS, n_cpus); 2725 dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids); 2726 dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1); 2727 dpi_bit_shift = ilog2(dpi_page_size / 4096); 2728 dpi_count = pwm_region_size / dpi_page_size; 2729 2730 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis; 2731 min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis); 2732 2733 p_hwfn->dpi_size = dpi_page_size; 2734 p_hwfn->dpi_count = dpi_count; 2735 2736 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift); 2737 2738 if (dpi_count < min_dpis) 2739 return -EINVAL; 2740 2741 return 0; 2742 } 2743 2744 enum QED_ROCE_EDPM_MODE { 2745 QED_ROCE_EDPM_MODE_ENABLE = 0, 2746 QED_ROCE_EDPM_MODE_FORCE_ON = 1, 2747 QED_ROCE_EDPM_MODE_DISABLE = 2, 2748 }; 2749 2750 bool qed_edpm_enabled(struct qed_hwfn *p_hwfn) 2751 { 2752 if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm) 2753 return false; 2754 2755 return true; 2756 } 2757 2758 static int 2759 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2760 { 2761 u32 pwm_regsize, norm_regsize; 2762 u32 non_pwm_conn, min_addr_reg1; 2763 u32 db_bar_size, n_cpus = 1; 2764 u32 roce_edpm_mode; 2765 u32 pf_dems_shift; 2766 int rc = 0; 2767 u8 cond; 2768 2769 db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1); 2770 if (p_hwfn->cdev->num_hwfns > 1) 2771 db_bar_size /= 2; 2772 2773 /* Calculate doorbell regions */ 2774 non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) + 2775 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE, 2776 NULL) + 2777 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, 2778 NULL); 2779 norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE); 2780 min_addr_reg1 = norm_regsize / 4096; 2781 pwm_regsize = db_bar_size - norm_regsize; 2782 2783 /* Check that the normal and PWM sizes are valid */ 2784 if (db_bar_size < norm_regsize) { 2785 DP_ERR(p_hwfn->cdev, 2786 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n", 2787 db_bar_size, norm_regsize); 2788 return -EINVAL; 2789 } 2790 2791 if (pwm_regsize < QED_MIN_PWM_REGION) { 2792 DP_ERR(p_hwfn->cdev, 2793 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n", 2794 pwm_regsize, 2795 QED_MIN_PWM_REGION, db_bar_size, norm_regsize); 2796 return -EINVAL; 2797 } 2798 2799 /* Calculate number of DPIs */ 2800 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode; 2801 if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) || 2802 ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) { 2803 /* Either EDPM is mandatory, or we are attempting to allocate a 2804 * WID per CPU. 2805 */ 2806 n_cpus = num_present_cpus(); 2807 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 2808 } 2809 2810 cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) || 2811 (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE); 2812 if (cond || p_hwfn->dcbx_no_edpm) { 2813 /* Either EDPM is disabled from user configuration, or it is 2814 * disabled via DCBx, or it is not mandatory and we failed to 2815 * allocated a WID per CPU. 2816 */ 2817 n_cpus = 1; 2818 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 2819 2820 if (cond) 2821 qed_rdma_dpm_bar(p_hwfn, p_ptt); 2822 } 2823 2824 p_hwfn->wid_count = (u16)n_cpus; 2825 2826 DP_INFO(p_hwfn, 2827 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s, page_size=%lu\n", 2828 norm_regsize, 2829 pwm_regsize, 2830 p_hwfn->dpi_size, 2831 p_hwfn->dpi_count, 2832 (!qed_edpm_enabled(p_hwfn)) ? 2833 "disabled" : "enabled", PAGE_SIZE); 2834 2835 if (rc) { 2836 DP_ERR(p_hwfn, 2837 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n", 2838 p_hwfn->dpi_count, 2839 p_hwfn->pf_params.rdma_pf_params.min_dpis); 2840 return -EINVAL; 2841 } 2842 2843 p_hwfn->dpi_start_offset = norm_regsize; 2844 2845 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */ 2846 pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4); 2847 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift); 2848 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1); 2849 2850 return 0; 2851 } 2852 2853 static int qed_hw_init_port(struct qed_hwfn *p_hwfn, 2854 struct qed_ptt *p_ptt, int hw_mode) 2855 { 2856 int rc = 0; 2857 2858 /* In CMT the gate should be cleared by the 2nd hwfn */ 2859 if (!QED_IS_CMT(p_hwfn->cdev) || !IS_LEAD_HWFN(p_hwfn)) 2860 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0); 2861 2862 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode); 2863 if (rc) 2864 return rc; 2865 2866 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0); 2867 2868 return 0; 2869 } 2870 2871 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, 2872 struct qed_ptt *p_ptt, 2873 struct qed_tunnel_info *p_tunn, 2874 int hw_mode, 2875 bool b_hw_start, 2876 enum qed_int_mode int_mode, 2877 bool allow_npar_tx_switch) 2878 { 2879 u8 rel_pf_id = p_hwfn->rel_pf_id; 2880 int rc = 0; 2881 2882 if (p_hwfn->mcp_info) { 2883 struct qed_mcp_function_info *p_info; 2884 2885 p_info = &p_hwfn->mcp_info->func_info; 2886 if (p_info->bandwidth_min) 2887 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; 2888 2889 /* Update rate limit once we'll actually have a link */ 2890 p_hwfn->qm_info.pf_rl = 100000; 2891 } 2892 2893 qed_cxt_hw_init_pf(p_hwfn, p_ptt); 2894 2895 qed_int_igu_init_rt(p_hwfn); 2896 2897 /* Set VLAN in NIG if needed */ 2898 if (hw_mode & BIT(MODE_MF_SD)) { 2899 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n"); 2900 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); 2901 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, 2902 p_hwfn->hw_info.ovlan); 2903 2904 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 2905 "Configuring LLH_FUNC_FILTER_HDR_SEL\n"); 2906 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET, 2907 1); 2908 } 2909 2910 /* Enable classification by MAC if needed */ 2911 if (hw_mode & BIT(MODE_MF_SI)) { 2912 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 2913 "Configuring TAGMAC_CLS_TYPE\n"); 2914 STORE_RT_REG(p_hwfn, 2915 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1); 2916 } 2917 2918 /* Protocol Configuration */ 2919 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 2920 ((p_hwfn->hw_info.personality == QED_PCI_ISCSI) || 2921 (p_hwfn->hw_info.personality == QED_PCI_NVMETCP)) ? 1 : 0); 2922 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 2923 (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0); 2924 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); 2925 2926 /* Sanity check before the PF init sequence that uses DMAE */ 2927 rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase"); 2928 if (rc) 2929 return rc; 2930 2931 /* PF Init sequence */ 2932 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); 2933 if (rc) 2934 return rc; 2935 2936 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ 2937 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); 2938 if (rc) 2939 return rc; 2940 2941 qed_fw_overlay_init_ram(p_hwfn, p_ptt, p_hwfn->fw_overlay_mem); 2942 2943 /* Pure runtime initializations - directly to the HW */ 2944 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); 2945 2946 rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt); 2947 if (rc) 2948 return rc; 2949 2950 /* Use the leading hwfn since in CMT only NIG #0 is operational */ 2951 if (IS_LEAD_HWFN(p_hwfn)) { 2952 rc = qed_llh_hw_init_pf(p_hwfn, p_ptt); 2953 if (rc) 2954 return rc; 2955 } 2956 2957 if (b_hw_start) { 2958 /* enable interrupts */ 2959 qed_int_igu_enable(p_hwfn, p_ptt, int_mode); 2960 2961 /* send function start command */ 2962 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn, 2963 allow_npar_tx_switch); 2964 if (rc) { 2965 DP_NOTICE(p_hwfn, "Function start ramrod failed\n"); 2966 return rc; 2967 } 2968 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) { 2969 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2)); 2970 qed_wr(p_hwfn, p_ptt, 2971 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST, 2972 0x100); 2973 } 2974 } 2975 return rc; 2976 } 2977 2978 int qed_pglueb_set_pfid_enable(struct qed_hwfn *p_hwfn, 2979 struct qed_ptt *p_ptt, bool b_enable) 2980 { 2981 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0; 2982 2983 /* Configure the PF's internal FID_enable for master transactions */ 2984 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); 2985 2986 /* Wait until value is set - try for 1 second every 50us */ 2987 for (delay_idx = 0; delay_idx < 20000; delay_idx++) { 2988 val = qed_rd(p_hwfn, p_ptt, 2989 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 2990 if (val == set_val) 2991 break; 2992 2993 usleep_range(50, 60); 2994 } 2995 2996 if (val != set_val) { 2997 DP_NOTICE(p_hwfn, 2998 "PFID_ENABLE_MASTER wasn't changed after a second\n"); 2999 return -EAGAIN; 3000 } 3001 3002 return 0; 3003 } 3004 3005 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn, 3006 struct qed_ptt *p_main_ptt) 3007 { 3008 /* Read shadow of current MFW mailbox */ 3009 qed_mcp_read_mb(p_hwfn, p_main_ptt); 3010 memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 3011 p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length); 3012 } 3013 3014 static void 3015 qed_fill_load_req_params(struct qed_load_req_params *p_load_req, 3016 struct qed_drv_load_params *p_drv_load) 3017 { 3018 memset(p_load_req, 0, sizeof(*p_load_req)); 3019 3020 p_load_req->drv_role = p_drv_load->is_crash_kernel ? 3021 QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS; 3022 p_load_req->timeout_val = p_drv_load->mfw_timeout_val; 3023 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset; 3024 p_load_req->override_force_load = p_drv_load->override_force_load; 3025 } 3026 3027 static int qed_vf_start(struct qed_hwfn *p_hwfn, 3028 struct qed_hw_init_params *p_params) 3029 { 3030 if (p_params->p_tunn) { 3031 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn); 3032 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn); 3033 } 3034 3035 p_hwfn->b_int_enabled = true; 3036 3037 return 0; 3038 } 3039 3040 static void qed_pglueb_clear_err(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3041 { 3042 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 3043 BIT(p_hwfn->abs_pf_id)); 3044 } 3045 3046 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params) 3047 { 3048 struct qed_load_req_params load_req_params; 3049 u32 load_code, resp, param, drv_mb_param; 3050 bool b_default_mtu = true; 3051 struct qed_hwfn *p_hwfn; 3052 const u32 *fw_overlays; 3053 u32 fw_overlays_len; 3054 u16 ether_type; 3055 int rc = 0, i; 3056 3057 if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 3058 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 3059 return -EINVAL; 3060 } 3061 3062 if (IS_PF(cdev)) { 3063 rc = qed_init_fw_data(cdev, p_params->bin_fw_data); 3064 if (rc) 3065 return rc; 3066 } 3067 3068 for_each_hwfn(cdev, i) { 3069 p_hwfn = &cdev->hwfns[i]; 3070 3071 /* If management didn't provide a default, set one of our own */ 3072 if (!p_hwfn->hw_info.mtu) { 3073 p_hwfn->hw_info.mtu = 1500; 3074 b_default_mtu = false; 3075 } 3076 3077 if (IS_VF(cdev)) { 3078 qed_vf_start(p_hwfn, p_params); 3079 continue; 3080 } 3081 3082 /* Some flows may keep variable set */ 3083 p_hwfn->mcp_info->mcp_handling_status = 0; 3084 3085 rc = qed_calc_hw_mode(p_hwfn); 3086 if (rc) 3087 return rc; 3088 3089 if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING, 3090 &cdev->mf_bits) || 3091 test_bit(QED_MF_8021AD_TAGGING, 3092 &cdev->mf_bits))) { 3093 if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits)) 3094 ether_type = ETH_P_8021Q; 3095 else 3096 ether_type = ETH_P_8021AD; 3097 STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET, 3098 ether_type); 3099 STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET, 3100 ether_type); 3101 STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET, 3102 ether_type); 3103 STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET, 3104 ether_type); 3105 } 3106 3107 qed_fill_load_req_params(&load_req_params, 3108 p_params->p_drv_load_params); 3109 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, 3110 &load_req_params); 3111 if (rc) { 3112 DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n"); 3113 return rc; 3114 } 3115 3116 load_code = load_req_params.load_code; 3117 DP_VERBOSE(p_hwfn, QED_MSG_SP, 3118 "Load request was sent. Load code: 0x%x\n", 3119 load_code); 3120 3121 /* Only relevant for recovery: 3122 * Clear the indication after LOAD_REQ is responded by the MFW. 3123 */ 3124 cdev->recov_in_prog = false; 3125 3126 qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt); 3127 3128 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); 3129 3130 /* Clean up chip from previous driver if such remains exist. 3131 * This is not needed when the PF is the first one on the 3132 * engine, since afterwards we are going to init the FW. 3133 */ 3134 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) { 3135 rc = qed_final_cleanup(p_hwfn, p_hwfn->p_main_ptt, 3136 p_hwfn->rel_pf_id, false); 3137 if (rc) { 3138 qed_hw_err_notify(p_hwfn, p_hwfn->p_main_ptt, 3139 QED_HW_ERR_RAMROD_FAIL, 3140 "Final cleanup failed\n"); 3141 goto load_err; 3142 } 3143 } 3144 3145 /* Log and clear previous pglue_b errors if such exist */ 3146 qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt, true); 3147 3148 /* Enable the PF's internal FID_enable in the PXP */ 3149 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt, 3150 true); 3151 if (rc) 3152 goto load_err; 3153 3154 /* Clear the pglue_b was_error indication. 3155 * In E4 it must be done after the BME and the internal 3156 * FID_enable for the PF are set, since VDMs may cause the 3157 * indication to be set again. 3158 */ 3159 qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt); 3160 3161 fw_overlays = cdev->fw_data->fw_overlays; 3162 fw_overlays_len = cdev->fw_data->fw_overlays_len; 3163 p_hwfn->fw_overlay_mem = 3164 qed_fw_overlay_mem_alloc(p_hwfn, fw_overlays, 3165 fw_overlays_len); 3166 if (!p_hwfn->fw_overlay_mem) { 3167 DP_NOTICE(p_hwfn, 3168 "Failed to allocate fw overlay memory\n"); 3169 rc = -ENOMEM; 3170 goto load_err; 3171 } 3172 3173 switch (load_code) { 3174 case FW_MSG_CODE_DRV_LOAD_ENGINE: 3175 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, 3176 p_hwfn->hw_info.hw_mode); 3177 if (rc) 3178 break; 3179 fallthrough; 3180 case FW_MSG_CODE_DRV_LOAD_PORT: 3181 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, 3182 p_hwfn->hw_info.hw_mode); 3183 if (rc) 3184 break; 3185 3186 fallthrough; 3187 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 3188 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, 3189 p_params->p_tunn, 3190 p_hwfn->hw_info.hw_mode, 3191 p_params->b_hw_start, 3192 p_params->int_mode, 3193 p_params->allow_npar_tx_switch); 3194 break; 3195 default: 3196 DP_NOTICE(p_hwfn, 3197 "Unexpected load code [0x%08x]", load_code); 3198 rc = -EINVAL; 3199 break; 3200 } 3201 3202 if (rc) { 3203 DP_NOTICE(p_hwfn, 3204 "init phase failed for loadcode 0x%x (rc %d)\n", 3205 load_code, rc); 3206 goto load_err; 3207 } 3208 3209 rc = qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt); 3210 if (rc) 3211 return rc; 3212 3213 /* send DCBX attention request command */ 3214 DP_VERBOSE(p_hwfn, 3215 QED_MSG_DCB, 3216 "sending phony dcbx set command to trigger DCBx attention handling\n"); 3217 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 3218 DRV_MSG_CODE_SET_DCBX, 3219 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, 3220 &resp, ¶m); 3221 if (rc) { 3222 DP_NOTICE(p_hwfn, 3223 "Failed to send DCBX attention request\n"); 3224 return rc; 3225 } 3226 3227 p_hwfn->hw_init_done = true; 3228 } 3229 3230 if (IS_PF(cdev)) { 3231 p_hwfn = QED_LEADING_HWFN(cdev); 3232 3233 /* Get pre-negotiated values for stag, bandwidth etc. */ 3234 DP_VERBOSE(p_hwfn, 3235 QED_MSG_SPQ, 3236 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n"); 3237 drv_mb_param = 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET; 3238 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 3239 DRV_MSG_CODE_GET_OEM_UPDATES, 3240 drv_mb_param, &resp, ¶m); 3241 if (rc) 3242 DP_NOTICE(p_hwfn, 3243 "Failed to send GET_OEM_UPDATES attention request\n"); 3244 3245 drv_mb_param = STORM_FW_VERSION; 3246 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 3247 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER, 3248 drv_mb_param, &load_code, ¶m); 3249 if (rc) 3250 DP_INFO(p_hwfn, "Failed to update firmware version\n"); 3251 3252 if (!b_default_mtu) { 3253 rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt, 3254 p_hwfn->hw_info.mtu); 3255 if (rc) 3256 DP_INFO(p_hwfn, 3257 "Failed to update default mtu\n"); 3258 } 3259 3260 rc = qed_mcp_ov_update_driver_state(p_hwfn, 3261 p_hwfn->p_main_ptt, 3262 QED_OV_DRIVER_STATE_DISABLED); 3263 if (rc) 3264 DP_INFO(p_hwfn, "Failed to update driver state\n"); 3265 3266 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt, 3267 QED_OV_ESWITCH_NONE); 3268 if (rc) 3269 DP_INFO(p_hwfn, "Failed to update eswitch mode\n"); 3270 } 3271 3272 return 0; 3273 3274 load_err: 3275 /* The MFW load lock should be released also when initialization fails. 3276 */ 3277 qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt); 3278 return rc; 3279 } 3280 3281 #define QED_HW_STOP_RETRY_LIMIT (10) 3282 static void qed_hw_timers_stop(struct qed_dev *cdev, 3283 struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3284 { 3285 int i; 3286 3287 /* close timers */ 3288 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); 3289 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); 3290 3291 if (cdev->recov_in_prog) 3292 return; 3293 3294 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) { 3295 if ((!qed_rd(p_hwfn, p_ptt, 3296 TM_REG_PF_SCAN_ACTIVE_CONN)) && 3297 (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK))) 3298 break; 3299 3300 /* Dependent on number of connection/tasks, possibly 3301 * 1ms sleep is required between polls 3302 */ 3303 usleep_range(1000, 2000); 3304 } 3305 3306 if (i < QED_HW_STOP_RETRY_LIMIT) 3307 return; 3308 3309 DP_NOTICE(p_hwfn, 3310 "Timers linear scans are not over [Connection %02x Tasks %02x]\n", 3311 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN), 3312 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)); 3313 } 3314 3315 void qed_hw_timers_stop_all(struct qed_dev *cdev) 3316 { 3317 int j; 3318 3319 for_each_hwfn(cdev, j) { 3320 struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 3321 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 3322 3323 qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 3324 } 3325 } 3326 3327 int qed_hw_stop(struct qed_dev *cdev) 3328 { 3329 struct qed_hwfn *p_hwfn; 3330 struct qed_ptt *p_ptt; 3331 int rc, rc2 = 0; 3332 int j; 3333 3334 for_each_hwfn(cdev, j) { 3335 p_hwfn = &cdev->hwfns[j]; 3336 p_ptt = p_hwfn->p_main_ptt; 3337 3338 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n"); 3339 3340 if (IS_VF(cdev)) { 3341 qed_vf_pf_int_cleanup(p_hwfn); 3342 rc = qed_vf_pf_reset(p_hwfn); 3343 if (rc) { 3344 DP_NOTICE(p_hwfn, 3345 "qed_vf_pf_reset failed. rc = %d.\n", 3346 rc); 3347 rc2 = -EINVAL; 3348 } 3349 continue; 3350 } 3351 3352 /* mark the hw as uninitialized... */ 3353 p_hwfn->hw_init_done = false; 3354 3355 /* Send unload command to MCP */ 3356 if (!cdev->recov_in_prog) { 3357 rc = qed_mcp_unload_req(p_hwfn, p_ptt); 3358 if (rc) { 3359 DP_NOTICE(p_hwfn, 3360 "Failed sending a UNLOAD_REQ command. rc = %d.\n", 3361 rc); 3362 rc2 = -EINVAL; 3363 } 3364 } 3365 3366 qed_slowpath_irq_sync(p_hwfn); 3367 3368 /* After this point no MFW attentions are expected, e.g. prevent 3369 * race between pf stop and dcbx pf update. 3370 */ 3371 rc = qed_sp_pf_stop(p_hwfn); 3372 if (rc) { 3373 DP_NOTICE(p_hwfn, 3374 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n", 3375 rc); 3376 rc2 = -EINVAL; 3377 } 3378 3379 qed_wr(p_hwfn, p_ptt, 3380 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 3381 3382 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 3383 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 3384 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 3385 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 3386 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 3387 3388 qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 3389 3390 /* Disable Attention Generation */ 3391 qed_int_igu_disable_int(p_hwfn, p_ptt); 3392 3393 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); 3394 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); 3395 3396 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); 3397 3398 /* Need to wait 1ms to guarantee SBs are cleared */ 3399 usleep_range(1000, 2000); 3400 3401 /* Disable PF in HW blocks */ 3402 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0); 3403 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0); 3404 3405 if (IS_LEAD_HWFN(p_hwfn) && 3406 test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits) && 3407 !QED_IS_FCOE_PERSONALITY(p_hwfn)) 3408 qed_llh_remove_mac_filter(cdev, 0, 3409 p_hwfn->hw_info.hw_mac_addr); 3410 3411 if (!cdev->recov_in_prog) { 3412 rc = qed_mcp_unload_done(p_hwfn, p_ptt); 3413 if (rc) { 3414 DP_NOTICE(p_hwfn, 3415 "Failed sending a UNLOAD_DONE command. rc = %d.\n", 3416 rc); 3417 rc2 = -EINVAL; 3418 } 3419 } 3420 } 3421 3422 if (IS_PF(cdev) && !cdev->recov_in_prog) { 3423 p_hwfn = QED_LEADING_HWFN(cdev); 3424 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt; 3425 3426 /* Clear the PF's internal FID_enable in the PXP. 3427 * In CMT this should only be done for first hw-function, and 3428 * only after all transactions have stopped for all active 3429 * hw-functions. 3430 */ 3431 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_ptt, false); 3432 if (rc) { 3433 DP_NOTICE(p_hwfn, 3434 "qed_pglueb_set_pfid_enable() failed. rc = %d.\n", 3435 rc); 3436 rc2 = -EINVAL; 3437 } 3438 } 3439 3440 return rc2; 3441 } 3442 3443 int qed_hw_stop_fastpath(struct qed_dev *cdev) 3444 { 3445 int j; 3446 3447 for_each_hwfn(cdev, j) { 3448 struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 3449 struct qed_ptt *p_ptt; 3450 3451 if (IS_VF(cdev)) { 3452 qed_vf_pf_int_cleanup(p_hwfn); 3453 continue; 3454 } 3455 p_ptt = qed_ptt_acquire(p_hwfn); 3456 if (!p_ptt) 3457 return -EAGAIN; 3458 3459 DP_VERBOSE(p_hwfn, 3460 NETIF_MSG_IFDOWN, "Shutting down the fastpath\n"); 3461 3462 qed_wr(p_hwfn, p_ptt, 3463 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 3464 3465 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 3466 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 3467 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 3468 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 3469 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 3470 3471 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); 3472 3473 /* Need to wait 1ms to guarantee SBs are cleared */ 3474 usleep_range(1000, 2000); 3475 qed_ptt_release(p_hwfn, p_ptt); 3476 } 3477 3478 return 0; 3479 } 3480 3481 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn) 3482 { 3483 struct qed_ptt *p_ptt; 3484 3485 if (IS_VF(p_hwfn->cdev)) 3486 return 0; 3487 3488 p_ptt = qed_ptt_acquire(p_hwfn); 3489 if (!p_ptt) 3490 return -EAGAIN; 3491 3492 if (p_hwfn->p_rdma_info && 3493 p_hwfn->p_rdma_info->active && p_hwfn->b_rdma_enabled_in_prs) 3494 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1); 3495 3496 /* Re-open incoming traffic */ 3497 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); 3498 qed_ptt_release(p_hwfn, p_ptt); 3499 3500 return 0; 3501 } 3502 3503 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ 3504 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn) 3505 { 3506 qed_ptt_pool_free(p_hwfn); 3507 kfree(p_hwfn->hw_info.p_igu_info); 3508 p_hwfn->hw_info.p_igu_info = NULL; 3509 } 3510 3511 /* Setup bar access */ 3512 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn) 3513 { 3514 /* clear indirect access */ 3515 if (QED_IS_AH(p_hwfn->cdev)) { 3516 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 3517 PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0); 3518 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 3519 PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0); 3520 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 3521 PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0); 3522 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 3523 PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0); 3524 } else { 3525 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 3526 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0); 3527 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 3528 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0); 3529 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 3530 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0); 3531 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 3532 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0); 3533 } 3534 3535 /* Clean previous pglue_b errors if such exist */ 3536 qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt); 3537 3538 /* enable internal target-read */ 3539 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 3540 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 3541 } 3542 3543 static void get_function_id(struct qed_hwfn *p_hwfn) 3544 { 3545 /* ME Register */ 3546 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, 3547 PXP_PF_ME_OPAQUE_ADDR); 3548 3549 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); 3550 3551 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; 3552 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 3553 PXP_CONCRETE_FID_PFID); 3554 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 3555 PXP_CONCRETE_FID_PORT); 3556 3557 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 3558 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n", 3559 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid); 3560 } 3561 3562 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn) 3563 { 3564 u32 *feat_num = p_hwfn->hw_info.feat_num; 3565 struct qed_sb_cnt_info sb_cnt; 3566 u32 non_l2_sbs = 0; 3567 3568 memset(&sb_cnt, 0, sizeof(sb_cnt)); 3569 qed_int_get_num_sbs(p_hwfn, &sb_cnt); 3570 3571 if (IS_ENABLED(CONFIG_QED_RDMA) && 3572 QED_IS_RDMA_PERSONALITY(p_hwfn)) { 3573 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide 3574 * the status blocks equally between L2 / RoCE but with 3575 * consideration as to how many l2 queues / cnqs we have. 3576 */ 3577 feat_num[QED_RDMA_CNQ] = 3578 min_t(u32, sb_cnt.cnt / 2, 3579 RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM)); 3580 3581 non_l2_sbs = feat_num[QED_RDMA_CNQ]; 3582 } 3583 if (QED_IS_L2_PERSONALITY(p_hwfn)) { 3584 /* Start by allocating VF queues, then PF's */ 3585 feat_num[QED_VF_L2_QUE] = min_t(u32, 3586 RESC_NUM(p_hwfn, QED_L2_QUEUE), 3587 sb_cnt.iov_cnt); 3588 feat_num[QED_PF_L2_QUE] = min_t(u32, 3589 sb_cnt.cnt - non_l2_sbs, 3590 RESC_NUM(p_hwfn, 3591 QED_L2_QUEUE) - 3592 FEAT_NUM(p_hwfn, 3593 QED_VF_L2_QUE)); 3594 } 3595 3596 if (QED_IS_FCOE_PERSONALITY(p_hwfn)) 3597 feat_num[QED_FCOE_CQ] = min_t(u32, sb_cnt.cnt, 3598 RESC_NUM(p_hwfn, 3599 QED_CMDQS_CQS)); 3600 3601 if (QED_IS_ISCSI_PERSONALITY(p_hwfn)) 3602 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt, 3603 RESC_NUM(p_hwfn, 3604 QED_CMDQS_CQS)); 3605 3606 if (QED_IS_NVMETCP_PERSONALITY(p_hwfn)) 3607 feat_num[QED_NVMETCP_CQ] = min_t(u32, sb_cnt.cnt, 3608 RESC_NUM(p_hwfn, 3609 QED_CMDQS_CQS)); 3610 3611 DP_VERBOSE(p_hwfn, 3612 NETIF_MSG_PROBE, 3613 "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d NVMETCP_CQ=%d #SBS=%d\n", 3614 (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE), 3615 (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE), 3616 (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ), 3617 (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ), 3618 (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ), 3619 (int)FEAT_NUM(p_hwfn, QED_NVMETCP_CQ), 3620 (int)sb_cnt.cnt); 3621 } 3622 3623 const char *qed_hw_get_resc_name(enum qed_resources res_id) 3624 { 3625 switch (res_id) { 3626 case QED_L2_QUEUE: 3627 return "L2_QUEUE"; 3628 case QED_VPORT: 3629 return "VPORT"; 3630 case QED_RSS_ENG: 3631 return "RSS_ENG"; 3632 case QED_PQ: 3633 return "PQ"; 3634 case QED_RL: 3635 return "RL"; 3636 case QED_MAC: 3637 return "MAC"; 3638 case QED_VLAN: 3639 return "VLAN"; 3640 case QED_RDMA_CNQ_RAM: 3641 return "RDMA_CNQ_RAM"; 3642 case QED_ILT: 3643 return "ILT"; 3644 case QED_LL2_RAM_QUEUE: 3645 return "LL2_RAM_QUEUE"; 3646 case QED_LL2_CTX_QUEUE: 3647 return "LL2_CTX_QUEUE"; 3648 case QED_CMDQS_CQS: 3649 return "CMDQS_CQS"; 3650 case QED_RDMA_STATS_QUEUE: 3651 return "RDMA_STATS_QUEUE"; 3652 case QED_BDQ: 3653 return "BDQ"; 3654 case QED_SB: 3655 return "SB"; 3656 default: 3657 return "UNKNOWN_RESOURCE"; 3658 } 3659 } 3660 3661 static int 3662 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, 3663 struct qed_ptt *p_ptt, 3664 enum qed_resources res_id, 3665 u32 resc_max_val, u32 *p_mcp_resp) 3666 { 3667 int rc; 3668 3669 rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id, 3670 resc_max_val, p_mcp_resp); 3671 if (rc) { 3672 DP_NOTICE(p_hwfn, 3673 "MFW response failure for a max value setting of resource %d [%s]\n", 3674 res_id, qed_hw_get_resc_name(res_id)); 3675 return rc; 3676 } 3677 3678 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) 3679 DP_INFO(p_hwfn, 3680 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n", 3681 res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp); 3682 3683 return 0; 3684 } 3685 3686 static u32 qed_hsi_def_val[][MAX_CHIP_IDS] = { 3687 {MAX_NUM_VFS_BB, MAX_NUM_VFS_K2}, 3688 {MAX_NUM_L2_QUEUES_BB, MAX_NUM_L2_QUEUES_K2}, 3689 {MAX_NUM_PORTS_BB, MAX_NUM_PORTS_K2}, 3690 {MAX_SB_PER_PATH_BB, MAX_SB_PER_PATH_K2,}, 3691 {MAX_NUM_PFS_BB, MAX_NUM_PFS_K2}, 3692 {MAX_NUM_VPORTS_BB, MAX_NUM_VPORTS_K2}, 3693 {ETH_RSS_ENGINE_NUM_BB, ETH_RSS_ENGINE_NUM_K2}, 3694 {MAX_QM_TX_QUEUES_BB, MAX_QM_TX_QUEUES_K2}, 3695 {PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2}, 3696 {RDMA_NUM_STATISTIC_COUNTERS_BB, RDMA_NUM_STATISTIC_COUNTERS_K2}, 3697 {MAX_QM_GLOBAL_RLS, MAX_QM_GLOBAL_RLS}, 3698 {PBF_MAX_CMD_LINES, PBF_MAX_CMD_LINES}, 3699 {BTB_MAX_BLOCKS_BB, BTB_MAX_BLOCKS_K2}, 3700 }; 3701 3702 u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type) 3703 { 3704 enum chip_ids chip_id = QED_IS_BB(cdev) ? CHIP_BB : CHIP_K2; 3705 3706 if (type >= QED_NUM_HSI_DEFS) { 3707 DP_ERR(cdev, "Unexpected HSI definition type [%d]\n", type); 3708 return 0; 3709 } 3710 3711 return qed_hsi_def_val[type][chip_id]; 3712 } 3713 3714 static int 3715 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3716 { 3717 u32 resc_max_val, mcp_resp; 3718 u8 res_id; 3719 int rc; 3720 3721 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) { 3722 switch (res_id) { 3723 case QED_LL2_RAM_QUEUE: 3724 resc_max_val = MAX_NUM_LL2_RX_RAM_QUEUES; 3725 break; 3726 case QED_LL2_CTX_QUEUE: 3727 resc_max_val = MAX_NUM_LL2_RX_CTX_QUEUES; 3728 break; 3729 case QED_RDMA_CNQ_RAM: 3730 /* No need for a case for QED_CMDQS_CQS since 3731 * CNQ/CMDQS are the same resource. 3732 */ 3733 resc_max_val = NUM_OF_GLOBAL_QUEUES; 3734 break; 3735 case QED_RDMA_STATS_QUEUE: 3736 resc_max_val = 3737 NUM_OF_RDMA_STATISTIC_COUNTERS(p_hwfn->cdev); 3738 break; 3739 case QED_BDQ: 3740 resc_max_val = BDQ_NUM_RESOURCES; 3741 break; 3742 default: 3743 continue; 3744 } 3745 3746 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id, 3747 resc_max_val, &mcp_resp); 3748 if (rc) 3749 return rc; 3750 3751 /* There's no point to continue to the next resource if the 3752 * command is not supported by the MFW. 3753 * We do continue if the command is supported but the resource 3754 * is unknown to the MFW. Such a resource will be later 3755 * configured with the default allocation values. 3756 */ 3757 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED) 3758 return -EINVAL; 3759 } 3760 3761 return 0; 3762 } 3763 3764 static 3765 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn, 3766 enum qed_resources res_id, 3767 u32 *p_resc_num, u32 *p_resc_start) 3768 { 3769 u8 num_funcs = p_hwfn->num_funcs_on_engine; 3770 struct qed_dev *cdev = p_hwfn->cdev; 3771 3772 switch (res_id) { 3773 case QED_L2_QUEUE: 3774 *p_resc_num = NUM_OF_L2_QUEUES(cdev) / num_funcs; 3775 break; 3776 case QED_VPORT: 3777 *p_resc_num = NUM_OF_VPORTS(cdev) / num_funcs; 3778 break; 3779 case QED_RSS_ENG: 3780 *p_resc_num = NUM_OF_RSS_ENGINES(cdev) / num_funcs; 3781 break; 3782 case QED_PQ: 3783 *p_resc_num = NUM_OF_QM_TX_QUEUES(cdev) / num_funcs; 3784 *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */ 3785 break; 3786 case QED_RL: 3787 *p_resc_num = NUM_OF_QM_GLOBAL_RLS(cdev) / num_funcs; 3788 break; 3789 case QED_MAC: 3790 case QED_VLAN: 3791 /* Each VFC resource can accommodate both a MAC and a VLAN */ 3792 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs; 3793 break; 3794 case QED_ILT: 3795 *p_resc_num = NUM_OF_PXP_ILT_RECORDS(cdev) / num_funcs; 3796 break; 3797 case QED_LL2_RAM_QUEUE: 3798 *p_resc_num = MAX_NUM_LL2_RX_RAM_QUEUES / num_funcs; 3799 break; 3800 case QED_LL2_CTX_QUEUE: 3801 *p_resc_num = MAX_NUM_LL2_RX_CTX_QUEUES / num_funcs; 3802 break; 3803 case QED_RDMA_CNQ_RAM: 3804 case QED_CMDQS_CQS: 3805 /* CNQ/CMDQS are the same resource */ 3806 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs; 3807 break; 3808 case QED_RDMA_STATS_QUEUE: 3809 *p_resc_num = NUM_OF_RDMA_STATISTIC_COUNTERS(cdev) / num_funcs; 3810 break; 3811 case QED_BDQ: 3812 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI && 3813 p_hwfn->hw_info.personality != QED_PCI_FCOE && 3814 p_hwfn->hw_info.personality != QED_PCI_NVMETCP) 3815 *p_resc_num = 0; 3816 else 3817 *p_resc_num = 1; 3818 break; 3819 case QED_SB: 3820 /* Since we want its value to reflect whether MFW supports 3821 * the new scheme, have a default of 0. 3822 */ 3823 *p_resc_num = 0; 3824 break; 3825 default: 3826 return -EINVAL; 3827 } 3828 3829 switch (res_id) { 3830 case QED_BDQ: 3831 if (!*p_resc_num) 3832 *p_resc_start = 0; 3833 else if (p_hwfn->cdev->num_ports_in_engine == 4) 3834 *p_resc_start = p_hwfn->port_id; 3835 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI || 3836 p_hwfn->hw_info.personality == QED_PCI_NVMETCP) 3837 *p_resc_start = p_hwfn->port_id; 3838 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 3839 *p_resc_start = p_hwfn->port_id + 2; 3840 break; 3841 default: 3842 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx; 3843 break; 3844 } 3845 3846 return 0; 3847 } 3848 3849 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn, 3850 enum qed_resources res_id) 3851 { 3852 u32 dflt_resc_num = 0, dflt_resc_start = 0; 3853 u32 mcp_resp, *p_resc_num, *p_resc_start; 3854 int rc; 3855 3856 p_resc_num = &RESC_NUM(p_hwfn, res_id); 3857 p_resc_start = &RESC_START(p_hwfn, res_id); 3858 3859 rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num, 3860 &dflt_resc_start); 3861 if (rc) { 3862 DP_ERR(p_hwfn, 3863 "Failed to get default amount for resource %d [%s]\n", 3864 res_id, qed_hw_get_resc_name(res_id)); 3865 return rc; 3866 } 3867 3868 rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id, 3869 &mcp_resp, p_resc_num, p_resc_start); 3870 if (rc) { 3871 DP_NOTICE(p_hwfn, 3872 "MFW response failure for an allocation request for resource %d [%s]\n", 3873 res_id, qed_hw_get_resc_name(res_id)); 3874 return rc; 3875 } 3876 3877 /* Default driver values are applied in the following cases: 3878 * - The resource allocation MB command is not supported by the MFW 3879 * - There is an internal error in the MFW while processing the request 3880 * - The resource ID is unknown to the MFW 3881 */ 3882 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) { 3883 DP_INFO(p_hwfn, 3884 "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n", 3885 res_id, 3886 qed_hw_get_resc_name(res_id), 3887 mcp_resp, dflt_resc_num, dflt_resc_start); 3888 *p_resc_num = dflt_resc_num; 3889 *p_resc_start = dflt_resc_start; 3890 goto out; 3891 } 3892 3893 out: 3894 /* PQs have to divide by 8 [that's the HW granularity]. 3895 * Reduce number so it would fit. 3896 */ 3897 if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) { 3898 DP_INFO(p_hwfn, 3899 "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n", 3900 *p_resc_num, 3901 (*p_resc_num) & ~0x7, 3902 *p_resc_start, (*p_resc_start) & ~0x7); 3903 *p_resc_num &= ~0x7; 3904 *p_resc_start &= ~0x7; 3905 } 3906 3907 return 0; 3908 } 3909 3910 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn) 3911 { 3912 int rc; 3913 u8 res_id; 3914 3915 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) { 3916 rc = __qed_hw_set_resc_info(p_hwfn, res_id); 3917 if (rc) 3918 return rc; 3919 } 3920 3921 return 0; 3922 } 3923 3924 static int qed_hw_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, 3925 struct qed_ptt *p_ptt) 3926 { 3927 struct qed_dev *cdev = p_hwfn->cdev; 3928 u8 native_ppfid_idx; 3929 int rc; 3930 3931 /* Calculation of BB/AH is different for native_ppfid_idx */ 3932 if (QED_IS_BB(cdev)) 3933 native_ppfid_idx = p_hwfn->rel_pf_id; 3934 else 3935 native_ppfid_idx = p_hwfn->rel_pf_id / 3936 cdev->num_ports_in_engine; 3937 3938 rc = qed_mcp_get_ppfid_bitmap(p_hwfn, p_ptt); 3939 if (rc != 0 && rc != -EOPNOTSUPP) 3940 return rc; 3941 else if (rc == -EOPNOTSUPP) 3942 cdev->ppfid_bitmap = 0x1 << native_ppfid_idx; 3943 3944 if (!(cdev->ppfid_bitmap & (0x1 << native_ppfid_idx))) { 3945 DP_INFO(p_hwfn, 3946 "Fix the PPFID bitmap to include the native PPFID [native_ppfid_idx %hhd, orig_bitmap 0x%hhx]\n", 3947 native_ppfid_idx, cdev->ppfid_bitmap); 3948 cdev->ppfid_bitmap = 0x1 << native_ppfid_idx; 3949 } 3950 3951 return 0; 3952 } 3953 3954 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3955 { 3956 struct qed_resc_unlock_params resc_unlock_params; 3957 struct qed_resc_lock_params resc_lock_params; 3958 bool b_ah = QED_IS_AH(p_hwfn->cdev); 3959 u8 res_id; 3960 int rc; 3961 3962 /* Setting the max values of the soft resources and the following 3963 * resources allocation queries should be atomic. Since several PFs can 3964 * run in parallel - a resource lock is needed. 3965 * If either the resource lock or resource set value commands are not 3966 * supported - skip the max values setting, release the lock if 3967 * needed, and proceed to the queries. Other failures, including a 3968 * failure to acquire the lock, will cause this function to fail. 3969 */ 3970 qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params, 3971 QED_RESC_LOCK_RESC_ALLOC, false); 3972 3973 rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params); 3974 if (rc && rc != -EINVAL) { 3975 return rc; 3976 } else if (rc == -EINVAL) { 3977 DP_INFO(p_hwfn, 3978 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n"); 3979 } else if (!resc_lock_params.b_granted) { 3980 DP_NOTICE(p_hwfn, 3981 "Failed to acquire the resource lock for the resource allocation commands\n"); 3982 return -EBUSY; 3983 } else { 3984 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt); 3985 if (rc && rc != -EINVAL) { 3986 DP_NOTICE(p_hwfn, 3987 "Failed to set the max values of the soft resources\n"); 3988 goto unlock_and_exit; 3989 } else if (rc == -EINVAL) { 3990 DP_INFO(p_hwfn, 3991 "Skip the max values setting of the soft resources since it is not supported by the MFW\n"); 3992 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, 3993 &resc_unlock_params); 3994 if (rc) 3995 DP_INFO(p_hwfn, 3996 "Failed to release the resource lock for the resource allocation commands\n"); 3997 } 3998 } 3999 4000 rc = qed_hw_set_resc_info(p_hwfn); 4001 if (rc) 4002 goto unlock_and_exit; 4003 4004 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) { 4005 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params); 4006 if (rc) 4007 DP_INFO(p_hwfn, 4008 "Failed to release the resource lock for the resource allocation commands\n"); 4009 } 4010 4011 /* PPFID bitmap */ 4012 if (IS_LEAD_HWFN(p_hwfn)) { 4013 rc = qed_hw_get_ppfid_bitmap(p_hwfn, p_ptt); 4014 if (rc) 4015 return rc; 4016 } 4017 4018 /* Sanity for ILT */ 4019 if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) || 4020 (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) { 4021 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n", 4022 RESC_START(p_hwfn, QED_ILT), 4023 RESC_END(p_hwfn, QED_ILT) - 1); 4024 return -EINVAL; 4025 } 4026 4027 /* This will also learn the number of SBs from MFW */ 4028 if (qed_int_igu_reset_cam(p_hwfn, p_ptt)) 4029 return -EINVAL; 4030 4031 qed_hw_set_feat(p_hwfn); 4032 4033 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) 4034 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n", 4035 qed_hw_get_resc_name(res_id), 4036 RESC_NUM(p_hwfn, res_id), 4037 RESC_START(p_hwfn, res_id)); 4038 4039 return 0; 4040 4041 unlock_and_exit: 4042 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) 4043 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params); 4044 return rc; 4045 } 4046 4047 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 4048 { 4049 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities, fld; 4050 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg; 4051 struct qed_mcp_link_speed_params *ext_speed; 4052 struct qed_mcp_link_capabilities *p_caps; 4053 struct qed_mcp_link_params *link; 4054 int i; 4055 4056 /* Read global nvm_cfg address */ 4057 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 4058 4059 /* Verify MCP has initialized it */ 4060 if (!nvm_cfg_addr) { 4061 DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 4062 return -EINVAL; 4063 } 4064 4065 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ 4066 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 4067 4068 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 4069 offsetof(struct nvm_cfg1, glob) + 4070 offsetof(struct nvm_cfg1_glob, core_cfg); 4071 4072 core_cfg = qed_rd(p_hwfn, p_ptt, addr); 4073 4074 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> 4075 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { 4076 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G: 4077 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G: 4078 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G: 4079 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F: 4080 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E: 4081 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G: 4082 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G: 4083 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G: 4084 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G: 4085 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G: 4086 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G: 4087 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X50G_R1: 4088 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_4X50G_R1: 4089 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R2: 4090 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X100G_R2: 4091 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R4: 4092 break; 4093 default: 4094 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg); 4095 break; 4096 } 4097 4098 /* Read default link configuration */ 4099 link = &p_hwfn->mcp_info->link_input; 4100 p_caps = &p_hwfn->mcp_info->link_capabilities; 4101 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 4102 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 4103 link_temp = qed_rd(p_hwfn, p_ptt, 4104 port_cfg_addr + 4105 offsetof(struct nvm_cfg1_port, speed_cap_mask)); 4106 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; 4107 link->speed.advertised_speeds = link_temp; 4108 4109 p_caps->speed_capabilities = link->speed.advertised_speeds; 4110 4111 link_temp = qed_rd(p_hwfn, p_ptt, 4112 port_cfg_addr + 4113 offsetof(struct nvm_cfg1_port, link_settings)); 4114 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> 4115 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { 4116 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: 4117 link->speed.autoneg = true; 4118 break; 4119 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: 4120 link->speed.forced_speed = 1000; 4121 break; 4122 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: 4123 link->speed.forced_speed = 10000; 4124 break; 4125 case NVM_CFG1_PORT_DRV_LINK_SPEED_20G: 4126 link->speed.forced_speed = 20000; 4127 break; 4128 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: 4129 link->speed.forced_speed = 25000; 4130 break; 4131 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: 4132 link->speed.forced_speed = 40000; 4133 break; 4134 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: 4135 link->speed.forced_speed = 50000; 4136 break; 4137 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G: 4138 link->speed.forced_speed = 100000; 4139 break; 4140 default: 4141 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp); 4142 } 4143 4144 p_caps->default_speed_autoneg = link->speed.autoneg; 4145 4146 fld = GET_MFW_FIELD(link_temp, NVM_CFG1_PORT_DRV_FLOW_CONTROL); 4147 link->pause.autoneg = !!(fld & NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); 4148 link->pause.forced_rx = !!(fld & NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); 4149 link->pause.forced_tx = !!(fld & NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); 4150 link->loopback_mode = 0; 4151 4152 if (p_hwfn->mcp_info->capabilities & 4153 FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL) { 4154 switch (GET_MFW_FIELD(link_temp, 4155 NVM_CFG1_PORT_FEC_FORCE_MODE)) { 4156 case NVM_CFG1_PORT_FEC_FORCE_MODE_NONE: 4157 p_caps->fec_default |= QED_FEC_MODE_NONE; 4158 break; 4159 case NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE: 4160 p_caps->fec_default |= QED_FEC_MODE_FIRECODE; 4161 break; 4162 case NVM_CFG1_PORT_FEC_FORCE_MODE_RS: 4163 p_caps->fec_default |= QED_FEC_MODE_RS; 4164 break; 4165 case NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO: 4166 p_caps->fec_default |= QED_FEC_MODE_AUTO; 4167 break; 4168 default: 4169 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 4170 "unknown FEC mode in 0x%08x\n", link_temp); 4171 } 4172 } else { 4173 p_caps->fec_default = QED_FEC_MODE_UNSUPPORTED; 4174 } 4175 4176 link->fec = p_caps->fec_default; 4177 4178 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) { 4179 link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr + 4180 offsetof(struct nvm_cfg1_port, ext_phy)); 4181 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK; 4182 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET; 4183 p_caps->default_eee = QED_MCP_EEE_ENABLED; 4184 link->eee.enable = true; 4185 switch (link_temp) { 4186 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED: 4187 p_caps->default_eee = QED_MCP_EEE_DISABLED; 4188 link->eee.enable = false; 4189 break; 4190 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED: 4191 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME; 4192 break; 4193 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE: 4194 p_caps->eee_lpi_timer = 4195 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME; 4196 break; 4197 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY: 4198 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME; 4199 break; 4200 } 4201 4202 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer; 4203 link->eee.tx_lpi_enable = link->eee.enable; 4204 link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV; 4205 } else { 4206 p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED; 4207 } 4208 4209 if (p_hwfn->mcp_info->capabilities & 4210 FW_MB_PARAM_FEATURE_SUPPORT_EXT_SPEED_FEC_CONTROL) { 4211 ext_speed = &link->ext_speed; 4212 4213 link_temp = qed_rd(p_hwfn, p_ptt, 4214 port_cfg_addr + 4215 offsetof(struct nvm_cfg1_port, 4216 extended_speed)); 4217 4218 fld = GET_MFW_FIELD(link_temp, NVM_CFG1_PORT_EXTENDED_SPEED); 4219 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_AN) 4220 ext_speed->autoneg = true; 4221 4222 ext_speed->forced_speed = 0; 4223 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_1G) 4224 ext_speed->forced_speed |= QED_EXT_SPEED_1G; 4225 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_10G) 4226 ext_speed->forced_speed |= QED_EXT_SPEED_10G; 4227 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_20G) 4228 ext_speed->forced_speed |= QED_EXT_SPEED_20G; 4229 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_25G) 4230 ext_speed->forced_speed |= QED_EXT_SPEED_25G; 4231 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_40G) 4232 ext_speed->forced_speed |= QED_EXT_SPEED_40G; 4233 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R) 4234 ext_speed->forced_speed |= QED_EXT_SPEED_50G_R; 4235 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R2) 4236 ext_speed->forced_speed |= QED_EXT_SPEED_50G_R2; 4237 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R2) 4238 ext_speed->forced_speed |= QED_EXT_SPEED_100G_R2; 4239 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R4) 4240 ext_speed->forced_speed |= QED_EXT_SPEED_100G_R4; 4241 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_P4) 4242 ext_speed->forced_speed |= QED_EXT_SPEED_100G_P4; 4243 4244 fld = GET_MFW_FIELD(link_temp, 4245 NVM_CFG1_PORT_EXTENDED_SPEED_CAP); 4246 4247 ext_speed->advertised_speeds = 0; 4248 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_RESERVED) 4249 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_RES; 4250 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_1G) 4251 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_1G; 4252 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_10G) 4253 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_10G; 4254 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_20G) 4255 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_20G; 4256 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_25G) 4257 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_25G; 4258 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_40G) 4259 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_40G; 4260 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R) 4261 ext_speed->advertised_speeds |= 4262 QED_EXT_SPEED_MASK_50G_R; 4263 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R2) 4264 ext_speed->advertised_speeds |= 4265 QED_EXT_SPEED_MASK_50G_R2; 4266 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R2) 4267 ext_speed->advertised_speeds |= 4268 QED_EXT_SPEED_MASK_100G_R2; 4269 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R4) 4270 ext_speed->advertised_speeds |= 4271 QED_EXT_SPEED_MASK_100G_R4; 4272 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_P4) 4273 ext_speed->advertised_speeds |= 4274 QED_EXT_SPEED_MASK_100G_P4; 4275 4276 link_temp = qed_rd(p_hwfn, p_ptt, 4277 port_cfg_addr + 4278 offsetof(struct nvm_cfg1_port, 4279 extended_fec_mode)); 4280 link->ext_fec_mode = link_temp; 4281 4282 p_caps->default_ext_speed_caps = ext_speed->advertised_speeds; 4283 p_caps->default_ext_speed = ext_speed->forced_speed; 4284 p_caps->default_ext_autoneg = ext_speed->autoneg; 4285 p_caps->default_ext_fec = link->ext_fec_mode; 4286 4287 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 4288 "Read default extended link config: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, FEC: 0x%02x\n", 4289 ext_speed->forced_speed, 4290 ext_speed->advertised_speeds, ext_speed->autoneg, 4291 p_caps->default_ext_fec); 4292 } 4293 4294 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 4295 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x, EEE: 0x%02x [0x%08x usec], FEC: 0x%02x\n", 4296 link->speed.forced_speed, link->speed.advertised_speeds, 4297 link->speed.autoneg, link->pause.autoneg, 4298 p_caps->default_eee, p_caps->eee_lpi_timer, 4299 p_caps->fec_default); 4300 4301 if (IS_LEAD_HWFN(p_hwfn)) { 4302 struct qed_dev *cdev = p_hwfn->cdev; 4303 4304 /* Read Multi-function information from shmem */ 4305 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 4306 offsetof(struct nvm_cfg1, glob) + 4307 offsetof(struct nvm_cfg1_glob, generic_cont0); 4308 4309 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr); 4310 4311 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> 4312 NVM_CFG1_GLOB_MF_MODE_OFFSET; 4313 4314 switch (mf_mode) { 4315 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: 4316 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS); 4317 break; 4318 case NVM_CFG1_GLOB_MF_MODE_UFP: 4319 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) | 4320 BIT(QED_MF_LLH_PROTO_CLSS) | 4321 BIT(QED_MF_UFP_SPECIFIC) | 4322 BIT(QED_MF_8021Q_TAGGING) | 4323 BIT(QED_MF_DONT_ADD_VLAN0_TAG); 4324 break; 4325 case NVM_CFG1_GLOB_MF_MODE_BD: 4326 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) | 4327 BIT(QED_MF_LLH_PROTO_CLSS) | 4328 BIT(QED_MF_8021AD_TAGGING) | 4329 BIT(QED_MF_DONT_ADD_VLAN0_TAG); 4330 break; 4331 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: 4332 cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) | 4333 BIT(QED_MF_LLH_PROTO_CLSS) | 4334 BIT(QED_MF_LL2_NON_UNICAST) | 4335 BIT(QED_MF_INTER_PF_SWITCH) | 4336 BIT(QED_MF_DISABLE_ARFS); 4337 break; 4338 case NVM_CFG1_GLOB_MF_MODE_DEFAULT: 4339 cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) | 4340 BIT(QED_MF_LLH_PROTO_CLSS) | 4341 BIT(QED_MF_LL2_NON_UNICAST); 4342 if (QED_IS_BB(p_hwfn->cdev)) 4343 cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF); 4344 break; 4345 } 4346 4347 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n", 4348 cdev->mf_bits); 4349 4350 /* In CMT the PF is unknown when the GFS block processes the 4351 * packet. Therefore cannot use searcher as it has a per PF 4352 * database, and thus ARFS must be disabled. 4353 * 4354 */ 4355 if (QED_IS_CMT(cdev)) 4356 cdev->mf_bits |= BIT(QED_MF_DISABLE_ARFS); 4357 } 4358 4359 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n", 4360 p_hwfn->cdev->mf_bits); 4361 4362 /* Read device capabilities information from shmem */ 4363 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 4364 offsetof(struct nvm_cfg1, glob) + 4365 offsetof(struct nvm_cfg1_glob, device_capabilities); 4366 4367 device_capabilities = qed_rd(p_hwfn, p_ptt, addr); 4368 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) 4369 __set_bit(QED_DEV_CAP_ETH, 4370 &p_hwfn->hw_info.device_capabilities); 4371 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE) 4372 __set_bit(QED_DEV_CAP_FCOE, 4373 &p_hwfn->hw_info.device_capabilities); 4374 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI) 4375 __set_bit(QED_DEV_CAP_ISCSI, 4376 &p_hwfn->hw_info.device_capabilities); 4377 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE) 4378 __set_bit(QED_DEV_CAP_ROCE, 4379 &p_hwfn->hw_info.device_capabilities); 4380 4381 /* Read device serial number information from shmem */ 4382 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 4383 offsetof(struct nvm_cfg1, glob) + 4384 offsetof(struct nvm_cfg1_glob, serial_number); 4385 4386 for (i = 0; i < 4; i++) 4387 p_hwfn->hw_info.part_num[i] = qed_rd(p_hwfn, p_ptt, addr + i * 4); 4388 4389 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt); 4390 } 4391 4392 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 4393 { 4394 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id; 4395 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask; 4396 struct qed_dev *cdev = p_hwfn->cdev; 4397 4398 num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB; 4399 4400 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values 4401 * in the other bits are selected. 4402 * Bits 1-15 are for functions 1-15, respectively, and their value is 4403 * '0' only for enabled functions (function 0 always exists and 4404 * enabled). 4405 * In case of CMT, only the "even" functions are enabled, and thus the 4406 * number of functions for both hwfns is learnt from the same bits. 4407 */ 4408 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE); 4409 4410 if (reg_function_hide & 0x1) { 4411 if (QED_IS_BB(cdev)) { 4412 if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) { 4413 num_funcs = 0; 4414 eng_mask = 0xaaaa; 4415 } else { 4416 num_funcs = 1; 4417 eng_mask = 0x5554; 4418 } 4419 } else { 4420 num_funcs = 1; 4421 eng_mask = 0xfffe; 4422 } 4423 4424 /* Get the number of the enabled functions on the engine */ 4425 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask; 4426 while (tmp) { 4427 if (tmp & 0x1) 4428 num_funcs++; 4429 tmp >>= 0x1; 4430 } 4431 4432 /* Get the PF index within the enabled functions */ 4433 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1; 4434 tmp = reg_function_hide & eng_mask & low_pfs_mask; 4435 while (tmp) { 4436 if (tmp & 0x1) 4437 enabled_func_idx--; 4438 tmp >>= 0x1; 4439 } 4440 } 4441 4442 p_hwfn->num_funcs_on_engine = num_funcs; 4443 p_hwfn->enabled_func_idx = enabled_func_idx; 4444 4445 DP_VERBOSE(p_hwfn, 4446 NETIF_MSG_PROBE, 4447 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n", 4448 p_hwfn->rel_pf_id, 4449 p_hwfn->abs_pf_id, 4450 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine); 4451 } 4452 4453 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 4454 { 4455 u32 addr, global_offsize, global_addr, port_mode; 4456 struct qed_dev *cdev = p_hwfn->cdev; 4457 4458 /* In CMT there is always only one port */ 4459 if (cdev->num_hwfns > 1) { 4460 cdev->num_ports_in_engine = 1; 4461 cdev->num_ports = 1; 4462 return; 4463 } 4464 4465 /* Determine the number of ports per engine */ 4466 port_mode = qed_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE); 4467 switch (port_mode) { 4468 case 0x0: 4469 cdev->num_ports_in_engine = 1; 4470 break; 4471 case 0x1: 4472 cdev->num_ports_in_engine = 2; 4473 break; 4474 case 0x2: 4475 cdev->num_ports_in_engine = 4; 4476 break; 4477 default: 4478 DP_NOTICE(p_hwfn, "Unknown port mode 0x%08x\n", port_mode); 4479 cdev->num_ports_in_engine = 1; /* Default to something */ 4480 break; 4481 } 4482 4483 /* Get the total number of ports of the device */ 4484 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 4485 PUBLIC_GLOBAL); 4486 global_offsize = qed_rd(p_hwfn, p_ptt, addr); 4487 global_addr = SECTION_ADDR(global_offsize, 0); 4488 addr = global_addr + offsetof(struct public_global, max_ports); 4489 cdev->num_ports = (u8)qed_rd(p_hwfn, p_ptt, addr); 4490 } 4491 4492 static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 4493 { 4494 struct qed_mcp_link_capabilities *p_caps; 4495 u32 eee_status; 4496 4497 p_caps = &p_hwfn->mcp_info->link_capabilities; 4498 if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED) 4499 return; 4500 4501 p_caps->eee_speed_caps = 0; 4502 eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 4503 offsetof(struct public_port, eee_status)); 4504 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >> 4505 EEE_SUPPORTED_SPEED_OFFSET; 4506 4507 if (eee_status & EEE_1G_SUPPORTED) 4508 p_caps->eee_speed_caps |= QED_EEE_1G_ADV; 4509 if (eee_status & EEE_10G_ADV) 4510 p_caps->eee_speed_caps |= QED_EEE_10G_ADV; 4511 } 4512 4513 static int 4514 qed_get_hw_info(struct qed_hwfn *p_hwfn, 4515 struct qed_ptt *p_ptt, 4516 enum qed_pci_personality personality) 4517 { 4518 int rc; 4519 4520 /* Since all information is common, only first hwfns should do this */ 4521 if (IS_LEAD_HWFN(p_hwfn)) { 4522 rc = qed_iov_hw_info(p_hwfn); 4523 if (rc) 4524 return rc; 4525 } 4526 4527 if (IS_LEAD_HWFN(p_hwfn)) 4528 qed_hw_info_port_num(p_hwfn, p_ptt); 4529 4530 qed_mcp_get_capabilities(p_hwfn, p_ptt); 4531 4532 qed_hw_get_nvm_info(p_hwfn, p_ptt); 4533 4534 rc = qed_int_igu_read_cam(p_hwfn, p_ptt); 4535 if (rc) 4536 return rc; 4537 4538 if (qed_mcp_is_init(p_hwfn)) 4539 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr, 4540 p_hwfn->mcp_info->func_info.mac); 4541 else 4542 eth_random_addr(p_hwfn->hw_info.hw_mac_addr); 4543 4544 if (qed_mcp_is_init(p_hwfn)) { 4545 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET) 4546 p_hwfn->hw_info.ovlan = 4547 p_hwfn->mcp_info->func_info.ovlan; 4548 4549 qed_mcp_cmd_port_init(p_hwfn, p_ptt); 4550 4551 qed_get_eee_caps(p_hwfn, p_ptt); 4552 4553 qed_mcp_read_ufp_config(p_hwfn, p_ptt); 4554 } 4555 4556 if (qed_mcp_is_init(p_hwfn)) { 4557 enum qed_pci_personality protocol; 4558 4559 protocol = p_hwfn->mcp_info->func_info.protocol; 4560 p_hwfn->hw_info.personality = protocol; 4561 } 4562 4563 if (QED_IS_ROCE_PERSONALITY(p_hwfn)) 4564 p_hwfn->hw_info.multi_tc_roce_en = true; 4565 4566 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2; 4567 p_hwfn->hw_info.num_active_tc = 1; 4568 4569 qed_get_num_funcs(p_hwfn, p_ptt); 4570 4571 if (qed_mcp_is_init(p_hwfn)) 4572 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu; 4573 4574 return qed_hw_get_resc(p_hwfn, p_ptt); 4575 } 4576 4577 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 4578 { 4579 struct qed_dev *cdev = p_hwfn->cdev; 4580 u16 device_id_mask; 4581 u32 tmp; 4582 4583 /* Read Vendor Id / Device Id */ 4584 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id); 4585 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id); 4586 4587 /* Determine type */ 4588 device_id_mask = cdev->device_id & QED_DEV_ID_MASK; 4589 switch (device_id_mask) { 4590 case QED_DEV_ID_MASK_BB: 4591 cdev->type = QED_DEV_TYPE_BB; 4592 break; 4593 case QED_DEV_ID_MASK_AH: 4594 cdev->type = QED_DEV_TYPE_AH; 4595 break; 4596 default: 4597 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id); 4598 return -EBUSY; 4599 } 4600 4601 cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM); 4602 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV); 4603 4604 MASK_FIELD(CHIP_REV, cdev->chip_rev); 4605 4606 /* Learn number of HW-functions */ 4607 tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR); 4608 4609 if (tmp & (1 << p_hwfn->rel_pf_id)) { 4610 DP_NOTICE(cdev->hwfns, "device in CMT mode\n"); 4611 cdev->num_hwfns = 2; 4612 } else { 4613 cdev->num_hwfns = 1; 4614 } 4615 4616 cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt, 4617 MISCS_REG_CHIP_TEST_REG) >> 4; 4618 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id); 4619 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL); 4620 MASK_FIELD(CHIP_METAL, cdev->chip_metal); 4621 4622 DP_INFO(cdev->hwfns, 4623 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n", 4624 QED_IS_BB(cdev) ? "BB" : "AH", 4625 'A' + cdev->chip_rev, 4626 (int)cdev->chip_metal, 4627 cdev->chip_num, cdev->chip_rev, 4628 cdev->chip_bond_id, cdev->chip_metal); 4629 4630 return 0; 4631 } 4632 4633 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn, 4634 void __iomem *p_regview, 4635 void __iomem *p_doorbells, 4636 u64 db_phys_addr, 4637 enum qed_pci_personality personality) 4638 { 4639 struct qed_dev *cdev = p_hwfn->cdev; 4640 int rc = 0; 4641 4642 /* Split PCI bars evenly between hwfns */ 4643 p_hwfn->regview = p_regview; 4644 p_hwfn->doorbells = p_doorbells; 4645 p_hwfn->db_phys_addr = db_phys_addr; 4646 4647 if (IS_VF(p_hwfn->cdev)) 4648 return qed_vf_hw_prepare(p_hwfn); 4649 4650 /* Validate that chip access is feasible */ 4651 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { 4652 DP_ERR(p_hwfn, 4653 "Reading the ME register returns all Fs; Preventing further chip access\n"); 4654 return -EINVAL; 4655 } 4656 4657 get_function_id(p_hwfn); 4658 4659 /* Allocate PTT pool */ 4660 rc = qed_ptt_pool_alloc(p_hwfn); 4661 if (rc) 4662 goto err0; 4663 4664 /* Allocate the main PTT */ 4665 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); 4666 4667 /* First hwfn learns basic information, e.g., number of hwfns */ 4668 if (!p_hwfn->my_id) { 4669 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt); 4670 if (rc) 4671 goto err1; 4672 } 4673 4674 qed_hw_hwfn_prepare(p_hwfn); 4675 4676 /* Initialize MCP structure */ 4677 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); 4678 if (rc) { 4679 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n"); 4680 goto err1; 4681 } 4682 4683 /* Read the device configuration information from the HW and SHMEM */ 4684 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality); 4685 if (rc) { 4686 DP_NOTICE(p_hwfn, "Failed to get HW information\n"); 4687 goto err2; 4688 } 4689 4690 /* Sending a mailbox to the MFW should be done after qed_get_hw_info() 4691 * is called as it sets the ports number in an engine. 4692 */ 4693 if (IS_LEAD_HWFN(p_hwfn) && !cdev->recov_in_prog) { 4694 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt); 4695 if (rc) 4696 DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n"); 4697 } 4698 4699 /* NVRAM info initialization and population */ 4700 if (IS_LEAD_HWFN(p_hwfn)) { 4701 rc = qed_mcp_nvm_info_populate(p_hwfn); 4702 if (rc) { 4703 DP_NOTICE(p_hwfn, 4704 "Failed to populate nvm info shadow\n"); 4705 goto err2; 4706 } 4707 } 4708 4709 /* Allocate the init RT array and initialize the init-ops engine */ 4710 rc = qed_init_alloc(p_hwfn); 4711 if (rc) 4712 goto err3; 4713 4714 return rc; 4715 err3: 4716 if (IS_LEAD_HWFN(p_hwfn)) 4717 qed_mcp_nvm_info_free(p_hwfn); 4718 err2: 4719 if (IS_LEAD_HWFN(p_hwfn)) 4720 qed_iov_free_hw_info(p_hwfn->cdev); 4721 qed_mcp_free(p_hwfn); 4722 err1: 4723 qed_hw_hwfn_free(p_hwfn); 4724 err0: 4725 return rc; 4726 } 4727 4728 int qed_hw_prepare(struct qed_dev *cdev, 4729 int personality) 4730 { 4731 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 4732 int rc; 4733 4734 /* Store the precompiled init data ptrs */ 4735 if (IS_PF(cdev)) 4736 qed_init_iro_array(cdev); 4737 4738 /* Initialize the first hwfn - will learn number of hwfns */ 4739 rc = qed_hw_prepare_single(p_hwfn, 4740 cdev->regview, 4741 cdev->doorbells, 4742 cdev->db_phys_addr, 4743 personality); 4744 if (rc) 4745 return rc; 4746 4747 personality = p_hwfn->hw_info.personality; 4748 4749 /* Initialize the rest of the hwfns */ 4750 if (cdev->num_hwfns > 1) { 4751 void __iomem *p_regview, *p_doorbell; 4752 u64 db_phys_addr; 4753 u32 offset; 4754 4755 /* adjust bar offset for second engine */ 4756 offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt, 4757 BAR_ID_0) / 2; 4758 p_regview = cdev->regview + offset; 4759 4760 offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt, 4761 BAR_ID_1) / 2; 4762 4763 p_doorbell = cdev->doorbells + offset; 4764 4765 db_phys_addr = cdev->db_phys_addr + offset; 4766 4767 /* prepare second hw function */ 4768 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview, 4769 p_doorbell, db_phys_addr, 4770 personality); 4771 4772 /* in case of error, need to free the previously 4773 * initiliazed hwfn 0. 4774 */ 4775 if (rc) { 4776 if (IS_PF(cdev)) { 4777 qed_init_free(p_hwfn); 4778 qed_mcp_nvm_info_free(p_hwfn); 4779 qed_mcp_free(p_hwfn); 4780 qed_hw_hwfn_free(p_hwfn); 4781 } 4782 } 4783 } 4784 4785 return rc; 4786 } 4787 4788 void qed_hw_remove(struct qed_dev *cdev) 4789 { 4790 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 4791 int i; 4792 4793 if (IS_PF(cdev)) 4794 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt, 4795 QED_OV_DRIVER_STATE_NOT_LOADED); 4796 4797 for_each_hwfn(cdev, i) { 4798 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 4799 4800 if (IS_VF(cdev)) { 4801 qed_vf_pf_release(p_hwfn); 4802 continue; 4803 } 4804 4805 qed_init_free(p_hwfn); 4806 qed_hw_hwfn_free(p_hwfn); 4807 qed_mcp_free(p_hwfn); 4808 } 4809 4810 qed_iov_free_hw_info(cdev); 4811 4812 qed_mcp_nvm_info_free(p_hwfn); 4813 } 4814 4815 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id) 4816 { 4817 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) { 4818 u16 min, max; 4819 4820 min = (u16)RESC_START(p_hwfn, QED_L2_QUEUE); 4821 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE); 4822 DP_NOTICE(p_hwfn, 4823 "l2_queue id [%d] is not valid, available indices [%d - %d]\n", 4824 src_id, min, max); 4825 4826 return -EINVAL; 4827 } 4828 4829 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id; 4830 4831 return 0; 4832 } 4833 4834 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 4835 { 4836 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) { 4837 u8 min, max; 4838 4839 min = (u8)RESC_START(p_hwfn, QED_VPORT); 4840 max = min + RESC_NUM(p_hwfn, QED_VPORT); 4841 DP_NOTICE(p_hwfn, 4842 "vport id [%d] is not valid, available indices [%d - %d]\n", 4843 src_id, min, max); 4844 4845 return -EINVAL; 4846 } 4847 4848 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id; 4849 4850 return 0; 4851 } 4852 4853 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 4854 { 4855 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) { 4856 u8 min, max; 4857 4858 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG); 4859 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG); 4860 DP_NOTICE(p_hwfn, 4861 "rss_eng id [%d] is not valid, available indices [%d - %d]\n", 4862 src_id, min, max); 4863 4864 return -EINVAL; 4865 } 4866 4867 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id; 4868 4869 return 0; 4870 } 4871 4872 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 4873 u32 hw_addr, void *p_eth_qzone, 4874 size_t eth_qzone_size, u8 timeset) 4875 { 4876 struct coalescing_timeset *p_coal_timeset; 4877 4878 if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) { 4879 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n"); 4880 return -EINVAL; 4881 } 4882 4883 p_coal_timeset = p_eth_qzone; 4884 memset(p_eth_qzone, 0, eth_qzone_size); 4885 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset); 4886 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1); 4887 qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size); 4888 4889 return 0; 4890 } 4891 4892 int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle) 4893 { 4894 struct qed_queue_cid *p_cid = p_handle; 4895 struct qed_hwfn *p_hwfn; 4896 struct qed_ptt *p_ptt; 4897 int rc = 0; 4898 4899 p_hwfn = p_cid->p_owner; 4900 4901 if (IS_VF(p_hwfn->cdev)) 4902 return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid); 4903 4904 p_ptt = qed_ptt_acquire(p_hwfn); 4905 if (!p_ptt) 4906 return -EAGAIN; 4907 4908 if (rx_coal) { 4909 rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid); 4910 if (rc) 4911 goto out; 4912 p_hwfn->cdev->rx_coalesce_usecs = rx_coal; 4913 } 4914 4915 if (tx_coal) { 4916 rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid); 4917 if (rc) 4918 goto out; 4919 p_hwfn->cdev->tx_coalesce_usecs = tx_coal; 4920 } 4921 out: 4922 qed_ptt_release(p_hwfn, p_ptt); 4923 return rc; 4924 } 4925 4926 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, 4927 struct qed_ptt *p_ptt, 4928 u16 coalesce, struct qed_queue_cid *p_cid) 4929 { 4930 struct ustorm_eth_queue_zone eth_qzone; 4931 u8 timeset, timer_res; 4932 u32 address; 4933 int rc; 4934 4935 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 4936 if (coalesce <= 0x7F) { 4937 timer_res = 0; 4938 } else if (coalesce <= 0xFF) { 4939 timer_res = 1; 4940 } else if (coalesce <= 0x1FF) { 4941 timer_res = 2; 4942 } else { 4943 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 4944 return -EINVAL; 4945 } 4946 timeset = (u8)(coalesce >> timer_res); 4947 4948 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, 4949 p_cid->sb_igu_id, false); 4950 if (rc) 4951 goto out; 4952 4953 address = BAR0_MAP_REG_USDM_RAM + 4954 USTORM_ETH_QUEUE_ZONE_GTT_OFFSET(p_cid->abs.queue_id); 4955 4956 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 4957 sizeof(struct ustorm_eth_queue_zone), timeset); 4958 if (rc) 4959 goto out; 4960 4961 out: 4962 return rc; 4963 } 4964 4965 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, 4966 struct qed_ptt *p_ptt, 4967 u16 coalesce, struct qed_queue_cid *p_cid) 4968 { 4969 struct xstorm_eth_queue_zone eth_qzone; 4970 u8 timeset, timer_res; 4971 u32 address; 4972 int rc; 4973 4974 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 4975 if (coalesce <= 0x7F) { 4976 timer_res = 0; 4977 } else if (coalesce <= 0xFF) { 4978 timer_res = 1; 4979 } else if (coalesce <= 0x1FF) { 4980 timer_res = 2; 4981 } else { 4982 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 4983 return -EINVAL; 4984 } 4985 timeset = (u8)(coalesce >> timer_res); 4986 4987 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, 4988 p_cid->sb_igu_id, true); 4989 if (rc) 4990 goto out; 4991 4992 address = BAR0_MAP_REG_XSDM_RAM + 4993 XSTORM_ETH_QUEUE_ZONE_GTT_OFFSET(p_cid->abs.queue_id); 4994 4995 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 4996 sizeof(struct xstorm_eth_queue_zone), timeset); 4997 out: 4998 return rc; 4999 } 5000 5001 /* Calculate final WFQ values for all vports and configure them. 5002 * After this configuration each vport will have 5003 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT) 5004 */ 5005 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 5006 struct qed_ptt *p_ptt, 5007 u32 min_pf_rate) 5008 { 5009 struct init_qm_vport_params *vport_params; 5010 int i; 5011 5012 vport_params = p_hwfn->qm_info.qm_vport_params; 5013 5014 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 5015 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 5016 5017 vport_params[i].wfq = (wfq_speed * QED_WFQ_UNIT) / 5018 min_pf_rate; 5019 qed_init_vport_wfq(p_hwfn, p_ptt, 5020 vport_params[i].first_tx_pq_id, 5021 vport_params[i].wfq); 5022 } 5023 } 5024 5025 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn, 5026 u32 min_pf_rate) 5027 5028 { 5029 int i; 5030 5031 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) 5032 p_hwfn->qm_info.qm_vport_params[i].wfq = 1; 5033 } 5034 5035 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 5036 struct qed_ptt *p_ptt, 5037 u32 min_pf_rate) 5038 { 5039 struct init_qm_vport_params *vport_params; 5040 int i; 5041 5042 vport_params = p_hwfn->qm_info.qm_vport_params; 5043 5044 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 5045 qed_init_wfq_default_param(p_hwfn, min_pf_rate); 5046 qed_init_vport_wfq(p_hwfn, p_ptt, 5047 vport_params[i].first_tx_pq_id, 5048 vport_params[i].wfq); 5049 } 5050 } 5051 5052 /* This function performs several validations for WFQ 5053 * configuration and required min rate for a given vport 5054 * 1. req_rate must be greater than one percent of min_pf_rate. 5055 * 2. req_rate should not cause other vports [not configured for WFQ explicitly] 5056 * rates to get less than one percent of min_pf_rate. 5057 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate. 5058 */ 5059 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn, 5060 u16 vport_id, u32 req_rate, u32 min_pf_rate) 5061 { 5062 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0; 5063 int non_requested_count = 0, req_count = 0, i, num_vports; 5064 5065 num_vports = p_hwfn->qm_info.num_vports; 5066 5067 if (num_vports < 2) { 5068 DP_NOTICE(p_hwfn, "Unexpected num_vports: %d\n", num_vports); 5069 return -EINVAL; 5070 } 5071 5072 /* Accounting for the vports which are configured for WFQ explicitly */ 5073 for (i = 0; i < num_vports; i++) { 5074 u32 tmp_speed; 5075 5076 if ((i != vport_id) && 5077 p_hwfn->qm_info.wfq_data[i].configured) { 5078 req_count++; 5079 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 5080 total_req_min_rate += tmp_speed; 5081 } 5082 } 5083 5084 /* Include current vport data as well */ 5085 req_count++; 5086 total_req_min_rate += req_rate; 5087 non_requested_count = num_vports - req_count; 5088 5089 if (req_rate < min_pf_rate / QED_WFQ_UNIT) { 5090 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 5091 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 5092 vport_id, req_rate, min_pf_rate); 5093 return -EINVAL; 5094 } 5095 5096 if (num_vports > QED_WFQ_UNIT) { 5097 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 5098 "Number of vports is greater than %d\n", 5099 QED_WFQ_UNIT); 5100 return -EINVAL; 5101 } 5102 5103 if (total_req_min_rate > min_pf_rate) { 5104 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 5105 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", 5106 total_req_min_rate, min_pf_rate); 5107 return -EINVAL; 5108 } 5109 5110 total_left_rate = min_pf_rate - total_req_min_rate; 5111 5112 left_rate_per_vp = total_left_rate / non_requested_count; 5113 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) { 5114 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 5115 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 5116 left_rate_per_vp, min_pf_rate); 5117 return -EINVAL; 5118 } 5119 5120 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate; 5121 p_hwfn->qm_info.wfq_data[vport_id].configured = true; 5122 5123 for (i = 0; i < num_vports; i++) { 5124 if (p_hwfn->qm_info.wfq_data[i].configured) 5125 continue; 5126 5127 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp; 5128 } 5129 5130 return 0; 5131 } 5132 5133 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn, 5134 struct qed_ptt *p_ptt, u16 vp_id, u32 rate) 5135 { 5136 struct qed_mcp_link_state *p_link; 5137 int rc = 0; 5138 5139 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output; 5140 5141 if (!p_link->min_pf_rate) { 5142 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate; 5143 p_hwfn->qm_info.wfq_data[vp_id].configured = true; 5144 return rc; 5145 } 5146 5147 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate); 5148 5149 if (!rc) 5150 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, 5151 p_link->min_pf_rate); 5152 else 5153 DP_NOTICE(p_hwfn, 5154 "Validation failed while configuring min rate\n"); 5155 5156 return rc; 5157 } 5158 5159 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn, 5160 struct qed_ptt *p_ptt, 5161 u32 min_pf_rate) 5162 { 5163 bool use_wfq = false; 5164 int rc = 0; 5165 u16 i; 5166 5167 /* Validate all pre configured vports for wfq */ 5168 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 5169 u32 rate; 5170 5171 if (!p_hwfn->qm_info.wfq_data[i].configured) 5172 continue; 5173 5174 rate = p_hwfn->qm_info.wfq_data[i].min_speed; 5175 use_wfq = true; 5176 5177 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate); 5178 if (rc) { 5179 DP_NOTICE(p_hwfn, 5180 "WFQ validation failed while configuring min rate\n"); 5181 break; 5182 } 5183 } 5184 5185 if (!rc && use_wfq) 5186 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 5187 else 5188 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 5189 5190 return rc; 5191 } 5192 5193 /* Main API for qed clients to configure vport min rate. 5194 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)] 5195 * rate - Speed in Mbps needs to be assigned to a given vport. 5196 */ 5197 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate) 5198 { 5199 int i, rc = -EINVAL; 5200 5201 /* Currently not supported; Might change in future */ 5202 if (cdev->num_hwfns > 1) { 5203 DP_NOTICE(cdev, 5204 "WFQ configuration is not supported for this device\n"); 5205 return rc; 5206 } 5207 5208 for_each_hwfn(cdev, i) { 5209 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 5210 struct qed_ptt *p_ptt; 5211 5212 p_ptt = qed_ptt_acquire(p_hwfn); 5213 if (!p_ptt) 5214 return -EBUSY; 5215 5216 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate); 5217 5218 if (rc) { 5219 qed_ptt_release(p_hwfn, p_ptt); 5220 return rc; 5221 } 5222 5223 qed_ptt_release(p_hwfn, p_ptt); 5224 } 5225 5226 return rc; 5227 } 5228 5229 /* API to configure WFQ from mcp link change */ 5230 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, 5231 struct qed_ptt *p_ptt, u32 min_pf_rate) 5232 { 5233 int i; 5234 5235 if (cdev->num_hwfns > 1) { 5236 DP_VERBOSE(cdev, 5237 NETIF_MSG_LINK, 5238 "WFQ configuration is not supported for this device\n"); 5239 return; 5240 } 5241 5242 for_each_hwfn(cdev, i) { 5243 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 5244 5245 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt, 5246 min_pf_rate); 5247 } 5248 } 5249 5250 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, 5251 struct qed_ptt *p_ptt, 5252 struct qed_mcp_link_state *p_link, 5253 u8 max_bw) 5254 { 5255 int rc = 0; 5256 5257 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw; 5258 5259 if (!p_link->line_speed && (max_bw != 100)) 5260 return rc; 5261 5262 p_link->speed = (p_link->line_speed * max_bw) / 100; 5263 p_hwfn->qm_info.pf_rl = p_link->speed; 5264 5265 /* Since the limiter also affects Tx-switched traffic, we don't want it 5266 * to limit such traffic in case there's no actual limit. 5267 * In that case, set limit to imaginary high boundary. 5268 */ 5269 if (max_bw == 100) 5270 p_hwfn->qm_info.pf_rl = 100000; 5271 5272 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 5273 p_hwfn->qm_info.pf_rl); 5274 5275 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 5276 "Configured MAX bandwidth to be %08x Mb/sec\n", 5277 p_link->speed); 5278 5279 return rc; 5280 } 5281 5282 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */ 5283 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw) 5284 { 5285 int i, rc = -EINVAL; 5286 5287 if (max_bw < 1 || max_bw > 100) { 5288 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n"); 5289 return rc; 5290 } 5291 5292 for_each_hwfn(cdev, i) { 5293 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 5294 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 5295 struct qed_mcp_link_state *p_link; 5296 struct qed_ptt *p_ptt; 5297 5298 p_link = &p_lead->mcp_info->link_output; 5299 5300 p_ptt = qed_ptt_acquire(p_hwfn); 5301 if (!p_ptt) 5302 return -EBUSY; 5303 5304 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, 5305 p_link, max_bw); 5306 5307 qed_ptt_release(p_hwfn, p_ptt); 5308 5309 if (rc) 5310 break; 5311 } 5312 5313 return rc; 5314 } 5315 5316 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn, 5317 struct qed_ptt *p_ptt, 5318 struct qed_mcp_link_state *p_link, 5319 u8 min_bw) 5320 { 5321 int rc = 0; 5322 5323 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw; 5324 p_hwfn->qm_info.pf_wfq = min_bw; 5325 5326 if (!p_link->line_speed) 5327 return rc; 5328 5329 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100; 5330 5331 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw); 5332 5333 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 5334 "Configured MIN bandwidth to be %d Mb/sec\n", 5335 p_link->min_pf_rate); 5336 5337 return rc; 5338 } 5339 5340 /* Main API to configure PF min bandwidth where bw range is [1-100] */ 5341 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw) 5342 { 5343 int i, rc = -EINVAL; 5344 5345 if (min_bw < 1 || min_bw > 100) { 5346 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n"); 5347 return rc; 5348 } 5349 5350 for_each_hwfn(cdev, i) { 5351 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 5352 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 5353 struct qed_mcp_link_state *p_link; 5354 struct qed_ptt *p_ptt; 5355 5356 p_link = &p_lead->mcp_info->link_output; 5357 5358 p_ptt = qed_ptt_acquire(p_hwfn); 5359 if (!p_ptt) 5360 return -EBUSY; 5361 5362 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, 5363 p_link, min_bw); 5364 if (rc) { 5365 qed_ptt_release(p_hwfn, p_ptt); 5366 return rc; 5367 } 5368 5369 if (p_link->min_pf_rate) { 5370 u32 min_rate = p_link->min_pf_rate; 5371 5372 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn, 5373 p_ptt, 5374 min_rate); 5375 } 5376 5377 qed_ptt_release(p_hwfn, p_ptt); 5378 } 5379 5380 return rc; 5381 } 5382 5383 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 5384 { 5385 struct qed_mcp_link_state *p_link; 5386 5387 p_link = &p_hwfn->mcp_info->link_output; 5388 5389 if (p_link->min_pf_rate) 5390 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, 5391 p_link->min_pf_rate); 5392 5393 memset(p_hwfn->qm_info.wfq_data, 0, 5394 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports); 5395 } 5396 5397 int qed_device_num_ports(struct qed_dev *cdev) 5398 { 5399 return cdev->num_ports; 5400 } 5401 5402 void qed_set_fw_mac_addr(__le16 *fw_msb, 5403 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac) 5404 { 5405 ((u8 *)fw_msb)[0] = mac[1]; 5406 ((u8 *)fw_msb)[1] = mac[0]; 5407 ((u8 *)fw_mid)[0] = mac[3]; 5408 ((u8 *)fw_mid)[1] = mac[2]; 5409 ((u8 *)fw_lsb)[0] = mac[5]; 5410 ((u8 *)fw_lsb)[1] = mac[4]; 5411 } 5412 5413 static int qed_llh_shadow_remove_all_filters(struct qed_dev *cdev, u8 ppfid) 5414 { 5415 struct qed_llh_info *p_llh_info = cdev->p_llh_info; 5416 struct qed_llh_filter_info *p_filters; 5417 int rc; 5418 5419 rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "remove_all"); 5420 if (rc) 5421 return rc; 5422 5423 p_filters = p_llh_info->pp_filters[ppfid]; 5424 memset(p_filters, 0, NIG_REG_LLH_FUNC_FILTER_EN_SIZE * 5425 sizeof(*p_filters)); 5426 5427 return 0; 5428 } 5429 5430 static void qed_llh_clear_ppfid_filters(struct qed_dev *cdev, u8 ppfid) 5431 { 5432 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 5433 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 5434 u8 filter_idx, abs_ppfid; 5435 int rc = 0; 5436 5437 if (!p_ptt) 5438 return; 5439 5440 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits) && 5441 !test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits)) 5442 goto out; 5443 5444 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 5445 if (rc) 5446 goto out; 5447 5448 rc = qed_llh_shadow_remove_all_filters(cdev, ppfid); 5449 if (rc) 5450 goto out; 5451 5452 for (filter_idx = 0; filter_idx < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; 5453 filter_idx++) { 5454 rc = qed_llh_remove_filter(p_hwfn, p_ptt, 5455 abs_ppfid, filter_idx); 5456 if (rc) 5457 goto out; 5458 } 5459 out: 5460 qed_ptt_release(p_hwfn, p_ptt); 5461 } 5462 5463 int qed_llh_add_src_tcp_port_filter(struct qed_dev *cdev, u16 src_port) 5464 { 5465 return qed_llh_add_protocol_filter(cdev, 0, 5466 QED_LLH_FILTER_TCP_SRC_PORT, 5467 src_port, QED_LLH_DONT_CARE); 5468 } 5469 5470 void qed_llh_remove_src_tcp_port_filter(struct qed_dev *cdev, u16 src_port) 5471 { 5472 qed_llh_remove_protocol_filter(cdev, 0, 5473 QED_LLH_FILTER_TCP_SRC_PORT, 5474 src_port, QED_LLH_DONT_CARE); 5475 } 5476 5477 int qed_llh_add_dst_tcp_port_filter(struct qed_dev *cdev, u16 dest_port) 5478 { 5479 return qed_llh_add_protocol_filter(cdev, 0, 5480 QED_LLH_FILTER_TCP_DEST_PORT, 5481 QED_LLH_DONT_CARE, dest_port); 5482 } 5483 5484 void qed_llh_remove_dst_tcp_port_filter(struct qed_dev *cdev, u16 dest_port) 5485 { 5486 qed_llh_remove_protocol_filter(cdev, 0, 5487 QED_LLH_FILTER_TCP_DEST_PORT, 5488 QED_LLH_DONT_CARE, dest_port); 5489 } 5490 5491 void qed_llh_clear_all_filters(struct qed_dev *cdev) 5492 { 5493 u8 ppfid; 5494 5495 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits) && 5496 !test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits)) 5497 return; 5498 5499 for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) 5500 qed_llh_clear_ppfid_filters(cdev, ppfid); 5501 } 5502