1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #include <linux/types.h> 10 #include <asm/byteorder.h> 11 #include <linux/io.h> 12 #include <linux/delay.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/errno.h> 15 #include <linux/kernel.h> 16 #include <linux/mutex.h> 17 #include <linux/pci.h> 18 #include <linux/slab.h> 19 #include <linux/string.h> 20 #include <linux/vmalloc.h> 21 #include <linux/etherdevice.h> 22 #include <linux/qed/qed_chain.h> 23 #include <linux/qed/qed_if.h> 24 #include "qed.h" 25 #include "qed_cxt.h" 26 #include "qed_dcbx.h" 27 #include "qed_dev_api.h" 28 #include "qed_hsi.h" 29 #include "qed_hw.h" 30 #include "qed_init_ops.h" 31 #include "qed_int.h" 32 #include "qed_ll2.h" 33 #include "qed_mcp.h" 34 #include "qed_reg_addr.h" 35 #include "qed_sp.h" 36 #include "qed_sriov.h" 37 #include "qed_vf.h" 38 #include "qed_roce.h" 39 40 static DEFINE_SPINLOCK(qm_lock); 41 42 #define QED_MIN_DPIS (4) 43 #define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS) 44 45 /* API common to all protocols */ 46 enum BAR_ID { 47 BAR_ID_0, /* used for GRC */ 48 BAR_ID_1 /* Used for doorbells */ 49 }; 50 51 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, enum BAR_ID bar_id) 52 { 53 u32 bar_reg = (bar_id == BAR_ID_0 ? 54 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); 55 u32 val; 56 57 if (IS_VF(p_hwfn->cdev)) 58 return 1 << 17; 59 60 val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg); 61 if (val) 62 return 1 << (val + 15); 63 64 /* Old MFW initialized above registered only conditionally */ 65 if (p_hwfn->cdev->num_hwfns > 1) { 66 DP_INFO(p_hwfn, 67 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n"); 68 return BAR_ID_0 ? 256 * 1024 : 512 * 1024; 69 } else { 70 DP_INFO(p_hwfn, 71 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n"); 72 return 512 * 1024; 73 } 74 } 75 76 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level) 77 { 78 u32 i; 79 80 cdev->dp_level = dp_level; 81 cdev->dp_module = dp_module; 82 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 83 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 84 85 p_hwfn->dp_level = dp_level; 86 p_hwfn->dp_module = dp_module; 87 } 88 } 89 90 void qed_init_struct(struct qed_dev *cdev) 91 { 92 u8 i; 93 94 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 95 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 96 97 p_hwfn->cdev = cdev; 98 p_hwfn->my_id = i; 99 p_hwfn->b_active = false; 100 101 mutex_init(&p_hwfn->dmae_info.mutex); 102 } 103 104 /* hwfn 0 is always active */ 105 cdev->hwfns[0].b_active = true; 106 107 /* set the default cache alignment to 128 */ 108 cdev->cache_shift = 7; 109 } 110 111 static void qed_qm_info_free(struct qed_hwfn *p_hwfn) 112 { 113 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 114 115 kfree(qm_info->qm_pq_params); 116 qm_info->qm_pq_params = NULL; 117 kfree(qm_info->qm_vport_params); 118 qm_info->qm_vport_params = NULL; 119 kfree(qm_info->qm_port_params); 120 qm_info->qm_port_params = NULL; 121 kfree(qm_info->wfq_data); 122 qm_info->wfq_data = NULL; 123 } 124 125 void qed_resc_free(struct qed_dev *cdev) 126 { 127 int i; 128 129 if (IS_VF(cdev)) 130 return; 131 132 kfree(cdev->fw_data); 133 cdev->fw_data = NULL; 134 135 kfree(cdev->reset_stats); 136 137 for_each_hwfn(cdev, i) { 138 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 139 140 kfree(p_hwfn->p_tx_cids); 141 p_hwfn->p_tx_cids = NULL; 142 kfree(p_hwfn->p_rx_cids); 143 p_hwfn->p_rx_cids = NULL; 144 } 145 146 for_each_hwfn(cdev, i) { 147 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 148 149 qed_cxt_mngr_free(p_hwfn); 150 qed_qm_info_free(p_hwfn); 151 qed_spq_free(p_hwfn); 152 qed_eq_free(p_hwfn, p_hwfn->p_eq); 153 qed_consq_free(p_hwfn, p_hwfn->p_consq); 154 qed_int_free(p_hwfn); 155 #ifdef CONFIG_QED_LL2 156 qed_ll2_free(p_hwfn, p_hwfn->p_ll2_info); 157 #endif 158 qed_iov_free(p_hwfn); 159 qed_dmae_info_free(p_hwfn); 160 qed_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info); 161 } 162 } 163 164 static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable) 165 { 166 u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0; 167 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 168 struct init_qm_port_params *p_qm_port; 169 bool init_rdma_offload_pq = false; 170 bool init_pure_ack_pq = false; 171 bool init_ooo_pq = false; 172 u16 num_pqs, multi_cos_tcs = 1; 173 u8 pf_wfq = qm_info->pf_wfq; 174 u32 pf_rl = qm_info->pf_rl; 175 u16 num_pf_rls = 0; 176 u16 num_vfs = 0; 177 178 #ifdef CONFIG_QED_SRIOV 179 if (p_hwfn->cdev->p_iov_info) 180 num_vfs = p_hwfn->cdev->p_iov_info->total_vfs; 181 #endif 182 memset(qm_info, 0, sizeof(*qm_info)); 183 184 num_pqs = multi_cos_tcs + num_vfs + 1; /* The '1' is for pure-LB */ 185 num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT); 186 187 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) { 188 num_pqs++; /* for RoCE queue */ 189 init_rdma_offload_pq = true; 190 /* we subtract num_vfs because each require a rate limiter, 191 * and one default rate limiter 192 */ 193 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn) 194 num_pf_rls = RESC_NUM(p_hwfn, QED_RL) - num_vfs - 1; 195 196 num_pqs += num_pf_rls; 197 qm_info->num_pf_rls = (u8) num_pf_rls; 198 } 199 200 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 201 num_pqs += 2; /* for iSCSI pure-ACK / OOO queue */ 202 init_pure_ack_pq = true; 203 init_ooo_pq = true; 204 } 205 206 /* Sanity checking that setup requires legal number of resources */ 207 if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) { 208 DP_ERR(p_hwfn, 209 "Need too many Physical queues - 0x%04x when only %04x are available\n", 210 num_pqs, RESC_NUM(p_hwfn, QED_PQ)); 211 return -EINVAL; 212 } 213 214 /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete. 215 */ 216 qm_info->qm_pq_params = kcalloc(num_pqs, 217 sizeof(struct init_qm_pq_params), 218 b_sleepable ? GFP_KERNEL : GFP_ATOMIC); 219 if (!qm_info->qm_pq_params) 220 goto alloc_err; 221 222 qm_info->qm_vport_params = kcalloc(num_vports, 223 sizeof(struct init_qm_vport_params), 224 b_sleepable ? GFP_KERNEL 225 : GFP_ATOMIC); 226 if (!qm_info->qm_vport_params) 227 goto alloc_err; 228 229 qm_info->qm_port_params = kcalloc(MAX_NUM_PORTS, 230 sizeof(struct init_qm_port_params), 231 b_sleepable ? GFP_KERNEL 232 : GFP_ATOMIC); 233 if (!qm_info->qm_port_params) 234 goto alloc_err; 235 236 qm_info->wfq_data = kcalloc(num_vports, sizeof(struct qed_wfq_data), 237 b_sleepable ? GFP_KERNEL : GFP_ATOMIC); 238 if (!qm_info->wfq_data) 239 goto alloc_err; 240 241 vport_id = (u8)RESC_START(p_hwfn, QED_VPORT); 242 243 /* First init rate limited queues */ 244 for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) { 245 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++; 246 qm_info->qm_pq_params[curr_queue].tc_id = 247 p_hwfn->hw_info.non_offload_tc; 248 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 249 qm_info->qm_pq_params[curr_queue].rl_valid = 1; 250 } 251 252 /* First init per-TC PQs */ 253 for (i = 0; i < multi_cos_tcs; i++) { 254 struct init_qm_pq_params *params = 255 &qm_info->qm_pq_params[curr_queue++]; 256 257 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE || 258 p_hwfn->hw_info.personality == QED_PCI_ETH) { 259 params->vport_id = vport_id; 260 params->tc_id = p_hwfn->hw_info.non_offload_tc; 261 params->wrr_group = 1; 262 } else { 263 params->vport_id = vport_id; 264 params->tc_id = p_hwfn->hw_info.offload_tc; 265 params->wrr_group = 1; 266 } 267 } 268 269 /* Then init pure-LB PQ */ 270 qm_info->pure_lb_pq = curr_queue; 271 qm_info->qm_pq_params[curr_queue].vport_id = 272 (u8) RESC_START(p_hwfn, QED_VPORT); 273 qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC; 274 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 275 curr_queue++; 276 277 qm_info->offload_pq = 0; 278 if (init_rdma_offload_pq) { 279 qm_info->offload_pq = curr_queue; 280 qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 281 qm_info->qm_pq_params[curr_queue].tc_id = 282 p_hwfn->hw_info.offload_tc; 283 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 284 curr_queue++; 285 } 286 287 if (init_pure_ack_pq) { 288 qm_info->pure_ack_pq = curr_queue; 289 qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 290 qm_info->qm_pq_params[curr_queue].tc_id = 291 p_hwfn->hw_info.offload_tc; 292 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 293 curr_queue++; 294 } 295 296 if (init_ooo_pq) { 297 qm_info->ooo_pq = curr_queue; 298 qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 299 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC; 300 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 301 curr_queue++; 302 } 303 304 /* Then init per-VF PQs */ 305 vf_offset = curr_queue; 306 for (i = 0; i < num_vfs; i++) { 307 /* First vport is used by the PF */ 308 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1; 309 qm_info->qm_pq_params[curr_queue].tc_id = 310 p_hwfn->hw_info.non_offload_tc; 311 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 312 qm_info->qm_pq_params[curr_queue].rl_valid = 1; 313 curr_queue++; 314 } 315 316 qm_info->vf_queues_offset = vf_offset; 317 qm_info->num_pqs = num_pqs; 318 qm_info->num_vports = num_vports; 319 320 /* Initialize qm port parameters */ 321 num_ports = p_hwfn->cdev->num_ports_in_engines; 322 for (i = 0; i < num_ports; i++) { 323 p_qm_port = &qm_info->qm_port_params[i]; 324 p_qm_port->active = 1; 325 if (num_ports == 4) 326 p_qm_port->active_phys_tcs = 0x7; 327 else 328 p_qm_port->active_phys_tcs = 0x9f; 329 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports; 330 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports; 331 } 332 333 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS; 334 335 qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ); 336 337 qm_info->num_vf_pqs = num_vfs; 338 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT); 339 340 for (i = 0; i < qm_info->num_vports; i++) 341 qm_info->qm_vport_params[i].vport_wfq = 1; 342 343 qm_info->vport_rl_en = 1; 344 qm_info->vport_wfq_en = 1; 345 qm_info->pf_rl = pf_rl; 346 qm_info->pf_wfq = pf_wfq; 347 348 return 0; 349 350 alloc_err: 351 qed_qm_info_free(p_hwfn); 352 return -ENOMEM; 353 } 354 355 /* This function reconfigures the QM pf on the fly. 356 * For this purpose we: 357 * 1. reconfigure the QM database 358 * 2. set new values to runtime arrat 359 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM 360 * 4. activate init tool in QM_PF stage 361 * 5. send an sdm_qm_cmd through rbc interface to release the QM 362 */ 363 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 364 { 365 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 366 bool b_rc; 367 int rc; 368 369 /* qm_info is allocated in qed_init_qm_info() which is already called 370 * from qed_resc_alloc() or previous call of qed_qm_reconf(). 371 * The allocated size may change each init, so we free it before next 372 * allocation. 373 */ 374 qed_qm_info_free(p_hwfn); 375 376 /* initialize qed's qm data structure */ 377 rc = qed_init_qm_info(p_hwfn, false); 378 if (rc) 379 return rc; 380 381 /* stop PF's qm queues */ 382 spin_lock_bh(&qm_lock); 383 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true, 384 qm_info->start_pq, qm_info->num_pqs); 385 spin_unlock_bh(&qm_lock); 386 if (!b_rc) 387 return -EINVAL; 388 389 /* clear the QM_PF runtime phase leftovers from previous init */ 390 qed_init_clear_rt_data(p_hwfn); 391 392 /* prepare QM portion of runtime array */ 393 qed_qm_init_pf(p_hwfn); 394 395 /* activate init tool on runtime array */ 396 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id, 397 p_hwfn->hw_info.hw_mode); 398 if (rc) 399 return rc; 400 401 /* start PF's qm queues */ 402 spin_lock_bh(&qm_lock); 403 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true, 404 qm_info->start_pq, qm_info->num_pqs); 405 spin_unlock_bh(&qm_lock); 406 if (!b_rc) 407 return -EINVAL; 408 409 return 0; 410 } 411 412 int qed_resc_alloc(struct qed_dev *cdev) 413 { 414 #ifdef CONFIG_QED_LL2 415 struct qed_ll2_info *p_ll2_info; 416 #endif 417 struct qed_consq *p_consq; 418 struct qed_eq *p_eq; 419 int i, rc = 0; 420 421 if (IS_VF(cdev)) 422 return rc; 423 424 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL); 425 if (!cdev->fw_data) 426 return -ENOMEM; 427 428 /* Allocate Memory for the Queue->CID mapping */ 429 for_each_hwfn(cdev, i) { 430 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 431 int tx_size = sizeof(struct qed_hw_cid_data) * 432 RESC_NUM(p_hwfn, QED_L2_QUEUE); 433 int rx_size = sizeof(struct qed_hw_cid_data) * 434 RESC_NUM(p_hwfn, QED_L2_QUEUE); 435 436 p_hwfn->p_tx_cids = kzalloc(tx_size, GFP_KERNEL); 437 if (!p_hwfn->p_tx_cids) 438 goto alloc_no_mem; 439 440 p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL); 441 if (!p_hwfn->p_rx_cids) 442 goto alloc_no_mem; 443 } 444 445 for_each_hwfn(cdev, i) { 446 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 447 u32 n_eqes, num_cons; 448 449 /* First allocate the context manager structure */ 450 rc = qed_cxt_mngr_alloc(p_hwfn); 451 if (rc) 452 goto alloc_err; 453 454 /* Set the HW cid/tid numbers (in the contest manager) 455 * Must be done prior to any further computations. 456 */ 457 rc = qed_cxt_set_pf_params(p_hwfn); 458 if (rc) 459 goto alloc_err; 460 461 /* Prepare and process QM requirements */ 462 rc = qed_init_qm_info(p_hwfn, true); 463 if (rc) 464 goto alloc_err; 465 466 /* Compute the ILT client partition */ 467 rc = qed_cxt_cfg_ilt_compute(p_hwfn); 468 if (rc) 469 goto alloc_err; 470 471 /* CID map / ILT shadow table / T2 472 * The talbes sizes are determined by the computations above 473 */ 474 rc = qed_cxt_tables_alloc(p_hwfn); 475 if (rc) 476 goto alloc_err; 477 478 /* SPQ, must follow ILT because initializes SPQ context */ 479 rc = qed_spq_alloc(p_hwfn); 480 if (rc) 481 goto alloc_err; 482 483 /* SP status block allocation */ 484 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn, 485 RESERVED_PTT_DPC); 486 487 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt); 488 if (rc) 489 goto alloc_err; 490 491 rc = qed_iov_alloc(p_hwfn); 492 if (rc) 493 goto alloc_err; 494 495 /* EQ */ 496 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain); 497 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) { 498 num_cons = qed_cxt_get_proto_cid_count(p_hwfn, 499 PROTOCOLID_ROCE, 500 NULL) * 2; 501 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB; 502 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 503 num_cons = 504 qed_cxt_get_proto_cid_count(p_hwfn, 505 PROTOCOLID_ISCSI, 506 NULL); 507 n_eqes += 2 * num_cons; 508 } 509 510 if (n_eqes > 0xFFFF) { 511 DP_ERR(p_hwfn, 512 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n", 513 n_eqes, 0xFFFF); 514 rc = -EINVAL; 515 goto alloc_err; 516 } 517 518 p_eq = qed_eq_alloc(p_hwfn, (u16) n_eqes); 519 if (!p_eq) 520 goto alloc_no_mem; 521 p_hwfn->p_eq = p_eq; 522 523 p_consq = qed_consq_alloc(p_hwfn); 524 if (!p_consq) 525 goto alloc_no_mem; 526 p_hwfn->p_consq = p_consq; 527 528 #ifdef CONFIG_QED_LL2 529 if (p_hwfn->using_ll2) { 530 p_ll2_info = qed_ll2_alloc(p_hwfn); 531 if (!p_ll2_info) 532 goto alloc_no_mem; 533 p_hwfn->p_ll2_info = p_ll2_info; 534 } 535 #endif 536 537 /* DMA info initialization */ 538 rc = qed_dmae_info_alloc(p_hwfn); 539 if (rc) 540 goto alloc_err; 541 542 /* DCBX initialization */ 543 rc = qed_dcbx_info_alloc(p_hwfn); 544 if (rc) 545 goto alloc_err; 546 } 547 548 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL); 549 if (!cdev->reset_stats) 550 goto alloc_no_mem; 551 552 return 0; 553 554 alloc_no_mem: 555 rc = -ENOMEM; 556 alloc_err: 557 qed_resc_free(cdev); 558 return rc; 559 } 560 561 void qed_resc_setup(struct qed_dev *cdev) 562 { 563 int i; 564 565 if (IS_VF(cdev)) 566 return; 567 568 for_each_hwfn(cdev, i) { 569 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 570 571 qed_cxt_mngr_setup(p_hwfn); 572 qed_spq_setup(p_hwfn); 573 qed_eq_setup(p_hwfn, p_hwfn->p_eq); 574 qed_consq_setup(p_hwfn, p_hwfn->p_consq); 575 576 /* Read shadow of current MFW mailbox */ 577 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); 578 memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 579 p_hwfn->mcp_info->mfw_mb_cur, 580 p_hwfn->mcp_info->mfw_mb_length); 581 582 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt); 583 584 qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt); 585 #ifdef CONFIG_QED_LL2 586 if (p_hwfn->using_ll2) 587 qed_ll2_setup(p_hwfn, p_hwfn->p_ll2_info); 588 #endif 589 } 590 } 591 592 #define FINAL_CLEANUP_POLL_CNT (100) 593 #define FINAL_CLEANUP_POLL_TIME (10) 594 int qed_final_cleanup(struct qed_hwfn *p_hwfn, 595 struct qed_ptt *p_ptt, u16 id, bool is_vf) 596 { 597 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; 598 int rc = -EBUSY; 599 600 addr = GTT_BAR0_MAP_REG_USDM_RAM + 601 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id); 602 603 if (is_vf) 604 id += 0x10; 605 606 command |= X_FINAL_CLEANUP_AGG_INT << 607 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; 608 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; 609 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; 610 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; 611 612 /* Make sure notification is not set before initiating final cleanup */ 613 if (REG_RD(p_hwfn, addr)) { 614 DP_NOTICE(p_hwfn, 615 "Unexpected; Found final cleanup notification before initiating final cleanup\n"); 616 REG_WR(p_hwfn, addr, 0); 617 } 618 619 DP_VERBOSE(p_hwfn, QED_MSG_IOV, 620 "Sending final cleanup for PFVF[%d] [Command %08x\n]", 621 id, command); 622 623 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command); 624 625 /* Poll until completion */ 626 while (!REG_RD(p_hwfn, addr) && count--) 627 msleep(FINAL_CLEANUP_POLL_TIME); 628 629 if (REG_RD(p_hwfn, addr)) 630 rc = 0; 631 else 632 DP_NOTICE(p_hwfn, 633 "Failed to receive FW final cleanup notification\n"); 634 635 /* Cleanup afterwards */ 636 REG_WR(p_hwfn, addr, 0); 637 638 return rc; 639 } 640 641 static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn) 642 { 643 int hw_mode = 0; 644 645 hw_mode = (1 << MODE_BB_B0); 646 647 switch (p_hwfn->cdev->num_ports_in_engines) { 648 case 1: 649 hw_mode |= 1 << MODE_PORTS_PER_ENG_1; 650 break; 651 case 2: 652 hw_mode |= 1 << MODE_PORTS_PER_ENG_2; 653 break; 654 case 4: 655 hw_mode |= 1 << MODE_PORTS_PER_ENG_4; 656 break; 657 default: 658 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n", 659 p_hwfn->cdev->num_ports_in_engines); 660 return; 661 } 662 663 switch (p_hwfn->cdev->mf_mode) { 664 case QED_MF_DEFAULT: 665 case QED_MF_NPAR: 666 hw_mode |= 1 << MODE_MF_SI; 667 break; 668 case QED_MF_OVLAN: 669 hw_mode |= 1 << MODE_MF_SD; 670 break; 671 default: 672 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n"); 673 hw_mode |= 1 << MODE_MF_SI; 674 } 675 676 hw_mode |= 1 << MODE_ASIC; 677 678 if (p_hwfn->cdev->num_hwfns > 1) 679 hw_mode |= 1 << MODE_100G; 680 681 p_hwfn->hw_info.hw_mode = hw_mode; 682 683 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP), 684 "Configuring function for hw_mode: 0x%08x\n", 685 p_hwfn->hw_info.hw_mode); 686 } 687 688 /* Init run time data for all PFs on an engine. */ 689 static void qed_init_cau_rt_data(struct qed_dev *cdev) 690 { 691 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; 692 int i, sb_id; 693 694 for_each_hwfn(cdev, i) { 695 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 696 struct qed_igu_info *p_igu_info; 697 struct qed_igu_block *p_block; 698 struct cau_sb_entry sb_entry; 699 700 p_igu_info = p_hwfn->hw_info.p_igu_info; 701 702 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev); 703 sb_id++) { 704 p_block = &p_igu_info->igu_map.igu_blocks[sb_id]; 705 if (!p_block->is_pf) 706 continue; 707 708 qed_init_cau_sb_entry(p_hwfn, &sb_entry, 709 p_block->function_id, 0, 0); 710 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry); 711 } 712 } 713 } 714 715 static int qed_hw_init_common(struct qed_hwfn *p_hwfn, 716 struct qed_ptt *p_ptt, int hw_mode) 717 { 718 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 719 struct qed_qm_common_rt_init_params params; 720 struct qed_dev *cdev = p_hwfn->cdev; 721 u16 num_pfs, pf_id; 722 u32 concrete_fid; 723 int rc = 0; 724 u8 vf_id; 725 726 qed_init_cau_rt_data(cdev); 727 728 /* Program GTT windows */ 729 qed_gtt_init(p_hwfn); 730 731 if (p_hwfn->mcp_info) { 732 if (p_hwfn->mcp_info->func_info.bandwidth_max) 733 qm_info->pf_rl_en = 1; 734 if (p_hwfn->mcp_info->func_info.bandwidth_min) 735 qm_info->pf_wfq_en = 1; 736 } 737 738 memset(¶ms, 0, sizeof(params)); 739 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines; 740 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; 741 params.pf_rl_en = qm_info->pf_rl_en; 742 params.pf_wfq_en = qm_info->pf_wfq_en; 743 params.vport_rl_en = qm_info->vport_rl_en; 744 params.vport_wfq_en = qm_info->vport_wfq_en; 745 params.port_params = qm_info->qm_port_params; 746 747 qed_qm_common_rt_init(p_hwfn, ¶ms); 748 749 qed_cxt_hw_init_common(p_hwfn); 750 751 /* Close gate from NIG to BRB/Storm; By default they are open, but 752 * we close them to prevent NIG from passing data to reset blocks. 753 * Should have been done in the ENGINE phase, but init-tool lacks 754 * proper port-pretend capabilities. 755 */ 756 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); 757 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); 758 qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1); 759 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); 760 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); 761 qed_port_unpretend(p_hwfn, p_ptt); 762 763 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode); 764 if (rc) 765 return rc; 766 767 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); 768 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); 769 770 if (QED_IS_BB(p_hwfn->cdev)) { 771 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev); 772 for (pf_id = 0; pf_id < num_pfs; pf_id++) { 773 qed_fid_pretend(p_hwfn, p_ptt, pf_id); 774 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 775 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 776 } 777 /* pretend to original PF */ 778 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 779 } 780 781 for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) { 782 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id); 783 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid); 784 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1); 785 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0); 786 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1); 787 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0); 788 } 789 /* pretend to original PF */ 790 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 791 792 return rc; 793 } 794 795 static int 796 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn, 797 struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus) 798 { 799 u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size; 800 u32 dpi_bit_shift, dpi_count; 801 u32 min_dpis; 802 803 /* Calculate DPI size */ 804 dpi_page_size_1 = QED_WID_SIZE * n_cpus; 805 dpi_page_size_2 = max_t(u32, QED_WID_SIZE, PAGE_SIZE); 806 dpi_page_size = max_t(u32, dpi_page_size_1, dpi_page_size_2); 807 dpi_page_size = roundup_pow_of_two(dpi_page_size); 808 dpi_bit_shift = ilog2(dpi_page_size / 4096); 809 810 dpi_count = pwm_region_size / dpi_page_size; 811 812 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis; 813 min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis); 814 815 p_hwfn->dpi_size = dpi_page_size; 816 p_hwfn->dpi_count = dpi_count; 817 818 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift); 819 820 if (dpi_count < min_dpis) 821 return -EINVAL; 822 823 return 0; 824 } 825 826 enum QED_ROCE_EDPM_MODE { 827 QED_ROCE_EDPM_MODE_ENABLE = 0, 828 QED_ROCE_EDPM_MODE_FORCE_ON = 1, 829 QED_ROCE_EDPM_MODE_DISABLE = 2, 830 }; 831 832 static int 833 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 834 { 835 u32 pwm_regsize, norm_regsize; 836 u32 non_pwm_conn, min_addr_reg1; 837 u32 db_bar_size, n_cpus; 838 u32 roce_edpm_mode; 839 u32 pf_dems_shift; 840 int rc = 0; 841 u8 cond; 842 843 db_bar_size = qed_hw_bar_size(p_hwfn, BAR_ID_1); 844 if (p_hwfn->cdev->num_hwfns > 1) 845 db_bar_size /= 2; 846 847 /* Calculate doorbell regions */ 848 non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) + 849 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE, 850 NULL) + 851 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, 852 NULL); 853 norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, 4096); 854 min_addr_reg1 = norm_regsize / 4096; 855 pwm_regsize = db_bar_size - norm_regsize; 856 857 /* Check that the normal and PWM sizes are valid */ 858 if (db_bar_size < norm_regsize) { 859 DP_ERR(p_hwfn->cdev, 860 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n", 861 db_bar_size, norm_regsize); 862 return -EINVAL; 863 } 864 865 if (pwm_regsize < QED_MIN_PWM_REGION) { 866 DP_ERR(p_hwfn->cdev, 867 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n", 868 pwm_regsize, 869 QED_MIN_PWM_REGION, db_bar_size, norm_regsize); 870 return -EINVAL; 871 } 872 873 /* Calculate number of DPIs */ 874 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode; 875 if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) || 876 ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) { 877 /* Either EDPM is mandatory, or we are attempting to allocate a 878 * WID per CPU. 879 */ 880 n_cpus = num_active_cpus(); 881 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 882 } 883 884 cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) || 885 (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE); 886 if (cond || p_hwfn->dcbx_no_edpm) { 887 /* Either EDPM is disabled from user configuration, or it is 888 * disabled via DCBx, or it is not mandatory and we failed to 889 * allocated a WID per CPU. 890 */ 891 n_cpus = 1; 892 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 893 894 if (cond) 895 qed_rdma_dpm_bar(p_hwfn, p_ptt); 896 } 897 898 DP_INFO(p_hwfn, 899 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n", 900 norm_regsize, 901 pwm_regsize, 902 p_hwfn->dpi_size, 903 p_hwfn->dpi_count, 904 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ? 905 "disabled" : "enabled"); 906 907 if (rc) { 908 DP_ERR(p_hwfn, 909 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n", 910 p_hwfn->dpi_count, 911 p_hwfn->pf_params.rdma_pf_params.min_dpis); 912 return -EINVAL; 913 } 914 915 p_hwfn->dpi_start_offset = norm_regsize; 916 917 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */ 918 pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4); 919 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift); 920 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1); 921 922 return 0; 923 } 924 925 static int qed_hw_init_port(struct qed_hwfn *p_hwfn, 926 struct qed_ptt *p_ptt, int hw_mode) 927 { 928 return qed_init_run(p_hwfn, p_ptt, PHASE_PORT, 929 p_hwfn->port_id, hw_mode); 930 } 931 932 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, 933 struct qed_ptt *p_ptt, 934 struct qed_tunn_start_params *p_tunn, 935 int hw_mode, 936 bool b_hw_start, 937 enum qed_int_mode int_mode, 938 bool allow_npar_tx_switch) 939 { 940 u8 rel_pf_id = p_hwfn->rel_pf_id; 941 int rc = 0; 942 943 if (p_hwfn->mcp_info) { 944 struct qed_mcp_function_info *p_info; 945 946 p_info = &p_hwfn->mcp_info->func_info; 947 if (p_info->bandwidth_min) 948 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; 949 950 /* Update rate limit once we'll actually have a link */ 951 p_hwfn->qm_info.pf_rl = 100000; 952 } 953 954 qed_cxt_hw_init_pf(p_hwfn); 955 956 qed_int_igu_init_rt(p_hwfn); 957 958 /* Set VLAN in NIG if needed */ 959 if (hw_mode & BIT(MODE_MF_SD)) { 960 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n"); 961 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); 962 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, 963 p_hwfn->hw_info.ovlan); 964 } 965 966 /* Enable classification by MAC if needed */ 967 if (hw_mode & BIT(MODE_MF_SI)) { 968 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 969 "Configuring TAGMAC_CLS_TYPE\n"); 970 STORE_RT_REG(p_hwfn, 971 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1); 972 } 973 974 /* Protocl Configuration */ 975 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 976 (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0); 977 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0); 978 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); 979 980 /* Cleanup chip from previous driver if such remains exist */ 981 rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false); 982 if (rc) 983 return rc; 984 985 /* PF Init sequence */ 986 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); 987 if (rc) 988 return rc; 989 990 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ 991 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); 992 if (rc) 993 return rc; 994 995 /* Pure runtime initializations - directly to the HW */ 996 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); 997 998 rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt); 999 if (rc) 1000 return rc; 1001 1002 if (b_hw_start) { 1003 /* enable interrupts */ 1004 qed_int_igu_enable(p_hwfn, p_ptt, int_mode); 1005 1006 /* send function start command */ 1007 rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode, 1008 allow_npar_tx_switch); 1009 if (rc) 1010 DP_NOTICE(p_hwfn, "Function start ramrod failed\n"); 1011 } 1012 return rc; 1013 } 1014 1015 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn, 1016 struct qed_ptt *p_ptt, 1017 u8 enable) 1018 { 1019 u32 delay_idx = 0, val, set_val = enable ? 1 : 0; 1020 1021 /* Change PF in PXP */ 1022 qed_wr(p_hwfn, p_ptt, 1023 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); 1024 1025 /* wait until value is set - try for 1 second every 50us */ 1026 for (delay_idx = 0; delay_idx < 20000; delay_idx++) { 1027 val = qed_rd(p_hwfn, p_ptt, 1028 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1029 if (val == set_val) 1030 break; 1031 1032 usleep_range(50, 60); 1033 } 1034 1035 if (val != set_val) { 1036 DP_NOTICE(p_hwfn, 1037 "PFID_ENABLE_MASTER wasn't changed after a second\n"); 1038 return -EAGAIN; 1039 } 1040 1041 return 0; 1042 } 1043 1044 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn, 1045 struct qed_ptt *p_main_ptt) 1046 { 1047 /* Read shadow of current MFW mailbox */ 1048 qed_mcp_read_mb(p_hwfn, p_main_ptt); 1049 memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 1050 p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length); 1051 } 1052 1053 int qed_hw_init(struct qed_dev *cdev, 1054 struct qed_tunn_start_params *p_tunn, 1055 bool b_hw_start, 1056 enum qed_int_mode int_mode, 1057 bool allow_npar_tx_switch, 1058 const u8 *bin_fw_data) 1059 { 1060 u32 load_code, param, drv_mb_param; 1061 bool b_default_mtu = true; 1062 struct qed_hwfn *p_hwfn; 1063 int rc = 0, mfw_rc, i; 1064 1065 if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 1066 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 1067 return -EINVAL; 1068 } 1069 1070 if (IS_PF(cdev)) { 1071 rc = qed_init_fw_data(cdev, bin_fw_data); 1072 if (rc) 1073 return rc; 1074 } 1075 1076 for_each_hwfn(cdev, i) { 1077 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1078 1079 /* If management didn't provide a default, set one of our own */ 1080 if (!p_hwfn->hw_info.mtu) { 1081 p_hwfn->hw_info.mtu = 1500; 1082 b_default_mtu = false; 1083 } 1084 1085 if (IS_VF(cdev)) { 1086 p_hwfn->b_int_enabled = 1; 1087 continue; 1088 } 1089 1090 /* Enable DMAE in PXP */ 1091 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true); 1092 1093 qed_calc_hw_mode(p_hwfn); 1094 1095 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code); 1096 if (rc) { 1097 DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n"); 1098 return rc; 1099 } 1100 1101 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); 1102 1103 DP_VERBOSE(p_hwfn, QED_MSG_SP, 1104 "Load request was sent. Resp:0x%x, Load code: 0x%x\n", 1105 rc, load_code); 1106 1107 p_hwfn->first_on_engine = (load_code == 1108 FW_MSG_CODE_DRV_LOAD_ENGINE); 1109 1110 switch (load_code) { 1111 case FW_MSG_CODE_DRV_LOAD_ENGINE: 1112 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, 1113 p_hwfn->hw_info.hw_mode); 1114 if (rc) 1115 break; 1116 /* Fall into */ 1117 case FW_MSG_CODE_DRV_LOAD_PORT: 1118 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, 1119 p_hwfn->hw_info.hw_mode); 1120 if (rc) 1121 break; 1122 1123 /* Fall into */ 1124 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 1125 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, 1126 p_tunn, p_hwfn->hw_info.hw_mode, 1127 b_hw_start, int_mode, 1128 allow_npar_tx_switch); 1129 break; 1130 default: 1131 rc = -EINVAL; 1132 break; 1133 } 1134 1135 if (rc) 1136 DP_NOTICE(p_hwfn, 1137 "init phase failed for loadcode 0x%x (rc %d)\n", 1138 load_code, rc); 1139 1140 /* ACK mfw regardless of success or failure of initialization */ 1141 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1142 DRV_MSG_CODE_LOAD_DONE, 1143 0, &load_code, ¶m); 1144 if (rc) 1145 return rc; 1146 if (mfw_rc) { 1147 DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n"); 1148 return mfw_rc; 1149 } 1150 1151 /* send DCBX attention request command */ 1152 DP_VERBOSE(p_hwfn, 1153 QED_MSG_DCB, 1154 "sending phony dcbx set command to trigger DCBx attention handling\n"); 1155 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1156 DRV_MSG_CODE_SET_DCBX, 1157 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, 1158 &load_code, ¶m); 1159 if (mfw_rc) { 1160 DP_NOTICE(p_hwfn, 1161 "Failed to send DCBX attention request\n"); 1162 return mfw_rc; 1163 } 1164 1165 p_hwfn->hw_init_done = true; 1166 } 1167 1168 if (IS_PF(cdev)) { 1169 p_hwfn = QED_LEADING_HWFN(cdev); 1170 drv_mb_param = (FW_MAJOR_VERSION << 24) | 1171 (FW_MINOR_VERSION << 16) | 1172 (FW_REVISION_VERSION << 8) | 1173 (FW_ENGINEERING_VERSION); 1174 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1175 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER, 1176 drv_mb_param, &load_code, ¶m); 1177 if (rc) 1178 DP_INFO(p_hwfn, "Failed to update firmware version\n"); 1179 1180 if (!b_default_mtu) { 1181 rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt, 1182 p_hwfn->hw_info.mtu); 1183 if (rc) 1184 DP_INFO(p_hwfn, 1185 "Failed to update default mtu\n"); 1186 } 1187 1188 rc = qed_mcp_ov_update_driver_state(p_hwfn, 1189 p_hwfn->p_main_ptt, 1190 QED_OV_DRIVER_STATE_DISABLED); 1191 if (rc) 1192 DP_INFO(p_hwfn, "Failed to update driver state\n"); 1193 1194 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt, 1195 QED_OV_ESWITCH_VEB); 1196 if (rc) 1197 DP_INFO(p_hwfn, "Failed to update eswitch mode\n"); 1198 } 1199 1200 return 0; 1201 } 1202 1203 #define QED_HW_STOP_RETRY_LIMIT (10) 1204 static void qed_hw_timers_stop(struct qed_dev *cdev, 1205 struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1206 { 1207 int i; 1208 1209 /* close timers */ 1210 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); 1211 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); 1212 1213 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) { 1214 if ((!qed_rd(p_hwfn, p_ptt, 1215 TM_REG_PF_SCAN_ACTIVE_CONN)) && 1216 (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK))) 1217 break; 1218 1219 /* Dependent on number of connection/tasks, possibly 1220 * 1ms sleep is required between polls 1221 */ 1222 usleep_range(1000, 2000); 1223 } 1224 1225 if (i < QED_HW_STOP_RETRY_LIMIT) 1226 return; 1227 1228 DP_NOTICE(p_hwfn, 1229 "Timers linear scans are not over [Connection %02x Tasks %02x]\n", 1230 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN), 1231 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)); 1232 } 1233 1234 void qed_hw_timers_stop_all(struct qed_dev *cdev) 1235 { 1236 int j; 1237 1238 for_each_hwfn(cdev, j) { 1239 struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 1240 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 1241 1242 qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 1243 } 1244 } 1245 1246 int qed_hw_stop(struct qed_dev *cdev) 1247 { 1248 int rc = 0, t_rc; 1249 int j; 1250 1251 for_each_hwfn(cdev, j) { 1252 struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 1253 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 1254 1255 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n"); 1256 1257 if (IS_VF(cdev)) { 1258 qed_vf_pf_int_cleanup(p_hwfn); 1259 continue; 1260 } 1261 1262 /* mark the hw as uninitialized... */ 1263 p_hwfn->hw_init_done = false; 1264 1265 rc = qed_sp_pf_stop(p_hwfn); 1266 if (rc) 1267 DP_NOTICE(p_hwfn, 1268 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n"); 1269 1270 qed_wr(p_hwfn, p_ptt, 1271 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1272 1273 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1274 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1275 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1276 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1277 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1278 1279 qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 1280 1281 /* Disable Attention Generation */ 1282 qed_int_igu_disable_int(p_hwfn, p_ptt); 1283 1284 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); 1285 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); 1286 1287 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); 1288 1289 /* Need to wait 1ms to guarantee SBs are cleared */ 1290 usleep_range(1000, 2000); 1291 } 1292 1293 if (IS_PF(cdev)) { 1294 /* Disable DMAE in PXP - in CMT, this should only be done for 1295 * first hw-function, and only after all transactions have 1296 * stopped for all active hw-functions. 1297 */ 1298 t_rc = qed_change_pci_hwfn(&cdev->hwfns[0], 1299 cdev->hwfns[0].p_main_ptt, false); 1300 if (t_rc != 0) 1301 rc = t_rc; 1302 } 1303 1304 return rc; 1305 } 1306 1307 void qed_hw_stop_fastpath(struct qed_dev *cdev) 1308 { 1309 int j; 1310 1311 for_each_hwfn(cdev, j) { 1312 struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 1313 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 1314 1315 if (IS_VF(cdev)) { 1316 qed_vf_pf_int_cleanup(p_hwfn); 1317 continue; 1318 } 1319 1320 DP_VERBOSE(p_hwfn, 1321 NETIF_MSG_IFDOWN, "Shutting down the fastpath\n"); 1322 1323 qed_wr(p_hwfn, p_ptt, 1324 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1325 1326 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1327 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1328 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1329 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1330 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1331 1332 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); 1333 1334 /* Need to wait 1ms to guarantee SBs are cleared */ 1335 usleep_range(1000, 2000); 1336 } 1337 } 1338 1339 void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn) 1340 { 1341 if (IS_VF(p_hwfn->cdev)) 1342 return; 1343 1344 /* Re-open incoming traffic */ 1345 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1346 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); 1347 } 1348 1349 static int qed_reg_assert(struct qed_hwfn *p_hwfn, 1350 struct qed_ptt *p_ptt, u32 reg, bool expected) 1351 { 1352 u32 assert_val = qed_rd(p_hwfn, p_ptt, reg); 1353 1354 if (assert_val != expected) { 1355 DP_NOTICE(p_hwfn, "Value at address 0x%08x != 0x%08x\n", 1356 reg, expected); 1357 return -EINVAL; 1358 } 1359 1360 return 0; 1361 } 1362 1363 int qed_hw_reset(struct qed_dev *cdev) 1364 { 1365 int rc = 0; 1366 u32 unload_resp, unload_param; 1367 u32 wol_param; 1368 int i; 1369 1370 switch (cdev->wol_config) { 1371 case QED_OV_WOL_DISABLED: 1372 wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED; 1373 break; 1374 case QED_OV_WOL_ENABLED: 1375 wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED; 1376 break; 1377 default: 1378 DP_NOTICE(cdev, 1379 "Unknown WoL configuration %02x\n", cdev->wol_config); 1380 /* Fallthrough */ 1381 case QED_OV_WOL_DEFAULT: 1382 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP; 1383 } 1384 1385 for_each_hwfn(cdev, i) { 1386 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1387 1388 if (IS_VF(cdev)) { 1389 rc = qed_vf_pf_reset(p_hwfn); 1390 if (rc) 1391 return rc; 1392 continue; 1393 } 1394 1395 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n"); 1396 1397 /* Check for incorrect states */ 1398 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt, 1399 QM_REG_USG_CNT_PF_TX, 0); 1400 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt, 1401 QM_REG_USG_CNT_PF_OTHER, 0); 1402 1403 /* Disable PF in HW blocks */ 1404 qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0); 1405 qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0); 1406 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1407 TCFC_REG_STRONG_ENABLE_PF, 0); 1408 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1409 CCFC_REG_STRONG_ENABLE_PF, 0); 1410 1411 /* Send unload command to MCP */ 1412 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1413 DRV_MSG_CODE_UNLOAD_REQ, wol_param, 1414 &unload_resp, &unload_param); 1415 if (rc) { 1416 DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n"); 1417 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE; 1418 } 1419 1420 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1421 DRV_MSG_CODE_UNLOAD_DONE, 1422 0, &unload_resp, &unload_param); 1423 if (rc) { 1424 DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n"); 1425 return rc; 1426 } 1427 } 1428 1429 return rc; 1430 } 1431 1432 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ 1433 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn) 1434 { 1435 qed_ptt_pool_free(p_hwfn); 1436 kfree(p_hwfn->hw_info.p_igu_info); 1437 } 1438 1439 /* Setup bar access */ 1440 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn) 1441 { 1442 /* clear indirect access */ 1443 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0); 1444 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0); 1445 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0); 1446 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0); 1447 1448 /* Clean Previous errors if such exist */ 1449 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1450 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id); 1451 1452 /* enable internal target-read */ 1453 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1454 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1455 } 1456 1457 static void get_function_id(struct qed_hwfn *p_hwfn) 1458 { 1459 /* ME Register */ 1460 p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn, 1461 PXP_PF_ME_OPAQUE_ADDR); 1462 1463 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); 1464 1465 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; 1466 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 1467 PXP_CONCRETE_FID_PFID); 1468 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 1469 PXP_CONCRETE_FID_PORT); 1470 1471 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 1472 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n", 1473 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid); 1474 } 1475 1476 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn) 1477 { 1478 u32 *feat_num = p_hwfn->hw_info.feat_num; 1479 struct qed_sb_cnt_info sb_cnt_info; 1480 int num_features = 1; 1481 1482 if (IS_ENABLED(CONFIG_QED_RDMA) && 1483 p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) { 1484 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide 1485 * the status blocks equally between L2 / RoCE but with 1486 * consideration as to how many l2 queues / cnqs we have. 1487 */ 1488 num_features++; 1489 1490 feat_num[QED_RDMA_CNQ] = 1491 min_t(u32, RESC_NUM(p_hwfn, QED_SB) / num_features, 1492 RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM)); 1493 } 1494 1495 feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) / 1496 num_features, 1497 RESC_NUM(p_hwfn, QED_L2_QUEUE)); 1498 1499 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); 1500 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info); 1501 feat_num[QED_VF_L2_QUE] = 1502 min_t(u32, 1503 RESC_NUM(p_hwfn, QED_L2_QUEUE) - 1504 FEAT_NUM(p_hwfn, QED_PF_L2_QUE), sb_cnt_info.sb_iov_cnt); 1505 1506 DP_VERBOSE(p_hwfn, 1507 NETIF_MSG_PROBE, 1508 "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d num_features=%d\n", 1509 (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE), 1510 (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE), 1511 (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ), 1512 RESC_NUM(p_hwfn, QED_SB), num_features); 1513 } 1514 1515 static enum resource_id_enum qed_hw_get_mfw_res_id(enum qed_resources res_id) 1516 { 1517 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID; 1518 1519 switch (res_id) { 1520 case QED_SB: 1521 mfw_res_id = RESOURCE_NUM_SB_E; 1522 break; 1523 case QED_L2_QUEUE: 1524 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E; 1525 break; 1526 case QED_VPORT: 1527 mfw_res_id = RESOURCE_NUM_VPORT_E; 1528 break; 1529 case QED_RSS_ENG: 1530 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E; 1531 break; 1532 case QED_PQ: 1533 mfw_res_id = RESOURCE_NUM_PQ_E; 1534 break; 1535 case QED_RL: 1536 mfw_res_id = RESOURCE_NUM_RL_E; 1537 break; 1538 case QED_MAC: 1539 case QED_VLAN: 1540 /* Each VFC resource can accommodate both a MAC and a VLAN */ 1541 mfw_res_id = RESOURCE_VFC_FILTER_E; 1542 break; 1543 case QED_ILT: 1544 mfw_res_id = RESOURCE_ILT_E; 1545 break; 1546 case QED_LL2_QUEUE: 1547 mfw_res_id = RESOURCE_LL2_QUEUE_E; 1548 break; 1549 case QED_RDMA_CNQ_RAM: 1550 case QED_CMDQS_CQS: 1551 /* CNQ/CMDQS are the same resource */ 1552 mfw_res_id = RESOURCE_CQS_E; 1553 break; 1554 case QED_RDMA_STATS_QUEUE: 1555 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E; 1556 break; 1557 default: 1558 break; 1559 } 1560 1561 return mfw_res_id; 1562 } 1563 1564 static u32 qed_hw_get_dflt_resc_num(struct qed_hwfn *p_hwfn, 1565 enum qed_resources res_id) 1566 { 1567 u8 num_funcs = p_hwfn->num_funcs_on_engine; 1568 struct qed_sb_cnt_info sb_cnt_info; 1569 u32 dflt_resc_num = 0; 1570 1571 switch (res_id) { 1572 case QED_SB: 1573 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); 1574 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info); 1575 dflt_resc_num = sb_cnt_info.sb_cnt; 1576 break; 1577 case QED_L2_QUEUE: 1578 dflt_resc_num = MAX_NUM_L2_QUEUES_BB / num_funcs; 1579 break; 1580 case QED_VPORT: 1581 dflt_resc_num = MAX_NUM_VPORTS_BB / num_funcs; 1582 break; 1583 case QED_RSS_ENG: 1584 dflt_resc_num = ETH_RSS_ENGINE_NUM_BB / num_funcs; 1585 break; 1586 case QED_PQ: 1587 /* The granularity of the PQs is 8 */ 1588 dflt_resc_num = MAX_QM_TX_QUEUES_BB / num_funcs; 1589 dflt_resc_num &= ~0x7; 1590 break; 1591 case QED_RL: 1592 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs; 1593 break; 1594 case QED_MAC: 1595 case QED_VLAN: 1596 /* Each VFC resource can accommodate both a MAC and a VLAN */ 1597 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs; 1598 break; 1599 case QED_ILT: 1600 dflt_resc_num = PXP_NUM_ILT_RECORDS_BB / num_funcs; 1601 break; 1602 case QED_LL2_QUEUE: 1603 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs; 1604 break; 1605 case QED_RDMA_CNQ_RAM: 1606 case QED_CMDQS_CQS: 1607 /* CNQ/CMDQS are the same resource */ 1608 dflt_resc_num = NUM_OF_CMDQS_CQS / num_funcs; 1609 break; 1610 case QED_RDMA_STATS_QUEUE: 1611 dflt_resc_num = RDMA_NUM_STATISTIC_COUNTERS_BB / num_funcs; 1612 break; 1613 default: 1614 break; 1615 } 1616 1617 return dflt_resc_num; 1618 } 1619 1620 static const char *qed_hw_get_resc_name(enum qed_resources res_id) 1621 { 1622 switch (res_id) { 1623 case QED_SB: 1624 return "SB"; 1625 case QED_L2_QUEUE: 1626 return "L2_QUEUE"; 1627 case QED_VPORT: 1628 return "VPORT"; 1629 case QED_RSS_ENG: 1630 return "RSS_ENG"; 1631 case QED_PQ: 1632 return "PQ"; 1633 case QED_RL: 1634 return "RL"; 1635 case QED_MAC: 1636 return "MAC"; 1637 case QED_VLAN: 1638 return "VLAN"; 1639 case QED_RDMA_CNQ_RAM: 1640 return "RDMA_CNQ_RAM"; 1641 case QED_ILT: 1642 return "ILT"; 1643 case QED_LL2_QUEUE: 1644 return "LL2_QUEUE"; 1645 case QED_CMDQS_CQS: 1646 return "CMDQS_CQS"; 1647 case QED_RDMA_STATS_QUEUE: 1648 return "RDMA_STATS_QUEUE"; 1649 default: 1650 return "UNKNOWN_RESOURCE"; 1651 } 1652 } 1653 1654 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn, 1655 enum qed_resources res_id) 1656 { 1657 u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param; 1658 u32 *p_resc_num, *p_resc_start; 1659 struct resource_info resc_info; 1660 int rc; 1661 1662 p_resc_num = &RESC_NUM(p_hwfn, res_id); 1663 p_resc_start = &RESC_START(p_hwfn, res_id); 1664 1665 /* Default values assumes that each function received equal share */ 1666 dflt_resc_num = qed_hw_get_dflt_resc_num(p_hwfn, res_id); 1667 if (!dflt_resc_num) { 1668 DP_ERR(p_hwfn, 1669 "Failed to get default amount for resource %d [%s]\n", 1670 res_id, qed_hw_get_resc_name(res_id)); 1671 return -EINVAL; 1672 } 1673 dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx; 1674 1675 memset(&resc_info, 0, sizeof(resc_info)); 1676 resc_info.res_id = qed_hw_get_mfw_res_id(res_id); 1677 if (resc_info.res_id == RESOURCE_NUM_INVALID) { 1678 DP_ERR(p_hwfn, 1679 "Failed to match resource %d [%s] with the MFW resources\n", 1680 res_id, qed_hw_get_resc_name(res_id)); 1681 return -EINVAL; 1682 } 1683 1684 rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info, 1685 &mcp_resp, &mcp_param); 1686 if (rc) { 1687 DP_NOTICE(p_hwfn, 1688 "MFW response failure for an allocation request for resource %d [%s]\n", 1689 res_id, qed_hw_get_resc_name(res_id)); 1690 return rc; 1691 } 1692 1693 /* Default driver values are applied in the following cases: 1694 * - The resource allocation MB command is not supported by the MFW 1695 * - There is an internal error in the MFW while processing the request 1696 * - The resource ID is unknown to the MFW 1697 */ 1698 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK && 1699 mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) { 1700 DP_NOTICE(p_hwfn, 1701 "Resource %d [%s]: No allocation info was received [mcp_resp 0x%x]. Applying default values [num %d, start %d].\n", 1702 res_id, 1703 qed_hw_get_resc_name(res_id), 1704 mcp_resp, dflt_resc_num, dflt_resc_start); 1705 *p_resc_num = dflt_resc_num; 1706 *p_resc_start = dflt_resc_start; 1707 goto out; 1708 } 1709 1710 /* Special handling for status blocks; Would be revised in future */ 1711 if (res_id == QED_SB) { 1712 resc_info.size -= 1; 1713 resc_info.offset -= p_hwfn->enabled_func_idx; 1714 } 1715 1716 *p_resc_num = resc_info.size; 1717 *p_resc_start = resc_info.offset; 1718 1719 out: 1720 /* PQs have to divide by 8 [that's the HW granularity]. 1721 * Reduce number so it would fit. 1722 */ 1723 if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) { 1724 DP_INFO(p_hwfn, 1725 "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n", 1726 *p_resc_num, 1727 (*p_resc_num) & ~0x7, 1728 *p_resc_start, (*p_resc_start) & ~0x7); 1729 *p_resc_num &= ~0x7; 1730 *p_resc_start &= ~0x7; 1731 } 1732 1733 return 0; 1734 } 1735 1736 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn) 1737 { 1738 u8 res_id; 1739 int rc; 1740 1741 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) { 1742 rc = qed_hw_set_resc_info(p_hwfn, res_id); 1743 if (rc) 1744 return rc; 1745 } 1746 1747 /* Sanity for ILT */ 1748 if ((RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB)) { 1749 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n", 1750 RESC_START(p_hwfn, QED_ILT), 1751 RESC_END(p_hwfn, QED_ILT) - 1); 1752 return -EINVAL; 1753 } 1754 1755 qed_hw_set_feat(p_hwfn); 1756 1757 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 1758 "The numbers for each resource are:\n"); 1759 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) 1760 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n", 1761 qed_hw_get_resc_name(res_id), 1762 RESC_NUM(p_hwfn, res_id), 1763 RESC_START(p_hwfn, res_id)); 1764 1765 return 0; 1766 } 1767 1768 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1769 { 1770 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg; 1771 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities; 1772 struct qed_mcp_link_params *link; 1773 1774 /* Read global nvm_cfg address */ 1775 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 1776 1777 /* Verify MCP has initialized it */ 1778 if (!nvm_cfg_addr) { 1779 DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 1780 return -EINVAL; 1781 } 1782 1783 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ 1784 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 1785 1786 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1787 offsetof(struct nvm_cfg1, glob) + 1788 offsetof(struct nvm_cfg1_glob, core_cfg); 1789 1790 core_cfg = qed_rd(p_hwfn, p_ptt, addr); 1791 1792 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> 1793 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { 1794 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G: 1795 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G; 1796 break; 1797 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G: 1798 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G; 1799 break; 1800 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G: 1801 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G; 1802 break; 1803 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F: 1804 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F; 1805 break; 1806 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E: 1807 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E; 1808 break; 1809 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G: 1810 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G; 1811 break; 1812 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G: 1813 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G; 1814 break; 1815 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G: 1816 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G; 1817 break; 1818 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G: 1819 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G; 1820 break; 1821 default: 1822 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg); 1823 break; 1824 } 1825 1826 /* Read default link configuration */ 1827 link = &p_hwfn->mcp_info->link_input; 1828 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1829 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 1830 link_temp = qed_rd(p_hwfn, p_ptt, 1831 port_cfg_addr + 1832 offsetof(struct nvm_cfg1_port, speed_cap_mask)); 1833 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; 1834 link->speed.advertised_speeds = link_temp; 1835 1836 link_temp = link->speed.advertised_speeds; 1837 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp; 1838 1839 link_temp = qed_rd(p_hwfn, p_ptt, 1840 port_cfg_addr + 1841 offsetof(struct nvm_cfg1_port, link_settings)); 1842 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> 1843 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { 1844 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: 1845 link->speed.autoneg = true; 1846 break; 1847 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: 1848 link->speed.forced_speed = 1000; 1849 break; 1850 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: 1851 link->speed.forced_speed = 10000; 1852 break; 1853 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: 1854 link->speed.forced_speed = 25000; 1855 break; 1856 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: 1857 link->speed.forced_speed = 40000; 1858 break; 1859 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: 1860 link->speed.forced_speed = 50000; 1861 break; 1862 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G: 1863 link->speed.forced_speed = 100000; 1864 break; 1865 default: 1866 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp); 1867 } 1868 1869 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK; 1870 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET; 1871 link->pause.autoneg = !!(link_temp & 1872 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); 1873 link->pause.forced_rx = !!(link_temp & 1874 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); 1875 link->pause.forced_tx = !!(link_temp & 1876 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); 1877 link->loopback_mode = 0; 1878 1879 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1880 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n", 1881 link->speed.forced_speed, link->speed.advertised_speeds, 1882 link->speed.autoneg, link->pause.autoneg); 1883 1884 /* Read Multi-function information from shmem */ 1885 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1886 offsetof(struct nvm_cfg1, glob) + 1887 offsetof(struct nvm_cfg1_glob, generic_cont0); 1888 1889 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr); 1890 1891 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> 1892 NVM_CFG1_GLOB_MF_MODE_OFFSET; 1893 1894 switch (mf_mode) { 1895 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: 1896 p_hwfn->cdev->mf_mode = QED_MF_OVLAN; 1897 break; 1898 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: 1899 p_hwfn->cdev->mf_mode = QED_MF_NPAR; 1900 break; 1901 case NVM_CFG1_GLOB_MF_MODE_DEFAULT: 1902 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT; 1903 break; 1904 } 1905 DP_INFO(p_hwfn, "Multi function mode is %08x\n", 1906 p_hwfn->cdev->mf_mode); 1907 1908 /* Read Multi-function information from shmem */ 1909 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1910 offsetof(struct nvm_cfg1, glob) + 1911 offsetof(struct nvm_cfg1_glob, device_capabilities); 1912 1913 device_capabilities = qed_rd(p_hwfn, p_ptt, addr); 1914 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) 1915 __set_bit(QED_DEV_CAP_ETH, 1916 &p_hwfn->hw_info.device_capabilities); 1917 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI) 1918 __set_bit(QED_DEV_CAP_ISCSI, 1919 &p_hwfn->hw_info.device_capabilities); 1920 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE) 1921 __set_bit(QED_DEV_CAP_ROCE, 1922 &p_hwfn->hw_info.device_capabilities); 1923 1924 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt); 1925 } 1926 1927 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1928 { 1929 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id; 1930 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask; 1931 1932 num_funcs = MAX_NUM_PFS_BB; 1933 1934 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values 1935 * in the other bits are selected. 1936 * Bits 1-15 are for functions 1-15, respectively, and their value is 1937 * '0' only for enabled functions (function 0 always exists and 1938 * enabled). 1939 * In case of CMT, only the "even" functions are enabled, and thus the 1940 * number of functions for both hwfns is learnt from the same bits. 1941 */ 1942 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE); 1943 1944 if (reg_function_hide & 0x1) { 1945 if (QED_PATH_ID(p_hwfn) && p_hwfn->cdev->num_hwfns == 1) { 1946 num_funcs = 0; 1947 eng_mask = 0xaaaa; 1948 } else { 1949 num_funcs = 1; 1950 eng_mask = 0x5554; 1951 } 1952 1953 /* Get the number of the enabled functions on the engine */ 1954 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask; 1955 while (tmp) { 1956 if (tmp & 0x1) 1957 num_funcs++; 1958 tmp >>= 0x1; 1959 } 1960 1961 /* Get the PF index within the enabled functions */ 1962 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1; 1963 tmp = reg_function_hide & eng_mask & low_pfs_mask; 1964 while (tmp) { 1965 if (tmp & 0x1) 1966 enabled_func_idx--; 1967 tmp >>= 0x1; 1968 } 1969 } 1970 1971 p_hwfn->num_funcs_on_engine = num_funcs; 1972 p_hwfn->enabled_func_idx = enabled_func_idx; 1973 1974 DP_VERBOSE(p_hwfn, 1975 NETIF_MSG_PROBE, 1976 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n", 1977 p_hwfn->rel_pf_id, 1978 p_hwfn->abs_pf_id, 1979 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine); 1980 } 1981 1982 static int 1983 qed_get_hw_info(struct qed_hwfn *p_hwfn, 1984 struct qed_ptt *p_ptt, 1985 enum qed_pci_personality personality) 1986 { 1987 u32 port_mode; 1988 int rc; 1989 1990 /* Since all information is common, only first hwfns should do this */ 1991 if (IS_LEAD_HWFN(p_hwfn)) { 1992 rc = qed_iov_hw_info(p_hwfn); 1993 if (rc) 1994 return rc; 1995 } 1996 1997 /* Read the port mode */ 1998 port_mode = qed_rd(p_hwfn, p_ptt, 1999 CNIG_REG_NW_PORT_MODE_BB_B0); 2000 2001 if (port_mode < 3) { 2002 p_hwfn->cdev->num_ports_in_engines = 1; 2003 } else if (port_mode <= 5) { 2004 p_hwfn->cdev->num_ports_in_engines = 2; 2005 } else { 2006 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n", 2007 p_hwfn->cdev->num_ports_in_engines); 2008 2009 /* Default num_ports_in_engines to something */ 2010 p_hwfn->cdev->num_ports_in_engines = 1; 2011 } 2012 2013 qed_hw_get_nvm_info(p_hwfn, p_ptt); 2014 2015 rc = qed_int_igu_read_cam(p_hwfn, p_ptt); 2016 if (rc) 2017 return rc; 2018 2019 if (qed_mcp_is_init(p_hwfn)) 2020 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr, 2021 p_hwfn->mcp_info->func_info.mac); 2022 else 2023 eth_random_addr(p_hwfn->hw_info.hw_mac_addr); 2024 2025 if (qed_mcp_is_init(p_hwfn)) { 2026 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET) 2027 p_hwfn->hw_info.ovlan = 2028 p_hwfn->mcp_info->func_info.ovlan; 2029 2030 qed_mcp_cmd_port_init(p_hwfn, p_ptt); 2031 } 2032 2033 if (qed_mcp_is_init(p_hwfn)) { 2034 enum qed_pci_personality protocol; 2035 2036 protocol = p_hwfn->mcp_info->func_info.protocol; 2037 p_hwfn->hw_info.personality = protocol; 2038 } 2039 2040 qed_get_num_funcs(p_hwfn, p_ptt); 2041 2042 if (qed_mcp_is_init(p_hwfn)) 2043 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu; 2044 2045 return qed_hw_get_resc(p_hwfn); 2046 } 2047 2048 static int qed_get_dev_info(struct qed_dev *cdev) 2049 { 2050 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2051 u32 tmp; 2052 2053 /* Read Vendor Id / Device Id */ 2054 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id); 2055 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id); 2056 2057 cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, 2058 MISCS_REG_CHIP_NUM); 2059 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, 2060 MISCS_REG_CHIP_REV); 2061 MASK_FIELD(CHIP_REV, cdev->chip_rev); 2062 2063 cdev->type = QED_DEV_TYPE_BB; 2064 /* Learn number of HW-functions */ 2065 tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt, 2066 MISCS_REG_CMT_ENABLED_FOR_PAIR); 2067 2068 if (tmp & (1 << p_hwfn->rel_pf_id)) { 2069 DP_NOTICE(cdev->hwfns, "device in CMT mode\n"); 2070 cdev->num_hwfns = 2; 2071 } else { 2072 cdev->num_hwfns = 1; 2073 } 2074 2075 cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt, 2076 MISCS_REG_CHIP_TEST_REG) >> 4; 2077 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id); 2078 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, 2079 MISCS_REG_CHIP_METAL); 2080 MASK_FIELD(CHIP_METAL, cdev->chip_metal); 2081 2082 DP_INFO(cdev->hwfns, 2083 "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n", 2084 cdev->chip_num, cdev->chip_rev, 2085 cdev->chip_bond_id, cdev->chip_metal); 2086 2087 if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) { 2088 DP_NOTICE(cdev->hwfns, 2089 "The chip type/rev (BB A0) is not supported!\n"); 2090 return -EINVAL; 2091 } 2092 2093 return 0; 2094 } 2095 2096 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn, 2097 void __iomem *p_regview, 2098 void __iomem *p_doorbells, 2099 enum qed_pci_personality personality) 2100 { 2101 int rc = 0; 2102 2103 /* Split PCI bars evenly between hwfns */ 2104 p_hwfn->regview = p_regview; 2105 p_hwfn->doorbells = p_doorbells; 2106 2107 if (IS_VF(p_hwfn->cdev)) 2108 return qed_vf_hw_prepare(p_hwfn); 2109 2110 /* Validate that chip access is feasible */ 2111 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { 2112 DP_ERR(p_hwfn, 2113 "Reading the ME register returns all Fs; Preventing further chip access\n"); 2114 return -EINVAL; 2115 } 2116 2117 get_function_id(p_hwfn); 2118 2119 /* Allocate PTT pool */ 2120 rc = qed_ptt_pool_alloc(p_hwfn); 2121 if (rc) 2122 goto err0; 2123 2124 /* Allocate the main PTT */ 2125 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); 2126 2127 /* First hwfn learns basic information, e.g., number of hwfns */ 2128 if (!p_hwfn->my_id) { 2129 rc = qed_get_dev_info(p_hwfn->cdev); 2130 if (rc) 2131 goto err1; 2132 } 2133 2134 qed_hw_hwfn_prepare(p_hwfn); 2135 2136 /* Initialize MCP structure */ 2137 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); 2138 if (rc) { 2139 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n"); 2140 goto err1; 2141 } 2142 2143 /* Read the device configuration information from the HW and SHMEM */ 2144 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality); 2145 if (rc) { 2146 DP_NOTICE(p_hwfn, "Failed to get HW information\n"); 2147 goto err2; 2148 } 2149 2150 /* Allocate the init RT array and initialize the init-ops engine */ 2151 rc = qed_init_alloc(p_hwfn); 2152 if (rc) 2153 goto err2; 2154 2155 return rc; 2156 err2: 2157 if (IS_LEAD_HWFN(p_hwfn)) 2158 qed_iov_free_hw_info(p_hwfn->cdev); 2159 qed_mcp_free(p_hwfn); 2160 err1: 2161 qed_hw_hwfn_free(p_hwfn); 2162 err0: 2163 return rc; 2164 } 2165 2166 int qed_hw_prepare(struct qed_dev *cdev, 2167 int personality) 2168 { 2169 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2170 int rc; 2171 2172 /* Store the precompiled init data ptrs */ 2173 if (IS_PF(cdev)) 2174 qed_init_iro_array(cdev); 2175 2176 /* Initialize the first hwfn - will learn number of hwfns */ 2177 rc = qed_hw_prepare_single(p_hwfn, 2178 cdev->regview, 2179 cdev->doorbells, personality); 2180 if (rc) 2181 return rc; 2182 2183 personality = p_hwfn->hw_info.personality; 2184 2185 /* Initialize the rest of the hwfns */ 2186 if (cdev->num_hwfns > 1) { 2187 void __iomem *p_regview, *p_doorbell; 2188 u8 __iomem *addr; 2189 2190 /* adjust bar offset for second engine */ 2191 addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2; 2192 p_regview = addr; 2193 2194 /* adjust doorbell bar offset for second engine */ 2195 addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2; 2196 p_doorbell = addr; 2197 2198 /* prepare second hw function */ 2199 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview, 2200 p_doorbell, personality); 2201 2202 /* in case of error, need to free the previously 2203 * initiliazed hwfn 0. 2204 */ 2205 if (rc) { 2206 if (IS_PF(cdev)) { 2207 qed_init_free(p_hwfn); 2208 qed_mcp_free(p_hwfn); 2209 qed_hw_hwfn_free(p_hwfn); 2210 } 2211 } 2212 } 2213 2214 return rc; 2215 } 2216 2217 void qed_hw_remove(struct qed_dev *cdev) 2218 { 2219 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2220 int i; 2221 2222 if (IS_PF(cdev)) 2223 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt, 2224 QED_OV_DRIVER_STATE_NOT_LOADED); 2225 2226 for_each_hwfn(cdev, i) { 2227 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2228 2229 if (IS_VF(cdev)) { 2230 qed_vf_pf_release(p_hwfn); 2231 continue; 2232 } 2233 2234 qed_init_free(p_hwfn); 2235 qed_hw_hwfn_free(p_hwfn); 2236 qed_mcp_free(p_hwfn); 2237 } 2238 2239 qed_iov_free_hw_info(cdev); 2240 } 2241 2242 static void qed_chain_free_next_ptr(struct qed_dev *cdev, 2243 struct qed_chain *p_chain) 2244 { 2245 void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL; 2246 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0; 2247 struct qed_chain_next *p_next; 2248 u32 size, i; 2249 2250 if (!p_virt) 2251 return; 2252 2253 size = p_chain->elem_size * p_chain->usable_per_page; 2254 2255 for (i = 0; i < p_chain->page_cnt; i++) { 2256 if (!p_virt) 2257 break; 2258 2259 p_next = (struct qed_chain_next *)((u8 *)p_virt + size); 2260 p_virt_next = p_next->next_virt; 2261 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys); 2262 2263 dma_free_coherent(&cdev->pdev->dev, 2264 QED_CHAIN_PAGE_SIZE, p_virt, p_phys); 2265 2266 p_virt = p_virt_next; 2267 p_phys = p_phys_next; 2268 } 2269 } 2270 2271 static void qed_chain_free_single(struct qed_dev *cdev, 2272 struct qed_chain *p_chain) 2273 { 2274 if (!p_chain->p_virt_addr) 2275 return; 2276 2277 dma_free_coherent(&cdev->pdev->dev, 2278 QED_CHAIN_PAGE_SIZE, 2279 p_chain->p_virt_addr, p_chain->p_phys_addr); 2280 } 2281 2282 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain) 2283 { 2284 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl; 2285 u32 page_cnt = p_chain->page_cnt, i, pbl_size; 2286 u8 *p_pbl_virt = p_chain->pbl.p_virt_table; 2287 2288 if (!pp_virt_addr_tbl) 2289 return; 2290 2291 if (!p_chain->pbl.p_virt_table) 2292 goto out; 2293 2294 for (i = 0; i < page_cnt; i++) { 2295 if (!pp_virt_addr_tbl[i]) 2296 break; 2297 2298 dma_free_coherent(&cdev->pdev->dev, 2299 QED_CHAIN_PAGE_SIZE, 2300 pp_virt_addr_tbl[i], 2301 *(dma_addr_t *)p_pbl_virt); 2302 2303 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 2304 } 2305 2306 pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 2307 dma_free_coherent(&cdev->pdev->dev, 2308 pbl_size, 2309 p_chain->pbl.p_virt_table, p_chain->pbl.p_phys_table); 2310 out: 2311 vfree(p_chain->pbl.pp_virt_addr_tbl); 2312 } 2313 2314 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain) 2315 { 2316 switch (p_chain->mode) { 2317 case QED_CHAIN_MODE_NEXT_PTR: 2318 qed_chain_free_next_ptr(cdev, p_chain); 2319 break; 2320 case QED_CHAIN_MODE_SINGLE: 2321 qed_chain_free_single(cdev, p_chain); 2322 break; 2323 case QED_CHAIN_MODE_PBL: 2324 qed_chain_free_pbl(cdev, p_chain); 2325 break; 2326 } 2327 } 2328 2329 static int 2330 qed_chain_alloc_sanity_check(struct qed_dev *cdev, 2331 enum qed_chain_cnt_type cnt_type, 2332 size_t elem_size, u32 page_cnt) 2333 { 2334 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt; 2335 2336 /* The actual chain size can be larger than the maximal possible value 2337 * after rounding up the requested elements number to pages, and after 2338 * taking into acount the unusuable elements (next-ptr elements). 2339 * The size of a "u16" chain can be (U16_MAX + 1) since the chain 2340 * size/capacity fields are of a u32 type. 2341 */ 2342 if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 && 2343 chain_size > 0x10000) || 2344 (cnt_type == QED_CHAIN_CNT_TYPE_U32 && 2345 chain_size > 0x100000000ULL)) { 2346 DP_NOTICE(cdev, 2347 "The actual chain size (0x%llx) is larger than the maximal possible value\n", 2348 chain_size); 2349 return -EINVAL; 2350 } 2351 2352 return 0; 2353 } 2354 2355 static int 2356 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain) 2357 { 2358 void *p_virt = NULL, *p_virt_prev = NULL; 2359 dma_addr_t p_phys = 0; 2360 u32 i; 2361 2362 for (i = 0; i < p_chain->page_cnt; i++) { 2363 p_virt = dma_alloc_coherent(&cdev->pdev->dev, 2364 QED_CHAIN_PAGE_SIZE, 2365 &p_phys, GFP_KERNEL); 2366 if (!p_virt) 2367 return -ENOMEM; 2368 2369 if (i == 0) { 2370 qed_chain_init_mem(p_chain, p_virt, p_phys); 2371 qed_chain_reset(p_chain); 2372 } else { 2373 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 2374 p_virt, p_phys); 2375 } 2376 2377 p_virt_prev = p_virt; 2378 } 2379 /* Last page's next element should point to the beginning of the 2380 * chain. 2381 */ 2382 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 2383 p_chain->p_virt_addr, 2384 p_chain->p_phys_addr); 2385 2386 return 0; 2387 } 2388 2389 static int 2390 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain) 2391 { 2392 dma_addr_t p_phys = 0; 2393 void *p_virt = NULL; 2394 2395 p_virt = dma_alloc_coherent(&cdev->pdev->dev, 2396 QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL); 2397 if (!p_virt) 2398 return -ENOMEM; 2399 2400 qed_chain_init_mem(p_chain, p_virt, p_phys); 2401 qed_chain_reset(p_chain); 2402 2403 return 0; 2404 } 2405 2406 static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain) 2407 { 2408 u32 page_cnt = p_chain->page_cnt, size, i; 2409 dma_addr_t p_phys = 0, p_pbl_phys = 0; 2410 void **pp_virt_addr_tbl = NULL; 2411 u8 *p_pbl_virt = NULL; 2412 void *p_virt = NULL; 2413 2414 size = page_cnt * sizeof(*pp_virt_addr_tbl); 2415 pp_virt_addr_tbl = vzalloc(size); 2416 if (!pp_virt_addr_tbl) 2417 return -ENOMEM; 2418 2419 /* The allocation of the PBL table is done with its full size, since it 2420 * is expected to be successive. 2421 * qed_chain_init_pbl_mem() is called even in a case of an allocation 2422 * failure, since pp_virt_addr_tbl was previously allocated, and it 2423 * should be saved to allow its freeing during the error flow. 2424 */ 2425 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 2426 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev, 2427 size, &p_pbl_phys, GFP_KERNEL); 2428 qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, 2429 pp_virt_addr_tbl); 2430 if (!p_pbl_virt) 2431 return -ENOMEM; 2432 2433 for (i = 0; i < page_cnt; i++) { 2434 p_virt = dma_alloc_coherent(&cdev->pdev->dev, 2435 QED_CHAIN_PAGE_SIZE, 2436 &p_phys, GFP_KERNEL); 2437 if (!p_virt) 2438 return -ENOMEM; 2439 2440 if (i == 0) { 2441 qed_chain_init_mem(p_chain, p_virt, p_phys); 2442 qed_chain_reset(p_chain); 2443 } 2444 2445 /* Fill the PBL table with the physical address of the page */ 2446 *(dma_addr_t *)p_pbl_virt = p_phys; 2447 /* Keep the virtual address of the page */ 2448 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt; 2449 2450 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 2451 } 2452 2453 return 0; 2454 } 2455 2456 int qed_chain_alloc(struct qed_dev *cdev, 2457 enum qed_chain_use_mode intended_use, 2458 enum qed_chain_mode mode, 2459 enum qed_chain_cnt_type cnt_type, 2460 u32 num_elems, size_t elem_size, struct qed_chain *p_chain) 2461 { 2462 u32 page_cnt; 2463 int rc = 0; 2464 2465 if (mode == QED_CHAIN_MODE_SINGLE) 2466 page_cnt = 1; 2467 else 2468 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode); 2469 2470 rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt); 2471 if (rc) { 2472 DP_NOTICE(cdev, 2473 "Cannot allocate a chain with the given arguments:\n"); 2474 DP_NOTICE(cdev, 2475 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n", 2476 intended_use, mode, cnt_type, num_elems, elem_size); 2477 return rc; 2478 } 2479 2480 qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use, 2481 mode, cnt_type); 2482 2483 switch (mode) { 2484 case QED_CHAIN_MODE_NEXT_PTR: 2485 rc = qed_chain_alloc_next_ptr(cdev, p_chain); 2486 break; 2487 case QED_CHAIN_MODE_SINGLE: 2488 rc = qed_chain_alloc_single(cdev, p_chain); 2489 break; 2490 case QED_CHAIN_MODE_PBL: 2491 rc = qed_chain_alloc_pbl(cdev, p_chain); 2492 break; 2493 } 2494 if (rc) 2495 goto nomem; 2496 2497 return 0; 2498 2499 nomem: 2500 qed_chain_free(cdev, p_chain); 2501 return rc; 2502 } 2503 2504 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id) 2505 { 2506 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) { 2507 u16 min, max; 2508 2509 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE); 2510 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE); 2511 DP_NOTICE(p_hwfn, 2512 "l2_queue id [%d] is not valid, available indices [%d - %d]\n", 2513 src_id, min, max); 2514 2515 return -EINVAL; 2516 } 2517 2518 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id; 2519 2520 return 0; 2521 } 2522 2523 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 2524 { 2525 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) { 2526 u8 min, max; 2527 2528 min = (u8)RESC_START(p_hwfn, QED_VPORT); 2529 max = min + RESC_NUM(p_hwfn, QED_VPORT); 2530 DP_NOTICE(p_hwfn, 2531 "vport id [%d] is not valid, available indices [%d - %d]\n", 2532 src_id, min, max); 2533 2534 return -EINVAL; 2535 } 2536 2537 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id; 2538 2539 return 0; 2540 } 2541 2542 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 2543 { 2544 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) { 2545 u8 min, max; 2546 2547 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG); 2548 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG); 2549 DP_NOTICE(p_hwfn, 2550 "rss_eng id [%d] is not valid, available indices [%d - %d]\n", 2551 src_id, min, max); 2552 2553 return -EINVAL; 2554 } 2555 2556 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id; 2557 2558 return 0; 2559 } 2560 2561 static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low, 2562 u8 *p_filter) 2563 { 2564 *p_high = p_filter[1] | (p_filter[0] << 8); 2565 *p_low = p_filter[5] | (p_filter[4] << 8) | 2566 (p_filter[3] << 16) | (p_filter[2] << 24); 2567 } 2568 2569 int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn, 2570 struct qed_ptt *p_ptt, u8 *p_filter) 2571 { 2572 u32 high = 0, low = 0, en; 2573 int i; 2574 2575 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 2576 return 0; 2577 2578 qed_llh_mac_to_filter(&high, &low, p_filter); 2579 2580 /* Find a free entry and utilize it */ 2581 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 2582 en = qed_rd(p_hwfn, p_ptt, 2583 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)); 2584 if (en) 2585 continue; 2586 qed_wr(p_hwfn, p_ptt, 2587 NIG_REG_LLH_FUNC_FILTER_VALUE + 2588 2 * i * sizeof(u32), low); 2589 qed_wr(p_hwfn, p_ptt, 2590 NIG_REG_LLH_FUNC_FILTER_VALUE + 2591 (2 * i + 1) * sizeof(u32), high); 2592 qed_wr(p_hwfn, p_ptt, 2593 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0); 2594 qed_wr(p_hwfn, p_ptt, 2595 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 2596 i * sizeof(u32), 0); 2597 qed_wr(p_hwfn, p_ptt, 2598 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1); 2599 break; 2600 } 2601 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 2602 DP_NOTICE(p_hwfn, 2603 "Failed to find an empty LLH filter to utilize\n"); 2604 return -EINVAL; 2605 } 2606 2607 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 2608 "mac: %pM is added at %d\n", 2609 p_filter, i); 2610 2611 return 0; 2612 } 2613 2614 void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn, 2615 struct qed_ptt *p_ptt, u8 *p_filter) 2616 { 2617 u32 high = 0, low = 0; 2618 int i; 2619 2620 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 2621 return; 2622 2623 qed_llh_mac_to_filter(&high, &low, p_filter); 2624 2625 /* Find the entry and clean it */ 2626 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 2627 if (qed_rd(p_hwfn, p_ptt, 2628 NIG_REG_LLH_FUNC_FILTER_VALUE + 2629 2 * i * sizeof(u32)) != low) 2630 continue; 2631 if (qed_rd(p_hwfn, p_ptt, 2632 NIG_REG_LLH_FUNC_FILTER_VALUE + 2633 (2 * i + 1) * sizeof(u32)) != high) 2634 continue; 2635 2636 qed_wr(p_hwfn, p_ptt, 2637 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); 2638 qed_wr(p_hwfn, p_ptt, 2639 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0); 2640 qed_wr(p_hwfn, p_ptt, 2641 NIG_REG_LLH_FUNC_FILTER_VALUE + 2642 (2 * i + 1) * sizeof(u32), 0); 2643 2644 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 2645 "mac: %pM is removed from %d\n", 2646 p_filter, i); 2647 break; 2648 } 2649 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 2650 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n"); 2651 } 2652 2653 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2654 u32 hw_addr, void *p_eth_qzone, 2655 size_t eth_qzone_size, u8 timeset) 2656 { 2657 struct coalescing_timeset *p_coal_timeset; 2658 2659 if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) { 2660 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n"); 2661 return -EINVAL; 2662 } 2663 2664 p_coal_timeset = p_eth_qzone; 2665 memset(p_coal_timeset, 0, eth_qzone_size); 2666 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset); 2667 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1); 2668 qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size); 2669 2670 return 0; 2671 } 2672 2673 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2674 u16 coalesce, u8 qid, u16 sb_id) 2675 { 2676 struct ustorm_eth_queue_zone eth_qzone; 2677 u8 timeset, timer_res; 2678 u16 fw_qid = 0; 2679 u32 address; 2680 int rc; 2681 2682 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 2683 if (coalesce <= 0x7F) { 2684 timer_res = 0; 2685 } else if (coalesce <= 0xFF) { 2686 timer_res = 1; 2687 } else if (coalesce <= 0x1FF) { 2688 timer_res = 2; 2689 } else { 2690 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 2691 return -EINVAL; 2692 } 2693 timeset = (u8)(coalesce >> timer_res); 2694 2695 rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid); 2696 if (rc) 2697 return rc; 2698 2699 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false); 2700 if (rc) 2701 goto out; 2702 2703 address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid); 2704 2705 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 2706 sizeof(struct ustorm_eth_queue_zone), timeset); 2707 if (rc) 2708 goto out; 2709 2710 p_hwfn->cdev->rx_coalesce_usecs = coalesce; 2711 out: 2712 return rc; 2713 } 2714 2715 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2716 u16 coalesce, u8 qid, u16 sb_id) 2717 { 2718 struct xstorm_eth_queue_zone eth_qzone; 2719 u8 timeset, timer_res; 2720 u16 fw_qid = 0; 2721 u32 address; 2722 int rc; 2723 2724 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 2725 if (coalesce <= 0x7F) { 2726 timer_res = 0; 2727 } else if (coalesce <= 0xFF) { 2728 timer_res = 1; 2729 } else if (coalesce <= 0x1FF) { 2730 timer_res = 2; 2731 } else { 2732 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 2733 return -EINVAL; 2734 } 2735 timeset = (u8)(coalesce >> timer_res); 2736 2737 rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid); 2738 if (rc) 2739 return rc; 2740 2741 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true); 2742 if (rc) 2743 goto out; 2744 2745 address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid); 2746 2747 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 2748 sizeof(struct xstorm_eth_queue_zone), timeset); 2749 if (rc) 2750 goto out; 2751 2752 p_hwfn->cdev->tx_coalesce_usecs = coalesce; 2753 out: 2754 return rc; 2755 } 2756 2757 /* Calculate final WFQ values for all vports and configure them. 2758 * After this configuration each vport will have 2759 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT) 2760 */ 2761 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 2762 struct qed_ptt *p_ptt, 2763 u32 min_pf_rate) 2764 { 2765 struct init_qm_vport_params *vport_params; 2766 int i; 2767 2768 vport_params = p_hwfn->qm_info.qm_vport_params; 2769 2770 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 2771 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 2772 2773 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) / 2774 min_pf_rate; 2775 qed_init_vport_wfq(p_hwfn, p_ptt, 2776 vport_params[i].first_tx_pq_id, 2777 vport_params[i].vport_wfq); 2778 } 2779 } 2780 2781 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn, 2782 u32 min_pf_rate) 2783 2784 { 2785 int i; 2786 2787 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) 2788 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1; 2789 } 2790 2791 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 2792 struct qed_ptt *p_ptt, 2793 u32 min_pf_rate) 2794 { 2795 struct init_qm_vport_params *vport_params; 2796 int i; 2797 2798 vport_params = p_hwfn->qm_info.qm_vport_params; 2799 2800 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 2801 qed_init_wfq_default_param(p_hwfn, min_pf_rate); 2802 qed_init_vport_wfq(p_hwfn, p_ptt, 2803 vport_params[i].first_tx_pq_id, 2804 vport_params[i].vport_wfq); 2805 } 2806 } 2807 2808 /* This function performs several validations for WFQ 2809 * configuration and required min rate for a given vport 2810 * 1. req_rate must be greater than one percent of min_pf_rate. 2811 * 2. req_rate should not cause other vports [not configured for WFQ explicitly] 2812 * rates to get less than one percent of min_pf_rate. 2813 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate. 2814 */ 2815 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn, 2816 u16 vport_id, u32 req_rate, u32 min_pf_rate) 2817 { 2818 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0; 2819 int non_requested_count = 0, req_count = 0, i, num_vports; 2820 2821 num_vports = p_hwfn->qm_info.num_vports; 2822 2823 /* Accounting for the vports which are configured for WFQ explicitly */ 2824 for (i = 0; i < num_vports; i++) { 2825 u32 tmp_speed; 2826 2827 if ((i != vport_id) && 2828 p_hwfn->qm_info.wfq_data[i].configured) { 2829 req_count++; 2830 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 2831 total_req_min_rate += tmp_speed; 2832 } 2833 } 2834 2835 /* Include current vport data as well */ 2836 req_count++; 2837 total_req_min_rate += req_rate; 2838 non_requested_count = num_vports - req_count; 2839 2840 if (req_rate < min_pf_rate / QED_WFQ_UNIT) { 2841 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2842 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 2843 vport_id, req_rate, min_pf_rate); 2844 return -EINVAL; 2845 } 2846 2847 if (num_vports > QED_WFQ_UNIT) { 2848 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2849 "Number of vports is greater than %d\n", 2850 QED_WFQ_UNIT); 2851 return -EINVAL; 2852 } 2853 2854 if (total_req_min_rate > min_pf_rate) { 2855 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2856 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", 2857 total_req_min_rate, min_pf_rate); 2858 return -EINVAL; 2859 } 2860 2861 total_left_rate = min_pf_rate - total_req_min_rate; 2862 2863 left_rate_per_vp = total_left_rate / non_requested_count; 2864 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) { 2865 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2866 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 2867 left_rate_per_vp, min_pf_rate); 2868 return -EINVAL; 2869 } 2870 2871 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate; 2872 p_hwfn->qm_info.wfq_data[vport_id].configured = true; 2873 2874 for (i = 0; i < num_vports; i++) { 2875 if (p_hwfn->qm_info.wfq_data[i].configured) 2876 continue; 2877 2878 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp; 2879 } 2880 2881 return 0; 2882 } 2883 2884 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn, 2885 struct qed_ptt *p_ptt, u16 vp_id, u32 rate) 2886 { 2887 struct qed_mcp_link_state *p_link; 2888 int rc = 0; 2889 2890 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output; 2891 2892 if (!p_link->min_pf_rate) { 2893 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate; 2894 p_hwfn->qm_info.wfq_data[vp_id].configured = true; 2895 return rc; 2896 } 2897 2898 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate); 2899 2900 if (!rc) 2901 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, 2902 p_link->min_pf_rate); 2903 else 2904 DP_NOTICE(p_hwfn, 2905 "Validation failed while configuring min rate\n"); 2906 2907 return rc; 2908 } 2909 2910 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn, 2911 struct qed_ptt *p_ptt, 2912 u32 min_pf_rate) 2913 { 2914 bool use_wfq = false; 2915 int rc = 0; 2916 u16 i; 2917 2918 /* Validate all pre configured vports for wfq */ 2919 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 2920 u32 rate; 2921 2922 if (!p_hwfn->qm_info.wfq_data[i].configured) 2923 continue; 2924 2925 rate = p_hwfn->qm_info.wfq_data[i].min_speed; 2926 use_wfq = true; 2927 2928 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate); 2929 if (rc) { 2930 DP_NOTICE(p_hwfn, 2931 "WFQ validation failed while configuring min rate\n"); 2932 break; 2933 } 2934 } 2935 2936 if (!rc && use_wfq) 2937 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 2938 else 2939 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 2940 2941 return rc; 2942 } 2943 2944 /* Main API for qed clients to configure vport min rate. 2945 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)] 2946 * rate - Speed in Mbps needs to be assigned to a given vport. 2947 */ 2948 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate) 2949 { 2950 int i, rc = -EINVAL; 2951 2952 /* Currently not supported; Might change in future */ 2953 if (cdev->num_hwfns > 1) { 2954 DP_NOTICE(cdev, 2955 "WFQ configuration is not supported for this device\n"); 2956 return rc; 2957 } 2958 2959 for_each_hwfn(cdev, i) { 2960 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2961 struct qed_ptt *p_ptt; 2962 2963 p_ptt = qed_ptt_acquire(p_hwfn); 2964 if (!p_ptt) 2965 return -EBUSY; 2966 2967 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate); 2968 2969 if (rc) { 2970 qed_ptt_release(p_hwfn, p_ptt); 2971 return rc; 2972 } 2973 2974 qed_ptt_release(p_hwfn, p_ptt); 2975 } 2976 2977 return rc; 2978 } 2979 2980 /* API to configure WFQ from mcp link change */ 2981 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate) 2982 { 2983 int i; 2984 2985 if (cdev->num_hwfns > 1) { 2986 DP_VERBOSE(cdev, 2987 NETIF_MSG_LINK, 2988 "WFQ configuration is not supported for this device\n"); 2989 return; 2990 } 2991 2992 for_each_hwfn(cdev, i) { 2993 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2994 2995 __qed_configure_vp_wfq_on_link_change(p_hwfn, 2996 p_hwfn->p_dpc_ptt, 2997 min_pf_rate); 2998 } 2999 } 3000 3001 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, 3002 struct qed_ptt *p_ptt, 3003 struct qed_mcp_link_state *p_link, 3004 u8 max_bw) 3005 { 3006 int rc = 0; 3007 3008 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw; 3009 3010 if (!p_link->line_speed && (max_bw != 100)) 3011 return rc; 3012 3013 p_link->speed = (p_link->line_speed * max_bw) / 100; 3014 p_hwfn->qm_info.pf_rl = p_link->speed; 3015 3016 /* Since the limiter also affects Tx-switched traffic, we don't want it 3017 * to limit such traffic in case there's no actual limit. 3018 * In that case, set limit to imaginary high boundary. 3019 */ 3020 if (max_bw == 100) 3021 p_hwfn->qm_info.pf_rl = 100000; 3022 3023 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 3024 p_hwfn->qm_info.pf_rl); 3025 3026 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 3027 "Configured MAX bandwidth to be %08x Mb/sec\n", 3028 p_link->speed); 3029 3030 return rc; 3031 } 3032 3033 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */ 3034 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw) 3035 { 3036 int i, rc = -EINVAL; 3037 3038 if (max_bw < 1 || max_bw > 100) { 3039 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n"); 3040 return rc; 3041 } 3042 3043 for_each_hwfn(cdev, i) { 3044 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 3045 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 3046 struct qed_mcp_link_state *p_link; 3047 struct qed_ptt *p_ptt; 3048 3049 p_link = &p_lead->mcp_info->link_output; 3050 3051 p_ptt = qed_ptt_acquire(p_hwfn); 3052 if (!p_ptt) 3053 return -EBUSY; 3054 3055 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, 3056 p_link, max_bw); 3057 3058 qed_ptt_release(p_hwfn, p_ptt); 3059 3060 if (rc) 3061 break; 3062 } 3063 3064 return rc; 3065 } 3066 3067 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn, 3068 struct qed_ptt *p_ptt, 3069 struct qed_mcp_link_state *p_link, 3070 u8 min_bw) 3071 { 3072 int rc = 0; 3073 3074 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw; 3075 p_hwfn->qm_info.pf_wfq = min_bw; 3076 3077 if (!p_link->line_speed) 3078 return rc; 3079 3080 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100; 3081 3082 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw); 3083 3084 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 3085 "Configured MIN bandwidth to be %d Mb/sec\n", 3086 p_link->min_pf_rate); 3087 3088 return rc; 3089 } 3090 3091 /* Main API to configure PF min bandwidth where bw range is [1-100] */ 3092 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw) 3093 { 3094 int i, rc = -EINVAL; 3095 3096 if (min_bw < 1 || min_bw > 100) { 3097 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n"); 3098 return rc; 3099 } 3100 3101 for_each_hwfn(cdev, i) { 3102 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 3103 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 3104 struct qed_mcp_link_state *p_link; 3105 struct qed_ptt *p_ptt; 3106 3107 p_link = &p_lead->mcp_info->link_output; 3108 3109 p_ptt = qed_ptt_acquire(p_hwfn); 3110 if (!p_ptt) 3111 return -EBUSY; 3112 3113 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, 3114 p_link, min_bw); 3115 if (rc) { 3116 qed_ptt_release(p_hwfn, p_ptt); 3117 return rc; 3118 } 3119 3120 if (p_link->min_pf_rate) { 3121 u32 min_rate = p_link->min_pf_rate; 3122 3123 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn, 3124 p_ptt, 3125 min_rate); 3126 } 3127 3128 qed_ptt_release(p_hwfn, p_ptt); 3129 } 3130 3131 return rc; 3132 } 3133 3134 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3135 { 3136 struct qed_mcp_link_state *p_link; 3137 3138 p_link = &p_hwfn->mcp_info->link_output; 3139 3140 if (p_link->min_pf_rate) 3141 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, 3142 p_link->min_pf_rate); 3143 3144 memset(p_hwfn->qm_info.wfq_data, 0, 3145 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports); 3146 } 3147