1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _QED_H 34 #define _QED_H 35 36 #include <linux/types.h> 37 #include <linux/io.h> 38 #include <linux/delay.h> 39 #include <linux/firmware.h> 40 #include <linux/interrupt.h> 41 #include <linux/list.h> 42 #include <linux/mutex.h> 43 #include <linux/pci.h> 44 #include <linux/slab.h> 45 #include <linux/string.h> 46 #include <linux/workqueue.h> 47 #include <linux/zlib.h> 48 #include <linux/hashtable.h> 49 #include <linux/qed/qed_if.h> 50 #include "qed_debug.h" 51 #include "qed_hsi.h" 52 53 extern const struct qed_common_ops qed_common_ops_pass; 54 #define DRV_MODULE_VERSION "8.10.10.20" 55 56 #define MAX_HWFNS_PER_DEVICE (4) 57 #define NAME_SIZE 16 58 #define VER_SIZE 16 59 60 #define QED_WFQ_UNIT 100 61 62 #define ISCSI_BDQ_ID(_port_id) (_port_id) 63 #define FCOE_BDQ_ID(_port_id) ((_port_id) + 2) 64 #define QED_WID_SIZE (1024) 65 #define QED_PF_DEMS_SIZE (4) 66 67 /* cau states */ 68 enum qed_coalescing_mode { 69 QED_COAL_MODE_DISABLE, 70 QED_COAL_MODE_ENABLE 71 }; 72 73 struct qed_eth_cb_ops; 74 struct qed_dev_info; 75 union qed_mcp_protocol_stats; 76 enum qed_mcp_protocol_type; 77 78 /* helpers */ 79 static inline u32 qed_db_addr(u32 cid, u32 DEMS) 80 { 81 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 82 (cid * QED_PF_DEMS_SIZE); 83 84 return db_addr; 85 } 86 87 static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS) 88 { 89 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 90 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); 91 92 return db_addr; 93 } 94 95 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ 96 ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \ 97 ~((1 << (p_hwfn->cdev->cache_shift)) - 1)) 98 99 #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++) 100 101 #define D_TRINE(val, cond1, cond2, true1, true2, def) \ 102 (val == (cond1) ? true1 : \ 103 (val == (cond2) ? true2 : def)) 104 105 /* forward */ 106 struct qed_ptt_pool; 107 struct qed_spq; 108 struct qed_sb_info; 109 struct qed_sb_attn_info; 110 struct qed_cxt_mngr; 111 struct qed_sb_sp_info; 112 struct qed_ll2_info; 113 struct qed_mcp_info; 114 115 struct qed_rt_data { 116 u32 *init_val; 117 bool *b_valid; 118 }; 119 120 enum qed_tunn_mode { 121 QED_MODE_L2GENEVE_TUNN, 122 QED_MODE_IPGENEVE_TUNN, 123 QED_MODE_L2GRE_TUNN, 124 QED_MODE_IPGRE_TUNN, 125 QED_MODE_VXLAN_TUNN, 126 }; 127 128 enum qed_tunn_clss { 129 QED_TUNN_CLSS_MAC_VLAN, 130 QED_TUNN_CLSS_MAC_VNI, 131 QED_TUNN_CLSS_INNER_MAC_VLAN, 132 QED_TUNN_CLSS_INNER_MAC_VNI, 133 MAX_QED_TUNN_CLSS, 134 }; 135 136 struct qed_tunn_start_params { 137 unsigned long tunn_mode; 138 u16 vxlan_udp_port; 139 u16 geneve_udp_port; 140 u8 update_vxlan_udp_port; 141 u8 update_geneve_udp_port; 142 u8 tunn_clss_vxlan; 143 u8 tunn_clss_l2geneve; 144 u8 tunn_clss_ipgeneve; 145 u8 tunn_clss_l2gre; 146 u8 tunn_clss_ipgre; 147 }; 148 149 struct qed_tunn_update_params { 150 unsigned long tunn_mode_update_mask; 151 unsigned long tunn_mode; 152 u16 vxlan_udp_port; 153 u16 geneve_udp_port; 154 u8 update_rx_pf_clss; 155 u8 update_tx_pf_clss; 156 u8 update_vxlan_udp_port; 157 u8 update_geneve_udp_port; 158 u8 tunn_clss_vxlan; 159 u8 tunn_clss_l2geneve; 160 u8 tunn_clss_ipgeneve; 161 u8 tunn_clss_l2gre; 162 u8 tunn_clss_ipgre; 163 }; 164 165 /* The PCI personality is not quite synonymous to protocol ID: 166 * 1. All personalities need CORE connections 167 * 2. The Ethernet personality may support also the RoCE protocol 168 */ 169 enum qed_pci_personality { 170 QED_PCI_ETH, 171 QED_PCI_FCOE, 172 QED_PCI_ISCSI, 173 QED_PCI_ETH_ROCE, 174 QED_PCI_DEFAULT /* default in shmem */ 175 }; 176 177 /* All VFs are symmetric, all counters are PF + all VFs */ 178 struct qed_qm_iids { 179 u32 cids; 180 u32 vf_cids; 181 u32 tids; 182 }; 183 184 /* HW / FW resources, output of features supported below, most information 185 * is received from MFW. 186 */ 187 enum qed_resources { 188 QED_SB, 189 QED_L2_QUEUE, 190 QED_VPORT, 191 QED_RSS_ENG, 192 QED_PQ, 193 QED_RL, 194 QED_MAC, 195 QED_VLAN, 196 QED_RDMA_CNQ_RAM, 197 QED_ILT, 198 QED_LL2_QUEUE, 199 QED_CMDQS_CQS, 200 QED_RDMA_STATS_QUEUE, 201 QED_MAX_RESC, 202 }; 203 204 enum QED_FEATURE { 205 QED_PF_L2_QUE, 206 QED_VF, 207 QED_RDMA_CNQ, 208 QED_VF_L2_QUE, 209 QED_FCOE_CQ, 210 QED_MAX_FEATURES, 211 }; 212 213 enum QED_PORT_MODE { 214 QED_PORT_MODE_DE_2X40G, 215 QED_PORT_MODE_DE_2X50G, 216 QED_PORT_MODE_DE_1X100G, 217 QED_PORT_MODE_DE_4X10G_F, 218 QED_PORT_MODE_DE_4X10G_E, 219 QED_PORT_MODE_DE_4X20G, 220 QED_PORT_MODE_DE_1X40G, 221 QED_PORT_MODE_DE_2X25G, 222 QED_PORT_MODE_DE_1X25G 223 }; 224 225 enum qed_dev_cap { 226 QED_DEV_CAP_ETH, 227 QED_DEV_CAP_FCOE, 228 QED_DEV_CAP_ISCSI, 229 QED_DEV_CAP_ROCE, 230 }; 231 232 enum qed_wol_support { 233 QED_WOL_SUPPORT_NONE, 234 QED_WOL_SUPPORT_PME, 235 }; 236 237 struct qed_hw_info { 238 /* PCI personality */ 239 enum qed_pci_personality personality; 240 241 /* Resource Allocation scheme results */ 242 u32 resc_start[QED_MAX_RESC]; 243 u32 resc_num[QED_MAX_RESC]; 244 u32 feat_num[QED_MAX_FEATURES]; 245 246 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) 247 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) 248 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ 249 RESC_NUM(_p_hwfn, resc)) 250 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) 251 252 u8 num_tc; 253 u8 offload_tc; 254 u8 non_offload_tc; 255 256 u32 concrete_fid; 257 u16 opaque_fid; 258 u16 ovlan; 259 u32 part_num[4]; 260 261 unsigned char hw_mac_addr[ETH_ALEN]; 262 u64 node_wwn; 263 u64 port_wwn; 264 265 u16 num_fcoe_conns; 266 267 struct qed_igu_info *p_igu_info; 268 269 u32 port_mode; 270 u32 hw_mode; 271 unsigned long device_capabilities; 272 u16 mtu; 273 274 enum qed_wol_support b_wol_support; 275 }; 276 277 /* maximun size of read/write commands (HW limit) */ 278 #define DMAE_MAX_RW_SIZE 0x2000 279 280 struct qed_dmae_info { 281 /* Mutex for synchronizing access to functions */ 282 struct mutex mutex; 283 284 u8 channel; 285 286 dma_addr_t completion_word_phys_addr; 287 288 /* The memory location where the DMAE writes the completion 289 * value when an operation is finished on this context. 290 */ 291 u32 *p_completion_word; 292 293 dma_addr_t intermediate_buffer_phys_addr; 294 295 /* An intermediate buffer for DMAE operations that use virtual 296 * addresses - data is DMA'd to/from this buffer and then 297 * memcpy'd to/from the virtual address 298 */ 299 u32 *p_intermediate_buffer; 300 301 dma_addr_t dmae_cmd_phys_addr; 302 struct dmae_cmd *p_dmae_cmd; 303 }; 304 305 struct qed_wfq_data { 306 /* when feature is configured for at least 1 vport */ 307 u32 min_speed; 308 bool configured; 309 }; 310 311 struct qed_qm_info { 312 struct init_qm_pq_params *qm_pq_params; 313 struct init_qm_vport_params *qm_vport_params; 314 struct init_qm_port_params *qm_port_params; 315 u16 start_pq; 316 u8 start_vport; 317 u8 pure_lb_pq; 318 u8 offload_pq; 319 u8 pure_ack_pq; 320 u8 ooo_pq; 321 u8 vf_queues_offset; 322 u16 num_pqs; 323 u16 num_vf_pqs; 324 u8 num_vports; 325 u8 max_phys_tcs_per_port; 326 bool pf_rl_en; 327 bool pf_wfq_en; 328 bool vport_rl_en; 329 bool vport_wfq_en; 330 u8 pf_wfq; 331 u32 pf_rl; 332 struct qed_wfq_data *wfq_data; 333 u8 num_pf_rls; 334 }; 335 336 struct storm_stats { 337 u32 address; 338 u32 len; 339 }; 340 341 struct qed_storm_stats { 342 struct storm_stats mstats; 343 struct storm_stats pstats; 344 struct storm_stats tstats; 345 struct storm_stats ustats; 346 }; 347 348 struct qed_fw_data { 349 struct fw_ver_info *fw_ver_info; 350 const u8 *modes_tree_buf; 351 union init_op *init_ops; 352 const u32 *arr_data; 353 u32 init_ops_size; 354 }; 355 356 struct qed_simd_fp_handler { 357 void *token; 358 void (*func)(void *); 359 }; 360 361 struct qed_hwfn { 362 struct qed_dev *cdev; 363 u8 my_id; /* ID inside the PF */ 364 #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) 365 u8 rel_pf_id; /* Relative to engine*/ 366 u8 abs_pf_id; 367 #define QED_PATH_ID(_p_hwfn) ((_p_hwfn)->abs_pf_id & 1) 368 u8 port_id; 369 bool b_active; 370 371 u32 dp_module; 372 u8 dp_level; 373 char name[NAME_SIZE]; 374 375 bool first_on_engine; 376 bool hw_init_done; 377 378 u8 num_funcs_on_engine; 379 u8 enabled_func_idx; 380 381 /* BAR access */ 382 void __iomem *regview; 383 void __iomem *doorbells; 384 u64 db_phys_addr; 385 unsigned long db_size; 386 387 /* PTT pool */ 388 struct qed_ptt_pool *p_ptt_pool; 389 390 /* HW info */ 391 struct qed_hw_info hw_info; 392 393 /* rt_array (for init-tool) */ 394 struct qed_rt_data rt_data; 395 396 /* SPQ */ 397 struct qed_spq *p_spq; 398 399 /* EQ */ 400 struct qed_eq *p_eq; 401 402 /* Consolidate Q*/ 403 struct qed_consq *p_consq; 404 405 /* Slow-Path definitions */ 406 struct tasklet_struct *sp_dpc; 407 bool b_sp_dpc_enabled; 408 409 struct qed_ptt *p_main_ptt; 410 struct qed_ptt *p_dpc_ptt; 411 412 struct qed_sb_sp_info *p_sp_sb; 413 struct qed_sb_attn_info *p_sb_attn; 414 415 /* Protocol related */ 416 bool using_ll2; 417 struct qed_ll2_info *p_ll2_info; 418 struct qed_ooo_info *p_ooo_info; 419 struct qed_rdma_info *p_rdma_info; 420 struct qed_iscsi_info *p_iscsi_info; 421 struct qed_fcoe_info *p_fcoe_info; 422 struct qed_pf_params pf_params; 423 424 bool b_rdma_enabled_in_prs; 425 u32 rdma_prs_search_reg; 426 427 /* Array of sb_info of all status blocks */ 428 struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD]; 429 u16 num_sbs; 430 431 struct qed_cxt_mngr *p_cxt_mngr; 432 433 /* Flag indicating whether interrupts are enabled or not*/ 434 bool b_int_enabled; 435 bool b_int_requested; 436 437 /* True if the driver requests for the link */ 438 bool b_drv_link_init; 439 440 struct qed_vf_iov *vf_iov_info; 441 struct qed_pf_iov *pf_iov_info; 442 struct qed_mcp_info *mcp_info; 443 444 struct qed_dcbx_info *p_dcbx_info; 445 446 struct qed_dmae_info dmae_info; 447 448 /* QM init */ 449 struct qed_qm_info qm_info; 450 struct qed_storm_stats storm_stats; 451 452 /* Buffer for unzipping firmware data */ 453 void *unzip_buf; 454 455 struct dbg_tools_data dbg_info; 456 457 /* PWM region specific data */ 458 u32 dpi_size; 459 u32 dpi_count; 460 461 /* This is used to calculate the doorbell address */ 462 u32 dpi_start_offset; 463 464 /* If one of the following is set then EDPM shouldn't be used */ 465 u8 dcbx_no_edpm; 466 u8 db_bar_no_edpm; 467 468 /* p_ptp_ptt is valid for leading HWFN only */ 469 struct qed_ptt *p_ptp_ptt; 470 struct qed_simd_fp_handler simd_proto_handler[64]; 471 472 #ifdef CONFIG_QED_SRIOV 473 struct workqueue_struct *iov_wq; 474 struct delayed_work iov_task; 475 unsigned long iov_task_flags; 476 #endif 477 478 struct z_stream_s *stream; 479 struct qed_roce_ll2_info *ll2; 480 }; 481 482 struct pci_params { 483 int pm_cap; 484 485 unsigned long mem_start; 486 unsigned long mem_end; 487 unsigned int irq; 488 u8 pf_num; 489 }; 490 491 struct qed_int_param { 492 u32 int_mode; 493 u8 num_vectors; 494 u8 min_msix_cnt; /* for minimal functionality */ 495 }; 496 497 struct qed_int_params { 498 struct qed_int_param in; 499 struct qed_int_param out; 500 struct msix_entry *msix_table; 501 bool fp_initialized; 502 u8 fp_msix_base; 503 u8 fp_msix_cnt; 504 u8 rdma_msix_base; 505 u8 rdma_msix_cnt; 506 }; 507 508 struct qed_dbg_feature { 509 struct dentry *dentry; 510 u8 *dump_buf; 511 u32 buf_size; 512 u32 dumped_dwords; 513 }; 514 515 struct qed_dbg_params { 516 struct qed_dbg_feature features[DBG_FEATURE_NUM]; 517 u8 engine_for_debug; 518 bool print_data; 519 }; 520 521 struct qed_dev { 522 u32 dp_module; 523 u8 dp_level; 524 char name[NAME_SIZE]; 525 526 u8 type; 527 #define QED_DEV_TYPE_BB (0 << 0) 528 #define QED_DEV_TYPE_AH BIT(0) 529 /* Translate type/revision combo into the proper conditions */ 530 #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB) 531 #define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \ 532 CHIP_REV_IS_A0(dev)) 533 #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \ 534 CHIP_REV_IS_B0(dev)) 535 #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH) 536 #define QED_IS_K2(dev) QED_IS_AH(dev) 537 538 #define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \ 539 QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2) 540 541 u16 vendor_id; 542 u16 device_id; 543 544 u16 chip_num; 545 #define CHIP_NUM_MASK 0xffff 546 #define CHIP_NUM_SHIFT 16 547 548 u16 chip_rev; 549 #define CHIP_REV_MASK 0xf 550 #define CHIP_REV_SHIFT 12 551 #define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev) 552 #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1) 553 554 u16 chip_metal; 555 #define CHIP_METAL_MASK 0xff 556 #define CHIP_METAL_SHIFT 4 557 558 u16 chip_bond_id; 559 #define CHIP_BOND_ID_MASK 0xf 560 #define CHIP_BOND_ID_SHIFT 0 561 562 u8 num_engines; 563 u8 num_ports_in_engines; 564 u8 num_funcs_in_port; 565 566 u8 path_id; 567 enum qed_mf_mode mf_mode; 568 #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT) 569 #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR) 570 #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN) 571 572 int pcie_width; 573 int pcie_speed; 574 u8 ver_str[VER_SIZE]; 575 576 /* Add MF related configuration */ 577 u8 mcp_rev; 578 u8 boot_mode; 579 580 /* WoL related configurations */ 581 u8 wol_config; 582 u8 wol_mac[ETH_ALEN]; 583 584 u32 int_mode; 585 enum qed_coalescing_mode int_coalescing_mode; 586 u16 rx_coalesce_usecs; 587 u16 tx_coalesce_usecs; 588 589 /* Start Bar offset of first hwfn */ 590 void __iomem *regview; 591 void __iomem *doorbells; 592 u64 db_phys_addr; 593 unsigned long db_size; 594 595 /* PCI */ 596 u8 cache_shift; 597 598 /* Init */ 599 const struct iro *iro_arr; 600 #define IRO (p_hwfn->cdev->iro_arr) 601 602 /* HW functions */ 603 u8 num_hwfns; 604 struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; 605 606 /* SRIOV */ 607 struct qed_hw_sriov_info *p_iov_info; 608 #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info) 609 610 unsigned long tunn_mode; 611 612 bool b_is_vf; 613 u32 drv_type; 614 struct qed_eth_stats *reset_stats; 615 struct qed_fw_data *fw_data; 616 617 u32 mcp_nvm_resp; 618 619 /* Linux specific here */ 620 struct qede_dev *edev; 621 struct pci_dev *pdev; 622 u32 flags; 623 #define QED_FLAG_STORAGE_STARTED (BIT(0)) 624 int msg_enable; 625 626 struct pci_params pci_params; 627 628 struct qed_int_params int_params; 629 630 u8 protocol; 631 #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH) 632 #define IS_QED_FCOE_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_FCOE) 633 634 /* Callbacks to protocol driver */ 635 union { 636 struct qed_common_cb_ops *common; 637 struct qed_eth_cb_ops *eth; 638 struct qed_fcoe_cb_ops *fcoe; 639 struct qed_iscsi_cb_ops *iscsi; 640 } protocol_ops; 641 void *ops_cookie; 642 643 struct qed_dbg_params dbg_params; 644 645 #ifdef CONFIG_QED_LL2 646 struct qed_cb_ll2_info *ll2; 647 u8 ll2_mac_address[ETH_ALEN]; 648 #endif 649 DECLARE_HASHTABLE(connections, 10); 650 const struct firmware *firmware; 651 652 u32 rdma_max_sge; 653 u32 rdma_max_inline; 654 u32 rdma_max_srq_sge; 655 }; 656 657 #define NUM_OF_VFS(dev) MAX_NUM_VFS_BB 658 #define NUM_OF_L2_QUEUES(dev) MAX_NUM_L2_QUEUES_BB 659 #define NUM_OF_SBS(dev) MAX_SB_PER_PATH_BB 660 #define NUM_OF_ENG_PFS(dev) MAX_NUM_PFS_BB 661 662 /** 663 * @brief qed_concrete_to_sw_fid - get the sw function id from 664 * the concrete value. 665 * 666 * @param concrete_fid 667 * 668 * @return inline u8 669 */ 670 static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, 671 u32 concrete_fid) 672 { 673 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); 674 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); 675 u8 vf_valid = GET_FIELD(concrete_fid, 676 PXP_CONCRETE_FID_VFVALID); 677 u8 sw_fid; 678 679 if (vf_valid) 680 sw_fid = vfid + MAX_NUM_PFS; 681 else 682 sw_fid = pfid; 683 684 return sw_fid; 685 } 686 687 #define PURE_LB_TC 8 688 #define OOO_LB_TC 9 689 690 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate); 691 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, 692 struct qed_ptt *p_ptt, 693 u32 min_pf_rate); 694 695 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 696 #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) 697 698 /* Other Linux specific common definitions */ 699 #define DP_NAME(cdev) ((cdev)->name) 700 701 #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\ 702 (cdev->regview) + \ 703 (offset)) 704 705 #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) 706 #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) 707 #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) 708 709 #define DOORBELL(cdev, db_addr, val) \ 710 writel((u32)val, (void __iomem *)((u8 __iomem *)\ 711 (cdev->doorbells) + (db_addr))) 712 713 /* Prototypes */ 714 int qed_fill_dev_info(struct qed_dev *cdev, 715 struct qed_dev_info *dev_info); 716 void qed_link_update(struct qed_hwfn *hwfn); 717 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, 718 u32 input_len, u8 *input_buf, 719 u32 max_size, u8 *unzip_buf); 720 void qed_get_protocol_stats(struct qed_dev *cdev, 721 enum qed_mcp_protocol_type type, 722 union qed_mcp_protocol_stats *stats); 723 int qed_slowpath_irq_req(struct qed_hwfn *hwfn); 724 725 #endif /* _QED_H */ 726