1 /* 2 * Copyright (C) 2003 - 2009 NetXen, Inc. 3 * Copyright (C) 2009 - QLogic Corporation. 4 * All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 * 19 * The full GNU General Public License is included in this distribution 20 * in the file called "COPYING". 21 * 22 */ 23 24 #include <linux/slab.h> 25 #include "netxen_nic.h" 26 #include "netxen_nic_hw.h" 27 28 #include <net/ip.h> 29 30 #define MASK(n) ((1ULL<<(n))-1) 31 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff)) 32 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff)) 33 #define MS_WIN(addr) (addr & 0x0ffc0000) 34 35 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 36 37 #define CRB_BLK(off) ((off >> 20) & 0x3f) 38 #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 39 #define CRB_WINDOW_2M (0x130060) 40 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000)) 41 #define CRB_INDIRECT_2M (0x1e0000UL) 42 43 static void netxen_nic_io_write_128M(struct netxen_adapter *adapter, 44 void __iomem *addr, u32 data); 45 static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter, 46 void __iomem *addr); 47 #ifndef readq 48 static inline u64 readq(void __iomem *addr) 49 { 50 return readl(addr) | (((u64) readl(addr + 4)) << 32LL); 51 } 52 #endif 53 54 #ifndef writeq 55 static inline void writeq(u64 val, void __iomem *addr) 56 { 57 writel(((u32) (val)), (addr)); 58 writel(((u32) (val >> 32)), (addr + 4)); 59 } 60 #endif 61 62 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \ 63 ((adapter)->ahw.pci_base0 + (off)) 64 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \ 65 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START) 66 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \ 67 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START) 68 69 static void __iomem *pci_base_offset(struct netxen_adapter *adapter, 70 unsigned long off) 71 { 72 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END)) 73 return PCI_OFFSET_FIRST_RANGE(adapter, off); 74 75 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END)) 76 return PCI_OFFSET_SECOND_RANGE(adapter, off); 77 78 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END)) 79 return PCI_OFFSET_THIRD_RANGE(adapter, off); 80 81 return NULL; 82 } 83 84 static crb_128M_2M_block_map_t 85 crb_128M_2M_map[64] __cacheline_aligned_in_smp = { 86 {{{0, 0, 0, 0} } }, /* 0: PCI */ 87 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ 88 {1, 0x0110000, 0x0120000, 0x130000}, 89 {1, 0x0120000, 0x0122000, 0x124000}, 90 {1, 0x0130000, 0x0132000, 0x126000}, 91 {1, 0x0140000, 0x0142000, 0x128000}, 92 {1, 0x0150000, 0x0152000, 0x12a000}, 93 {1, 0x0160000, 0x0170000, 0x110000}, 94 {1, 0x0170000, 0x0172000, 0x12e000}, 95 {0, 0x0000000, 0x0000000, 0x000000}, 96 {0, 0x0000000, 0x0000000, 0x000000}, 97 {0, 0x0000000, 0x0000000, 0x000000}, 98 {0, 0x0000000, 0x0000000, 0x000000}, 99 {0, 0x0000000, 0x0000000, 0x000000}, 100 {0, 0x0000000, 0x0000000, 0x000000}, 101 {1, 0x01e0000, 0x01e0800, 0x122000}, 102 {0, 0x0000000, 0x0000000, 0x000000} } }, 103 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */ 104 {{{0, 0, 0, 0} } }, /* 3: */ 105 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */ 106 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */ 107 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */ 108 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */ 109 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */ 110 {0, 0x0000000, 0x0000000, 0x000000}, 111 {0, 0x0000000, 0x0000000, 0x000000}, 112 {0, 0x0000000, 0x0000000, 0x000000}, 113 {0, 0x0000000, 0x0000000, 0x000000}, 114 {0, 0x0000000, 0x0000000, 0x000000}, 115 {0, 0x0000000, 0x0000000, 0x000000}, 116 {0, 0x0000000, 0x0000000, 0x000000}, 117 {0, 0x0000000, 0x0000000, 0x000000}, 118 {0, 0x0000000, 0x0000000, 0x000000}, 119 {0, 0x0000000, 0x0000000, 0x000000}, 120 {0, 0x0000000, 0x0000000, 0x000000}, 121 {0, 0x0000000, 0x0000000, 0x000000}, 122 {0, 0x0000000, 0x0000000, 0x000000}, 123 {0, 0x0000000, 0x0000000, 0x000000}, 124 {1, 0x08f0000, 0x08f2000, 0x172000} } }, 125 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/ 126 {0, 0x0000000, 0x0000000, 0x000000}, 127 {0, 0x0000000, 0x0000000, 0x000000}, 128 {0, 0x0000000, 0x0000000, 0x000000}, 129 {0, 0x0000000, 0x0000000, 0x000000}, 130 {0, 0x0000000, 0x0000000, 0x000000}, 131 {0, 0x0000000, 0x0000000, 0x000000}, 132 {0, 0x0000000, 0x0000000, 0x000000}, 133 {0, 0x0000000, 0x0000000, 0x000000}, 134 {0, 0x0000000, 0x0000000, 0x000000}, 135 {0, 0x0000000, 0x0000000, 0x000000}, 136 {0, 0x0000000, 0x0000000, 0x000000}, 137 {0, 0x0000000, 0x0000000, 0x000000}, 138 {0, 0x0000000, 0x0000000, 0x000000}, 139 {0, 0x0000000, 0x0000000, 0x000000}, 140 {1, 0x09f0000, 0x09f2000, 0x176000} } }, 141 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/ 142 {0, 0x0000000, 0x0000000, 0x000000}, 143 {0, 0x0000000, 0x0000000, 0x000000}, 144 {0, 0x0000000, 0x0000000, 0x000000}, 145 {0, 0x0000000, 0x0000000, 0x000000}, 146 {0, 0x0000000, 0x0000000, 0x000000}, 147 {0, 0x0000000, 0x0000000, 0x000000}, 148 {0, 0x0000000, 0x0000000, 0x000000}, 149 {0, 0x0000000, 0x0000000, 0x000000}, 150 {0, 0x0000000, 0x0000000, 0x000000}, 151 {0, 0x0000000, 0x0000000, 0x000000}, 152 {0, 0x0000000, 0x0000000, 0x000000}, 153 {0, 0x0000000, 0x0000000, 0x000000}, 154 {0, 0x0000000, 0x0000000, 0x000000}, 155 {0, 0x0000000, 0x0000000, 0x000000}, 156 {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 157 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/ 158 {0, 0x0000000, 0x0000000, 0x000000}, 159 {0, 0x0000000, 0x0000000, 0x000000}, 160 {0, 0x0000000, 0x0000000, 0x000000}, 161 {0, 0x0000000, 0x0000000, 0x000000}, 162 {0, 0x0000000, 0x0000000, 0x000000}, 163 {0, 0x0000000, 0x0000000, 0x000000}, 164 {0, 0x0000000, 0x0000000, 0x000000}, 165 {0, 0x0000000, 0x0000000, 0x000000}, 166 {0, 0x0000000, 0x0000000, 0x000000}, 167 {0, 0x0000000, 0x0000000, 0x000000}, 168 {0, 0x0000000, 0x0000000, 0x000000}, 169 {0, 0x0000000, 0x0000000, 0x000000}, 170 {0, 0x0000000, 0x0000000, 0x000000}, 171 {0, 0x0000000, 0x0000000, 0x000000}, 172 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 173 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */ 174 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */ 175 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */ 176 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */ 177 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */ 178 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */ 179 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */ 180 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */ 181 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */ 182 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */ 183 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */ 184 {{{0, 0, 0, 0} } }, /* 23: */ 185 {{{0, 0, 0, 0} } }, /* 24: */ 186 {{{0, 0, 0, 0} } }, /* 25: */ 187 {{{0, 0, 0, 0} } }, /* 26: */ 188 {{{0, 0, 0, 0} } }, /* 27: */ 189 {{{0, 0, 0, 0} } }, /* 28: */ 190 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */ 191 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */ 192 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */ 193 {{{0} } }, /* 32: PCI */ 194 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */ 195 {1, 0x2110000, 0x2120000, 0x130000}, 196 {1, 0x2120000, 0x2122000, 0x124000}, 197 {1, 0x2130000, 0x2132000, 0x126000}, 198 {1, 0x2140000, 0x2142000, 0x128000}, 199 {1, 0x2150000, 0x2152000, 0x12a000}, 200 {1, 0x2160000, 0x2170000, 0x110000}, 201 {1, 0x2170000, 0x2172000, 0x12e000}, 202 {0, 0x0000000, 0x0000000, 0x000000}, 203 {0, 0x0000000, 0x0000000, 0x000000}, 204 {0, 0x0000000, 0x0000000, 0x000000}, 205 {0, 0x0000000, 0x0000000, 0x000000}, 206 {0, 0x0000000, 0x0000000, 0x000000}, 207 {0, 0x0000000, 0x0000000, 0x000000}, 208 {0, 0x0000000, 0x0000000, 0x000000}, 209 {0, 0x0000000, 0x0000000, 0x000000} } }, 210 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */ 211 {{{0} } }, /* 35: */ 212 {{{0} } }, /* 36: */ 213 {{{0} } }, /* 37: */ 214 {{{0} } }, /* 38: */ 215 {{{0} } }, /* 39: */ 216 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */ 217 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */ 218 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */ 219 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */ 220 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */ 221 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */ 222 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */ 223 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */ 224 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */ 225 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */ 226 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */ 227 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */ 228 {{{0} } }, /* 52: */ 229 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */ 230 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */ 231 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */ 232 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */ 233 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */ 234 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */ 235 {{{0} } }, /* 59: I2C0 */ 236 {{{0} } }, /* 60: I2C1 */ 237 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */ 238 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */ 239 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */ 240 }; 241 242 /* 243 * top 12 bits of crb internal address (hub, agent) 244 */ 245 static unsigned crb_hub_agt[64] = 246 { 247 0, 248 NETXEN_HW_CRB_HUB_AGT_ADR_PS, 249 NETXEN_HW_CRB_HUB_AGT_ADR_MN, 250 NETXEN_HW_CRB_HUB_AGT_ADR_MS, 251 0, 252 NETXEN_HW_CRB_HUB_AGT_ADR_SRE, 253 NETXEN_HW_CRB_HUB_AGT_ADR_NIU, 254 NETXEN_HW_CRB_HUB_AGT_ADR_QMN, 255 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0, 256 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1, 257 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2, 258 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3, 259 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q, 260 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR, 261 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB, 262 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4, 263 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA, 264 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0, 265 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1, 266 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2, 267 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3, 268 NETXEN_HW_CRB_HUB_AGT_ADR_PGND, 269 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI, 270 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0, 271 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1, 272 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2, 273 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3, 274 0, 275 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI, 276 NETXEN_HW_CRB_HUB_AGT_ADR_SN, 277 0, 278 NETXEN_HW_CRB_HUB_AGT_ADR_EG, 279 0, 280 NETXEN_HW_CRB_HUB_AGT_ADR_PS, 281 NETXEN_HW_CRB_HUB_AGT_ADR_CAM, 282 0, 283 0, 284 0, 285 0, 286 0, 287 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR, 288 0, 289 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1, 290 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2, 291 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3, 292 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4, 293 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5, 294 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6, 295 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7, 296 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA, 297 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q, 298 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB, 299 0, 300 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0, 301 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8, 302 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9, 303 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0, 304 0, 305 NETXEN_HW_CRB_HUB_AGT_ADR_SMB, 306 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0, 307 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1, 308 0, 309 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC, 310 0, 311 }; 312 313 /* PCI Windowing for DDR regions. */ 314 315 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */ 316 317 #define NETXEN_PCIE_SEM_TIMEOUT 10000 318 319 static int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu); 320 321 int 322 netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg) 323 { 324 int done = 0, timeout = 0; 325 326 while (!done) { 327 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem))); 328 if (done == 1) 329 break; 330 if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT) 331 return -EIO; 332 msleep(1); 333 } 334 335 if (id_reg) 336 NXWR32(adapter, id_reg, adapter->portnum); 337 338 return 0; 339 } 340 341 void 342 netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem) 343 { 344 NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem))); 345 } 346 347 static int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port) 348 { 349 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { 350 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447); 351 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5); 352 } 353 354 return 0; 355 } 356 357 /* Disable an XG interface */ 358 static int netxen_niu_disable_xg_port(struct netxen_adapter *adapter) 359 { 360 __u32 mac_cfg; 361 u32 port = adapter->physical_port; 362 363 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) 364 return 0; 365 366 if (port >= NETXEN_NIU_MAX_XG_PORTS) 367 return -EINVAL; 368 369 mac_cfg = 0; 370 if (NXWR32(adapter, 371 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg)) 372 return -EIO; 373 return 0; 374 } 375 376 #define NETXEN_UNICAST_ADDR(port, index) \ 377 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8)) 378 #define NETXEN_MCAST_ADDR(port, index) \ 379 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8)) 380 #define MAC_HI(addr) \ 381 ((addr[2] << 16) | (addr[1] << 8) | (addr[0])) 382 #define MAC_LO(addr) \ 383 ((addr[5] << 16) | (addr[4] << 8) | (addr[3])) 384 385 static int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode) 386 { 387 u32 mac_cfg; 388 u32 cnt = 0; 389 __u32 reg = 0x0200; 390 u32 port = adapter->physical_port; 391 u16 board_type = adapter->ahw.board_type; 392 393 if (port >= NETXEN_NIU_MAX_XG_PORTS) 394 return -EINVAL; 395 396 mac_cfg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port)); 397 mac_cfg &= ~0x4; 398 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg); 399 400 if ((board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) || 401 (board_type == NETXEN_BRDTYPE_P2_SB31_10G_HMEZ)) 402 reg = (0x20 << port); 403 404 NXWR32(adapter, NETXEN_NIU_FRAME_COUNT_SELECT, reg); 405 406 mdelay(10); 407 408 while (NXRD32(adapter, NETXEN_NIU_FRAME_COUNT) && ++cnt < 20) 409 mdelay(10); 410 411 if (cnt < 20) { 412 413 reg = NXRD32(adapter, 414 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port)); 415 416 if (mode == NETXEN_NIU_PROMISC_MODE) 417 reg = (reg | 0x2000UL); 418 else 419 reg = (reg & ~0x2000UL); 420 421 if (mode == NETXEN_NIU_ALLMULTI_MODE) 422 reg = (reg | 0x1000UL); 423 else 424 reg = (reg & ~0x1000UL); 425 426 NXWR32(adapter, 427 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg); 428 } 429 430 mac_cfg |= 0x4; 431 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg); 432 433 return 0; 434 } 435 436 static int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr) 437 { 438 u32 mac_hi, mac_lo; 439 u32 reg_hi, reg_lo; 440 441 u8 phy = adapter->physical_port; 442 443 if (phy >= NETXEN_NIU_MAX_XG_PORTS) 444 return -EINVAL; 445 446 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24); 447 mac_hi = addr[2] | ((u32)addr[3] << 8) | 448 ((u32)addr[4] << 16) | ((u32)addr[5] << 24); 449 450 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy); 451 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy); 452 453 /* write twice to flush */ 454 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi)) 455 return -EIO; 456 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi)) 457 return -EIO; 458 459 return 0; 460 } 461 462 static int 463 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter) 464 { 465 u32 val = 0; 466 u16 port = adapter->physical_port; 467 u8 *addr = adapter->mac_addr; 468 469 if (adapter->mc_enabled) 470 return 0; 471 472 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG); 473 val |= (1UL << (28+port)); 474 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val); 475 476 /* add broadcast addr to filter */ 477 val = 0xffffff; 478 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val); 479 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val); 480 481 /* add station addr to filter */ 482 val = MAC_HI(addr); 483 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val); 484 val = MAC_LO(addr); 485 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val); 486 487 adapter->mc_enabled = 1; 488 return 0; 489 } 490 491 static int 492 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter) 493 { 494 u32 val = 0; 495 u16 port = adapter->physical_port; 496 u8 *addr = adapter->mac_addr; 497 498 if (!adapter->mc_enabled) 499 return 0; 500 501 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG); 502 val &= ~(1UL << (28+port)); 503 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val); 504 505 val = MAC_HI(addr); 506 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val); 507 val = MAC_LO(addr); 508 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val); 509 510 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0); 511 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0); 512 513 adapter->mc_enabled = 0; 514 return 0; 515 } 516 517 static int 518 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter, 519 int index, u8 *addr) 520 { 521 u32 hi = 0, lo = 0; 522 u16 port = adapter->physical_port; 523 524 lo = MAC_LO(addr); 525 hi = MAC_HI(addr); 526 527 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi); 528 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo); 529 530 return 0; 531 } 532 533 static void netxen_p2_nic_set_multi(struct net_device *netdev) 534 { 535 struct netxen_adapter *adapter = netdev_priv(netdev); 536 struct netdev_hw_addr *ha; 537 u8 null_addr[ETH_ALEN]; 538 int i; 539 540 eth_zero_addr(null_addr); 541 542 if (netdev->flags & IFF_PROMISC) { 543 544 adapter->set_promisc(adapter, 545 NETXEN_NIU_PROMISC_MODE); 546 547 /* Full promiscuous mode */ 548 netxen_nic_disable_mcast_filter(adapter); 549 550 return; 551 } 552 553 if (netdev_mc_empty(netdev)) { 554 adapter->set_promisc(adapter, 555 NETXEN_NIU_NON_PROMISC_MODE); 556 netxen_nic_disable_mcast_filter(adapter); 557 return; 558 } 559 560 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE); 561 if (netdev->flags & IFF_ALLMULTI || 562 netdev_mc_count(netdev) > adapter->max_mc_count) { 563 netxen_nic_disable_mcast_filter(adapter); 564 return; 565 } 566 567 netxen_nic_enable_mcast_filter(adapter); 568 569 i = 0; 570 netdev_for_each_mc_addr(ha, netdev) 571 netxen_nic_set_mcast_addr(adapter, i++, ha->addr); 572 573 /* Clear out remaining addresses */ 574 while (i < adapter->max_mc_count) 575 netxen_nic_set_mcast_addr(adapter, i++, null_addr); 576 } 577 578 static int 579 netxen_send_cmd_descs(struct netxen_adapter *adapter, 580 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc) 581 { 582 u32 i, producer, consumer; 583 struct netxen_cmd_buffer *pbuf; 584 struct cmd_desc_type0 *cmd_desc; 585 struct nx_host_tx_ring *tx_ring; 586 587 i = 0; 588 589 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) 590 return -EIO; 591 592 tx_ring = adapter->tx_ring; 593 __netif_tx_lock_bh(tx_ring->txq); 594 595 producer = tx_ring->producer; 596 consumer = tx_ring->sw_consumer; 597 598 if (nr_desc >= netxen_tx_avail(tx_ring)) { 599 netif_tx_stop_queue(tx_ring->txq); 600 smp_mb(); 601 if (netxen_tx_avail(tx_ring) > nr_desc) { 602 if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH) 603 netif_tx_wake_queue(tx_ring->txq); 604 } else { 605 __netif_tx_unlock_bh(tx_ring->txq); 606 return -EBUSY; 607 } 608 } 609 610 do { 611 cmd_desc = &cmd_desc_arr[i]; 612 613 pbuf = &tx_ring->cmd_buf_arr[producer]; 614 pbuf->skb = NULL; 615 pbuf->frag_count = 0; 616 617 memcpy(&tx_ring->desc_head[producer], 618 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0)); 619 620 producer = get_next_index(producer, tx_ring->num_desc); 621 i++; 622 623 } while (i != nr_desc); 624 625 tx_ring->producer = producer; 626 627 netxen_nic_update_cmd_producer(adapter, tx_ring); 628 629 __netif_tx_unlock_bh(tx_ring->txq); 630 631 return 0; 632 } 633 634 static int 635 nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op) 636 { 637 nx_nic_req_t req; 638 nx_mac_req_t *mac_req; 639 u64 word; 640 641 memset(&req, 0, sizeof(nx_nic_req_t)); 642 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23); 643 644 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16); 645 req.req_hdr = cpu_to_le64(word); 646 647 mac_req = (nx_mac_req_t *)&req.words[0]; 648 mac_req->op = op; 649 memcpy(mac_req->mac_addr, addr, ETH_ALEN); 650 651 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 652 } 653 654 static int nx_p3_nic_add_mac(struct netxen_adapter *adapter, 655 const u8 *addr, struct list_head *del_list) 656 { 657 struct list_head *head; 658 nx_mac_list_t *cur; 659 660 /* look up if already exists */ 661 list_for_each(head, del_list) { 662 cur = list_entry(head, nx_mac_list_t, list); 663 664 if (ether_addr_equal(addr, cur->mac_addr)) { 665 list_move_tail(head, &adapter->mac_list); 666 return 0; 667 } 668 } 669 670 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC); 671 if (cur == NULL) 672 return -ENOMEM; 673 674 memcpy(cur->mac_addr, addr, ETH_ALEN); 675 list_add_tail(&cur->list, &adapter->mac_list); 676 return nx_p3_sre_macaddr_change(adapter, 677 cur->mac_addr, NETXEN_MAC_ADD); 678 } 679 680 static void netxen_p3_nic_set_multi(struct net_device *netdev) 681 { 682 struct netxen_adapter *adapter = netdev_priv(netdev); 683 struct netdev_hw_addr *ha; 684 static const u8 bcast_addr[ETH_ALEN] = { 685 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 686 }; 687 u32 mode = VPORT_MISS_MODE_DROP; 688 LIST_HEAD(del_list); 689 struct list_head *head; 690 nx_mac_list_t *cur; 691 692 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) 693 return; 694 695 list_splice_tail_init(&adapter->mac_list, &del_list); 696 697 nx_p3_nic_add_mac(adapter, adapter->mac_addr, &del_list); 698 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list); 699 700 if (netdev->flags & IFF_PROMISC) { 701 mode = VPORT_MISS_MODE_ACCEPT_ALL; 702 goto send_fw_cmd; 703 } 704 705 if ((netdev->flags & IFF_ALLMULTI) || 706 (netdev_mc_count(netdev) > adapter->max_mc_count)) { 707 mode = VPORT_MISS_MODE_ACCEPT_MULTI; 708 goto send_fw_cmd; 709 } 710 711 if (!netdev_mc_empty(netdev)) { 712 netdev_for_each_mc_addr(ha, netdev) 713 nx_p3_nic_add_mac(adapter, ha->addr, &del_list); 714 } 715 716 send_fw_cmd: 717 adapter->set_promisc(adapter, mode); 718 head = &del_list; 719 while (!list_empty(head)) { 720 cur = list_entry(head->next, nx_mac_list_t, list); 721 722 nx_p3_sre_macaddr_change(adapter, 723 cur->mac_addr, NETXEN_MAC_DEL); 724 list_del(&cur->list); 725 kfree(cur); 726 } 727 } 728 729 static int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode) 730 { 731 nx_nic_req_t req; 732 u64 word; 733 734 memset(&req, 0, sizeof(nx_nic_req_t)); 735 736 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); 737 738 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE | 739 ((u64)adapter->portnum << 16); 740 req.req_hdr = cpu_to_le64(word); 741 742 req.words[0] = cpu_to_le64(mode); 743 744 return netxen_send_cmd_descs(adapter, 745 (struct cmd_desc_type0 *)&req, 1); 746 } 747 748 void netxen_p3_free_mac_list(struct netxen_adapter *adapter) 749 { 750 nx_mac_list_t *cur; 751 struct list_head *head = &adapter->mac_list; 752 753 while (!list_empty(head)) { 754 cur = list_entry(head->next, nx_mac_list_t, list); 755 nx_p3_sre_macaddr_change(adapter, 756 cur->mac_addr, NETXEN_MAC_DEL); 757 list_del(&cur->list); 758 kfree(cur); 759 } 760 } 761 762 static int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr) 763 { 764 /* assuming caller has already copied new addr to netdev */ 765 netxen_p3_nic_set_multi(adapter->netdev); 766 return 0; 767 } 768 769 #define NETXEN_CONFIG_INTR_COALESCE 3 770 771 /* 772 * Send the interrupt coalescing parameter set by ethtool to the card. 773 */ 774 int netxen_config_intr_coalesce(struct netxen_adapter *adapter) 775 { 776 nx_nic_req_t req; 777 u64 word[6]; 778 int rv, i; 779 780 memset(&req, 0, sizeof(nx_nic_req_t)); 781 memset(word, 0, sizeof(word)); 782 783 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); 784 785 word[0] = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16); 786 req.req_hdr = cpu_to_le64(word[0]); 787 788 memcpy(&word[0], &adapter->coal, sizeof(adapter->coal)); 789 for (i = 0; i < 6; i++) 790 req.words[i] = cpu_to_le64(word[i]); 791 792 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 793 if (rv != 0) { 794 printk(KERN_ERR "ERROR. Could not send " 795 "interrupt coalescing parameters\n"); 796 } 797 798 return rv; 799 } 800 801 int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable) 802 { 803 nx_nic_req_t req; 804 u64 word; 805 int rv = 0; 806 807 if (!test_bit(__NX_FW_ATTACHED, &adapter->state)) 808 return 0; 809 810 memset(&req, 0, sizeof(nx_nic_req_t)); 811 812 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); 813 814 word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16); 815 req.req_hdr = cpu_to_le64(word); 816 817 req.words[0] = cpu_to_le64(enable); 818 819 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 820 if (rv != 0) { 821 printk(KERN_ERR "ERROR. Could not send " 822 "configure hw lro request\n"); 823 } 824 825 return rv; 826 } 827 828 int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable) 829 { 830 nx_nic_req_t req; 831 u64 word; 832 int rv = 0; 833 834 if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable) 835 return rv; 836 837 memset(&req, 0, sizeof(nx_nic_req_t)); 838 839 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); 840 841 word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING | 842 ((u64)adapter->portnum << 16); 843 req.req_hdr = cpu_to_le64(word); 844 845 req.words[0] = cpu_to_le64(enable); 846 847 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 848 if (rv != 0) { 849 printk(KERN_ERR "ERROR. Could not send " 850 "configure bridge mode request\n"); 851 } 852 853 adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED; 854 855 return rv; 856 } 857 858 859 #define RSS_HASHTYPE_IP_TCP 0x3 860 861 int netxen_config_rss(struct netxen_adapter *adapter, int enable) 862 { 863 nx_nic_req_t req; 864 u64 word; 865 int i, rv; 866 867 static const u64 key[] = { 868 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL, 869 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL, 870 0x255b0ec26d5a56daULL 871 }; 872 873 874 memset(&req, 0, sizeof(nx_nic_req_t)); 875 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); 876 877 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16); 878 req.req_hdr = cpu_to_le64(word); 879 880 /* 881 * RSS request: 882 * bits 3-0: hash_method 883 * 5-4: hash_type_ipv4 884 * 7-6: hash_type_ipv6 885 * 8: enable 886 * 9: use indirection table 887 * 47-10: reserved 888 * 63-48: indirection table mask 889 */ 890 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) | 891 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) | 892 ((u64)(enable & 0x1) << 8) | 893 ((0x7ULL) << 48); 894 req.words[0] = cpu_to_le64(word); 895 for (i = 0; i < ARRAY_SIZE(key); i++) 896 req.words[i+1] = cpu_to_le64(key[i]); 897 898 899 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 900 if (rv != 0) { 901 printk(KERN_ERR "%s: could not configure RSS\n", 902 adapter->netdev->name); 903 } 904 905 return rv; 906 } 907 908 int netxen_config_ipaddr(struct netxen_adapter *adapter, __be32 ip, int cmd) 909 { 910 nx_nic_req_t req; 911 u64 word; 912 int rv; 913 914 memset(&req, 0, sizeof(nx_nic_req_t)); 915 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); 916 917 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16); 918 req.req_hdr = cpu_to_le64(word); 919 920 req.words[0] = cpu_to_le64(cmd); 921 memcpy(&req.words[1], &ip, sizeof(u32)); 922 923 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 924 if (rv != 0) { 925 printk(KERN_ERR "%s: could not notify %s IP 0x%x request\n", 926 adapter->netdev->name, 927 (cmd == NX_IP_UP) ? "Add" : "Remove", ip); 928 } 929 return rv; 930 } 931 932 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable) 933 { 934 nx_nic_req_t req; 935 u64 word; 936 int rv; 937 938 memset(&req, 0, sizeof(nx_nic_req_t)); 939 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); 940 941 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16); 942 req.req_hdr = cpu_to_le64(word); 943 req.words[0] = cpu_to_le64(enable | (enable << 8)); 944 945 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 946 if (rv != 0) { 947 printk(KERN_ERR "%s: could not configure link notification\n", 948 adapter->netdev->name); 949 } 950 951 return rv; 952 } 953 954 int netxen_send_lro_cleanup(struct netxen_adapter *adapter) 955 { 956 nx_nic_req_t req; 957 u64 word; 958 int rv; 959 960 if (!test_bit(__NX_FW_ATTACHED, &adapter->state)) 961 return 0; 962 963 memset(&req, 0, sizeof(nx_nic_req_t)); 964 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); 965 966 word = NX_NIC_H2C_OPCODE_LRO_REQUEST | 967 ((u64)adapter->portnum << 16) | 968 ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ; 969 970 req.req_hdr = cpu_to_le64(word); 971 972 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 973 if (rv != 0) { 974 printk(KERN_ERR "%s: could not cleanup lro flows\n", 975 adapter->netdev->name); 976 } 977 return rv; 978 } 979 980 /* 981 * netxen_nic_change_mtu - Change the Maximum Transfer Unit 982 * @returns 0 on success, negative on failure 983 */ 984 985 #define MTU_FUDGE_FACTOR 100 986 987 int netxen_nic_change_mtu(struct net_device *netdev, int mtu) 988 { 989 struct netxen_adapter *adapter = netdev_priv(netdev); 990 int rc = 0; 991 992 if (adapter->set_mtu) 993 rc = adapter->set_mtu(adapter, mtu); 994 995 if (!rc) 996 netdev->mtu = mtu; 997 998 return rc; 999 } 1000 1001 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base, 1002 int size, __le32 * buf) 1003 { 1004 int i, v, addr; 1005 __le32 *ptr32; 1006 int ret; 1007 1008 addr = base; 1009 ptr32 = buf; 1010 for (i = 0; i < size / sizeof(u32); i++) { 1011 ret = netxen_rom_fast_read(adapter, addr, &v); 1012 if (ret) 1013 return ret; 1014 1015 *ptr32 = cpu_to_le32(v); 1016 ptr32++; 1017 addr += sizeof(u32); 1018 } 1019 if ((char *)buf + size > (char *)ptr32) { 1020 __le32 local; 1021 ret = netxen_rom_fast_read(adapter, addr, &v); 1022 if (ret) 1023 return ret; 1024 local = cpu_to_le32(v); 1025 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32); 1026 } 1027 1028 return 0; 1029 } 1030 1031 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 *mac) 1032 { 1033 __le32 *pmac = (__le32 *) mac; 1034 u32 offset; 1035 1036 offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64)); 1037 1038 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1) 1039 return -1; 1040 1041 if (*mac == ~0ULL) { 1042 1043 offset = NX_OLD_MAC_ADDR_OFFSET + 1044 (adapter->portnum * sizeof(u64)); 1045 1046 if (netxen_get_flash_block(adapter, 1047 offset, sizeof(u64), pmac) == -1) 1048 return -1; 1049 1050 if (*mac == ~0ULL) 1051 return -1; 1052 } 1053 return 0; 1054 } 1055 1056 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, u64 *mac) 1057 { 1058 uint32_t crbaddr, mac_hi, mac_lo; 1059 int pci_func = adapter->ahw.pci_func; 1060 1061 crbaddr = CRB_MAC_BLOCK_START + 1062 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1)); 1063 1064 mac_lo = NXRD32(adapter, crbaddr); 1065 mac_hi = NXRD32(adapter, crbaddr+4); 1066 1067 if (pci_func & 1) 1068 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16)); 1069 else 1070 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32)); 1071 1072 return 0; 1073 } 1074 1075 /* 1076 * Changes the CRB window to the specified window. 1077 */ 1078 static void 1079 netxen_nic_pci_set_crbwindow_128M(struct netxen_adapter *adapter, 1080 u32 window) 1081 { 1082 void __iomem *offset; 1083 int count = 10; 1084 u8 func = adapter->ahw.pci_func; 1085 1086 if (adapter->ahw.crb_win == window) 1087 return; 1088 1089 offset = PCI_OFFSET_SECOND_RANGE(adapter, 1090 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func))); 1091 1092 writel(window, offset); 1093 do { 1094 if (window == readl(offset)) 1095 break; 1096 1097 if (printk_ratelimit()) 1098 dev_warn(&adapter->pdev->dev, 1099 "failed to set CRB window to %d\n", 1100 (window == NETXEN_WINDOW_ONE)); 1101 udelay(1); 1102 1103 } while (--count > 0); 1104 1105 if (count > 0) 1106 adapter->ahw.crb_win = window; 1107 } 1108 1109 /* 1110 * Returns < 0 if off is not valid, 1111 * 1 if window access is needed. 'off' is set to offset from 1112 * CRB space in 128M pci map 1113 * 0 if no window access is needed. 'off' is set to 2M addr 1114 * In: 'off' is offset from base in 128M pci map 1115 */ 1116 static int 1117 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter, 1118 ulong off, void __iomem **addr) 1119 { 1120 crb_128M_2M_sub_block_map_t *m; 1121 1122 1123 if ((off >= NETXEN_CRB_MAX) || (off < NETXEN_PCI_CRBSPACE)) 1124 return -EINVAL; 1125 1126 off -= NETXEN_PCI_CRBSPACE; 1127 1128 /* 1129 * Try direct map 1130 */ 1131 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)]; 1132 1133 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) { 1134 *addr = adapter->ahw.pci_base0 + m->start_2M + 1135 (off - m->start_128M); 1136 return 0; 1137 } 1138 1139 /* 1140 * Not in direct map, use crb window 1141 */ 1142 *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M + 1143 (off & MASK(16)); 1144 return 1; 1145 } 1146 1147 /* 1148 * In: 'off' is offset from CRB space in 128M pci map 1149 * Out: 'off' is 2M pci map addr 1150 * side effect: lock crb window 1151 */ 1152 static void 1153 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong off) 1154 { 1155 u32 window; 1156 void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M; 1157 1158 off -= NETXEN_PCI_CRBSPACE; 1159 1160 window = CRB_HI(off); 1161 1162 writel(window, addr); 1163 if (readl(addr) != window) { 1164 if (printk_ratelimit()) 1165 dev_warn(&adapter->pdev->dev, 1166 "failed to set CRB window to %d off 0x%lx\n", 1167 window, off); 1168 } 1169 } 1170 1171 static void __iomem * 1172 netxen_nic_map_indirect_address_128M(struct netxen_adapter *adapter, 1173 ulong win_off, void __iomem **mem_ptr) 1174 { 1175 ulong off = win_off; 1176 void __iomem *addr; 1177 resource_size_t mem_base; 1178 1179 if (ADDR_IN_WINDOW1(win_off)) 1180 off = NETXEN_CRB_NORMAL(win_off); 1181 1182 addr = pci_base_offset(adapter, off); 1183 if (addr) 1184 return addr; 1185 1186 if (adapter->ahw.pci_len0 == 0) 1187 off -= NETXEN_PCI_CRBSPACE; 1188 1189 mem_base = pci_resource_start(adapter->pdev, 0); 1190 *mem_ptr = ioremap(mem_base + (off & PAGE_MASK), PAGE_SIZE); 1191 if (*mem_ptr) 1192 addr = *mem_ptr + (off & (PAGE_SIZE - 1)); 1193 1194 return addr; 1195 } 1196 1197 static int 1198 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data) 1199 { 1200 unsigned long flags; 1201 void __iomem *addr, *mem_ptr = NULL; 1202 1203 addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr); 1204 if (!addr) 1205 return -EIO; 1206 1207 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */ 1208 netxen_nic_io_write_128M(adapter, addr, data); 1209 } else { /* Window 0 */ 1210 write_lock_irqsave(&adapter->ahw.crb_lock, flags); 1211 netxen_nic_pci_set_crbwindow_128M(adapter, 0); 1212 writel(data, addr); 1213 netxen_nic_pci_set_crbwindow_128M(adapter, 1214 NETXEN_WINDOW_ONE); 1215 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags); 1216 } 1217 1218 if (mem_ptr) 1219 iounmap(mem_ptr); 1220 1221 return 0; 1222 } 1223 1224 static u32 1225 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off) 1226 { 1227 unsigned long flags; 1228 void __iomem *addr, *mem_ptr = NULL; 1229 u32 data; 1230 1231 addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr); 1232 if (!addr) 1233 return -EIO; 1234 1235 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */ 1236 data = netxen_nic_io_read_128M(adapter, addr); 1237 } else { /* Window 0 */ 1238 write_lock_irqsave(&adapter->ahw.crb_lock, flags); 1239 netxen_nic_pci_set_crbwindow_128M(adapter, 0); 1240 data = readl(addr); 1241 netxen_nic_pci_set_crbwindow_128M(adapter, 1242 NETXEN_WINDOW_ONE); 1243 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags); 1244 } 1245 1246 if (mem_ptr) 1247 iounmap(mem_ptr); 1248 1249 return data; 1250 } 1251 1252 static int 1253 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data) 1254 { 1255 unsigned long flags; 1256 int rv; 1257 void __iomem *addr = NULL; 1258 1259 rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr); 1260 1261 if (rv == 0) { 1262 writel(data, addr); 1263 return 0; 1264 } 1265 1266 if (rv > 0) { 1267 /* indirect access */ 1268 write_lock_irqsave(&adapter->ahw.crb_lock, flags); 1269 crb_win_lock(adapter); 1270 netxen_nic_pci_set_crbwindow_2M(adapter, off); 1271 writel(data, addr); 1272 crb_win_unlock(adapter); 1273 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags); 1274 return 0; 1275 } 1276 1277 dev_err(&adapter->pdev->dev, 1278 "%s: invalid offset: 0x%016lx\n", __func__, off); 1279 dump_stack(); 1280 return -EIO; 1281 } 1282 1283 static u32 1284 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off) 1285 { 1286 unsigned long flags; 1287 int rv; 1288 u32 data; 1289 void __iomem *addr = NULL; 1290 1291 rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr); 1292 1293 if (rv == 0) 1294 return readl(addr); 1295 1296 if (rv > 0) { 1297 /* indirect access */ 1298 write_lock_irqsave(&adapter->ahw.crb_lock, flags); 1299 crb_win_lock(adapter); 1300 netxen_nic_pci_set_crbwindow_2M(adapter, off); 1301 data = readl(addr); 1302 crb_win_unlock(adapter); 1303 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags); 1304 return data; 1305 } 1306 1307 dev_err(&adapter->pdev->dev, 1308 "%s: invalid offset: 0x%016lx\n", __func__, off); 1309 dump_stack(); 1310 return -1; 1311 } 1312 1313 /* window 1 registers only */ 1314 static void netxen_nic_io_write_128M(struct netxen_adapter *adapter, 1315 void __iomem *addr, u32 data) 1316 { 1317 read_lock(&adapter->ahw.crb_lock); 1318 writel(data, addr); 1319 read_unlock(&adapter->ahw.crb_lock); 1320 } 1321 1322 static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter, 1323 void __iomem *addr) 1324 { 1325 u32 val; 1326 1327 read_lock(&adapter->ahw.crb_lock); 1328 val = readl(addr); 1329 read_unlock(&adapter->ahw.crb_lock); 1330 1331 return val; 1332 } 1333 1334 static void netxen_nic_io_write_2M(struct netxen_adapter *adapter, 1335 void __iomem *addr, u32 data) 1336 { 1337 writel(data, addr); 1338 } 1339 1340 static u32 netxen_nic_io_read_2M(struct netxen_adapter *adapter, 1341 void __iomem *addr) 1342 { 1343 return readl(addr); 1344 } 1345 1346 void __iomem * 1347 netxen_get_ioaddr(struct netxen_adapter *adapter, u32 offset) 1348 { 1349 void __iomem *addr = NULL; 1350 1351 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { 1352 if ((offset < NETXEN_CRB_PCIX_HOST2) && 1353 (offset > NETXEN_CRB_PCIX_HOST)) 1354 addr = PCI_OFFSET_SECOND_RANGE(adapter, offset); 1355 else 1356 addr = NETXEN_CRB_NORMALIZE(adapter, offset); 1357 } else { 1358 WARN_ON(netxen_nic_pci_get_crb_addr_2M(adapter, 1359 offset, &addr)); 1360 } 1361 1362 return addr; 1363 } 1364 1365 static int 1366 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter, 1367 u64 addr, u32 *start) 1368 { 1369 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { 1370 *start = (addr - NETXEN_ADDR_OCM0 + NETXEN_PCI_OCM0); 1371 return 0; 1372 } else if (ADDR_IN_RANGE(addr, 1373 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { 1374 *start = (addr - NETXEN_ADDR_OCM1 + NETXEN_PCI_OCM1); 1375 return 0; 1376 } 1377 1378 return -EIO; 1379 } 1380 1381 static int 1382 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter, 1383 u64 addr, u32 *start) 1384 { 1385 u32 window; 1386 1387 window = OCM_WIN(addr); 1388 1389 writel(window, adapter->ahw.ocm_win_crb); 1390 /* read back to flush */ 1391 readl(adapter->ahw.ocm_win_crb); 1392 1393 adapter->ahw.ocm_win = window; 1394 *start = NETXEN_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr); 1395 return 0; 1396 } 1397 1398 static int 1399 netxen_nic_pci_mem_access_direct(struct netxen_adapter *adapter, u64 off, 1400 u64 *data, int op) 1401 { 1402 void __iomem *addr, *mem_ptr = NULL; 1403 resource_size_t mem_base; 1404 int ret; 1405 u32 start; 1406 1407 spin_lock(&adapter->ahw.mem_lock); 1408 1409 ret = adapter->pci_set_window(adapter, off, &start); 1410 if (ret != 0) 1411 goto unlock; 1412 1413 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { 1414 addr = adapter->ahw.pci_base0 + start; 1415 } else { 1416 addr = pci_base_offset(adapter, start); 1417 if (addr) 1418 goto noremap; 1419 1420 mem_base = pci_resource_start(adapter->pdev, 0) + 1421 (start & PAGE_MASK); 1422 mem_ptr = ioremap(mem_base, PAGE_SIZE); 1423 if (mem_ptr == NULL) { 1424 ret = -EIO; 1425 goto unlock; 1426 } 1427 1428 addr = mem_ptr + (start & (PAGE_SIZE-1)); 1429 } 1430 noremap: 1431 if (op == 0) /* read */ 1432 *data = readq(addr); 1433 else /* write */ 1434 writeq(*data, addr); 1435 1436 unlock: 1437 spin_unlock(&adapter->ahw.mem_lock); 1438 1439 if (mem_ptr) 1440 iounmap(mem_ptr); 1441 return ret; 1442 } 1443 1444 void 1445 netxen_pci_camqm_read_2M(struct netxen_adapter *adapter, u64 off, u64 *data) 1446 { 1447 void __iomem *addr = adapter->ahw.pci_base0 + 1448 NETXEN_PCI_CAMQM_2M_BASE + (off - NETXEN_PCI_CAMQM); 1449 1450 spin_lock(&adapter->ahw.mem_lock); 1451 *data = readq(addr); 1452 spin_unlock(&adapter->ahw.mem_lock); 1453 } 1454 1455 void 1456 netxen_pci_camqm_write_2M(struct netxen_adapter *adapter, u64 off, u64 data) 1457 { 1458 void __iomem *addr = adapter->ahw.pci_base0 + 1459 NETXEN_PCI_CAMQM_2M_BASE + (off - NETXEN_PCI_CAMQM); 1460 1461 spin_lock(&adapter->ahw.mem_lock); 1462 writeq(data, addr); 1463 spin_unlock(&adapter->ahw.mem_lock); 1464 } 1465 1466 #define MAX_CTL_CHECK 1000 1467 1468 static int 1469 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter, 1470 u64 off, u64 data) 1471 { 1472 int j, ret; 1473 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo; 1474 void __iomem *mem_crb; 1475 1476 /* Only 64-bit aligned access */ 1477 if (off & 7) 1478 return -EIO; 1479 1480 /* P2 has different SIU and MIU test agent base addr */ 1481 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, 1482 NETXEN_ADDR_QDR_NET_MAX_P2)) { 1483 mem_crb = pci_base_offset(adapter, 1484 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE); 1485 addr_hi = SIU_TEST_AGT_ADDR_HI; 1486 data_lo = SIU_TEST_AGT_WRDATA_LO; 1487 data_hi = SIU_TEST_AGT_WRDATA_HI; 1488 off_lo = off & SIU_TEST_AGT_ADDR_MASK; 1489 off_hi = SIU_TEST_AGT_UPPER_ADDR(off); 1490 goto correct; 1491 } 1492 1493 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { 1494 mem_crb = pci_base_offset(adapter, 1495 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE); 1496 addr_hi = MIU_TEST_AGT_ADDR_HI; 1497 data_lo = MIU_TEST_AGT_WRDATA_LO; 1498 data_hi = MIU_TEST_AGT_WRDATA_HI; 1499 off_lo = off & MIU_TEST_AGT_ADDR_MASK; 1500 off_hi = 0; 1501 goto correct; 1502 } 1503 1504 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) || 1505 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { 1506 if (adapter->ahw.pci_len0 != 0) { 1507 return netxen_nic_pci_mem_access_direct(adapter, 1508 off, &data, 1); 1509 } 1510 } 1511 1512 return -EIO; 1513 1514 correct: 1515 spin_lock(&adapter->ahw.mem_lock); 1516 netxen_nic_pci_set_crbwindow_128M(adapter, 0); 1517 1518 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO)); 1519 writel(off_hi, (mem_crb + addr_hi)); 1520 writel(data & 0xffffffff, (mem_crb + data_lo)); 1521 writel((data >> 32) & 0xffffffff, (mem_crb + data_hi)); 1522 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL)); 1523 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE), 1524 (mem_crb + TEST_AGT_CTRL)); 1525 1526 for (j = 0; j < MAX_CTL_CHECK; j++) { 1527 temp = readl((mem_crb + TEST_AGT_CTRL)); 1528 if ((temp & TA_CTL_BUSY) == 0) 1529 break; 1530 } 1531 1532 if (j >= MAX_CTL_CHECK) { 1533 if (printk_ratelimit()) 1534 dev_err(&adapter->pdev->dev, 1535 "failed to write through agent\n"); 1536 ret = -EIO; 1537 } else 1538 ret = 0; 1539 1540 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE); 1541 spin_unlock(&adapter->ahw.mem_lock); 1542 return ret; 1543 } 1544 1545 static int 1546 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter, 1547 u64 off, u64 *data) 1548 { 1549 int j, ret; 1550 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo; 1551 u64 val; 1552 void __iomem *mem_crb; 1553 1554 /* Only 64-bit aligned access */ 1555 if (off & 7) 1556 return -EIO; 1557 1558 /* P2 has different SIU and MIU test agent base addr */ 1559 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, 1560 NETXEN_ADDR_QDR_NET_MAX_P2)) { 1561 mem_crb = pci_base_offset(adapter, 1562 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE); 1563 addr_hi = SIU_TEST_AGT_ADDR_HI; 1564 data_lo = SIU_TEST_AGT_RDDATA_LO; 1565 data_hi = SIU_TEST_AGT_RDDATA_HI; 1566 off_lo = off & SIU_TEST_AGT_ADDR_MASK; 1567 off_hi = SIU_TEST_AGT_UPPER_ADDR(off); 1568 goto correct; 1569 } 1570 1571 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { 1572 mem_crb = pci_base_offset(adapter, 1573 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE); 1574 addr_hi = MIU_TEST_AGT_ADDR_HI; 1575 data_lo = MIU_TEST_AGT_RDDATA_LO; 1576 data_hi = MIU_TEST_AGT_RDDATA_HI; 1577 off_lo = off & MIU_TEST_AGT_ADDR_MASK; 1578 off_hi = 0; 1579 goto correct; 1580 } 1581 1582 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) || 1583 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { 1584 if (adapter->ahw.pci_len0 != 0) { 1585 return netxen_nic_pci_mem_access_direct(adapter, 1586 off, data, 0); 1587 } 1588 } 1589 1590 return -EIO; 1591 1592 correct: 1593 spin_lock(&adapter->ahw.mem_lock); 1594 netxen_nic_pci_set_crbwindow_128M(adapter, 0); 1595 1596 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO)); 1597 writel(off_hi, (mem_crb + addr_hi)); 1598 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL)); 1599 writel((TA_CTL_START|TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL)); 1600 1601 for (j = 0; j < MAX_CTL_CHECK; j++) { 1602 temp = readl(mem_crb + TEST_AGT_CTRL); 1603 if ((temp & TA_CTL_BUSY) == 0) 1604 break; 1605 } 1606 1607 if (j >= MAX_CTL_CHECK) { 1608 if (printk_ratelimit()) 1609 dev_err(&adapter->pdev->dev, 1610 "failed to read through agent\n"); 1611 ret = -EIO; 1612 } else { 1613 1614 temp = readl(mem_crb + data_hi); 1615 val = ((u64)temp << 32); 1616 val |= readl(mem_crb + data_lo); 1617 *data = val; 1618 ret = 0; 1619 } 1620 1621 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE); 1622 spin_unlock(&adapter->ahw.mem_lock); 1623 1624 return ret; 1625 } 1626 1627 static int 1628 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, 1629 u64 off, u64 data) 1630 { 1631 int j, ret; 1632 u32 temp, off8; 1633 void __iomem *mem_crb; 1634 1635 /* Only 64-bit aligned access */ 1636 if (off & 7) 1637 return -EIO; 1638 1639 /* P3 onward, test agent base for MIU and SIU is same */ 1640 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, 1641 NETXEN_ADDR_QDR_NET_MAX_P3)) { 1642 mem_crb = netxen_get_ioaddr(adapter, 1643 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE); 1644 goto correct; 1645 } 1646 1647 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { 1648 mem_crb = netxen_get_ioaddr(adapter, 1649 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE); 1650 goto correct; 1651 } 1652 1653 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) 1654 return netxen_nic_pci_mem_access_direct(adapter, off, &data, 1); 1655 1656 return -EIO; 1657 1658 correct: 1659 off8 = off & 0xfffffff8; 1660 1661 spin_lock(&adapter->ahw.mem_lock); 1662 1663 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO)); 1664 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI)); 1665 1666 writel(data & 0xffffffff, 1667 mem_crb + MIU_TEST_AGT_WRDATA_LO); 1668 writel((data >> 32) & 0xffffffff, 1669 mem_crb + MIU_TEST_AGT_WRDATA_HI); 1670 1671 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL)); 1672 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE), 1673 (mem_crb + TEST_AGT_CTRL)); 1674 1675 for (j = 0; j < MAX_CTL_CHECK; j++) { 1676 temp = readl(mem_crb + TEST_AGT_CTRL); 1677 if ((temp & TA_CTL_BUSY) == 0) 1678 break; 1679 } 1680 1681 if (j >= MAX_CTL_CHECK) { 1682 if (printk_ratelimit()) 1683 dev_err(&adapter->pdev->dev, 1684 "failed to write through agent\n"); 1685 ret = -EIO; 1686 } else 1687 ret = 0; 1688 1689 spin_unlock(&adapter->ahw.mem_lock); 1690 1691 return ret; 1692 } 1693 1694 static int 1695 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter, 1696 u64 off, u64 *data) 1697 { 1698 int j, ret; 1699 u32 temp, off8; 1700 u64 val; 1701 void __iomem *mem_crb; 1702 1703 /* Only 64-bit aligned access */ 1704 if (off & 7) 1705 return -EIO; 1706 1707 /* P3 onward, test agent base for MIU and SIU is same */ 1708 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, 1709 NETXEN_ADDR_QDR_NET_MAX_P3)) { 1710 mem_crb = netxen_get_ioaddr(adapter, 1711 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE); 1712 goto correct; 1713 } 1714 1715 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { 1716 mem_crb = netxen_get_ioaddr(adapter, 1717 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE); 1718 goto correct; 1719 } 1720 1721 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { 1722 return netxen_nic_pci_mem_access_direct(adapter, 1723 off, data, 0); 1724 } 1725 1726 return -EIO; 1727 1728 correct: 1729 off8 = off & 0xfffffff8; 1730 1731 spin_lock(&adapter->ahw.mem_lock); 1732 1733 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO)); 1734 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI)); 1735 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL)); 1736 writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL)); 1737 1738 for (j = 0; j < MAX_CTL_CHECK; j++) { 1739 temp = readl(mem_crb + TEST_AGT_CTRL); 1740 if ((temp & TA_CTL_BUSY) == 0) 1741 break; 1742 } 1743 1744 if (j >= MAX_CTL_CHECK) { 1745 if (printk_ratelimit()) 1746 dev_err(&adapter->pdev->dev, 1747 "failed to read through agent\n"); 1748 ret = -EIO; 1749 } else { 1750 val = (u64)(readl(mem_crb + MIU_TEST_AGT_RDDATA_HI)) << 32; 1751 val |= readl(mem_crb + MIU_TEST_AGT_RDDATA_LO); 1752 *data = val; 1753 ret = 0; 1754 } 1755 1756 spin_unlock(&adapter->ahw.mem_lock); 1757 1758 return ret; 1759 } 1760 1761 void 1762 netxen_setup_hwops(struct netxen_adapter *adapter) 1763 { 1764 adapter->init_port = netxen_niu_xg_init_port; 1765 adapter->stop_port = netxen_niu_disable_xg_port; 1766 1767 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { 1768 adapter->crb_read = netxen_nic_hw_read_wx_128M, 1769 adapter->crb_write = netxen_nic_hw_write_wx_128M, 1770 adapter->pci_set_window = netxen_nic_pci_set_window_128M, 1771 adapter->pci_mem_read = netxen_nic_pci_mem_read_128M, 1772 adapter->pci_mem_write = netxen_nic_pci_mem_write_128M, 1773 adapter->io_read = netxen_nic_io_read_128M, 1774 adapter->io_write = netxen_nic_io_write_128M, 1775 1776 adapter->macaddr_set = netxen_p2_nic_set_mac_addr; 1777 adapter->set_multi = netxen_p2_nic_set_multi; 1778 adapter->set_mtu = netxen_nic_set_mtu_xgb; 1779 adapter->set_promisc = netxen_p2_nic_set_promisc; 1780 1781 } else { 1782 adapter->crb_read = netxen_nic_hw_read_wx_2M, 1783 adapter->crb_write = netxen_nic_hw_write_wx_2M, 1784 adapter->pci_set_window = netxen_nic_pci_set_window_2M, 1785 adapter->pci_mem_read = netxen_nic_pci_mem_read_2M, 1786 adapter->pci_mem_write = netxen_nic_pci_mem_write_2M, 1787 adapter->io_read = netxen_nic_io_read_2M, 1788 adapter->io_write = netxen_nic_io_write_2M, 1789 1790 adapter->set_mtu = nx_fw_cmd_set_mtu; 1791 adapter->set_promisc = netxen_p3_nic_set_promisc; 1792 adapter->macaddr_set = netxen_p3_nic_set_mac_addr; 1793 adapter->set_multi = netxen_p3_nic_set_multi; 1794 1795 adapter->phy_read = nx_fw_cmd_query_phy; 1796 adapter->phy_write = nx_fw_cmd_set_phy; 1797 } 1798 } 1799 1800 int netxen_nic_get_board_info(struct netxen_adapter *adapter) 1801 { 1802 int offset, board_type, magic; 1803 struct pci_dev *pdev = adapter->pdev; 1804 1805 offset = NX_FW_MAGIC_OFFSET; 1806 if (netxen_rom_fast_read(adapter, offset, &magic)) 1807 return -EIO; 1808 1809 if (magic != NETXEN_BDINFO_MAGIC) { 1810 dev_err(&pdev->dev, "invalid board config, magic=%08x\n", 1811 magic); 1812 return -EIO; 1813 } 1814 1815 offset = NX_BRDTYPE_OFFSET; 1816 if (netxen_rom_fast_read(adapter, offset, &board_type)) 1817 return -EIO; 1818 1819 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) { 1820 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I); 1821 if ((gpio & 0x8000) == 0) 1822 board_type = NETXEN_BRDTYPE_P3_10G_TP; 1823 } 1824 1825 adapter->ahw.board_type = board_type; 1826 1827 switch (board_type) { 1828 case NETXEN_BRDTYPE_P2_SB35_4G: 1829 adapter->ahw.port_type = NETXEN_NIC_GBE; 1830 break; 1831 case NETXEN_BRDTYPE_P2_SB31_10G: 1832 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ: 1833 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ: 1834 case NETXEN_BRDTYPE_P2_SB31_10G_CX4: 1835 case NETXEN_BRDTYPE_P3_HMEZ: 1836 case NETXEN_BRDTYPE_P3_XG_LOM: 1837 case NETXEN_BRDTYPE_P3_10G_CX4: 1838 case NETXEN_BRDTYPE_P3_10G_CX4_LP: 1839 case NETXEN_BRDTYPE_P3_IMEZ: 1840 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS: 1841 case NETXEN_BRDTYPE_P3_10G_SFP_CT: 1842 case NETXEN_BRDTYPE_P3_10G_SFP_QT: 1843 case NETXEN_BRDTYPE_P3_10G_XFP: 1844 case NETXEN_BRDTYPE_P3_10000_BASE_T: 1845 adapter->ahw.port_type = NETXEN_NIC_XGBE; 1846 break; 1847 case NETXEN_BRDTYPE_P1_BD: 1848 case NETXEN_BRDTYPE_P1_SB: 1849 case NETXEN_BRDTYPE_P1_SMAX: 1850 case NETXEN_BRDTYPE_P1_SOCK: 1851 case NETXEN_BRDTYPE_P3_REF_QG: 1852 case NETXEN_BRDTYPE_P3_4_GB: 1853 case NETXEN_BRDTYPE_P3_4_GB_MM: 1854 adapter->ahw.port_type = NETXEN_NIC_GBE; 1855 break; 1856 case NETXEN_BRDTYPE_P3_10G_TP: 1857 adapter->ahw.port_type = (adapter->portnum < 2) ? 1858 NETXEN_NIC_XGBE : NETXEN_NIC_GBE; 1859 break; 1860 default: 1861 dev_err(&pdev->dev, "unknown board type %x\n", board_type); 1862 adapter->ahw.port_type = NETXEN_NIC_XGBE; 1863 break; 1864 } 1865 1866 return 0; 1867 } 1868 1869 /* NIU access sections */ 1870 static int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu) 1871 { 1872 new_mtu += MTU_FUDGE_FACTOR; 1873 if (adapter->physical_port == 0) 1874 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu); 1875 else 1876 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu); 1877 return 0; 1878 } 1879 1880 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter) 1881 { 1882 __u32 status; 1883 __u32 autoneg; 1884 __u32 port_mode; 1885 1886 if (!netif_carrier_ok(adapter->netdev)) { 1887 adapter->link_speed = 0; 1888 adapter->link_duplex = -1; 1889 adapter->link_autoneg = AUTONEG_ENABLE; 1890 return; 1891 } 1892 1893 if (adapter->ahw.port_type == NETXEN_NIC_GBE) { 1894 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR); 1895 if (port_mode == NETXEN_PORT_MODE_802_3_AP) { 1896 adapter->link_speed = SPEED_1000; 1897 adapter->link_duplex = DUPLEX_FULL; 1898 adapter->link_autoneg = AUTONEG_DISABLE; 1899 return; 1900 } 1901 1902 if (adapter->phy_read && 1903 adapter->phy_read(adapter, 1904 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS, 1905 &status) == 0) { 1906 if (netxen_get_phy_link(status)) { 1907 switch (netxen_get_phy_speed(status)) { 1908 case 0: 1909 adapter->link_speed = SPEED_10; 1910 break; 1911 case 1: 1912 adapter->link_speed = SPEED_100; 1913 break; 1914 case 2: 1915 adapter->link_speed = SPEED_1000; 1916 break; 1917 default: 1918 adapter->link_speed = 0; 1919 break; 1920 } 1921 switch (netxen_get_phy_duplex(status)) { 1922 case 0: 1923 adapter->link_duplex = DUPLEX_HALF; 1924 break; 1925 case 1: 1926 adapter->link_duplex = DUPLEX_FULL; 1927 break; 1928 default: 1929 adapter->link_duplex = -1; 1930 break; 1931 } 1932 if (adapter->phy_read && 1933 adapter->phy_read(adapter, 1934 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG, 1935 &autoneg) == 0) 1936 adapter->link_autoneg = autoneg; 1937 } else 1938 goto link_down; 1939 } else { 1940 link_down: 1941 adapter->link_speed = 0; 1942 adapter->link_duplex = -1; 1943 } 1944 } 1945 } 1946 1947 int 1948 netxen_nic_wol_supported(struct netxen_adapter *adapter) 1949 { 1950 u32 wol_cfg; 1951 1952 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) 1953 return 0; 1954 1955 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV); 1956 if (wol_cfg & (1UL << adapter->portnum)) { 1957 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG); 1958 if (wol_cfg & (1 << adapter->portnum)) 1959 return 1; 1960 } 1961 1962 return 0; 1963 } 1964 1965 static u32 netxen_md_cntrl(struct netxen_adapter *adapter, 1966 struct netxen_minidump_template_hdr *template_hdr, 1967 struct netxen_minidump_entry_crb *crtEntry) 1968 { 1969 int loop_cnt, i, rv = 0, timeout_flag; 1970 u32 op_count, stride; 1971 u32 opcode, read_value, addr; 1972 unsigned long timeout, timeout_jiffies; 1973 addr = crtEntry->addr; 1974 op_count = crtEntry->op_count; 1975 stride = crtEntry->addr_stride; 1976 1977 for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) { 1978 for (i = 0; i < sizeof(crtEntry->opcode) * 8; i++) { 1979 opcode = (crtEntry->opcode & (0x1 << i)); 1980 if (opcode) { 1981 switch (opcode) { 1982 case NX_DUMP_WCRB: 1983 NX_WR_DUMP_REG(addr, 1984 adapter->ahw.pci_base0, 1985 crtEntry->value_1); 1986 break; 1987 case NX_DUMP_RWCRB: 1988 NX_RD_DUMP_REG(addr, 1989 adapter->ahw.pci_base0, 1990 &read_value); 1991 NX_WR_DUMP_REG(addr, 1992 adapter->ahw.pci_base0, 1993 read_value); 1994 break; 1995 case NX_DUMP_ANDCRB: 1996 NX_RD_DUMP_REG(addr, 1997 adapter->ahw.pci_base0, 1998 &read_value); 1999 read_value &= crtEntry->value_2; 2000 NX_WR_DUMP_REG(addr, 2001 adapter->ahw.pci_base0, 2002 read_value); 2003 break; 2004 case NX_DUMP_ORCRB: 2005 NX_RD_DUMP_REG(addr, 2006 adapter->ahw.pci_base0, 2007 &read_value); 2008 read_value |= crtEntry->value_3; 2009 NX_WR_DUMP_REG(addr, 2010 adapter->ahw.pci_base0, 2011 read_value); 2012 break; 2013 case NX_DUMP_POLLCRB: 2014 timeout = crtEntry->poll_timeout; 2015 NX_RD_DUMP_REG(addr, 2016 adapter->ahw.pci_base0, 2017 &read_value); 2018 timeout_jiffies = 2019 msecs_to_jiffies(timeout) + jiffies; 2020 for (timeout_flag = 0; 2021 !timeout_flag 2022 && ((read_value & crtEntry->value_2) 2023 != crtEntry->value_1);) { 2024 if (time_after(jiffies, 2025 timeout_jiffies)) 2026 timeout_flag = 1; 2027 NX_RD_DUMP_REG(addr, 2028 adapter->ahw.pci_base0, 2029 &read_value); 2030 } 2031 2032 if (timeout_flag) { 2033 dev_err(&adapter->pdev->dev, "%s : " 2034 "Timeout in poll_crb control operation.\n" 2035 , __func__); 2036 return -1; 2037 } 2038 break; 2039 case NX_DUMP_RD_SAVE: 2040 /* Decide which address to use */ 2041 if (crtEntry->state_index_a) 2042 addr = 2043 template_hdr->saved_state_array 2044 [crtEntry->state_index_a]; 2045 NX_RD_DUMP_REG(addr, 2046 adapter->ahw.pci_base0, 2047 &read_value); 2048 template_hdr->saved_state_array 2049 [crtEntry->state_index_v] 2050 = read_value; 2051 break; 2052 case NX_DUMP_WRT_SAVED: 2053 /* Decide which value to use */ 2054 if (crtEntry->state_index_v) 2055 read_value = 2056 template_hdr->saved_state_array 2057 [crtEntry->state_index_v]; 2058 else 2059 read_value = crtEntry->value_1; 2060 2061 /* Decide which address to use */ 2062 if (crtEntry->state_index_a) 2063 addr = 2064 template_hdr->saved_state_array 2065 [crtEntry->state_index_a]; 2066 2067 NX_WR_DUMP_REG(addr, 2068 adapter->ahw.pci_base0, 2069 read_value); 2070 break; 2071 case NX_DUMP_MOD_SAVE_ST: 2072 read_value = 2073 template_hdr->saved_state_array 2074 [crtEntry->state_index_v]; 2075 read_value <<= crtEntry->shl; 2076 read_value >>= crtEntry->shr; 2077 if (crtEntry->value_2) 2078 read_value &= 2079 crtEntry->value_2; 2080 read_value |= crtEntry->value_3; 2081 read_value += crtEntry->value_1; 2082 /* Write value back to state area.*/ 2083 template_hdr->saved_state_array 2084 [crtEntry->state_index_v] 2085 = read_value; 2086 break; 2087 default: 2088 rv = 1; 2089 break; 2090 } 2091 } 2092 } 2093 addr = addr + stride; 2094 } 2095 return rv; 2096 } 2097 2098 /* Read memory or MN */ 2099 static u32 2100 netxen_md_rdmem(struct netxen_adapter *adapter, 2101 struct netxen_minidump_entry_rdmem 2102 *memEntry, u64 *data_buff) 2103 { 2104 u64 addr, value = 0; 2105 int i = 0, loop_cnt; 2106 2107 addr = (u64)memEntry->read_addr; 2108 loop_cnt = memEntry->read_data_size; /* This is size in bytes */ 2109 loop_cnt /= sizeof(value); 2110 2111 for (i = 0; i < loop_cnt; i++) { 2112 if (netxen_nic_pci_mem_read_2M(adapter, addr, &value)) 2113 goto out; 2114 *data_buff++ = value; 2115 addr += sizeof(value); 2116 } 2117 out: 2118 return i * sizeof(value); 2119 } 2120 2121 /* Read CRB operation */ 2122 static u32 netxen_md_rd_crb(struct netxen_adapter *adapter, 2123 struct netxen_minidump_entry_crb 2124 *crbEntry, u32 *data_buff) 2125 { 2126 int loop_cnt; 2127 u32 op_count, addr, stride, value; 2128 2129 addr = crbEntry->addr; 2130 op_count = crbEntry->op_count; 2131 stride = crbEntry->addr_stride; 2132 2133 for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) { 2134 NX_RD_DUMP_REG(addr, adapter->ahw.pci_base0, &value); 2135 *data_buff++ = addr; 2136 *data_buff++ = value; 2137 addr = addr + stride; 2138 } 2139 return loop_cnt * (2 * sizeof(u32)); 2140 } 2141 2142 /* Read ROM */ 2143 static u32 2144 netxen_md_rdrom(struct netxen_adapter *adapter, 2145 struct netxen_minidump_entry_rdrom 2146 *romEntry, __le32 *data_buff) 2147 { 2148 int i, count = 0; 2149 u32 size, lck_val; 2150 u32 val; 2151 u32 fl_addr, waddr, raddr; 2152 fl_addr = romEntry->read_addr; 2153 size = romEntry->read_data_size/4; 2154 lock_try: 2155 lck_val = readl((void __iomem *)(adapter->ahw.pci_base0 + 2156 NX_FLASH_SEM2_LK)); 2157 if (!lck_val && count < MAX_CTL_CHECK) { 2158 msleep(20); 2159 count++; 2160 goto lock_try; 2161 } 2162 writel(adapter->ahw.pci_func, (void __iomem *)(adapter->ahw.pci_base0 + 2163 NX_FLASH_LOCK_ID)); 2164 for (i = 0; i < size; i++) { 2165 waddr = fl_addr & 0xFFFF0000; 2166 NX_WR_DUMP_REG(FLASH_ROM_WINDOW, adapter->ahw.pci_base0, waddr); 2167 raddr = FLASH_ROM_DATA + (fl_addr & 0x0000FFFF); 2168 NX_RD_DUMP_REG(raddr, adapter->ahw.pci_base0, &val); 2169 *data_buff++ = cpu_to_le32(val); 2170 fl_addr += sizeof(val); 2171 } 2172 readl((void __iomem *)(adapter->ahw.pci_base0 + NX_FLASH_SEM2_ULK)); 2173 return romEntry->read_data_size; 2174 } 2175 2176 /* Handle L2 Cache */ 2177 static u32 2178 netxen_md_L2Cache(struct netxen_adapter *adapter, 2179 struct netxen_minidump_entry_cache 2180 *cacheEntry, u32 *data_buff) 2181 { 2182 int loop_cnt, i, k, timeout_flag = 0; 2183 u32 addr, read_addr, read_value, cntrl_addr, tag_reg_addr; 2184 u32 tag_value, read_cnt; 2185 u8 cntl_value_w, cntl_value_r; 2186 unsigned long timeout, timeout_jiffies; 2187 2188 loop_cnt = cacheEntry->op_count; 2189 read_addr = cacheEntry->read_addr; 2190 cntrl_addr = cacheEntry->control_addr; 2191 cntl_value_w = (u32) cacheEntry->write_value; 2192 tag_reg_addr = cacheEntry->tag_reg_addr; 2193 tag_value = cacheEntry->init_tag_value; 2194 read_cnt = cacheEntry->read_addr_cnt; 2195 2196 for (i = 0; i < loop_cnt; i++) { 2197 NX_WR_DUMP_REG(tag_reg_addr, adapter->ahw.pci_base0, tag_value); 2198 if (cntl_value_w) 2199 NX_WR_DUMP_REG(cntrl_addr, adapter->ahw.pci_base0, 2200 (u32)cntl_value_w); 2201 if (cacheEntry->poll_mask) { 2202 timeout = cacheEntry->poll_wait; 2203 NX_RD_DUMP_REG(cntrl_addr, adapter->ahw.pci_base0, 2204 &cntl_value_r); 2205 timeout_jiffies = msecs_to_jiffies(timeout) + jiffies; 2206 for (timeout_flag = 0; !timeout_flag && 2207 ((cntl_value_r & cacheEntry->poll_mask) != 0);) { 2208 if (time_after(jiffies, timeout_jiffies)) 2209 timeout_flag = 1; 2210 NX_RD_DUMP_REG(cntrl_addr, 2211 adapter->ahw.pci_base0, 2212 &cntl_value_r); 2213 } 2214 if (timeout_flag) { 2215 dev_err(&adapter->pdev->dev, 2216 "Timeout in processing L2 Tag poll.\n"); 2217 return -1; 2218 } 2219 } 2220 addr = read_addr; 2221 for (k = 0; k < read_cnt; k++) { 2222 NX_RD_DUMP_REG(addr, adapter->ahw.pci_base0, 2223 &read_value); 2224 *data_buff++ = read_value; 2225 addr += cacheEntry->read_addr_stride; 2226 } 2227 tag_value += cacheEntry->tag_value_stride; 2228 } 2229 return read_cnt * loop_cnt * sizeof(read_value); 2230 } 2231 2232 2233 /* Handle L1 Cache */ 2234 static u32 netxen_md_L1Cache(struct netxen_adapter *adapter, 2235 struct netxen_minidump_entry_cache 2236 *cacheEntry, u32 *data_buff) 2237 { 2238 int i, k, loop_cnt; 2239 u32 addr, read_addr, read_value, cntrl_addr, tag_reg_addr; 2240 u32 tag_value, read_cnt; 2241 u8 cntl_value_w; 2242 2243 loop_cnt = cacheEntry->op_count; 2244 read_addr = cacheEntry->read_addr; 2245 cntrl_addr = cacheEntry->control_addr; 2246 cntl_value_w = (u32) cacheEntry->write_value; 2247 tag_reg_addr = cacheEntry->tag_reg_addr; 2248 tag_value = cacheEntry->init_tag_value; 2249 read_cnt = cacheEntry->read_addr_cnt; 2250 2251 for (i = 0; i < loop_cnt; i++) { 2252 NX_WR_DUMP_REG(tag_reg_addr, adapter->ahw.pci_base0, tag_value); 2253 NX_WR_DUMP_REG(cntrl_addr, adapter->ahw.pci_base0, 2254 (u32) cntl_value_w); 2255 addr = read_addr; 2256 for (k = 0; k < read_cnt; k++) { 2257 NX_RD_DUMP_REG(addr, 2258 adapter->ahw.pci_base0, 2259 &read_value); 2260 *data_buff++ = read_value; 2261 addr += cacheEntry->read_addr_stride; 2262 } 2263 tag_value += cacheEntry->tag_value_stride; 2264 } 2265 return read_cnt * loop_cnt * sizeof(read_value); 2266 } 2267 2268 /* Reading OCM memory */ 2269 static u32 2270 netxen_md_rdocm(struct netxen_adapter *adapter, 2271 struct netxen_minidump_entry_rdocm 2272 *ocmEntry, u32 *data_buff) 2273 { 2274 int i, loop_cnt; 2275 u32 value; 2276 void __iomem *addr; 2277 addr = (ocmEntry->read_addr + adapter->ahw.pci_base0); 2278 loop_cnt = ocmEntry->op_count; 2279 2280 for (i = 0; i < loop_cnt; i++) { 2281 value = readl(addr); 2282 *data_buff++ = value; 2283 addr += ocmEntry->read_addr_stride; 2284 } 2285 return i * sizeof(u32); 2286 } 2287 2288 /* Read MUX data */ 2289 static u32 2290 netxen_md_rdmux(struct netxen_adapter *adapter, struct netxen_minidump_entry_mux 2291 *muxEntry, u32 *data_buff) 2292 { 2293 int loop_cnt = 0; 2294 u32 read_addr, read_value, select_addr, sel_value; 2295 2296 read_addr = muxEntry->read_addr; 2297 sel_value = muxEntry->select_value; 2298 select_addr = muxEntry->select_addr; 2299 2300 for (loop_cnt = 0; loop_cnt < muxEntry->op_count; loop_cnt++) { 2301 NX_WR_DUMP_REG(select_addr, adapter->ahw.pci_base0, sel_value); 2302 NX_RD_DUMP_REG(read_addr, adapter->ahw.pci_base0, &read_value); 2303 *data_buff++ = sel_value; 2304 *data_buff++ = read_value; 2305 sel_value += muxEntry->select_value_stride; 2306 } 2307 return loop_cnt * (2 * sizeof(u32)); 2308 } 2309 2310 /* Handling Queue State Reads */ 2311 static u32 2312 netxen_md_rdqueue(struct netxen_adapter *adapter, 2313 struct netxen_minidump_entry_queue 2314 *queueEntry, u32 *data_buff) 2315 { 2316 int loop_cnt, k; 2317 u32 queue_id, read_addr, read_value, read_stride, select_addr, read_cnt; 2318 2319 read_cnt = queueEntry->read_addr_cnt; 2320 read_stride = queueEntry->read_addr_stride; 2321 select_addr = queueEntry->select_addr; 2322 2323 for (loop_cnt = 0, queue_id = 0; loop_cnt < queueEntry->op_count; 2324 loop_cnt++) { 2325 NX_WR_DUMP_REG(select_addr, adapter->ahw.pci_base0, queue_id); 2326 read_addr = queueEntry->read_addr; 2327 for (k = 0; k < read_cnt; k--) { 2328 NX_RD_DUMP_REG(read_addr, adapter->ahw.pci_base0, 2329 &read_value); 2330 *data_buff++ = read_value; 2331 read_addr += read_stride; 2332 } 2333 queue_id += queueEntry->queue_id_stride; 2334 } 2335 return loop_cnt * (read_cnt * sizeof(read_value)); 2336 } 2337 2338 2339 /* 2340 * We catch an error where driver does not read 2341 * as much data as we expect from the entry. 2342 */ 2343 2344 static int netxen_md_entry_err_chk(struct netxen_adapter *adapter, 2345 struct netxen_minidump_entry *entry, int esize) 2346 { 2347 if (esize < 0) { 2348 entry->hdr.driver_flags |= NX_DUMP_SKIP; 2349 return esize; 2350 } 2351 if (esize != entry->hdr.entry_capture_size) { 2352 entry->hdr.entry_capture_size = esize; 2353 entry->hdr.driver_flags |= NX_DUMP_SIZE_ERR; 2354 dev_info(&adapter->pdev->dev, 2355 "Invalidate dump, Type:%d\tMask:%d\tSize:%dCap_size:%d\n", 2356 entry->hdr.entry_type, entry->hdr.entry_capture_mask, 2357 esize, entry->hdr.entry_capture_size); 2358 dev_info(&adapter->pdev->dev, "Aborting further dump capture\n"); 2359 } 2360 return 0; 2361 } 2362 2363 static int netxen_parse_md_template(struct netxen_adapter *adapter) 2364 { 2365 int num_of_entries, buff_level, e_cnt, esize; 2366 int end_cnt = 0, rv = 0, sane_start = 0, sane_end = 0; 2367 char *dbuff; 2368 void *template_buff = adapter->mdump.md_template; 2369 char *dump_buff = adapter->mdump.md_capture_buff; 2370 int capture_mask = adapter->mdump.md_capture_mask; 2371 struct netxen_minidump_template_hdr *template_hdr; 2372 struct netxen_minidump_entry *entry; 2373 2374 if ((capture_mask & 0x3) != 0x3) { 2375 dev_err(&adapter->pdev->dev, "Capture mask %02x below minimum needed " 2376 "for valid firmware dump\n", capture_mask); 2377 return -EINVAL; 2378 } 2379 template_hdr = (struct netxen_minidump_template_hdr *) template_buff; 2380 num_of_entries = template_hdr->num_of_entries; 2381 entry = (struct netxen_minidump_entry *) ((char *) template_buff + 2382 template_hdr->first_entry_offset); 2383 memcpy(dump_buff, template_buff, adapter->mdump.md_template_size); 2384 dump_buff = dump_buff + adapter->mdump.md_template_size; 2385 2386 if (template_hdr->entry_type == TLHDR) 2387 sane_start = 1; 2388 2389 for (e_cnt = 0, buff_level = 0; e_cnt < num_of_entries; e_cnt++) { 2390 if (!(entry->hdr.entry_capture_mask & capture_mask)) { 2391 entry->hdr.driver_flags |= NX_DUMP_SKIP; 2392 entry = (struct netxen_minidump_entry *) 2393 ((char *) entry + entry->hdr.entry_size); 2394 continue; 2395 } 2396 switch (entry->hdr.entry_type) { 2397 case RDNOP: 2398 entry->hdr.driver_flags |= NX_DUMP_SKIP; 2399 break; 2400 case RDEND: 2401 entry->hdr.driver_flags |= NX_DUMP_SKIP; 2402 if (!sane_end) 2403 end_cnt = e_cnt; 2404 sane_end += 1; 2405 break; 2406 case CNTRL: 2407 rv = netxen_md_cntrl(adapter, 2408 template_hdr, (void *)entry); 2409 if (rv) 2410 entry->hdr.driver_flags |= NX_DUMP_SKIP; 2411 break; 2412 case RDCRB: 2413 dbuff = dump_buff + buff_level; 2414 esize = netxen_md_rd_crb(adapter, 2415 (void *) entry, (void *) dbuff); 2416 rv = netxen_md_entry_err_chk 2417 (adapter, entry, esize); 2418 if (rv < 0) 2419 break; 2420 buff_level += esize; 2421 break; 2422 case RDMN: 2423 case RDMEM: 2424 dbuff = dump_buff + buff_level; 2425 esize = netxen_md_rdmem(adapter, 2426 (void *) entry, (void *) dbuff); 2427 rv = netxen_md_entry_err_chk 2428 (adapter, entry, esize); 2429 if (rv < 0) 2430 break; 2431 buff_level += esize; 2432 break; 2433 case BOARD: 2434 case RDROM: 2435 dbuff = dump_buff + buff_level; 2436 esize = netxen_md_rdrom(adapter, 2437 (void *) entry, (void *) dbuff); 2438 rv = netxen_md_entry_err_chk 2439 (adapter, entry, esize); 2440 if (rv < 0) 2441 break; 2442 buff_level += esize; 2443 break; 2444 case L2ITG: 2445 case L2DTG: 2446 case L2DAT: 2447 case L2INS: 2448 dbuff = dump_buff + buff_level; 2449 esize = netxen_md_L2Cache(adapter, 2450 (void *) entry, (void *) dbuff); 2451 rv = netxen_md_entry_err_chk 2452 (adapter, entry, esize); 2453 if (rv < 0) 2454 break; 2455 buff_level += esize; 2456 break; 2457 case L1DAT: 2458 case L1INS: 2459 dbuff = dump_buff + buff_level; 2460 esize = netxen_md_L1Cache(adapter, 2461 (void *) entry, (void *) dbuff); 2462 rv = netxen_md_entry_err_chk 2463 (adapter, entry, esize); 2464 if (rv < 0) 2465 break; 2466 buff_level += esize; 2467 break; 2468 case RDOCM: 2469 dbuff = dump_buff + buff_level; 2470 esize = netxen_md_rdocm(adapter, 2471 (void *) entry, (void *) dbuff); 2472 rv = netxen_md_entry_err_chk 2473 (adapter, entry, esize); 2474 if (rv < 0) 2475 break; 2476 buff_level += esize; 2477 break; 2478 case RDMUX: 2479 dbuff = dump_buff + buff_level; 2480 esize = netxen_md_rdmux(adapter, 2481 (void *) entry, (void *) dbuff); 2482 rv = netxen_md_entry_err_chk 2483 (adapter, entry, esize); 2484 if (rv < 0) 2485 break; 2486 buff_level += esize; 2487 break; 2488 case QUEUE: 2489 dbuff = dump_buff + buff_level; 2490 esize = netxen_md_rdqueue(adapter, 2491 (void *) entry, (void *) dbuff); 2492 rv = netxen_md_entry_err_chk 2493 (adapter, entry, esize); 2494 if (rv < 0) 2495 break; 2496 buff_level += esize; 2497 break; 2498 default: 2499 entry->hdr.driver_flags |= NX_DUMP_SKIP; 2500 break; 2501 } 2502 /* Next entry in the template */ 2503 entry = (struct netxen_minidump_entry *) 2504 ((char *) entry + entry->hdr.entry_size); 2505 } 2506 if (!sane_start || sane_end > 1) { 2507 dev_err(&adapter->pdev->dev, 2508 "Firmware minidump template configuration error.\n"); 2509 } 2510 return 0; 2511 } 2512 2513 static int 2514 netxen_collect_minidump(struct netxen_adapter *adapter) 2515 { 2516 int ret = 0; 2517 struct netxen_minidump_template_hdr *hdr; 2518 struct timespec val; 2519 hdr = (struct netxen_minidump_template_hdr *) 2520 adapter->mdump.md_template; 2521 hdr->driver_capture_mask = adapter->mdump.md_capture_mask; 2522 jiffies_to_timespec(jiffies, &val); 2523 hdr->driver_timestamp = (u32) val.tv_sec; 2524 hdr->driver_info_word2 = adapter->fw_version; 2525 hdr->driver_info_word3 = NXRD32(adapter, CRB_DRIVER_VERSION); 2526 ret = netxen_parse_md_template(adapter); 2527 if (ret) 2528 return ret; 2529 2530 return ret; 2531 } 2532 2533 2534 void 2535 netxen_dump_fw(struct netxen_adapter *adapter) 2536 { 2537 struct netxen_minidump_template_hdr *hdr; 2538 int i, k, data_size = 0; 2539 u32 capture_mask; 2540 hdr = (struct netxen_minidump_template_hdr *) 2541 adapter->mdump.md_template; 2542 capture_mask = adapter->mdump.md_capture_mask; 2543 2544 for (i = 0x2, k = 1; (i & NX_DUMP_MASK_MAX); i <<= 1, k++) { 2545 if (i & capture_mask) 2546 data_size += hdr->capture_size_array[k]; 2547 } 2548 if (!data_size) { 2549 dev_err(&adapter->pdev->dev, 2550 "Invalid cap sizes for capture_mask=0x%x\n", 2551 adapter->mdump.md_capture_mask); 2552 return; 2553 } 2554 adapter->mdump.md_capture_size = data_size; 2555 adapter->mdump.md_dump_size = adapter->mdump.md_template_size + 2556 adapter->mdump.md_capture_size; 2557 if (!adapter->mdump.md_capture_buff) { 2558 adapter->mdump.md_capture_buff = 2559 vzalloc(adapter->mdump.md_dump_size); 2560 if (!adapter->mdump.md_capture_buff) 2561 return; 2562 2563 if (netxen_collect_minidump(adapter)) { 2564 adapter->mdump.has_valid_dump = 0; 2565 adapter->mdump.md_dump_size = 0; 2566 vfree(adapter->mdump.md_capture_buff); 2567 adapter->mdump.md_capture_buff = NULL; 2568 dev_err(&adapter->pdev->dev, 2569 "Error in collecting firmware minidump.\n"); 2570 } else { 2571 adapter->mdump.md_timestamp = jiffies; 2572 adapter->mdump.has_valid_dump = 1; 2573 adapter->fw_mdump_rdy = 1; 2574 dev_info(&adapter->pdev->dev, "%s Successfully " 2575 "collected fw dump.\n", adapter->netdev->name); 2576 } 2577 2578 } else { 2579 dev_info(&adapter->pdev->dev, 2580 "Cannot overwrite previously collected " 2581 "firmware minidump.\n"); 2582 adapter->fw_mdump_rdy = 1; 2583 return; 2584 } 2585 } 2586