1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/ip.h> 5 #include <linux/ipv6.h> 6 #include <linux/if_vlan.h> 7 #include <net/ip6_checksum.h> 8 9 #include "ionic.h" 10 #include "ionic_lif.h" 11 #include "ionic_txrx.h" 12 13 static void ionic_rx_clean(struct ionic_queue *q, 14 struct ionic_desc_info *desc_info, 15 struct ionic_cq_info *cq_info, 16 void *cb_arg); 17 18 static bool ionic_rx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info); 19 20 static bool ionic_tx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info); 21 22 static inline void ionic_txq_post(struct ionic_queue *q, bool ring_dbell, 23 ionic_desc_cb cb_func, void *cb_arg) 24 { 25 DEBUG_STATS_TXQ_POST(q, ring_dbell); 26 27 ionic_q_post(q, ring_dbell, cb_func, cb_arg); 28 } 29 30 static inline void ionic_rxq_post(struct ionic_queue *q, bool ring_dbell, 31 ionic_desc_cb cb_func, void *cb_arg) 32 { 33 ionic_q_post(q, ring_dbell, cb_func, cb_arg); 34 35 DEBUG_STATS_RX_BUFF_CNT(q); 36 } 37 38 static inline struct netdev_queue *q_to_ndq(struct ionic_queue *q) 39 { 40 return netdev_get_tx_queue(q->lif->netdev, q->index); 41 } 42 43 static struct sk_buff *ionic_rx_skb_alloc(struct ionic_queue *q, 44 unsigned int len, bool frags) 45 { 46 struct ionic_lif *lif = q->lif; 47 struct ionic_rx_stats *stats; 48 struct net_device *netdev; 49 struct sk_buff *skb; 50 51 netdev = lif->netdev; 52 stats = &q->lif->rxqstats[q->index]; 53 54 if (frags) 55 skb = napi_get_frags(&q_to_qcq(q)->napi); 56 else 57 skb = netdev_alloc_skb_ip_align(netdev, len); 58 59 if (unlikely(!skb)) { 60 net_warn_ratelimited("%s: SKB alloc failed on %s!\n", 61 netdev->name, q->name); 62 stats->alloc_err++; 63 return NULL; 64 } 65 66 return skb; 67 } 68 69 static struct sk_buff *ionic_rx_frags(struct ionic_queue *q, 70 struct ionic_desc_info *desc_info, 71 struct ionic_cq_info *cq_info) 72 { 73 struct ionic_rxq_comp *comp = cq_info->cq_desc; 74 struct device *dev = q->lif->ionic->dev; 75 struct ionic_page_info *page_info; 76 struct sk_buff *skb; 77 unsigned int i; 78 u16 frag_len; 79 u16 len; 80 81 page_info = &desc_info->pages[0]; 82 len = le16_to_cpu(comp->len); 83 84 prefetch(page_address(page_info->page) + NET_IP_ALIGN); 85 86 skb = ionic_rx_skb_alloc(q, len, true); 87 if (unlikely(!skb)) 88 return NULL; 89 90 i = comp->num_sg_elems + 1; 91 do { 92 if (unlikely(!page_info->page)) { 93 struct napi_struct *napi = &q_to_qcq(q)->napi; 94 95 napi->skb = NULL; 96 dev_kfree_skb(skb); 97 return NULL; 98 } 99 100 frag_len = min(len, (u16)PAGE_SIZE); 101 len -= frag_len; 102 103 dma_unmap_page(dev, dma_unmap_addr(page_info, dma_addr), 104 PAGE_SIZE, DMA_FROM_DEVICE); 105 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 106 page_info->page, 0, frag_len, PAGE_SIZE); 107 page_info->page = NULL; 108 page_info++; 109 i--; 110 } while (i > 0); 111 112 return skb; 113 } 114 115 static struct sk_buff *ionic_rx_copybreak(struct ionic_queue *q, 116 struct ionic_desc_info *desc_info, 117 struct ionic_cq_info *cq_info) 118 { 119 struct ionic_rxq_comp *comp = cq_info->cq_desc; 120 struct device *dev = q->lif->ionic->dev; 121 struct ionic_page_info *page_info; 122 struct sk_buff *skb; 123 u16 len; 124 125 page_info = &desc_info->pages[0]; 126 len = le16_to_cpu(comp->len); 127 128 skb = ionic_rx_skb_alloc(q, len, false); 129 if (unlikely(!skb)) 130 return NULL; 131 132 if (unlikely(!page_info->page)) { 133 dev_kfree_skb(skb); 134 return NULL; 135 } 136 137 dma_sync_single_for_cpu(dev, dma_unmap_addr(page_info, dma_addr), 138 len, DMA_FROM_DEVICE); 139 skb_copy_to_linear_data(skb, page_address(page_info->page), len); 140 dma_sync_single_for_device(dev, dma_unmap_addr(page_info, dma_addr), 141 len, DMA_FROM_DEVICE); 142 143 skb_put(skb, len); 144 skb->protocol = eth_type_trans(skb, q->lif->netdev); 145 146 return skb; 147 } 148 149 static void ionic_rx_clean(struct ionic_queue *q, 150 struct ionic_desc_info *desc_info, 151 struct ionic_cq_info *cq_info, 152 void *cb_arg) 153 { 154 struct ionic_rxq_comp *comp = cq_info->cq_desc; 155 struct ionic_qcq *qcq = q_to_qcq(q); 156 struct ionic_rx_stats *stats; 157 struct net_device *netdev; 158 struct sk_buff *skb; 159 160 stats = q_to_rx_stats(q); 161 netdev = q->lif->netdev; 162 163 if (comp->status) { 164 stats->dropped++; 165 return; 166 } 167 168 stats->pkts++; 169 stats->bytes += le16_to_cpu(comp->len); 170 171 if (le16_to_cpu(comp->len) <= q->lif->rx_copybreak) 172 skb = ionic_rx_copybreak(q, desc_info, cq_info); 173 else 174 skb = ionic_rx_frags(q, desc_info, cq_info); 175 176 if (unlikely(!skb)) { 177 stats->dropped++; 178 return; 179 } 180 181 skb_record_rx_queue(skb, q->index); 182 183 if (likely(netdev->features & NETIF_F_RXHASH)) { 184 switch (comp->pkt_type_color & IONIC_RXQ_COMP_PKT_TYPE_MASK) { 185 case IONIC_PKT_TYPE_IPV4: 186 case IONIC_PKT_TYPE_IPV6: 187 skb_set_hash(skb, le32_to_cpu(comp->rss_hash), 188 PKT_HASH_TYPE_L3); 189 break; 190 case IONIC_PKT_TYPE_IPV4_TCP: 191 case IONIC_PKT_TYPE_IPV6_TCP: 192 case IONIC_PKT_TYPE_IPV4_UDP: 193 case IONIC_PKT_TYPE_IPV6_UDP: 194 skb_set_hash(skb, le32_to_cpu(comp->rss_hash), 195 PKT_HASH_TYPE_L4); 196 break; 197 } 198 } 199 200 if (likely(netdev->features & NETIF_F_RXCSUM)) { 201 if (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_CALC) { 202 skb->ip_summed = CHECKSUM_COMPLETE; 203 skb->csum = (__wsum)le16_to_cpu(comp->csum); 204 stats->csum_complete++; 205 } 206 } else { 207 stats->csum_none++; 208 } 209 210 if (unlikely((comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_TCP_BAD) || 211 (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_UDP_BAD) || 212 (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_IP_BAD))) 213 stats->csum_error++; 214 215 if (likely(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && 216 (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_VLAN)) { 217 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 218 le16_to_cpu(comp->vlan_tci)); 219 stats->vlan_stripped++; 220 } 221 222 if (le16_to_cpu(comp->len) <= q->lif->rx_copybreak) 223 napi_gro_receive(&qcq->napi, skb); 224 else 225 napi_gro_frags(&qcq->napi); 226 } 227 228 static bool ionic_rx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info) 229 { 230 struct ionic_rxq_comp *comp = cq_info->cq_desc; 231 struct ionic_queue *q = cq->bound_q; 232 struct ionic_desc_info *desc_info; 233 234 if (!color_match(comp->pkt_type_color, cq->done_color)) 235 return false; 236 237 /* check for empty queue */ 238 if (q->tail_idx == q->head_idx) 239 return false; 240 241 desc_info = &q->info[q->tail_idx]; 242 if (desc_info->index != le16_to_cpu(comp->comp_index)) 243 return false; 244 245 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); 246 247 /* clean the related q entry, only one per qc completion */ 248 ionic_rx_clean(q, desc_info, cq_info, desc_info->cb_arg); 249 250 desc_info->cb = NULL; 251 desc_info->cb_arg = NULL; 252 253 return true; 254 } 255 256 void ionic_rx_flush(struct ionic_cq *cq) 257 { 258 struct ionic_dev *idev = &cq->lif->ionic->idev; 259 u32 work_done; 260 261 work_done = ionic_cq_service(cq, cq->num_descs, 262 ionic_rx_service, NULL, NULL); 263 264 if (work_done) 265 ionic_intr_credits(idev->intr_ctrl, cq->bound_intr->index, 266 work_done, IONIC_INTR_CRED_RESET_COALESCE); 267 } 268 269 static struct page *ionic_rx_page_alloc(struct ionic_queue *q, 270 dma_addr_t *dma_addr) 271 { 272 struct ionic_lif *lif = q->lif; 273 struct ionic_rx_stats *stats; 274 struct net_device *netdev; 275 struct device *dev; 276 struct page *page; 277 278 netdev = lif->netdev; 279 dev = lif->ionic->dev; 280 stats = q_to_rx_stats(q); 281 page = alloc_page(GFP_ATOMIC); 282 if (unlikely(!page)) { 283 net_err_ratelimited("%s: Page alloc failed on %s!\n", 284 netdev->name, q->name); 285 stats->alloc_err++; 286 return NULL; 287 } 288 289 *dma_addr = dma_map_page(dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 290 if (unlikely(dma_mapping_error(dev, *dma_addr))) { 291 __free_page(page); 292 net_err_ratelimited("%s: DMA single map failed on %s!\n", 293 netdev->name, q->name); 294 stats->dma_map_err++; 295 return NULL; 296 } 297 298 return page; 299 } 300 301 static void ionic_rx_page_free(struct ionic_queue *q, struct page *page, 302 dma_addr_t dma_addr) 303 { 304 struct ionic_lif *lif = q->lif; 305 struct net_device *netdev; 306 struct device *dev; 307 308 netdev = lif->netdev; 309 dev = lif->ionic->dev; 310 311 if (unlikely(!page)) { 312 net_err_ratelimited("%s: Trying to free unallocated buffer on %s!\n", 313 netdev->name, q->name); 314 return; 315 } 316 317 dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE); 318 319 __free_page(page); 320 } 321 322 void ionic_rx_fill(struct ionic_queue *q) 323 { 324 struct net_device *netdev = q->lif->netdev; 325 struct ionic_desc_info *desc_info; 326 struct ionic_page_info *page_info; 327 struct ionic_rxq_sg_desc *sg_desc; 328 struct ionic_rxq_sg_elem *sg_elem; 329 struct ionic_rxq_desc *desc; 330 unsigned int remain_len; 331 unsigned int seg_len; 332 unsigned int nfrags; 333 unsigned int i, j; 334 unsigned int len; 335 336 len = netdev->mtu + ETH_HLEN; 337 nfrags = round_up(len, PAGE_SIZE) / PAGE_SIZE; 338 339 for (i = ionic_q_space_avail(q); i; i--) { 340 remain_len = len; 341 desc_info = &q->info[q->head_idx]; 342 desc = desc_info->desc; 343 sg_desc = desc_info->sg_desc; 344 page_info = &desc_info->pages[0]; 345 346 if (page_info->page) { /* recycle the buffer */ 347 ionic_rxq_post(q, false, ionic_rx_clean, NULL); 348 continue; 349 } 350 351 /* fill main descriptor - pages[0] */ 352 desc->opcode = (nfrags > 1) ? IONIC_RXQ_DESC_OPCODE_SG : 353 IONIC_RXQ_DESC_OPCODE_SIMPLE; 354 desc_info->npages = nfrags; 355 page_info->page = ionic_rx_page_alloc(q, &page_info->dma_addr); 356 if (unlikely(!page_info->page)) { 357 desc->addr = 0; 358 desc->len = 0; 359 return; 360 } 361 desc->addr = cpu_to_le64(page_info->dma_addr); 362 seg_len = min_t(unsigned int, PAGE_SIZE, len); 363 desc->len = cpu_to_le16(seg_len); 364 remain_len -= seg_len; 365 page_info++; 366 367 /* fill sg descriptors - pages[1..n] */ 368 for (j = 0; j < nfrags - 1; j++) { 369 if (page_info->page) /* recycle the sg buffer */ 370 continue; 371 372 sg_elem = &sg_desc->elems[j]; 373 page_info->page = ionic_rx_page_alloc(q, &page_info->dma_addr); 374 if (unlikely(!page_info->page)) { 375 sg_elem->addr = 0; 376 sg_elem->len = 0; 377 return; 378 } 379 sg_elem->addr = cpu_to_le64(page_info->dma_addr); 380 seg_len = min_t(unsigned int, PAGE_SIZE, remain_len); 381 sg_elem->len = cpu_to_le16(seg_len); 382 remain_len -= seg_len; 383 page_info++; 384 } 385 386 ionic_rxq_post(q, false, ionic_rx_clean, NULL); 387 } 388 389 ionic_dbell_ring(q->lif->kern_dbpage, q->hw_type, 390 q->dbval | q->head_idx); 391 } 392 393 static void ionic_rx_fill_cb(void *arg) 394 { 395 ionic_rx_fill(arg); 396 } 397 398 void ionic_rx_empty(struct ionic_queue *q) 399 { 400 struct ionic_desc_info *desc_info; 401 struct ionic_rxq_desc *desc; 402 unsigned int i; 403 u16 idx; 404 405 idx = q->tail_idx; 406 while (idx != q->head_idx) { 407 desc_info = &q->info[idx]; 408 desc = desc_info->desc; 409 desc->addr = 0; 410 desc->len = 0; 411 412 for (i = 0; i < desc_info->npages; i++) { 413 if (likely(desc_info->pages[i].page)) { 414 ionic_rx_page_free(q, desc_info->pages[i].page, 415 desc_info->pages[i].dma_addr); 416 desc_info->pages[i].page = NULL; 417 desc_info->pages[i].dma_addr = 0; 418 } 419 } 420 421 desc_info->cb_arg = NULL; 422 idx = (idx + 1) & (q->num_descs - 1); 423 } 424 } 425 426 int ionic_tx_napi(struct napi_struct *napi, int budget) 427 { 428 struct ionic_qcq *qcq = napi_to_qcq(napi); 429 struct ionic_cq *cq = napi_to_cq(napi); 430 struct ionic_dev *idev; 431 struct ionic_lif *lif; 432 u32 work_done = 0; 433 u32 flags = 0; 434 435 lif = cq->bound_q->lif; 436 idev = &lif->ionic->idev; 437 438 work_done = ionic_cq_service(cq, budget, 439 ionic_tx_service, NULL, NULL); 440 441 if (work_done < budget && napi_complete_done(napi, work_done)) { 442 flags |= IONIC_INTR_CRED_UNMASK; 443 DEBUG_STATS_INTR_REARM(cq->bound_intr); 444 } 445 446 if (work_done || flags) { 447 flags |= IONIC_INTR_CRED_RESET_COALESCE; 448 ionic_intr_credits(idev->intr_ctrl, 449 cq->bound_intr->index, 450 work_done, flags); 451 } 452 453 DEBUG_STATS_NAPI_POLL(qcq, work_done); 454 455 return work_done; 456 } 457 458 int ionic_rx_napi(struct napi_struct *napi, int budget) 459 { 460 struct ionic_qcq *qcq = napi_to_qcq(napi); 461 struct ionic_cq *cq = napi_to_cq(napi); 462 struct ionic_dev *idev; 463 struct ionic_lif *lif; 464 u32 work_done = 0; 465 u32 flags = 0; 466 467 lif = cq->bound_q->lif; 468 idev = &lif->ionic->idev; 469 470 work_done = ionic_cq_service(cq, budget, 471 ionic_rx_service, NULL, NULL); 472 473 if (work_done) 474 ionic_rx_fill(cq->bound_q); 475 476 if (work_done < budget && napi_complete_done(napi, work_done)) { 477 flags |= IONIC_INTR_CRED_UNMASK; 478 DEBUG_STATS_INTR_REARM(cq->bound_intr); 479 } 480 481 if (work_done || flags) { 482 flags |= IONIC_INTR_CRED_RESET_COALESCE; 483 ionic_intr_credits(idev->intr_ctrl, 484 cq->bound_intr->index, 485 work_done, flags); 486 } 487 488 DEBUG_STATS_NAPI_POLL(qcq, work_done); 489 490 return work_done; 491 } 492 493 int ionic_txrx_napi(struct napi_struct *napi, int budget) 494 { 495 struct ionic_qcq *qcq = napi_to_qcq(napi); 496 struct ionic_cq *rxcq = napi_to_cq(napi); 497 unsigned int qi = rxcq->bound_q->index; 498 struct ionic_dev *idev; 499 struct ionic_lif *lif; 500 struct ionic_cq *txcq; 501 u32 rx_work_done = 0; 502 u32 tx_work_done = 0; 503 u32 work_done = 0; 504 u32 flags = 0; 505 bool unmask; 506 507 lif = rxcq->bound_q->lif; 508 idev = &lif->ionic->idev; 509 txcq = &lif->txqcqs[qi]->cq; 510 511 tx_work_done = ionic_cq_service(txcq, lif->tx_budget, 512 ionic_tx_service, NULL, NULL); 513 514 rx_work_done = ionic_cq_service(rxcq, budget, 515 ionic_rx_service, NULL, NULL); 516 if (rx_work_done) 517 ionic_rx_fill_cb(rxcq->bound_q); 518 519 unmask = (rx_work_done < budget) && (tx_work_done < lif->tx_budget); 520 521 if (unmask && napi_complete_done(napi, rx_work_done)) { 522 flags |= IONIC_INTR_CRED_UNMASK; 523 DEBUG_STATS_INTR_REARM(rxcq->bound_intr); 524 work_done = rx_work_done; 525 } else { 526 work_done = budget; 527 } 528 529 if (work_done || flags) { 530 flags |= IONIC_INTR_CRED_RESET_COALESCE; 531 ionic_intr_credits(idev->intr_ctrl, rxcq->bound_intr->index, 532 tx_work_done + rx_work_done, flags); 533 } 534 535 DEBUG_STATS_NAPI_POLL(qcq, rx_work_done); 536 DEBUG_STATS_NAPI_POLL(qcq, tx_work_done); 537 538 return work_done; 539 } 540 541 static dma_addr_t ionic_tx_map_single(struct ionic_queue *q, 542 void *data, size_t len) 543 { 544 struct ionic_tx_stats *stats = q_to_tx_stats(q); 545 struct device *dev = q->lif->ionic->dev; 546 dma_addr_t dma_addr; 547 548 dma_addr = dma_map_single(dev, data, len, DMA_TO_DEVICE); 549 if (dma_mapping_error(dev, dma_addr)) { 550 net_warn_ratelimited("%s: DMA single map failed on %s!\n", 551 q->lif->netdev->name, q->name); 552 stats->dma_map_err++; 553 return 0; 554 } 555 return dma_addr; 556 } 557 558 static dma_addr_t ionic_tx_map_frag(struct ionic_queue *q, 559 const skb_frag_t *frag, 560 size_t offset, size_t len) 561 { 562 struct ionic_tx_stats *stats = q_to_tx_stats(q); 563 struct device *dev = q->lif->ionic->dev; 564 dma_addr_t dma_addr; 565 566 dma_addr = skb_frag_dma_map(dev, frag, offset, len, DMA_TO_DEVICE); 567 if (dma_mapping_error(dev, dma_addr)) { 568 net_warn_ratelimited("%s: DMA frag map failed on %s!\n", 569 q->lif->netdev->name, q->name); 570 stats->dma_map_err++; 571 } 572 return dma_addr; 573 } 574 575 static void ionic_tx_clean(struct ionic_queue *q, 576 struct ionic_desc_info *desc_info, 577 struct ionic_cq_info *cq_info, 578 void *cb_arg) 579 { 580 struct ionic_txq_sg_desc *sg_desc = desc_info->sg_desc; 581 struct ionic_txq_sg_elem *elem = sg_desc->elems; 582 struct ionic_tx_stats *stats = q_to_tx_stats(q); 583 struct ionic_txq_desc *desc = desc_info->desc; 584 struct device *dev = q->lif->ionic->dev; 585 u8 opcode, flags, nsge; 586 u16 queue_index; 587 unsigned int i; 588 u64 addr; 589 590 decode_txq_desc_cmd(le64_to_cpu(desc->cmd), 591 &opcode, &flags, &nsge, &addr); 592 593 /* use unmap_single only if either this is not TSO, 594 * or this is first descriptor of a TSO 595 */ 596 if (opcode != IONIC_TXQ_DESC_OPCODE_TSO || 597 flags & IONIC_TXQ_DESC_FLAG_TSO_SOT) 598 dma_unmap_single(dev, (dma_addr_t)addr, 599 le16_to_cpu(desc->len), DMA_TO_DEVICE); 600 else 601 dma_unmap_page(dev, (dma_addr_t)addr, 602 le16_to_cpu(desc->len), DMA_TO_DEVICE); 603 604 for (i = 0; i < nsge; i++, elem++) 605 dma_unmap_page(dev, (dma_addr_t)le64_to_cpu(elem->addr), 606 le16_to_cpu(elem->len), DMA_TO_DEVICE); 607 608 if (cb_arg) { 609 struct sk_buff *skb = cb_arg; 610 u32 len = skb->len; 611 612 queue_index = skb_get_queue_mapping(skb); 613 if (unlikely(__netif_subqueue_stopped(q->lif->netdev, 614 queue_index))) { 615 netif_wake_subqueue(q->lif->netdev, queue_index); 616 q->wake++; 617 } 618 dev_kfree_skb_any(skb); 619 stats->clean++; 620 netdev_tx_completed_queue(q_to_ndq(q), 1, len); 621 } 622 } 623 624 static bool ionic_tx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info) 625 { 626 struct ionic_txq_comp *comp = cq_info->cq_desc; 627 struct ionic_queue *q = cq->bound_q; 628 struct ionic_desc_info *desc_info; 629 630 if (!color_match(comp->color, cq->done_color)) 631 return false; 632 633 /* clean the related q entries, there could be 634 * several q entries completed for each cq completion 635 */ 636 do { 637 desc_info = &q->info[q->tail_idx]; 638 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); 639 ionic_tx_clean(q, desc_info, cq_info, desc_info->cb_arg); 640 desc_info->cb = NULL; 641 desc_info->cb_arg = NULL; 642 } while (desc_info->index != le16_to_cpu(comp->comp_index)); 643 644 return true; 645 } 646 647 void ionic_tx_flush(struct ionic_cq *cq) 648 { 649 struct ionic_dev *idev = &cq->lif->ionic->idev; 650 u32 work_done; 651 652 work_done = ionic_cq_service(cq, cq->num_descs, 653 ionic_tx_service, NULL, NULL); 654 if (work_done) 655 ionic_intr_credits(idev->intr_ctrl, cq->bound_intr->index, 656 work_done, IONIC_INTR_CRED_RESET_COALESCE); 657 } 658 659 void ionic_tx_empty(struct ionic_queue *q) 660 { 661 struct ionic_desc_info *desc_info; 662 int done = 0; 663 664 /* walk the not completed tx entries, if any */ 665 while (q->head_idx != q->tail_idx) { 666 desc_info = &q->info[q->tail_idx]; 667 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); 668 ionic_tx_clean(q, desc_info, NULL, desc_info->cb_arg); 669 desc_info->cb = NULL; 670 desc_info->cb_arg = NULL; 671 done++; 672 } 673 } 674 675 static int ionic_tx_tcp_inner_pseudo_csum(struct sk_buff *skb) 676 { 677 int err; 678 679 err = skb_cow_head(skb, 0); 680 if (err) 681 return err; 682 683 if (skb->protocol == cpu_to_be16(ETH_P_IP)) { 684 inner_ip_hdr(skb)->check = 0; 685 inner_tcp_hdr(skb)->check = 686 ~csum_tcpudp_magic(inner_ip_hdr(skb)->saddr, 687 inner_ip_hdr(skb)->daddr, 688 0, IPPROTO_TCP, 0); 689 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) { 690 inner_tcp_hdr(skb)->check = 691 ~csum_ipv6_magic(&inner_ipv6_hdr(skb)->saddr, 692 &inner_ipv6_hdr(skb)->daddr, 693 0, IPPROTO_TCP, 0); 694 } 695 696 return 0; 697 } 698 699 static int ionic_tx_tcp_pseudo_csum(struct sk_buff *skb) 700 { 701 int err; 702 703 err = skb_cow_head(skb, 0); 704 if (err) 705 return err; 706 707 if (skb->protocol == cpu_to_be16(ETH_P_IP)) { 708 ip_hdr(skb)->check = 0; 709 tcp_hdr(skb)->check = 710 ~csum_tcpudp_magic(ip_hdr(skb)->saddr, 711 ip_hdr(skb)->daddr, 712 0, IPPROTO_TCP, 0); 713 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) { 714 tcp_v6_gso_csum_prep(skb); 715 } 716 717 return 0; 718 } 719 720 static void ionic_tx_tso_post(struct ionic_queue *q, struct ionic_txq_desc *desc, 721 struct sk_buff *skb, 722 dma_addr_t addr, u8 nsge, u16 len, 723 unsigned int hdrlen, unsigned int mss, 724 bool outer_csum, 725 u16 vlan_tci, bool has_vlan, 726 bool start, bool done) 727 { 728 u8 flags = 0; 729 u64 cmd; 730 731 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0; 732 flags |= outer_csum ? IONIC_TXQ_DESC_FLAG_ENCAP : 0; 733 flags |= start ? IONIC_TXQ_DESC_FLAG_TSO_SOT : 0; 734 flags |= done ? IONIC_TXQ_DESC_FLAG_TSO_EOT : 0; 735 736 cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_TSO, flags, nsge, addr); 737 desc->cmd = cpu_to_le64(cmd); 738 desc->len = cpu_to_le16(len); 739 desc->vlan_tci = cpu_to_le16(vlan_tci); 740 desc->hdr_len = cpu_to_le16(hdrlen); 741 desc->mss = cpu_to_le16(mss); 742 743 if (done) { 744 skb_tx_timestamp(skb); 745 netdev_tx_sent_queue(q_to_ndq(q), skb->len); 746 ionic_txq_post(q, !netdev_xmit_more(), ionic_tx_clean, skb); 747 } else { 748 ionic_txq_post(q, false, ionic_tx_clean, NULL); 749 } 750 } 751 752 static struct ionic_txq_desc *ionic_tx_tso_next(struct ionic_queue *q, 753 struct ionic_txq_sg_elem **elem) 754 { 755 struct ionic_txq_sg_desc *sg_desc = q->info[q->head_idx].txq_sg_desc; 756 struct ionic_txq_desc *desc = q->info[q->head_idx].txq_desc; 757 758 *elem = sg_desc->elems; 759 return desc; 760 } 761 762 static int ionic_tx_tso(struct ionic_queue *q, struct sk_buff *skb) 763 { 764 struct ionic_tx_stats *stats = q_to_tx_stats(q); 765 struct ionic_desc_info *rewind_desc_info; 766 struct device *dev = q->lif->ionic->dev; 767 struct ionic_txq_sg_elem *elem; 768 struct ionic_txq_desc *desc; 769 unsigned int frag_left = 0; 770 unsigned int offset = 0; 771 u16 abort = q->head_idx; 772 unsigned int len_left; 773 dma_addr_t desc_addr; 774 unsigned int hdrlen; 775 unsigned int nfrags; 776 unsigned int seglen; 777 u64 total_bytes = 0; 778 u64 total_pkts = 0; 779 u16 rewind = abort; 780 unsigned int left; 781 unsigned int len; 782 unsigned int mss; 783 skb_frag_t *frag; 784 bool start, done; 785 bool outer_csum; 786 bool has_vlan; 787 u16 desc_len; 788 u8 desc_nsge; 789 u16 vlan_tci; 790 bool encap; 791 int err; 792 793 mss = skb_shinfo(skb)->gso_size; 794 nfrags = skb_shinfo(skb)->nr_frags; 795 len_left = skb->len - skb_headlen(skb); 796 outer_csum = (skb_shinfo(skb)->gso_type & SKB_GSO_GRE_CSUM) || 797 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM); 798 has_vlan = !!skb_vlan_tag_present(skb); 799 vlan_tci = skb_vlan_tag_get(skb); 800 encap = skb->encapsulation; 801 802 /* Preload inner-most TCP csum field with IP pseudo hdr 803 * calculated with IP length set to zero. HW will later 804 * add in length to each TCP segment resulting from the TSO. 805 */ 806 807 if (encap) 808 err = ionic_tx_tcp_inner_pseudo_csum(skb); 809 else 810 err = ionic_tx_tcp_pseudo_csum(skb); 811 if (err) 812 return err; 813 814 if (encap) 815 hdrlen = skb_inner_transport_header(skb) - skb->data + 816 inner_tcp_hdrlen(skb); 817 else 818 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb); 819 820 seglen = hdrlen + mss; 821 left = skb_headlen(skb); 822 823 desc = ionic_tx_tso_next(q, &elem); 824 start = true; 825 826 /* Chop skb->data up into desc segments */ 827 828 while (left > 0) { 829 len = min(seglen, left); 830 frag_left = seglen - len; 831 desc_addr = ionic_tx_map_single(q, skb->data + offset, len); 832 if (dma_mapping_error(dev, desc_addr)) 833 goto err_out_abort; 834 desc_len = len; 835 desc_nsge = 0; 836 left -= len; 837 offset += len; 838 if (nfrags > 0 && frag_left > 0) 839 continue; 840 done = (nfrags == 0 && left == 0); 841 ionic_tx_tso_post(q, desc, skb, 842 desc_addr, desc_nsge, desc_len, 843 hdrlen, mss, 844 outer_csum, 845 vlan_tci, has_vlan, 846 start, done); 847 total_pkts++; 848 total_bytes += start ? len : len + hdrlen; 849 desc = ionic_tx_tso_next(q, &elem); 850 start = false; 851 seglen = mss; 852 } 853 854 /* Chop skb frags into desc segments */ 855 856 for (frag = skb_shinfo(skb)->frags; len_left; frag++) { 857 offset = 0; 858 left = skb_frag_size(frag); 859 len_left -= left; 860 nfrags--; 861 stats->frags++; 862 863 while (left > 0) { 864 if (frag_left > 0) { 865 len = min(frag_left, left); 866 frag_left -= len; 867 elem->addr = 868 cpu_to_le64(ionic_tx_map_frag(q, frag, 869 offset, len)); 870 if (dma_mapping_error(dev, elem->addr)) 871 goto err_out_abort; 872 elem->len = cpu_to_le16(len); 873 elem++; 874 desc_nsge++; 875 left -= len; 876 offset += len; 877 if (nfrags > 0 && frag_left > 0) 878 continue; 879 done = (nfrags == 0 && left == 0); 880 ionic_tx_tso_post(q, desc, skb, desc_addr, 881 desc_nsge, desc_len, 882 hdrlen, mss, outer_csum, 883 vlan_tci, has_vlan, 884 start, done); 885 total_pkts++; 886 total_bytes += start ? len : len + hdrlen; 887 desc = ionic_tx_tso_next(q, &elem); 888 start = false; 889 } else { 890 len = min(mss, left); 891 frag_left = mss - len; 892 desc_addr = ionic_tx_map_frag(q, frag, 893 offset, len); 894 if (dma_mapping_error(dev, desc_addr)) 895 goto err_out_abort; 896 desc_len = len; 897 desc_nsge = 0; 898 left -= len; 899 offset += len; 900 if (nfrags > 0 && frag_left > 0) 901 continue; 902 done = (nfrags == 0 && left == 0); 903 ionic_tx_tso_post(q, desc, skb, desc_addr, 904 desc_nsge, desc_len, 905 hdrlen, mss, outer_csum, 906 vlan_tci, has_vlan, 907 start, done); 908 total_pkts++; 909 total_bytes += start ? len : len + hdrlen; 910 desc = ionic_tx_tso_next(q, &elem); 911 start = false; 912 } 913 } 914 } 915 916 stats->pkts += total_pkts; 917 stats->bytes += total_bytes; 918 stats->tso++; 919 stats->tso_bytes += total_bytes; 920 921 return 0; 922 923 err_out_abort: 924 while (rewind != q->head_idx) { 925 rewind_desc_info = &q->info[rewind]; 926 ionic_tx_clean(q, rewind_desc_info, NULL, NULL); 927 rewind = (rewind + 1) & (q->num_descs - 1); 928 } 929 q->head_idx = abort; 930 931 return -ENOMEM; 932 } 933 934 static int ionic_tx_calc_csum(struct ionic_queue *q, struct sk_buff *skb) 935 { 936 struct ionic_txq_desc *desc = q->info[q->head_idx].txq_desc; 937 struct ionic_tx_stats *stats = q_to_tx_stats(q); 938 struct device *dev = q->lif->ionic->dev; 939 dma_addr_t dma_addr; 940 bool has_vlan; 941 u8 flags = 0; 942 bool encap; 943 u64 cmd; 944 945 has_vlan = !!skb_vlan_tag_present(skb); 946 encap = skb->encapsulation; 947 948 dma_addr = ionic_tx_map_single(q, skb->data, skb_headlen(skb)); 949 if (dma_mapping_error(dev, dma_addr)) 950 return -ENOMEM; 951 952 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0; 953 flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0; 954 955 cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL, 956 flags, skb_shinfo(skb)->nr_frags, dma_addr); 957 desc->cmd = cpu_to_le64(cmd); 958 desc->len = cpu_to_le16(skb_headlen(skb)); 959 desc->csum_start = cpu_to_le16(skb_checksum_start_offset(skb)); 960 desc->csum_offset = cpu_to_le16(skb->csum_offset); 961 if (has_vlan) { 962 desc->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb)); 963 stats->vlan_inserted++; 964 } 965 966 if (skb->csum_not_inet) 967 stats->crc32_csum++; 968 else 969 stats->csum++; 970 971 return 0; 972 } 973 974 static int ionic_tx_calc_no_csum(struct ionic_queue *q, struct sk_buff *skb) 975 { 976 struct ionic_txq_desc *desc = q->info[q->head_idx].txq_desc; 977 struct ionic_tx_stats *stats = q_to_tx_stats(q); 978 struct device *dev = q->lif->ionic->dev; 979 dma_addr_t dma_addr; 980 bool has_vlan; 981 u8 flags = 0; 982 bool encap; 983 u64 cmd; 984 985 has_vlan = !!skb_vlan_tag_present(skb); 986 encap = skb->encapsulation; 987 988 dma_addr = ionic_tx_map_single(q, skb->data, skb_headlen(skb)); 989 if (dma_mapping_error(dev, dma_addr)) 990 return -ENOMEM; 991 992 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0; 993 flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0; 994 995 cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_CSUM_NONE, 996 flags, skb_shinfo(skb)->nr_frags, dma_addr); 997 desc->cmd = cpu_to_le64(cmd); 998 desc->len = cpu_to_le16(skb_headlen(skb)); 999 if (has_vlan) { 1000 desc->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb)); 1001 stats->vlan_inserted++; 1002 } 1003 1004 stats->csum_none++; 1005 1006 return 0; 1007 } 1008 1009 static int ionic_tx_skb_frags(struct ionic_queue *q, struct sk_buff *skb) 1010 { 1011 struct ionic_txq_sg_desc *sg_desc = q->info[q->head_idx].txq_sg_desc; 1012 unsigned int len_left = skb->len - skb_headlen(skb); 1013 struct ionic_txq_sg_elem *elem = sg_desc->elems; 1014 struct ionic_tx_stats *stats = q_to_tx_stats(q); 1015 struct device *dev = q->lif->ionic->dev; 1016 dma_addr_t dma_addr; 1017 skb_frag_t *frag; 1018 u16 len; 1019 1020 for (frag = skb_shinfo(skb)->frags; len_left; frag++, elem++) { 1021 len = skb_frag_size(frag); 1022 elem->len = cpu_to_le16(len); 1023 dma_addr = ionic_tx_map_frag(q, frag, 0, len); 1024 if (dma_mapping_error(dev, dma_addr)) 1025 return -ENOMEM; 1026 elem->addr = cpu_to_le64(dma_addr); 1027 len_left -= len; 1028 stats->frags++; 1029 } 1030 1031 return 0; 1032 } 1033 1034 static int ionic_tx(struct ionic_queue *q, struct sk_buff *skb) 1035 { 1036 struct ionic_tx_stats *stats = q_to_tx_stats(q); 1037 int err; 1038 1039 /* set up the initial descriptor */ 1040 if (skb->ip_summed == CHECKSUM_PARTIAL) 1041 err = ionic_tx_calc_csum(q, skb); 1042 else 1043 err = ionic_tx_calc_no_csum(q, skb); 1044 if (err) 1045 return err; 1046 1047 /* add frags */ 1048 err = ionic_tx_skb_frags(q, skb); 1049 if (err) 1050 return err; 1051 1052 skb_tx_timestamp(skb); 1053 stats->pkts++; 1054 stats->bytes += skb->len; 1055 1056 netdev_tx_sent_queue(q_to_ndq(q), skb->len); 1057 ionic_txq_post(q, !netdev_xmit_more(), ionic_tx_clean, skb); 1058 1059 return 0; 1060 } 1061 1062 static int ionic_tx_descs_needed(struct ionic_queue *q, struct sk_buff *skb) 1063 { 1064 int sg_elems = q->lif->qtype_info[IONIC_QTYPE_TXQ].max_sg_elems; 1065 struct ionic_tx_stats *stats = q_to_tx_stats(q); 1066 int err; 1067 1068 /* If TSO, need roundup(skb->len/mss) descs */ 1069 if (skb_is_gso(skb)) 1070 return (skb->len / skb_shinfo(skb)->gso_size) + 1; 1071 1072 /* If non-TSO, just need 1 desc and nr_frags sg elems */ 1073 if (skb_shinfo(skb)->nr_frags <= sg_elems) 1074 return 1; 1075 1076 /* Too many frags, so linearize */ 1077 err = skb_linearize(skb); 1078 if (err) 1079 return err; 1080 1081 stats->linearize++; 1082 1083 /* Need 1 desc and zero sg elems */ 1084 return 1; 1085 } 1086 1087 static int ionic_maybe_stop_tx(struct ionic_queue *q, int ndescs) 1088 { 1089 int stopped = 0; 1090 1091 if (unlikely(!ionic_q_has_space(q, ndescs))) { 1092 netif_stop_subqueue(q->lif->netdev, q->index); 1093 q->stop++; 1094 stopped = 1; 1095 1096 /* Might race with ionic_tx_clean, check again */ 1097 smp_rmb(); 1098 if (ionic_q_has_space(q, ndescs)) { 1099 netif_wake_subqueue(q->lif->netdev, q->index); 1100 stopped = 0; 1101 } 1102 } 1103 1104 return stopped; 1105 } 1106 1107 netdev_tx_t ionic_start_xmit(struct sk_buff *skb, struct net_device *netdev) 1108 { 1109 u16 queue_index = skb_get_queue_mapping(skb); 1110 struct ionic_lif *lif = netdev_priv(netdev); 1111 struct ionic_queue *q; 1112 int ndescs; 1113 int err; 1114 1115 if (unlikely(!test_bit(IONIC_LIF_F_UP, lif->state))) { 1116 dev_kfree_skb(skb); 1117 return NETDEV_TX_OK; 1118 } 1119 1120 if (unlikely(queue_index >= lif->nxqs)) 1121 queue_index = 0; 1122 q = &lif->txqcqs[queue_index]->q; 1123 1124 ndescs = ionic_tx_descs_needed(q, skb); 1125 if (ndescs < 0) 1126 goto err_out_drop; 1127 1128 if (unlikely(ionic_maybe_stop_tx(q, ndescs))) 1129 return NETDEV_TX_BUSY; 1130 1131 if (skb_is_gso(skb)) 1132 err = ionic_tx_tso(q, skb); 1133 else 1134 err = ionic_tx(q, skb); 1135 1136 if (err) 1137 goto err_out_drop; 1138 1139 /* Stop the queue if there aren't descriptors for the next packet. 1140 * Since our SG lists per descriptor take care of most of the possible 1141 * fragmentation, we don't need to have many descriptors available. 1142 */ 1143 ionic_maybe_stop_tx(q, 4); 1144 1145 return NETDEV_TX_OK; 1146 1147 err_out_drop: 1148 q->stop++; 1149 q->drop++; 1150 dev_kfree_skb(skb); 1151 return NETDEV_TX_OK; 1152 } 1153