1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #ifndef _IONIC_LIF_H_ 5 #define _IONIC_LIF_H_ 6 7 #include <linux/pci.h> 8 #include "ionic_rx_filter.h" 9 10 #define IONIC_ADMINQ_LENGTH 16 /* must be a power of two */ 11 #define IONIC_NOTIFYQ_LENGTH 64 /* must be a power of two */ 12 13 #define IONIC_MAX_NUM_NAPI_CNTR (NAPI_POLL_WEIGHT + 1) 14 #define IONIC_MAX_NUM_SG_CNTR (IONIC_TX_MAX_SG_ELEMS + 1) 15 #define IONIC_RX_COPYBREAK_DEFAULT 256 16 #define IONIC_TX_BUDGET_DEFAULT 256 17 18 struct ionic_tx_stats { 19 u64 dma_map_err; 20 u64 pkts; 21 u64 bytes; 22 u64 clean; 23 u64 linearize; 24 u64 csum_none; 25 u64 csum; 26 u64 crc32_csum; 27 u64 tso; 28 u64 tso_bytes; 29 u64 frags; 30 u64 vlan_inserted; 31 u64 sg_cntr[IONIC_MAX_NUM_SG_CNTR]; 32 }; 33 34 struct ionic_rx_stats { 35 u64 dma_map_err; 36 u64 alloc_err; 37 u64 pkts; 38 u64 bytes; 39 u64 csum_none; 40 u64 csum_complete; 41 u64 csum_error; 42 u64 buffers_posted; 43 u64 dropped; 44 u64 vlan_stripped; 45 }; 46 47 #define IONIC_QCQ_F_INITED BIT(0) 48 #define IONIC_QCQ_F_SG BIT(1) 49 #define IONIC_QCQ_F_INTR BIT(2) 50 #define IONIC_QCQ_F_TX_STATS BIT(3) 51 #define IONIC_QCQ_F_RX_STATS BIT(4) 52 #define IONIC_QCQ_F_NOTIFYQ BIT(5) 53 54 struct ionic_napi_stats { 55 u64 poll_count; 56 u64 work_done_cntr[IONIC_MAX_NUM_NAPI_CNTR]; 57 }; 58 59 struct ionic_qcq { 60 void *q_base; 61 dma_addr_t q_base_pa; 62 u32 q_size; 63 void *cq_base; 64 dma_addr_t cq_base_pa; 65 u32 cq_size; 66 void *sg_base; 67 dma_addr_t sg_base_pa; 68 u32 sg_size; 69 struct ionic_queue q; 70 struct ionic_cq cq; 71 struct ionic_intr_info intr; 72 struct napi_struct napi; 73 struct ionic_napi_stats napi_stats; 74 unsigned int flags; 75 struct dentry *dentry; 76 }; 77 78 #define q_to_qcq(q) container_of(q, struct ionic_qcq, q) 79 #define q_to_tx_stats(q) (&(q)->lif->txqstats[(q)->index]) 80 #define q_to_rx_stats(q) (&(q)->lif->rxqstats[(q)->index]) 81 #define napi_to_qcq(napi) container_of(napi, struct ionic_qcq, napi) 82 #define napi_to_cq(napi) (&napi_to_qcq(napi)->cq) 83 84 enum ionic_deferred_work_type { 85 IONIC_DW_TYPE_RX_MODE, 86 IONIC_DW_TYPE_RX_ADDR_ADD, 87 IONIC_DW_TYPE_RX_ADDR_DEL, 88 IONIC_DW_TYPE_LINK_STATUS, 89 IONIC_DW_TYPE_LIF_RESET, 90 }; 91 92 struct ionic_deferred_work { 93 struct list_head list; 94 enum ionic_deferred_work_type type; 95 union { 96 unsigned int rx_mode; 97 u8 addr[ETH_ALEN]; 98 u8 fw_status; 99 }; 100 }; 101 102 struct ionic_deferred { 103 spinlock_t lock; /* lock for deferred work list */ 104 struct list_head list; 105 struct work_struct work; 106 }; 107 108 struct ionic_lif_sw_stats { 109 u64 tx_packets; 110 u64 tx_bytes; 111 u64 rx_packets; 112 u64 rx_bytes; 113 u64 tx_tso; 114 u64 tx_tso_bytes; 115 u64 tx_csum_none; 116 u64 tx_csum; 117 u64 rx_csum_none; 118 u64 rx_csum_complete; 119 u64 rx_csum_error; 120 u64 hw_tx_dropped; 121 u64 hw_rx_dropped; 122 u64 hw_rx_over_errors; 123 u64 hw_rx_missed_errors; 124 u64 hw_tx_aborted_errors; 125 }; 126 127 enum ionic_lif_state_flags { 128 IONIC_LIF_F_INITED, 129 IONIC_LIF_F_SW_DEBUG_STATS, 130 IONIC_LIF_F_UP, 131 IONIC_LIF_F_LINK_CHECK_REQUESTED, 132 IONIC_LIF_F_FW_RESET, 133 IONIC_LIF_F_SPLIT_INTR, 134 135 /* leave this as last */ 136 IONIC_LIF_F_STATE_SIZE 137 }; 138 139 struct ionic_qtype_info { 140 u8 version; 141 u8 supported; 142 u64 features; 143 u16 desc_sz; 144 u16 comp_sz; 145 u16 sg_desc_sz; 146 u16 max_sg_elems; 147 u16 sg_desc_stride; 148 }; 149 150 #define IONIC_LIF_NAME_MAX_SZ 32 151 struct ionic_lif { 152 char name[IONIC_LIF_NAME_MAX_SZ]; 153 struct list_head list; 154 struct net_device *netdev; 155 DECLARE_BITMAP(state, IONIC_LIF_F_STATE_SIZE); 156 struct ionic *ionic; 157 bool registered; 158 unsigned int index; 159 unsigned int hw_index; 160 unsigned int kern_pid; 161 u64 __iomem *kern_dbpage; 162 struct mutex queue_lock; /* lock for queue structures */ 163 spinlock_t adminq_lock; /* lock for AdminQ operations */ 164 struct ionic_qcq *adminqcq; 165 struct ionic_qcq *notifyqcq; 166 struct ionic_qcq **txqcqs; 167 struct ionic_tx_stats *txqstats; 168 struct ionic_qcq **rxqcqs; 169 struct ionic_rx_stats *rxqstats; 170 u64 last_eid; 171 unsigned int neqs; 172 unsigned int nxqs; 173 unsigned int ntxq_descs; 174 unsigned int nrxq_descs; 175 u32 rx_copybreak; 176 u32 tx_budget; 177 unsigned int rx_mode; 178 u64 hw_features; 179 bool mc_overflow; 180 unsigned int nmcast; 181 bool uc_overflow; 182 u16 lif_type; 183 unsigned int nucast; 184 185 union ionic_lif_identity *identity; 186 struct ionic_lif_info *info; 187 dma_addr_t info_pa; 188 u32 info_sz; 189 struct ionic_qtype_info qtype_info[IONIC_QTYPE_MAX]; 190 191 u16 rss_types; 192 u8 rss_hash_key[IONIC_RSS_HASH_KEY_SIZE]; 193 u8 *rss_ind_tbl; 194 dma_addr_t rss_ind_tbl_pa; 195 u32 rss_ind_tbl_sz; 196 197 struct ionic_rx_filters rx_filters; 198 struct ionic_deferred deferred; 199 unsigned long *dbid_inuse; 200 unsigned int dbid_count; 201 struct dentry *dentry; 202 u32 rx_coalesce_usecs; /* what the user asked for */ 203 u32 rx_coalesce_hw; /* what the hw is using */ 204 u32 tx_coalesce_usecs; /* what the user asked for */ 205 u32 tx_coalesce_hw; /* what the hw is using */ 206 207 struct work_struct tx_timeout_work; 208 }; 209 210 struct ionic_queue_params { 211 unsigned int nxqs; 212 unsigned int ntxq_descs; 213 unsigned int nrxq_descs; 214 unsigned int intr_split; 215 }; 216 217 static inline void ionic_init_queue_params(struct ionic_lif *lif, 218 struct ionic_queue_params *qparam) 219 { 220 qparam->nxqs = lif->nxqs; 221 qparam->ntxq_descs = lif->ntxq_descs; 222 qparam->nrxq_descs = lif->nrxq_descs; 223 qparam->intr_split = test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 224 } 225 226 static inline u32 ionic_coal_usec_to_hw(struct ionic *ionic, u32 usecs) 227 { 228 u32 mult = le32_to_cpu(ionic->ident.dev.intr_coal_mult); 229 u32 div = le32_to_cpu(ionic->ident.dev.intr_coal_div); 230 231 /* Div-by-zero should never be an issue, but check anyway */ 232 if (!div || !mult) 233 return 0; 234 235 /* Round up in case usecs is close to the next hw unit */ 236 usecs += (div / mult) >> 1; 237 238 /* Convert from usecs to device units */ 239 return (usecs * mult) / div; 240 } 241 242 typedef void (*ionic_reset_cb)(struct ionic_lif *lif, void *arg); 243 244 void ionic_link_status_check_request(struct ionic_lif *lif); 245 void ionic_get_stats64(struct net_device *netdev, 246 struct rtnl_link_stats64 *ns); 247 void ionic_lif_deferred_enqueue(struct ionic_deferred *def, 248 struct ionic_deferred_work *work); 249 int ionic_lif_alloc(struct ionic *ionic); 250 int ionic_lif_init(struct ionic_lif *lif); 251 void ionic_lif_free(struct ionic_lif *lif); 252 void ionic_lif_deinit(struct ionic_lif *lif); 253 int ionic_lif_register(struct ionic_lif *lif); 254 void ionic_lif_unregister(struct ionic_lif *lif); 255 int ionic_lif_identify(struct ionic *ionic, u8 lif_type, 256 union ionic_lif_identity *lif_ident); 257 int ionic_lif_size(struct ionic *ionic); 258 int ionic_lif_rss_config(struct ionic_lif *lif, u16 types, 259 const u8 *key, const u32 *indir); 260 int ionic_reconfigure_queues(struct ionic_lif *lif, 261 struct ionic_queue_params *qparam); 262 263 static inline void debug_stats_txq_post(struct ionic_queue *q, bool dbell) 264 { 265 struct ionic_txq_desc *desc = &q->txq[q->head_idx]; 266 u8 num_sg_elems; 267 268 q->dbell_count += dbell; 269 270 num_sg_elems = ((le64_to_cpu(desc->cmd) >> IONIC_TXQ_DESC_NSGE_SHIFT) 271 & IONIC_TXQ_DESC_NSGE_MASK); 272 if (num_sg_elems > (IONIC_MAX_NUM_SG_CNTR - 1)) 273 num_sg_elems = IONIC_MAX_NUM_SG_CNTR - 1; 274 275 q->lif->txqstats[q->index].sg_cntr[num_sg_elems]++; 276 } 277 278 static inline void debug_stats_napi_poll(struct ionic_qcq *qcq, 279 unsigned int work_done) 280 { 281 qcq->napi_stats.poll_count++; 282 283 if (work_done > (IONIC_MAX_NUM_NAPI_CNTR - 1)) 284 work_done = IONIC_MAX_NUM_NAPI_CNTR - 1; 285 286 qcq->napi_stats.work_done_cntr[work_done]++; 287 } 288 289 #define DEBUG_STATS_CQE_CNT(cq) ((cq)->compl_count++) 290 #define DEBUG_STATS_RX_BUFF_CNT(q) ((q)->lif->rxqstats[q->index].buffers_posted++) 291 #define DEBUG_STATS_INTR_REARM(intr) ((intr)->rearm_count++) 292 #define DEBUG_STATS_TXQ_POST(q, dbell) debug_stats_txq_post(q, dbell) 293 #define DEBUG_STATS_NAPI_POLL(qcq, work_done) \ 294 debug_stats_napi_poll(qcq, work_done) 295 296 #endif /* _IONIC_LIF_H_ */ 297