1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/ethtool.h> 5 #include <linux/printk.h> 6 #include <linux/dynamic_debug.h> 7 #include <linux/netdevice.h> 8 #include <linux/etherdevice.h> 9 #include <linux/if_vlan.h> 10 #include <linux/rtnetlink.h> 11 #include <linux/interrupt.h> 12 #include <linux/pci.h> 13 #include <linux/cpumask.h> 14 #include <linux/crash_dump.h> 15 #include <linux/vmalloc.h> 16 17 #include "ionic.h" 18 #include "ionic_bus.h" 19 #include "ionic_lif.h" 20 #include "ionic_txrx.h" 21 #include "ionic_ethtool.h" 22 #include "ionic_debugfs.h" 23 24 /* queuetype support level */ 25 static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = { 26 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */ 27 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */ 28 [IONIC_QTYPE_RXQ] = 0, /* 0 = Base version with CQ+SG support */ 29 [IONIC_QTYPE_TXQ] = 1, /* 0 = Base version with CQ+SG support 30 * 1 = ... with Tx SG version 1 31 */ 32 }; 33 34 static void ionic_link_status_check(struct ionic_lif *lif); 35 static void ionic_lif_handle_fw_down(struct ionic_lif *lif); 36 static void ionic_lif_handle_fw_up(struct ionic_lif *lif); 37 static void ionic_lif_set_netdev_info(struct ionic_lif *lif); 38 39 static void ionic_txrx_deinit(struct ionic_lif *lif); 40 static int ionic_txrx_init(struct ionic_lif *lif); 41 static int ionic_start_queues(struct ionic_lif *lif); 42 static void ionic_stop_queues(struct ionic_lif *lif); 43 static void ionic_lif_queue_identify(struct ionic_lif *lif); 44 45 static void ionic_dim_work(struct work_struct *work) 46 { 47 struct dim *dim = container_of(work, struct dim, work); 48 struct dim_cq_moder cur_moder; 49 struct ionic_qcq *qcq; 50 u32 new_coal; 51 52 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 53 qcq = container_of(dim, struct ionic_qcq, dim); 54 new_coal = ionic_coal_usec_to_hw(qcq->q.lif->ionic, cur_moder.usec); 55 new_coal = new_coal ? new_coal : 1; 56 57 if (qcq->intr.dim_coal_hw != new_coal) { 58 unsigned int qi = qcq->cq.bound_q->index; 59 struct ionic_lif *lif = qcq->q.lif; 60 61 qcq->intr.dim_coal_hw = new_coal; 62 63 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 64 lif->rxqcqs[qi]->intr.index, 65 qcq->intr.dim_coal_hw); 66 } 67 68 dim->state = DIM_START_MEASURE; 69 } 70 71 static void ionic_lif_deferred_work(struct work_struct *work) 72 { 73 struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work); 74 struct ionic_deferred *def = &lif->deferred; 75 struct ionic_deferred_work *w = NULL; 76 77 do { 78 spin_lock_bh(&def->lock); 79 if (!list_empty(&def->list)) { 80 w = list_first_entry(&def->list, 81 struct ionic_deferred_work, list); 82 list_del(&w->list); 83 } 84 spin_unlock_bh(&def->lock); 85 86 if (!w) 87 break; 88 89 switch (w->type) { 90 case IONIC_DW_TYPE_RX_MODE: 91 ionic_lif_rx_mode(lif); 92 break; 93 case IONIC_DW_TYPE_LINK_STATUS: 94 ionic_link_status_check(lif); 95 break; 96 case IONIC_DW_TYPE_LIF_RESET: 97 if (w->fw_status) { 98 ionic_lif_handle_fw_up(lif); 99 } else { 100 ionic_lif_handle_fw_down(lif); 101 102 /* Fire off another watchdog to see 103 * if the FW is already back rather than 104 * waiting another whole cycle 105 */ 106 mod_timer(&lif->ionic->watchdog_timer, jiffies + 1); 107 } 108 break; 109 default: 110 break; 111 } 112 kfree(w); 113 w = NULL; 114 } while (true); 115 } 116 117 void ionic_lif_deferred_enqueue(struct ionic_deferred *def, 118 struct ionic_deferred_work *work) 119 { 120 spin_lock_bh(&def->lock); 121 list_add_tail(&work->list, &def->list); 122 spin_unlock_bh(&def->lock); 123 schedule_work(&def->work); 124 } 125 126 static void ionic_link_status_check(struct ionic_lif *lif) 127 { 128 struct net_device *netdev = lif->netdev; 129 u16 link_status; 130 bool link_up; 131 132 if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 133 return; 134 135 /* Don't put carrier back up if we're in a broken state */ 136 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) { 137 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 138 return; 139 } 140 141 link_status = le16_to_cpu(lif->info->status.link_status); 142 link_up = link_status == IONIC_PORT_OPER_STATUS_UP; 143 144 if (link_up) { 145 int err = 0; 146 147 if (netdev->flags & IFF_UP && netif_running(netdev)) { 148 mutex_lock(&lif->queue_lock); 149 err = ionic_start_queues(lif); 150 if (err && err != -EBUSY) { 151 netdev_err(lif->netdev, 152 "Failed to start queues: %d\n", err); 153 set_bit(IONIC_LIF_F_BROKEN, lif->state); 154 netif_carrier_off(lif->netdev); 155 } 156 mutex_unlock(&lif->queue_lock); 157 } 158 159 if (!err && !netif_carrier_ok(netdev)) { 160 ionic_port_identify(lif->ionic); 161 netdev_info(netdev, "Link up - %d Gbps\n", 162 le32_to_cpu(lif->info->status.link_speed) / 1000); 163 netif_carrier_on(netdev); 164 } 165 } else { 166 if (netif_carrier_ok(netdev)) { 167 netdev_info(netdev, "Link down\n"); 168 netif_carrier_off(netdev); 169 } 170 171 if (netdev->flags & IFF_UP && netif_running(netdev)) { 172 mutex_lock(&lif->queue_lock); 173 ionic_stop_queues(lif); 174 mutex_unlock(&lif->queue_lock); 175 } 176 } 177 178 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 179 } 180 181 void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep) 182 { 183 struct ionic_deferred_work *work; 184 185 /* we only need one request outstanding at a time */ 186 if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 187 return; 188 189 if (!can_sleep) { 190 work = kzalloc(sizeof(*work), GFP_ATOMIC); 191 if (!work) { 192 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 193 return; 194 } 195 196 work->type = IONIC_DW_TYPE_LINK_STATUS; 197 ionic_lif_deferred_enqueue(&lif->deferred, work); 198 } else { 199 ionic_link_status_check(lif); 200 } 201 } 202 203 static irqreturn_t ionic_isr(int irq, void *data) 204 { 205 struct napi_struct *napi = data; 206 207 napi_schedule_irqoff(napi); 208 209 return IRQ_HANDLED; 210 } 211 212 static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq) 213 { 214 struct ionic_intr_info *intr = &qcq->intr; 215 struct device *dev = lif->ionic->dev; 216 struct ionic_queue *q = &qcq->q; 217 const char *name; 218 219 if (lif->registered) 220 name = lif->netdev->name; 221 else 222 name = dev_name(dev); 223 224 snprintf(intr->name, sizeof(intr->name), 225 "%s-%s-%s", IONIC_DRV_NAME, name, q->name); 226 227 return devm_request_irq(dev, intr->vector, ionic_isr, 228 0, intr->name, &qcq->napi); 229 } 230 231 static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) 232 { 233 struct ionic *ionic = lif->ionic; 234 int index; 235 236 index = find_first_zero_bit(ionic->intrs, ionic->nintrs); 237 if (index == ionic->nintrs) { 238 netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n", 239 __func__, index, ionic->nintrs); 240 return -ENOSPC; 241 } 242 243 set_bit(index, ionic->intrs); 244 ionic_intr_init(&ionic->idev, intr, index); 245 246 return 0; 247 } 248 249 static void ionic_intr_free(struct ionic *ionic, int index) 250 { 251 if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < ionic->nintrs) 252 clear_bit(index, ionic->intrs); 253 } 254 255 static int ionic_qcq_enable(struct ionic_qcq *qcq) 256 { 257 struct ionic_queue *q = &qcq->q; 258 struct ionic_lif *lif = q->lif; 259 struct ionic_dev *idev; 260 struct device *dev; 261 262 struct ionic_admin_ctx ctx = { 263 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 264 .cmd.q_control = { 265 .opcode = IONIC_CMD_Q_CONTROL, 266 .lif_index = cpu_to_le16(lif->index), 267 .type = q->type, 268 .index = cpu_to_le32(q->index), 269 .oper = IONIC_Q_ENABLE, 270 }, 271 }; 272 273 idev = &lif->ionic->idev; 274 dev = lif->ionic->dev; 275 276 dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n", 277 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 278 279 if (qcq->flags & IONIC_QCQ_F_INTR) { 280 irq_set_affinity_hint(qcq->intr.vector, 281 &qcq->intr.affinity_mask); 282 napi_enable(&qcq->napi); 283 ionic_intr_clean(idev->intr_ctrl, qcq->intr.index); 284 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 285 IONIC_INTR_MASK_CLEAR); 286 } 287 288 return ionic_adminq_post_wait(lif, &ctx); 289 } 290 291 static int ionic_qcq_disable(struct ionic_lif *lif, struct ionic_qcq *qcq, int fw_err) 292 { 293 struct ionic_queue *q; 294 295 struct ionic_admin_ctx ctx = { 296 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 297 .cmd.q_control = { 298 .opcode = IONIC_CMD_Q_CONTROL, 299 .oper = IONIC_Q_DISABLE, 300 }, 301 }; 302 303 if (!qcq) { 304 netdev_err(lif->netdev, "%s: bad qcq\n", __func__); 305 return -ENXIO; 306 } 307 308 q = &qcq->q; 309 310 if (qcq->flags & IONIC_QCQ_F_INTR) { 311 struct ionic_dev *idev = &lif->ionic->idev; 312 313 cancel_work_sync(&qcq->dim.work); 314 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 315 IONIC_INTR_MASK_SET); 316 synchronize_irq(qcq->intr.vector); 317 irq_set_affinity_hint(qcq->intr.vector, NULL); 318 napi_disable(&qcq->napi); 319 } 320 321 /* If there was a previous fw communcation error, don't bother with 322 * sending the adminq command and just return the same error value. 323 */ 324 if (fw_err == -ETIMEDOUT || fw_err == -ENXIO) 325 return fw_err; 326 327 ctx.cmd.q_control.lif_index = cpu_to_le16(lif->index); 328 ctx.cmd.q_control.type = q->type; 329 ctx.cmd.q_control.index = cpu_to_le32(q->index); 330 dev_dbg(lif->ionic->dev, "q_disable.index %d q_disable.qtype %d\n", 331 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 332 333 return ionic_adminq_post_wait(lif, &ctx); 334 } 335 336 static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq) 337 { 338 struct ionic_dev *idev = &lif->ionic->idev; 339 340 if (!qcq) 341 return; 342 343 if (!(qcq->flags & IONIC_QCQ_F_INITED)) 344 return; 345 346 if (qcq->flags & IONIC_QCQ_F_INTR) { 347 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 348 IONIC_INTR_MASK_SET); 349 netif_napi_del(&qcq->napi); 350 } 351 352 qcq->flags &= ~IONIC_QCQ_F_INITED; 353 } 354 355 static void ionic_qcq_intr_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 356 { 357 if (!(qcq->flags & IONIC_QCQ_F_INTR) || qcq->intr.vector == 0) 358 return; 359 360 irq_set_affinity_hint(qcq->intr.vector, NULL); 361 devm_free_irq(lif->ionic->dev, qcq->intr.vector, &qcq->napi); 362 qcq->intr.vector = 0; 363 ionic_intr_free(lif->ionic, qcq->intr.index); 364 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 365 } 366 367 static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 368 { 369 struct device *dev = lif->ionic->dev; 370 371 if (!qcq) 372 return; 373 374 ionic_debugfs_del_qcq(qcq); 375 376 if (qcq->q_base) { 377 dma_free_coherent(dev, qcq->q_size, qcq->q_base, qcq->q_base_pa); 378 qcq->q_base = NULL; 379 qcq->q_base_pa = 0; 380 } 381 382 if (qcq->cq_base) { 383 dma_free_coherent(dev, qcq->cq_size, qcq->cq_base, qcq->cq_base_pa); 384 qcq->cq_base = NULL; 385 qcq->cq_base_pa = 0; 386 } 387 388 if (qcq->sg_base) { 389 dma_free_coherent(dev, qcq->sg_size, qcq->sg_base, qcq->sg_base_pa); 390 qcq->sg_base = NULL; 391 qcq->sg_base_pa = 0; 392 } 393 394 ionic_qcq_intr_free(lif, qcq); 395 396 if (qcq->cq.info) { 397 vfree(qcq->cq.info); 398 qcq->cq.info = NULL; 399 } 400 if (qcq->q.info) { 401 vfree(qcq->q.info); 402 qcq->q.info = NULL; 403 } 404 } 405 406 static void ionic_qcqs_free(struct ionic_lif *lif) 407 { 408 struct device *dev = lif->ionic->dev; 409 struct ionic_qcq *adminqcq; 410 unsigned long irqflags; 411 412 if (lif->notifyqcq) { 413 ionic_qcq_free(lif, lif->notifyqcq); 414 devm_kfree(dev, lif->notifyqcq); 415 lif->notifyqcq = NULL; 416 } 417 418 if (lif->adminqcq) { 419 spin_lock_irqsave(&lif->adminq_lock, irqflags); 420 adminqcq = READ_ONCE(lif->adminqcq); 421 lif->adminqcq = NULL; 422 spin_unlock_irqrestore(&lif->adminq_lock, irqflags); 423 if (adminqcq) { 424 ionic_qcq_free(lif, adminqcq); 425 devm_kfree(dev, adminqcq); 426 } 427 } 428 429 if (lif->rxqcqs) { 430 devm_kfree(dev, lif->rxqstats); 431 lif->rxqstats = NULL; 432 devm_kfree(dev, lif->rxqcqs); 433 lif->rxqcqs = NULL; 434 } 435 436 if (lif->txqcqs) { 437 devm_kfree(dev, lif->txqstats); 438 lif->txqstats = NULL; 439 devm_kfree(dev, lif->txqcqs); 440 lif->txqcqs = NULL; 441 } 442 } 443 444 static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq, 445 struct ionic_qcq *n_qcq) 446 { 447 if (WARN_ON(n_qcq->flags & IONIC_QCQ_F_INTR)) { 448 ionic_intr_free(n_qcq->cq.lif->ionic, n_qcq->intr.index); 449 n_qcq->flags &= ~IONIC_QCQ_F_INTR; 450 } 451 452 n_qcq->intr.vector = src_qcq->intr.vector; 453 n_qcq->intr.index = src_qcq->intr.index; 454 } 455 456 static int ionic_alloc_qcq_interrupt(struct ionic_lif *lif, struct ionic_qcq *qcq) 457 { 458 int err; 459 460 if (!(qcq->flags & IONIC_QCQ_F_INTR)) { 461 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 462 return 0; 463 } 464 465 err = ionic_intr_alloc(lif, &qcq->intr); 466 if (err) { 467 netdev_warn(lif->netdev, "no intr for %s: %d\n", 468 qcq->q.name, err); 469 goto err_out; 470 } 471 472 err = ionic_bus_get_irq(lif->ionic, qcq->intr.index); 473 if (err < 0) { 474 netdev_warn(lif->netdev, "no vector for %s: %d\n", 475 qcq->q.name, err); 476 goto err_out_free_intr; 477 } 478 qcq->intr.vector = err; 479 ionic_intr_mask_assert(lif->ionic->idev.intr_ctrl, qcq->intr.index, 480 IONIC_INTR_MASK_SET); 481 482 err = ionic_request_irq(lif, qcq); 483 if (err) { 484 netdev_warn(lif->netdev, "irq request failed %d\n", err); 485 goto err_out_free_intr; 486 } 487 488 /* try to get the irq on the local numa node first */ 489 qcq->intr.cpu = cpumask_local_spread(qcq->intr.index, 490 dev_to_node(lif->ionic->dev)); 491 if (qcq->intr.cpu != -1) 492 cpumask_set_cpu(qcq->intr.cpu, &qcq->intr.affinity_mask); 493 494 netdev_dbg(lif->netdev, "%s: Interrupt index %d\n", qcq->q.name, qcq->intr.index); 495 return 0; 496 497 err_out_free_intr: 498 ionic_intr_free(lif->ionic, qcq->intr.index); 499 err_out: 500 return err; 501 } 502 503 static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type, 504 unsigned int index, 505 const char *name, unsigned int flags, 506 unsigned int num_descs, unsigned int desc_size, 507 unsigned int cq_desc_size, 508 unsigned int sg_desc_size, 509 unsigned int pid, struct ionic_qcq **qcq) 510 { 511 struct ionic_dev *idev = &lif->ionic->idev; 512 struct device *dev = lif->ionic->dev; 513 void *q_base, *cq_base, *sg_base; 514 dma_addr_t cq_base_pa = 0; 515 dma_addr_t sg_base_pa = 0; 516 dma_addr_t q_base_pa = 0; 517 struct ionic_qcq *new; 518 int err; 519 520 *qcq = NULL; 521 522 new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL); 523 if (!new) { 524 netdev_err(lif->netdev, "Cannot allocate queue structure\n"); 525 err = -ENOMEM; 526 goto err_out; 527 } 528 529 new->q.dev = dev; 530 new->flags = flags; 531 532 new->q.info = vzalloc(num_descs * sizeof(*new->q.info)); 533 if (!new->q.info) { 534 netdev_err(lif->netdev, "Cannot allocate queue info\n"); 535 err = -ENOMEM; 536 goto err_out_free_qcq; 537 } 538 539 new->q.type = type; 540 new->q.max_sg_elems = lif->qtype_info[type].max_sg_elems; 541 542 err = ionic_q_init(lif, idev, &new->q, index, name, num_descs, 543 desc_size, sg_desc_size, pid); 544 if (err) { 545 netdev_err(lif->netdev, "Cannot initialize queue\n"); 546 goto err_out_free_q_info; 547 } 548 549 err = ionic_alloc_qcq_interrupt(lif, new); 550 if (err) 551 goto err_out; 552 553 new->cq.info = vzalloc(num_descs * sizeof(*new->cq.info)); 554 if (!new->cq.info) { 555 netdev_err(lif->netdev, "Cannot allocate completion queue info\n"); 556 err = -ENOMEM; 557 goto err_out_free_irq; 558 } 559 560 err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size); 561 if (err) { 562 netdev_err(lif->netdev, "Cannot initialize completion queue\n"); 563 goto err_out_free_cq_info; 564 } 565 566 if (flags & IONIC_QCQ_F_NOTIFYQ) { 567 int q_size, cq_size; 568 569 /* q & cq need to be contiguous in case of notifyq */ 570 q_size = ALIGN(num_descs * desc_size, PAGE_SIZE); 571 cq_size = ALIGN(num_descs * cq_desc_size, PAGE_SIZE); 572 573 new->q_size = PAGE_SIZE + q_size + cq_size; 574 new->q_base = dma_alloc_coherent(dev, new->q_size, 575 &new->q_base_pa, GFP_KERNEL); 576 if (!new->q_base) { 577 netdev_err(lif->netdev, "Cannot allocate qcq DMA memory\n"); 578 err = -ENOMEM; 579 goto err_out_free_cq_info; 580 } 581 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE); 582 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 583 ionic_q_map(&new->q, q_base, q_base_pa); 584 585 cq_base = PTR_ALIGN(q_base + q_size, PAGE_SIZE); 586 cq_base_pa = ALIGN(new->q_base_pa + q_size, PAGE_SIZE); 587 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 588 ionic_cq_bind(&new->cq, &new->q); 589 } else { 590 new->q_size = PAGE_SIZE + (num_descs * desc_size); 591 new->q_base = dma_alloc_coherent(dev, new->q_size, &new->q_base_pa, 592 GFP_KERNEL); 593 if (!new->q_base) { 594 netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n"); 595 err = -ENOMEM; 596 goto err_out_free_cq_info; 597 } 598 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE); 599 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 600 ionic_q_map(&new->q, q_base, q_base_pa); 601 602 new->cq_size = PAGE_SIZE + (num_descs * cq_desc_size); 603 new->cq_base = dma_alloc_coherent(dev, new->cq_size, &new->cq_base_pa, 604 GFP_KERNEL); 605 if (!new->cq_base) { 606 netdev_err(lif->netdev, "Cannot allocate cq DMA memory\n"); 607 err = -ENOMEM; 608 goto err_out_free_q; 609 } 610 cq_base = PTR_ALIGN(new->cq_base, PAGE_SIZE); 611 cq_base_pa = ALIGN(new->cq_base_pa, PAGE_SIZE); 612 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 613 ionic_cq_bind(&new->cq, &new->q); 614 } 615 616 if (flags & IONIC_QCQ_F_SG) { 617 new->sg_size = PAGE_SIZE + (num_descs * sg_desc_size); 618 new->sg_base = dma_alloc_coherent(dev, new->sg_size, &new->sg_base_pa, 619 GFP_KERNEL); 620 if (!new->sg_base) { 621 netdev_err(lif->netdev, "Cannot allocate sg DMA memory\n"); 622 err = -ENOMEM; 623 goto err_out_free_cq; 624 } 625 sg_base = PTR_ALIGN(new->sg_base, PAGE_SIZE); 626 sg_base_pa = ALIGN(new->sg_base_pa, PAGE_SIZE); 627 ionic_q_sg_map(&new->q, sg_base, sg_base_pa); 628 } 629 630 INIT_WORK(&new->dim.work, ionic_dim_work); 631 new->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 632 633 *qcq = new; 634 635 return 0; 636 637 err_out_free_cq: 638 dma_free_coherent(dev, new->cq_size, new->cq_base, new->cq_base_pa); 639 err_out_free_q: 640 dma_free_coherent(dev, new->q_size, new->q_base, new->q_base_pa); 641 err_out_free_cq_info: 642 vfree(new->cq.info); 643 err_out_free_irq: 644 if (flags & IONIC_QCQ_F_INTR) { 645 devm_free_irq(dev, new->intr.vector, &new->napi); 646 ionic_intr_free(lif->ionic, new->intr.index); 647 } 648 err_out_free_q_info: 649 vfree(new->q.info); 650 err_out_free_qcq: 651 devm_kfree(dev, new); 652 err_out: 653 dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err); 654 return err; 655 } 656 657 static int ionic_qcqs_alloc(struct ionic_lif *lif) 658 { 659 struct device *dev = lif->ionic->dev; 660 unsigned int flags; 661 int err; 662 663 flags = IONIC_QCQ_F_INTR; 664 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags, 665 IONIC_ADMINQ_LENGTH, 666 sizeof(struct ionic_admin_cmd), 667 sizeof(struct ionic_admin_comp), 668 0, lif->kern_pid, &lif->adminqcq); 669 if (err) 670 return err; 671 ionic_debugfs_add_qcq(lif, lif->adminqcq); 672 673 if (lif->ionic->nnqs_per_lif) { 674 flags = IONIC_QCQ_F_NOTIFYQ; 675 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq", 676 flags, IONIC_NOTIFYQ_LENGTH, 677 sizeof(struct ionic_notifyq_cmd), 678 sizeof(union ionic_notifyq_comp), 679 0, lif->kern_pid, &lif->notifyqcq); 680 if (err) 681 goto err_out; 682 ionic_debugfs_add_qcq(lif, lif->notifyqcq); 683 684 /* Let the notifyq ride on the adminq interrupt */ 685 ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq); 686 } 687 688 err = -ENOMEM; 689 lif->txqcqs = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif, 690 sizeof(*lif->txqcqs), GFP_KERNEL); 691 if (!lif->txqcqs) 692 goto err_out; 693 lif->rxqcqs = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif, 694 sizeof(*lif->rxqcqs), GFP_KERNEL); 695 if (!lif->rxqcqs) 696 goto err_out; 697 698 lif->txqstats = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif + 1, 699 sizeof(*lif->txqstats), GFP_KERNEL); 700 if (!lif->txqstats) 701 goto err_out; 702 lif->rxqstats = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif + 1, 703 sizeof(*lif->rxqstats), GFP_KERNEL); 704 if (!lif->rxqstats) 705 goto err_out; 706 707 return 0; 708 709 err_out: 710 ionic_qcqs_free(lif); 711 return err; 712 } 713 714 static void ionic_qcq_sanitize(struct ionic_qcq *qcq) 715 { 716 qcq->q.tail_idx = 0; 717 qcq->q.head_idx = 0; 718 qcq->cq.tail_idx = 0; 719 qcq->cq.done_color = 1; 720 memset(qcq->q_base, 0, qcq->q_size); 721 memset(qcq->cq_base, 0, qcq->cq_size); 722 memset(qcq->sg_base, 0, qcq->sg_size); 723 } 724 725 static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 726 { 727 struct device *dev = lif->ionic->dev; 728 struct ionic_queue *q = &qcq->q; 729 struct ionic_cq *cq = &qcq->cq; 730 struct ionic_admin_ctx ctx = { 731 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 732 .cmd.q_init = { 733 .opcode = IONIC_CMD_Q_INIT, 734 .lif_index = cpu_to_le16(lif->index), 735 .type = q->type, 736 .ver = lif->qtype_info[q->type].version, 737 .index = cpu_to_le32(q->index), 738 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 739 IONIC_QINIT_F_SG), 740 .pid = cpu_to_le16(q->pid), 741 .ring_size = ilog2(q->num_descs), 742 .ring_base = cpu_to_le64(q->base_pa), 743 .cq_ring_base = cpu_to_le64(cq->base_pa), 744 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 745 .features = cpu_to_le64(q->features), 746 }, 747 }; 748 unsigned int intr_index; 749 int err; 750 751 intr_index = qcq->intr.index; 752 753 ctx.cmd.q_init.intr_index = cpu_to_le16(intr_index); 754 755 dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid); 756 dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index); 757 dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 758 dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 759 dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 760 dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver); 761 dev_dbg(dev, "txq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 762 763 ionic_qcq_sanitize(qcq); 764 765 err = ionic_adminq_post_wait(lif, &ctx); 766 if (err) 767 return err; 768 769 q->hw_type = ctx.comp.q_init.hw_type; 770 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 771 q->dbval = IONIC_DBELL_QID(q->hw_index); 772 773 dev_dbg(dev, "txq->hw_type %d\n", q->hw_type); 774 dev_dbg(dev, "txq->hw_index %d\n", q->hw_index); 775 776 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 777 netif_napi_add(lif->netdev, &qcq->napi, ionic_tx_napi); 778 779 qcq->flags |= IONIC_QCQ_F_INITED; 780 781 return 0; 782 } 783 784 static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 785 { 786 struct device *dev = lif->ionic->dev; 787 struct ionic_queue *q = &qcq->q; 788 struct ionic_cq *cq = &qcq->cq; 789 struct ionic_admin_ctx ctx = { 790 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 791 .cmd.q_init = { 792 .opcode = IONIC_CMD_Q_INIT, 793 .lif_index = cpu_to_le16(lif->index), 794 .type = q->type, 795 .ver = lif->qtype_info[q->type].version, 796 .index = cpu_to_le32(q->index), 797 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 798 IONIC_QINIT_F_SG), 799 .intr_index = cpu_to_le16(cq->bound_intr->index), 800 .pid = cpu_to_le16(q->pid), 801 .ring_size = ilog2(q->num_descs), 802 .ring_base = cpu_to_le64(q->base_pa), 803 .cq_ring_base = cpu_to_le64(cq->base_pa), 804 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 805 .features = cpu_to_le64(q->features), 806 }, 807 }; 808 int err; 809 810 dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid); 811 dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index); 812 dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 813 dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 814 dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 815 dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver); 816 dev_dbg(dev, "rxq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 817 818 ionic_qcq_sanitize(qcq); 819 820 err = ionic_adminq_post_wait(lif, &ctx); 821 if (err) 822 return err; 823 824 q->hw_type = ctx.comp.q_init.hw_type; 825 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 826 q->dbval = IONIC_DBELL_QID(q->hw_index); 827 828 dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type); 829 dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index); 830 831 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 832 netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi); 833 else 834 netif_napi_add(lif->netdev, &qcq->napi, ionic_txrx_napi); 835 836 qcq->flags |= IONIC_QCQ_F_INITED; 837 838 return 0; 839 } 840 841 int ionic_lif_create_hwstamp_txq(struct ionic_lif *lif) 842 { 843 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz; 844 unsigned int txq_i, flags; 845 struct ionic_qcq *txq; 846 u64 features; 847 int err; 848 849 if (lif->hwstamp_txq) 850 return 0; 851 852 features = IONIC_Q_F_2X_CQ_DESC | IONIC_TXQ_F_HWSTAMP; 853 854 num_desc = IONIC_MIN_TXRX_DESC; 855 desc_sz = sizeof(struct ionic_txq_desc); 856 comp_sz = 2 * sizeof(struct ionic_txq_comp); 857 858 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 859 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == sizeof(struct ionic_txq_sg_desc_v1)) 860 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 861 else 862 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 863 864 txq_i = lif->ionic->ntxqs_per_lif; 865 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 866 867 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, txq_i, "hwstamp_tx", flags, 868 num_desc, desc_sz, comp_sz, sg_desc_sz, 869 lif->kern_pid, &txq); 870 if (err) 871 goto err_qcq_alloc; 872 873 txq->q.features = features; 874 875 ionic_link_qcq_interrupts(lif->adminqcq, txq); 876 ionic_debugfs_add_qcq(lif, txq); 877 878 lif->hwstamp_txq = txq; 879 880 if (netif_running(lif->netdev)) { 881 err = ionic_lif_txq_init(lif, txq); 882 if (err) 883 goto err_qcq_init; 884 885 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 886 err = ionic_qcq_enable(txq); 887 if (err) 888 goto err_qcq_enable; 889 } 890 } 891 892 return 0; 893 894 err_qcq_enable: 895 ionic_lif_qcq_deinit(lif, txq); 896 err_qcq_init: 897 lif->hwstamp_txq = NULL; 898 ionic_debugfs_del_qcq(txq); 899 ionic_qcq_free(lif, txq); 900 devm_kfree(lif->ionic->dev, txq); 901 err_qcq_alloc: 902 return err; 903 } 904 905 int ionic_lif_create_hwstamp_rxq(struct ionic_lif *lif) 906 { 907 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz; 908 unsigned int rxq_i, flags; 909 struct ionic_qcq *rxq; 910 u64 features; 911 int err; 912 913 if (lif->hwstamp_rxq) 914 return 0; 915 916 features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP; 917 918 num_desc = IONIC_MIN_TXRX_DESC; 919 desc_sz = sizeof(struct ionic_rxq_desc); 920 comp_sz = 2 * sizeof(struct ionic_rxq_comp); 921 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 922 923 rxq_i = lif->ionic->nrxqs_per_lif; 924 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG; 925 926 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, rxq_i, "hwstamp_rx", flags, 927 num_desc, desc_sz, comp_sz, sg_desc_sz, 928 lif->kern_pid, &rxq); 929 if (err) 930 goto err_qcq_alloc; 931 932 rxq->q.features = features; 933 934 ionic_link_qcq_interrupts(lif->adminqcq, rxq); 935 ionic_debugfs_add_qcq(lif, rxq); 936 937 lif->hwstamp_rxq = rxq; 938 939 if (netif_running(lif->netdev)) { 940 err = ionic_lif_rxq_init(lif, rxq); 941 if (err) 942 goto err_qcq_init; 943 944 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 945 ionic_rx_fill(&rxq->q); 946 err = ionic_qcq_enable(rxq); 947 if (err) 948 goto err_qcq_enable; 949 } 950 } 951 952 return 0; 953 954 err_qcq_enable: 955 ionic_lif_qcq_deinit(lif, rxq); 956 err_qcq_init: 957 lif->hwstamp_rxq = NULL; 958 ionic_debugfs_del_qcq(rxq); 959 ionic_qcq_free(lif, rxq); 960 devm_kfree(lif->ionic->dev, rxq); 961 err_qcq_alloc: 962 return err; 963 } 964 965 int ionic_lif_config_hwstamp_rxq_all(struct ionic_lif *lif, bool rx_all) 966 { 967 struct ionic_queue_params qparam; 968 969 ionic_init_queue_params(lif, &qparam); 970 971 if (rx_all) 972 qparam.rxq_features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP; 973 else 974 qparam.rxq_features = 0; 975 976 /* if we're not running, just set the values and return */ 977 if (!netif_running(lif->netdev)) { 978 lif->rxq_features = qparam.rxq_features; 979 return 0; 980 } 981 982 return ionic_reconfigure_queues(lif, &qparam); 983 } 984 985 int ionic_lif_set_hwstamp_txmode(struct ionic_lif *lif, u16 txstamp_mode) 986 { 987 struct ionic_admin_ctx ctx = { 988 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 989 .cmd.lif_setattr = { 990 .opcode = IONIC_CMD_LIF_SETATTR, 991 .index = cpu_to_le16(lif->index), 992 .attr = IONIC_LIF_ATTR_TXSTAMP, 993 .txstamp_mode = cpu_to_le16(txstamp_mode), 994 }, 995 }; 996 997 return ionic_adminq_post_wait(lif, &ctx); 998 } 999 1000 static void ionic_lif_del_hwstamp_rxfilt(struct ionic_lif *lif) 1001 { 1002 struct ionic_admin_ctx ctx = { 1003 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1004 .cmd.rx_filter_del = { 1005 .opcode = IONIC_CMD_RX_FILTER_DEL, 1006 .lif_index = cpu_to_le16(lif->index), 1007 }, 1008 }; 1009 struct ionic_rx_filter *f; 1010 u32 filter_id; 1011 int err; 1012 1013 spin_lock_bh(&lif->rx_filters.lock); 1014 1015 f = ionic_rx_filter_rxsteer(lif); 1016 if (!f) { 1017 spin_unlock_bh(&lif->rx_filters.lock); 1018 return; 1019 } 1020 1021 filter_id = f->filter_id; 1022 ionic_rx_filter_free(lif, f); 1023 1024 spin_unlock_bh(&lif->rx_filters.lock); 1025 1026 netdev_dbg(lif->netdev, "rx_filter del RXSTEER (id %d)\n", filter_id); 1027 1028 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(filter_id); 1029 1030 err = ionic_adminq_post_wait(lif, &ctx); 1031 if (err && err != -EEXIST) 1032 netdev_dbg(lif->netdev, "failed to delete rx_filter RXSTEER (id %d)\n", filter_id); 1033 } 1034 1035 static int ionic_lif_add_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class) 1036 { 1037 struct ionic_admin_ctx ctx = { 1038 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1039 .cmd.rx_filter_add = { 1040 .opcode = IONIC_CMD_RX_FILTER_ADD, 1041 .lif_index = cpu_to_le16(lif->index), 1042 .match = cpu_to_le16(IONIC_RX_FILTER_STEER_PKTCLASS), 1043 .pkt_class = cpu_to_le64(pkt_class), 1044 }, 1045 }; 1046 u8 qtype; 1047 u32 qid; 1048 int err; 1049 1050 if (!lif->hwstamp_rxq) 1051 return -EINVAL; 1052 1053 qtype = lif->hwstamp_rxq->q.type; 1054 ctx.cmd.rx_filter_add.qtype = qtype; 1055 1056 qid = lif->hwstamp_rxq->q.index; 1057 ctx.cmd.rx_filter_add.qid = cpu_to_le32(qid); 1058 1059 netdev_dbg(lif->netdev, "rx_filter add RXSTEER\n"); 1060 err = ionic_adminq_post_wait(lif, &ctx); 1061 if (err && err != -EEXIST) 1062 return err; 1063 1064 spin_lock_bh(&lif->rx_filters.lock); 1065 err = ionic_rx_filter_save(lif, 0, qid, 0, &ctx, IONIC_FILTER_STATE_SYNCED); 1066 spin_unlock_bh(&lif->rx_filters.lock); 1067 1068 return err; 1069 } 1070 1071 int ionic_lif_set_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class) 1072 { 1073 ionic_lif_del_hwstamp_rxfilt(lif); 1074 1075 if (!pkt_class) 1076 return 0; 1077 1078 return ionic_lif_add_hwstamp_rxfilt(lif, pkt_class); 1079 } 1080 1081 static bool ionic_notifyq_service(struct ionic_cq *cq, 1082 struct ionic_cq_info *cq_info) 1083 { 1084 union ionic_notifyq_comp *comp = cq_info->cq_desc; 1085 struct ionic_deferred_work *work; 1086 struct net_device *netdev; 1087 struct ionic_queue *q; 1088 struct ionic_lif *lif; 1089 u64 eid; 1090 1091 q = cq->bound_q; 1092 lif = q->info[0].cb_arg; 1093 netdev = lif->netdev; 1094 eid = le64_to_cpu(comp->event.eid); 1095 1096 /* Have we run out of new completions to process? */ 1097 if ((s64)(eid - lif->last_eid) <= 0) 1098 return false; 1099 1100 lif->last_eid = eid; 1101 1102 dev_dbg(lif->ionic->dev, "notifyq event:\n"); 1103 dynamic_hex_dump("event ", DUMP_PREFIX_OFFSET, 16, 1, 1104 comp, sizeof(*comp), true); 1105 1106 switch (le16_to_cpu(comp->event.ecode)) { 1107 case IONIC_EVENT_LINK_CHANGE: 1108 ionic_link_status_check_request(lif, CAN_NOT_SLEEP); 1109 break; 1110 case IONIC_EVENT_RESET: 1111 if (lif->ionic->idev.fw_status_ready && 1112 !test_bit(IONIC_LIF_F_FW_RESET, lif->state) && 1113 !test_and_set_bit(IONIC_LIF_F_FW_STOPPING, lif->state)) { 1114 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1115 if (!work) { 1116 netdev_err(lif->netdev, "Reset event dropped\n"); 1117 clear_bit(IONIC_LIF_F_FW_STOPPING, lif->state); 1118 } else { 1119 work->type = IONIC_DW_TYPE_LIF_RESET; 1120 ionic_lif_deferred_enqueue(&lif->deferred, work); 1121 } 1122 } 1123 break; 1124 default: 1125 netdev_warn(netdev, "Notifyq event ecode=%d eid=%lld\n", 1126 comp->event.ecode, eid); 1127 break; 1128 } 1129 1130 return true; 1131 } 1132 1133 static bool ionic_adminq_service(struct ionic_cq *cq, 1134 struct ionic_cq_info *cq_info) 1135 { 1136 struct ionic_admin_comp *comp = cq_info->cq_desc; 1137 1138 if (!color_match(comp->color, cq->done_color)) 1139 return false; 1140 1141 ionic_q_service(cq->bound_q, cq_info, le16_to_cpu(comp->comp_index)); 1142 1143 return true; 1144 } 1145 1146 static int ionic_adminq_napi(struct napi_struct *napi, int budget) 1147 { 1148 struct ionic_intr_info *intr = napi_to_cq(napi)->bound_intr; 1149 struct ionic_lif *lif = napi_to_cq(napi)->lif; 1150 struct ionic_dev *idev = &lif->ionic->idev; 1151 unsigned long irqflags; 1152 unsigned int flags = 0; 1153 int rx_work = 0; 1154 int tx_work = 0; 1155 int n_work = 0; 1156 int a_work = 0; 1157 int work_done; 1158 int credits; 1159 1160 if (lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED) 1161 n_work = ionic_cq_service(&lif->notifyqcq->cq, budget, 1162 ionic_notifyq_service, NULL, NULL); 1163 1164 spin_lock_irqsave(&lif->adminq_lock, irqflags); 1165 if (lif->adminqcq && lif->adminqcq->flags & IONIC_QCQ_F_INITED) 1166 a_work = ionic_cq_service(&lif->adminqcq->cq, budget, 1167 ionic_adminq_service, NULL, NULL); 1168 spin_unlock_irqrestore(&lif->adminq_lock, irqflags); 1169 1170 if (lif->hwstamp_rxq) 1171 rx_work = ionic_cq_service(&lif->hwstamp_rxq->cq, budget, 1172 ionic_rx_service, NULL, NULL); 1173 1174 if (lif->hwstamp_txq) 1175 tx_work = ionic_cq_service(&lif->hwstamp_txq->cq, budget, 1176 ionic_tx_service, NULL, NULL); 1177 1178 work_done = max(max(n_work, a_work), max(rx_work, tx_work)); 1179 if (work_done < budget && napi_complete_done(napi, work_done)) { 1180 flags |= IONIC_INTR_CRED_UNMASK; 1181 intr->rearm_count++; 1182 } 1183 1184 if (work_done || flags) { 1185 flags |= IONIC_INTR_CRED_RESET_COALESCE; 1186 credits = n_work + a_work + rx_work + tx_work; 1187 ionic_intr_credits(idev->intr_ctrl, intr->index, credits, flags); 1188 } 1189 1190 return work_done; 1191 } 1192 1193 void ionic_get_stats64(struct net_device *netdev, 1194 struct rtnl_link_stats64 *ns) 1195 { 1196 struct ionic_lif *lif = netdev_priv(netdev); 1197 struct ionic_lif_stats *ls; 1198 1199 memset(ns, 0, sizeof(*ns)); 1200 ls = &lif->info->stats; 1201 1202 ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) + 1203 le64_to_cpu(ls->rx_mcast_packets) + 1204 le64_to_cpu(ls->rx_bcast_packets); 1205 1206 ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) + 1207 le64_to_cpu(ls->tx_mcast_packets) + 1208 le64_to_cpu(ls->tx_bcast_packets); 1209 1210 ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) + 1211 le64_to_cpu(ls->rx_mcast_bytes) + 1212 le64_to_cpu(ls->rx_bcast_bytes); 1213 1214 ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) + 1215 le64_to_cpu(ls->tx_mcast_bytes) + 1216 le64_to_cpu(ls->tx_bcast_bytes); 1217 1218 ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) + 1219 le64_to_cpu(ls->rx_mcast_drop_packets) + 1220 le64_to_cpu(ls->rx_bcast_drop_packets); 1221 1222 ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) + 1223 le64_to_cpu(ls->tx_mcast_drop_packets) + 1224 le64_to_cpu(ls->tx_bcast_drop_packets); 1225 1226 ns->multicast = le64_to_cpu(ls->rx_mcast_packets); 1227 1228 ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty); 1229 1230 ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) + 1231 le64_to_cpu(ls->rx_queue_disabled) + 1232 le64_to_cpu(ls->rx_desc_fetch_error) + 1233 le64_to_cpu(ls->rx_desc_data_error); 1234 1235 ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) + 1236 le64_to_cpu(ls->tx_queue_disabled) + 1237 le64_to_cpu(ls->tx_desc_fetch_error) + 1238 le64_to_cpu(ls->tx_desc_data_error); 1239 1240 ns->rx_errors = ns->rx_over_errors + 1241 ns->rx_missed_errors; 1242 1243 ns->tx_errors = ns->tx_aborted_errors; 1244 } 1245 1246 static int ionic_addr_add(struct net_device *netdev, const u8 *addr) 1247 { 1248 return ionic_lif_list_addr(netdev_priv(netdev), addr, ADD_ADDR); 1249 } 1250 1251 static int ionic_addr_del(struct net_device *netdev, const u8 *addr) 1252 { 1253 /* Don't delete our own address from the uc list */ 1254 if (ether_addr_equal(addr, netdev->dev_addr)) 1255 return 0; 1256 1257 return ionic_lif_list_addr(netdev_priv(netdev), addr, DEL_ADDR); 1258 } 1259 1260 void ionic_lif_rx_mode(struct ionic_lif *lif) 1261 { 1262 struct net_device *netdev = lif->netdev; 1263 unsigned int nfilters; 1264 unsigned int nd_flags; 1265 char buf[128]; 1266 u16 rx_mode; 1267 int i; 1268 #define REMAIN(__x) (sizeof(buf) - (__x)) 1269 1270 mutex_lock(&lif->config_lock); 1271 1272 /* grab the flags once for local use */ 1273 nd_flags = netdev->flags; 1274 1275 rx_mode = IONIC_RX_MODE_F_UNICAST; 1276 rx_mode |= (nd_flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0; 1277 rx_mode |= (nd_flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0; 1278 rx_mode |= (nd_flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0; 1279 rx_mode |= (nd_flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0; 1280 1281 /* sync the filters */ 1282 ionic_rx_filter_sync(lif); 1283 1284 /* check for overflow state 1285 * if so, we track that we overflowed and enable NIC PROMISC 1286 * else if the overflow is set and not needed 1287 * we remove our overflow flag and check the netdev flags 1288 * to see if we can disable NIC PROMISC 1289 */ 1290 nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters); 1291 1292 if (((lif->nucast + lif->nmcast) >= nfilters) || 1293 (lif->max_vlans && lif->nvlans >= lif->max_vlans)) { 1294 rx_mode |= IONIC_RX_MODE_F_PROMISC; 1295 rx_mode |= IONIC_RX_MODE_F_ALLMULTI; 1296 } else { 1297 if (!(nd_flags & IFF_PROMISC)) 1298 rx_mode &= ~IONIC_RX_MODE_F_PROMISC; 1299 if (!(nd_flags & IFF_ALLMULTI)) 1300 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI; 1301 } 1302 1303 i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:", 1304 lif->rx_mode, rx_mode); 1305 if (rx_mode & IONIC_RX_MODE_F_UNICAST) 1306 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST"); 1307 if (rx_mode & IONIC_RX_MODE_F_MULTICAST) 1308 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST"); 1309 if (rx_mode & IONIC_RX_MODE_F_BROADCAST) 1310 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST"); 1311 if (rx_mode & IONIC_RX_MODE_F_PROMISC) 1312 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC"); 1313 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI) 1314 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI"); 1315 if (rx_mode & IONIC_RX_MODE_F_RDMA_SNIFFER) 1316 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_RDMA_SNIFFER"); 1317 netdev_dbg(netdev, "lif%d %s\n", lif->index, buf); 1318 1319 if (lif->rx_mode != rx_mode) { 1320 struct ionic_admin_ctx ctx = { 1321 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1322 .cmd.rx_mode_set = { 1323 .opcode = IONIC_CMD_RX_MODE_SET, 1324 .lif_index = cpu_to_le16(lif->index), 1325 }, 1326 }; 1327 int err; 1328 1329 ctx.cmd.rx_mode_set.rx_mode = cpu_to_le16(rx_mode); 1330 err = ionic_adminq_post_wait(lif, &ctx); 1331 if (err) 1332 netdev_warn(netdev, "set rx_mode 0x%04x failed: %d\n", 1333 rx_mode, err); 1334 else 1335 lif->rx_mode = rx_mode; 1336 } 1337 1338 mutex_unlock(&lif->config_lock); 1339 } 1340 1341 static void ionic_ndo_set_rx_mode(struct net_device *netdev) 1342 { 1343 struct ionic_lif *lif = netdev_priv(netdev); 1344 struct ionic_deferred_work *work; 1345 1346 /* Sync the kernel filter list with the driver filter list */ 1347 __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del); 1348 __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del); 1349 1350 /* Shove off the rest of the rxmode work to the work task 1351 * which will include syncing the filters to the firmware. 1352 */ 1353 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1354 if (!work) { 1355 netdev_err(lif->netdev, "rxmode change dropped\n"); 1356 return; 1357 } 1358 work->type = IONIC_DW_TYPE_RX_MODE; 1359 netdev_dbg(lif->netdev, "deferred: rx_mode\n"); 1360 ionic_lif_deferred_enqueue(&lif->deferred, work); 1361 } 1362 1363 static __le64 ionic_netdev_features_to_nic(netdev_features_t features) 1364 { 1365 u64 wanted = 0; 1366 1367 if (features & NETIF_F_HW_VLAN_CTAG_TX) 1368 wanted |= IONIC_ETH_HW_VLAN_TX_TAG; 1369 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1370 wanted |= IONIC_ETH_HW_VLAN_RX_STRIP; 1371 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1372 wanted |= IONIC_ETH_HW_VLAN_RX_FILTER; 1373 if (features & NETIF_F_RXHASH) 1374 wanted |= IONIC_ETH_HW_RX_HASH; 1375 if (features & NETIF_F_RXCSUM) 1376 wanted |= IONIC_ETH_HW_RX_CSUM; 1377 if (features & NETIF_F_SG) 1378 wanted |= IONIC_ETH_HW_TX_SG; 1379 if (features & NETIF_F_HW_CSUM) 1380 wanted |= IONIC_ETH_HW_TX_CSUM; 1381 if (features & NETIF_F_TSO) 1382 wanted |= IONIC_ETH_HW_TSO; 1383 if (features & NETIF_F_TSO6) 1384 wanted |= IONIC_ETH_HW_TSO_IPV6; 1385 if (features & NETIF_F_TSO_ECN) 1386 wanted |= IONIC_ETH_HW_TSO_ECN; 1387 if (features & NETIF_F_GSO_GRE) 1388 wanted |= IONIC_ETH_HW_TSO_GRE; 1389 if (features & NETIF_F_GSO_GRE_CSUM) 1390 wanted |= IONIC_ETH_HW_TSO_GRE_CSUM; 1391 if (features & NETIF_F_GSO_IPXIP4) 1392 wanted |= IONIC_ETH_HW_TSO_IPXIP4; 1393 if (features & NETIF_F_GSO_IPXIP6) 1394 wanted |= IONIC_ETH_HW_TSO_IPXIP6; 1395 if (features & NETIF_F_GSO_UDP_TUNNEL) 1396 wanted |= IONIC_ETH_HW_TSO_UDP; 1397 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) 1398 wanted |= IONIC_ETH_HW_TSO_UDP_CSUM; 1399 1400 return cpu_to_le64(wanted); 1401 } 1402 1403 static int ionic_set_nic_features(struct ionic_lif *lif, 1404 netdev_features_t features) 1405 { 1406 struct device *dev = lif->ionic->dev; 1407 struct ionic_admin_ctx ctx = { 1408 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1409 .cmd.lif_setattr = { 1410 .opcode = IONIC_CMD_LIF_SETATTR, 1411 .index = cpu_to_le16(lif->index), 1412 .attr = IONIC_LIF_ATTR_FEATURES, 1413 }, 1414 }; 1415 u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG | 1416 IONIC_ETH_HW_VLAN_RX_STRIP | 1417 IONIC_ETH_HW_VLAN_RX_FILTER; 1418 u64 old_hw_features; 1419 int err; 1420 1421 ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features); 1422 1423 if (lif->phc) 1424 ctx.cmd.lif_setattr.features |= cpu_to_le64(IONIC_ETH_HW_TIMESTAMP); 1425 1426 err = ionic_adminq_post_wait(lif, &ctx); 1427 if (err) 1428 return err; 1429 1430 old_hw_features = lif->hw_features; 1431 lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features & 1432 ctx.comp.lif_setattr.features); 1433 1434 if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH) 1435 ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1436 1437 if ((vlan_flags & le64_to_cpu(ctx.cmd.lif_setattr.features)) && 1438 !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features))) 1439 dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n"); 1440 1441 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1442 dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n"); 1443 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1444 dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n"); 1445 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1446 dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n"); 1447 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1448 dev_dbg(dev, "feature ETH_HW_RX_HASH\n"); 1449 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1450 dev_dbg(dev, "feature ETH_HW_TX_SG\n"); 1451 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1452 dev_dbg(dev, "feature ETH_HW_TX_CSUM\n"); 1453 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1454 dev_dbg(dev, "feature ETH_HW_RX_CSUM\n"); 1455 if (lif->hw_features & IONIC_ETH_HW_TSO) 1456 dev_dbg(dev, "feature ETH_HW_TSO\n"); 1457 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1458 dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n"); 1459 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1460 dev_dbg(dev, "feature ETH_HW_TSO_ECN\n"); 1461 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1462 dev_dbg(dev, "feature ETH_HW_TSO_GRE\n"); 1463 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1464 dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n"); 1465 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1466 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n"); 1467 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1468 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n"); 1469 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1470 dev_dbg(dev, "feature ETH_HW_TSO_UDP\n"); 1471 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1472 dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n"); 1473 if (lif->hw_features & IONIC_ETH_HW_TIMESTAMP) 1474 dev_dbg(dev, "feature ETH_HW_TIMESTAMP\n"); 1475 1476 return 0; 1477 } 1478 1479 static int ionic_init_nic_features(struct ionic_lif *lif) 1480 { 1481 struct net_device *netdev = lif->netdev; 1482 netdev_features_t features; 1483 int err; 1484 1485 /* set up what we expect to support by default */ 1486 features = NETIF_F_HW_VLAN_CTAG_TX | 1487 NETIF_F_HW_VLAN_CTAG_RX | 1488 NETIF_F_HW_VLAN_CTAG_FILTER | 1489 NETIF_F_SG | 1490 NETIF_F_HW_CSUM | 1491 NETIF_F_RXCSUM | 1492 NETIF_F_TSO | 1493 NETIF_F_TSO6 | 1494 NETIF_F_TSO_ECN; 1495 1496 if (lif->nxqs > 1) 1497 features |= NETIF_F_RXHASH; 1498 1499 err = ionic_set_nic_features(lif, features); 1500 if (err) 1501 return err; 1502 1503 /* tell the netdev what we actually can support */ 1504 netdev->features |= NETIF_F_HIGHDMA; 1505 1506 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1507 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 1508 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1509 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 1510 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1511 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1512 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1513 netdev->hw_features |= NETIF_F_RXHASH; 1514 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1515 netdev->hw_features |= NETIF_F_SG; 1516 1517 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1518 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 1519 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1520 netdev->hw_enc_features |= NETIF_F_RXCSUM; 1521 if (lif->hw_features & IONIC_ETH_HW_TSO) 1522 netdev->hw_enc_features |= NETIF_F_TSO; 1523 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1524 netdev->hw_enc_features |= NETIF_F_TSO6; 1525 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1526 netdev->hw_enc_features |= NETIF_F_TSO_ECN; 1527 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1528 netdev->hw_enc_features |= NETIF_F_GSO_GRE; 1529 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1530 netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM; 1531 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1532 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4; 1533 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1534 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6; 1535 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1536 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL; 1537 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1538 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 1539 1540 netdev->hw_features |= netdev->hw_enc_features; 1541 netdev->features |= netdev->hw_features; 1542 netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES; 1543 1544 netdev->priv_flags |= IFF_UNICAST_FLT | 1545 IFF_LIVE_ADDR_CHANGE; 1546 1547 return 0; 1548 } 1549 1550 static int ionic_set_features(struct net_device *netdev, 1551 netdev_features_t features) 1552 { 1553 struct ionic_lif *lif = netdev_priv(netdev); 1554 int err; 1555 1556 netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n", 1557 __func__, (u64)lif->netdev->features, (u64)features); 1558 1559 err = ionic_set_nic_features(lif, features); 1560 1561 return err; 1562 } 1563 1564 static int ionic_set_attr_mac(struct ionic_lif *lif, u8 *mac) 1565 { 1566 struct ionic_admin_ctx ctx = { 1567 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1568 .cmd.lif_setattr = { 1569 .opcode = IONIC_CMD_LIF_SETATTR, 1570 .index = cpu_to_le16(lif->index), 1571 .attr = IONIC_LIF_ATTR_MAC, 1572 }, 1573 }; 1574 1575 ether_addr_copy(ctx.cmd.lif_setattr.mac, mac); 1576 return ionic_adminq_post_wait(lif, &ctx); 1577 } 1578 1579 static int ionic_get_attr_mac(struct ionic_lif *lif, u8 *mac_addr) 1580 { 1581 struct ionic_admin_ctx ctx = { 1582 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1583 .cmd.lif_getattr = { 1584 .opcode = IONIC_CMD_LIF_GETATTR, 1585 .index = cpu_to_le16(lif->index), 1586 .attr = IONIC_LIF_ATTR_MAC, 1587 }, 1588 }; 1589 int err; 1590 1591 err = ionic_adminq_post_wait(lif, &ctx); 1592 if (err) 1593 return err; 1594 1595 ether_addr_copy(mac_addr, ctx.comp.lif_getattr.mac); 1596 return 0; 1597 } 1598 1599 static int ionic_program_mac(struct ionic_lif *lif, u8 *mac) 1600 { 1601 u8 get_mac[ETH_ALEN]; 1602 int err; 1603 1604 err = ionic_set_attr_mac(lif, mac); 1605 if (err) 1606 return err; 1607 1608 err = ionic_get_attr_mac(lif, get_mac); 1609 if (err) 1610 return err; 1611 1612 /* To deal with older firmware that silently ignores the set attr mac: 1613 * doesn't actually change the mac and doesn't return an error, so we 1614 * do the get attr to verify whether or not the set actually happened 1615 */ 1616 if (!ether_addr_equal(get_mac, mac)) 1617 return 1; 1618 1619 return 0; 1620 } 1621 1622 static int ionic_set_mac_address(struct net_device *netdev, void *sa) 1623 { 1624 struct ionic_lif *lif = netdev_priv(netdev); 1625 struct sockaddr *addr = sa; 1626 u8 *mac; 1627 int err; 1628 1629 mac = (u8 *)addr->sa_data; 1630 if (ether_addr_equal(netdev->dev_addr, mac)) 1631 return 0; 1632 1633 err = ionic_program_mac(lif, mac); 1634 if (err < 0) 1635 return err; 1636 1637 if (err > 0) 1638 netdev_dbg(netdev, "%s: SET and GET ATTR Mac are not equal-due to old FW running\n", 1639 __func__); 1640 1641 err = eth_prepare_mac_addr_change(netdev, addr); 1642 if (err) 1643 return err; 1644 1645 if (!is_zero_ether_addr(netdev->dev_addr)) { 1646 netdev_info(netdev, "deleting mac addr %pM\n", 1647 netdev->dev_addr); 1648 ionic_lif_addr_del(netdev_priv(netdev), netdev->dev_addr); 1649 } 1650 1651 eth_commit_mac_addr_change(netdev, addr); 1652 netdev_info(netdev, "updating mac addr %pM\n", mac); 1653 1654 return ionic_lif_addr_add(netdev_priv(netdev), mac); 1655 } 1656 1657 static void ionic_stop_queues_reconfig(struct ionic_lif *lif) 1658 { 1659 /* Stop and clean the queues before reconfiguration */ 1660 netif_device_detach(lif->netdev); 1661 ionic_stop_queues(lif); 1662 ionic_txrx_deinit(lif); 1663 } 1664 1665 static int ionic_start_queues_reconfig(struct ionic_lif *lif) 1666 { 1667 int err; 1668 1669 /* Re-init the queues after reconfiguration */ 1670 1671 /* The only way txrx_init can fail here is if communication 1672 * with FW is suddenly broken. There's not much we can do 1673 * at this point - error messages have already been printed, 1674 * so we can continue on and the user can eventually do a 1675 * DOWN and UP to try to reset and clear the issue. 1676 */ 1677 err = ionic_txrx_init(lif); 1678 ionic_link_status_check_request(lif, CAN_NOT_SLEEP); 1679 netif_device_attach(lif->netdev); 1680 1681 return err; 1682 } 1683 1684 static int ionic_change_mtu(struct net_device *netdev, int new_mtu) 1685 { 1686 struct ionic_lif *lif = netdev_priv(netdev); 1687 struct ionic_admin_ctx ctx = { 1688 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1689 .cmd.lif_setattr = { 1690 .opcode = IONIC_CMD_LIF_SETATTR, 1691 .index = cpu_to_le16(lif->index), 1692 .attr = IONIC_LIF_ATTR_MTU, 1693 .mtu = cpu_to_le32(new_mtu), 1694 }, 1695 }; 1696 int err; 1697 1698 err = ionic_adminq_post_wait(lif, &ctx); 1699 if (err) 1700 return err; 1701 1702 /* if we're not running, nothing more to do */ 1703 if (!netif_running(netdev)) { 1704 netdev->mtu = new_mtu; 1705 return 0; 1706 } 1707 1708 mutex_lock(&lif->queue_lock); 1709 ionic_stop_queues_reconfig(lif); 1710 netdev->mtu = new_mtu; 1711 err = ionic_start_queues_reconfig(lif); 1712 mutex_unlock(&lif->queue_lock); 1713 1714 return err; 1715 } 1716 1717 static void ionic_tx_timeout_work(struct work_struct *ws) 1718 { 1719 struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work); 1720 1721 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 1722 return; 1723 1724 /* if we were stopped before this scheduled job was launched, 1725 * don't bother the queues as they are already stopped. 1726 */ 1727 if (!netif_running(lif->netdev)) 1728 return; 1729 1730 mutex_lock(&lif->queue_lock); 1731 ionic_stop_queues_reconfig(lif); 1732 ionic_start_queues_reconfig(lif); 1733 mutex_unlock(&lif->queue_lock); 1734 } 1735 1736 static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1737 { 1738 struct ionic_lif *lif = netdev_priv(netdev); 1739 1740 netdev_info(lif->netdev, "Tx Timeout triggered - txq %d\n", txqueue); 1741 schedule_work(&lif->tx_timeout_work); 1742 } 1743 1744 static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, 1745 u16 vid) 1746 { 1747 struct ionic_lif *lif = netdev_priv(netdev); 1748 int err; 1749 1750 err = ionic_lif_vlan_add(lif, vid); 1751 if (err) 1752 return err; 1753 1754 ionic_lif_rx_mode(lif); 1755 1756 return 0; 1757 } 1758 1759 static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, 1760 u16 vid) 1761 { 1762 struct ionic_lif *lif = netdev_priv(netdev); 1763 int err; 1764 1765 err = ionic_lif_vlan_del(lif, vid); 1766 if (err) 1767 return err; 1768 1769 ionic_lif_rx_mode(lif); 1770 1771 return 0; 1772 } 1773 1774 int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types, 1775 const u8 *key, const u32 *indir) 1776 { 1777 struct ionic_admin_ctx ctx = { 1778 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1779 .cmd.lif_setattr = { 1780 .opcode = IONIC_CMD_LIF_SETATTR, 1781 .attr = IONIC_LIF_ATTR_RSS, 1782 .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa), 1783 }, 1784 }; 1785 unsigned int i, tbl_sz; 1786 1787 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) { 1788 lif->rss_types = types; 1789 ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types); 1790 } 1791 1792 if (key) 1793 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE); 1794 1795 if (indir) { 1796 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1797 for (i = 0; i < tbl_sz; i++) 1798 lif->rss_ind_tbl[i] = indir[i]; 1799 } 1800 1801 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key, 1802 IONIC_RSS_HASH_KEY_SIZE); 1803 1804 return ionic_adminq_post_wait(lif, &ctx); 1805 } 1806 1807 static int ionic_lif_rss_init(struct ionic_lif *lif) 1808 { 1809 unsigned int tbl_sz; 1810 unsigned int i; 1811 1812 lif->rss_types = IONIC_RSS_TYPE_IPV4 | 1813 IONIC_RSS_TYPE_IPV4_TCP | 1814 IONIC_RSS_TYPE_IPV4_UDP | 1815 IONIC_RSS_TYPE_IPV6 | 1816 IONIC_RSS_TYPE_IPV6_TCP | 1817 IONIC_RSS_TYPE_IPV6_UDP; 1818 1819 /* Fill indirection table with 'default' values */ 1820 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1821 for (i = 0; i < tbl_sz; i++) 1822 lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs); 1823 1824 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1825 } 1826 1827 static void ionic_lif_rss_deinit(struct ionic_lif *lif) 1828 { 1829 int tbl_sz; 1830 1831 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1832 memset(lif->rss_ind_tbl, 0, tbl_sz); 1833 memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE); 1834 1835 ionic_lif_rss_config(lif, 0x0, NULL, NULL); 1836 } 1837 1838 static void ionic_lif_quiesce(struct ionic_lif *lif) 1839 { 1840 struct ionic_admin_ctx ctx = { 1841 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1842 .cmd.lif_setattr = { 1843 .opcode = IONIC_CMD_LIF_SETATTR, 1844 .index = cpu_to_le16(lif->index), 1845 .attr = IONIC_LIF_ATTR_STATE, 1846 .state = IONIC_LIF_QUIESCE, 1847 }, 1848 }; 1849 int err; 1850 1851 err = ionic_adminq_post_wait(lif, &ctx); 1852 if (err) 1853 netdev_dbg(lif->netdev, "lif quiesce failed %d\n", err); 1854 } 1855 1856 static void ionic_txrx_disable(struct ionic_lif *lif) 1857 { 1858 unsigned int i; 1859 int err = 0; 1860 1861 if (lif->txqcqs) { 1862 for (i = 0; i < lif->nxqs; i++) 1863 err = ionic_qcq_disable(lif, lif->txqcqs[i], err); 1864 } 1865 1866 if (lif->hwstamp_txq) 1867 err = ionic_qcq_disable(lif, lif->hwstamp_txq, err); 1868 1869 if (lif->rxqcqs) { 1870 for (i = 0; i < lif->nxqs; i++) 1871 err = ionic_qcq_disable(lif, lif->rxqcqs[i], err); 1872 } 1873 1874 if (lif->hwstamp_rxq) 1875 err = ionic_qcq_disable(lif, lif->hwstamp_rxq, err); 1876 1877 ionic_lif_quiesce(lif); 1878 } 1879 1880 static void ionic_txrx_deinit(struct ionic_lif *lif) 1881 { 1882 unsigned int i; 1883 1884 if (lif->txqcqs) { 1885 for (i = 0; i < lif->nxqs && lif->txqcqs[i]; i++) { 1886 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 1887 ionic_tx_flush(&lif->txqcqs[i]->cq); 1888 ionic_tx_empty(&lif->txqcqs[i]->q); 1889 } 1890 } 1891 1892 if (lif->rxqcqs) { 1893 for (i = 0; i < lif->nxqs && lif->rxqcqs[i]; i++) { 1894 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 1895 ionic_rx_empty(&lif->rxqcqs[i]->q); 1896 } 1897 } 1898 lif->rx_mode = 0; 1899 1900 if (lif->hwstamp_txq) { 1901 ionic_lif_qcq_deinit(lif, lif->hwstamp_txq); 1902 ionic_tx_flush(&lif->hwstamp_txq->cq); 1903 ionic_tx_empty(&lif->hwstamp_txq->q); 1904 } 1905 1906 if (lif->hwstamp_rxq) { 1907 ionic_lif_qcq_deinit(lif, lif->hwstamp_rxq); 1908 ionic_rx_empty(&lif->hwstamp_rxq->q); 1909 } 1910 } 1911 1912 static void ionic_txrx_free(struct ionic_lif *lif) 1913 { 1914 unsigned int i; 1915 1916 if (lif->txqcqs) { 1917 for (i = 0; i < lif->ionic->ntxqs_per_lif && lif->txqcqs[i]; i++) { 1918 ionic_qcq_free(lif, lif->txqcqs[i]); 1919 devm_kfree(lif->ionic->dev, lif->txqcqs[i]); 1920 lif->txqcqs[i] = NULL; 1921 } 1922 } 1923 1924 if (lif->rxqcqs) { 1925 for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) { 1926 ionic_qcq_free(lif, lif->rxqcqs[i]); 1927 devm_kfree(lif->ionic->dev, lif->rxqcqs[i]); 1928 lif->rxqcqs[i] = NULL; 1929 } 1930 } 1931 1932 if (lif->hwstamp_txq) { 1933 ionic_qcq_free(lif, lif->hwstamp_txq); 1934 devm_kfree(lif->ionic->dev, lif->hwstamp_txq); 1935 lif->hwstamp_txq = NULL; 1936 } 1937 1938 if (lif->hwstamp_rxq) { 1939 ionic_qcq_free(lif, lif->hwstamp_rxq); 1940 devm_kfree(lif->ionic->dev, lif->hwstamp_rxq); 1941 lif->hwstamp_rxq = NULL; 1942 } 1943 } 1944 1945 static int ionic_txrx_alloc(struct ionic_lif *lif) 1946 { 1947 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz; 1948 unsigned int flags, i; 1949 int err = 0; 1950 1951 num_desc = lif->ntxq_descs; 1952 desc_sz = sizeof(struct ionic_txq_desc); 1953 comp_sz = sizeof(struct ionic_txq_comp); 1954 1955 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 1956 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 1957 sizeof(struct ionic_txq_sg_desc_v1)) 1958 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 1959 else 1960 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 1961 1962 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 1963 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 1964 flags |= IONIC_QCQ_F_INTR; 1965 for (i = 0; i < lif->nxqs; i++) { 1966 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 1967 num_desc, desc_sz, comp_sz, sg_desc_sz, 1968 lif->kern_pid, &lif->txqcqs[i]); 1969 if (err) 1970 goto err_out; 1971 1972 if (flags & IONIC_QCQ_F_INTR) { 1973 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 1974 lif->txqcqs[i]->intr.index, 1975 lif->tx_coalesce_hw); 1976 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 1977 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 1978 } 1979 1980 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 1981 } 1982 1983 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG | IONIC_QCQ_F_INTR; 1984 1985 num_desc = lif->nrxq_descs; 1986 desc_sz = sizeof(struct ionic_rxq_desc); 1987 comp_sz = sizeof(struct ionic_rxq_comp); 1988 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 1989 1990 if (lif->rxq_features & IONIC_Q_F_2X_CQ_DESC) 1991 comp_sz *= 2; 1992 1993 for (i = 0; i < lif->nxqs; i++) { 1994 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 1995 num_desc, desc_sz, comp_sz, sg_desc_sz, 1996 lif->kern_pid, &lif->rxqcqs[i]); 1997 if (err) 1998 goto err_out; 1999 2000 lif->rxqcqs[i]->q.features = lif->rxq_features; 2001 2002 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2003 lif->rxqcqs[i]->intr.index, 2004 lif->rx_coalesce_hw); 2005 if (test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state)) 2006 lif->rxqcqs[i]->intr.dim_coal_hw = lif->rx_coalesce_hw; 2007 2008 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 2009 ionic_link_qcq_interrupts(lif->rxqcqs[i], 2010 lif->txqcqs[i]); 2011 2012 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 2013 } 2014 2015 return 0; 2016 2017 err_out: 2018 ionic_txrx_free(lif); 2019 2020 return err; 2021 } 2022 2023 static int ionic_txrx_init(struct ionic_lif *lif) 2024 { 2025 unsigned int i; 2026 int err; 2027 2028 for (i = 0; i < lif->nxqs; i++) { 2029 err = ionic_lif_txq_init(lif, lif->txqcqs[i]); 2030 if (err) 2031 goto err_out; 2032 2033 err = ionic_lif_rxq_init(lif, lif->rxqcqs[i]); 2034 if (err) { 2035 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 2036 goto err_out; 2037 } 2038 } 2039 2040 if (lif->netdev->features & NETIF_F_RXHASH) 2041 ionic_lif_rss_init(lif); 2042 2043 ionic_lif_rx_mode(lif); 2044 2045 return 0; 2046 2047 err_out: 2048 while (i--) { 2049 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 2050 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 2051 } 2052 2053 return err; 2054 } 2055 2056 static int ionic_txrx_enable(struct ionic_lif *lif) 2057 { 2058 int derr = 0; 2059 int i, err; 2060 2061 for (i = 0; i < lif->nxqs; i++) { 2062 if (!(lif->rxqcqs[i] && lif->txqcqs[i])) { 2063 dev_err(lif->ionic->dev, "%s: bad qcq %d\n", __func__, i); 2064 err = -ENXIO; 2065 goto err_out; 2066 } 2067 2068 ionic_rx_fill(&lif->rxqcqs[i]->q); 2069 err = ionic_qcq_enable(lif->rxqcqs[i]); 2070 if (err) 2071 goto err_out; 2072 2073 err = ionic_qcq_enable(lif->txqcqs[i]); 2074 if (err) { 2075 derr = ionic_qcq_disable(lif, lif->rxqcqs[i], err); 2076 goto err_out; 2077 } 2078 } 2079 2080 if (lif->hwstamp_rxq) { 2081 ionic_rx_fill(&lif->hwstamp_rxq->q); 2082 err = ionic_qcq_enable(lif->hwstamp_rxq); 2083 if (err) 2084 goto err_out_hwstamp_rx; 2085 } 2086 2087 if (lif->hwstamp_txq) { 2088 err = ionic_qcq_enable(lif->hwstamp_txq); 2089 if (err) 2090 goto err_out_hwstamp_tx; 2091 } 2092 2093 return 0; 2094 2095 err_out_hwstamp_tx: 2096 if (lif->hwstamp_rxq) 2097 derr = ionic_qcq_disable(lif, lif->hwstamp_rxq, derr); 2098 err_out_hwstamp_rx: 2099 i = lif->nxqs; 2100 err_out: 2101 while (i--) { 2102 derr = ionic_qcq_disable(lif, lif->txqcqs[i], derr); 2103 derr = ionic_qcq_disable(lif, lif->rxqcqs[i], derr); 2104 } 2105 2106 return err; 2107 } 2108 2109 static int ionic_start_queues(struct ionic_lif *lif) 2110 { 2111 int err; 2112 2113 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) 2114 return -EIO; 2115 2116 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2117 return -EBUSY; 2118 2119 if (test_and_set_bit(IONIC_LIF_F_UP, lif->state)) 2120 return 0; 2121 2122 err = ionic_txrx_enable(lif); 2123 if (err) { 2124 clear_bit(IONIC_LIF_F_UP, lif->state); 2125 return err; 2126 } 2127 netif_tx_wake_all_queues(lif->netdev); 2128 2129 return 0; 2130 } 2131 2132 static int ionic_open(struct net_device *netdev) 2133 { 2134 struct ionic_lif *lif = netdev_priv(netdev); 2135 int err; 2136 2137 /* If recovering from a broken state, clear the bit and we'll try again */ 2138 if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state)) 2139 netdev_info(netdev, "clearing broken state\n"); 2140 2141 mutex_lock(&lif->queue_lock); 2142 2143 err = ionic_txrx_alloc(lif); 2144 if (err) 2145 goto err_unlock; 2146 2147 err = ionic_txrx_init(lif); 2148 if (err) 2149 goto err_txrx_free; 2150 2151 err = netif_set_real_num_tx_queues(netdev, lif->nxqs); 2152 if (err) 2153 goto err_txrx_deinit; 2154 2155 err = netif_set_real_num_rx_queues(netdev, lif->nxqs); 2156 if (err) 2157 goto err_txrx_deinit; 2158 2159 /* don't start the queues until we have link */ 2160 if (netif_carrier_ok(netdev)) { 2161 err = ionic_start_queues(lif); 2162 if (err) 2163 goto err_txrx_deinit; 2164 } 2165 2166 /* If hardware timestamping is enabled, but the queues were freed by 2167 * ionic_stop, those need to be reallocated and initialized, too. 2168 */ 2169 ionic_lif_hwstamp_recreate_queues(lif); 2170 2171 mutex_unlock(&lif->queue_lock); 2172 2173 return 0; 2174 2175 err_txrx_deinit: 2176 ionic_txrx_deinit(lif); 2177 err_txrx_free: 2178 ionic_txrx_free(lif); 2179 err_unlock: 2180 mutex_unlock(&lif->queue_lock); 2181 return err; 2182 } 2183 2184 static void ionic_stop_queues(struct ionic_lif *lif) 2185 { 2186 if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state)) 2187 return; 2188 2189 netif_tx_disable(lif->netdev); 2190 ionic_txrx_disable(lif); 2191 } 2192 2193 static int ionic_stop(struct net_device *netdev) 2194 { 2195 struct ionic_lif *lif = netdev_priv(netdev); 2196 2197 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2198 return 0; 2199 2200 mutex_lock(&lif->queue_lock); 2201 ionic_stop_queues(lif); 2202 ionic_txrx_deinit(lif); 2203 ionic_txrx_free(lif); 2204 mutex_unlock(&lif->queue_lock); 2205 2206 return 0; 2207 } 2208 2209 static int ionic_eth_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 2210 { 2211 struct ionic_lif *lif = netdev_priv(netdev); 2212 2213 switch (cmd) { 2214 case SIOCSHWTSTAMP: 2215 return ionic_lif_hwstamp_set(lif, ifr); 2216 case SIOCGHWTSTAMP: 2217 return ionic_lif_hwstamp_get(lif, ifr); 2218 default: 2219 return -EOPNOTSUPP; 2220 } 2221 } 2222 2223 static int ionic_update_cached_vf_config(struct ionic *ionic, int vf) 2224 { 2225 struct ionic_vf_getattr_comp comp = { 0 }; 2226 int err; 2227 u8 attr; 2228 2229 attr = IONIC_VF_ATTR_VLAN; 2230 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp); 2231 if (err && comp.status != IONIC_RC_ENOSUPP) 2232 goto err_out; 2233 if (!err) 2234 ionic->vfs[vf].vlanid = comp.vlanid; 2235 2236 attr = IONIC_VF_ATTR_SPOOFCHK; 2237 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp); 2238 if (err && comp.status != IONIC_RC_ENOSUPP) 2239 goto err_out; 2240 if (!err) 2241 ionic->vfs[vf].spoofchk = comp.spoofchk; 2242 2243 attr = IONIC_VF_ATTR_LINKSTATE; 2244 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp); 2245 if (err && comp.status != IONIC_RC_ENOSUPP) 2246 goto err_out; 2247 if (!err) { 2248 switch (comp.linkstate) { 2249 case IONIC_VF_LINK_STATUS_UP: 2250 ionic->vfs[vf].linkstate = IFLA_VF_LINK_STATE_ENABLE; 2251 break; 2252 case IONIC_VF_LINK_STATUS_DOWN: 2253 ionic->vfs[vf].linkstate = IFLA_VF_LINK_STATE_DISABLE; 2254 break; 2255 case IONIC_VF_LINK_STATUS_AUTO: 2256 ionic->vfs[vf].linkstate = IFLA_VF_LINK_STATE_AUTO; 2257 break; 2258 default: 2259 dev_warn(ionic->dev, "Unexpected link state %u\n", comp.linkstate); 2260 break; 2261 } 2262 } 2263 2264 attr = IONIC_VF_ATTR_RATE; 2265 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp); 2266 if (err && comp.status != IONIC_RC_ENOSUPP) 2267 goto err_out; 2268 if (!err) 2269 ionic->vfs[vf].maxrate = comp.maxrate; 2270 2271 attr = IONIC_VF_ATTR_TRUST; 2272 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp); 2273 if (err && comp.status != IONIC_RC_ENOSUPP) 2274 goto err_out; 2275 if (!err) 2276 ionic->vfs[vf].trusted = comp.trust; 2277 2278 attr = IONIC_VF_ATTR_MAC; 2279 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp); 2280 if (err && comp.status != IONIC_RC_ENOSUPP) 2281 goto err_out; 2282 if (!err) 2283 ether_addr_copy(ionic->vfs[vf].macaddr, comp.macaddr); 2284 2285 err_out: 2286 if (err) 2287 dev_err(ionic->dev, "Failed to get %s for VF %d\n", 2288 ionic_vf_attr_to_str(attr), vf); 2289 2290 return err; 2291 } 2292 2293 static int ionic_get_vf_config(struct net_device *netdev, 2294 int vf, struct ifla_vf_info *ivf) 2295 { 2296 struct ionic_lif *lif = netdev_priv(netdev); 2297 struct ionic *ionic = lif->ionic; 2298 int ret = 0; 2299 2300 if (!netif_device_present(netdev)) 2301 return -EBUSY; 2302 2303 down_read(&ionic->vf_op_lock); 2304 2305 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2306 ret = -EINVAL; 2307 } else { 2308 ivf->vf = vf; 2309 ivf->qos = 0; 2310 2311 ret = ionic_update_cached_vf_config(ionic, vf); 2312 if (!ret) { 2313 ivf->vlan = le16_to_cpu(ionic->vfs[vf].vlanid); 2314 ivf->spoofchk = ionic->vfs[vf].spoofchk; 2315 ivf->linkstate = ionic->vfs[vf].linkstate; 2316 ivf->max_tx_rate = le32_to_cpu(ionic->vfs[vf].maxrate); 2317 ivf->trusted = ionic->vfs[vf].trusted; 2318 ether_addr_copy(ivf->mac, ionic->vfs[vf].macaddr); 2319 } 2320 } 2321 2322 up_read(&ionic->vf_op_lock); 2323 return ret; 2324 } 2325 2326 static int ionic_get_vf_stats(struct net_device *netdev, int vf, 2327 struct ifla_vf_stats *vf_stats) 2328 { 2329 struct ionic_lif *lif = netdev_priv(netdev); 2330 struct ionic *ionic = lif->ionic; 2331 struct ionic_lif_stats *vs; 2332 int ret = 0; 2333 2334 if (!netif_device_present(netdev)) 2335 return -EBUSY; 2336 2337 down_read(&ionic->vf_op_lock); 2338 2339 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2340 ret = -EINVAL; 2341 } else { 2342 memset(vf_stats, 0, sizeof(*vf_stats)); 2343 vs = &ionic->vfs[vf].stats; 2344 2345 vf_stats->rx_packets = le64_to_cpu(vs->rx_ucast_packets); 2346 vf_stats->tx_packets = le64_to_cpu(vs->tx_ucast_packets); 2347 vf_stats->rx_bytes = le64_to_cpu(vs->rx_ucast_bytes); 2348 vf_stats->tx_bytes = le64_to_cpu(vs->tx_ucast_bytes); 2349 vf_stats->broadcast = le64_to_cpu(vs->rx_bcast_packets); 2350 vf_stats->multicast = le64_to_cpu(vs->rx_mcast_packets); 2351 vf_stats->rx_dropped = le64_to_cpu(vs->rx_ucast_drop_packets) + 2352 le64_to_cpu(vs->rx_mcast_drop_packets) + 2353 le64_to_cpu(vs->rx_bcast_drop_packets); 2354 vf_stats->tx_dropped = le64_to_cpu(vs->tx_ucast_drop_packets) + 2355 le64_to_cpu(vs->tx_mcast_drop_packets) + 2356 le64_to_cpu(vs->tx_bcast_drop_packets); 2357 } 2358 2359 up_read(&ionic->vf_op_lock); 2360 return ret; 2361 } 2362 2363 static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2364 { 2365 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_MAC }; 2366 struct ionic_lif *lif = netdev_priv(netdev); 2367 struct ionic *ionic = lif->ionic; 2368 int ret; 2369 2370 if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac))) 2371 return -EINVAL; 2372 2373 if (!netif_device_present(netdev)) 2374 return -EBUSY; 2375 2376 down_write(&ionic->vf_op_lock); 2377 2378 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2379 ret = -EINVAL; 2380 } else { 2381 ether_addr_copy(vfc.macaddr, mac); 2382 dev_dbg(ionic->dev, "%s: vf %d macaddr %pM\n", 2383 __func__, vf, vfc.macaddr); 2384 2385 ret = ionic_set_vf_config(ionic, vf, &vfc); 2386 if (!ret) 2387 ether_addr_copy(ionic->vfs[vf].macaddr, mac); 2388 } 2389 2390 up_write(&ionic->vf_op_lock); 2391 return ret; 2392 } 2393 2394 static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 2395 u8 qos, __be16 proto) 2396 { 2397 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_VLAN }; 2398 struct ionic_lif *lif = netdev_priv(netdev); 2399 struct ionic *ionic = lif->ionic; 2400 int ret; 2401 2402 /* until someday when we support qos */ 2403 if (qos) 2404 return -EINVAL; 2405 2406 if (vlan > 4095) 2407 return -EINVAL; 2408 2409 if (proto != htons(ETH_P_8021Q)) 2410 return -EPROTONOSUPPORT; 2411 2412 if (!netif_device_present(netdev)) 2413 return -EBUSY; 2414 2415 down_write(&ionic->vf_op_lock); 2416 2417 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2418 ret = -EINVAL; 2419 } else { 2420 vfc.vlanid = cpu_to_le16(vlan); 2421 dev_dbg(ionic->dev, "%s: vf %d vlan %d\n", 2422 __func__, vf, le16_to_cpu(vfc.vlanid)); 2423 2424 ret = ionic_set_vf_config(ionic, vf, &vfc); 2425 if (!ret) 2426 ionic->vfs[vf].vlanid = cpu_to_le16(vlan); 2427 } 2428 2429 up_write(&ionic->vf_op_lock); 2430 return ret; 2431 } 2432 2433 static int ionic_set_vf_rate(struct net_device *netdev, int vf, 2434 int tx_min, int tx_max) 2435 { 2436 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_RATE }; 2437 struct ionic_lif *lif = netdev_priv(netdev); 2438 struct ionic *ionic = lif->ionic; 2439 int ret; 2440 2441 /* setting the min just seems silly */ 2442 if (tx_min) 2443 return -EINVAL; 2444 2445 if (!netif_device_present(netdev)) 2446 return -EBUSY; 2447 2448 down_write(&ionic->vf_op_lock); 2449 2450 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2451 ret = -EINVAL; 2452 } else { 2453 vfc.maxrate = cpu_to_le32(tx_max); 2454 dev_dbg(ionic->dev, "%s: vf %d maxrate %d\n", 2455 __func__, vf, le32_to_cpu(vfc.maxrate)); 2456 2457 ret = ionic_set_vf_config(ionic, vf, &vfc); 2458 if (!ret) 2459 lif->ionic->vfs[vf].maxrate = cpu_to_le32(tx_max); 2460 } 2461 2462 up_write(&ionic->vf_op_lock); 2463 return ret; 2464 } 2465 2466 static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set) 2467 { 2468 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_SPOOFCHK }; 2469 struct ionic_lif *lif = netdev_priv(netdev); 2470 struct ionic *ionic = lif->ionic; 2471 int ret; 2472 2473 if (!netif_device_present(netdev)) 2474 return -EBUSY; 2475 2476 down_write(&ionic->vf_op_lock); 2477 2478 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2479 ret = -EINVAL; 2480 } else { 2481 vfc.spoofchk = set; 2482 dev_dbg(ionic->dev, "%s: vf %d spoof %d\n", 2483 __func__, vf, vfc.spoofchk); 2484 2485 ret = ionic_set_vf_config(ionic, vf, &vfc); 2486 if (!ret) 2487 ionic->vfs[vf].spoofchk = set; 2488 } 2489 2490 up_write(&ionic->vf_op_lock); 2491 return ret; 2492 } 2493 2494 static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set) 2495 { 2496 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_TRUST }; 2497 struct ionic_lif *lif = netdev_priv(netdev); 2498 struct ionic *ionic = lif->ionic; 2499 int ret; 2500 2501 if (!netif_device_present(netdev)) 2502 return -EBUSY; 2503 2504 down_write(&ionic->vf_op_lock); 2505 2506 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2507 ret = -EINVAL; 2508 } else { 2509 vfc.trust = set; 2510 dev_dbg(ionic->dev, "%s: vf %d trust %d\n", 2511 __func__, vf, vfc.trust); 2512 2513 ret = ionic_set_vf_config(ionic, vf, &vfc); 2514 if (!ret) 2515 ionic->vfs[vf].trusted = set; 2516 } 2517 2518 up_write(&ionic->vf_op_lock); 2519 return ret; 2520 } 2521 2522 static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set) 2523 { 2524 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_LINKSTATE }; 2525 struct ionic_lif *lif = netdev_priv(netdev); 2526 struct ionic *ionic = lif->ionic; 2527 u8 vfls; 2528 int ret; 2529 2530 switch (set) { 2531 case IFLA_VF_LINK_STATE_ENABLE: 2532 vfls = IONIC_VF_LINK_STATUS_UP; 2533 break; 2534 case IFLA_VF_LINK_STATE_DISABLE: 2535 vfls = IONIC_VF_LINK_STATUS_DOWN; 2536 break; 2537 case IFLA_VF_LINK_STATE_AUTO: 2538 vfls = IONIC_VF_LINK_STATUS_AUTO; 2539 break; 2540 default: 2541 return -EINVAL; 2542 } 2543 2544 if (!netif_device_present(netdev)) 2545 return -EBUSY; 2546 2547 down_write(&ionic->vf_op_lock); 2548 2549 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2550 ret = -EINVAL; 2551 } else { 2552 vfc.linkstate = vfls; 2553 dev_dbg(ionic->dev, "%s: vf %d linkstate %d\n", 2554 __func__, vf, vfc.linkstate); 2555 2556 ret = ionic_set_vf_config(ionic, vf, &vfc); 2557 if (!ret) 2558 ionic->vfs[vf].linkstate = set; 2559 } 2560 2561 up_write(&ionic->vf_op_lock); 2562 return ret; 2563 } 2564 2565 static const struct net_device_ops ionic_netdev_ops = { 2566 .ndo_open = ionic_open, 2567 .ndo_stop = ionic_stop, 2568 .ndo_eth_ioctl = ionic_eth_ioctl, 2569 .ndo_start_xmit = ionic_start_xmit, 2570 .ndo_get_stats64 = ionic_get_stats64, 2571 .ndo_set_rx_mode = ionic_ndo_set_rx_mode, 2572 .ndo_set_features = ionic_set_features, 2573 .ndo_set_mac_address = ionic_set_mac_address, 2574 .ndo_validate_addr = eth_validate_addr, 2575 .ndo_tx_timeout = ionic_tx_timeout, 2576 .ndo_change_mtu = ionic_change_mtu, 2577 .ndo_vlan_rx_add_vid = ionic_vlan_rx_add_vid, 2578 .ndo_vlan_rx_kill_vid = ionic_vlan_rx_kill_vid, 2579 .ndo_set_vf_vlan = ionic_set_vf_vlan, 2580 .ndo_set_vf_trust = ionic_set_vf_trust, 2581 .ndo_set_vf_mac = ionic_set_vf_mac, 2582 .ndo_set_vf_rate = ionic_set_vf_rate, 2583 .ndo_set_vf_spoofchk = ionic_set_vf_spoofchk, 2584 .ndo_get_vf_config = ionic_get_vf_config, 2585 .ndo_set_vf_link_state = ionic_set_vf_link_state, 2586 .ndo_get_vf_stats = ionic_get_vf_stats, 2587 }; 2588 2589 static void ionic_swap_queues(struct ionic_qcq *a, struct ionic_qcq *b) 2590 { 2591 /* only swapping the queues, not the napi, flags, or other stuff */ 2592 swap(a->q.features, b->q.features); 2593 swap(a->q.num_descs, b->q.num_descs); 2594 swap(a->q.desc_size, b->q.desc_size); 2595 swap(a->q.base, b->q.base); 2596 swap(a->q.base_pa, b->q.base_pa); 2597 swap(a->q.info, b->q.info); 2598 swap(a->q_base, b->q_base); 2599 swap(a->q_base_pa, b->q_base_pa); 2600 swap(a->q_size, b->q_size); 2601 2602 swap(a->q.sg_desc_size, b->q.sg_desc_size); 2603 swap(a->q.sg_base, b->q.sg_base); 2604 swap(a->q.sg_base_pa, b->q.sg_base_pa); 2605 swap(a->sg_base, b->sg_base); 2606 swap(a->sg_base_pa, b->sg_base_pa); 2607 swap(a->sg_size, b->sg_size); 2608 2609 swap(a->cq.num_descs, b->cq.num_descs); 2610 swap(a->cq.desc_size, b->cq.desc_size); 2611 swap(a->cq.base, b->cq.base); 2612 swap(a->cq.base_pa, b->cq.base_pa); 2613 swap(a->cq.info, b->cq.info); 2614 swap(a->cq_base, b->cq_base); 2615 swap(a->cq_base_pa, b->cq_base_pa); 2616 swap(a->cq_size, b->cq_size); 2617 2618 ionic_debugfs_del_qcq(a); 2619 ionic_debugfs_add_qcq(a->q.lif, a); 2620 } 2621 2622 int ionic_reconfigure_queues(struct ionic_lif *lif, 2623 struct ionic_queue_params *qparam) 2624 { 2625 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz; 2626 struct ionic_qcq **tx_qcqs = NULL; 2627 struct ionic_qcq **rx_qcqs = NULL; 2628 unsigned int flags, i; 2629 int err = 0; 2630 2631 /* allocate temporary qcq arrays to hold new queue structs */ 2632 if (qparam->nxqs != lif->nxqs || qparam->ntxq_descs != lif->ntxq_descs) { 2633 tx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->ntxqs_per_lif, 2634 sizeof(struct ionic_qcq *), GFP_KERNEL); 2635 if (!tx_qcqs) { 2636 err = -ENOMEM; 2637 goto err_out; 2638 } 2639 } 2640 if (qparam->nxqs != lif->nxqs || 2641 qparam->nrxq_descs != lif->nrxq_descs || 2642 qparam->rxq_features != lif->rxq_features) { 2643 rx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->nrxqs_per_lif, 2644 sizeof(struct ionic_qcq *), GFP_KERNEL); 2645 if (!rx_qcqs) { 2646 err = -ENOMEM; 2647 goto err_out; 2648 } 2649 } 2650 2651 /* allocate new desc_info and rings, but leave the interrupt setup 2652 * until later so as to not mess with the still-running queues 2653 */ 2654 if (tx_qcqs) { 2655 num_desc = qparam->ntxq_descs; 2656 desc_sz = sizeof(struct ionic_txq_desc); 2657 comp_sz = sizeof(struct ionic_txq_comp); 2658 2659 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 2660 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 2661 sizeof(struct ionic_txq_sg_desc_v1)) 2662 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 2663 else 2664 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 2665 2666 for (i = 0; i < qparam->nxqs; i++) { 2667 flags = lif->txqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2668 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 2669 num_desc, desc_sz, comp_sz, sg_desc_sz, 2670 lif->kern_pid, &tx_qcqs[i]); 2671 if (err) 2672 goto err_out; 2673 } 2674 } 2675 2676 if (rx_qcqs) { 2677 num_desc = qparam->nrxq_descs; 2678 desc_sz = sizeof(struct ionic_rxq_desc); 2679 comp_sz = sizeof(struct ionic_rxq_comp); 2680 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 2681 2682 if (qparam->rxq_features & IONIC_Q_F_2X_CQ_DESC) 2683 comp_sz *= 2; 2684 2685 for (i = 0; i < qparam->nxqs; i++) { 2686 flags = lif->rxqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2687 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 2688 num_desc, desc_sz, comp_sz, sg_desc_sz, 2689 lif->kern_pid, &rx_qcqs[i]); 2690 if (err) 2691 goto err_out; 2692 2693 rx_qcqs[i]->q.features = qparam->rxq_features; 2694 } 2695 } 2696 2697 /* stop and clean the queues */ 2698 ionic_stop_queues_reconfig(lif); 2699 2700 if (qparam->nxqs != lif->nxqs) { 2701 err = netif_set_real_num_tx_queues(lif->netdev, qparam->nxqs); 2702 if (err) 2703 goto err_out_reinit_unlock; 2704 err = netif_set_real_num_rx_queues(lif->netdev, qparam->nxqs); 2705 if (err) { 2706 netif_set_real_num_tx_queues(lif->netdev, lif->nxqs); 2707 goto err_out_reinit_unlock; 2708 } 2709 } 2710 2711 /* swap new desc_info and rings, keeping existing interrupt config */ 2712 if (tx_qcqs) { 2713 lif->ntxq_descs = qparam->ntxq_descs; 2714 for (i = 0; i < qparam->nxqs; i++) 2715 ionic_swap_queues(lif->txqcqs[i], tx_qcqs[i]); 2716 } 2717 2718 if (rx_qcqs) { 2719 lif->nrxq_descs = qparam->nrxq_descs; 2720 for (i = 0; i < qparam->nxqs; i++) 2721 ionic_swap_queues(lif->rxqcqs[i], rx_qcqs[i]); 2722 } 2723 2724 /* if we need to change the interrupt layout, this is the time */ 2725 if (qparam->intr_split != test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) || 2726 qparam->nxqs != lif->nxqs) { 2727 if (qparam->intr_split) { 2728 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 2729 } else { 2730 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 2731 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 2732 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 2733 } 2734 2735 /* clear existing interrupt assignments */ 2736 for (i = 0; i < lif->ionic->ntxqs_per_lif; i++) { 2737 ionic_qcq_intr_free(lif, lif->txqcqs[i]); 2738 ionic_qcq_intr_free(lif, lif->rxqcqs[i]); 2739 } 2740 2741 /* re-assign the interrupts */ 2742 for (i = 0; i < qparam->nxqs; i++) { 2743 lif->rxqcqs[i]->flags |= IONIC_QCQ_F_INTR; 2744 err = ionic_alloc_qcq_interrupt(lif, lif->rxqcqs[i]); 2745 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2746 lif->rxqcqs[i]->intr.index, 2747 lif->rx_coalesce_hw); 2748 2749 if (qparam->intr_split) { 2750 lif->txqcqs[i]->flags |= IONIC_QCQ_F_INTR; 2751 err = ionic_alloc_qcq_interrupt(lif, lif->txqcqs[i]); 2752 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2753 lif->txqcqs[i]->intr.index, 2754 lif->tx_coalesce_hw); 2755 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 2756 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 2757 } else { 2758 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2759 ionic_link_qcq_interrupts(lif->rxqcqs[i], lif->txqcqs[i]); 2760 } 2761 } 2762 } 2763 2764 /* now we can rework the debugfs mappings */ 2765 if (tx_qcqs) { 2766 for (i = 0; i < qparam->nxqs; i++) { 2767 ionic_debugfs_del_qcq(lif->txqcqs[i]); 2768 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 2769 } 2770 } 2771 2772 if (rx_qcqs) { 2773 for (i = 0; i < qparam->nxqs; i++) { 2774 ionic_debugfs_del_qcq(lif->rxqcqs[i]); 2775 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 2776 } 2777 } 2778 2779 swap(lif->nxqs, qparam->nxqs); 2780 swap(lif->rxq_features, qparam->rxq_features); 2781 2782 err_out_reinit_unlock: 2783 /* re-init the queues, but don't lose an error code */ 2784 if (err) 2785 ionic_start_queues_reconfig(lif); 2786 else 2787 err = ionic_start_queues_reconfig(lif); 2788 2789 err_out: 2790 /* free old allocs without cleaning intr */ 2791 for (i = 0; i < qparam->nxqs; i++) { 2792 if (tx_qcqs && tx_qcqs[i]) { 2793 tx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2794 ionic_qcq_free(lif, tx_qcqs[i]); 2795 devm_kfree(lif->ionic->dev, tx_qcqs[i]); 2796 tx_qcqs[i] = NULL; 2797 } 2798 if (rx_qcqs && rx_qcqs[i]) { 2799 rx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2800 ionic_qcq_free(lif, rx_qcqs[i]); 2801 devm_kfree(lif->ionic->dev, rx_qcqs[i]); 2802 rx_qcqs[i] = NULL; 2803 } 2804 } 2805 2806 /* free q array */ 2807 if (rx_qcqs) { 2808 devm_kfree(lif->ionic->dev, rx_qcqs); 2809 rx_qcqs = NULL; 2810 } 2811 if (tx_qcqs) { 2812 devm_kfree(lif->ionic->dev, tx_qcqs); 2813 tx_qcqs = NULL; 2814 } 2815 2816 /* clean the unused dma and info allocations when new set is smaller 2817 * than the full array, but leave the qcq shells in place 2818 */ 2819 for (i = lif->nxqs; i < lif->ionic->ntxqs_per_lif; i++) { 2820 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2821 ionic_qcq_free(lif, lif->txqcqs[i]); 2822 2823 lif->rxqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2824 ionic_qcq_free(lif, lif->rxqcqs[i]); 2825 } 2826 2827 if (err) 2828 netdev_info(lif->netdev, "%s: failed %d\n", __func__, err); 2829 2830 return err; 2831 } 2832 2833 int ionic_lif_alloc(struct ionic *ionic) 2834 { 2835 struct device *dev = ionic->dev; 2836 union ionic_lif_identity *lid; 2837 struct net_device *netdev; 2838 struct ionic_lif *lif; 2839 int tbl_sz; 2840 int err; 2841 2842 lid = kzalloc(sizeof(*lid), GFP_KERNEL); 2843 if (!lid) 2844 return -ENOMEM; 2845 2846 netdev = alloc_etherdev_mqs(sizeof(*lif), 2847 ionic->ntxqs_per_lif, ionic->ntxqs_per_lif); 2848 if (!netdev) { 2849 dev_err(dev, "Cannot allocate netdev, aborting\n"); 2850 err = -ENOMEM; 2851 goto err_out_free_lid; 2852 } 2853 2854 SET_NETDEV_DEV(netdev, dev); 2855 2856 lif = netdev_priv(netdev); 2857 lif->netdev = netdev; 2858 ionic->lif = lif; 2859 netdev->netdev_ops = &ionic_netdev_ops; 2860 ionic_ethtool_set_ops(netdev); 2861 2862 netdev->watchdog_timeo = 2 * HZ; 2863 netif_carrier_off(netdev); 2864 2865 lif->identity = lid; 2866 lif->lif_type = IONIC_LIF_TYPE_CLASSIC; 2867 err = ionic_lif_identify(ionic, lif->lif_type, lif->identity); 2868 if (err) { 2869 dev_err(ionic->dev, "Cannot identify type %d: %d\n", 2870 lif->lif_type, err); 2871 goto err_out_free_netdev; 2872 } 2873 lif->netdev->min_mtu = max_t(unsigned int, ETH_MIN_MTU, 2874 le32_to_cpu(lif->identity->eth.min_frame_size)); 2875 lif->netdev->max_mtu = 2876 le32_to_cpu(lif->identity->eth.max_frame_size) - ETH_HLEN - VLAN_HLEN; 2877 2878 lif->neqs = ionic->neqs_per_lif; 2879 lif->nxqs = ionic->ntxqs_per_lif; 2880 2881 lif->ionic = ionic; 2882 lif->index = 0; 2883 2884 if (is_kdump_kernel()) { 2885 lif->ntxq_descs = IONIC_MIN_TXRX_DESC; 2886 lif->nrxq_descs = IONIC_MIN_TXRX_DESC; 2887 } else { 2888 lif->ntxq_descs = IONIC_DEF_TXRX_DESC; 2889 lif->nrxq_descs = IONIC_DEF_TXRX_DESC; 2890 } 2891 2892 /* Convert the default coalesce value to actual hw resolution */ 2893 lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT; 2894 lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic, 2895 lif->rx_coalesce_usecs); 2896 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 2897 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 2898 set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 2899 set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 2900 2901 snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index); 2902 2903 mutex_init(&lif->queue_lock); 2904 mutex_init(&lif->config_lock); 2905 2906 spin_lock_init(&lif->adminq_lock); 2907 2908 spin_lock_init(&lif->deferred.lock); 2909 INIT_LIST_HEAD(&lif->deferred.list); 2910 INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work); 2911 2912 /* allocate lif info */ 2913 lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE); 2914 lif->info = dma_alloc_coherent(dev, lif->info_sz, 2915 &lif->info_pa, GFP_KERNEL); 2916 if (!lif->info) { 2917 dev_err(dev, "Failed to allocate lif info, aborting\n"); 2918 err = -ENOMEM; 2919 goto err_out_free_mutex; 2920 } 2921 2922 ionic_debugfs_add_lif(lif); 2923 2924 /* allocate control queues and txrx queue arrays */ 2925 ionic_lif_queue_identify(lif); 2926 err = ionic_qcqs_alloc(lif); 2927 if (err) 2928 goto err_out_free_lif_info; 2929 2930 /* allocate rss indirection table */ 2931 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 2932 lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz; 2933 lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz, 2934 &lif->rss_ind_tbl_pa, 2935 GFP_KERNEL); 2936 2937 if (!lif->rss_ind_tbl) { 2938 err = -ENOMEM; 2939 dev_err(dev, "Failed to allocate rss indirection table, aborting\n"); 2940 goto err_out_free_qcqs; 2941 } 2942 netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE); 2943 2944 ionic_lif_alloc_phc(lif); 2945 2946 return 0; 2947 2948 err_out_free_qcqs: 2949 ionic_qcqs_free(lif); 2950 err_out_free_lif_info: 2951 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 2952 lif->info = NULL; 2953 lif->info_pa = 0; 2954 err_out_free_mutex: 2955 mutex_destroy(&lif->config_lock); 2956 mutex_destroy(&lif->queue_lock); 2957 err_out_free_netdev: 2958 free_netdev(lif->netdev); 2959 lif = NULL; 2960 err_out_free_lid: 2961 kfree(lid); 2962 2963 return err; 2964 } 2965 2966 static void ionic_lif_reset(struct ionic_lif *lif) 2967 { 2968 struct ionic_dev *idev = &lif->ionic->idev; 2969 2970 mutex_lock(&lif->ionic->dev_cmd_lock); 2971 ionic_dev_cmd_lif_reset(idev, lif->index); 2972 ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2973 mutex_unlock(&lif->ionic->dev_cmd_lock); 2974 } 2975 2976 static void ionic_lif_handle_fw_down(struct ionic_lif *lif) 2977 { 2978 struct ionic *ionic = lif->ionic; 2979 2980 if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2981 return; 2982 2983 dev_info(ionic->dev, "FW Down: Stopping LIFs\n"); 2984 2985 netif_device_detach(lif->netdev); 2986 2987 mutex_lock(&lif->queue_lock); 2988 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 2989 dev_info(ionic->dev, "Surprise FW stop, stopping queues\n"); 2990 ionic_stop_queues(lif); 2991 } 2992 2993 if (netif_running(lif->netdev)) { 2994 ionic_txrx_deinit(lif); 2995 ionic_txrx_free(lif); 2996 } 2997 ionic_lif_deinit(lif); 2998 ionic_reset(ionic); 2999 ionic_qcqs_free(lif); 3000 3001 mutex_unlock(&lif->queue_lock); 3002 3003 clear_bit(IONIC_LIF_F_FW_STOPPING, lif->state); 3004 dev_info(ionic->dev, "FW Down: LIFs stopped\n"); 3005 } 3006 3007 static void ionic_lif_handle_fw_up(struct ionic_lif *lif) 3008 { 3009 struct ionic *ionic = lif->ionic; 3010 int err; 3011 3012 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 3013 return; 3014 3015 dev_info(ionic->dev, "FW Up: restarting LIFs\n"); 3016 3017 ionic_init_devinfo(ionic); 3018 err = ionic_identify(ionic); 3019 if (err) 3020 goto err_out; 3021 err = ionic_port_identify(ionic); 3022 if (err) 3023 goto err_out; 3024 err = ionic_port_init(ionic); 3025 if (err) 3026 goto err_out; 3027 3028 mutex_lock(&lif->queue_lock); 3029 3030 if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state)) 3031 dev_info(ionic->dev, "FW Up: clearing broken state\n"); 3032 3033 err = ionic_qcqs_alloc(lif); 3034 if (err) 3035 goto err_unlock; 3036 3037 err = ionic_lif_init(lif); 3038 if (err) 3039 goto err_qcqs_free; 3040 3041 if (lif->registered) 3042 ionic_lif_set_netdev_info(lif); 3043 3044 ionic_rx_filter_replay(lif); 3045 3046 if (netif_running(lif->netdev)) { 3047 err = ionic_txrx_alloc(lif); 3048 if (err) 3049 goto err_lifs_deinit; 3050 3051 err = ionic_txrx_init(lif); 3052 if (err) 3053 goto err_txrx_free; 3054 } 3055 3056 mutex_unlock(&lif->queue_lock); 3057 3058 clear_bit(IONIC_LIF_F_FW_RESET, lif->state); 3059 ionic_link_status_check_request(lif, CAN_SLEEP); 3060 netif_device_attach(lif->netdev); 3061 dev_info(ionic->dev, "FW Up: LIFs restarted\n"); 3062 3063 /* restore the hardware timestamping queues */ 3064 ionic_lif_hwstamp_replay(lif); 3065 3066 return; 3067 3068 err_txrx_free: 3069 ionic_txrx_free(lif); 3070 err_lifs_deinit: 3071 ionic_lif_deinit(lif); 3072 err_qcqs_free: 3073 ionic_qcqs_free(lif); 3074 err_unlock: 3075 mutex_unlock(&lif->queue_lock); 3076 err_out: 3077 dev_err(ionic->dev, "FW Up: LIFs restart failed - err %d\n", err); 3078 } 3079 3080 void ionic_lif_free(struct ionic_lif *lif) 3081 { 3082 struct device *dev = lif->ionic->dev; 3083 3084 ionic_lif_free_phc(lif); 3085 3086 /* free rss indirection table */ 3087 dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl, 3088 lif->rss_ind_tbl_pa); 3089 lif->rss_ind_tbl = NULL; 3090 lif->rss_ind_tbl_pa = 0; 3091 3092 /* free queues */ 3093 ionic_qcqs_free(lif); 3094 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 3095 ionic_lif_reset(lif); 3096 3097 /* free lif info */ 3098 kfree(lif->identity); 3099 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 3100 lif->info = NULL; 3101 lif->info_pa = 0; 3102 3103 /* unmap doorbell page */ 3104 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 3105 lif->kern_dbpage = NULL; 3106 3107 mutex_destroy(&lif->config_lock); 3108 mutex_destroy(&lif->queue_lock); 3109 3110 /* free netdev & lif */ 3111 ionic_debugfs_del_lif(lif); 3112 free_netdev(lif->netdev); 3113 } 3114 3115 void ionic_lif_deinit(struct ionic_lif *lif) 3116 { 3117 if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state)) 3118 return; 3119 3120 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 3121 cancel_work_sync(&lif->deferred.work); 3122 cancel_work_sync(&lif->tx_timeout_work); 3123 ionic_rx_filters_deinit(lif); 3124 if (lif->netdev->features & NETIF_F_RXHASH) 3125 ionic_lif_rss_deinit(lif); 3126 } 3127 3128 napi_disable(&lif->adminqcq->napi); 3129 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 3130 ionic_lif_qcq_deinit(lif, lif->adminqcq); 3131 3132 ionic_lif_reset(lif); 3133 } 3134 3135 static int ionic_lif_adminq_init(struct ionic_lif *lif) 3136 { 3137 struct device *dev = lif->ionic->dev; 3138 struct ionic_q_init_comp comp; 3139 struct ionic_dev *idev; 3140 struct ionic_qcq *qcq; 3141 struct ionic_queue *q; 3142 int err; 3143 3144 idev = &lif->ionic->idev; 3145 qcq = lif->adminqcq; 3146 q = &qcq->q; 3147 3148 mutex_lock(&lif->ionic->dev_cmd_lock); 3149 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index); 3150 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 3151 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 3152 mutex_unlock(&lif->ionic->dev_cmd_lock); 3153 if (err) { 3154 netdev_err(lif->netdev, "adminq init failed %d\n", err); 3155 return err; 3156 } 3157 3158 q->hw_type = comp.hw_type; 3159 q->hw_index = le32_to_cpu(comp.hw_index); 3160 q->dbval = IONIC_DBELL_QID(q->hw_index); 3161 3162 dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type); 3163 dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index); 3164 3165 netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi); 3166 3167 napi_enable(&qcq->napi); 3168 3169 if (qcq->flags & IONIC_QCQ_F_INTR) 3170 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 3171 IONIC_INTR_MASK_CLEAR); 3172 3173 qcq->flags |= IONIC_QCQ_F_INITED; 3174 3175 return 0; 3176 } 3177 3178 static int ionic_lif_notifyq_init(struct ionic_lif *lif) 3179 { 3180 struct ionic_qcq *qcq = lif->notifyqcq; 3181 struct device *dev = lif->ionic->dev; 3182 struct ionic_queue *q = &qcq->q; 3183 int err; 3184 3185 struct ionic_admin_ctx ctx = { 3186 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3187 .cmd.q_init = { 3188 .opcode = IONIC_CMD_Q_INIT, 3189 .lif_index = cpu_to_le16(lif->index), 3190 .type = q->type, 3191 .ver = lif->qtype_info[q->type].version, 3192 .index = cpu_to_le32(q->index), 3193 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 3194 IONIC_QINIT_F_ENA), 3195 .intr_index = cpu_to_le16(lif->adminqcq->intr.index), 3196 .pid = cpu_to_le16(q->pid), 3197 .ring_size = ilog2(q->num_descs), 3198 .ring_base = cpu_to_le64(q->base_pa), 3199 } 3200 }; 3201 3202 dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid); 3203 dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index); 3204 dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 3205 dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 3206 3207 err = ionic_adminq_post_wait(lif, &ctx); 3208 if (err) 3209 return err; 3210 3211 lif->last_eid = 0; 3212 q->hw_type = ctx.comp.q_init.hw_type; 3213 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 3214 q->dbval = IONIC_DBELL_QID(q->hw_index); 3215 3216 dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type); 3217 dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index); 3218 3219 /* preset the callback info */ 3220 q->info[0].cb_arg = lif; 3221 3222 qcq->flags |= IONIC_QCQ_F_INITED; 3223 3224 return 0; 3225 } 3226 3227 static int ionic_station_set(struct ionic_lif *lif) 3228 { 3229 struct net_device *netdev = lif->netdev; 3230 struct ionic_admin_ctx ctx = { 3231 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3232 .cmd.lif_getattr = { 3233 .opcode = IONIC_CMD_LIF_GETATTR, 3234 .index = cpu_to_le16(lif->index), 3235 .attr = IONIC_LIF_ATTR_MAC, 3236 }, 3237 }; 3238 u8 mac_address[ETH_ALEN]; 3239 struct sockaddr addr; 3240 int err; 3241 3242 err = ionic_adminq_post_wait(lif, &ctx); 3243 if (err) 3244 return err; 3245 netdev_dbg(lif->netdev, "found initial MAC addr %pM\n", 3246 ctx.comp.lif_getattr.mac); 3247 ether_addr_copy(mac_address, ctx.comp.lif_getattr.mac); 3248 3249 if (is_zero_ether_addr(mac_address)) { 3250 eth_hw_addr_random(netdev); 3251 netdev_dbg(netdev, "Random Mac generated: %pM\n", netdev->dev_addr); 3252 ether_addr_copy(mac_address, netdev->dev_addr); 3253 3254 err = ionic_program_mac(lif, mac_address); 3255 if (err < 0) 3256 return err; 3257 3258 if (err > 0) { 3259 netdev_dbg(netdev, "%s:SET/GET ATTR Mac are not same-due to old FW running\n", 3260 __func__); 3261 return 0; 3262 } 3263 } 3264 3265 if (!is_zero_ether_addr(netdev->dev_addr)) { 3266 /* If the netdev mac is non-zero and doesn't match the default 3267 * device address, it was set by something earlier and we're 3268 * likely here again after a fw-upgrade reset. We need to be 3269 * sure the netdev mac is in our filter list. 3270 */ 3271 if (!ether_addr_equal(mac_address, netdev->dev_addr)) 3272 ionic_lif_addr_add(lif, netdev->dev_addr); 3273 } else { 3274 /* Update the netdev mac with the device's mac */ 3275 ether_addr_copy(addr.sa_data, mac_address); 3276 addr.sa_family = AF_INET; 3277 err = eth_prepare_mac_addr_change(netdev, &addr); 3278 if (err) { 3279 netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n", 3280 addr.sa_data, err); 3281 return 0; 3282 } 3283 3284 eth_commit_mac_addr_change(netdev, &addr); 3285 } 3286 3287 netdev_dbg(lif->netdev, "adding station MAC addr %pM\n", 3288 netdev->dev_addr); 3289 ionic_lif_addr_add(lif, netdev->dev_addr); 3290 3291 return 0; 3292 } 3293 3294 int ionic_lif_init(struct ionic_lif *lif) 3295 { 3296 struct ionic_dev *idev = &lif->ionic->idev; 3297 struct device *dev = lif->ionic->dev; 3298 struct ionic_lif_init_comp comp; 3299 int dbpage_num; 3300 int err; 3301 3302 mutex_lock(&lif->ionic->dev_cmd_lock); 3303 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa); 3304 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 3305 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 3306 mutex_unlock(&lif->ionic->dev_cmd_lock); 3307 if (err) 3308 return err; 3309 3310 lif->hw_index = le16_to_cpu(comp.hw_index); 3311 3312 /* now that we have the hw_index we can figure out our doorbell page */ 3313 lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif); 3314 if (!lif->dbid_count) { 3315 dev_err(dev, "No doorbell pages, aborting\n"); 3316 return -EINVAL; 3317 } 3318 3319 lif->kern_pid = 0; 3320 dbpage_num = ionic_db_page_num(lif, lif->kern_pid); 3321 lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num); 3322 if (!lif->kern_dbpage) { 3323 dev_err(dev, "Cannot map dbpage, aborting\n"); 3324 return -ENOMEM; 3325 } 3326 3327 err = ionic_lif_adminq_init(lif); 3328 if (err) 3329 goto err_out_adminq_deinit; 3330 3331 if (lif->ionic->nnqs_per_lif) { 3332 err = ionic_lif_notifyq_init(lif); 3333 if (err) 3334 goto err_out_notifyq_deinit; 3335 } 3336 3337 err = ionic_init_nic_features(lif); 3338 if (err) 3339 goto err_out_notifyq_deinit; 3340 3341 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 3342 err = ionic_rx_filters_init(lif); 3343 if (err) 3344 goto err_out_notifyq_deinit; 3345 } 3346 3347 err = ionic_station_set(lif); 3348 if (err) 3349 goto err_out_notifyq_deinit; 3350 3351 lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT; 3352 3353 set_bit(IONIC_LIF_F_INITED, lif->state); 3354 3355 INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work); 3356 3357 return 0; 3358 3359 err_out_notifyq_deinit: 3360 napi_disable(&lif->adminqcq->napi); 3361 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 3362 err_out_adminq_deinit: 3363 ionic_lif_qcq_deinit(lif, lif->adminqcq); 3364 ionic_lif_reset(lif); 3365 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 3366 lif->kern_dbpage = NULL; 3367 3368 return err; 3369 } 3370 3371 static void ionic_lif_notify_work(struct work_struct *ws) 3372 { 3373 } 3374 3375 static void ionic_lif_set_netdev_info(struct ionic_lif *lif) 3376 { 3377 struct ionic_admin_ctx ctx = { 3378 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3379 .cmd.lif_setattr = { 3380 .opcode = IONIC_CMD_LIF_SETATTR, 3381 .index = cpu_to_le16(lif->index), 3382 .attr = IONIC_LIF_ATTR_NAME, 3383 }, 3384 }; 3385 3386 strscpy(ctx.cmd.lif_setattr.name, lif->netdev->name, 3387 sizeof(ctx.cmd.lif_setattr.name)); 3388 3389 ionic_adminq_post_wait(lif, &ctx); 3390 } 3391 3392 static struct ionic_lif *ionic_netdev_lif(struct net_device *netdev) 3393 { 3394 if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit) 3395 return NULL; 3396 3397 return netdev_priv(netdev); 3398 } 3399 3400 static int ionic_lif_notify(struct notifier_block *nb, 3401 unsigned long event, void *info) 3402 { 3403 struct net_device *ndev = netdev_notifier_info_to_dev(info); 3404 struct ionic *ionic = container_of(nb, struct ionic, nb); 3405 struct ionic_lif *lif = ionic_netdev_lif(ndev); 3406 3407 if (!lif || lif->ionic != ionic) 3408 return NOTIFY_DONE; 3409 3410 switch (event) { 3411 case NETDEV_CHANGENAME: 3412 ionic_lif_set_netdev_info(lif); 3413 break; 3414 } 3415 3416 return NOTIFY_DONE; 3417 } 3418 3419 int ionic_lif_register(struct ionic_lif *lif) 3420 { 3421 int err; 3422 3423 ionic_lif_register_phc(lif); 3424 3425 INIT_WORK(&lif->ionic->nb_work, ionic_lif_notify_work); 3426 3427 lif->ionic->nb.notifier_call = ionic_lif_notify; 3428 3429 err = register_netdevice_notifier(&lif->ionic->nb); 3430 if (err) 3431 lif->ionic->nb.notifier_call = NULL; 3432 3433 /* only register LIF0 for now */ 3434 err = register_netdev(lif->netdev); 3435 if (err) { 3436 dev_err(lif->ionic->dev, "Cannot register net device, aborting\n"); 3437 ionic_lif_unregister_phc(lif); 3438 return err; 3439 } 3440 3441 ionic_link_status_check_request(lif, CAN_SLEEP); 3442 lif->registered = true; 3443 ionic_lif_set_netdev_info(lif); 3444 3445 return 0; 3446 } 3447 3448 void ionic_lif_unregister(struct ionic_lif *lif) 3449 { 3450 if (lif->ionic->nb.notifier_call) { 3451 unregister_netdevice_notifier(&lif->ionic->nb); 3452 cancel_work_sync(&lif->ionic->nb_work); 3453 lif->ionic->nb.notifier_call = NULL; 3454 } 3455 3456 if (lif->netdev->reg_state == NETREG_REGISTERED) 3457 unregister_netdev(lif->netdev); 3458 3459 ionic_lif_unregister_phc(lif); 3460 3461 lif->registered = false; 3462 } 3463 3464 static void ionic_lif_queue_identify(struct ionic_lif *lif) 3465 { 3466 union ionic_q_identity __iomem *q_ident; 3467 struct ionic *ionic = lif->ionic; 3468 struct ionic_dev *idev; 3469 int qtype; 3470 int err; 3471 3472 idev = &lif->ionic->idev; 3473 q_ident = (union ionic_q_identity __iomem *)&idev->dev_cmd_regs->data; 3474 3475 for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) { 3476 struct ionic_qtype_info *qti = &lif->qtype_info[qtype]; 3477 3478 /* filter out the ones we know about */ 3479 switch (qtype) { 3480 case IONIC_QTYPE_ADMINQ: 3481 case IONIC_QTYPE_NOTIFYQ: 3482 case IONIC_QTYPE_RXQ: 3483 case IONIC_QTYPE_TXQ: 3484 break; 3485 default: 3486 continue; 3487 } 3488 3489 memset(qti, 0, sizeof(*qti)); 3490 3491 mutex_lock(&ionic->dev_cmd_lock); 3492 ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype, 3493 ionic_qtype_versions[qtype]); 3494 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3495 if (!err) { 3496 qti->version = readb(&q_ident->version); 3497 qti->supported = readb(&q_ident->supported); 3498 qti->features = readq(&q_ident->features); 3499 qti->desc_sz = readw(&q_ident->desc_sz); 3500 qti->comp_sz = readw(&q_ident->comp_sz); 3501 qti->sg_desc_sz = readw(&q_ident->sg_desc_sz); 3502 qti->max_sg_elems = readw(&q_ident->max_sg_elems); 3503 qti->sg_desc_stride = readw(&q_ident->sg_desc_stride); 3504 } 3505 mutex_unlock(&ionic->dev_cmd_lock); 3506 3507 if (err == -EINVAL) { 3508 dev_err(ionic->dev, "qtype %d not supported\n", qtype); 3509 continue; 3510 } else if (err == -EIO) { 3511 dev_err(ionic->dev, "q_ident failed, not supported on older FW\n"); 3512 return; 3513 } else if (err) { 3514 dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n", 3515 qtype, err); 3516 return; 3517 } 3518 3519 dev_dbg(ionic->dev, " qtype[%d].version = %d\n", 3520 qtype, qti->version); 3521 dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n", 3522 qtype, qti->supported); 3523 dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n", 3524 qtype, qti->features); 3525 dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n", 3526 qtype, qti->desc_sz); 3527 dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n", 3528 qtype, qti->comp_sz); 3529 dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n", 3530 qtype, qti->sg_desc_sz); 3531 dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n", 3532 qtype, qti->max_sg_elems); 3533 dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n", 3534 qtype, qti->sg_desc_stride); 3535 } 3536 } 3537 3538 int ionic_lif_identify(struct ionic *ionic, u8 lif_type, 3539 union ionic_lif_identity *lid) 3540 { 3541 struct ionic_dev *idev = &ionic->idev; 3542 size_t sz; 3543 int err; 3544 3545 sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data)); 3546 3547 mutex_lock(&ionic->dev_cmd_lock); 3548 ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1); 3549 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3550 memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz); 3551 mutex_unlock(&ionic->dev_cmd_lock); 3552 if (err) 3553 return (err); 3554 3555 dev_dbg(ionic->dev, "capabilities 0x%llx\n", 3556 le64_to_cpu(lid->capabilities)); 3557 3558 dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n", 3559 le32_to_cpu(lid->eth.max_ucast_filters)); 3560 dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n", 3561 le32_to_cpu(lid->eth.max_mcast_filters)); 3562 dev_dbg(ionic->dev, "eth.features 0x%llx\n", 3563 le64_to_cpu(lid->eth.config.features)); 3564 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n", 3565 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ])); 3566 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n", 3567 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ])); 3568 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n", 3569 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ])); 3570 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n", 3571 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ])); 3572 dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name); 3573 dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac); 3574 dev_dbg(ionic->dev, "eth.config.mtu %d\n", 3575 le32_to_cpu(lid->eth.config.mtu)); 3576 3577 return 0; 3578 } 3579 3580 int ionic_lif_size(struct ionic *ionic) 3581 { 3582 struct ionic_identity *ident = &ionic->ident; 3583 unsigned int nintrs, dev_nintrs; 3584 union ionic_lif_config *lc; 3585 unsigned int ntxqs_per_lif; 3586 unsigned int nrxqs_per_lif; 3587 unsigned int neqs_per_lif; 3588 unsigned int nnqs_per_lif; 3589 unsigned int nxqs, neqs; 3590 unsigned int min_intrs; 3591 int err; 3592 3593 /* retrieve basic values from FW */ 3594 lc = &ident->lif.eth.config; 3595 dev_nintrs = le32_to_cpu(ident->dev.nintrs); 3596 neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count); 3597 nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]); 3598 ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]); 3599 nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]); 3600 3601 /* limit values to play nice with kdump */ 3602 if (is_kdump_kernel()) { 3603 dev_nintrs = 2; 3604 neqs_per_lif = 0; 3605 nnqs_per_lif = 0; 3606 ntxqs_per_lif = 1; 3607 nrxqs_per_lif = 1; 3608 } 3609 3610 /* reserve last queue id for hardware timestamping */ 3611 if (lc->features & cpu_to_le64(IONIC_ETH_HW_TIMESTAMP)) { 3612 if (ntxqs_per_lif <= 1 || nrxqs_per_lif <= 1) { 3613 lc->features &= cpu_to_le64(~IONIC_ETH_HW_TIMESTAMP); 3614 } else { 3615 ntxqs_per_lif -= 1; 3616 nrxqs_per_lif -= 1; 3617 } 3618 } 3619 3620 nxqs = min(ntxqs_per_lif, nrxqs_per_lif); 3621 nxqs = min(nxqs, num_online_cpus()); 3622 neqs = min(neqs_per_lif, num_online_cpus()); 3623 3624 try_again: 3625 /* interrupt usage: 3626 * 1 for master lif adminq/notifyq 3627 * 1 for each CPU for master lif TxRx queue pairs 3628 * whatever's left is for RDMA queues 3629 */ 3630 nintrs = 1 + nxqs + neqs; 3631 min_intrs = 2; /* adminq + 1 TxRx queue pair */ 3632 3633 if (nintrs > dev_nintrs) 3634 goto try_fewer; 3635 3636 err = ionic_bus_alloc_irq_vectors(ionic, nintrs); 3637 if (err < 0 && err != -ENOSPC) { 3638 dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err); 3639 return err; 3640 } 3641 if (err == -ENOSPC) 3642 goto try_fewer; 3643 3644 if (err != nintrs) { 3645 ionic_bus_free_irq_vectors(ionic); 3646 goto try_fewer; 3647 } 3648 3649 ionic->nnqs_per_lif = nnqs_per_lif; 3650 ionic->neqs_per_lif = neqs; 3651 ionic->ntxqs_per_lif = nxqs; 3652 ionic->nrxqs_per_lif = nxqs; 3653 ionic->nintrs = nintrs; 3654 3655 ionic_debugfs_add_sizes(ionic); 3656 3657 return 0; 3658 3659 try_fewer: 3660 if (nnqs_per_lif > 1) { 3661 nnqs_per_lif >>= 1; 3662 goto try_again; 3663 } 3664 if (neqs > 1) { 3665 neqs >>= 1; 3666 goto try_again; 3667 } 3668 if (nxqs > 1) { 3669 nxqs >>= 1; 3670 goto try_again; 3671 } 3672 dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs); 3673 return -ENOSPC; 3674 } 3675