1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/ethtool.h> 5 #include <linux/printk.h> 6 #include <linux/dynamic_debug.h> 7 #include <linux/netdevice.h> 8 #include <linux/etherdevice.h> 9 #include <linux/if_vlan.h> 10 #include <linux/rtnetlink.h> 11 #include <linux/interrupt.h> 12 #include <linux/pci.h> 13 #include <linux/cpumask.h> 14 #include <linux/crash_dump.h> 15 16 #include "ionic.h" 17 #include "ionic_bus.h" 18 #include "ionic_lif.h" 19 #include "ionic_txrx.h" 20 #include "ionic_ethtool.h" 21 #include "ionic_debugfs.h" 22 23 /* queuetype support level */ 24 static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = { 25 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */ 26 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */ 27 [IONIC_QTYPE_RXQ] = 0, /* 0 = Base version with CQ+SG support */ 28 [IONIC_QTYPE_TXQ] = 1, /* 0 = Base version with CQ+SG support 29 * 1 = ... with Tx SG version 1 30 */ 31 }; 32 33 static void ionic_link_status_check(struct ionic_lif *lif); 34 static void ionic_lif_handle_fw_down(struct ionic_lif *lif); 35 static void ionic_lif_handle_fw_up(struct ionic_lif *lif); 36 static void ionic_lif_set_netdev_info(struct ionic_lif *lif); 37 38 static void ionic_txrx_deinit(struct ionic_lif *lif); 39 static int ionic_txrx_init(struct ionic_lif *lif); 40 static int ionic_start_queues(struct ionic_lif *lif); 41 static void ionic_stop_queues(struct ionic_lif *lif); 42 static void ionic_lif_queue_identify(struct ionic_lif *lif); 43 44 static void ionic_dim_work(struct work_struct *work) 45 { 46 struct dim *dim = container_of(work, struct dim, work); 47 struct dim_cq_moder cur_moder; 48 struct ionic_qcq *qcq; 49 u32 new_coal; 50 51 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 52 qcq = container_of(dim, struct ionic_qcq, dim); 53 new_coal = ionic_coal_usec_to_hw(qcq->q.lif->ionic, cur_moder.usec); 54 new_coal = new_coal ? new_coal : 1; 55 56 if (qcq->intr.dim_coal_hw != new_coal) { 57 unsigned int qi = qcq->cq.bound_q->index; 58 struct ionic_lif *lif = qcq->q.lif; 59 60 qcq->intr.dim_coal_hw = new_coal; 61 62 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 63 lif->rxqcqs[qi]->intr.index, 64 qcq->intr.dim_coal_hw); 65 } 66 67 dim->state = DIM_START_MEASURE; 68 } 69 70 static void ionic_lif_deferred_work(struct work_struct *work) 71 { 72 struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work); 73 struct ionic_deferred *def = &lif->deferred; 74 struct ionic_deferred_work *w = NULL; 75 76 do { 77 spin_lock_bh(&def->lock); 78 if (!list_empty(&def->list)) { 79 w = list_first_entry(&def->list, 80 struct ionic_deferred_work, list); 81 list_del(&w->list); 82 } 83 spin_unlock_bh(&def->lock); 84 85 if (!w) 86 break; 87 88 switch (w->type) { 89 case IONIC_DW_TYPE_RX_MODE: 90 ionic_lif_rx_mode(lif); 91 break; 92 case IONIC_DW_TYPE_LINK_STATUS: 93 ionic_link_status_check(lif); 94 break; 95 case IONIC_DW_TYPE_LIF_RESET: 96 if (w->fw_status) { 97 ionic_lif_handle_fw_up(lif); 98 } else { 99 ionic_lif_handle_fw_down(lif); 100 101 /* Fire off another watchdog to see 102 * if the FW is already back rather than 103 * waiting another whole cycle 104 */ 105 mod_timer(&lif->ionic->watchdog_timer, jiffies + 1); 106 } 107 break; 108 default: 109 break; 110 } 111 kfree(w); 112 w = NULL; 113 } while (true); 114 } 115 116 void ionic_lif_deferred_enqueue(struct ionic_deferred *def, 117 struct ionic_deferred_work *work) 118 { 119 spin_lock_bh(&def->lock); 120 list_add_tail(&work->list, &def->list); 121 spin_unlock_bh(&def->lock); 122 schedule_work(&def->work); 123 } 124 125 static void ionic_link_status_check(struct ionic_lif *lif) 126 { 127 struct net_device *netdev = lif->netdev; 128 u16 link_status; 129 bool link_up; 130 131 if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 132 return; 133 134 /* Don't put carrier back up if we're in a broken state */ 135 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) { 136 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 137 return; 138 } 139 140 link_status = le16_to_cpu(lif->info->status.link_status); 141 link_up = link_status == IONIC_PORT_OPER_STATUS_UP; 142 143 if (link_up) { 144 int err = 0; 145 146 if (netdev->flags & IFF_UP && netif_running(netdev)) { 147 mutex_lock(&lif->queue_lock); 148 err = ionic_start_queues(lif); 149 if (err && err != -EBUSY) { 150 netdev_err(lif->netdev, 151 "Failed to start queues: %d\n", err); 152 set_bit(IONIC_LIF_F_BROKEN, lif->state); 153 netif_carrier_off(lif->netdev); 154 } 155 mutex_unlock(&lif->queue_lock); 156 } 157 158 if (!err && !netif_carrier_ok(netdev)) { 159 ionic_port_identify(lif->ionic); 160 netdev_info(netdev, "Link up - %d Gbps\n", 161 le32_to_cpu(lif->info->status.link_speed) / 1000); 162 netif_carrier_on(netdev); 163 } 164 } else { 165 if (netif_carrier_ok(netdev)) { 166 netdev_info(netdev, "Link down\n"); 167 netif_carrier_off(netdev); 168 } 169 170 if (netdev->flags & IFF_UP && netif_running(netdev)) { 171 mutex_lock(&lif->queue_lock); 172 ionic_stop_queues(lif); 173 mutex_unlock(&lif->queue_lock); 174 } 175 } 176 177 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 178 } 179 180 void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep) 181 { 182 struct ionic_deferred_work *work; 183 184 /* we only need one request outstanding at a time */ 185 if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 186 return; 187 188 if (!can_sleep) { 189 work = kzalloc(sizeof(*work), GFP_ATOMIC); 190 if (!work) { 191 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 192 return; 193 } 194 195 work->type = IONIC_DW_TYPE_LINK_STATUS; 196 ionic_lif_deferred_enqueue(&lif->deferred, work); 197 } else { 198 ionic_link_status_check(lif); 199 } 200 } 201 202 static irqreturn_t ionic_isr(int irq, void *data) 203 { 204 struct napi_struct *napi = data; 205 206 napi_schedule_irqoff(napi); 207 208 return IRQ_HANDLED; 209 } 210 211 static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq) 212 { 213 struct ionic_intr_info *intr = &qcq->intr; 214 struct device *dev = lif->ionic->dev; 215 struct ionic_queue *q = &qcq->q; 216 const char *name; 217 218 if (lif->registered) 219 name = lif->netdev->name; 220 else 221 name = dev_name(dev); 222 223 snprintf(intr->name, sizeof(intr->name), 224 "%s-%s-%s", IONIC_DRV_NAME, name, q->name); 225 226 return devm_request_irq(dev, intr->vector, ionic_isr, 227 0, intr->name, &qcq->napi); 228 } 229 230 static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) 231 { 232 struct ionic *ionic = lif->ionic; 233 int index; 234 235 index = find_first_zero_bit(ionic->intrs, ionic->nintrs); 236 if (index == ionic->nintrs) { 237 netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n", 238 __func__, index, ionic->nintrs); 239 return -ENOSPC; 240 } 241 242 set_bit(index, ionic->intrs); 243 ionic_intr_init(&ionic->idev, intr, index); 244 245 return 0; 246 } 247 248 static void ionic_intr_free(struct ionic *ionic, int index) 249 { 250 if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < ionic->nintrs) 251 clear_bit(index, ionic->intrs); 252 } 253 254 static int ionic_qcq_enable(struct ionic_qcq *qcq) 255 { 256 struct ionic_queue *q = &qcq->q; 257 struct ionic_lif *lif = q->lif; 258 struct ionic_dev *idev; 259 struct device *dev; 260 261 struct ionic_admin_ctx ctx = { 262 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 263 .cmd.q_control = { 264 .opcode = IONIC_CMD_Q_CONTROL, 265 .lif_index = cpu_to_le16(lif->index), 266 .type = q->type, 267 .index = cpu_to_le32(q->index), 268 .oper = IONIC_Q_ENABLE, 269 }, 270 }; 271 272 idev = &lif->ionic->idev; 273 dev = lif->ionic->dev; 274 275 dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n", 276 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 277 278 if (qcq->flags & IONIC_QCQ_F_INTR) { 279 irq_set_affinity_hint(qcq->intr.vector, 280 &qcq->intr.affinity_mask); 281 napi_enable(&qcq->napi); 282 ionic_intr_clean(idev->intr_ctrl, qcq->intr.index); 283 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 284 IONIC_INTR_MASK_CLEAR); 285 } 286 287 return ionic_adminq_post_wait(lif, &ctx); 288 } 289 290 static int ionic_qcq_disable(struct ionic_lif *lif, struct ionic_qcq *qcq, int fw_err) 291 { 292 struct ionic_queue *q; 293 294 struct ionic_admin_ctx ctx = { 295 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 296 .cmd.q_control = { 297 .opcode = IONIC_CMD_Q_CONTROL, 298 .oper = IONIC_Q_DISABLE, 299 }, 300 }; 301 302 if (!qcq) { 303 netdev_err(lif->netdev, "%s: bad qcq\n", __func__); 304 return -ENXIO; 305 } 306 307 q = &qcq->q; 308 309 if (qcq->flags & IONIC_QCQ_F_INTR) { 310 struct ionic_dev *idev = &lif->ionic->idev; 311 312 cancel_work_sync(&qcq->dim.work); 313 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 314 IONIC_INTR_MASK_SET); 315 synchronize_irq(qcq->intr.vector); 316 irq_set_affinity_hint(qcq->intr.vector, NULL); 317 napi_disable(&qcq->napi); 318 } 319 320 /* If there was a previous fw communcation error, don't bother with 321 * sending the adminq command and just return the same error value. 322 */ 323 if (fw_err == -ETIMEDOUT || fw_err == -ENXIO) 324 return fw_err; 325 326 ctx.cmd.q_control.lif_index = cpu_to_le16(lif->index); 327 ctx.cmd.q_control.type = q->type; 328 ctx.cmd.q_control.index = cpu_to_le32(q->index); 329 dev_dbg(lif->ionic->dev, "q_disable.index %d q_disable.qtype %d\n", 330 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 331 332 return ionic_adminq_post_wait(lif, &ctx); 333 } 334 335 static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq) 336 { 337 struct ionic_dev *idev = &lif->ionic->idev; 338 339 if (!qcq) 340 return; 341 342 if (!(qcq->flags & IONIC_QCQ_F_INITED)) 343 return; 344 345 if (qcq->flags & IONIC_QCQ_F_INTR) { 346 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 347 IONIC_INTR_MASK_SET); 348 netif_napi_del(&qcq->napi); 349 } 350 351 qcq->flags &= ~IONIC_QCQ_F_INITED; 352 } 353 354 static void ionic_qcq_intr_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 355 { 356 if (!(qcq->flags & IONIC_QCQ_F_INTR) || qcq->intr.vector == 0) 357 return; 358 359 irq_set_affinity_hint(qcq->intr.vector, NULL); 360 devm_free_irq(lif->ionic->dev, qcq->intr.vector, &qcq->napi); 361 qcq->intr.vector = 0; 362 ionic_intr_free(lif->ionic, qcq->intr.index); 363 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 364 } 365 366 static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 367 { 368 struct device *dev = lif->ionic->dev; 369 370 if (!qcq) 371 return; 372 373 ionic_debugfs_del_qcq(qcq); 374 375 if (qcq->q_base) { 376 dma_free_coherent(dev, qcq->q_size, qcq->q_base, qcq->q_base_pa); 377 qcq->q_base = NULL; 378 qcq->q_base_pa = 0; 379 } 380 381 if (qcq->cq_base) { 382 dma_free_coherent(dev, qcq->cq_size, qcq->cq_base, qcq->cq_base_pa); 383 qcq->cq_base = NULL; 384 qcq->cq_base_pa = 0; 385 } 386 387 if (qcq->sg_base) { 388 dma_free_coherent(dev, qcq->sg_size, qcq->sg_base, qcq->sg_base_pa); 389 qcq->sg_base = NULL; 390 qcq->sg_base_pa = 0; 391 } 392 393 ionic_qcq_intr_free(lif, qcq); 394 395 if (qcq->cq.info) { 396 devm_kfree(dev, qcq->cq.info); 397 qcq->cq.info = NULL; 398 } 399 if (qcq->q.info) { 400 devm_kfree(dev, qcq->q.info); 401 qcq->q.info = NULL; 402 } 403 } 404 405 static void ionic_qcqs_free(struct ionic_lif *lif) 406 { 407 struct device *dev = lif->ionic->dev; 408 struct ionic_qcq *adminqcq; 409 unsigned long irqflags; 410 411 if (lif->notifyqcq) { 412 ionic_qcq_free(lif, lif->notifyqcq); 413 devm_kfree(dev, lif->notifyqcq); 414 lif->notifyqcq = NULL; 415 } 416 417 if (lif->adminqcq) { 418 spin_lock_irqsave(&lif->adminq_lock, irqflags); 419 adminqcq = READ_ONCE(lif->adminqcq); 420 lif->adminqcq = NULL; 421 spin_unlock_irqrestore(&lif->adminq_lock, irqflags); 422 if (adminqcq) { 423 ionic_qcq_free(lif, adminqcq); 424 devm_kfree(dev, adminqcq); 425 } 426 } 427 428 if (lif->rxqcqs) { 429 devm_kfree(dev, lif->rxqstats); 430 lif->rxqstats = NULL; 431 devm_kfree(dev, lif->rxqcqs); 432 lif->rxqcqs = NULL; 433 } 434 435 if (lif->txqcqs) { 436 devm_kfree(dev, lif->txqstats); 437 lif->txqstats = NULL; 438 devm_kfree(dev, lif->txqcqs); 439 lif->txqcqs = NULL; 440 } 441 } 442 443 static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq, 444 struct ionic_qcq *n_qcq) 445 { 446 if (WARN_ON(n_qcq->flags & IONIC_QCQ_F_INTR)) { 447 ionic_intr_free(n_qcq->cq.lif->ionic, n_qcq->intr.index); 448 n_qcq->flags &= ~IONIC_QCQ_F_INTR; 449 } 450 451 n_qcq->intr.vector = src_qcq->intr.vector; 452 n_qcq->intr.index = src_qcq->intr.index; 453 } 454 455 static int ionic_alloc_qcq_interrupt(struct ionic_lif *lif, struct ionic_qcq *qcq) 456 { 457 int err; 458 459 if (!(qcq->flags & IONIC_QCQ_F_INTR)) { 460 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 461 return 0; 462 } 463 464 err = ionic_intr_alloc(lif, &qcq->intr); 465 if (err) { 466 netdev_warn(lif->netdev, "no intr for %s: %d\n", 467 qcq->q.name, err); 468 goto err_out; 469 } 470 471 err = ionic_bus_get_irq(lif->ionic, qcq->intr.index); 472 if (err < 0) { 473 netdev_warn(lif->netdev, "no vector for %s: %d\n", 474 qcq->q.name, err); 475 goto err_out_free_intr; 476 } 477 qcq->intr.vector = err; 478 ionic_intr_mask_assert(lif->ionic->idev.intr_ctrl, qcq->intr.index, 479 IONIC_INTR_MASK_SET); 480 481 err = ionic_request_irq(lif, qcq); 482 if (err) { 483 netdev_warn(lif->netdev, "irq request failed %d\n", err); 484 goto err_out_free_intr; 485 } 486 487 /* try to get the irq on the local numa node first */ 488 qcq->intr.cpu = cpumask_local_spread(qcq->intr.index, 489 dev_to_node(lif->ionic->dev)); 490 if (qcq->intr.cpu != -1) 491 cpumask_set_cpu(qcq->intr.cpu, &qcq->intr.affinity_mask); 492 493 netdev_dbg(lif->netdev, "%s: Interrupt index %d\n", qcq->q.name, qcq->intr.index); 494 return 0; 495 496 err_out_free_intr: 497 ionic_intr_free(lif->ionic, qcq->intr.index); 498 err_out: 499 return err; 500 } 501 502 static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type, 503 unsigned int index, 504 const char *name, unsigned int flags, 505 unsigned int num_descs, unsigned int desc_size, 506 unsigned int cq_desc_size, 507 unsigned int sg_desc_size, 508 unsigned int pid, struct ionic_qcq **qcq) 509 { 510 struct ionic_dev *idev = &lif->ionic->idev; 511 struct device *dev = lif->ionic->dev; 512 void *q_base, *cq_base, *sg_base; 513 dma_addr_t cq_base_pa = 0; 514 dma_addr_t sg_base_pa = 0; 515 dma_addr_t q_base_pa = 0; 516 struct ionic_qcq *new; 517 int err; 518 519 *qcq = NULL; 520 521 new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL); 522 if (!new) { 523 netdev_err(lif->netdev, "Cannot allocate queue structure\n"); 524 err = -ENOMEM; 525 goto err_out; 526 } 527 528 new->q.dev = dev; 529 new->flags = flags; 530 531 new->q.info = devm_kcalloc(dev, num_descs, sizeof(*new->q.info), 532 GFP_KERNEL); 533 if (!new->q.info) { 534 netdev_err(lif->netdev, "Cannot allocate queue info\n"); 535 err = -ENOMEM; 536 goto err_out_free_qcq; 537 } 538 539 new->q.type = type; 540 new->q.max_sg_elems = lif->qtype_info[type].max_sg_elems; 541 542 err = ionic_q_init(lif, idev, &new->q, index, name, num_descs, 543 desc_size, sg_desc_size, pid); 544 if (err) { 545 netdev_err(lif->netdev, "Cannot initialize queue\n"); 546 goto err_out_free_q_info; 547 } 548 549 err = ionic_alloc_qcq_interrupt(lif, new); 550 if (err) 551 goto err_out; 552 553 new->cq.info = devm_kcalloc(dev, num_descs, sizeof(*new->cq.info), 554 GFP_KERNEL); 555 if (!new->cq.info) { 556 netdev_err(lif->netdev, "Cannot allocate completion queue info\n"); 557 err = -ENOMEM; 558 goto err_out_free_irq; 559 } 560 561 err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size); 562 if (err) { 563 netdev_err(lif->netdev, "Cannot initialize completion queue\n"); 564 goto err_out_free_cq_info; 565 } 566 567 if (flags & IONIC_QCQ_F_NOTIFYQ) { 568 int q_size, cq_size; 569 570 /* q & cq need to be contiguous in case of notifyq */ 571 q_size = ALIGN(num_descs * desc_size, PAGE_SIZE); 572 cq_size = ALIGN(num_descs * cq_desc_size, PAGE_SIZE); 573 574 new->q_size = PAGE_SIZE + q_size + cq_size; 575 new->q_base = dma_alloc_coherent(dev, new->q_size, 576 &new->q_base_pa, GFP_KERNEL); 577 if (!new->q_base) { 578 netdev_err(lif->netdev, "Cannot allocate qcq DMA memory\n"); 579 err = -ENOMEM; 580 goto err_out_free_cq_info; 581 } 582 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE); 583 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 584 ionic_q_map(&new->q, q_base, q_base_pa); 585 586 cq_base = PTR_ALIGN(q_base + q_size, PAGE_SIZE); 587 cq_base_pa = ALIGN(new->q_base_pa + q_size, PAGE_SIZE); 588 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 589 ionic_cq_bind(&new->cq, &new->q); 590 } else { 591 new->q_size = PAGE_SIZE + (num_descs * desc_size); 592 new->q_base = dma_alloc_coherent(dev, new->q_size, &new->q_base_pa, 593 GFP_KERNEL); 594 if (!new->q_base) { 595 netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n"); 596 err = -ENOMEM; 597 goto err_out_free_cq_info; 598 } 599 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE); 600 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 601 ionic_q_map(&new->q, q_base, q_base_pa); 602 603 new->cq_size = PAGE_SIZE + (num_descs * cq_desc_size); 604 new->cq_base = dma_alloc_coherent(dev, new->cq_size, &new->cq_base_pa, 605 GFP_KERNEL); 606 if (!new->cq_base) { 607 netdev_err(lif->netdev, "Cannot allocate cq DMA memory\n"); 608 err = -ENOMEM; 609 goto err_out_free_q; 610 } 611 cq_base = PTR_ALIGN(new->cq_base, PAGE_SIZE); 612 cq_base_pa = ALIGN(new->cq_base_pa, PAGE_SIZE); 613 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 614 ionic_cq_bind(&new->cq, &new->q); 615 } 616 617 if (flags & IONIC_QCQ_F_SG) { 618 new->sg_size = PAGE_SIZE + (num_descs * sg_desc_size); 619 new->sg_base = dma_alloc_coherent(dev, new->sg_size, &new->sg_base_pa, 620 GFP_KERNEL); 621 if (!new->sg_base) { 622 netdev_err(lif->netdev, "Cannot allocate sg DMA memory\n"); 623 err = -ENOMEM; 624 goto err_out_free_cq; 625 } 626 sg_base = PTR_ALIGN(new->sg_base, PAGE_SIZE); 627 sg_base_pa = ALIGN(new->sg_base_pa, PAGE_SIZE); 628 ionic_q_sg_map(&new->q, sg_base, sg_base_pa); 629 } 630 631 INIT_WORK(&new->dim.work, ionic_dim_work); 632 new->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 633 634 *qcq = new; 635 636 return 0; 637 638 err_out_free_cq: 639 dma_free_coherent(dev, new->cq_size, new->cq_base, new->cq_base_pa); 640 err_out_free_q: 641 dma_free_coherent(dev, new->q_size, new->q_base, new->q_base_pa); 642 err_out_free_cq_info: 643 devm_kfree(dev, new->cq.info); 644 err_out_free_irq: 645 if (flags & IONIC_QCQ_F_INTR) { 646 devm_free_irq(dev, new->intr.vector, &new->napi); 647 ionic_intr_free(lif->ionic, new->intr.index); 648 } 649 err_out_free_q_info: 650 devm_kfree(dev, new->q.info); 651 err_out_free_qcq: 652 devm_kfree(dev, new); 653 err_out: 654 dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err); 655 return err; 656 } 657 658 static int ionic_qcqs_alloc(struct ionic_lif *lif) 659 { 660 struct device *dev = lif->ionic->dev; 661 unsigned int flags; 662 int err; 663 664 flags = IONIC_QCQ_F_INTR; 665 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags, 666 IONIC_ADMINQ_LENGTH, 667 sizeof(struct ionic_admin_cmd), 668 sizeof(struct ionic_admin_comp), 669 0, lif->kern_pid, &lif->adminqcq); 670 if (err) 671 return err; 672 ionic_debugfs_add_qcq(lif, lif->adminqcq); 673 674 if (lif->ionic->nnqs_per_lif) { 675 flags = IONIC_QCQ_F_NOTIFYQ; 676 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq", 677 flags, IONIC_NOTIFYQ_LENGTH, 678 sizeof(struct ionic_notifyq_cmd), 679 sizeof(union ionic_notifyq_comp), 680 0, lif->kern_pid, &lif->notifyqcq); 681 if (err) 682 goto err_out; 683 ionic_debugfs_add_qcq(lif, lif->notifyqcq); 684 685 /* Let the notifyq ride on the adminq interrupt */ 686 ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq); 687 } 688 689 err = -ENOMEM; 690 lif->txqcqs = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif, 691 sizeof(*lif->txqcqs), GFP_KERNEL); 692 if (!lif->txqcqs) 693 goto err_out; 694 lif->rxqcqs = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif, 695 sizeof(*lif->rxqcqs), GFP_KERNEL); 696 if (!lif->rxqcqs) 697 goto err_out; 698 699 lif->txqstats = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif + 1, 700 sizeof(*lif->txqstats), GFP_KERNEL); 701 if (!lif->txqstats) 702 goto err_out; 703 lif->rxqstats = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif + 1, 704 sizeof(*lif->rxqstats), GFP_KERNEL); 705 if (!lif->rxqstats) 706 goto err_out; 707 708 return 0; 709 710 err_out: 711 ionic_qcqs_free(lif); 712 return err; 713 } 714 715 static void ionic_qcq_sanitize(struct ionic_qcq *qcq) 716 { 717 qcq->q.tail_idx = 0; 718 qcq->q.head_idx = 0; 719 qcq->cq.tail_idx = 0; 720 qcq->cq.done_color = 1; 721 memset(qcq->q_base, 0, qcq->q_size); 722 memset(qcq->cq_base, 0, qcq->cq_size); 723 memset(qcq->sg_base, 0, qcq->sg_size); 724 } 725 726 static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 727 { 728 struct device *dev = lif->ionic->dev; 729 struct ionic_queue *q = &qcq->q; 730 struct ionic_cq *cq = &qcq->cq; 731 struct ionic_admin_ctx ctx = { 732 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 733 .cmd.q_init = { 734 .opcode = IONIC_CMD_Q_INIT, 735 .lif_index = cpu_to_le16(lif->index), 736 .type = q->type, 737 .ver = lif->qtype_info[q->type].version, 738 .index = cpu_to_le32(q->index), 739 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 740 IONIC_QINIT_F_SG), 741 .pid = cpu_to_le16(q->pid), 742 .ring_size = ilog2(q->num_descs), 743 .ring_base = cpu_to_le64(q->base_pa), 744 .cq_ring_base = cpu_to_le64(cq->base_pa), 745 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 746 .features = cpu_to_le64(q->features), 747 }, 748 }; 749 unsigned int intr_index; 750 int err; 751 752 intr_index = qcq->intr.index; 753 754 ctx.cmd.q_init.intr_index = cpu_to_le16(intr_index); 755 756 dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid); 757 dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index); 758 dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 759 dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 760 dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 761 dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver); 762 dev_dbg(dev, "txq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 763 764 ionic_qcq_sanitize(qcq); 765 766 err = ionic_adminq_post_wait(lif, &ctx); 767 if (err) 768 return err; 769 770 q->hw_type = ctx.comp.q_init.hw_type; 771 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 772 q->dbval = IONIC_DBELL_QID(q->hw_index); 773 774 dev_dbg(dev, "txq->hw_type %d\n", q->hw_type); 775 dev_dbg(dev, "txq->hw_index %d\n", q->hw_index); 776 777 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 778 netif_napi_add(lif->netdev, &qcq->napi, ionic_tx_napi, 779 NAPI_POLL_WEIGHT); 780 781 qcq->flags |= IONIC_QCQ_F_INITED; 782 783 return 0; 784 } 785 786 static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 787 { 788 struct device *dev = lif->ionic->dev; 789 struct ionic_queue *q = &qcq->q; 790 struct ionic_cq *cq = &qcq->cq; 791 struct ionic_admin_ctx ctx = { 792 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 793 .cmd.q_init = { 794 .opcode = IONIC_CMD_Q_INIT, 795 .lif_index = cpu_to_le16(lif->index), 796 .type = q->type, 797 .ver = lif->qtype_info[q->type].version, 798 .index = cpu_to_le32(q->index), 799 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 800 IONIC_QINIT_F_SG), 801 .intr_index = cpu_to_le16(cq->bound_intr->index), 802 .pid = cpu_to_le16(q->pid), 803 .ring_size = ilog2(q->num_descs), 804 .ring_base = cpu_to_le64(q->base_pa), 805 .cq_ring_base = cpu_to_le64(cq->base_pa), 806 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 807 .features = cpu_to_le64(q->features), 808 }, 809 }; 810 int err; 811 812 dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid); 813 dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index); 814 dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 815 dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 816 dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 817 dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver); 818 dev_dbg(dev, "rxq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 819 820 ionic_qcq_sanitize(qcq); 821 822 err = ionic_adminq_post_wait(lif, &ctx); 823 if (err) 824 return err; 825 826 q->hw_type = ctx.comp.q_init.hw_type; 827 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 828 q->dbval = IONIC_DBELL_QID(q->hw_index); 829 830 dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type); 831 dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index); 832 833 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 834 netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi, 835 NAPI_POLL_WEIGHT); 836 else 837 netif_napi_add(lif->netdev, &qcq->napi, ionic_txrx_napi, 838 NAPI_POLL_WEIGHT); 839 840 qcq->flags |= IONIC_QCQ_F_INITED; 841 842 return 0; 843 } 844 845 int ionic_lif_create_hwstamp_txq(struct ionic_lif *lif) 846 { 847 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz; 848 unsigned int txq_i, flags; 849 struct ionic_qcq *txq; 850 u64 features; 851 int err; 852 853 if (lif->hwstamp_txq) 854 return 0; 855 856 features = IONIC_Q_F_2X_CQ_DESC | IONIC_TXQ_F_HWSTAMP; 857 858 num_desc = IONIC_MIN_TXRX_DESC; 859 desc_sz = sizeof(struct ionic_txq_desc); 860 comp_sz = 2 * sizeof(struct ionic_txq_comp); 861 862 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 863 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == sizeof(struct ionic_txq_sg_desc_v1)) 864 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 865 else 866 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 867 868 txq_i = lif->ionic->ntxqs_per_lif; 869 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 870 871 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, txq_i, "hwstamp_tx", flags, 872 num_desc, desc_sz, comp_sz, sg_desc_sz, 873 lif->kern_pid, &txq); 874 if (err) 875 goto err_qcq_alloc; 876 877 txq->q.features = features; 878 879 ionic_link_qcq_interrupts(lif->adminqcq, txq); 880 ionic_debugfs_add_qcq(lif, txq); 881 882 lif->hwstamp_txq = txq; 883 884 if (netif_running(lif->netdev)) { 885 err = ionic_lif_txq_init(lif, txq); 886 if (err) 887 goto err_qcq_init; 888 889 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 890 err = ionic_qcq_enable(txq); 891 if (err) 892 goto err_qcq_enable; 893 } 894 } 895 896 return 0; 897 898 err_qcq_enable: 899 ionic_lif_qcq_deinit(lif, txq); 900 err_qcq_init: 901 lif->hwstamp_txq = NULL; 902 ionic_debugfs_del_qcq(txq); 903 ionic_qcq_free(lif, txq); 904 devm_kfree(lif->ionic->dev, txq); 905 err_qcq_alloc: 906 return err; 907 } 908 909 int ionic_lif_create_hwstamp_rxq(struct ionic_lif *lif) 910 { 911 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz; 912 unsigned int rxq_i, flags; 913 struct ionic_qcq *rxq; 914 u64 features; 915 int err; 916 917 if (lif->hwstamp_rxq) 918 return 0; 919 920 features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP; 921 922 num_desc = IONIC_MIN_TXRX_DESC; 923 desc_sz = sizeof(struct ionic_rxq_desc); 924 comp_sz = 2 * sizeof(struct ionic_rxq_comp); 925 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 926 927 rxq_i = lif->ionic->nrxqs_per_lif; 928 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG; 929 930 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, rxq_i, "hwstamp_rx", flags, 931 num_desc, desc_sz, comp_sz, sg_desc_sz, 932 lif->kern_pid, &rxq); 933 if (err) 934 goto err_qcq_alloc; 935 936 rxq->q.features = features; 937 938 ionic_link_qcq_interrupts(lif->adminqcq, rxq); 939 ionic_debugfs_add_qcq(lif, rxq); 940 941 lif->hwstamp_rxq = rxq; 942 943 if (netif_running(lif->netdev)) { 944 err = ionic_lif_rxq_init(lif, rxq); 945 if (err) 946 goto err_qcq_init; 947 948 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 949 ionic_rx_fill(&rxq->q); 950 err = ionic_qcq_enable(rxq); 951 if (err) 952 goto err_qcq_enable; 953 } 954 } 955 956 return 0; 957 958 err_qcq_enable: 959 ionic_lif_qcq_deinit(lif, rxq); 960 err_qcq_init: 961 lif->hwstamp_rxq = NULL; 962 ionic_debugfs_del_qcq(rxq); 963 ionic_qcq_free(lif, rxq); 964 devm_kfree(lif->ionic->dev, rxq); 965 err_qcq_alloc: 966 return err; 967 } 968 969 int ionic_lif_config_hwstamp_rxq_all(struct ionic_lif *lif, bool rx_all) 970 { 971 struct ionic_queue_params qparam; 972 973 ionic_init_queue_params(lif, &qparam); 974 975 if (rx_all) 976 qparam.rxq_features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP; 977 else 978 qparam.rxq_features = 0; 979 980 /* if we're not running, just set the values and return */ 981 if (!netif_running(lif->netdev)) { 982 lif->rxq_features = qparam.rxq_features; 983 return 0; 984 } 985 986 return ionic_reconfigure_queues(lif, &qparam); 987 } 988 989 int ionic_lif_set_hwstamp_txmode(struct ionic_lif *lif, u16 txstamp_mode) 990 { 991 struct ionic_admin_ctx ctx = { 992 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 993 .cmd.lif_setattr = { 994 .opcode = IONIC_CMD_LIF_SETATTR, 995 .index = cpu_to_le16(lif->index), 996 .attr = IONIC_LIF_ATTR_TXSTAMP, 997 .txstamp_mode = cpu_to_le16(txstamp_mode), 998 }, 999 }; 1000 1001 return ionic_adminq_post_wait(lif, &ctx); 1002 } 1003 1004 static void ionic_lif_del_hwstamp_rxfilt(struct ionic_lif *lif) 1005 { 1006 struct ionic_admin_ctx ctx = { 1007 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1008 .cmd.rx_filter_del = { 1009 .opcode = IONIC_CMD_RX_FILTER_DEL, 1010 .lif_index = cpu_to_le16(lif->index), 1011 }, 1012 }; 1013 struct ionic_rx_filter *f; 1014 u32 filter_id; 1015 int err; 1016 1017 spin_lock_bh(&lif->rx_filters.lock); 1018 1019 f = ionic_rx_filter_rxsteer(lif); 1020 if (!f) { 1021 spin_unlock_bh(&lif->rx_filters.lock); 1022 return; 1023 } 1024 1025 filter_id = f->filter_id; 1026 ionic_rx_filter_free(lif, f); 1027 1028 spin_unlock_bh(&lif->rx_filters.lock); 1029 1030 netdev_dbg(lif->netdev, "rx_filter del RXSTEER (id %d)\n", filter_id); 1031 1032 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(filter_id); 1033 1034 err = ionic_adminq_post_wait(lif, &ctx); 1035 if (err && err != -EEXIST) 1036 netdev_dbg(lif->netdev, "failed to delete rx_filter RXSTEER (id %d)\n", filter_id); 1037 } 1038 1039 static int ionic_lif_add_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class) 1040 { 1041 struct ionic_admin_ctx ctx = { 1042 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1043 .cmd.rx_filter_add = { 1044 .opcode = IONIC_CMD_RX_FILTER_ADD, 1045 .lif_index = cpu_to_le16(lif->index), 1046 .match = cpu_to_le16(IONIC_RX_FILTER_STEER_PKTCLASS), 1047 .pkt_class = cpu_to_le64(pkt_class), 1048 }, 1049 }; 1050 u8 qtype; 1051 u32 qid; 1052 int err; 1053 1054 if (!lif->hwstamp_rxq) 1055 return -EINVAL; 1056 1057 qtype = lif->hwstamp_rxq->q.type; 1058 ctx.cmd.rx_filter_add.qtype = qtype; 1059 1060 qid = lif->hwstamp_rxq->q.index; 1061 ctx.cmd.rx_filter_add.qid = cpu_to_le32(qid); 1062 1063 netdev_dbg(lif->netdev, "rx_filter add RXSTEER\n"); 1064 err = ionic_adminq_post_wait(lif, &ctx); 1065 if (err && err != -EEXIST) 1066 return err; 1067 1068 spin_lock_bh(&lif->rx_filters.lock); 1069 err = ionic_rx_filter_save(lif, 0, qid, 0, &ctx, IONIC_FILTER_STATE_SYNCED); 1070 spin_unlock_bh(&lif->rx_filters.lock); 1071 1072 return err; 1073 } 1074 1075 int ionic_lif_set_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class) 1076 { 1077 ionic_lif_del_hwstamp_rxfilt(lif); 1078 1079 if (!pkt_class) 1080 return 0; 1081 1082 return ionic_lif_add_hwstamp_rxfilt(lif, pkt_class); 1083 } 1084 1085 static bool ionic_notifyq_service(struct ionic_cq *cq, 1086 struct ionic_cq_info *cq_info) 1087 { 1088 union ionic_notifyq_comp *comp = cq_info->cq_desc; 1089 struct ionic_deferred_work *work; 1090 struct net_device *netdev; 1091 struct ionic_queue *q; 1092 struct ionic_lif *lif; 1093 u64 eid; 1094 1095 q = cq->bound_q; 1096 lif = q->info[0].cb_arg; 1097 netdev = lif->netdev; 1098 eid = le64_to_cpu(comp->event.eid); 1099 1100 /* Have we run out of new completions to process? */ 1101 if ((s64)(eid - lif->last_eid) <= 0) 1102 return false; 1103 1104 lif->last_eid = eid; 1105 1106 dev_dbg(lif->ionic->dev, "notifyq event:\n"); 1107 dynamic_hex_dump("event ", DUMP_PREFIX_OFFSET, 16, 1, 1108 comp, sizeof(*comp), true); 1109 1110 switch (le16_to_cpu(comp->event.ecode)) { 1111 case IONIC_EVENT_LINK_CHANGE: 1112 ionic_link_status_check_request(lif, CAN_NOT_SLEEP); 1113 break; 1114 case IONIC_EVENT_RESET: 1115 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1116 if (!work) { 1117 netdev_err(lif->netdev, "Reset event dropped\n"); 1118 } else { 1119 work->type = IONIC_DW_TYPE_LIF_RESET; 1120 ionic_lif_deferred_enqueue(&lif->deferred, work); 1121 } 1122 break; 1123 default: 1124 netdev_warn(netdev, "Notifyq event ecode=%d eid=%lld\n", 1125 comp->event.ecode, eid); 1126 break; 1127 } 1128 1129 return true; 1130 } 1131 1132 static bool ionic_adminq_service(struct ionic_cq *cq, 1133 struct ionic_cq_info *cq_info) 1134 { 1135 struct ionic_admin_comp *comp = cq_info->cq_desc; 1136 1137 if (!color_match(comp->color, cq->done_color)) 1138 return false; 1139 1140 ionic_q_service(cq->bound_q, cq_info, le16_to_cpu(comp->comp_index)); 1141 1142 return true; 1143 } 1144 1145 static int ionic_adminq_napi(struct napi_struct *napi, int budget) 1146 { 1147 struct ionic_intr_info *intr = napi_to_cq(napi)->bound_intr; 1148 struct ionic_lif *lif = napi_to_cq(napi)->lif; 1149 struct ionic_dev *idev = &lif->ionic->idev; 1150 unsigned long irqflags; 1151 unsigned int flags = 0; 1152 int rx_work = 0; 1153 int tx_work = 0; 1154 int n_work = 0; 1155 int a_work = 0; 1156 int work_done; 1157 int credits; 1158 1159 if (lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED) 1160 n_work = ionic_cq_service(&lif->notifyqcq->cq, budget, 1161 ionic_notifyq_service, NULL, NULL); 1162 1163 spin_lock_irqsave(&lif->adminq_lock, irqflags); 1164 if (lif->adminqcq && lif->adminqcq->flags & IONIC_QCQ_F_INITED) 1165 a_work = ionic_cq_service(&lif->adminqcq->cq, budget, 1166 ionic_adminq_service, NULL, NULL); 1167 spin_unlock_irqrestore(&lif->adminq_lock, irqflags); 1168 1169 if (lif->hwstamp_rxq) 1170 rx_work = ionic_cq_service(&lif->hwstamp_rxq->cq, budget, 1171 ionic_rx_service, NULL, NULL); 1172 1173 if (lif->hwstamp_txq) 1174 tx_work = ionic_cq_service(&lif->hwstamp_txq->cq, budget, 1175 ionic_tx_service, NULL, NULL); 1176 1177 work_done = max(max(n_work, a_work), max(rx_work, tx_work)); 1178 if (work_done < budget && napi_complete_done(napi, work_done)) { 1179 flags |= IONIC_INTR_CRED_UNMASK; 1180 intr->rearm_count++; 1181 } 1182 1183 if (work_done || flags) { 1184 flags |= IONIC_INTR_CRED_RESET_COALESCE; 1185 credits = n_work + a_work + rx_work + tx_work; 1186 ionic_intr_credits(idev->intr_ctrl, intr->index, credits, flags); 1187 } 1188 1189 return work_done; 1190 } 1191 1192 void ionic_get_stats64(struct net_device *netdev, 1193 struct rtnl_link_stats64 *ns) 1194 { 1195 struct ionic_lif *lif = netdev_priv(netdev); 1196 struct ionic_lif_stats *ls; 1197 1198 memset(ns, 0, sizeof(*ns)); 1199 ls = &lif->info->stats; 1200 1201 ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) + 1202 le64_to_cpu(ls->rx_mcast_packets) + 1203 le64_to_cpu(ls->rx_bcast_packets); 1204 1205 ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) + 1206 le64_to_cpu(ls->tx_mcast_packets) + 1207 le64_to_cpu(ls->tx_bcast_packets); 1208 1209 ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) + 1210 le64_to_cpu(ls->rx_mcast_bytes) + 1211 le64_to_cpu(ls->rx_bcast_bytes); 1212 1213 ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) + 1214 le64_to_cpu(ls->tx_mcast_bytes) + 1215 le64_to_cpu(ls->tx_bcast_bytes); 1216 1217 ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) + 1218 le64_to_cpu(ls->rx_mcast_drop_packets) + 1219 le64_to_cpu(ls->rx_bcast_drop_packets); 1220 1221 ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) + 1222 le64_to_cpu(ls->tx_mcast_drop_packets) + 1223 le64_to_cpu(ls->tx_bcast_drop_packets); 1224 1225 ns->multicast = le64_to_cpu(ls->rx_mcast_packets); 1226 1227 ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty); 1228 1229 ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) + 1230 le64_to_cpu(ls->rx_queue_disabled) + 1231 le64_to_cpu(ls->rx_desc_fetch_error) + 1232 le64_to_cpu(ls->rx_desc_data_error); 1233 1234 ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) + 1235 le64_to_cpu(ls->tx_queue_disabled) + 1236 le64_to_cpu(ls->tx_desc_fetch_error) + 1237 le64_to_cpu(ls->tx_desc_data_error); 1238 1239 ns->rx_errors = ns->rx_over_errors + 1240 ns->rx_missed_errors; 1241 1242 ns->tx_errors = ns->tx_aborted_errors; 1243 } 1244 1245 int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr) 1246 { 1247 struct ionic_admin_ctx ctx = { 1248 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1249 .cmd.rx_filter_add = { 1250 .opcode = IONIC_CMD_RX_FILTER_ADD, 1251 .lif_index = cpu_to_le16(lif->index), 1252 .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_MAC), 1253 }, 1254 }; 1255 int nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters); 1256 bool mc = is_multicast_ether_addr(addr); 1257 struct ionic_rx_filter *f; 1258 int err = 0; 1259 1260 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, ETH_ALEN); 1261 1262 spin_lock_bh(&lif->rx_filters.lock); 1263 f = ionic_rx_filter_by_addr(lif, addr); 1264 if (f) { 1265 /* don't bother if we already have it and it is sync'd */ 1266 if (f->state == IONIC_FILTER_STATE_SYNCED) { 1267 spin_unlock_bh(&lif->rx_filters.lock); 1268 return 0; 1269 } 1270 1271 /* mark preemptively as sync'd to block any parallel attempts */ 1272 f->state = IONIC_FILTER_STATE_SYNCED; 1273 } else { 1274 /* save as SYNCED to catch any DEL requests while processing */ 1275 err = ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx, 1276 IONIC_FILTER_STATE_SYNCED); 1277 } 1278 spin_unlock_bh(&lif->rx_filters.lock); 1279 if (err) 1280 return err; 1281 1282 netdev_dbg(lif->netdev, "rx_filter add ADDR %pM\n", addr); 1283 1284 /* Don't bother with the write to FW if we know there's no room, 1285 * we can try again on the next sync attempt. 1286 */ 1287 if ((lif->nucast + lif->nmcast) >= nfilters) 1288 err = -ENOSPC; 1289 else 1290 err = ionic_adminq_post_wait(lif, &ctx); 1291 1292 spin_lock_bh(&lif->rx_filters.lock); 1293 if (err && err != -EEXIST) { 1294 /* set the state back to NEW so we can try again later */ 1295 f = ionic_rx_filter_by_addr(lif, addr); 1296 if (f && f->state == IONIC_FILTER_STATE_SYNCED) { 1297 f->state = IONIC_FILTER_STATE_NEW; 1298 set_bit(IONIC_LIF_F_FILTER_SYNC_NEEDED, lif->state); 1299 } 1300 1301 spin_unlock_bh(&lif->rx_filters.lock); 1302 1303 if (err == -ENOSPC) 1304 return 0; 1305 else 1306 return err; 1307 } 1308 1309 if (mc) 1310 lif->nmcast++; 1311 else 1312 lif->nucast++; 1313 1314 f = ionic_rx_filter_by_addr(lif, addr); 1315 if (f && f->state == IONIC_FILTER_STATE_OLD) { 1316 /* Someone requested a delete while we were adding 1317 * so update the filter info with the results from the add 1318 * and the data will be there for the delete on the next 1319 * sync cycle. 1320 */ 1321 err = ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx, 1322 IONIC_FILTER_STATE_OLD); 1323 } else { 1324 err = ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx, 1325 IONIC_FILTER_STATE_SYNCED); 1326 } 1327 1328 spin_unlock_bh(&lif->rx_filters.lock); 1329 1330 return err; 1331 } 1332 1333 int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr) 1334 { 1335 struct ionic_admin_ctx ctx = { 1336 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1337 .cmd.rx_filter_del = { 1338 .opcode = IONIC_CMD_RX_FILTER_DEL, 1339 .lif_index = cpu_to_le16(lif->index), 1340 }, 1341 }; 1342 struct ionic_rx_filter *f; 1343 int state; 1344 int err; 1345 1346 spin_lock_bh(&lif->rx_filters.lock); 1347 f = ionic_rx_filter_by_addr(lif, addr); 1348 if (!f) { 1349 spin_unlock_bh(&lif->rx_filters.lock); 1350 return -ENOENT; 1351 } 1352 1353 netdev_dbg(lif->netdev, "rx_filter del ADDR %pM (id %d)\n", 1354 addr, f->filter_id); 1355 1356 state = f->state; 1357 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id); 1358 ionic_rx_filter_free(lif, f); 1359 1360 if (is_multicast_ether_addr(addr) && lif->nmcast) 1361 lif->nmcast--; 1362 else if (!is_multicast_ether_addr(addr) && lif->nucast) 1363 lif->nucast--; 1364 1365 spin_unlock_bh(&lif->rx_filters.lock); 1366 1367 if (state != IONIC_FILTER_STATE_NEW) { 1368 err = ionic_adminq_post_wait(lif, &ctx); 1369 if (err && err != -EEXIST) 1370 return err; 1371 } 1372 1373 return 0; 1374 } 1375 1376 static int ionic_addr_add(struct net_device *netdev, const u8 *addr) 1377 { 1378 return ionic_lif_list_addr(netdev_priv(netdev), addr, ADD_ADDR); 1379 } 1380 1381 static int ionic_addr_del(struct net_device *netdev, const u8 *addr) 1382 { 1383 return ionic_lif_list_addr(netdev_priv(netdev), addr, DEL_ADDR); 1384 } 1385 1386 void ionic_lif_rx_mode(struct ionic_lif *lif) 1387 { 1388 struct net_device *netdev = lif->netdev; 1389 unsigned int nfilters; 1390 unsigned int nd_flags; 1391 char buf[128]; 1392 u16 rx_mode; 1393 int i; 1394 #define REMAIN(__x) (sizeof(buf) - (__x)) 1395 1396 mutex_lock(&lif->config_lock); 1397 1398 /* grab the flags once for local use */ 1399 nd_flags = netdev->flags; 1400 1401 rx_mode = IONIC_RX_MODE_F_UNICAST; 1402 rx_mode |= (nd_flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0; 1403 rx_mode |= (nd_flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0; 1404 rx_mode |= (nd_flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0; 1405 rx_mode |= (nd_flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0; 1406 1407 /* sync the mac filters */ 1408 ionic_rx_filter_sync(lif); 1409 1410 /* check for overflow state 1411 * if so, we track that we overflowed and enable NIC PROMISC 1412 * else if the overflow is set and not needed 1413 * we remove our overflow flag and check the netdev flags 1414 * to see if we can disable NIC PROMISC 1415 */ 1416 nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters); 1417 if ((lif->nucast + lif->nmcast) >= nfilters) { 1418 rx_mode |= IONIC_RX_MODE_F_PROMISC; 1419 rx_mode |= IONIC_RX_MODE_F_ALLMULTI; 1420 lif->uc_overflow = true; 1421 lif->mc_overflow = true; 1422 } else if (lif->uc_overflow) { 1423 lif->uc_overflow = false; 1424 lif->mc_overflow = false; 1425 if (!(nd_flags & IFF_PROMISC)) 1426 rx_mode &= ~IONIC_RX_MODE_F_PROMISC; 1427 if (!(nd_flags & IFF_ALLMULTI)) 1428 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI; 1429 } 1430 1431 i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:", 1432 lif->rx_mode, rx_mode); 1433 if (rx_mode & IONIC_RX_MODE_F_UNICAST) 1434 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST"); 1435 if (rx_mode & IONIC_RX_MODE_F_MULTICAST) 1436 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST"); 1437 if (rx_mode & IONIC_RX_MODE_F_BROADCAST) 1438 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST"); 1439 if (rx_mode & IONIC_RX_MODE_F_PROMISC) 1440 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC"); 1441 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI) 1442 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI"); 1443 if (rx_mode & IONIC_RX_MODE_F_RDMA_SNIFFER) 1444 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_RDMA_SNIFFER"); 1445 netdev_dbg(netdev, "lif%d %s\n", lif->index, buf); 1446 1447 if (lif->rx_mode != rx_mode) { 1448 struct ionic_admin_ctx ctx = { 1449 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1450 .cmd.rx_mode_set = { 1451 .opcode = IONIC_CMD_RX_MODE_SET, 1452 .lif_index = cpu_to_le16(lif->index), 1453 }, 1454 }; 1455 int err; 1456 1457 ctx.cmd.rx_mode_set.rx_mode = cpu_to_le16(rx_mode); 1458 err = ionic_adminq_post_wait(lif, &ctx); 1459 if (err) 1460 netdev_warn(netdev, "set rx_mode 0x%04x failed: %d\n", 1461 rx_mode, err); 1462 else 1463 lif->rx_mode = rx_mode; 1464 } 1465 1466 mutex_unlock(&lif->config_lock); 1467 } 1468 1469 static void ionic_ndo_set_rx_mode(struct net_device *netdev) 1470 { 1471 struct ionic_lif *lif = netdev_priv(netdev); 1472 struct ionic_deferred_work *work; 1473 1474 /* Sync the kernel filter list with the driver filter list */ 1475 __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del); 1476 __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del); 1477 1478 /* Shove off the rest of the rxmode work to the work task 1479 * which will include syncing the filters to the firmware. 1480 */ 1481 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1482 if (!work) { 1483 netdev_err(lif->netdev, "rxmode change dropped\n"); 1484 return; 1485 } 1486 work->type = IONIC_DW_TYPE_RX_MODE; 1487 netdev_dbg(lif->netdev, "deferred: rx_mode\n"); 1488 ionic_lif_deferred_enqueue(&lif->deferred, work); 1489 } 1490 1491 static __le64 ionic_netdev_features_to_nic(netdev_features_t features) 1492 { 1493 u64 wanted = 0; 1494 1495 if (features & NETIF_F_HW_VLAN_CTAG_TX) 1496 wanted |= IONIC_ETH_HW_VLAN_TX_TAG; 1497 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1498 wanted |= IONIC_ETH_HW_VLAN_RX_STRIP; 1499 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1500 wanted |= IONIC_ETH_HW_VLAN_RX_FILTER; 1501 if (features & NETIF_F_RXHASH) 1502 wanted |= IONIC_ETH_HW_RX_HASH; 1503 if (features & NETIF_F_RXCSUM) 1504 wanted |= IONIC_ETH_HW_RX_CSUM; 1505 if (features & NETIF_F_SG) 1506 wanted |= IONIC_ETH_HW_TX_SG; 1507 if (features & NETIF_F_HW_CSUM) 1508 wanted |= IONIC_ETH_HW_TX_CSUM; 1509 if (features & NETIF_F_TSO) 1510 wanted |= IONIC_ETH_HW_TSO; 1511 if (features & NETIF_F_TSO6) 1512 wanted |= IONIC_ETH_HW_TSO_IPV6; 1513 if (features & NETIF_F_TSO_ECN) 1514 wanted |= IONIC_ETH_HW_TSO_ECN; 1515 if (features & NETIF_F_GSO_GRE) 1516 wanted |= IONIC_ETH_HW_TSO_GRE; 1517 if (features & NETIF_F_GSO_GRE_CSUM) 1518 wanted |= IONIC_ETH_HW_TSO_GRE_CSUM; 1519 if (features & NETIF_F_GSO_IPXIP4) 1520 wanted |= IONIC_ETH_HW_TSO_IPXIP4; 1521 if (features & NETIF_F_GSO_IPXIP6) 1522 wanted |= IONIC_ETH_HW_TSO_IPXIP6; 1523 if (features & NETIF_F_GSO_UDP_TUNNEL) 1524 wanted |= IONIC_ETH_HW_TSO_UDP; 1525 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) 1526 wanted |= IONIC_ETH_HW_TSO_UDP_CSUM; 1527 1528 return cpu_to_le64(wanted); 1529 } 1530 1531 static int ionic_set_nic_features(struct ionic_lif *lif, 1532 netdev_features_t features) 1533 { 1534 struct device *dev = lif->ionic->dev; 1535 struct ionic_admin_ctx ctx = { 1536 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1537 .cmd.lif_setattr = { 1538 .opcode = IONIC_CMD_LIF_SETATTR, 1539 .index = cpu_to_le16(lif->index), 1540 .attr = IONIC_LIF_ATTR_FEATURES, 1541 }, 1542 }; 1543 u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG | 1544 IONIC_ETH_HW_VLAN_RX_STRIP | 1545 IONIC_ETH_HW_VLAN_RX_FILTER; 1546 u64 old_hw_features; 1547 int err; 1548 1549 ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features); 1550 1551 if (lif->phc) 1552 ctx.cmd.lif_setattr.features |= cpu_to_le64(IONIC_ETH_HW_TIMESTAMP); 1553 1554 err = ionic_adminq_post_wait(lif, &ctx); 1555 if (err) 1556 return err; 1557 1558 old_hw_features = lif->hw_features; 1559 lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features & 1560 ctx.comp.lif_setattr.features); 1561 1562 if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH) 1563 ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1564 1565 if ((vlan_flags & features) && 1566 !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features))) 1567 dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n"); 1568 1569 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1570 dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n"); 1571 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1572 dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n"); 1573 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1574 dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n"); 1575 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1576 dev_dbg(dev, "feature ETH_HW_RX_HASH\n"); 1577 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1578 dev_dbg(dev, "feature ETH_HW_TX_SG\n"); 1579 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1580 dev_dbg(dev, "feature ETH_HW_TX_CSUM\n"); 1581 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1582 dev_dbg(dev, "feature ETH_HW_RX_CSUM\n"); 1583 if (lif->hw_features & IONIC_ETH_HW_TSO) 1584 dev_dbg(dev, "feature ETH_HW_TSO\n"); 1585 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1586 dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n"); 1587 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1588 dev_dbg(dev, "feature ETH_HW_TSO_ECN\n"); 1589 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1590 dev_dbg(dev, "feature ETH_HW_TSO_GRE\n"); 1591 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1592 dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n"); 1593 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1594 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n"); 1595 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1596 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n"); 1597 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1598 dev_dbg(dev, "feature ETH_HW_TSO_UDP\n"); 1599 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1600 dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n"); 1601 if (lif->hw_features & IONIC_ETH_HW_TIMESTAMP) 1602 dev_dbg(dev, "feature ETH_HW_TIMESTAMP\n"); 1603 1604 return 0; 1605 } 1606 1607 static int ionic_init_nic_features(struct ionic_lif *lif) 1608 { 1609 struct net_device *netdev = lif->netdev; 1610 netdev_features_t features; 1611 int err; 1612 1613 /* set up what we expect to support by default */ 1614 features = NETIF_F_HW_VLAN_CTAG_TX | 1615 NETIF_F_HW_VLAN_CTAG_RX | 1616 NETIF_F_HW_VLAN_CTAG_FILTER | 1617 NETIF_F_SG | 1618 NETIF_F_HW_CSUM | 1619 NETIF_F_RXCSUM | 1620 NETIF_F_TSO | 1621 NETIF_F_TSO6 | 1622 NETIF_F_TSO_ECN; 1623 1624 if (lif->nxqs > 1) 1625 features |= NETIF_F_RXHASH; 1626 1627 err = ionic_set_nic_features(lif, features); 1628 if (err) 1629 return err; 1630 1631 /* tell the netdev what we actually can support */ 1632 netdev->features |= NETIF_F_HIGHDMA; 1633 1634 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1635 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 1636 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1637 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 1638 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1639 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1640 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1641 netdev->hw_features |= NETIF_F_RXHASH; 1642 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1643 netdev->hw_features |= NETIF_F_SG; 1644 1645 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1646 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 1647 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1648 netdev->hw_enc_features |= NETIF_F_RXCSUM; 1649 if (lif->hw_features & IONIC_ETH_HW_TSO) 1650 netdev->hw_enc_features |= NETIF_F_TSO; 1651 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1652 netdev->hw_enc_features |= NETIF_F_TSO6; 1653 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1654 netdev->hw_enc_features |= NETIF_F_TSO_ECN; 1655 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1656 netdev->hw_enc_features |= NETIF_F_GSO_GRE; 1657 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1658 netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM; 1659 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1660 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4; 1661 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1662 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6; 1663 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1664 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL; 1665 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1666 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 1667 1668 netdev->hw_features |= netdev->hw_enc_features; 1669 netdev->features |= netdev->hw_features; 1670 netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES; 1671 1672 netdev->priv_flags |= IFF_UNICAST_FLT | 1673 IFF_LIVE_ADDR_CHANGE; 1674 1675 return 0; 1676 } 1677 1678 static int ionic_set_features(struct net_device *netdev, 1679 netdev_features_t features) 1680 { 1681 struct ionic_lif *lif = netdev_priv(netdev); 1682 int err; 1683 1684 netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n", 1685 __func__, (u64)lif->netdev->features, (u64)features); 1686 1687 err = ionic_set_nic_features(lif, features); 1688 1689 return err; 1690 } 1691 1692 static int ionic_set_mac_address(struct net_device *netdev, void *sa) 1693 { 1694 struct sockaddr *addr = sa; 1695 u8 *mac; 1696 int err; 1697 1698 mac = (u8 *)addr->sa_data; 1699 if (ether_addr_equal(netdev->dev_addr, mac)) 1700 return 0; 1701 1702 err = eth_prepare_mac_addr_change(netdev, addr); 1703 if (err) 1704 return err; 1705 1706 if (!is_zero_ether_addr(netdev->dev_addr)) { 1707 netdev_info(netdev, "deleting mac addr %pM\n", 1708 netdev->dev_addr); 1709 ionic_lif_addr_del(netdev_priv(netdev), netdev->dev_addr); 1710 } 1711 1712 eth_commit_mac_addr_change(netdev, addr); 1713 netdev_info(netdev, "updating mac addr %pM\n", mac); 1714 1715 return ionic_lif_addr_add(netdev_priv(netdev), mac); 1716 } 1717 1718 static void ionic_stop_queues_reconfig(struct ionic_lif *lif) 1719 { 1720 /* Stop and clean the queues before reconfiguration */ 1721 netif_device_detach(lif->netdev); 1722 ionic_stop_queues(lif); 1723 ionic_txrx_deinit(lif); 1724 } 1725 1726 static int ionic_start_queues_reconfig(struct ionic_lif *lif) 1727 { 1728 int err; 1729 1730 /* Re-init the queues after reconfiguration */ 1731 1732 /* The only way txrx_init can fail here is if communication 1733 * with FW is suddenly broken. There's not much we can do 1734 * at this point - error messages have already been printed, 1735 * so we can continue on and the user can eventually do a 1736 * DOWN and UP to try to reset and clear the issue. 1737 */ 1738 err = ionic_txrx_init(lif); 1739 ionic_link_status_check_request(lif, CAN_NOT_SLEEP); 1740 netif_device_attach(lif->netdev); 1741 1742 return err; 1743 } 1744 1745 static int ionic_change_mtu(struct net_device *netdev, int new_mtu) 1746 { 1747 struct ionic_lif *lif = netdev_priv(netdev); 1748 struct ionic_admin_ctx ctx = { 1749 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1750 .cmd.lif_setattr = { 1751 .opcode = IONIC_CMD_LIF_SETATTR, 1752 .index = cpu_to_le16(lif->index), 1753 .attr = IONIC_LIF_ATTR_MTU, 1754 .mtu = cpu_to_le32(new_mtu), 1755 }, 1756 }; 1757 int err; 1758 1759 err = ionic_adminq_post_wait(lif, &ctx); 1760 if (err) 1761 return err; 1762 1763 /* if we're not running, nothing more to do */ 1764 if (!netif_running(netdev)) { 1765 netdev->mtu = new_mtu; 1766 return 0; 1767 } 1768 1769 mutex_lock(&lif->queue_lock); 1770 ionic_stop_queues_reconfig(lif); 1771 netdev->mtu = new_mtu; 1772 err = ionic_start_queues_reconfig(lif); 1773 mutex_unlock(&lif->queue_lock); 1774 1775 return err; 1776 } 1777 1778 static void ionic_tx_timeout_work(struct work_struct *ws) 1779 { 1780 struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work); 1781 1782 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 1783 return; 1784 1785 /* if we were stopped before this scheduled job was launched, 1786 * don't bother the queues as they are already stopped. 1787 */ 1788 if (!netif_running(lif->netdev)) 1789 return; 1790 1791 mutex_lock(&lif->queue_lock); 1792 ionic_stop_queues_reconfig(lif); 1793 ionic_start_queues_reconfig(lif); 1794 mutex_unlock(&lif->queue_lock); 1795 } 1796 1797 static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1798 { 1799 struct ionic_lif *lif = netdev_priv(netdev); 1800 1801 netdev_info(lif->netdev, "Tx Timeout triggered - txq %d\n", txqueue); 1802 schedule_work(&lif->tx_timeout_work); 1803 } 1804 1805 static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, 1806 u16 vid) 1807 { 1808 struct ionic_lif *lif = netdev_priv(netdev); 1809 struct ionic_admin_ctx ctx = { 1810 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1811 .cmd.rx_filter_add = { 1812 .opcode = IONIC_CMD_RX_FILTER_ADD, 1813 .lif_index = cpu_to_le16(lif->index), 1814 .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_VLAN), 1815 .vlan.vlan = cpu_to_le16(vid), 1816 }, 1817 }; 1818 int err; 1819 1820 netdev_dbg(netdev, "rx_filter add VLAN %d\n", vid); 1821 err = ionic_adminq_post_wait(lif, &ctx); 1822 if (err) 1823 return err; 1824 1825 spin_lock_bh(&lif->rx_filters.lock); 1826 err = ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx, 1827 IONIC_FILTER_STATE_SYNCED); 1828 spin_unlock_bh(&lif->rx_filters.lock); 1829 1830 return err; 1831 } 1832 1833 static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, 1834 u16 vid) 1835 { 1836 struct ionic_lif *lif = netdev_priv(netdev); 1837 struct ionic_admin_ctx ctx = { 1838 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1839 .cmd.rx_filter_del = { 1840 .opcode = IONIC_CMD_RX_FILTER_DEL, 1841 .lif_index = cpu_to_le16(lif->index), 1842 }, 1843 }; 1844 struct ionic_rx_filter *f; 1845 1846 spin_lock_bh(&lif->rx_filters.lock); 1847 1848 f = ionic_rx_filter_by_vlan(lif, vid); 1849 if (!f) { 1850 spin_unlock_bh(&lif->rx_filters.lock); 1851 return -ENOENT; 1852 } 1853 1854 netdev_dbg(netdev, "rx_filter del VLAN %d (id %d)\n", 1855 vid, f->filter_id); 1856 1857 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id); 1858 ionic_rx_filter_free(lif, f); 1859 spin_unlock_bh(&lif->rx_filters.lock); 1860 1861 return ionic_adminq_post_wait(lif, &ctx); 1862 } 1863 1864 int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types, 1865 const u8 *key, const u32 *indir) 1866 { 1867 struct ionic_admin_ctx ctx = { 1868 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1869 .cmd.lif_setattr = { 1870 .opcode = IONIC_CMD_LIF_SETATTR, 1871 .attr = IONIC_LIF_ATTR_RSS, 1872 .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa), 1873 }, 1874 }; 1875 unsigned int i, tbl_sz; 1876 1877 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) { 1878 lif->rss_types = types; 1879 ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types); 1880 } 1881 1882 if (key) 1883 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE); 1884 1885 if (indir) { 1886 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1887 for (i = 0; i < tbl_sz; i++) 1888 lif->rss_ind_tbl[i] = indir[i]; 1889 } 1890 1891 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key, 1892 IONIC_RSS_HASH_KEY_SIZE); 1893 1894 return ionic_adminq_post_wait(lif, &ctx); 1895 } 1896 1897 static int ionic_lif_rss_init(struct ionic_lif *lif) 1898 { 1899 unsigned int tbl_sz; 1900 unsigned int i; 1901 1902 lif->rss_types = IONIC_RSS_TYPE_IPV4 | 1903 IONIC_RSS_TYPE_IPV4_TCP | 1904 IONIC_RSS_TYPE_IPV4_UDP | 1905 IONIC_RSS_TYPE_IPV6 | 1906 IONIC_RSS_TYPE_IPV6_TCP | 1907 IONIC_RSS_TYPE_IPV6_UDP; 1908 1909 /* Fill indirection table with 'default' values */ 1910 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1911 for (i = 0; i < tbl_sz; i++) 1912 lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs); 1913 1914 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1915 } 1916 1917 static void ionic_lif_rss_deinit(struct ionic_lif *lif) 1918 { 1919 int tbl_sz; 1920 1921 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1922 memset(lif->rss_ind_tbl, 0, tbl_sz); 1923 memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE); 1924 1925 ionic_lif_rss_config(lif, 0x0, NULL, NULL); 1926 } 1927 1928 static void ionic_lif_quiesce(struct ionic_lif *lif) 1929 { 1930 struct ionic_admin_ctx ctx = { 1931 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1932 .cmd.lif_setattr = { 1933 .opcode = IONIC_CMD_LIF_SETATTR, 1934 .index = cpu_to_le16(lif->index), 1935 .attr = IONIC_LIF_ATTR_STATE, 1936 .state = IONIC_LIF_QUIESCE, 1937 }, 1938 }; 1939 int err; 1940 1941 err = ionic_adminq_post_wait(lif, &ctx); 1942 if (err) 1943 netdev_err(lif->netdev, "lif quiesce failed %d\n", err); 1944 } 1945 1946 static void ionic_txrx_disable(struct ionic_lif *lif) 1947 { 1948 unsigned int i; 1949 int err = 0; 1950 1951 if (lif->txqcqs) { 1952 for (i = 0; i < lif->nxqs; i++) 1953 err = ionic_qcq_disable(lif, lif->txqcqs[i], err); 1954 } 1955 1956 if (lif->hwstamp_txq) 1957 err = ionic_qcq_disable(lif, lif->hwstamp_txq, err); 1958 1959 if (lif->rxqcqs) { 1960 for (i = 0; i < lif->nxqs; i++) 1961 err = ionic_qcq_disable(lif, lif->rxqcqs[i], err); 1962 } 1963 1964 if (lif->hwstamp_rxq) 1965 err = ionic_qcq_disable(lif, lif->hwstamp_rxq, err); 1966 1967 ionic_lif_quiesce(lif); 1968 } 1969 1970 static void ionic_txrx_deinit(struct ionic_lif *lif) 1971 { 1972 unsigned int i; 1973 1974 if (lif->txqcqs) { 1975 for (i = 0; i < lif->nxqs && lif->txqcqs[i]; i++) { 1976 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 1977 ionic_tx_flush(&lif->txqcqs[i]->cq); 1978 ionic_tx_empty(&lif->txqcqs[i]->q); 1979 } 1980 } 1981 1982 if (lif->rxqcqs) { 1983 for (i = 0; i < lif->nxqs && lif->rxqcqs[i]; i++) { 1984 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 1985 ionic_rx_empty(&lif->rxqcqs[i]->q); 1986 } 1987 } 1988 lif->rx_mode = 0; 1989 1990 if (lif->hwstamp_txq) { 1991 ionic_lif_qcq_deinit(lif, lif->hwstamp_txq); 1992 ionic_tx_flush(&lif->hwstamp_txq->cq); 1993 ionic_tx_empty(&lif->hwstamp_txq->q); 1994 } 1995 1996 if (lif->hwstamp_rxq) { 1997 ionic_lif_qcq_deinit(lif, lif->hwstamp_rxq); 1998 ionic_rx_empty(&lif->hwstamp_rxq->q); 1999 } 2000 } 2001 2002 static void ionic_txrx_free(struct ionic_lif *lif) 2003 { 2004 unsigned int i; 2005 2006 if (lif->txqcqs) { 2007 for (i = 0; i < lif->ionic->ntxqs_per_lif && lif->txqcqs[i]; i++) { 2008 ionic_qcq_free(lif, lif->txqcqs[i]); 2009 devm_kfree(lif->ionic->dev, lif->txqcqs[i]); 2010 lif->txqcqs[i] = NULL; 2011 } 2012 } 2013 2014 if (lif->rxqcqs) { 2015 for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) { 2016 ionic_qcq_free(lif, lif->rxqcqs[i]); 2017 devm_kfree(lif->ionic->dev, lif->rxqcqs[i]); 2018 lif->rxqcqs[i] = NULL; 2019 } 2020 } 2021 2022 if (lif->hwstamp_txq) { 2023 ionic_qcq_free(lif, lif->hwstamp_txq); 2024 devm_kfree(lif->ionic->dev, lif->hwstamp_txq); 2025 lif->hwstamp_txq = NULL; 2026 } 2027 2028 if (lif->hwstamp_rxq) { 2029 ionic_qcq_free(lif, lif->hwstamp_rxq); 2030 devm_kfree(lif->ionic->dev, lif->hwstamp_rxq); 2031 lif->hwstamp_rxq = NULL; 2032 } 2033 } 2034 2035 static int ionic_txrx_alloc(struct ionic_lif *lif) 2036 { 2037 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz; 2038 unsigned int flags, i; 2039 int err = 0; 2040 2041 num_desc = lif->ntxq_descs; 2042 desc_sz = sizeof(struct ionic_txq_desc); 2043 comp_sz = sizeof(struct ionic_txq_comp); 2044 2045 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 2046 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 2047 sizeof(struct ionic_txq_sg_desc_v1)) 2048 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 2049 else 2050 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 2051 2052 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 2053 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 2054 flags |= IONIC_QCQ_F_INTR; 2055 for (i = 0; i < lif->nxqs; i++) { 2056 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 2057 num_desc, desc_sz, comp_sz, sg_desc_sz, 2058 lif->kern_pid, &lif->txqcqs[i]); 2059 if (err) 2060 goto err_out; 2061 2062 if (flags & IONIC_QCQ_F_INTR) { 2063 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2064 lif->txqcqs[i]->intr.index, 2065 lif->tx_coalesce_hw); 2066 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 2067 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 2068 } 2069 2070 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 2071 } 2072 2073 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG | IONIC_QCQ_F_INTR; 2074 2075 num_desc = lif->nrxq_descs; 2076 desc_sz = sizeof(struct ionic_rxq_desc); 2077 comp_sz = sizeof(struct ionic_rxq_comp); 2078 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 2079 2080 if (lif->rxq_features & IONIC_Q_F_2X_CQ_DESC) 2081 comp_sz *= 2; 2082 2083 for (i = 0; i < lif->nxqs; i++) { 2084 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 2085 num_desc, desc_sz, comp_sz, sg_desc_sz, 2086 lif->kern_pid, &lif->rxqcqs[i]); 2087 if (err) 2088 goto err_out; 2089 2090 lif->rxqcqs[i]->q.features = lif->rxq_features; 2091 2092 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2093 lif->rxqcqs[i]->intr.index, 2094 lif->rx_coalesce_hw); 2095 if (test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state)) 2096 lif->rxqcqs[i]->intr.dim_coal_hw = lif->rx_coalesce_hw; 2097 2098 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 2099 ionic_link_qcq_interrupts(lif->rxqcqs[i], 2100 lif->txqcqs[i]); 2101 2102 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 2103 } 2104 2105 return 0; 2106 2107 err_out: 2108 ionic_txrx_free(lif); 2109 2110 return err; 2111 } 2112 2113 static int ionic_txrx_init(struct ionic_lif *lif) 2114 { 2115 unsigned int i; 2116 int err; 2117 2118 for (i = 0; i < lif->nxqs; i++) { 2119 err = ionic_lif_txq_init(lif, lif->txqcqs[i]); 2120 if (err) 2121 goto err_out; 2122 2123 err = ionic_lif_rxq_init(lif, lif->rxqcqs[i]); 2124 if (err) { 2125 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 2126 goto err_out; 2127 } 2128 } 2129 2130 if (lif->netdev->features & NETIF_F_RXHASH) 2131 ionic_lif_rss_init(lif); 2132 2133 ionic_lif_rx_mode(lif); 2134 2135 return 0; 2136 2137 err_out: 2138 while (i--) { 2139 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 2140 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 2141 } 2142 2143 return err; 2144 } 2145 2146 static int ionic_txrx_enable(struct ionic_lif *lif) 2147 { 2148 int derr = 0; 2149 int i, err; 2150 2151 for (i = 0; i < lif->nxqs; i++) { 2152 if (!(lif->rxqcqs[i] && lif->txqcqs[i])) { 2153 dev_err(lif->ionic->dev, "%s: bad qcq %d\n", __func__, i); 2154 err = -ENXIO; 2155 goto err_out; 2156 } 2157 2158 ionic_rx_fill(&lif->rxqcqs[i]->q); 2159 err = ionic_qcq_enable(lif->rxqcqs[i]); 2160 if (err) 2161 goto err_out; 2162 2163 err = ionic_qcq_enable(lif->txqcqs[i]); 2164 if (err) { 2165 derr = ionic_qcq_disable(lif, lif->rxqcqs[i], err); 2166 goto err_out; 2167 } 2168 } 2169 2170 if (lif->hwstamp_rxq) { 2171 ionic_rx_fill(&lif->hwstamp_rxq->q); 2172 err = ionic_qcq_enable(lif->hwstamp_rxq); 2173 if (err) 2174 goto err_out_hwstamp_rx; 2175 } 2176 2177 if (lif->hwstamp_txq) { 2178 err = ionic_qcq_enable(lif->hwstamp_txq); 2179 if (err) 2180 goto err_out_hwstamp_tx; 2181 } 2182 2183 return 0; 2184 2185 err_out_hwstamp_tx: 2186 if (lif->hwstamp_rxq) 2187 derr = ionic_qcq_disable(lif, lif->hwstamp_rxq, derr); 2188 err_out_hwstamp_rx: 2189 i = lif->nxqs; 2190 err_out: 2191 while (i--) { 2192 derr = ionic_qcq_disable(lif, lif->txqcqs[i], derr); 2193 derr = ionic_qcq_disable(lif, lif->rxqcqs[i], derr); 2194 } 2195 2196 return err; 2197 } 2198 2199 static int ionic_start_queues(struct ionic_lif *lif) 2200 { 2201 int err; 2202 2203 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) 2204 return -EIO; 2205 2206 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2207 return -EBUSY; 2208 2209 if (test_and_set_bit(IONIC_LIF_F_UP, lif->state)) 2210 return 0; 2211 2212 err = ionic_txrx_enable(lif); 2213 if (err) { 2214 clear_bit(IONIC_LIF_F_UP, lif->state); 2215 return err; 2216 } 2217 netif_tx_wake_all_queues(lif->netdev); 2218 2219 return 0; 2220 } 2221 2222 static int ionic_open(struct net_device *netdev) 2223 { 2224 struct ionic_lif *lif = netdev_priv(netdev); 2225 int err; 2226 2227 /* If recovering from a broken state, clear the bit and we'll try again */ 2228 if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state)) 2229 netdev_info(netdev, "clearing broken state\n"); 2230 2231 mutex_lock(&lif->queue_lock); 2232 2233 err = ionic_txrx_alloc(lif); 2234 if (err) 2235 goto err_unlock; 2236 2237 err = ionic_txrx_init(lif); 2238 if (err) 2239 goto err_txrx_free; 2240 2241 err = netif_set_real_num_tx_queues(netdev, lif->nxqs); 2242 if (err) 2243 goto err_txrx_deinit; 2244 2245 err = netif_set_real_num_rx_queues(netdev, lif->nxqs); 2246 if (err) 2247 goto err_txrx_deinit; 2248 2249 /* don't start the queues until we have link */ 2250 if (netif_carrier_ok(netdev)) { 2251 err = ionic_start_queues(lif); 2252 if (err) 2253 goto err_txrx_deinit; 2254 } 2255 2256 /* If hardware timestamping is enabled, but the queues were freed by 2257 * ionic_stop, those need to be reallocated and initialized, too. 2258 */ 2259 ionic_lif_hwstamp_recreate_queues(lif); 2260 2261 mutex_unlock(&lif->queue_lock); 2262 2263 return 0; 2264 2265 err_txrx_deinit: 2266 ionic_txrx_deinit(lif); 2267 err_txrx_free: 2268 ionic_txrx_free(lif); 2269 err_unlock: 2270 mutex_unlock(&lif->queue_lock); 2271 return err; 2272 } 2273 2274 static void ionic_stop_queues(struct ionic_lif *lif) 2275 { 2276 if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state)) 2277 return; 2278 2279 netif_tx_disable(lif->netdev); 2280 ionic_txrx_disable(lif); 2281 } 2282 2283 static int ionic_stop(struct net_device *netdev) 2284 { 2285 struct ionic_lif *lif = netdev_priv(netdev); 2286 2287 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2288 return 0; 2289 2290 mutex_lock(&lif->queue_lock); 2291 ionic_stop_queues(lif); 2292 ionic_txrx_deinit(lif); 2293 ionic_txrx_free(lif); 2294 mutex_unlock(&lif->queue_lock); 2295 2296 return 0; 2297 } 2298 2299 static int ionic_eth_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 2300 { 2301 struct ionic_lif *lif = netdev_priv(netdev); 2302 2303 switch (cmd) { 2304 case SIOCSHWTSTAMP: 2305 return ionic_lif_hwstamp_set(lif, ifr); 2306 case SIOCGHWTSTAMP: 2307 return ionic_lif_hwstamp_get(lif, ifr); 2308 default: 2309 return -EOPNOTSUPP; 2310 } 2311 } 2312 2313 static int ionic_get_vf_config(struct net_device *netdev, 2314 int vf, struct ifla_vf_info *ivf) 2315 { 2316 struct ionic_lif *lif = netdev_priv(netdev); 2317 struct ionic *ionic = lif->ionic; 2318 int ret = 0; 2319 2320 if (!netif_device_present(netdev)) 2321 return -EBUSY; 2322 2323 down_read(&ionic->vf_op_lock); 2324 2325 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2326 ret = -EINVAL; 2327 } else { 2328 ivf->vf = vf; 2329 ivf->vlan = le16_to_cpu(ionic->vfs[vf].vlanid); 2330 ivf->qos = 0; 2331 ivf->spoofchk = ionic->vfs[vf].spoofchk; 2332 ivf->linkstate = ionic->vfs[vf].linkstate; 2333 ivf->max_tx_rate = le32_to_cpu(ionic->vfs[vf].maxrate); 2334 ivf->trusted = ionic->vfs[vf].trusted; 2335 ether_addr_copy(ivf->mac, ionic->vfs[vf].macaddr); 2336 } 2337 2338 up_read(&ionic->vf_op_lock); 2339 return ret; 2340 } 2341 2342 static int ionic_get_vf_stats(struct net_device *netdev, int vf, 2343 struct ifla_vf_stats *vf_stats) 2344 { 2345 struct ionic_lif *lif = netdev_priv(netdev); 2346 struct ionic *ionic = lif->ionic; 2347 struct ionic_lif_stats *vs; 2348 int ret = 0; 2349 2350 if (!netif_device_present(netdev)) 2351 return -EBUSY; 2352 2353 down_read(&ionic->vf_op_lock); 2354 2355 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2356 ret = -EINVAL; 2357 } else { 2358 memset(vf_stats, 0, sizeof(*vf_stats)); 2359 vs = &ionic->vfs[vf].stats; 2360 2361 vf_stats->rx_packets = le64_to_cpu(vs->rx_ucast_packets); 2362 vf_stats->tx_packets = le64_to_cpu(vs->tx_ucast_packets); 2363 vf_stats->rx_bytes = le64_to_cpu(vs->rx_ucast_bytes); 2364 vf_stats->tx_bytes = le64_to_cpu(vs->tx_ucast_bytes); 2365 vf_stats->broadcast = le64_to_cpu(vs->rx_bcast_packets); 2366 vf_stats->multicast = le64_to_cpu(vs->rx_mcast_packets); 2367 vf_stats->rx_dropped = le64_to_cpu(vs->rx_ucast_drop_packets) + 2368 le64_to_cpu(vs->rx_mcast_drop_packets) + 2369 le64_to_cpu(vs->rx_bcast_drop_packets); 2370 vf_stats->tx_dropped = le64_to_cpu(vs->tx_ucast_drop_packets) + 2371 le64_to_cpu(vs->tx_mcast_drop_packets) + 2372 le64_to_cpu(vs->tx_bcast_drop_packets); 2373 } 2374 2375 up_read(&ionic->vf_op_lock); 2376 return ret; 2377 } 2378 2379 static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2380 { 2381 struct ionic_lif *lif = netdev_priv(netdev); 2382 struct ionic *ionic = lif->ionic; 2383 int ret; 2384 2385 if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac))) 2386 return -EINVAL; 2387 2388 if (!netif_device_present(netdev)) 2389 return -EBUSY; 2390 2391 down_write(&ionic->vf_op_lock); 2392 2393 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2394 ret = -EINVAL; 2395 } else { 2396 ret = ionic_set_vf_config(ionic, vf, IONIC_VF_ATTR_MAC, mac); 2397 if (!ret) 2398 ether_addr_copy(ionic->vfs[vf].macaddr, mac); 2399 } 2400 2401 up_write(&ionic->vf_op_lock); 2402 return ret; 2403 } 2404 2405 static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 2406 u8 qos, __be16 proto) 2407 { 2408 struct ionic_lif *lif = netdev_priv(netdev); 2409 struct ionic *ionic = lif->ionic; 2410 int ret; 2411 2412 /* until someday when we support qos */ 2413 if (qos) 2414 return -EINVAL; 2415 2416 if (vlan > 4095) 2417 return -EINVAL; 2418 2419 if (proto != htons(ETH_P_8021Q)) 2420 return -EPROTONOSUPPORT; 2421 2422 if (!netif_device_present(netdev)) 2423 return -EBUSY; 2424 2425 down_write(&ionic->vf_op_lock); 2426 2427 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2428 ret = -EINVAL; 2429 } else { 2430 ret = ionic_set_vf_config(ionic, vf, 2431 IONIC_VF_ATTR_VLAN, (u8 *)&vlan); 2432 if (!ret) 2433 ionic->vfs[vf].vlanid = cpu_to_le16(vlan); 2434 } 2435 2436 up_write(&ionic->vf_op_lock); 2437 return ret; 2438 } 2439 2440 static int ionic_set_vf_rate(struct net_device *netdev, int vf, 2441 int tx_min, int tx_max) 2442 { 2443 struct ionic_lif *lif = netdev_priv(netdev); 2444 struct ionic *ionic = lif->ionic; 2445 int ret; 2446 2447 /* setting the min just seems silly */ 2448 if (tx_min) 2449 return -EINVAL; 2450 2451 if (!netif_device_present(netdev)) 2452 return -EBUSY; 2453 2454 down_write(&ionic->vf_op_lock); 2455 2456 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2457 ret = -EINVAL; 2458 } else { 2459 ret = ionic_set_vf_config(ionic, vf, 2460 IONIC_VF_ATTR_RATE, (u8 *)&tx_max); 2461 if (!ret) 2462 lif->ionic->vfs[vf].maxrate = cpu_to_le32(tx_max); 2463 } 2464 2465 up_write(&ionic->vf_op_lock); 2466 return ret; 2467 } 2468 2469 static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set) 2470 { 2471 struct ionic_lif *lif = netdev_priv(netdev); 2472 struct ionic *ionic = lif->ionic; 2473 u8 data = set; /* convert to u8 for config */ 2474 int ret; 2475 2476 if (!netif_device_present(netdev)) 2477 return -EBUSY; 2478 2479 down_write(&ionic->vf_op_lock); 2480 2481 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2482 ret = -EINVAL; 2483 } else { 2484 ret = ionic_set_vf_config(ionic, vf, 2485 IONIC_VF_ATTR_SPOOFCHK, &data); 2486 if (!ret) 2487 ionic->vfs[vf].spoofchk = data; 2488 } 2489 2490 up_write(&ionic->vf_op_lock); 2491 return ret; 2492 } 2493 2494 static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set) 2495 { 2496 struct ionic_lif *lif = netdev_priv(netdev); 2497 struct ionic *ionic = lif->ionic; 2498 u8 data = set; /* convert to u8 for config */ 2499 int ret; 2500 2501 if (!netif_device_present(netdev)) 2502 return -EBUSY; 2503 2504 down_write(&ionic->vf_op_lock); 2505 2506 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2507 ret = -EINVAL; 2508 } else { 2509 ret = ionic_set_vf_config(ionic, vf, 2510 IONIC_VF_ATTR_TRUST, &data); 2511 if (!ret) 2512 ionic->vfs[vf].trusted = data; 2513 } 2514 2515 up_write(&ionic->vf_op_lock); 2516 return ret; 2517 } 2518 2519 static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set) 2520 { 2521 struct ionic_lif *lif = netdev_priv(netdev); 2522 struct ionic *ionic = lif->ionic; 2523 u8 data; 2524 int ret; 2525 2526 switch (set) { 2527 case IFLA_VF_LINK_STATE_ENABLE: 2528 data = IONIC_VF_LINK_STATUS_UP; 2529 break; 2530 case IFLA_VF_LINK_STATE_DISABLE: 2531 data = IONIC_VF_LINK_STATUS_DOWN; 2532 break; 2533 case IFLA_VF_LINK_STATE_AUTO: 2534 data = IONIC_VF_LINK_STATUS_AUTO; 2535 break; 2536 default: 2537 return -EINVAL; 2538 } 2539 2540 if (!netif_device_present(netdev)) 2541 return -EBUSY; 2542 2543 down_write(&ionic->vf_op_lock); 2544 2545 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2546 ret = -EINVAL; 2547 } else { 2548 ret = ionic_set_vf_config(ionic, vf, 2549 IONIC_VF_ATTR_LINKSTATE, &data); 2550 if (!ret) 2551 ionic->vfs[vf].linkstate = set; 2552 } 2553 2554 up_write(&ionic->vf_op_lock); 2555 return ret; 2556 } 2557 2558 static const struct net_device_ops ionic_netdev_ops = { 2559 .ndo_open = ionic_open, 2560 .ndo_stop = ionic_stop, 2561 .ndo_eth_ioctl = ionic_eth_ioctl, 2562 .ndo_start_xmit = ionic_start_xmit, 2563 .ndo_get_stats64 = ionic_get_stats64, 2564 .ndo_set_rx_mode = ionic_ndo_set_rx_mode, 2565 .ndo_set_features = ionic_set_features, 2566 .ndo_set_mac_address = ionic_set_mac_address, 2567 .ndo_validate_addr = eth_validate_addr, 2568 .ndo_tx_timeout = ionic_tx_timeout, 2569 .ndo_change_mtu = ionic_change_mtu, 2570 .ndo_vlan_rx_add_vid = ionic_vlan_rx_add_vid, 2571 .ndo_vlan_rx_kill_vid = ionic_vlan_rx_kill_vid, 2572 .ndo_set_vf_vlan = ionic_set_vf_vlan, 2573 .ndo_set_vf_trust = ionic_set_vf_trust, 2574 .ndo_set_vf_mac = ionic_set_vf_mac, 2575 .ndo_set_vf_rate = ionic_set_vf_rate, 2576 .ndo_set_vf_spoofchk = ionic_set_vf_spoofchk, 2577 .ndo_get_vf_config = ionic_get_vf_config, 2578 .ndo_set_vf_link_state = ionic_set_vf_link_state, 2579 .ndo_get_vf_stats = ionic_get_vf_stats, 2580 }; 2581 2582 static void ionic_swap_queues(struct ionic_qcq *a, struct ionic_qcq *b) 2583 { 2584 /* only swapping the queues, not the napi, flags, or other stuff */ 2585 swap(a->q.features, b->q.features); 2586 swap(a->q.num_descs, b->q.num_descs); 2587 swap(a->q.desc_size, b->q.desc_size); 2588 swap(a->q.base, b->q.base); 2589 swap(a->q.base_pa, b->q.base_pa); 2590 swap(a->q.info, b->q.info); 2591 swap(a->q_base, b->q_base); 2592 swap(a->q_base_pa, b->q_base_pa); 2593 swap(a->q_size, b->q_size); 2594 2595 swap(a->q.sg_desc_size, b->q.sg_desc_size); 2596 swap(a->q.sg_base, b->q.sg_base); 2597 swap(a->q.sg_base_pa, b->q.sg_base_pa); 2598 swap(a->sg_base, b->sg_base); 2599 swap(a->sg_base_pa, b->sg_base_pa); 2600 swap(a->sg_size, b->sg_size); 2601 2602 swap(a->cq.num_descs, b->cq.num_descs); 2603 swap(a->cq.desc_size, b->cq.desc_size); 2604 swap(a->cq.base, b->cq.base); 2605 swap(a->cq.base_pa, b->cq.base_pa); 2606 swap(a->cq.info, b->cq.info); 2607 swap(a->cq_base, b->cq_base); 2608 swap(a->cq_base_pa, b->cq_base_pa); 2609 swap(a->cq_size, b->cq_size); 2610 2611 ionic_debugfs_del_qcq(a); 2612 ionic_debugfs_add_qcq(a->q.lif, a); 2613 } 2614 2615 int ionic_reconfigure_queues(struct ionic_lif *lif, 2616 struct ionic_queue_params *qparam) 2617 { 2618 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz; 2619 struct ionic_qcq **tx_qcqs = NULL; 2620 struct ionic_qcq **rx_qcqs = NULL; 2621 unsigned int flags, i; 2622 int err = 0; 2623 2624 /* allocate temporary qcq arrays to hold new queue structs */ 2625 if (qparam->nxqs != lif->nxqs || qparam->ntxq_descs != lif->ntxq_descs) { 2626 tx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->ntxqs_per_lif, 2627 sizeof(struct ionic_qcq *), GFP_KERNEL); 2628 if (!tx_qcqs) { 2629 err = -ENOMEM; 2630 goto err_out; 2631 } 2632 } 2633 if (qparam->nxqs != lif->nxqs || 2634 qparam->nrxq_descs != lif->nrxq_descs || 2635 qparam->rxq_features != lif->rxq_features) { 2636 rx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->nrxqs_per_lif, 2637 sizeof(struct ionic_qcq *), GFP_KERNEL); 2638 if (!rx_qcqs) { 2639 err = -ENOMEM; 2640 goto err_out; 2641 } 2642 } 2643 2644 /* allocate new desc_info and rings, but leave the interrupt setup 2645 * until later so as to not mess with the still-running queues 2646 */ 2647 if (tx_qcqs) { 2648 num_desc = qparam->ntxq_descs; 2649 desc_sz = sizeof(struct ionic_txq_desc); 2650 comp_sz = sizeof(struct ionic_txq_comp); 2651 2652 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 2653 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 2654 sizeof(struct ionic_txq_sg_desc_v1)) 2655 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 2656 else 2657 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 2658 2659 for (i = 0; i < qparam->nxqs; i++) { 2660 flags = lif->txqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2661 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 2662 num_desc, desc_sz, comp_sz, sg_desc_sz, 2663 lif->kern_pid, &tx_qcqs[i]); 2664 if (err) 2665 goto err_out; 2666 } 2667 } 2668 2669 if (rx_qcqs) { 2670 num_desc = qparam->nrxq_descs; 2671 desc_sz = sizeof(struct ionic_rxq_desc); 2672 comp_sz = sizeof(struct ionic_rxq_comp); 2673 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 2674 2675 if (qparam->rxq_features & IONIC_Q_F_2X_CQ_DESC) 2676 comp_sz *= 2; 2677 2678 for (i = 0; i < qparam->nxqs; i++) { 2679 flags = lif->rxqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2680 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 2681 num_desc, desc_sz, comp_sz, sg_desc_sz, 2682 lif->kern_pid, &rx_qcqs[i]); 2683 if (err) 2684 goto err_out; 2685 2686 rx_qcqs[i]->q.features = qparam->rxq_features; 2687 } 2688 } 2689 2690 /* stop and clean the queues */ 2691 ionic_stop_queues_reconfig(lif); 2692 2693 if (qparam->nxqs != lif->nxqs) { 2694 err = netif_set_real_num_tx_queues(lif->netdev, qparam->nxqs); 2695 if (err) 2696 goto err_out_reinit_unlock; 2697 err = netif_set_real_num_rx_queues(lif->netdev, qparam->nxqs); 2698 if (err) { 2699 netif_set_real_num_tx_queues(lif->netdev, lif->nxqs); 2700 goto err_out_reinit_unlock; 2701 } 2702 } 2703 2704 /* swap new desc_info and rings, keeping existing interrupt config */ 2705 if (tx_qcqs) { 2706 lif->ntxq_descs = qparam->ntxq_descs; 2707 for (i = 0; i < qparam->nxqs; i++) 2708 ionic_swap_queues(lif->txqcqs[i], tx_qcqs[i]); 2709 } 2710 2711 if (rx_qcqs) { 2712 lif->nrxq_descs = qparam->nrxq_descs; 2713 for (i = 0; i < qparam->nxqs; i++) 2714 ionic_swap_queues(lif->rxqcqs[i], rx_qcqs[i]); 2715 } 2716 2717 /* if we need to change the interrupt layout, this is the time */ 2718 if (qparam->intr_split != test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) || 2719 qparam->nxqs != lif->nxqs) { 2720 if (qparam->intr_split) { 2721 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 2722 } else { 2723 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 2724 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 2725 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 2726 } 2727 2728 /* clear existing interrupt assignments */ 2729 for (i = 0; i < lif->ionic->ntxqs_per_lif; i++) { 2730 ionic_qcq_intr_free(lif, lif->txqcqs[i]); 2731 ionic_qcq_intr_free(lif, lif->rxqcqs[i]); 2732 } 2733 2734 /* re-assign the interrupts */ 2735 for (i = 0; i < qparam->nxqs; i++) { 2736 lif->rxqcqs[i]->flags |= IONIC_QCQ_F_INTR; 2737 err = ionic_alloc_qcq_interrupt(lif, lif->rxqcqs[i]); 2738 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2739 lif->rxqcqs[i]->intr.index, 2740 lif->rx_coalesce_hw); 2741 2742 if (qparam->intr_split) { 2743 lif->txqcqs[i]->flags |= IONIC_QCQ_F_INTR; 2744 err = ionic_alloc_qcq_interrupt(lif, lif->txqcqs[i]); 2745 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2746 lif->txqcqs[i]->intr.index, 2747 lif->tx_coalesce_hw); 2748 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 2749 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 2750 } else { 2751 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2752 ionic_link_qcq_interrupts(lif->rxqcqs[i], lif->txqcqs[i]); 2753 } 2754 } 2755 } 2756 2757 /* now we can rework the debugfs mappings */ 2758 if (tx_qcqs) { 2759 for (i = 0; i < qparam->nxqs; i++) { 2760 ionic_debugfs_del_qcq(lif->txqcqs[i]); 2761 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 2762 } 2763 } 2764 2765 if (rx_qcqs) { 2766 for (i = 0; i < qparam->nxqs; i++) { 2767 ionic_debugfs_del_qcq(lif->rxqcqs[i]); 2768 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 2769 } 2770 } 2771 2772 swap(lif->nxqs, qparam->nxqs); 2773 swap(lif->rxq_features, qparam->rxq_features); 2774 2775 err_out_reinit_unlock: 2776 /* re-init the queues, but don't lose an error code */ 2777 if (err) 2778 ionic_start_queues_reconfig(lif); 2779 else 2780 err = ionic_start_queues_reconfig(lif); 2781 2782 err_out: 2783 /* free old allocs without cleaning intr */ 2784 for (i = 0; i < qparam->nxqs; i++) { 2785 if (tx_qcqs && tx_qcqs[i]) { 2786 tx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2787 ionic_qcq_free(lif, tx_qcqs[i]); 2788 devm_kfree(lif->ionic->dev, tx_qcqs[i]); 2789 tx_qcqs[i] = NULL; 2790 } 2791 if (rx_qcqs && rx_qcqs[i]) { 2792 rx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2793 ionic_qcq_free(lif, rx_qcqs[i]); 2794 devm_kfree(lif->ionic->dev, rx_qcqs[i]); 2795 rx_qcqs[i] = NULL; 2796 } 2797 } 2798 2799 /* free q array */ 2800 if (rx_qcqs) { 2801 devm_kfree(lif->ionic->dev, rx_qcqs); 2802 rx_qcqs = NULL; 2803 } 2804 if (tx_qcqs) { 2805 devm_kfree(lif->ionic->dev, tx_qcqs); 2806 tx_qcqs = NULL; 2807 } 2808 2809 /* clean the unused dma and info allocations when new set is smaller 2810 * than the full array, but leave the qcq shells in place 2811 */ 2812 for (i = lif->nxqs; i < lif->ionic->ntxqs_per_lif; i++) { 2813 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2814 ionic_qcq_free(lif, lif->txqcqs[i]); 2815 2816 lif->rxqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2817 ionic_qcq_free(lif, lif->rxqcqs[i]); 2818 } 2819 2820 if (err) 2821 netdev_info(lif->netdev, "%s: failed %d\n", __func__, err); 2822 2823 return err; 2824 } 2825 2826 int ionic_lif_alloc(struct ionic *ionic) 2827 { 2828 struct device *dev = ionic->dev; 2829 union ionic_lif_identity *lid; 2830 struct net_device *netdev; 2831 struct ionic_lif *lif; 2832 int tbl_sz; 2833 int err; 2834 2835 lid = kzalloc(sizeof(*lid), GFP_KERNEL); 2836 if (!lid) 2837 return -ENOMEM; 2838 2839 netdev = alloc_etherdev_mqs(sizeof(*lif), 2840 ionic->ntxqs_per_lif, ionic->ntxqs_per_lif); 2841 if (!netdev) { 2842 dev_err(dev, "Cannot allocate netdev, aborting\n"); 2843 err = -ENOMEM; 2844 goto err_out_free_lid; 2845 } 2846 2847 SET_NETDEV_DEV(netdev, dev); 2848 2849 lif = netdev_priv(netdev); 2850 lif->netdev = netdev; 2851 ionic->lif = lif; 2852 netdev->netdev_ops = &ionic_netdev_ops; 2853 ionic_ethtool_set_ops(netdev); 2854 2855 netdev->watchdog_timeo = 2 * HZ; 2856 netif_carrier_off(netdev); 2857 2858 lif->identity = lid; 2859 lif->lif_type = IONIC_LIF_TYPE_CLASSIC; 2860 err = ionic_lif_identify(ionic, lif->lif_type, lif->identity); 2861 if (err) { 2862 dev_err(ionic->dev, "Cannot identify type %d: %d\n", 2863 lif->lif_type, err); 2864 goto err_out_free_netdev; 2865 } 2866 lif->netdev->min_mtu = max_t(unsigned int, ETH_MIN_MTU, 2867 le32_to_cpu(lif->identity->eth.min_frame_size)); 2868 lif->netdev->max_mtu = 2869 le32_to_cpu(lif->identity->eth.max_frame_size) - ETH_HLEN - VLAN_HLEN; 2870 2871 lif->neqs = ionic->neqs_per_lif; 2872 lif->nxqs = ionic->ntxqs_per_lif; 2873 2874 lif->ionic = ionic; 2875 lif->index = 0; 2876 2877 if (is_kdump_kernel()) { 2878 lif->ntxq_descs = IONIC_MIN_TXRX_DESC; 2879 lif->nrxq_descs = IONIC_MIN_TXRX_DESC; 2880 } else { 2881 lif->ntxq_descs = IONIC_DEF_TXRX_DESC; 2882 lif->nrxq_descs = IONIC_DEF_TXRX_DESC; 2883 } 2884 2885 /* Convert the default coalesce value to actual hw resolution */ 2886 lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT; 2887 lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic, 2888 lif->rx_coalesce_usecs); 2889 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 2890 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 2891 set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 2892 set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 2893 2894 snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index); 2895 2896 mutex_init(&lif->queue_lock); 2897 mutex_init(&lif->config_lock); 2898 2899 spin_lock_init(&lif->adminq_lock); 2900 2901 spin_lock_init(&lif->deferred.lock); 2902 INIT_LIST_HEAD(&lif->deferred.list); 2903 INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work); 2904 2905 /* allocate lif info */ 2906 lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE); 2907 lif->info = dma_alloc_coherent(dev, lif->info_sz, 2908 &lif->info_pa, GFP_KERNEL); 2909 if (!lif->info) { 2910 dev_err(dev, "Failed to allocate lif info, aborting\n"); 2911 err = -ENOMEM; 2912 goto err_out_free_mutex; 2913 } 2914 2915 ionic_debugfs_add_lif(lif); 2916 2917 /* allocate control queues and txrx queue arrays */ 2918 ionic_lif_queue_identify(lif); 2919 err = ionic_qcqs_alloc(lif); 2920 if (err) 2921 goto err_out_free_lif_info; 2922 2923 /* allocate rss indirection table */ 2924 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 2925 lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz; 2926 lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz, 2927 &lif->rss_ind_tbl_pa, 2928 GFP_KERNEL); 2929 2930 if (!lif->rss_ind_tbl) { 2931 err = -ENOMEM; 2932 dev_err(dev, "Failed to allocate rss indirection table, aborting\n"); 2933 goto err_out_free_qcqs; 2934 } 2935 netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE); 2936 2937 ionic_lif_alloc_phc(lif); 2938 2939 return 0; 2940 2941 err_out_free_qcqs: 2942 ionic_qcqs_free(lif); 2943 err_out_free_lif_info: 2944 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 2945 lif->info = NULL; 2946 lif->info_pa = 0; 2947 err_out_free_mutex: 2948 mutex_destroy(&lif->config_lock); 2949 mutex_destroy(&lif->queue_lock); 2950 err_out_free_netdev: 2951 free_netdev(lif->netdev); 2952 lif = NULL; 2953 err_out_free_lid: 2954 kfree(lid); 2955 2956 return err; 2957 } 2958 2959 static void ionic_lif_reset(struct ionic_lif *lif) 2960 { 2961 struct ionic_dev *idev = &lif->ionic->idev; 2962 2963 mutex_lock(&lif->ionic->dev_cmd_lock); 2964 ionic_dev_cmd_lif_reset(idev, lif->index); 2965 ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2966 mutex_unlock(&lif->ionic->dev_cmd_lock); 2967 } 2968 2969 static void ionic_lif_handle_fw_down(struct ionic_lif *lif) 2970 { 2971 struct ionic *ionic = lif->ionic; 2972 2973 if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2974 return; 2975 2976 dev_info(ionic->dev, "FW Down: Stopping LIFs\n"); 2977 2978 netif_device_detach(lif->netdev); 2979 2980 mutex_lock(&lif->queue_lock); 2981 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 2982 dev_info(ionic->dev, "Surprise FW stop, stopping queues\n"); 2983 ionic_stop_queues(lif); 2984 } 2985 2986 if (netif_running(lif->netdev)) { 2987 ionic_txrx_deinit(lif); 2988 ionic_txrx_free(lif); 2989 } 2990 ionic_lif_deinit(lif); 2991 ionic_reset(ionic); 2992 ionic_qcqs_free(lif); 2993 2994 mutex_unlock(&lif->queue_lock); 2995 2996 dev_info(ionic->dev, "FW Down: LIFs stopped\n"); 2997 } 2998 2999 static void ionic_lif_handle_fw_up(struct ionic_lif *lif) 3000 { 3001 struct ionic *ionic = lif->ionic; 3002 int err; 3003 3004 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 3005 return; 3006 3007 dev_info(ionic->dev, "FW Up: restarting LIFs\n"); 3008 3009 ionic_init_devinfo(ionic); 3010 err = ionic_identify(ionic); 3011 if (err) 3012 goto err_out; 3013 err = ionic_port_identify(ionic); 3014 if (err) 3015 goto err_out; 3016 err = ionic_port_init(ionic); 3017 if (err) 3018 goto err_out; 3019 3020 mutex_lock(&lif->queue_lock); 3021 3022 err = ionic_qcqs_alloc(lif); 3023 if (err) 3024 goto err_unlock; 3025 3026 err = ionic_lif_init(lif); 3027 if (err) 3028 goto err_qcqs_free; 3029 3030 if (lif->registered) 3031 ionic_lif_set_netdev_info(lif); 3032 3033 ionic_rx_filter_replay(lif); 3034 3035 if (netif_running(lif->netdev)) { 3036 err = ionic_txrx_alloc(lif); 3037 if (err) 3038 goto err_lifs_deinit; 3039 3040 err = ionic_txrx_init(lif); 3041 if (err) 3042 goto err_txrx_free; 3043 } 3044 3045 mutex_unlock(&lif->queue_lock); 3046 3047 clear_bit(IONIC_LIF_F_FW_RESET, lif->state); 3048 ionic_link_status_check_request(lif, CAN_SLEEP); 3049 netif_device_attach(lif->netdev); 3050 dev_info(ionic->dev, "FW Up: LIFs restarted\n"); 3051 3052 /* restore the hardware timestamping queues */ 3053 ionic_lif_hwstamp_replay(lif); 3054 3055 return; 3056 3057 err_txrx_free: 3058 ionic_txrx_free(lif); 3059 err_lifs_deinit: 3060 ionic_lif_deinit(lif); 3061 err_qcqs_free: 3062 ionic_qcqs_free(lif); 3063 err_unlock: 3064 mutex_unlock(&lif->queue_lock); 3065 err_out: 3066 dev_err(ionic->dev, "FW Up: LIFs restart failed - err %d\n", err); 3067 } 3068 3069 void ionic_lif_free(struct ionic_lif *lif) 3070 { 3071 struct device *dev = lif->ionic->dev; 3072 3073 ionic_lif_free_phc(lif); 3074 3075 /* free rss indirection table */ 3076 dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl, 3077 lif->rss_ind_tbl_pa); 3078 lif->rss_ind_tbl = NULL; 3079 lif->rss_ind_tbl_pa = 0; 3080 3081 /* free queues */ 3082 ionic_qcqs_free(lif); 3083 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 3084 ionic_lif_reset(lif); 3085 3086 /* free lif info */ 3087 kfree(lif->identity); 3088 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 3089 lif->info = NULL; 3090 lif->info_pa = 0; 3091 3092 /* unmap doorbell page */ 3093 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 3094 lif->kern_dbpage = NULL; 3095 kfree(lif->dbid_inuse); 3096 lif->dbid_inuse = NULL; 3097 3098 mutex_destroy(&lif->config_lock); 3099 mutex_destroy(&lif->queue_lock); 3100 3101 /* free netdev & lif */ 3102 ionic_debugfs_del_lif(lif); 3103 free_netdev(lif->netdev); 3104 } 3105 3106 void ionic_lif_deinit(struct ionic_lif *lif) 3107 { 3108 if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state)) 3109 return; 3110 3111 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 3112 cancel_work_sync(&lif->deferred.work); 3113 cancel_work_sync(&lif->tx_timeout_work); 3114 ionic_rx_filters_deinit(lif); 3115 if (lif->netdev->features & NETIF_F_RXHASH) 3116 ionic_lif_rss_deinit(lif); 3117 } 3118 3119 napi_disable(&lif->adminqcq->napi); 3120 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 3121 ionic_lif_qcq_deinit(lif, lif->adminqcq); 3122 3123 ionic_lif_reset(lif); 3124 } 3125 3126 static int ionic_lif_adminq_init(struct ionic_lif *lif) 3127 { 3128 struct device *dev = lif->ionic->dev; 3129 struct ionic_q_init_comp comp; 3130 struct ionic_dev *idev; 3131 struct ionic_qcq *qcq; 3132 struct ionic_queue *q; 3133 int err; 3134 3135 idev = &lif->ionic->idev; 3136 qcq = lif->adminqcq; 3137 q = &qcq->q; 3138 3139 mutex_lock(&lif->ionic->dev_cmd_lock); 3140 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index); 3141 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 3142 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 3143 mutex_unlock(&lif->ionic->dev_cmd_lock); 3144 if (err) { 3145 netdev_err(lif->netdev, "adminq init failed %d\n", err); 3146 return err; 3147 } 3148 3149 q->hw_type = comp.hw_type; 3150 q->hw_index = le32_to_cpu(comp.hw_index); 3151 q->dbval = IONIC_DBELL_QID(q->hw_index); 3152 3153 dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type); 3154 dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index); 3155 3156 netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi, 3157 NAPI_POLL_WEIGHT); 3158 3159 napi_enable(&qcq->napi); 3160 3161 if (qcq->flags & IONIC_QCQ_F_INTR) 3162 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 3163 IONIC_INTR_MASK_CLEAR); 3164 3165 qcq->flags |= IONIC_QCQ_F_INITED; 3166 3167 return 0; 3168 } 3169 3170 static int ionic_lif_notifyq_init(struct ionic_lif *lif) 3171 { 3172 struct ionic_qcq *qcq = lif->notifyqcq; 3173 struct device *dev = lif->ionic->dev; 3174 struct ionic_queue *q = &qcq->q; 3175 int err; 3176 3177 struct ionic_admin_ctx ctx = { 3178 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3179 .cmd.q_init = { 3180 .opcode = IONIC_CMD_Q_INIT, 3181 .lif_index = cpu_to_le16(lif->index), 3182 .type = q->type, 3183 .ver = lif->qtype_info[q->type].version, 3184 .index = cpu_to_le32(q->index), 3185 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 3186 IONIC_QINIT_F_ENA), 3187 .intr_index = cpu_to_le16(lif->adminqcq->intr.index), 3188 .pid = cpu_to_le16(q->pid), 3189 .ring_size = ilog2(q->num_descs), 3190 .ring_base = cpu_to_le64(q->base_pa), 3191 } 3192 }; 3193 3194 dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid); 3195 dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index); 3196 dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 3197 dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 3198 3199 err = ionic_adminq_post_wait(lif, &ctx); 3200 if (err) 3201 return err; 3202 3203 lif->last_eid = 0; 3204 q->hw_type = ctx.comp.q_init.hw_type; 3205 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 3206 q->dbval = IONIC_DBELL_QID(q->hw_index); 3207 3208 dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type); 3209 dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index); 3210 3211 /* preset the callback info */ 3212 q->info[0].cb_arg = lif; 3213 3214 qcq->flags |= IONIC_QCQ_F_INITED; 3215 3216 return 0; 3217 } 3218 3219 static int ionic_station_set(struct ionic_lif *lif) 3220 { 3221 struct net_device *netdev = lif->netdev; 3222 struct ionic_admin_ctx ctx = { 3223 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3224 .cmd.lif_getattr = { 3225 .opcode = IONIC_CMD_LIF_GETATTR, 3226 .index = cpu_to_le16(lif->index), 3227 .attr = IONIC_LIF_ATTR_MAC, 3228 }, 3229 }; 3230 struct sockaddr addr; 3231 int err; 3232 3233 err = ionic_adminq_post_wait(lif, &ctx); 3234 if (err) 3235 return err; 3236 netdev_dbg(lif->netdev, "found initial MAC addr %pM\n", 3237 ctx.comp.lif_getattr.mac); 3238 if (is_zero_ether_addr(ctx.comp.lif_getattr.mac)) 3239 return 0; 3240 3241 if (!is_zero_ether_addr(netdev->dev_addr)) { 3242 /* If the netdev mac is non-zero and doesn't match the default 3243 * device address, it was set by something earlier and we're 3244 * likely here again after a fw-upgrade reset. We need to be 3245 * sure the netdev mac is in our filter list. 3246 */ 3247 if (!ether_addr_equal(ctx.comp.lif_getattr.mac, 3248 netdev->dev_addr)) 3249 ionic_lif_addr_add(lif, netdev->dev_addr); 3250 } else { 3251 /* Update the netdev mac with the device's mac */ 3252 memcpy(addr.sa_data, ctx.comp.lif_getattr.mac, netdev->addr_len); 3253 addr.sa_family = AF_INET; 3254 err = eth_prepare_mac_addr_change(netdev, &addr); 3255 if (err) { 3256 netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n", 3257 addr.sa_data, err); 3258 return 0; 3259 } 3260 3261 eth_commit_mac_addr_change(netdev, &addr); 3262 } 3263 3264 netdev_dbg(lif->netdev, "adding station MAC addr %pM\n", 3265 netdev->dev_addr); 3266 ionic_lif_addr_add(lif, netdev->dev_addr); 3267 3268 return 0; 3269 } 3270 3271 int ionic_lif_init(struct ionic_lif *lif) 3272 { 3273 struct ionic_dev *idev = &lif->ionic->idev; 3274 struct device *dev = lif->ionic->dev; 3275 struct ionic_lif_init_comp comp; 3276 int dbpage_num; 3277 int err; 3278 3279 mutex_lock(&lif->ionic->dev_cmd_lock); 3280 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa); 3281 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 3282 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 3283 mutex_unlock(&lif->ionic->dev_cmd_lock); 3284 if (err) 3285 return err; 3286 3287 lif->hw_index = le16_to_cpu(comp.hw_index); 3288 3289 /* now that we have the hw_index we can figure out our doorbell page */ 3290 lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif); 3291 if (!lif->dbid_count) { 3292 dev_err(dev, "No doorbell pages, aborting\n"); 3293 return -EINVAL; 3294 } 3295 3296 lif->dbid_inuse = bitmap_alloc(lif->dbid_count, GFP_KERNEL); 3297 if (!lif->dbid_inuse) { 3298 dev_err(dev, "Failed alloc doorbell id bitmap, aborting\n"); 3299 return -ENOMEM; 3300 } 3301 3302 /* first doorbell id reserved for kernel (dbid aka pid == zero) */ 3303 set_bit(0, lif->dbid_inuse); 3304 lif->kern_pid = 0; 3305 3306 dbpage_num = ionic_db_page_num(lif, lif->kern_pid); 3307 lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num); 3308 if (!lif->kern_dbpage) { 3309 dev_err(dev, "Cannot map dbpage, aborting\n"); 3310 err = -ENOMEM; 3311 goto err_out_free_dbid; 3312 } 3313 3314 err = ionic_lif_adminq_init(lif); 3315 if (err) 3316 goto err_out_adminq_deinit; 3317 3318 if (lif->ionic->nnqs_per_lif) { 3319 err = ionic_lif_notifyq_init(lif); 3320 if (err) 3321 goto err_out_notifyq_deinit; 3322 } 3323 3324 err = ionic_init_nic_features(lif); 3325 if (err) 3326 goto err_out_notifyq_deinit; 3327 3328 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 3329 err = ionic_rx_filters_init(lif); 3330 if (err) 3331 goto err_out_notifyq_deinit; 3332 } 3333 3334 err = ionic_station_set(lif); 3335 if (err) 3336 goto err_out_notifyq_deinit; 3337 3338 lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT; 3339 3340 set_bit(IONIC_LIF_F_INITED, lif->state); 3341 3342 INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work); 3343 3344 return 0; 3345 3346 err_out_notifyq_deinit: 3347 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 3348 err_out_adminq_deinit: 3349 ionic_lif_qcq_deinit(lif, lif->adminqcq); 3350 ionic_lif_reset(lif); 3351 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 3352 lif->kern_dbpage = NULL; 3353 err_out_free_dbid: 3354 kfree(lif->dbid_inuse); 3355 lif->dbid_inuse = NULL; 3356 3357 return err; 3358 } 3359 3360 static void ionic_lif_notify_work(struct work_struct *ws) 3361 { 3362 } 3363 3364 static void ionic_lif_set_netdev_info(struct ionic_lif *lif) 3365 { 3366 struct ionic_admin_ctx ctx = { 3367 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3368 .cmd.lif_setattr = { 3369 .opcode = IONIC_CMD_LIF_SETATTR, 3370 .index = cpu_to_le16(lif->index), 3371 .attr = IONIC_LIF_ATTR_NAME, 3372 }, 3373 }; 3374 3375 strlcpy(ctx.cmd.lif_setattr.name, lif->netdev->name, 3376 sizeof(ctx.cmd.lif_setattr.name)); 3377 3378 ionic_adminq_post_wait(lif, &ctx); 3379 } 3380 3381 static struct ionic_lif *ionic_netdev_lif(struct net_device *netdev) 3382 { 3383 if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit) 3384 return NULL; 3385 3386 return netdev_priv(netdev); 3387 } 3388 3389 static int ionic_lif_notify(struct notifier_block *nb, 3390 unsigned long event, void *info) 3391 { 3392 struct net_device *ndev = netdev_notifier_info_to_dev(info); 3393 struct ionic *ionic = container_of(nb, struct ionic, nb); 3394 struct ionic_lif *lif = ionic_netdev_lif(ndev); 3395 3396 if (!lif || lif->ionic != ionic) 3397 return NOTIFY_DONE; 3398 3399 switch (event) { 3400 case NETDEV_CHANGENAME: 3401 ionic_lif_set_netdev_info(lif); 3402 break; 3403 } 3404 3405 return NOTIFY_DONE; 3406 } 3407 3408 int ionic_lif_register(struct ionic_lif *lif) 3409 { 3410 int err; 3411 3412 ionic_lif_register_phc(lif); 3413 3414 INIT_WORK(&lif->ionic->nb_work, ionic_lif_notify_work); 3415 3416 lif->ionic->nb.notifier_call = ionic_lif_notify; 3417 3418 err = register_netdevice_notifier(&lif->ionic->nb); 3419 if (err) 3420 lif->ionic->nb.notifier_call = NULL; 3421 3422 /* only register LIF0 for now */ 3423 err = register_netdev(lif->netdev); 3424 if (err) { 3425 dev_err(lif->ionic->dev, "Cannot register net device, aborting\n"); 3426 ionic_lif_unregister_phc(lif); 3427 return err; 3428 } 3429 3430 ionic_link_status_check_request(lif, CAN_SLEEP); 3431 lif->registered = true; 3432 ionic_lif_set_netdev_info(lif); 3433 3434 return 0; 3435 } 3436 3437 void ionic_lif_unregister(struct ionic_lif *lif) 3438 { 3439 if (lif->ionic->nb.notifier_call) { 3440 unregister_netdevice_notifier(&lif->ionic->nb); 3441 cancel_work_sync(&lif->ionic->nb_work); 3442 lif->ionic->nb.notifier_call = NULL; 3443 } 3444 3445 if (lif->netdev->reg_state == NETREG_REGISTERED) 3446 unregister_netdev(lif->netdev); 3447 3448 ionic_lif_unregister_phc(lif); 3449 3450 lif->registered = false; 3451 } 3452 3453 static void ionic_lif_queue_identify(struct ionic_lif *lif) 3454 { 3455 union ionic_q_identity __iomem *q_ident; 3456 struct ionic *ionic = lif->ionic; 3457 struct ionic_dev *idev; 3458 int qtype; 3459 int err; 3460 3461 idev = &lif->ionic->idev; 3462 q_ident = (union ionic_q_identity __iomem *)&idev->dev_cmd_regs->data; 3463 3464 for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) { 3465 struct ionic_qtype_info *qti = &lif->qtype_info[qtype]; 3466 3467 /* filter out the ones we know about */ 3468 switch (qtype) { 3469 case IONIC_QTYPE_ADMINQ: 3470 case IONIC_QTYPE_NOTIFYQ: 3471 case IONIC_QTYPE_RXQ: 3472 case IONIC_QTYPE_TXQ: 3473 break; 3474 default: 3475 continue; 3476 } 3477 3478 memset(qti, 0, sizeof(*qti)); 3479 3480 mutex_lock(&ionic->dev_cmd_lock); 3481 ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype, 3482 ionic_qtype_versions[qtype]); 3483 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3484 if (!err) { 3485 qti->version = readb(&q_ident->version); 3486 qti->supported = readb(&q_ident->supported); 3487 qti->features = readq(&q_ident->features); 3488 qti->desc_sz = readw(&q_ident->desc_sz); 3489 qti->comp_sz = readw(&q_ident->comp_sz); 3490 qti->sg_desc_sz = readw(&q_ident->sg_desc_sz); 3491 qti->max_sg_elems = readw(&q_ident->max_sg_elems); 3492 qti->sg_desc_stride = readw(&q_ident->sg_desc_stride); 3493 } 3494 mutex_unlock(&ionic->dev_cmd_lock); 3495 3496 if (err == -EINVAL) { 3497 dev_err(ionic->dev, "qtype %d not supported\n", qtype); 3498 continue; 3499 } else if (err == -EIO) { 3500 dev_err(ionic->dev, "q_ident failed, not supported on older FW\n"); 3501 return; 3502 } else if (err) { 3503 dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n", 3504 qtype, err); 3505 return; 3506 } 3507 3508 dev_dbg(ionic->dev, " qtype[%d].version = %d\n", 3509 qtype, qti->version); 3510 dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n", 3511 qtype, qti->supported); 3512 dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n", 3513 qtype, qti->features); 3514 dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n", 3515 qtype, qti->desc_sz); 3516 dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n", 3517 qtype, qti->comp_sz); 3518 dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n", 3519 qtype, qti->sg_desc_sz); 3520 dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n", 3521 qtype, qti->max_sg_elems); 3522 dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n", 3523 qtype, qti->sg_desc_stride); 3524 } 3525 } 3526 3527 int ionic_lif_identify(struct ionic *ionic, u8 lif_type, 3528 union ionic_lif_identity *lid) 3529 { 3530 struct ionic_dev *idev = &ionic->idev; 3531 size_t sz; 3532 int err; 3533 3534 sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data)); 3535 3536 mutex_lock(&ionic->dev_cmd_lock); 3537 ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1); 3538 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3539 memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz); 3540 mutex_unlock(&ionic->dev_cmd_lock); 3541 if (err) 3542 return (err); 3543 3544 dev_dbg(ionic->dev, "capabilities 0x%llx\n", 3545 le64_to_cpu(lid->capabilities)); 3546 3547 dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n", 3548 le32_to_cpu(lid->eth.max_ucast_filters)); 3549 dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n", 3550 le32_to_cpu(lid->eth.max_mcast_filters)); 3551 dev_dbg(ionic->dev, "eth.features 0x%llx\n", 3552 le64_to_cpu(lid->eth.config.features)); 3553 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n", 3554 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ])); 3555 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n", 3556 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ])); 3557 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n", 3558 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ])); 3559 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n", 3560 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ])); 3561 dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name); 3562 dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac); 3563 dev_dbg(ionic->dev, "eth.config.mtu %d\n", 3564 le32_to_cpu(lid->eth.config.mtu)); 3565 3566 return 0; 3567 } 3568 3569 int ionic_lif_size(struct ionic *ionic) 3570 { 3571 struct ionic_identity *ident = &ionic->ident; 3572 unsigned int nintrs, dev_nintrs; 3573 union ionic_lif_config *lc; 3574 unsigned int ntxqs_per_lif; 3575 unsigned int nrxqs_per_lif; 3576 unsigned int neqs_per_lif; 3577 unsigned int nnqs_per_lif; 3578 unsigned int nxqs, neqs; 3579 unsigned int min_intrs; 3580 int err; 3581 3582 /* retrieve basic values from FW */ 3583 lc = &ident->lif.eth.config; 3584 dev_nintrs = le32_to_cpu(ident->dev.nintrs); 3585 neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count); 3586 nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]); 3587 ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]); 3588 nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]); 3589 3590 /* limit values to play nice with kdump */ 3591 if (is_kdump_kernel()) { 3592 dev_nintrs = 2; 3593 neqs_per_lif = 0; 3594 nnqs_per_lif = 0; 3595 ntxqs_per_lif = 1; 3596 nrxqs_per_lif = 1; 3597 } 3598 3599 /* reserve last queue id for hardware timestamping */ 3600 if (lc->features & cpu_to_le64(IONIC_ETH_HW_TIMESTAMP)) { 3601 if (ntxqs_per_lif <= 1 || nrxqs_per_lif <= 1) { 3602 lc->features &= cpu_to_le64(~IONIC_ETH_HW_TIMESTAMP); 3603 } else { 3604 ntxqs_per_lif -= 1; 3605 nrxqs_per_lif -= 1; 3606 } 3607 } 3608 3609 nxqs = min(ntxqs_per_lif, nrxqs_per_lif); 3610 nxqs = min(nxqs, num_online_cpus()); 3611 neqs = min(neqs_per_lif, num_online_cpus()); 3612 3613 try_again: 3614 /* interrupt usage: 3615 * 1 for master lif adminq/notifyq 3616 * 1 for each CPU for master lif TxRx queue pairs 3617 * whatever's left is for RDMA queues 3618 */ 3619 nintrs = 1 + nxqs + neqs; 3620 min_intrs = 2; /* adminq + 1 TxRx queue pair */ 3621 3622 if (nintrs > dev_nintrs) 3623 goto try_fewer; 3624 3625 err = ionic_bus_alloc_irq_vectors(ionic, nintrs); 3626 if (err < 0 && err != -ENOSPC) { 3627 dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err); 3628 return err; 3629 } 3630 if (err == -ENOSPC) 3631 goto try_fewer; 3632 3633 if (err != nintrs) { 3634 ionic_bus_free_irq_vectors(ionic); 3635 goto try_fewer; 3636 } 3637 3638 ionic->nnqs_per_lif = nnqs_per_lif; 3639 ionic->neqs_per_lif = neqs; 3640 ionic->ntxqs_per_lif = nxqs; 3641 ionic->nrxqs_per_lif = nxqs; 3642 ionic->nintrs = nintrs; 3643 3644 ionic_debugfs_add_sizes(ionic); 3645 3646 return 0; 3647 3648 try_fewer: 3649 if (nnqs_per_lif > 1) { 3650 nnqs_per_lif >>= 1; 3651 goto try_again; 3652 } 3653 if (neqs > 1) { 3654 neqs >>= 1; 3655 goto try_again; 3656 } 3657 if (nxqs > 1) { 3658 nxqs >>= 1; 3659 goto try_again; 3660 } 3661 dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs); 3662 return -ENOSPC; 3663 } 3664