1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/printk.h> 5 #include <linux/dynamic_debug.h> 6 #include <linux/netdevice.h> 7 #include <linux/etherdevice.h> 8 #include <linux/if_vlan.h> 9 #include <linux/rtnetlink.h> 10 #include <linux/interrupt.h> 11 #include <linux/pci.h> 12 #include <linux/cpumask.h> 13 14 #include "ionic.h" 15 #include "ionic_bus.h" 16 #include "ionic_lif.h" 17 #include "ionic_txrx.h" 18 #include "ionic_ethtool.h" 19 #include "ionic_debugfs.h" 20 21 /* queuetype support level */ 22 static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = { 23 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */ 24 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */ 25 [IONIC_QTYPE_RXQ] = 0, /* 0 = Base version with CQ+SG support */ 26 [IONIC_QTYPE_TXQ] = 1, /* 0 = Base version with CQ+SG support 27 * 1 = ... with Tx SG version 1 28 */ 29 }; 30 31 static void ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode); 32 static int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr); 33 static int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr); 34 static void ionic_link_status_check(struct ionic_lif *lif); 35 static void ionic_lif_handle_fw_down(struct ionic_lif *lif); 36 static void ionic_lif_handle_fw_up(struct ionic_lif *lif); 37 static void ionic_lif_set_netdev_info(struct ionic_lif *lif); 38 39 static void ionic_txrx_deinit(struct ionic_lif *lif); 40 static int ionic_txrx_init(struct ionic_lif *lif); 41 static int ionic_start_queues(struct ionic_lif *lif); 42 static void ionic_stop_queues(struct ionic_lif *lif); 43 static void ionic_lif_queue_identify(struct ionic_lif *lif); 44 45 static void ionic_lif_deferred_work(struct work_struct *work) 46 { 47 struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work); 48 struct ionic_deferred *def = &lif->deferred; 49 struct ionic_deferred_work *w = NULL; 50 51 spin_lock_bh(&def->lock); 52 if (!list_empty(&def->list)) { 53 w = list_first_entry(&def->list, 54 struct ionic_deferred_work, list); 55 list_del(&w->list); 56 } 57 spin_unlock_bh(&def->lock); 58 59 if (w) { 60 switch (w->type) { 61 case IONIC_DW_TYPE_RX_MODE: 62 ionic_lif_rx_mode(lif, w->rx_mode); 63 break; 64 case IONIC_DW_TYPE_RX_ADDR_ADD: 65 ionic_lif_addr_add(lif, w->addr); 66 break; 67 case IONIC_DW_TYPE_RX_ADDR_DEL: 68 ionic_lif_addr_del(lif, w->addr); 69 break; 70 case IONIC_DW_TYPE_LINK_STATUS: 71 ionic_link_status_check(lif); 72 break; 73 case IONIC_DW_TYPE_LIF_RESET: 74 if (w->fw_status) 75 ionic_lif_handle_fw_up(lif); 76 else 77 ionic_lif_handle_fw_down(lif); 78 break; 79 default: 80 break; 81 } 82 kfree(w); 83 schedule_work(&def->work); 84 } 85 } 86 87 void ionic_lif_deferred_enqueue(struct ionic_deferred *def, 88 struct ionic_deferred_work *work) 89 { 90 spin_lock_bh(&def->lock); 91 list_add_tail(&work->list, &def->list); 92 spin_unlock_bh(&def->lock); 93 schedule_work(&def->work); 94 } 95 96 static void ionic_link_status_check(struct ionic_lif *lif) 97 { 98 struct net_device *netdev = lif->netdev; 99 u16 link_status; 100 bool link_up; 101 102 if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 103 return; 104 105 link_status = le16_to_cpu(lif->info->status.link_status); 106 link_up = link_status == IONIC_PORT_OPER_STATUS_UP; 107 108 if (link_up) { 109 if (!netif_carrier_ok(netdev)) { 110 u32 link_speed; 111 112 ionic_port_identify(lif->ionic); 113 link_speed = le32_to_cpu(lif->info->status.link_speed); 114 netdev_info(netdev, "Link up - %d Gbps\n", 115 link_speed / 1000); 116 netif_carrier_on(netdev); 117 } 118 119 if (lif->netdev->flags & IFF_UP && netif_running(lif->netdev)) { 120 mutex_lock(&lif->queue_lock); 121 ionic_start_queues(lif); 122 mutex_unlock(&lif->queue_lock); 123 } 124 } else { 125 if (netif_carrier_ok(netdev)) { 126 netdev_info(netdev, "Link down\n"); 127 netif_carrier_off(netdev); 128 } 129 130 if (lif->netdev->flags & IFF_UP && netif_running(lif->netdev)) { 131 mutex_lock(&lif->queue_lock); 132 ionic_stop_queues(lif); 133 mutex_unlock(&lif->queue_lock); 134 } 135 } 136 137 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 138 } 139 140 void ionic_link_status_check_request(struct ionic_lif *lif) 141 { 142 struct ionic_deferred_work *work; 143 144 /* we only need one request outstanding at a time */ 145 if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 146 return; 147 148 if (in_interrupt()) { 149 work = kzalloc(sizeof(*work), GFP_ATOMIC); 150 if (!work) 151 return; 152 153 work->type = IONIC_DW_TYPE_LINK_STATUS; 154 ionic_lif_deferred_enqueue(&lif->deferred, work); 155 } else { 156 ionic_link_status_check(lif); 157 } 158 } 159 160 static irqreturn_t ionic_isr(int irq, void *data) 161 { 162 struct napi_struct *napi = data; 163 164 napi_schedule_irqoff(napi); 165 166 return IRQ_HANDLED; 167 } 168 169 static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq) 170 { 171 struct ionic_intr_info *intr = &qcq->intr; 172 struct device *dev = lif->ionic->dev; 173 struct ionic_queue *q = &qcq->q; 174 const char *name; 175 176 if (lif->registered) 177 name = lif->netdev->name; 178 else 179 name = dev_name(dev); 180 181 snprintf(intr->name, sizeof(intr->name), 182 "%s-%s-%s", IONIC_DRV_NAME, name, q->name); 183 184 return devm_request_irq(dev, intr->vector, ionic_isr, 185 0, intr->name, &qcq->napi); 186 } 187 188 static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) 189 { 190 struct ionic *ionic = lif->ionic; 191 int index; 192 193 index = find_first_zero_bit(ionic->intrs, ionic->nintrs); 194 if (index == ionic->nintrs) { 195 netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n", 196 __func__, index, ionic->nintrs); 197 return -ENOSPC; 198 } 199 200 set_bit(index, ionic->intrs); 201 ionic_intr_init(&ionic->idev, intr, index); 202 203 return 0; 204 } 205 206 static void ionic_intr_free(struct ionic *ionic, int index) 207 { 208 if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < ionic->nintrs) 209 clear_bit(index, ionic->intrs); 210 } 211 212 static int ionic_qcq_enable(struct ionic_qcq *qcq) 213 { 214 struct ionic_queue *q = &qcq->q; 215 struct ionic_lif *lif = q->lif; 216 struct ionic_dev *idev; 217 struct device *dev; 218 219 struct ionic_admin_ctx ctx = { 220 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 221 .cmd.q_control = { 222 .opcode = IONIC_CMD_Q_CONTROL, 223 .lif_index = cpu_to_le16(lif->index), 224 .type = q->type, 225 .index = cpu_to_le32(q->index), 226 .oper = IONIC_Q_ENABLE, 227 }, 228 }; 229 230 idev = &lif->ionic->idev; 231 dev = lif->ionic->dev; 232 233 dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n", 234 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 235 236 if (qcq->flags & IONIC_QCQ_F_INTR) { 237 irq_set_affinity_hint(qcq->intr.vector, 238 &qcq->intr.affinity_mask); 239 napi_enable(&qcq->napi); 240 ionic_intr_clean(idev->intr_ctrl, qcq->intr.index); 241 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 242 IONIC_INTR_MASK_CLEAR); 243 } 244 245 return ionic_adminq_post_wait(lif, &ctx); 246 } 247 248 static int ionic_qcq_disable(struct ionic_qcq *qcq) 249 { 250 struct ionic_queue *q = &qcq->q; 251 struct ionic_lif *lif = q->lif; 252 struct ionic_dev *idev; 253 struct device *dev; 254 255 struct ionic_admin_ctx ctx = { 256 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 257 .cmd.q_control = { 258 .opcode = IONIC_CMD_Q_CONTROL, 259 .lif_index = cpu_to_le16(lif->index), 260 .type = q->type, 261 .index = cpu_to_le32(q->index), 262 .oper = IONIC_Q_DISABLE, 263 }, 264 }; 265 266 idev = &lif->ionic->idev; 267 dev = lif->ionic->dev; 268 269 dev_dbg(dev, "q_disable.index %d q_disable.qtype %d\n", 270 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 271 272 if (qcq->flags & IONIC_QCQ_F_INTR) { 273 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 274 IONIC_INTR_MASK_SET); 275 synchronize_irq(qcq->intr.vector); 276 irq_set_affinity_hint(qcq->intr.vector, NULL); 277 napi_disable(&qcq->napi); 278 } 279 280 return ionic_adminq_post_wait(lif, &ctx); 281 } 282 283 static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq) 284 { 285 struct ionic_dev *idev = &lif->ionic->idev; 286 287 if (!qcq) 288 return; 289 290 if (!(qcq->flags & IONIC_QCQ_F_INITED)) 291 return; 292 293 if (qcq->flags & IONIC_QCQ_F_INTR) { 294 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 295 IONIC_INTR_MASK_SET); 296 netif_napi_del(&qcq->napi); 297 } 298 299 qcq->flags &= ~IONIC_QCQ_F_INITED; 300 } 301 302 static void ionic_qcq_intr_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 303 { 304 if (!(qcq->flags & IONIC_QCQ_F_INTR) || qcq->intr.vector == 0) 305 return; 306 307 irq_set_affinity_hint(qcq->intr.vector, NULL); 308 devm_free_irq(lif->ionic->dev, qcq->intr.vector, &qcq->napi); 309 qcq->intr.vector = 0; 310 ionic_intr_free(lif->ionic, qcq->intr.index); 311 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 312 } 313 314 static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 315 { 316 struct device *dev = lif->ionic->dev; 317 318 if (!qcq) 319 return; 320 321 ionic_debugfs_del_qcq(qcq); 322 323 if (qcq->q_base) { 324 dma_free_coherent(dev, qcq->q_size, qcq->q_base, qcq->q_base_pa); 325 qcq->q_base = NULL; 326 qcq->q_base_pa = 0; 327 } 328 329 if (qcq->cq_base) { 330 dma_free_coherent(dev, qcq->cq_size, qcq->cq_base, qcq->cq_base_pa); 331 qcq->cq_base = NULL; 332 qcq->cq_base_pa = 0; 333 } 334 335 if (qcq->sg_base) { 336 dma_free_coherent(dev, qcq->sg_size, qcq->sg_base, qcq->sg_base_pa); 337 qcq->sg_base = NULL; 338 qcq->sg_base_pa = 0; 339 } 340 341 ionic_qcq_intr_free(lif, qcq); 342 343 if (qcq->cq.info) { 344 devm_kfree(dev, qcq->cq.info); 345 qcq->cq.info = NULL; 346 } 347 if (qcq->q.info) { 348 devm_kfree(dev, qcq->q.info); 349 qcq->q.info = NULL; 350 } 351 } 352 353 static void ionic_qcqs_free(struct ionic_lif *lif) 354 { 355 struct device *dev = lif->ionic->dev; 356 357 if (lif->notifyqcq) { 358 ionic_qcq_free(lif, lif->notifyqcq); 359 devm_kfree(dev, lif->notifyqcq); 360 lif->notifyqcq = NULL; 361 } 362 363 if (lif->adminqcq) { 364 ionic_qcq_free(lif, lif->adminqcq); 365 devm_kfree(dev, lif->adminqcq); 366 lif->adminqcq = NULL; 367 } 368 369 if (lif->rxqcqs) { 370 devm_kfree(dev, lif->rxqstats); 371 lif->rxqstats = NULL; 372 devm_kfree(dev, lif->rxqcqs); 373 lif->rxqcqs = NULL; 374 } 375 376 if (lif->txqcqs) { 377 devm_kfree(dev, lif->txqstats); 378 lif->txqstats = NULL; 379 devm_kfree(dev, lif->txqcqs); 380 lif->txqcqs = NULL; 381 } 382 } 383 384 static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq, 385 struct ionic_qcq *n_qcq) 386 { 387 if (WARN_ON(n_qcq->flags & IONIC_QCQ_F_INTR)) { 388 ionic_intr_free(n_qcq->cq.lif->ionic, n_qcq->intr.index); 389 n_qcq->flags &= ~IONIC_QCQ_F_INTR; 390 } 391 392 n_qcq->intr.vector = src_qcq->intr.vector; 393 n_qcq->intr.index = src_qcq->intr.index; 394 } 395 396 static int ionic_alloc_qcq_interrupt(struct ionic_lif *lif, struct ionic_qcq *qcq) 397 { 398 int err; 399 400 if (!(qcq->flags & IONIC_QCQ_F_INTR)) { 401 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 402 return 0; 403 } 404 405 err = ionic_intr_alloc(lif, &qcq->intr); 406 if (err) { 407 netdev_warn(lif->netdev, "no intr for %s: %d\n", 408 qcq->q.name, err); 409 goto err_out; 410 } 411 412 err = ionic_bus_get_irq(lif->ionic, qcq->intr.index); 413 if (err < 0) { 414 netdev_warn(lif->netdev, "no vector for %s: %d\n", 415 qcq->q.name, err); 416 goto err_out_free_intr; 417 } 418 qcq->intr.vector = err; 419 ionic_intr_mask_assert(lif->ionic->idev.intr_ctrl, qcq->intr.index, 420 IONIC_INTR_MASK_SET); 421 422 err = ionic_request_irq(lif, qcq); 423 if (err) { 424 netdev_warn(lif->netdev, "irq request failed %d\n", err); 425 goto err_out_free_intr; 426 } 427 428 /* try to get the irq on the local numa node first */ 429 qcq->intr.cpu = cpumask_local_spread(qcq->intr.index, 430 dev_to_node(lif->ionic->dev)); 431 if (qcq->intr.cpu != -1) 432 cpumask_set_cpu(qcq->intr.cpu, &qcq->intr.affinity_mask); 433 434 netdev_dbg(lif->netdev, "%s: Interrupt index %d\n", qcq->q.name, qcq->intr.index); 435 return 0; 436 437 err_out_free_intr: 438 ionic_intr_free(lif->ionic, qcq->intr.index); 439 err_out: 440 return err; 441 } 442 443 static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type, 444 unsigned int index, 445 const char *name, unsigned int flags, 446 unsigned int num_descs, unsigned int desc_size, 447 unsigned int cq_desc_size, 448 unsigned int sg_desc_size, 449 unsigned int pid, struct ionic_qcq **qcq) 450 { 451 struct ionic_dev *idev = &lif->ionic->idev; 452 struct device *dev = lif->ionic->dev; 453 void *q_base, *cq_base, *sg_base; 454 dma_addr_t cq_base_pa = 0; 455 dma_addr_t sg_base_pa = 0; 456 dma_addr_t q_base_pa = 0; 457 struct ionic_qcq *new; 458 int err; 459 460 *qcq = NULL; 461 462 new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL); 463 if (!new) { 464 netdev_err(lif->netdev, "Cannot allocate queue structure\n"); 465 err = -ENOMEM; 466 goto err_out; 467 } 468 469 new->flags = flags; 470 471 new->q.info = devm_kcalloc(dev, num_descs, sizeof(*new->q.info), 472 GFP_KERNEL); 473 if (!new->q.info) { 474 netdev_err(lif->netdev, "Cannot allocate queue info\n"); 475 err = -ENOMEM; 476 goto err_out_free_qcq; 477 } 478 479 new->q.type = type; 480 481 err = ionic_q_init(lif, idev, &new->q, index, name, num_descs, 482 desc_size, sg_desc_size, pid); 483 if (err) { 484 netdev_err(lif->netdev, "Cannot initialize queue\n"); 485 goto err_out_free_q_info; 486 } 487 488 err = ionic_alloc_qcq_interrupt(lif, new); 489 if (err) 490 goto err_out; 491 492 new->cq.info = devm_kcalloc(dev, num_descs, sizeof(*new->cq.info), 493 GFP_KERNEL); 494 if (!new->cq.info) { 495 netdev_err(lif->netdev, "Cannot allocate completion queue info\n"); 496 err = -ENOMEM; 497 goto err_out_free_irq; 498 } 499 500 err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size); 501 if (err) { 502 netdev_err(lif->netdev, "Cannot initialize completion queue\n"); 503 goto err_out_free_cq_info; 504 } 505 506 new->q_size = PAGE_SIZE + (num_descs * desc_size); 507 new->q_base = dma_alloc_coherent(dev, new->q_size, &new->q_base_pa, 508 GFP_KERNEL); 509 if (!new->q_base) { 510 netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n"); 511 err = -ENOMEM; 512 goto err_out_free_cq_info; 513 } 514 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE); 515 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 516 ionic_q_map(&new->q, q_base, q_base_pa); 517 518 new->cq_size = PAGE_SIZE + (num_descs * cq_desc_size); 519 new->cq_base = dma_alloc_coherent(dev, new->cq_size, &new->cq_base_pa, 520 GFP_KERNEL); 521 if (!new->cq_base) { 522 netdev_err(lif->netdev, "Cannot allocate cq DMA memory\n"); 523 err = -ENOMEM; 524 goto err_out_free_q; 525 } 526 cq_base = PTR_ALIGN(new->cq_base, PAGE_SIZE); 527 cq_base_pa = ALIGN(new->cq_base_pa, PAGE_SIZE); 528 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 529 ionic_cq_bind(&new->cq, &new->q); 530 531 if (flags & IONIC_QCQ_F_SG) { 532 new->sg_size = PAGE_SIZE + (num_descs * sg_desc_size); 533 new->sg_base = dma_alloc_coherent(dev, new->sg_size, &new->sg_base_pa, 534 GFP_KERNEL); 535 if (!new->sg_base) { 536 netdev_err(lif->netdev, "Cannot allocate sg DMA memory\n"); 537 err = -ENOMEM; 538 goto err_out_free_cq; 539 } 540 sg_base = PTR_ALIGN(new->sg_base, PAGE_SIZE); 541 sg_base_pa = ALIGN(new->sg_base_pa, PAGE_SIZE); 542 ionic_q_sg_map(&new->q, sg_base, sg_base_pa); 543 } 544 545 *qcq = new; 546 547 return 0; 548 549 err_out_free_cq: 550 dma_free_coherent(dev, new->cq_size, new->cq_base, new->cq_base_pa); 551 err_out_free_q: 552 dma_free_coherent(dev, new->q_size, new->q_base, new->q_base_pa); 553 err_out_free_cq_info: 554 devm_kfree(dev, new->cq.info); 555 err_out_free_irq: 556 if (flags & IONIC_QCQ_F_INTR) { 557 devm_free_irq(dev, new->intr.vector, &new->napi); 558 ionic_intr_free(lif->ionic, new->intr.index); 559 } 560 err_out_free_q_info: 561 devm_kfree(dev, new->q.info); 562 err_out_free_qcq: 563 devm_kfree(dev, new); 564 err_out: 565 dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err); 566 return err; 567 } 568 569 static int ionic_qcqs_alloc(struct ionic_lif *lif) 570 { 571 struct device *dev = lif->ionic->dev; 572 unsigned int flags; 573 int err; 574 575 flags = IONIC_QCQ_F_INTR; 576 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags, 577 IONIC_ADMINQ_LENGTH, 578 sizeof(struct ionic_admin_cmd), 579 sizeof(struct ionic_admin_comp), 580 0, lif->kern_pid, &lif->adminqcq); 581 if (err) 582 return err; 583 ionic_debugfs_add_qcq(lif, lif->adminqcq); 584 585 if (lif->ionic->nnqs_per_lif) { 586 flags = IONIC_QCQ_F_NOTIFYQ; 587 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq", 588 flags, IONIC_NOTIFYQ_LENGTH, 589 sizeof(struct ionic_notifyq_cmd), 590 sizeof(union ionic_notifyq_comp), 591 0, lif->kern_pid, &lif->notifyqcq); 592 if (err) 593 goto err_out; 594 ionic_debugfs_add_qcq(lif, lif->notifyqcq); 595 596 /* Let the notifyq ride on the adminq interrupt */ 597 ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq); 598 } 599 600 err = -ENOMEM; 601 lif->txqcqs = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif, 602 sizeof(struct ionic_qcq *), GFP_KERNEL); 603 if (!lif->txqcqs) 604 goto err_out; 605 lif->rxqcqs = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif, 606 sizeof(struct ionic_qcq *), GFP_KERNEL); 607 if (!lif->rxqcqs) 608 goto err_out; 609 610 lif->txqstats = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif, 611 sizeof(struct ionic_tx_stats), GFP_KERNEL); 612 if (!lif->txqstats) 613 goto err_out; 614 lif->rxqstats = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif, 615 sizeof(struct ionic_rx_stats), GFP_KERNEL); 616 if (!lif->rxqstats) 617 goto err_out; 618 619 return 0; 620 621 err_out: 622 ionic_qcqs_free(lif); 623 return err; 624 } 625 626 static void ionic_qcq_sanitize(struct ionic_qcq *qcq) 627 { 628 qcq->q.tail_idx = 0; 629 qcq->q.head_idx = 0; 630 qcq->cq.tail_idx = 0; 631 qcq->cq.done_color = 1; 632 memset(qcq->q_base, 0, qcq->q_size); 633 memset(qcq->cq_base, 0, qcq->cq_size); 634 memset(qcq->sg_base, 0, qcq->sg_size); 635 } 636 637 static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 638 { 639 struct device *dev = lif->ionic->dev; 640 struct ionic_queue *q = &qcq->q; 641 struct ionic_cq *cq = &qcq->cq; 642 struct ionic_admin_ctx ctx = { 643 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 644 .cmd.q_init = { 645 .opcode = IONIC_CMD_Q_INIT, 646 .lif_index = cpu_to_le16(lif->index), 647 .type = q->type, 648 .ver = lif->qtype_info[q->type].version, 649 .index = cpu_to_le32(q->index), 650 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 651 IONIC_QINIT_F_SG), 652 .pid = cpu_to_le16(q->pid), 653 .ring_size = ilog2(q->num_descs), 654 .ring_base = cpu_to_le64(q->base_pa), 655 .cq_ring_base = cpu_to_le64(cq->base_pa), 656 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 657 }, 658 }; 659 unsigned int intr_index; 660 int err; 661 662 if (qcq->flags & IONIC_QCQ_F_INTR) 663 intr_index = qcq->intr.index; 664 else 665 intr_index = lif->rxqcqs[q->index]->intr.index; 666 ctx.cmd.q_init.intr_index = cpu_to_le16(intr_index); 667 668 dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid); 669 dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index); 670 dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 671 dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 672 dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 673 dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver); 674 dev_dbg(dev, "txq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 675 676 ionic_qcq_sanitize(qcq); 677 678 err = ionic_adminq_post_wait(lif, &ctx); 679 if (err) 680 return err; 681 682 q->hw_type = ctx.comp.q_init.hw_type; 683 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 684 q->dbval = IONIC_DBELL_QID(q->hw_index); 685 686 dev_dbg(dev, "txq->hw_type %d\n", q->hw_type); 687 dev_dbg(dev, "txq->hw_index %d\n", q->hw_index); 688 689 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 690 netif_napi_add(lif->netdev, &qcq->napi, ionic_tx_napi, 691 NAPI_POLL_WEIGHT); 692 693 qcq->flags |= IONIC_QCQ_F_INITED; 694 695 return 0; 696 } 697 698 static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 699 { 700 struct device *dev = lif->ionic->dev; 701 struct ionic_queue *q = &qcq->q; 702 struct ionic_cq *cq = &qcq->cq; 703 struct ionic_admin_ctx ctx = { 704 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 705 .cmd.q_init = { 706 .opcode = IONIC_CMD_Q_INIT, 707 .lif_index = cpu_to_le16(lif->index), 708 .type = q->type, 709 .ver = lif->qtype_info[q->type].version, 710 .index = cpu_to_le32(q->index), 711 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 712 IONIC_QINIT_F_SG), 713 .intr_index = cpu_to_le16(cq->bound_intr->index), 714 .pid = cpu_to_le16(q->pid), 715 .ring_size = ilog2(q->num_descs), 716 .ring_base = cpu_to_le64(q->base_pa), 717 .cq_ring_base = cpu_to_le64(cq->base_pa), 718 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 719 }, 720 }; 721 int err; 722 723 dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid); 724 dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index); 725 dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 726 dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 727 dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 728 dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver); 729 dev_dbg(dev, "rxq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 730 731 ionic_qcq_sanitize(qcq); 732 733 err = ionic_adminq_post_wait(lif, &ctx); 734 if (err) 735 return err; 736 737 q->hw_type = ctx.comp.q_init.hw_type; 738 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 739 q->dbval = IONIC_DBELL_QID(q->hw_index); 740 741 dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type); 742 dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index); 743 744 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 745 netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi, 746 NAPI_POLL_WEIGHT); 747 else 748 netif_napi_add(lif->netdev, &qcq->napi, ionic_txrx_napi, 749 NAPI_POLL_WEIGHT); 750 751 qcq->flags |= IONIC_QCQ_F_INITED; 752 753 return 0; 754 } 755 756 static bool ionic_notifyq_service(struct ionic_cq *cq, 757 struct ionic_cq_info *cq_info) 758 { 759 union ionic_notifyq_comp *comp = cq_info->cq_desc; 760 struct ionic_deferred_work *work; 761 struct net_device *netdev; 762 struct ionic_queue *q; 763 struct ionic_lif *lif; 764 u64 eid; 765 766 q = cq->bound_q; 767 lif = q->info[0].cb_arg; 768 netdev = lif->netdev; 769 eid = le64_to_cpu(comp->event.eid); 770 771 /* Have we run out of new completions to process? */ 772 if ((s64)(eid - lif->last_eid) <= 0) 773 return false; 774 775 lif->last_eid = eid; 776 777 dev_dbg(lif->ionic->dev, "notifyq event:\n"); 778 dynamic_hex_dump("event ", DUMP_PREFIX_OFFSET, 16, 1, 779 comp, sizeof(*comp), true); 780 781 switch (le16_to_cpu(comp->event.ecode)) { 782 case IONIC_EVENT_LINK_CHANGE: 783 ionic_link_status_check_request(lif); 784 break; 785 case IONIC_EVENT_RESET: 786 work = kzalloc(sizeof(*work), GFP_ATOMIC); 787 if (!work) { 788 netdev_err(lif->netdev, "%s OOM\n", __func__); 789 } else { 790 work->type = IONIC_DW_TYPE_LIF_RESET; 791 ionic_lif_deferred_enqueue(&lif->deferred, work); 792 } 793 break; 794 default: 795 netdev_warn(netdev, "Notifyq event ecode=%d eid=%lld\n", 796 comp->event.ecode, eid); 797 break; 798 } 799 800 return true; 801 } 802 803 static int ionic_notifyq_clean(struct ionic_lif *lif, int budget) 804 { 805 struct ionic_dev *idev = &lif->ionic->idev; 806 struct ionic_cq *cq = &lif->notifyqcq->cq; 807 u32 work_done; 808 809 work_done = ionic_cq_service(cq, budget, ionic_notifyq_service, 810 NULL, NULL); 811 if (work_done) 812 ionic_intr_credits(idev->intr_ctrl, cq->bound_intr->index, 813 work_done, IONIC_INTR_CRED_RESET_COALESCE); 814 815 return work_done; 816 } 817 818 static bool ionic_adminq_service(struct ionic_cq *cq, 819 struct ionic_cq_info *cq_info) 820 { 821 struct ionic_admin_comp *comp = cq_info->cq_desc; 822 823 if (!color_match(comp->color, cq->done_color)) 824 return false; 825 826 ionic_q_service(cq->bound_q, cq_info, le16_to_cpu(comp->comp_index)); 827 828 return true; 829 } 830 831 static int ionic_adminq_napi(struct napi_struct *napi, int budget) 832 { 833 struct ionic_lif *lif = napi_to_cq(napi)->lif; 834 int n_work = 0; 835 int a_work = 0; 836 837 if (likely(lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED)) 838 n_work = ionic_notifyq_clean(lif, budget); 839 a_work = ionic_napi(napi, budget, ionic_adminq_service, NULL, NULL); 840 841 return max(n_work, a_work); 842 } 843 844 void ionic_get_stats64(struct net_device *netdev, 845 struct rtnl_link_stats64 *ns) 846 { 847 struct ionic_lif *lif = netdev_priv(netdev); 848 struct ionic_lif_stats *ls; 849 850 memset(ns, 0, sizeof(*ns)); 851 ls = &lif->info->stats; 852 853 ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) + 854 le64_to_cpu(ls->rx_mcast_packets) + 855 le64_to_cpu(ls->rx_bcast_packets); 856 857 ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) + 858 le64_to_cpu(ls->tx_mcast_packets) + 859 le64_to_cpu(ls->tx_bcast_packets); 860 861 ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) + 862 le64_to_cpu(ls->rx_mcast_bytes) + 863 le64_to_cpu(ls->rx_bcast_bytes); 864 865 ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) + 866 le64_to_cpu(ls->tx_mcast_bytes) + 867 le64_to_cpu(ls->tx_bcast_bytes); 868 869 ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) + 870 le64_to_cpu(ls->rx_mcast_drop_packets) + 871 le64_to_cpu(ls->rx_bcast_drop_packets); 872 873 ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) + 874 le64_to_cpu(ls->tx_mcast_drop_packets) + 875 le64_to_cpu(ls->tx_bcast_drop_packets); 876 877 ns->multicast = le64_to_cpu(ls->rx_mcast_packets); 878 879 ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty); 880 881 ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) + 882 le64_to_cpu(ls->rx_queue_disabled) + 883 le64_to_cpu(ls->rx_desc_fetch_error) + 884 le64_to_cpu(ls->rx_desc_data_error); 885 886 ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) + 887 le64_to_cpu(ls->tx_queue_disabled) + 888 le64_to_cpu(ls->tx_desc_fetch_error) + 889 le64_to_cpu(ls->tx_desc_data_error); 890 891 ns->rx_errors = ns->rx_over_errors + 892 ns->rx_missed_errors; 893 894 ns->tx_errors = ns->tx_aborted_errors; 895 } 896 897 static int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr) 898 { 899 struct ionic_admin_ctx ctx = { 900 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 901 .cmd.rx_filter_add = { 902 .opcode = IONIC_CMD_RX_FILTER_ADD, 903 .lif_index = cpu_to_le16(lif->index), 904 .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_MAC), 905 }, 906 }; 907 struct ionic_rx_filter *f; 908 int err; 909 910 /* don't bother if we already have it */ 911 spin_lock_bh(&lif->rx_filters.lock); 912 f = ionic_rx_filter_by_addr(lif, addr); 913 spin_unlock_bh(&lif->rx_filters.lock); 914 if (f) 915 return 0; 916 917 netdev_dbg(lif->netdev, "rx_filter add ADDR %pM\n", addr); 918 919 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, ETH_ALEN); 920 err = ionic_adminq_post_wait(lif, &ctx); 921 if (err && err != -EEXIST) 922 return err; 923 924 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx); 925 } 926 927 static int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr) 928 { 929 struct ionic_admin_ctx ctx = { 930 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 931 .cmd.rx_filter_del = { 932 .opcode = IONIC_CMD_RX_FILTER_DEL, 933 .lif_index = cpu_to_le16(lif->index), 934 }, 935 }; 936 struct ionic_rx_filter *f; 937 int err; 938 939 spin_lock_bh(&lif->rx_filters.lock); 940 f = ionic_rx_filter_by_addr(lif, addr); 941 if (!f) { 942 spin_unlock_bh(&lif->rx_filters.lock); 943 return -ENOENT; 944 } 945 946 netdev_dbg(lif->netdev, "rx_filter del ADDR %pM (id %d)\n", 947 addr, f->filter_id); 948 949 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id); 950 ionic_rx_filter_free(lif, f); 951 spin_unlock_bh(&lif->rx_filters.lock); 952 953 err = ionic_adminq_post_wait(lif, &ctx); 954 if (err && err != -EEXIST) 955 return err; 956 957 return 0; 958 } 959 960 static int ionic_lif_addr(struct ionic_lif *lif, const u8 *addr, bool add) 961 { 962 struct ionic *ionic = lif->ionic; 963 struct ionic_deferred_work *work; 964 unsigned int nmfilters; 965 unsigned int nufilters; 966 967 if (add) { 968 /* Do we have space for this filter? We test the counters 969 * here before checking the need for deferral so that we 970 * can return an overflow error to the stack. 971 */ 972 nmfilters = le32_to_cpu(ionic->ident.lif.eth.max_mcast_filters); 973 nufilters = le32_to_cpu(ionic->ident.lif.eth.max_ucast_filters); 974 975 if ((is_multicast_ether_addr(addr) && lif->nmcast < nmfilters)) 976 lif->nmcast++; 977 else if (!is_multicast_ether_addr(addr) && 978 lif->nucast < nufilters) 979 lif->nucast++; 980 else 981 return -ENOSPC; 982 } else { 983 if (is_multicast_ether_addr(addr) && lif->nmcast) 984 lif->nmcast--; 985 else if (!is_multicast_ether_addr(addr) && lif->nucast) 986 lif->nucast--; 987 } 988 989 if (in_interrupt()) { 990 work = kzalloc(sizeof(*work), GFP_ATOMIC); 991 if (!work) { 992 netdev_err(lif->netdev, "%s OOM\n", __func__); 993 return -ENOMEM; 994 } 995 work->type = add ? IONIC_DW_TYPE_RX_ADDR_ADD : 996 IONIC_DW_TYPE_RX_ADDR_DEL; 997 memcpy(work->addr, addr, ETH_ALEN); 998 netdev_dbg(lif->netdev, "deferred: rx_filter %s %pM\n", 999 add ? "add" : "del", addr); 1000 ionic_lif_deferred_enqueue(&lif->deferred, work); 1001 } else { 1002 netdev_dbg(lif->netdev, "rx_filter %s %pM\n", 1003 add ? "add" : "del", addr); 1004 if (add) 1005 return ionic_lif_addr_add(lif, addr); 1006 else 1007 return ionic_lif_addr_del(lif, addr); 1008 } 1009 1010 return 0; 1011 } 1012 1013 static int ionic_addr_add(struct net_device *netdev, const u8 *addr) 1014 { 1015 return ionic_lif_addr(netdev_priv(netdev), addr, true); 1016 } 1017 1018 static int ionic_addr_del(struct net_device *netdev, const u8 *addr) 1019 { 1020 return ionic_lif_addr(netdev_priv(netdev), addr, false); 1021 } 1022 1023 static void ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode) 1024 { 1025 struct ionic_admin_ctx ctx = { 1026 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1027 .cmd.rx_mode_set = { 1028 .opcode = IONIC_CMD_RX_MODE_SET, 1029 .lif_index = cpu_to_le16(lif->index), 1030 .rx_mode = cpu_to_le16(rx_mode), 1031 }, 1032 }; 1033 char buf[128]; 1034 int err; 1035 int i; 1036 #define REMAIN(__x) (sizeof(buf) - (__x)) 1037 1038 i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:", 1039 lif->rx_mode, rx_mode); 1040 if (rx_mode & IONIC_RX_MODE_F_UNICAST) 1041 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST"); 1042 if (rx_mode & IONIC_RX_MODE_F_MULTICAST) 1043 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST"); 1044 if (rx_mode & IONIC_RX_MODE_F_BROADCAST) 1045 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST"); 1046 if (rx_mode & IONIC_RX_MODE_F_PROMISC) 1047 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC"); 1048 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI) 1049 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI"); 1050 netdev_dbg(lif->netdev, "lif%d %s\n", lif->index, buf); 1051 1052 err = ionic_adminq_post_wait(lif, &ctx); 1053 if (err) 1054 netdev_warn(lif->netdev, "set rx_mode 0x%04x failed: %d\n", 1055 rx_mode, err); 1056 else 1057 lif->rx_mode = rx_mode; 1058 } 1059 1060 static void _ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode) 1061 { 1062 struct ionic_deferred_work *work; 1063 1064 if (in_interrupt()) { 1065 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1066 if (!work) { 1067 netdev_err(lif->netdev, "%s OOM\n", __func__); 1068 return; 1069 } 1070 work->type = IONIC_DW_TYPE_RX_MODE; 1071 work->rx_mode = rx_mode; 1072 netdev_dbg(lif->netdev, "deferred: rx_mode\n"); 1073 ionic_lif_deferred_enqueue(&lif->deferred, work); 1074 } else { 1075 ionic_lif_rx_mode(lif, rx_mode); 1076 } 1077 } 1078 1079 static void ionic_set_rx_mode(struct net_device *netdev) 1080 { 1081 struct ionic_lif *lif = netdev_priv(netdev); 1082 struct ionic_identity *ident; 1083 unsigned int nfilters; 1084 unsigned int rx_mode; 1085 1086 ident = &lif->ionic->ident; 1087 1088 rx_mode = IONIC_RX_MODE_F_UNICAST; 1089 rx_mode |= (netdev->flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0; 1090 rx_mode |= (netdev->flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0; 1091 rx_mode |= (netdev->flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0; 1092 rx_mode |= (netdev->flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0; 1093 1094 /* sync unicast addresses 1095 * next check to see if we're in an overflow state 1096 * if so, we track that we overflowed and enable NIC PROMISC 1097 * else if the overflow is set and not needed 1098 * we remove our overflow flag and check the netdev flags 1099 * to see if we can disable NIC PROMISC 1100 */ 1101 __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del); 1102 nfilters = le32_to_cpu(ident->lif.eth.max_ucast_filters); 1103 if (netdev_uc_count(netdev) + 1 > nfilters) { 1104 rx_mode |= IONIC_RX_MODE_F_PROMISC; 1105 lif->uc_overflow = true; 1106 } else if (lif->uc_overflow) { 1107 lif->uc_overflow = false; 1108 if (!(netdev->flags & IFF_PROMISC)) 1109 rx_mode &= ~IONIC_RX_MODE_F_PROMISC; 1110 } 1111 1112 /* same for multicast */ 1113 __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del); 1114 nfilters = le32_to_cpu(ident->lif.eth.max_mcast_filters); 1115 if (netdev_mc_count(netdev) > nfilters) { 1116 rx_mode |= IONIC_RX_MODE_F_ALLMULTI; 1117 lif->mc_overflow = true; 1118 } else if (lif->mc_overflow) { 1119 lif->mc_overflow = false; 1120 if (!(netdev->flags & IFF_ALLMULTI)) 1121 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI; 1122 } 1123 1124 if (lif->rx_mode != rx_mode) 1125 _ionic_lif_rx_mode(lif, rx_mode); 1126 } 1127 1128 static __le64 ionic_netdev_features_to_nic(netdev_features_t features) 1129 { 1130 u64 wanted = 0; 1131 1132 if (features & NETIF_F_HW_VLAN_CTAG_TX) 1133 wanted |= IONIC_ETH_HW_VLAN_TX_TAG; 1134 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1135 wanted |= IONIC_ETH_HW_VLAN_RX_STRIP; 1136 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1137 wanted |= IONIC_ETH_HW_VLAN_RX_FILTER; 1138 if (features & NETIF_F_RXHASH) 1139 wanted |= IONIC_ETH_HW_RX_HASH; 1140 if (features & NETIF_F_RXCSUM) 1141 wanted |= IONIC_ETH_HW_RX_CSUM; 1142 if (features & NETIF_F_SG) 1143 wanted |= IONIC_ETH_HW_TX_SG; 1144 if (features & NETIF_F_HW_CSUM) 1145 wanted |= IONIC_ETH_HW_TX_CSUM; 1146 if (features & NETIF_F_TSO) 1147 wanted |= IONIC_ETH_HW_TSO; 1148 if (features & NETIF_F_TSO6) 1149 wanted |= IONIC_ETH_HW_TSO_IPV6; 1150 if (features & NETIF_F_TSO_ECN) 1151 wanted |= IONIC_ETH_HW_TSO_ECN; 1152 if (features & NETIF_F_GSO_GRE) 1153 wanted |= IONIC_ETH_HW_TSO_GRE; 1154 if (features & NETIF_F_GSO_GRE_CSUM) 1155 wanted |= IONIC_ETH_HW_TSO_GRE_CSUM; 1156 if (features & NETIF_F_GSO_IPXIP4) 1157 wanted |= IONIC_ETH_HW_TSO_IPXIP4; 1158 if (features & NETIF_F_GSO_IPXIP6) 1159 wanted |= IONIC_ETH_HW_TSO_IPXIP6; 1160 if (features & NETIF_F_GSO_UDP_TUNNEL) 1161 wanted |= IONIC_ETH_HW_TSO_UDP; 1162 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) 1163 wanted |= IONIC_ETH_HW_TSO_UDP_CSUM; 1164 1165 return cpu_to_le64(wanted); 1166 } 1167 1168 static int ionic_set_nic_features(struct ionic_lif *lif, 1169 netdev_features_t features) 1170 { 1171 struct device *dev = lif->ionic->dev; 1172 struct ionic_admin_ctx ctx = { 1173 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1174 .cmd.lif_setattr = { 1175 .opcode = IONIC_CMD_LIF_SETATTR, 1176 .index = cpu_to_le16(lif->index), 1177 .attr = IONIC_LIF_ATTR_FEATURES, 1178 }, 1179 }; 1180 u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG | 1181 IONIC_ETH_HW_VLAN_RX_STRIP | 1182 IONIC_ETH_HW_VLAN_RX_FILTER; 1183 u64 old_hw_features; 1184 int err; 1185 1186 ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features); 1187 err = ionic_adminq_post_wait(lif, &ctx); 1188 if (err) 1189 return err; 1190 1191 old_hw_features = lif->hw_features; 1192 lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features & 1193 ctx.comp.lif_setattr.features); 1194 1195 if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH) 1196 ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1197 1198 if ((vlan_flags & features) && 1199 !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features))) 1200 dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n"); 1201 1202 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1203 dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n"); 1204 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1205 dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n"); 1206 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1207 dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n"); 1208 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1209 dev_dbg(dev, "feature ETH_HW_RX_HASH\n"); 1210 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1211 dev_dbg(dev, "feature ETH_HW_TX_SG\n"); 1212 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1213 dev_dbg(dev, "feature ETH_HW_TX_CSUM\n"); 1214 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1215 dev_dbg(dev, "feature ETH_HW_RX_CSUM\n"); 1216 if (lif->hw_features & IONIC_ETH_HW_TSO) 1217 dev_dbg(dev, "feature ETH_HW_TSO\n"); 1218 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1219 dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n"); 1220 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1221 dev_dbg(dev, "feature ETH_HW_TSO_ECN\n"); 1222 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1223 dev_dbg(dev, "feature ETH_HW_TSO_GRE\n"); 1224 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1225 dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n"); 1226 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1227 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n"); 1228 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1229 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n"); 1230 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1231 dev_dbg(dev, "feature ETH_HW_TSO_UDP\n"); 1232 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1233 dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n"); 1234 1235 return 0; 1236 } 1237 1238 static int ionic_init_nic_features(struct ionic_lif *lif) 1239 { 1240 struct net_device *netdev = lif->netdev; 1241 netdev_features_t features; 1242 int err; 1243 1244 /* set up what we expect to support by default */ 1245 features = NETIF_F_HW_VLAN_CTAG_TX | 1246 NETIF_F_HW_VLAN_CTAG_RX | 1247 NETIF_F_HW_VLAN_CTAG_FILTER | 1248 NETIF_F_RXHASH | 1249 NETIF_F_SG | 1250 NETIF_F_HW_CSUM | 1251 NETIF_F_RXCSUM | 1252 NETIF_F_TSO | 1253 NETIF_F_TSO6 | 1254 NETIF_F_TSO_ECN; 1255 1256 err = ionic_set_nic_features(lif, features); 1257 if (err) 1258 return err; 1259 1260 /* tell the netdev what we actually can support */ 1261 netdev->features |= NETIF_F_HIGHDMA; 1262 1263 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1264 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 1265 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1266 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 1267 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1268 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1269 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1270 netdev->hw_features |= NETIF_F_RXHASH; 1271 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1272 netdev->hw_features |= NETIF_F_SG; 1273 1274 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1275 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 1276 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1277 netdev->hw_enc_features |= NETIF_F_RXCSUM; 1278 if (lif->hw_features & IONIC_ETH_HW_TSO) 1279 netdev->hw_enc_features |= NETIF_F_TSO; 1280 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1281 netdev->hw_enc_features |= NETIF_F_TSO6; 1282 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1283 netdev->hw_enc_features |= NETIF_F_TSO_ECN; 1284 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1285 netdev->hw_enc_features |= NETIF_F_GSO_GRE; 1286 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1287 netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM; 1288 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1289 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4; 1290 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1291 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6; 1292 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1293 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL; 1294 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1295 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 1296 1297 netdev->hw_features |= netdev->hw_enc_features; 1298 netdev->features |= netdev->hw_features; 1299 netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES; 1300 1301 netdev->priv_flags |= IFF_UNICAST_FLT | 1302 IFF_LIVE_ADDR_CHANGE; 1303 1304 return 0; 1305 } 1306 1307 static int ionic_set_features(struct net_device *netdev, 1308 netdev_features_t features) 1309 { 1310 struct ionic_lif *lif = netdev_priv(netdev); 1311 int err; 1312 1313 netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n", 1314 __func__, (u64)lif->netdev->features, (u64)features); 1315 1316 err = ionic_set_nic_features(lif, features); 1317 1318 return err; 1319 } 1320 1321 static int ionic_set_mac_address(struct net_device *netdev, void *sa) 1322 { 1323 struct sockaddr *addr = sa; 1324 u8 *mac; 1325 int err; 1326 1327 mac = (u8 *)addr->sa_data; 1328 if (ether_addr_equal(netdev->dev_addr, mac)) 1329 return 0; 1330 1331 err = eth_prepare_mac_addr_change(netdev, addr); 1332 if (err) 1333 return err; 1334 1335 if (!is_zero_ether_addr(netdev->dev_addr)) { 1336 netdev_info(netdev, "deleting mac addr %pM\n", 1337 netdev->dev_addr); 1338 ionic_addr_del(netdev, netdev->dev_addr); 1339 } 1340 1341 eth_commit_mac_addr_change(netdev, addr); 1342 netdev_info(netdev, "updating mac addr %pM\n", mac); 1343 1344 return ionic_addr_add(netdev, mac); 1345 } 1346 1347 static void ionic_stop_queues_reconfig(struct ionic_lif *lif) 1348 { 1349 /* Stop and clean the queues before reconfiguration */ 1350 mutex_lock(&lif->queue_lock); 1351 netif_device_detach(lif->netdev); 1352 ionic_stop_queues(lif); 1353 ionic_txrx_deinit(lif); 1354 } 1355 1356 static int ionic_start_queues_reconfig(struct ionic_lif *lif) 1357 { 1358 int err; 1359 1360 /* Re-init the queues after reconfiguration */ 1361 1362 /* The only way txrx_init can fail here is if communication 1363 * with FW is suddenly broken. There's not much we can do 1364 * at this point - error messages have already been printed, 1365 * so we can continue on and the user can eventually do a 1366 * DOWN and UP to try to reset and clear the issue. 1367 */ 1368 err = ionic_txrx_init(lif); 1369 mutex_unlock(&lif->queue_lock); 1370 ionic_link_status_check_request(lif); 1371 netif_device_attach(lif->netdev); 1372 1373 return err; 1374 } 1375 1376 static int ionic_change_mtu(struct net_device *netdev, int new_mtu) 1377 { 1378 struct ionic_lif *lif = netdev_priv(netdev); 1379 struct ionic_admin_ctx ctx = { 1380 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1381 .cmd.lif_setattr = { 1382 .opcode = IONIC_CMD_LIF_SETATTR, 1383 .index = cpu_to_le16(lif->index), 1384 .attr = IONIC_LIF_ATTR_MTU, 1385 .mtu = cpu_to_le32(new_mtu), 1386 }, 1387 }; 1388 int err; 1389 1390 err = ionic_adminq_post_wait(lif, &ctx); 1391 if (err) 1392 return err; 1393 1394 netdev->mtu = new_mtu; 1395 /* if we're not running, nothing more to do */ 1396 if (!netif_running(netdev)) 1397 return 0; 1398 1399 ionic_stop_queues_reconfig(lif); 1400 return ionic_start_queues_reconfig(lif); 1401 } 1402 1403 static void ionic_tx_timeout_work(struct work_struct *ws) 1404 { 1405 struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work); 1406 1407 netdev_info(lif->netdev, "Tx Timeout recovery\n"); 1408 1409 /* if we were stopped before this scheduled job was launched, 1410 * don't bother the queues as they are already stopped. 1411 */ 1412 if (!netif_running(lif->netdev)) 1413 return; 1414 1415 ionic_stop_queues_reconfig(lif); 1416 ionic_start_queues_reconfig(lif); 1417 } 1418 1419 static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1420 { 1421 struct ionic_lif *lif = netdev_priv(netdev); 1422 1423 schedule_work(&lif->tx_timeout_work); 1424 } 1425 1426 static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, 1427 u16 vid) 1428 { 1429 struct ionic_lif *lif = netdev_priv(netdev); 1430 struct ionic_admin_ctx ctx = { 1431 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1432 .cmd.rx_filter_add = { 1433 .opcode = IONIC_CMD_RX_FILTER_ADD, 1434 .lif_index = cpu_to_le16(lif->index), 1435 .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_VLAN), 1436 .vlan.vlan = cpu_to_le16(vid), 1437 }, 1438 }; 1439 int err; 1440 1441 netdev_dbg(netdev, "rx_filter add VLAN %d\n", vid); 1442 err = ionic_adminq_post_wait(lif, &ctx); 1443 if (err) 1444 return err; 1445 1446 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx); 1447 } 1448 1449 static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, 1450 u16 vid) 1451 { 1452 struct ionic_lif *lif = netdev_priv(netdev); 1453 struct ionic_admin_ctx ctx = { 1454 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1455 .cmd.rx_filter_del = { 1456 .opcode = IONIC_CMD_RX_FILTER_DEL, 1457 .lif_index = cpu_to_le16(lif->index), 1458 }, 1459 }; 1460 struct ionic_rx_filter *f; 1461 1462 spin_lock_bh(&lif->rx_filters.lock); 1463 1464 f = ionic_rx_filter_by_vlan(lif, vid); 1465 if (!f) { 1466 spin_unlock_bh(&lif->rx_filters.lock); 1467 return -ENOENT; 1468 } 1469 1470 netdev_dbg(netdev, "rx_filter del VLAN %d (id %d)\n", 1471 vid, f->filter_id); 1472 1473 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id); 1474 ionic_rx_filter_free(lif, f); 1475 spin_unlock_bh(&lif->rx_filters.lock); 1476 1477 return ionic_adminq_post_wait(lif, &ctx); 1478 } 1479 1480 int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types, 1481 const u8 *key, const u32 *indir) 1482 { 1483 struct ionic_admin_ctx ctx = { 1484 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1485 .cmd.lif_setattr = { 1486 .opcode = IONIC_CMD_LIF_SETATTR, 1487 .attr = IONIC_LIF_ATTR_RSS, 1488 .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa), 1489 }, 1490 }; 1491 unsigned int i, tbl_sz; 1492 1493 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) { 1494 lif->rss_types = types; 1495 ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types); 1496 } 1497 1498 if (key) 1499 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE); 1500 1501 if (indir) { 1502 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1503 for (i = 0; i < tbl_sz; i++) 1504 lif->rss_ind_tbl[i] = indir[i]; 1505 } 1506 1507 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key, 1508 IONIC_RSS_HASH_KEY_SIZE); 1509 1510 return ionic_adminq_post_wait(lif, &ctx); 1511 } 1512 1513 static int ionic_lif_rss_init(struct ionic_lif *lif) 1514 { 1515 unsigned int tbl_sz; 1516 unsigned int i; 1517 1518 lif->rss_types = IONIC_RSS_TYPE_IPV4 | 1519 IONIC_RSS_TYPE_IPV4_TCP | 1520 IONIC_RSS_TYPE_IPV4_UDP | 1521 IONIC_RSS_TYPE_IPV6 | 1522 IONIC_RSS_TYPE_IPV6_TCP | 1523 IONIC_RSS_TYPE_IPV6_UDP; 1524 1525 /* Fill indirection table with 'default' values */ 1526 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1527 for (i = 0; i < tbl_sz; i++) 1528 lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs); 1529 1530 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1531 } 1532 1533 static void ionic_lif_rss_deinit(struct ionic_lif *lif) 1534 { 1535 int tbl_sz; 1536 1537 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1538 memset(lif->rss_ind_tbl, 0, tbl_sz); 1539 memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE); 1540 1541 ionic_lif_rss_config(lif, 0x0, NULL, NULL); 1542 } 1543 1544 static void ionic_txrx_disable(struct ionic_lif *lif) 1545 { 1546 unsigned int i; 1547 int err; 1548 1549 if (lif->txqcqs) { 1550 for (i = 0; i < lif->nxqs; i++) { 1551 err = ionic_qcq_disable(lif->txqcqs[i]); 1552 if (err == -ETIMEDOUT) 1553 break; 1554 } 1555 } 1556 1557 if (lif->rxqcqs) { 1558 for (i = 0; i < lif->nxqs; i++) { 1559 err = ionic_qcq_disable(lif->rxqcqs[i]); 1560 if (err == -ETIMEDOUT) 1561 break; 1562 } 1563 } 1564 } 1565 1566 static void ionic_txrx_deinit(struct ionic_lif *lif) 1567 { 1568 unsigned int i; 1569 1570 if (lif->txqcqs) { 1571 for (i = 0; i < lif->nxqs && lif->txqcqs[i]; i++) { 1572 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 1573 ionic_tx_flush(&lif->txqcqs[i]->cq); 1574 ionic_tx_empty(&lif->txqcqs[i]->q); 1575 } 1576 } 1577 1578 if (lif->rxqcqs) { 1579 for (i = 0; i < lif->nxqs && lif->rxqcqs[i]; i++) { 1580 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 1581 ionic_rx_flush(&lif->rxqcqs[i]->cq); 1582 ionic_rx_empty(&lif->rxqcqs[i]->q); 1583 } 1584 } 1585 lif->rx_mode = 0; 1586 } 1587 1588 static void ionic_txrx_free(struct ionic_lif *lif) 1589 { 1590 unsigned int i; 1591 1592 if (lif->txqcqs) { 1593 for (i = 0; i < lif->ionic->ntxqs_per_lif && lif->txqcqs[i]; i++) { 1594 ionic_qcq_free(lif, lif->txqcqs[i]); 1595 devm_kfree(lif->ionic->dev, lif->txqcqs[i]); 1596 lif->txqcqs[i] = NULL; 1597 } 1598 } 1599 1600 if (lif->rxqcqs) { 1601 for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) { 1602 ionic_qcq_free(lif, lif->rxqcqs[i]); 1603 devm_kfree(lif->ionic->dev, lif->rxqcqs[i]); 1604 lif->rxqcqs[i] = NULL; 1605 } 1606 } 1607 } 1608 1609 static int ionic_txrx_alloc(struct ionic_lif *lif) 1610 { 1611 unsigned int sg_desc_sz; 1612 unsigned int flags; 1613 unsigned int i; 1614 int err = 0; 1615 1616 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 1617 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 1618 sizeof(struct ionic_txq_sg_desc_v1)) 1619 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 1620 else 1621 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 1622 1623 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 1624 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 1625 flags |= IONIC_QCQ_F_INTR; 1626 for (i = 0; i < lif->nxqs; i++) { 1627 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 1628 lif->ntxq_descs, 1629 sizeof(struct ionic_txq_desc), 1630 sizeof(struct ionic_txq_comp), 1631 sg_desc_sz, 1632 lif->kern_pid, &lif->txqcqs[i]); 1633 if (err) 1634 goto err_out; 1635 1636 if (flags & IONIC_QCQ_F_INTR) 1637 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 1638 lif->txqcqs[i]->intr.index, 1639 lif->tx_coalesce_hw); 1640 1641 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 1642 } 1643 1644 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG | IONIC_QCQ_F_INTR; 1645 for (i = 0; i < lif->nxqs; i++) { 1646 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 1647 lif->nrxq_descs, 1648 sizeof(struct ionic_rxq_desc), 1649 sizeof(struct ionic_rxq_comp), 1650 sizeof(struct ionic_rxq_sg_desc), 1651 lif->kern_pid, &lif->rxqcqs[i]); 1652 if (err) 1653 goto err_out; 1654 1655 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 1656 lif->rxqcqs[i]->intr.index, 1657 lif->rx_coalesce_hw); 1658 1659 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 1660 ionic_link_qcq_interrupts(lif->rxqcqs[i], 1661 lif->txqcqs[i]); 1662 1663 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 1664 } 1665 1666 return 0; 1667 1668 err_out: 1669 ionic_txrx_free(lif); 1670 1671 return err; 1672 } 1673 1674 static int ionic_txrx_init(struct ionic_lif *lif) 1675 { 1676 unsigned int i; 1677 int err; 1678 1679 for (i = 0; i < lif->nxqs; i++) { 1680 err = ionic_lif_txq_init(lif, lif->txqcqs[i]); 1681 if (err) 1682 goto err_out; 1683 1684 err = ionic_lif_rxq_init(lif, lif->rxqcqs[i]); 1685 if (err) { 1686 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 1687 goto err_out; 1688 } 1689 } 1690 1691 if (lif->netdev->features & NETIF_F_RXHASH) 1692 ionic_lif_rss_init(lif); 1693 1694 ionic_set_rx_mode(lif->netdev); 1695 1696 return 0; 1697 1698 err_out: 1699 while (i--) { 1700 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 1701 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 1702 } 1703 1704 return err; 1705 } 1706 1707 static int ionic_txrx_enable(struct ionic_lif *lif) 1708 { 1709 int i, err; 1710 1711 for (i = 0; i < lif->nxqs; i++) { 1712 ionic_rx_fill(&lif->rxqcqs[i]->q); 1713 err = ionic_qcq_enable(lif->rxqcqs[i]); 1714 if (err) 1715 goto err_out; 1716 1717 err = ionic_qcq_enable(lif->txqcqs[i]); 1718 if (err) { 1719 if (err != -ETIMEDOUT) 1720 ionic_qcq_disable(lif->rxqcqs[i]); 1721 goto err_out; 1722 } 1723 } 1724 1725 return 0; 1726 1727 err_out: 1728 while (i--) { 1729 err = ionic_qcq_disable(lif->txqcqs[i]); 1730 if (err == -ETIMEDOUT) 1731 break; 1732 err = ionic_qcq_disable(lif->rxqcqs[i]); 1733 if (err == -ETIMEDOUT) 1734 break; 1735 } 1736 1737 return err; 1738 } 1739 1740 static int ionic_start_queues(struct ionic_lif *lif) 1741 { 1742 int err; 1743 1744 if (test_and_set_bit(IONIC_LIF_F_UP, lif->state)) 1745 return 0; 1746 1747 err = ionic_txrx_enable(lif); 1748 if (err) { 1749 clear_bit(IONIC_LIF_F_UP, lif->state); 1750 return err; 1751 } 1752 netif_tx_wake_all_queues(lif->netdev); 1753 1754 return 0; 1755 } 1756 1757 static int ionic_open(struct net_device *netdev) 1758 { 1759 struct ionic_lif *lif = netdev_priv(netdev); 1760 int err; 1761 1762 err = ionic_txrx_alloc(lif); 1763 if (err) 1764 return err; 1765 1766 err = ionic_txrx_init(lif); 1767 if (err) 1768 goto err_out; 1769 1770 err = netif_set_real_num_tx_queues(netdev, lif->nxqs); 1771 if (err) 1772 goto err_txrx_deinit; 1773 1774 err = netif_set_real_num_rx_queues(netdev, lif->nxqs); 1775 if (err) 1776 goto err_txrx_deinit; 1777 1778 /* don't start the queues until we have link */ 1779 if (netif_carrier_ok(netdev)) { 1780 err = ionic_start_queues(lif); 1781 if (err) 1782 goto err_txrx_deinit; 1783 } 1784 1785 return 0; 1786 1787 err_txrx_deinit: 1788 ionic_txrx_deinit(lif); 1789 err_out: 1790 ionic_txrx_free(lif); 1791 return err; 1792 } 1793 1794 static void ionic_stop_queues(struct ionic_lif *lif) 1795 { 1796 if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state)) 1797 return; 1798 1799 netif_tx_disable(lif->netdev); 1800 ionic_txrx_disable(lif); 1801 } 1802 1803 static int ionic_stop(struct net_device *netdev) 1804 { 1805 struct ionic_lif *lif = netdev_priv(netdev); 1806 1807 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 1808 return 0; 1809 1810 ionic_stop_queues(lif); 1811 ionic_txrx_deinit(lif); 1812 ionic_txrx_free(lif); 1813 1814 return 0; 1815 } 1816 1817 static int ionic_get_vf_config(struct net_device *netdev, 1818 int vf, struct ifla_vf_info *ivf) 1819 { 1820 struct ionic_lif *lif = netdev_priv(netdev); 1821 struct ionic *ionic = lif->ionic; 1822 int ret = 0; 1823 1824 if (!netif_device_present(netdev)) 1825 return -EBUSY; 1826 1827 down_read(&ionic->vf_op_lock); 1828 1829 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1830 ret = -EINVAL; 1831 } else { 1832 ivf->vf = vf; 1833 ivf->vlan = ionic->vfs[vf].vlanid; 1834 ivf->qos = 0; 1835 ivf->spoofchk = ionic->vfs[vf].spoofchk; 1836 ivf->linkstate = ionic->vfs[vf].linkstate; 1837 ivf->max_tx_rate = ionic->vfs[vf].maxrate; 1838 ivf->trusted = ionic->vfs[vf].trusted; 1839 ether_addr_copy(ivf->mac, ionic->vfs[vf].macaddr); 1840 } 1841 1842 up_read(&ionic->vf_op_lock); 1843 return ret; 1844 } 1845 1846 static int ionic_get_vf_stats(struct net_device *netdev, int vf, 1847 struct ifla_vf_stats *vf_stats) 1848 { 1849 struct ionic_lif *lif = netdev_priv(netdev); 1850 struct ionic *ionic = lif->ionic; 1851 struct ionic_lif_stats *vs; 1852 int ret = 0; 1853 1854 if (!netif_device_present(netdev)) 1855 return -EBUSY; 1856 1857 down_read(&ionic->vf_op_lock); 1858 1859 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1860 ret = -EINVAL; 1861 } else { 1862 memset(vf_stats, 0, sizeof(*vf_stats)); 1863 vs = &ionic->vfs[vf].stats; 1864 1865 vf_stats->rx_packets = le64_to_cpu(vs->rx_ucast_packets); 1866 vf_stats->tx_packets = le64_to_cpu(vs->tx_ucast_packets); 1867 vf_stats->rx_bytes = le64_to_cpu(vs->rx_ucast_bytes); 1868 vf_stats->tx_bytes = le64_to_cpu(vs->tx_ucast_bytes); 1869 vf_stats->broadcast = le64_to_cpu(vs->rx_bcast_packets); 1870 vf_stats->multicast = le64_to_cpu(vs->rx_mcast_packets); 1871 vf_stats->rx_dropped = le64_to_cpu(vs->rx_ucast_drop_packets) + 1872 le64_to_cpu(vs->rx_mcast_drop_packets) + 1873 le64_to_cpu(vs->rx_bcast_drop_packets); 1874 vf_stats->tx_dropped = le64_to_cpu(vs->tx_ucast_drop_packets) + 1875 le64_to_cpu(vs->tx_mcast_drop_packets) + 1876 le64_to_cpu(vs->tx_bcast_drop_packets); 1877 } 1878 1879 up_read(&ionic->vf_op_lock); 1880 return ret; 1881 } 1882 1883 static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 1884 { 1885 struct ionic_lif *lif = netdev_priv(netdev); 1886 struct ionic *ionic = lif->ionic; 1887 int ret; 1888 1889 if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac))) 1890 return -EINVAL; 1891 1892 if (!netif_device_present(netdev)) 1893 return -EBUSY; 1894 1895 down_write(&ionic->vf_op_lock); 1896 1897 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1898 ret = -EINVAL; 1899 } else { 1900 ret = ionic_set_vf_config(ionic, vf, IONIC_VF_ATTR_MAC, mac); 1901 if (!ret) 1902 ether_addr_copy(ionic->vfs[vf].macaddr, mac); 1903 } 1904 1905 up_write(&ionic->vf_op_lock); 1906 return ret; 1907 } 1908 1909 static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1910 u8 qos, __be16 proto) 1911 { 1912 struct ionic_lif *lif = netdev_priv(netdev); 1913 struct ionic *ionic = lif->ionic; 1914 int ret; 1915 1916 /* until someday when we support qos */ 1917 if (qos) 1918 return -EINVAL; 1919 1920 if (vlan > 4095) 1921 return -EINVAL; 1922 1923 if (proto != htons(ETH_P_8021Q)) 1924 return -EPROTONOSUPPORT; 1925 1926 if (!netif_device_present(netdev)) 1927 return -EBUSY; 1928 1929 down_write(&ionic->vf_op_lock); 1930 1931 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1932 ret = -EINVAL; 1933 } else { 1934 ret = ionic_set_vf_config(ionic, vf, 1935 IONIC_VF_ATTR_VLAN, (u8 *)&vlan); 1936 if (!ret) 1937 ionic->vfs[vf].vlanid = vlan; 1938 } 1939 1940 up_write(&ionic->vf_op_lock); 1941 return ret; 1942 } 1943 1944 static int ionic_set_vf_rate(struct net_device *netdev, int vf, 1945 int tx_min, int tx_max) 1946 { 1947 struct ionic_lif *lif = netdev_priv(netdev); 1948 struct ionic *ionic = lif->ionic; 1949 int ret; 1950 1951 /* setting the min just seems silly */ 1952 if (tx_min) 1953 return -EINVAL; 1954 1955 if (!netif_device_present(netdev)) 1956 return -EBUSY; 1957 1958 down_write(&ionic->vf_op_lock); 1959 1960 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1961 ret = -EINVAL; 1962 } else { 1963 ret = ionic_set_vf_config(ionic, vf, 1964 IONIC_VF_ATTR_RATE, (u8 *)&tx_max); 1965 if (!ret) 1966 lif->ionic->vfs[vf].maxrate = tx_max; 1967 } 1968 1969 up_write(&ionic->vf_op_lock); 1970 return ret; 1971 } 1972 1973 static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set) 1974 { 1975 struct ionic_lif *lif = netdev_priv(netdev); 1976 struct ionic *ionic = lif->ionic; 1977 u8 data = set; /* convert to u8 for config */ 1978 int ret; 1979 1980 if (!netif_device_present(netdev)) 1981 return -EBUSY; 1982 1983 down_write(&ionic->vf_op_lock); 1984 1985 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1986 ret = -EINVAL; 1987 } else { 1988 ret = ionic_set_vf_config(ionic, vf, 1989 IONIC_VF_ATTR_SPOOFCHK, &data); 1990 if (!ret) 1991 ionic->vfs[vf].spoofchk = data; 1992 } 1993 1994 up_write(&ionic->vf_op_lock); 1995 return ret; 1996 } 1997 1998 static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set) 1999 { 2000 struct ionic_lif *lif = netdev_priv(netdev); 2001 struct ionic *ionic = lif->ionic; 2002 u8 data = set; /* convert to u8 for config */ 2003 int ret; 2004 2005 if (!netif_device_present(netdev)) 2006 return -EBUSY; 2007 2008 down_write(&ionic->vf_op_lock); 2009 2010 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2011 ret = -EINVAL; 2012 } else { 2013 ret = ionic_set_vf_config(ionic, vf, 2014 IONIC_VF_ATTR_TRUST, &data); 2015 if (!ret) 2016 ionic->vfs[vf].trusted = data; 2017 } 2018 2019 up_write(&ionic->vf_op_lock); 2020 return ret; 2021 } 2022 2023 static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set) 2024 { 2025 struct ionic_lif *lif = netdev_priv(netdev); 2026 struct ionic *ionic = lif->ionic; 2027 u8 data; 2028 int ret; 2029 2030 switch (set) { 2031 case IFLA_VF_LINK_STATE_ENABLE: 2032 data = IONIC_VF_LINK_STATUS_UP; 2033 break; 2034 case IFLA_VF_LINK_STATE_DISABLE: 2035 data = IONIC_VF_LINK_STATUS_DOWN; 2036 break; 2037 case IFLA_VF_LINK_STATE_AUTO: 2038 data = IONIC_VF_LINK_STATUS_AUTO; 2039 break; 2040 default: 2041 return -EINVAL; 2042 } 2043 2044 if (!netif_device_present(netdev)) 2045 return -EBUSY; 2046 2047 down_write(&ionic->vf_op_lock); 2048 2049 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2050 ret = -EINVAL; 2051 } else { 2052 ret = ionic_set_vf_config(ionic, vf, 2053 IONIC_VF_ATTR_LINKSTATE, &data); 2054 if (!ret) 2055 ionic->vfs[vf].linkstate = set; 2056 } 2057 2058 up_write(&ionic->vf_op_lock); 2059 return ret; 2060 } 2061 2062 static const struct net_device_ops ionic_netdev_ops = { 2063 .ndo_open = ionic_open, 2064 .ndo_stop = ionic_stop, 2065 .ndo_start_xmit = ionic_start_xmit, 2066 .ndo_get_stats64 = ionic_get_stats64, 2067 .ndo_set_rx_mode = ionic_set_rx_mode, 2068 .ndo_set_features = ionic_set_features, 2069 .ndo_set_mac_address = ionic_set_mac_address, 2070 .ndo_validate_addr = eth_validate_addr, 2071 .ndo_tx_timeout = ionic_tx_timeout, 2072 .ndo_change_mtu = ionic_change_mtu, 2073 .ndo_vlan_rx_add_vid = ionic_vlan_rx_add_vid, 2074 .ndo_vlan_rx_kill_vid = ionic_vlan_rx_kill_vid, 2075 .ndo_set_vf_vlan = ionic_set_vf_vlan, 2076 .ndo_set_vf_trust = ionic_set_vf_trust, 2077 .ndo_set_vf_mac = ionic_set_vf_mac, 2078 .ndo_set_vf_rate = ionic_set_vf_rate, 2079 .ndo_set_vf_spoofchk = ionic_set_vf_spoofchk, 2080 .ndo_get_vf_config = ionic_get_vf_config, 2081 .ndo_set_vf_link_state = ionic_set_vf_link_state, 2082 .ndo_get_vf_stats = ionic_get_vf_stats, 2083 }; 2084 2085 static void ionic_swap_queues(struct ionic_qcq *a, struct ionic_qcq *b) 2086 { 2087 /* only swapping the queues, not the napi, flags, or other stuff */ 2088 swap(a->q.num_descs, b->q.num_descs); 2089 swap(a->q.base, b->q.base); 2090 swap(a->q.base_pa, b->q.base_pa); 2091 swap(a->q.info, b->q.info); 2092 swap(a->q_base, b->q_base); 2093 swap(a->q_base_pa, b->q_base_pa); 2094 swap(a->q_size, b->q_size); 2095 2096 swap(a->q.sg_base, b->q.sg_base); 2097 swap(a->q.sg_base_pa, b->q.sg_base_pa); 2098 swap(a->sg_base, b->sg_base); 2099 swap(a->sg_base_pa, b->sg_base_pa); 2100 swap(a->sg_size, b->sg_size); 2101 2102 swap(a->cq.num_descs, b->cq.num_descs); 2103 swap(a->cq.base, b->cq.base); 2104 swap(a->cq.base_pa, b->cq.base_pa); 2105 swap(a->cq.info, b->cq.info); 2106 swap(a->cq_base, b->cq_base); 2107 swap(a->cq_base_pa, b->cq_base_pa); 2108 swap(a->cq_size, b->cq_size); 2109 } 2110 2111 int ionic_reconfigure_queues(struct ionic_lif *lif, 2112 struct ionic_queue_params *qparam) 2113 { 2114 struct ionic_qcq **tx_qcqs = NULL; 2115 struct ionic_qcq **rx_qcqs = NULL; 2116 unsigned int sg_desc_sz; 2117 unsigned int flags; 2118 int err = -ENOMEM; 2119 unsigned int i; 2120 2121 /* allocate temporary qcq arrays to hold new queue structs */ 2122 if (qparam->nxqs != lif->nxqs || qparam->ntxq_descs != lif->ntxq_descs) { 2123 tx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->ntxqs_per_lif, 2124 sizeof(struct ionic_qcq *), GFP_KERNEL); 2125 if (!tx_qcqs) 2126 goto err_out; 2127 } 2128 if (qparam->nxqs != lif->nxqs || qparam->nrxq_descs != lif->nrxq_descs) { 2129 rx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->nrxqs_per_lif, 2130 sizeof(struct ionic_qcq *), GFP_KERNEL); 2131 if (!rx_qcqs) 2132 goto err_out; 2133 } 2134 2135 /* allocate new desc_info and rings, but leave the interrupt setup 2136 * until later so as to not mess with the still-running queues 2137 */ 2138 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 2139 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 2140 sizeof(struct ionic_txq_sg_desc_v1)) 2141 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 2142 else 2143 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 2144 2145 if (tx_qcqs) { 2146 for (i = 0; i < qparam->nxqs; i++) { 2147 flags = lif->txqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2148 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 2149 qparam->ntxq_descs, 2150 sizeof(struct ionic_txq_desc), 2151 sizeof(struct ionic_txq_comp), 2152 sg_desc_sz, 2153 lif->kern_pid, &tx_qcqs[i]); 2154 if (err) 2155 goto err_out; 2156 } 2157 } 2158 2159 if (rx_qcqs) { 2160 for (i = 0; i < qparam->nxqs; i++) { 2161 flags = lif->rxqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2162 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 2163 qparam->nrxq_descs, 2164 sizeof(struct ionic_rxq_desc), 2165 sizeof(struct ionic_rxq_comp), 2166 sizeof(struct ionic_rxq_sg_desc), 2167 lif->kern_pid, &rx_qcqs[i]); 2168 if (err) 2169 goto err_out; 2170 } 2171 } 2172 2173 /* stop and clean the queues */ 2174 ionic_stop_queues_reconfig(lif); 2175 2176 if (qparam->nxqs != lif->nxqs) { 2177 err = netif_set_real_num_tx_queues(lif->netdev, qparam->nxqs); 2178 if (err) 2179 goto err_out_reinit_unlock; 2180 err = netif_set_real_num_rx_queues(lif->netdev, qparam->nxqs); 2181 if (err) { 2182 netif_set_real_num_tx_queues(lif->netdev, lif->nxqs); 2183 goto err_out_reinit_unlock; 2184 } 2185 } 2186 2187 /* swap new desc_info and rings, keeping existing interrupt config */ 2188 if (tx_qcqs) { 2189 lif->ntxq_descs = qparam->ntxq_descs; 2190 for (i = 0; i < qparam->nxqs; i++) 2191 ionic_swap_queues(lif->txqcqs[i], tx_qcqs[i]); 2192 } 2193 2194 if (rx_qcqs) { 2195 lif->nrxq_descs = qparam->nrxq_descs; 2196 for (i = 0; i < qparam->nxqs; i++) 2197 ionic_swap_queues(lif->rxqcqs[i], rx_qcqs[i]); 2198 } 2199 2200 /* if we need to change the interrupt layout, this is the time */ 2201 if (qparam->intr_split != test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) || 2202 qparam->nxqs != lif->nxqs) { 2203 if (qparam->intr_split) { 2204 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 2205 } else { 2206 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 2207 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 2208 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 2209 } 2210 2211 /* clear existing interrupt assignments */ 2212 for (i = 0; i < lif->ionic->ntxqs_per_lif; i++) { 2213 ionic_qcq_intr_free(lif, lif->txqcqs[i]); 2214 ionic_qcq_intr_free(lif, lif->rxqcqs[i]); 2215 } 2216 2217 /* re-assign the interrupts */ 2218 for (i = 0; i < qparam->nxqs; i++) { 2219 lif->rxqcqs[i]->flags |= IONIC_QCQ_F_INTR; 2220 err = ionic_alloc_qcq_interrupt(lif, lif->rxqcqs[i]); 2221 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2222 lif->rxqcqs[i]->intr.index, 2223 lif->rx_coalesce_hw); 2224 2225 if (qparam->intr_split) { 2226 lif->txqcqs[i]->flags |= IONIC_QCQ_F_INTR; 2227 err = ionic_alloc_qcq_interrupt(lif, lif->txqcqs[i]); 2228 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2229 lif->txqcqs[i]->intr.index, 2230 lif->tx_coalesce_hw); 2231 } else { 2232 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2233 ionic_link_qcq_interrupts(lif->rxqcqs[i], lif->txqcqs[i]); 2234 } 2235 } 2236 } 2237 2238 swap(lif->nxqs, qparam->nxqs); 2239 2240 err_out_reinit_unlock: 2241 /* re-init the queues, but don't loose an error code */ 2242 if (err) 2243 ionic_start_queues_reconfig(lif); 2244 else 2245 err = ionic_start_queues_reconfig(lif); 2246 2247 err_out: 2248 /* free old allocs without cleaning intr */ 2249 for (i = 0; i < qparam->nxqs; i++) { 2250 if (tx_qcqs && tx_qcqs[i]) { 2251 tx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2252 ionic_qcq_free(lif, tx_qcqs[i]); 2253 devm_kfree(lif->ionic->dev, tx_qcqs[i]); 2254 tx_qcqs[i] = NULL; 2255 } 2256 if (rx_qcqs && rx_qcqs[i]) { 2257 rx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2258 ionic_qcq_free(lif, rx_qcqs[i]); 2259 devm_kfree(lif->ionic->dev, rx_qcqs[i]); 2260 rx_qcqs[i] = NULL; 2261 } 2262 } 2263 2264 /* free q array */ 2265 if (rx_qcqs) { 2266 devm_kfree(lif->ionic->dev, rx_qcqs); 2267 rx_qcqs = NULL; 2268 } 2269 if (tx_qcqs) { 2270 devm_kfree(lif->ionic->dev, tx_qcqs); 2271 tx_qcqs = NULL; 2272 } 2273 2274 /* clean the unused dma and info allocations when new set is smaller 2275 * than the full array, but leave the qcq shells in place 2276 */ 2277 for (i = lif->nxqs; i < lif->ionic->ntxqs_per_lif; i++) { 2278 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2279 ionic_qcq_free(lif, lif->txqcqs[i]); 2280 2281 lif->rxqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2282 ionic_qcq_free(lif, lif->rxqcqs[i]); 2283 } 2284 2285 return err; 2286 } 2287 2288 int ionic_lif_alloc(struct ionic *ionic) 2289 { 2290 struct device *dev = ionic->dev; 2291 union ionic_lif_identity *lid; 2292 struct net_device *netdev; 2293 struct ionic_lif *lif; 2294 int tbl_sz; 2295 int err; 2296 2297 lid = kzalloc(sizeof(*lid), GFP_KERNEL); 2298 if (!lid) 2299 return -ENOMEM; 2300 2301 netdev = alloc_etherdev_mqs(sizeof(*lif), 2302 ionic->ntxqs_per_lif, ionic->ntxqs_per_lif); 2303 if (!netdev) { 2304 dev_err(dev, "Cannot allocate netdev, aborting\n"); 2305 err = -ENOMEM; 2306 goto err_out_free_lid; 2307 } 2308 2309 SET_NETDEV_DEV(netdev, dev); 2310 2311 lif = netdev_priv(netdev); 2312 lif->netdev = netdev; 2313 ionic->lif = lif; 2314 netdev->netdev_ops = &ionic_netdev_ops; 2315 ionic_ethtool_set_ops(netdev); 2316 2317 netdev->watchdog_timeo = 2 * HZ; 2318 netif_carrier_off(netdev); 2319 2320 lif->identity = lid; 2321 lif->lif_type = IONIC_LIF_TYPE_CLASSIC; 2322 ionic_lif_identify(ionic, lif->lif_type, lif->identity); 2323 lif->netdev->min_mtu = max_t(unsigned int, ETH_MIN_MTU, 2324 le32_to_cpu(lif->identity->eth.min_frame_size)); 2325 lif->netdev->max_mtu = 2326 le32_to_cpu(lif->identity->eth.max_frame_size) - ETH_HLEN - VLAN_HLEN; 2327 2328 lif->neqs = ionic->neqs_per_lif; 2329 lif->nxqs = ionic->ntxqs_per_lif; 2330 2331 lif->ionic = ionic; 2332 lif->index = 0; 2333 lif->ntxq_descs = IONIC_DEF_TXRX_DESC; 2334 lif->nrxq_descs = IONIC_DEF_TXRX_DESC; 2335 lif->tx_budget = IONIC_TX_BUDGET_DEFAULT; 2336 2337 /* Convert the default coalesce value to actual hw resolution */ 2338 lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT; 2339 lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic, 2340 lif->rx_coalesce_usecs); 2341 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 2342 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 2343 2344 snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index); 2345 2346 spin_lock_init(&lif->adminq_lock); 2347 2348 spin_lock_init(&lif->deferred.lock); 2349 INIT_LIST_HEAD(&lif->deferred.list); 2350 INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work); 2351 2352 /* allocate lif info */ 2353 lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE); 2354 lif->info = dma_alloc_coherent(dev, lif->info_sz, 2355 &lif->info_pa, GFP_KERNEL); 2356 if (!lif->info) { 2357 dev_err(dev, "Failed to allocate lif info, aborting\n"); 2358 err = -ENOMEM; 2359 goto err_out_free_netdev; 2360 } 2361 2362 ionic_debugfs_add_lif(lif); 2363 2364 /* allocate control queues and txrx queue arrays */ 2365 ionic_lif_queue_identify(lif); 2366 err = ionic_qcqs_alloc(lif); 2367 if (err) 2368 goto err_out_free_lif_info; 2369 2370 /* allocate rss indirection table */ 2371 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 2372 lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz; 2373 lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz, 2374 &lif->rss_ind_tbl_pa, 2375 GFP_KERNEL); 2376 2377 if (!lif->rss_ind_tbl) { 2378 err = -ENOMEM; 2379 dev_err(dev, "Failed to allocate rss indirection table, aborting\n"); 2380 goto err_out_free_qcqs; 2381 } 2382 netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE); 2383 2384 return 0; 2385 2386 err_out_free_qcqs: 2387 ionic_qcqs_free(lif); 2388 err_out_free_lif_info: 2389 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 2390 lif->info = NULL; 2391 lif->info_pa = 0; 2392 err_out_free_netdev: 2393 free_netdev(lif->netdev); 2394 lif = NULL; 2395 err_out_free_lid: 2396 kfree(lid); 2397 2398 return err; 2399 } 2400 2401 static void ionic_lif_reset(struct ionic_lif *lif) 2402 { 2403 struct ionic_dev *idev = &lif->ionic->idev; 2404 2405 mutex_lock(&lif->ionic->dev_cmd_lock); 2406 ionic_dev_cmd_lif_reset(idev, lif->index); 2407 ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2408 mutex_unlock(&lif->ionic->dev_cmd_lock); 2409 } 2410 2411 static void ionic_lif_handle_fw_down(struct ionic_lif *lif) 2412 { 2413 struct ionic *ionic = lif->ionic; 2414 2415 if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2416 return; 2417 2418 dev_info(ionic->dev, "FW Down: Stopping LIFs\n"); 2419 2420 netif_device_detach(lif->netdev); 2421 2422 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 2423 dev_info(ionic->dev, "Surprise FW stop, stopping queues\n"); 2424 mutex_lock(&lif->queue_lock); 2425 ionic_stop_queues(lif); 2426 mutex_unlock(&lif->queue_lock); 2427 } 2428 2429 if (netif_running(lif->netdev)) { 2430 ionic_txrx_deinit(lif); 2431 ionic_txrx_free(lif); 2432 } 2433 ionic_lif_deinit(lif); 2434 ionic_reset(ionic); 2435 ionic_qcqs_free(lif); 2436 2437 dev_info(ionic->dev, "FW Down: LIFs stopped\n"); 2438 } 2439 2440 static void ionic_lif_handle_fw_up(struct ionic_lif *lif) 2441 { 2442 struct ionic *ionic = lif->ionic; 2443 int err; 2444 2445 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2446 return; 2447 2448 dev_info(ionic->dev, "FW Up: restarting LIFs\n"); 2449 2450 ionic_init_devinfo(ionic); 2451 ionic_port_init(ionic); 2452 err = ionic_qcqs_alloc(lif); 2453 if (err) 2454 goto err_out; 2455 2456 err = ionic_lif_init(lif); 2457 if (err) 2458 goto err_qcqs_free; 2459 2460 if (lif->registered) 2461 ionic_lif_set_netdev_info(lif); 2462 2463 ionic_rx_filter_replay(lif); 2464 2465 if (netif_running(lif->netdev)) { 2466 err = ionic_txrx_alloc(lif); 2467 if (err) 2468 goto err_lifs_deinit; 2469 2470 err = ionic_txrx_init(lif); 2471 if (err) 2472 goto err_txrx_free; 2473 } 2474 2475 clear_bit(IONIC_LIF_F_FW_RESET, lif->state); 2476 ionic_link_status_check_request(lif); 2477 netif_device_attach(lif->netdev); 2478 dev_info(ionic->dev, "FW Up: LIFs restarted\n"); 2479 2480 return; 2481 2482 err_txrx_free: 2483 ionic_txrx_free(lif); 2484 err_lifs_deinit: 2485 ionic_lif_deinit(lif); 2486 err_qcqs_free: 2487 ionic_qcqs_free(lif); 2488 err_out: 2489 dev_err(ionic->dev, "FW Up: LIFs restart failed - err %d\n", err); 2490 } 2491 2492 void ionic_lif_free(struct ionic_lif *lif) 2493 { 2494 struct device *dev = lif->ionic->dev; 2495 2496 /* free rss indirection table */ 2497 dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl, 2498 lif->rss_ind_tbl_pa); 2499 lif->rss_ind_tbl = NULL; 2500 lif->rss_ind_tbl_pa = 0; 2501 2502 /* free queues */ 2503 ionic_qcqs_free(lif); 2504 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2505 ionic_lif_reset(lif); 2506 2507 /* free lif info */ 2508 kfree(lif->identity); 2509 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 2510 lif->info = NULL; 2511 lif->info_pa = 0; 2512 2513 /* unmap doorbell page */ 2514 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 2515 lif->kern_dbpage = NULL; 2516 kfree(lif->dbid_inuse); 2517 lif->dbid_inuse = NULL; 2518 2519 /* free netdev & lif */ 2520 ionic_debugfs_del_lif(lif); 2521 free_netdev(lif->netdev); 2522 } 2523 2524 void ionic_lif_deinit(struct ionic_lif *lif) 2525 { 2526 if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state)) 2527 return; 2528 2529 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 2530 cancel_work_sync(&lif->deferred.work); 2531 cancel_work_sync(&lif->tx_timeout_work); 2532 ionic_rx_filters_deinit(lif); 2533 if (lif->netdev->features & NETIF_F_RXHASH) 2534 ionic_lif_rss_deinit(lif); 2535 } 2536 2537 napi_disable(&lif->adminqcq->napi); 2538 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 2539 ionic_lif_qcq_deinit(lif, lif->adminqcq); 2540 2541 mutex_destroy(&lif->queue_lock); 2542 ionic_lif_reset(lif); 2543 } 2544 2545 static int ionic_lif_adminq_init(struct ionic_lif *lif) 2546 { 2547 struct device *dev = lif->ionic->dev; 2548 struct ionic_q_init_comp comp; 2549 struct ionic_dev *idev; 2550 struct ionic_qcq *qcq; 2551 struct ionic_queue *q; 2552 int err; 2553 2554 idev = &lif->ionic->idev; 2555 qcq = lif->adminqcq; 2556 q = &qcq->q; 2557 2558 mutex_lock(&lif->ionic->dev_cmd_lock); 2559 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index); 2560 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2561 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 2562 mutex_unlock(&lif->ionic->dev_cmd_lock); 2563 if (err) { 2564 netdev_err(lif->netdev, "adminq init failed %d\n", err); 2565 return err; 2566 } 2567 2568 q->hw_type = comp.hw_type; 2569 q->hw_index = le32_to_cpu(comp.hw_index); 2570 q->dbval = IONIC_DBELL_QID(q->hw_index); 2571 2572 dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type); 2573 dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index); 2574 2575 netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi, 2576 NAPI_POLL_WEIGHT); 2577 2578 napi_enable(&qcq->napi); 2579 2580 if (qcq->flags & IONIC_QCQ_F_INTR) 2581 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 2582 IONIC_INTR_MASK_CLEAR); 2583 2584 qcq->flags |= IONIC_QCQ_F_INITED; 2585 2586 return 0; 2587 } 2588 2589 static int ionic_lif_notifyq_init(struct ionic_lif *lif) 2590 { 2591 struct ionic_qcq *qcq = lif->notifyqcq; 2592 struct device *dev = lif->ionic->dev; 2593 struct ionic_queue *q = &qcq->q; 2594 int err; 2595 2596 struct ionic_admin_ctx ctx = { 2597 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 2598 .cmd.q_init = { 2599 .opcode = IONIC_CMD_Q_INIT, 2600 .lif_index = cpu_to_le16(lif->index), 2601 .type = q->type, 2602 .ver = lif->qtype_info[q->type].version, 2603 .index = cpu_to_le32(q->index), 2604 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 2605 IONIC_QINIT_F_ENA), 2606 .intr_index = cpu_to_le16(lif->adminqcq->intr.index), 2607 .pid = cpu_to_le16(q->pid), 2608 .ring_size = ilog2(q->num_descs), 2609 .ring_base = cpu_to_le64(q->base_pa), 2610 } 2611 }; 2612 2613 dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid); 2614 dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index); 2615 dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 2616 dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 2617 2618 err = ionic_adminq_post_wait(lif, &ctx); 2619 if (err) 2620 return err; 2621 2622 lif->last_eid = 0; 2623 q->hw_type = ctx.comp.q_init.hw_type; 2624 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 2625 q->dbval = IONIC_DBELL_QID(q->hw_index); 2626 2627 dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type); 2628 dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index); 2629 2630 /* preset the callback info */ 2631 q->info[0].cb_arg = lif; 2632 2633 qcq->flags |= IONIC_QCQ_F_INITED; 2634 2635 return 0; 2636 } 2637 2638 static int ionic_station_set(struct ionic_lif *lif) 2639 { 2640 struct net_device *netdev = lif->netdev; 2641 struct ionic_admin_ctx ctx = { 2642 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 2643 .cmd.lif_getattr = { 2644 .opcode = IONIC_CMD_LIF_GETATTR, 2645 .index = cpu_to_le16(lif->index), 2646 .attr = IONIC_LIF_ATTR_MAC, 2647 }, 2648 }; 2649 struct sockaddr addr; 2650 int err; 2651 2652 err = ionic_adminq_post_wait(lif, &ctx); 2653 if (err) 2654 return err; 2655 netdev_dbg(lif->netdev, "found initial MAC addr %pM\n", 2656 ctx.comp.lif_getattr.mac); 2657 if (is_zero_ether_addr(ctx.comp.lif_getattr.mac)) 2658 return 0; 2659 2660 if (!is_zero_ether_addr(netdev->dev_addr)) { 2661 /* If the netdev mac is non-zero and doesn't match the default 2662 * device address, it was set by something earlier and we're 2663 * likely here again after a fw-upgrade reset. We need to be 2664 * sure the netdev mac is in our filter list. 2665 */ 2666 if (!ether_addr_equal(ctx.comp.lif_getattr.mac, 2667 netdev->dev_addr)) 2668 ionic_lif_addr(lif, netdev->dev_addr, true); 2669 } else { 2670 /* Update the netdev mac with the device's mac */ 2671 memcpy(addr.sa_data, ctx.comp.lif_getattr.mac, netdev->addr_len); 2672 addr.sa_family = AF_INET; 2673 err = eth_prepare_mac_addr_change(netdev, &addr); 2674 if (err) { 2675 netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n", 2676 addr.sa_data, err); 2677 return 0; 2678 } 2679 2680 eth_commit_mac_addr_change(netdev, &addr); 2681 } 2682 2683 netdev_dbg(lif->netdev, "adding station MAC addr %pM\n", 2684 netdev->dev_addr); 2685 ionic_lif_addr(lif, netdev->dev_addr, true); 2686 2687 return 0; 2688 } 2689 2690 int ionic_lif_init(struct ionic_lif *lif) 2691 { 2692 struct ionic_dev *idev = &lif->ionic->idev; 2693 struct device *dev = lif->ionic->dev; 2694 struct ionic_lif_init_comp comp; 2695 int dbpage_num; 2696 int err; 2697 2698 mutex_lock(&lif->ionic->dev_cmd_lock); 2699 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa); 2700 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2701 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 2702 mutex_unlock(&lif->ionic->dev_cmd_lock); 2703 if (err) 2704 return err; 2705 2706 lif->hw_index = le16_to_cpu(comp.hw_index); 2707 mutex_init(&lif->queue_lock); 2708 2709 /* now that we have the hw_index we can figure out our doorbell page */ 2710 lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif); 2711 if (!lif->dbid_count) { 2712 dev_err(dev, "No doorbell pages, aborting\n"); 2713 return -EINVAL; 2714 } 2715 2716 lif->dbid_inuse = bitmap_alloc(lif->dbid_count, GFP_KERNEL); 2717 if (!lif->dbid_inuse) { 2718 dev_err(dev, "Failed alloc doorbell id bitmap, aborting\n"); 2719 return -ENOMEM; 2720 } 2721 2722 /* first doorbell id reserved for kernel (dbid aka pid == zero) */ 2723 set_bit(0, lif->dbid_inuse); 2724 lif->kern_pid = 0; 2725 2726 dbpage_num = ionic_db_page_num(lif, lif->kern_pid); 2727 lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num); 2728 if (!lif->kern_dbpage) { 2729 dev_err(dev, "Cannot map dbpage, aborting\n"); 2730 err = -ENOMEM; 2731 goto err_out_free_dbid; 2732 } 2733 2734 err = ionic_lif_adminq_init(lif); 2735 if (err) 2736 goto err_out_adminq_deinit; 2737 2738 if (lif->ionic->nnqs_per_lif) { 2739 err = ionic_lif_notifyq_init(lif); 2740 if (err) 2741 goto err_out_notifyq_deinit; 2742 } 2743 2744 err = ionic_init_nic_features(lif); 2745 if (err) 2746 goto err_out_notifyq_deinit; 2747 2748 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 2749 err = ionic_rx_filters_init(lif); 2750 if (err) 2751 goto err_out_notifyq_deinit; 2752 } 2753 2754 err = ionic_station_set(lif); 2755 if (err) 2756 goto err_out_notifyq_deinit; 2757 2758 lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT; 2759 2760 set_bit(IONIC_LIF_F_INITED, lif->state); 2761 2762 INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work); 2763 2764 return 0; 2765 2766 err_out_notifyq_deinit: 2767 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 2768 err_out_adminq_deinit: 2769 ionic_lif_qcq_deinit(lif, lif->adminqcq); 2770 ionic_lif_reset(lif); 2771 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 2772 lif->kern_dbpage = NULL; 2773 err_out_free_dbid: 2774 kfree(lif->dbid_inuse); 2775 lif->dbid_inuse = NULL; 2776 2777 return err; 2778 } 2779 2780 static void ionic_lif_notify_work(struct work_struct *ws) 2781 { 2782 } 2783 2784 static void ionic_lif_set_netdev_info(struct ionic_lif *lif) 2785 { 2786 struct ionic_admin_ctx ctx = { 2787 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 2788 .cmd.lif_setattr = { 2789 .opcode = IONIC_CMD_LIF_SETATTR, 2790 .index = cpu_to_le16(lif->index), 2791 .attr = IONIC_LIF_ATTR_NAME, 2792 }, 2793 }; 2794 2795 strlcpy(ctx.cmd.lif_setattr.name, lif->netdev->name, 2796 sizeof(ctx.cmd.lif_setattr.name)); 2797 2798 ionic_adminq_post_wait(lif, &ctx); 2799 } 2800 2801 static struct ionic_lif *ionic_netdev_lif(struct net_device *netdev) 2802 { 2803 if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit) 2804 return NULL; 2805 2806 return netdev_priv(netdev); 2807 } 2808 2809 static int ionic_lif_notify(struct notifier_block *nb, 2810 unsigned long event, void *info) 2811 { 2812 struct net_device *ndev = netdev_notifier_info_to_dev(info); 2813 struct ionic *ionic = container_of(nb, struct ionic, nb); 2814 struct ionic_lif *lif = ionic_netdev_lif(ndev); 2815 2816 if (!lif || lif->ionic != ionic) 2817 return NOTIFY_DONE; 2818 2819 switch (event) { 2820 case NETDEV_CHANGENAME: 2821 ionic_lif_set_netdev_info(lif); 2822 break; 2823 } 2824 2825 return NOTIFY_DONE; 2826 } 2827 2828 int ionic_lif_register(struct ionic_lif *lif) 2829 { 2830 int err; 2831 2832 INIT_WORK(&lif->ionic->nb_work, ionic_lif_notify_work); 2833 2834 lif->ionic->nb.notifier_call = ionic_lif_notify; 2835 2836 err = register_netdevice_notifier(&lif->ionic->nb); 2837 if (err) 2838 lif->ionic->nb.notifier_call = NULL; 2839 2840 /* only register LIF0 for now */ 2841 err = register_netdev(lif->netdev); 2842 if (err) { 2843 dev_err(lif->ionic->dev, "Cannot register net device, aborting\n"); 2844 return err; 2845 } 2846 lif->registered = true; 2847 ionic_lif_set_netdev_info(lif); 2848 2849 return 0; 2850 } 2851 2852 void ionic_lif_unregister(struct ionic_lif *lif) 2853 { 2854 if (lif->ionic->nb.notifier_call) { 2855 unregister_netdevice_notifier(&lif->ionic->nb); 2856 cancel_work_sync(&lif->ionic->nb_work); 2857 lif->ionic->nb.notifier_call = NULL; 2858 } 2859 2860 if (lif->netdev->reg_state == NETREG_REGISTERED) 2861 unregister_netdev(lif->netdev); 2862 lif->registered = false; 2863 } 2864 2865 static void ionic_lif_queue_identify(struct ionic_lif *lif) 2866 { 2867 struct ionic *ionic = lif->ionic; 2868 union ionic_q_identity *q_ident; 2869 struct ionic_dev *idev; 2870 int qtype; 2871 int err; 2872 2873 idev = &lif->ionic->idev; 2874 q_ident = (union ionic_q_identity *)&idev->dev_cmd_regs->data; 2875 2876 for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) { 2877 struct ionic_qtype_info *qti = &lif->qtype_info[qtype]; 2878 2879 /* filter out the ones we know about */ 2880 switch (qtype) { 2881 case IONIC_QTYPE_ADMINQ: 2882 case IONIC_QTYPE_NOTIFYQ: 2883 case IONIC_QTYPE_RXQ: 2884 case IONIC_QTYPE_TXQ: 2885 break; 2886 default: 2887 continue; 2888 } 2889 2890 memset(qti, 0, sizeof(*qti)); 2891 2892 mutex_lock(&ionic->dev_cmd_lock); 2893 ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype, 2894 ionic_qtype_versions[qtype]); 2895 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 2896 if (!err) { 2897 qti->version = q_ident->version; 2898 qti->supported = q_ident->supported; 2899 qti->features = le64_to_cpu(q_ident->features); 2900 qti->desc_sz = le16_to_cpu(q_ident->desc_sz); 2901 qti->comp_sz = le16_to_cpu(q_ident->comp_sz); 2902 qti->sg_desc_sz = le16_to_cpu(q_ident->sg_desc_sz); 2903 qti->max_sg_elems = le16_to_cpu(q_ident->max_sg_elems); 2904 qti->sg_desc_stride = le16_to_cpu(q_ident->sg_desc_stride); 2905 } 2906 mutex_unlock(&ionic->dev_cmd_lock); 2907 2908 if (err == -EINVAL) { 2909 dev_err(ionic->dev, "qtype %d not supported\n", qtype); 2910 continue; 2911 } else if (err == -EIO) { 2912 dev_err(ionic->dev, "q_ident failed, not supported on older FW\n"); 2913 return; 2914 } else if (err) { 2915 dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n", 2916 qtype, err); 2917 return; 2918 } 2919 2920 dev_dbg(ionic->dev, " qtype[%d].version = %d\n", 2921 qtype, qti->version); 2922 dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n", 2923 qtype, qti->supported); 2924 dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n", 2925 qtype, qti->features); 2926 dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n", 2927 qtype, qti->desc_sz); 2928 dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n", 2929 qtype, qti->comp_sz); 2930 dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n", 2931 qtype, qti->sg_desc_sz); 2932 dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n", 2933 qtype, qti->max_sg_elems); 2934 dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n", 2935 qtype, qti->sg_desc_stride); 2936 } 2937 } 2938 2939 int ionic_lif_identify(struct ionic *ionic, u8 lif_type, 2940 union ionic_lif_identity *lid) 2941 { 2942 struct ionic_dev *idev = &ionic->idev; 2943 size_t sz; 2944 int err; 2945 2946 sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data)); 2947 2948 mutex_lock(&ionic->dev_cmd_lock); 2949 ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1); 2950 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 2951 memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz); 2952 mutex_unlock(&ionic->dev_cmd_lock); 2953 if (err) 2954 return (err); 2955 2956 dev_dbg(ionic->dev, "capabilities 0x%llx\n", 2957 le64_to_cpu(lid->capabilities)); 2958 2959 dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n", 2960 le32_to_cpu(lid->eth.max_ucast_filters)); 2961 dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n", 2962 le32_to_cpu(lid->eth.max_mcast_filters)); 2963 dev_dbg(ionic->dev, "eth.features 0x%llx\n", 2964 le64_to_cpu(lid->eth.config.features)); 2965 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n", 2966 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ])); 2967 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n", 2968 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ])); 2969 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n", 2970 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ])); 2971 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n", 2972 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ])); 2973 dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name); 2974 dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac); 2975 dev_dbg(ionic->dev, "eth.config.mtu %d\n", 2976 le32_to_cpu(lid->eth.config.mtu)); 2977 2978 return 0; 2979 } 2980 2981 int ionic_lif_size(struct ionic *ionic) 2982 { 2983 struct ionic_identity *ident = &ionic->ident; 2984 unsigned int nintrs, dev_nintrs; 2985 union ionic_lif_config *lc; 2986 unsigned int ntxqs_per_lif; 2987 unsigned int nrxqs_per_lif; 2988 unsigned int neqs_per_lif; 2989 unsigned int nnqs_per_lif; 2990 unsigned int nxqs, neqs; 2991 unsigned int min_intrs; 2992 int err; 2993 2994 lc = &ident->lif.eth.config; 2995 dev_nintrs = le32_to_cpu(ident->dev.nintrs); 2996 neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count); 2997 nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]); 2998 ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]); 2999 nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]); 3000 3001 nxqs = min(ntxqs_per_lif, nrxqs_per_lif); 3002 nxqs = min(nxqs, num_online_cpus()); 3003 neqs = min(neqs_per_lif, num_online_cpus()); 3004 3005 try_again: 3006 /* interrupt usage: 3007 * 1 for master lif adminq/notifyq 3008 * 1 for each CPU for master lif TxRx queue pairs 3009 * whatever's left is for RDMA queues 3010 */ 3011 nintrs = 1 + nxqs + neqs; 3012 min_intrs = 2; /* adminq + 1 TxRx queue pair */ 3013 3014 if (nintrs > dev_nintrs) 3015 goto try_fewer; 3016 3017 err = ionic_bus_alloc_irq_vectors(ionic, nintrs); 3018 if (err < 0 && err != -ENOSPC) { 3019 dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err); 3020 return err; 3021 } 3022 if (err == -ENOSPC) 3023 goto try_fewer; 3024 3025 if (err != nintrs) { 3026 ionic_bus_free_irq_vectors(ionic); 3027 goto try_fewer; 3028 } 3029 3030 ionic->nnqs_per_lif = nnqs_per_lif; 3031 ionic->neqs_per_lif = neqs; 3032 ionic->ntxqs_per_lif = nxqs; 3033 ionic->nrxqs_per_lif = nxqs; 3034 ionic->nintrs = nintrs; 3035 3036 ionic_debugfs_add_sizes(ionic); 3037 3038 return 0; 3039 3040 try_fewer: 3041 if (nnqs_per_lif > 1) { 3042 nnqs_per_lif >>= 1; 3043 goto try_again; 3044 } 3045 if (neqs > 1) { 3046 neqs >>= 1; 3047 goto try_again; 3048 } 3049 if (nxqs > 1) { 3050 nxqs >>= 1; 3051 goto try_again; 3052 } 3053 dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs); 3054 return -ENOSPC; 3055 } 3056