1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/ethtool.h> 5 #include <linux/printk.h> 6 #include <linux/dynamic_debug.h> 7 #include <linux/netdevice.h> 8 #include <linux/etherdevice.h> 9 #include <linux/if_vlan.h> 10 #include <linux/rtnetlink.h> 11 #include <linux/interrupt.h> 12 #include <linux/pci.h> 13 #include <linux/cpumask.h> 14 #include <linux/crash_dump.h> 15 #include <linux/vmalloc.h> 16 #include <net/page_pool/helpers.h> 17 18 #include "ionic.h" 19 #include "ionic_bus.h" 20 #include "ionic_dev.h" 21 #include "ionic_lif.h" 22 #include "ionic_aux.h" 23 #include "ionic_txrx.h" 24 #include "ionic_ethtool.h" 25 #include "ionic_debugfs.h" 26 27 /* queuetype support level */ 28 static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = { 29 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */ 30 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */ 31 [IONIC_QTYPE_RXQ] = 2, /* 0 = Base version with CQ+SG support 32 * 2 = ... with CMB rings 33 */ 34 [IONIC_QTYPE_TXQ] = 3, /* 0 = Base version with CQ+SG support 35 * 1 = ... with Tx SG version 1 36 * 3 = ... with CMB rings 37 */ 38 }; 39 40 static void ionic_link_status_check(struct ionic_lif *lif); 41 static void ionic_lif_handle_fw_down(struct ionic_lif *lif); 42 static void ionic_lif_handle_fw_up(struct ionic_lif *lif); 43 static void ionic_lif_set_netdev_info(struct ionic_lif *lif); 44 45 static void ionic_txrx_deinit(struct ionic_lif *lif); 46 static int ionic_txrx_init(struct ionic_lif *lif); 47 static int ionic_start_queues(struct ionic_lif *lif); 48 static void ionic_stop_queues(struct ionic_lif *lif); 49 static void ionic_lif_queue_identify(struct ionic_lif *lif); 50 51 static void ionic_xdp_rxqs_prog_update(struct ionic_lif *lif); 52 static void ionic_unregister_rxq_info(struct ionic_queue *q); 53 static int ionic_register_rxq_info(struct ionic_queue *q, unsigned int napi_id); 54 55 static void ionic_dim_work(struct work_struct *work) 56 { 57 struct dim *dim = container_of(work, struct dim, work); 58 struct dim_cq_moder cur_moder; 59 struct ionic_intr_info *intr; 60 struct ionic_qcq *qcq; 61 struct ionic_lif *lif; 62 struct ionic_queue *q; 63 u32 new_coal; 64 65 qcq = container_of(dim, struct ionic_qcq, dim); 66 q = &qcq->q; 67 if (q->type == IONIC_QTYPE_RXQ) 68 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 69 else 70 cur_moder = net_dim_get_tx_moderation(dim->mode, dim->profile_ix); 71 lif = q->lif; 72 new_coal = ionic_coal_usec_to_hw(lif->ionic, cur_moder.usec); 73 new_coal = new_coal ? new_coal : 1; 74 75 intr = &qcq->intr; 76 if (intr->dim_coal_hw != new_coal) { 77 intr->dim_coal_hw = new_coal; 78 79 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 80 intr->index, intr->dim_coal_hw); 81 } 82 83 dim->state = DIM_START_MEASURE; 84 } 85 86 static void ionic_lif_deferred_work(struct work_struct *work) 87 { 88 struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work); 89 struct ionic_deferred *def = &lif->deferred; 90 struct ionic_deferred_work *w = NULL; 91 92 do { 93 spin_lock_bh(&def->lock); 94 if (!list_empty(&def->list)) { 95 w = list_first_entry(&def->list, 96 struct ionic_deferred_work, list); 97 list_del(&w->list); 98 } 99 spin_unlock_bh(&def->lock); 100 101 if (!w) 102 break; 103 104 switch (w->type) { 105 case IONIC_DW_TYPE_RX_MODE: 106 ionic_lif_rx_mode(lif); 107 break; 108 case IONIC_DW_TYPE_LINK_STATUS: 109 ionic_link_status_check(lif); 110 break; 111 case IONIC_DW_TYPE_LIF_RESET: 112 if (w->fw_status) { 113 ionic_lif_handle_fw_up(lif); 114 } else { 115 ionic_lif_handle_fw_down(lif); 116 117 /* Fire off another watchdog to see 118 * if the FW is already back rather than 119 * waiting another whole cycle 120 */ 121 mod_timer(&lif->ionic->watchdog_timer, jiffies + 1); 122 } 123 break; 124 default: 125 break; 126 } 127 kfree(w); 128 w = NULL; 129 } while (true); 130 } 131 132 void ionic_lif_deferred_enqueue(struct ionic_lif *lif, 133 struct ionic_deferred_work *work) 134 { 135 spin_lock_bh(&lif->deferred.lock); 136 list_add_tail(&work->list, &lif->deferred.list); 137 spin_unlock_bh(&lif->deferred.lock); 138 queue_work(lif->ionic->wq, &lif->deferred.work); 139 } 140 141 static void ionic_link_status_check(struct ionic_lif *lif) 142 { 143 struct ionic_dev *idev = &lif->ionic->idev; 144 struct net_device *netdev = lif->netdev; 145 u16 link_status; 146 bool link_up; 147 148 if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 149 return; 150 151 /* Don't put carrier back up if we're in a broken state */ 152 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) { 153 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 154 return; 155 } 156 157 ionic_reset_link_down_count(idev); 158 159 link_status = le16_to_cpu(lif->info->status.link_status); 160 link_up = link_status == IONIC_PORT_OPER_STATUS_UP; 161 162 if (link_up) { 163 int err = 0; 164 165 if (netdev->flags & IFF_UP && netif_running(netdev)) { 166 mutex_lock(&lif->queue_lock); 167 err = ionic_start_queues(lif); 168 if (err && err != -EBUSY) { 169 netdev_err(netdev, 170 "Failed to start queues: %d\n", err); 171 set_bit(IONIC_LIF_F_BROKEN, lif->state); 172 netif_carrier_off(lif->netdev); 173 } 174 mutex_unlock(&lif->queue_lock); 175 } 176 177 if (!err && !netif_carrier_ok(netdev)) { 178 ionic_port_identify(lif->ionic); 179 netdev_info(netdev, "Link up - %d Gbps\n", 180 le32_to_cpu(lif->info->status.link_speed) / 1000); 181 netif_carrier_on(netdev); 182 } 183 } else { 184 if (netif_carrier_ok(netdev)) { 185 netdev_info(netdev, "Link down\n"); 186 netif_carrier_off(netdev); 187 } 188 189 if (netdev->flags & IFF_UP && netif_running(netdev)) { 190 mutex_lock(&lif->queue_lock); 191 ionic_stop_queues(lif); 192 mutex_unlock(&lif->queue_lock); 193 } 194 } 195 196 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 197 } 198 199 void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep) 200 { 201 struct ionic_deferred_work *work; 202 203 /* we only need one request outstanding at a time */ 204 if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 205 return; 206 207 if (!can_sleep) { 208 work = kzalloc_obj(*work, GFP_ATOMIC); 209 if (!work) { 210 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 211 return; 212 } 213 214 work->type = IONIC_DW_TYPE_LINK_STATUS; 215 ionic_lif_deferred_enqueue(lif, work); 216 } else { 217 ionic_link_status_check(lif); 218 } 219 } 220 221 static irqreturn_t ionic_isr(int irq, void *data) 222 { 223 struct napi_struct *napi = data; 224 225 napi_schedule_irqoff(napi); 226 227 return IRQ_HANDLED; 228 } 229 230 static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq) 231 { 232 struct ionic_intr_info *intr = &qcq->intr; 233 struct device *dev = lif->ionic->dev; 234 struct ionic_queue *q = &qcq->q; 235 const char *name; 236 237 if (lif->registered) 238 name = netdev_name(lif->netdev); 239 else 240 name = dev_name(dev); 241 242 snprintf(intr->name, sizeof(intr->name), 243 "%.5s-%.16s-%.8s", IONIC_DRV_NAME, name, q->name); 244 245 return devm_request_irq(dev, intr->vector, ionic_isr, 246 0, intr->name, &qcq->napi); 247 } 248 249 int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) 250 { 251 struct ionic *ionic = lif->ionic; 252 int index, err; 253 254 index = find_first_zero_bit(ionic->intrs, ionic->nintrs); 255 if (index == ionic->nintrs) 256 return -ENOSPC; 257 258 set_bit(index, ionic->intrs); 259 ionic_intr_init(&ionic->idev, intr, index); 260 261 err = ionic_bus_get_irq(ionic, intr->index); 262 if (err < 0) { 263 clear_bit(index, ionic->intrs); 264 return err; 265 } 266 267 intr->vector = err; 268 269 return 0; 270 } 271 EXPORT_SYMBOL_NS(ionic_intr_alloc, "NET_IONIC"); 272 273 void ionic_intr_free(struct ionic_lif *lif, int index) 274 { 275 if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < lif->ionic->nintrs) 276 clear_bit(index, lif->ionic->intrs); 277 } 278 EXPORT_SYMBOL_NS(ionic_intr_free, "NET_IONIC"); 279 280 static void ionic_irq_aff_notify(struct irq_affinity_notify *notify, 281 const cpumask_t *mask) 282 { 283 struct ionic_intr_info *intr = container_of(notify, struct ionic_intr_info, aff_notify); 284 285 cpumask_copy(*intr->affinity_mask, mask); 286 } 287 288 static void ionic_irq_aff_release(struct kref __always_unused *ref) 289 { 290 } 291 292 static int ionic_qcq_enable(struct ionic_qcq *qcq) 293 { 294 struct ionic_queue *q = &qcq->q; 295 struct ionic_lif *lif = q->lif; 296 struct ionic_dev *idev; 297 struct device *dev; 298 299 struct ionic_admin_ctx ctx = { 300 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 301 .cmd.q_control = { 302 .opcode = IONIC_CMD_Q_CONTROL, 303 .lif_index = cpu_to_le16(lif->index), 304 .type = q->type, 305 .index = cpu_to_le32(q->index), 306 .oper = IONIC_Q_ENABLE, 307 }, 308 }; 309 int ret; 310 311 idev = &lif->ionic->idev; 312 dev = lif->ionic->dev; 313 314 dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n", 315 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 316 317 if (qcq->flags & IONIC_QCQ_F_INTR) 318 ionic_intr_clean(idev->intr_ctrl, qcq->intr.index); 319 320 ret = ionic_adminq_post_wait(lif, &ctx); 321 if (ret) 322 return ret; 323 324 if (qcq->flags & IONIC_QCQ_F_INTR) { 325 napi_enable(&qcq->napi); 326 irq_set_affinity_notifier(qcq->intr.vector, 327 &qcq->intr.aff_notify); 328 irq_set_affinity_hint(qcq->intr.vector, 329 *qcq->intr.affinity_mask); 330 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 331 IONIC_INTR_MASK_CLEAR); 332 } 333 334 return 0; 335 } 336 337 static int ionic_qcq_disable(struct ionic_lif *lif, struct ionic_qcq *qcq, int fw_err) 338 { 339 struct ionic_queue *q; 340 341 struct ionic_admin_ctx ctx = { 342 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 343 .cmd.q_control = { 344 .opcode = IONIC_CMD_Q_CONTROL, 345 .oper = IONIC_Q_DISABLE, 346 }, 347 }; 348 349 if (!qcq) { 350 netdev_err(lif->netdev, "%s: bad qcq\n", __func__); 351 return -ENXIO; 352 } 353 354 q = &qcq->q; 355 356 if (qcq->flags & IONIC_QCQ_F_INTR) { 357 struct ionic_dev *idev = &lif->ionic->idev; 358 359 if (lif->doorbell_wa) 360 cancel_work_sync(&qcq->doorbell_napi_work); 361 cancel_work_sync(&qcq->dim.work); 362 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 363 IONIC_INTR_MASK_SET); 364 synchronize_irq(qcq->intr.vector); 365 irq_set_affinity_notifier(qcq->intr.vector, NULL); 366 irq_set_affinity_hint(qcq->intr.vector, NULL); 367 napi_disable(&qcq->napi); 368 } 369 370 /* If there was a previous fw communcation error, don't bother with 371 * sending the adminq command and just return the same error value. 372 */ 373 if (fw_err == -ETIMEDOUT || fw_err == -ENXIO) 374 return fw_err; 375 376 ctx.cmd.q_control.lif_index = cpu_to_le16(lif->index); 377 ctx.cmd.q_control.type = q->type; 378 ctx.cmd.q_control.index = cpu_to_le32(q->index); 379 dev_dbg(lif->ionic->dev, "q_disable.index %d q_disable.qtype %d\n", 380 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 381 382 return ionic_adminq_post_wait(lif, &ctx); 383 } 384 385 static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq) 386 { 387 struct ionic_dev *idev = &lif->ionic->idev; 388 389 if (!qcq) 390 return; 391 392 if (!(qcq->flags & IONIC_QCQ_F_INITED)) 393 return; 394 395 ionic_unregister_rxq_info(&qcq->q); 396 if (qcq->flags & IONIC_QCQ_F_INTR) { 397 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 398 IONIC_INTR_MASK_SET); 399 netif_napi_del(&qcq->napi); 400 } 401 402 qcq->flags &= ~IONIC_QCQ_F_INITED; 403 } 404 405 static void ionic_qcq_intr_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 406 { 407 if (!(qcq->flags & IONIC_QCQ_F_INTR) || qcq->intr.vector == 0) 408 return; 409 410 irq_set_affinity_hint(qcq->intr.vector, NULL); 411 devm_free_irq(lif->ionic->dev, qcq->intr.vector, &qcq->napi); 412 qcq->intr.vector = 0; 413 ionic_intr_free(lif, qcq->intr.index); 414 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 415 } 416 417 static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 418 { 419 struct device *dev = lif->ionic->dev; 420 421 if (!qcq) 422 return; 423 424 ionic_debugfs_del_qcq(qcq); 425 426 if (qcq->q_base) { 427 dma_free_coherent(dev, qcq->q_size, qcq->q_base, qcq->q_base_pa); 428 qcq->q_base = NULL; 429 qcq->q_base_pa = 0; 430 } 431 432 if (qcq->cmb_q_base) { 433 iounmap(qcq->cmb_q_base); 434 ionic_put_cmb(lif, qcq->cmb_pgid, qcq->cmb_order); 435 qcq->cmb_pgid = 0; 436 qcq->cmb_order = 0; 437 qcq->cmb_q_base = NULL; 438 qcq->cmb_q_base_pa = 0; 439 } 440 441 if (qcq->cq_base) { 442 dma_free_coherent(dev, qcq->cq_size, qcq->cq_base, qcq->cq_base_pa); 443 qcq->cq_base = NULL; 444 qcq->cq_base_pa = 0; 445 } 446 447 if (qcq->sg_base) { 448 dma_free_coherent(dev, qcq->sg_size, qcq->sg_base, qcq->sg_base_pa); 449 qcq->sg_base = NULL; 450 qcq->sg_base_pa = 0; 451 } 452 453 page_pool_destroy(qcq->q.page_pool); 454 qcq->q.page_pool = NULL; 455 456 ionic_qcq_intr_free(lif, qcq); 457 vfree(qcq->q.info); 458 qcq->q.info = NULL; 459 } 460 461 void ionic_qcqs_free(struct ionic_lif *lif) 462 { 463 struct device *dev = lif->ionic->dev; 464 struct ionic_qcq *adminqcq; 465 unsigned long irqflags; 466 467 if (lif->notifyqcq) { 468 ionic_qcq_free(lif, lif->notifyqcq); 469 devm_kfree(dev, lif->notifyqcq); 470 lif->notifyqcq = NULL; 471 } 472 473 if (lif->adminqcq) { 474 spin_lock_irqsave(&lif->adminq_lock, irqflags); 475 adminqcq = READ_ONCE(lif->adminqcq); 476 lif->adminqcq = NULL; 477 spin_unlock_irqrestore(&lif->adminq_lock, irqflags); 478 if (adminqcq) { 479 ionic_qcq_free(lif, adminqcq); 480 devm_kfree(dev, adminqcq); 481 } 482 } 483 484 if (lif->rxqcqs) { 485 devm_kfree(dev, lif->rxqstats); 486 lif->rxqstats = NULL; 487 devm_kfree(dev, lif->rxqcqs); 488 lif->rxqcqs = NULL; 489 } 490 491 if (lif->txqcqs) { 492 devm_kfree(dev, lif->txqstats); 493 lif->txqstats = NULL; 494 devm_kfree(dev, lif->txqcqs); 495 lif->txqcqs = NULL; 496 } 497 } 498 499 static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq, 500 struct ionic_qcq *n_qcq) 501 { 502 n_qcq->intr.vector = src_qcq->intr.vector; 503 n_qcq->intr.index = src_qcq->intr.index; 504 } 505 506 static int ionic_alloc_qcq_interrupt(struct ionic_lif *lif, struct ionic_qcq *qcq) 507 { 508 cpumask_var_t *affinity_mask; 509 int err; 510 511 if (!(qcq->flags & IONIC_QCQ_F_INTR)) { 512 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 513 return 0; 514 } 515 516 err = ionic_intr_alloc(lif, &qcq->intr); 517 if (err) { 518 netdev_warn(lif->netdev, "no intr for %s: %d\n", 519 qcq->q.name, err); 520 goto err_out; 521 } 522 523 ionic_intr_mask_assert(lif->ionic->idev.intr_ctrl, qcq->intr.index, 524 IONIC_INTR_MASK_SET); 525 526 err = ionic_request_irq(lif, qcq); 527 if (err) { 528 netdev_warn(lif->netdev, "irq request failed %d\n", err); 529 goto err_out_free_intr; 530 } 531 532 /* try to get the irq on the local numa node first */ 533 affinity_mask = &lif->ionic->affinity_masks[qcq->intr.index]; 534 if (cpumask_empty(*affinity_mask)) { 535 unsigned int cpu; 536 537 cpu = cpumask_local_spread(qcq->intr.index, 538 dev_to_node(lif->ionic->dev)); 539 if (cpu != -1) 540 cpumask_set_cpu(cpu, *affinity_mask); 541 } 542 543 qcq->intr.affinity_mask = affinity_mask; 544 qcq->intr.aff_notify.notify = ionic_irq_aff_notify; 545 qcq->intr.aff_notify.release = ionic_irq_aff_release; 546 547 netdev_dbg(lif->netdev, "%s: Interrupt index %d\n", qcq->q.name, qcq->intr.index); 548 return 0; 549 550 err_out_free_intr: 551 ionic_intr_free(lif, qcq->intr.index); 552 err_out: 553 return err; 554 } 555 556 static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type, 557 unsigned int index, 558 const char *name, unsigned int flags, 559 unsigned int num_descs, unsigned int desc_size, 560 unsigned int cq_desc_size, 561 unsigned int sg_desc_size, 562 unsigned int desc_info_size, 563 unsigned int pid, struct bpf_prog *xdp_prog, 564 struct ionic_qcq **qcq) 565 { 566 struct ionic_dev *idev = &lif->ionic->idev; 567 struct device *dev = lif->ionic->dev; 568 struct ionic_qcq *new; 569 int err; 570 571 *qcq = NULL; 572 573 new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL); 574 if (!new) { 575 netdev_err(lif->netdev, "Cannot allocate queue structure\n"); 576 err = -ENOMEM; 577 goto err_out; 578 } 579 580 new->q.dev = dev; 581 new->flags = flags; 582 583 new->q.info = vcalloc(num_descs, desc_info_size); 584 if (!new->q.info) { 585 netdev_err(lif->netdev, "Cannot allocate queue info\n"); 586 err = -ENOMEM; 587 goto err_out_free_qcq; 588 } 589 590 if (type == IONIC_QTYPE_RXQ) { 591 struct page_pool_params pp_params = { 592 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 593 .order = 0, 594 .pool_size = num_descs, 595 .nid = NUMA_NO_NODE, 596 .dev = lif->ionic->dev, 597 .napi = &new->napi, 598 .dma_dir = DMA_FROM_DEVICE, 599 .max_len = PAGE_SIZE, 600 .netdev = lif->netdev, 601 }; 602 603 if (xdp_prog) 604 pp_params.dma_dir = DMA_BIDIRECTIONAL; 605 606 new->q.page_pool = page_pool_create(&pp_params); 607 if (IS_ERR(new->q.page_pool)) { 608 netdev_err(lif->netdev, "Cannot create page_pool\n"); 609 err = PTR_ERR(new->q.page_pool); 610 new->q.page_pool = NULL; 611 goto err_out_free_q_info; 612 } 613 } 614 615 new->q.type = type; 616 new->q.max_sg_elems = lif->qtype_info[type].max_sg_elems; 617 618 err = ionic_q_init(lif, idev, &new->q, index, name, num_descs, 619 desc_size, sg_desc_size, pid); 620 if (err) { 621 netdev_err(lif->netdev, "Cannot initialize queue\n"); 622 goto err_out_free_page_pool; 623 } 624 625 err = ionic_alloc_qcq_interrupt(lif, new); 626 if (err) 627 goto err_out_free_page_pool; 628 629 err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size); 630 if (err) { 631 netdev_err(lif->netdev, "Cannot initialize completion queue\n"); 632 goto err_out_free_irq; 633 } 634 635 if (flags & IONIC_QCQ_F_NOTIFYQ) { 636 int q_size; 637 638 /* q & cq need to be contiguous in NotifyQ, so alloc it all in q 639 * and don't alloc qc. We leave new->qc_size and new->qc_base 640 * as 0 to be sure we don't try to free it later. 641 */ 642 q_size = ALIGN(num_descs * desc_size, PAGE_SIZE); 643 new->q_size = PAGE_SIZE + q_size + 644 ALIGN(num_descs * cq_desc_size, PAGE_SIZE); 645 new->q_base = dma_alloc_coherent(dev, new->q_size, 646 &new->q_base_pa, GFP_KERNEL); 647 if (!new->q_base) { 648 netdev_err(lif->netdev, "Cannot allocate qcq DMA memory\n"); 649 err = -ENOMEM; 650 goto err_out_free_irq; 651 } 652 new->q.base = PTR_ALIGN(new->q_base, PAGE_SIZE); 653 new->q.base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 654 655 /* Base the NotifyQ cq.base off of the ALIGNed q.base */ 656 new->cq.base = PTR_ALIGN(new->q.base + q_size, PAGE_SIZE); 657 new->cq.base_pa = ALIGN(new->q_base_pa + q_size, PAGE_SIZE); 658 new->cq.bound_q = &new->q; 659 } else { 660 /* regular DMA q descriptors */ 661 new->q_size = PAGE_SIZE + (num_descs * desc_size); 662 new->q_base = dma_alloc_coherent(dev, new->q_size, &new->q_base_pa, 663 GFP_KERNEL); 664 if (!new->q_base) { 665 netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n"); 666 err = -ENOMEM; 667 goto err_out_free_irq; 668 } 669 new->q.base = PTR_ALIGN(new->q_base, PAGE_SIZE); 670 new->q.base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 671 672 if (flags & IONIC_QCQ_F_CMB_RINGS) { 673 /* on-chip CMB q descriptors */ 674 new->cmb_q_size = num_descs * desc_size; 675 new->cmb_order = order_base_2(new->cmb_q_size / PAGE_SIZE); 676 677 err = ionic_get_cmb(lif, &new->cmb_pgid, &new->cmb_q_base_pa, 678 new->cmb_order, 0, NULL); 679 if (err) { 680 netdev_err(lif->netdev, 681 "Cannot allocate queue order %d from cmb: err %d\n", 682 new->cmb_order, err); 683 goto err_out_free_q; 684 } 685 686 new->cmb_q_base = ioremap_wc(new->cmb_q_base_pa, new->cmb_q_size); 687 if (!new->cmb_q_base) { 688 netdev_err(lif->netdev, "Cannot map queue from cmb\n"); 689 ionic_put_cmb(lif, new->cmb_pgid, new->cmb_order); 690 err = -ENOMEM; 691 goto err_out_free_q; 692 } 693 694 new->cmb_q_base_pa -= idev->phy_cmb_pages; 695 new->q.cmb_base = new->cmb_q_base; 696 new->q.cmb_base_pa = new->cmb_q_base_pa; 697 } 698 699 /* cq DMA descriptors */ 700 new->cq_size = PAGE_SIZE + (num_descs * cq_desc_size); 701 new->cq_base = dma_alloc_coherent(dev, new->cq_size, &new->cq_base_pa, 702 GFP_KERNEL); 703 if (!new->cq_base) { 704 netdev_err(lif->netdev, "Cannot allocate cq DMA memory\n"); 705 err = -ENOMEM; 706 goto err_out_free_q; 707 } 708 new->cq.base = PTR_ALIGN(new->cq_base, PAGE_SIZE); 709 new->cq.base_pa = ALIGN(new->cq_base_pa, PAGE_SIZE); 710 new->cq.bound_q = &new->q; 711 } 712 713 if (flags & IONIC_QCQ_F_SG) { 714 new->sg_size = PAGE_SIZE + (num_descs * sg_desc_size); 715 new->sg_base = dma_alloc_coherent(dev, new->sg_size, &new->sg_base_pa, 716 GFP_KERNEL); 717 if (!new->sg_base) { 718 netdev_err(lif->netdev, "Cannot allocate sg DMA memory\n"); 719 err = -ENOMEM; 720 goto err_out_free_cq; 721 } 722 new->q.sg_base = PTR_ALIGN(new->sg_base, PAGE_SIZE); 723 new->q.sg_base_pa = ALIGN(new->sg_base_pa, PAGE_SIZE); 724 } 725 726 INIT_WORK(&new->dim.work, ionic_dim_work); 727 new->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; 728 if (lif->doorbell_wa) 729 INIT_WORK(&new->doorbell_napi_work, ionic_doorbell_napi_work); 730 731 *qcq = new; 732 733 return 0; 734 735 err_out_free_cq: 736 dma_free_coherent(dev, new->cq_size, new->cq_base, new->cq_base_pa); 737 err_out_free_q: 738 if (new->cmb_q_base) { 739 iounmap(new->cmb_q_base); 740 ionic_put_cmb(lif, new->cmb_pgid, new->cmb_order); 741 } 742 dma_free_coherent(dev, new->q_size, new->q_base, new->q_base_pa); 743 err_out_free_irq: 744 if (flags & IONIC_QCQ_F_INTR) { 745 devm_free_irq(dev, new->intr.vector, &new->napi); 746 ionic_intr_free(lif, new->intr.index); 747 } 748 err_out_free_page_pool: 749 page_pool_destroy(new->q.page_pool); 750 err_out_free_q_info: 751 vfree(new->q.info); 752 err_out_free_qcq: 753 devm_kfree(dev, new); 754 err_out: 755 dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err); 756 return err; 757 } 758 759 static int ionic_qcqs_alloc(struct ionic_lif *lif) 760 { 761 struct device *dev = lif->ionic->dev; 762 unsigned int flags; 763 int err; 764 765 flags = IONIC_QCQ_F_INTR; 766 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags, 767 IONIC_ADMINQ_LENGTH, 768 sizeof(struct ionic_admin_cmd), 769 sizeof(struct ionic_admin_comp), 770 0, 771 sizeof(struct ionic_admin_desc_info), 772 lif->kern_pid, NULL, &lif->adminqcq); 773 if (err) 774 return err; 775 ionic_debugfs_add_qcq(lif, lif->adminqcq); 776 777 if (lif->ionic->nnqs_per_lif) { 778 flags = IONIC_QCQ_F_NOTIFYQ; 779 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq", 780 flags, IONIC_NOTIFYQ_LENGTH, 781 sizeof(struct ionic_notifyq_cmd), 782 sizeof(union ionic_notifyq_comp), 783 0, 784 sizeof(struct ionic_admin_desc_info), 785 lif->kern_pid, NULL, &lif->notifyqcq); 786 if (err) 787 goto err_out; 788 ionic_debugfs_add_qcq(lif, lif->notifyqcq); 789 790 /* Let the notifyq ride on the adminq interrupt */ 791 ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq); 792 } 793 794 err = -ENOMEM; 795 lif->txqcqs = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif, 796 sizeof(*lif->txqcqs), GFP_KERNEL); 797 if (!lif->txqcqs) 798 goto err_out; 799 lif->rxqcqs = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif, 800 sizeof(*lif->rxqcqs), GFP_KERNEL); 801 if (!lif->rxqcqs) 802 goto err_out; 803 804 lif->txqstats = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif + 1, 805 sizeof(*lif->txqstats), GFP_KERNEL); 806 if (!lif->txqstats) 807 goto err_out; 808 lif->rxqstats = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif + 1, 809 sizeof(*lif->rxqstats), GFP_KERNEL); 810 if (!lif->rxqstats) 811 goto err_out; 812 813 return 0; 814 815 err_out: 816 ionic_qcqs_free(lif); 817 return err; 818 } 819 820 static void ionic_qcq_sanitize(struct ionic_qcq *qcq) 821 { 822 qcq->q.tail_idx = 0; 823 qcq->q.head_idx = 0; 824 qcq->cq.tail_idx = 0; 825 qcq->cq.done_color = 1; 826 memset(qcq->q_base, 0, qcq->q_size); 827 if (qcq->cmb_q_base) 828 memset_io(qcq->cmb_q_base, 0, qcq->cmb_q_size); 829 memset(qcq->cq_base, 0, qcq->cq_size); 830 memset(qcq->sg_base, 0, qcq->sg_size); 831 } 832 833 static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 834 { 835 struct device *dev = lif->ionic->dev; 836 struct ionic_queue *q = &qcq->q; 837 struct ionic_cq *cq = &qcq->cq; 838 struct ionic_admin_ctx ctx = { 839 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 840 .cmd.q_init = { 841 .opcode = IONIC_CMD_Q_INIT, 842 .lif_index = cpu_to_le16(lif->index), 843 .type = q->type, 844 .ver = lif->qtype_info[q->type].version, 845 .index = cpu_to_le32(q->index), 846 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 847 IONIC_QINIT_F_SG), 848 .intr_index = cpu_to_le16(qcq->intr.index), 849 .pid = cpu_to_le16(q->pid), 850 .ring_size = ilog2(q->num_descs), 851 .ring_base = cpu_to_le64(q->base_pa), 852 .cq_ring_base = cpu_to_le64(cq->base_pa), 853 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 854 .features = cpu_to_le64(q->features), 855 }, 856 }; 857 int err; 858 859 if (qcq->flags & IONIC_QCQ_F_CMB_RINGS) { 860 ctx.cmd.q_init.flags |= cpu_to_le16(IONIC_QINIT_F_CMB); 861 ctx.cmd.q_init.ring_base = cpu_to_le64(qcq->cmb_q_base_pa); 862 } 863 864 dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid); 865 dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index); 866 dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 867 dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 868 dev_dbg(dev, "txq_init.cq_ring_base 0x%llx\n", ctx.cmd.q_init.cq_ring_base); 869 dev_dbg(dev, "txq_init.sg_ring_base 0x%llx\n", ctx.cmd.q_init.sg_ring_base); 870 dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 871 dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver); 872 dev_dbg(dev, "txq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 873 874 ionic_qcq_sanitize(qcq); 875 876 err = ionic_adminq_post_wait(lif, &ctx); 877 if (err) 878 return err; 879 880 q->hw_type = ctx.comp.q_init.hw_type; 881 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 882 q->dbval = IONIC_DBELL_QID(q->hw_index); 883 884 dev_dbg(dev, "txq->hw_type %d\n", q->hw_type); 885 dev_dbg(dev, "txq->hw_index %d\n", q->hw_index); 886 887 q->dbell_deadline = IONIC_TX_DOORBELL_DEADLINE; 888 q->dbell_jiffies = jiffies; 889 890 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 891 netif_napi_add(lif->netdev, &qcq->napi, ionic_tx_napi); 892 893 qcq->flags |= IONIC_QCQ_F_INITED; 894 895 return 0; 896 } 897 898 static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 899 { 900 struct device *dev = lif->ionic->dev; 901 struct ionic_queue *q = &qcq->q; 902 struct ionic_cq *cq = &qcq->cq; 903 struct ionic_admin_ctx ctx = { 904 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 905 .cmd.q_init = { 906 .opcode = IONIC_CMD_Q_INIT, 907 .lif_index = cpu_to_le16(lif->index), 908 .type = q->type, 909 .ver = lif->qtype_info[q->type].version, 910 .index = cpu_to_le32(q->index), 911 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ), 912 .intr_index = cpu_to_le16(cq->bound_intr->index), 913 .pid = cpu_to_le16(q->pid), 914 .ring_size = ilog2(q->num_descs), 915 .ring_base = cpu_to_le64(q->base_pa), 916 .cq_ring_base = cpu_to_le64(cq->base_pa), 917 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 918 .features = cpu_to_le64(q->features), 919 }, 920 }; 921 int err; 922 923 q->partner = &lif->txqcqs[q->index]->q; 924 q->partner->partner = q; 925 926 if (!lif->xdp_prog || 927 (lif->xdp_prog->aux && lif->xdp_prog->aux->xdp_has_frags)) 928 ctx.cmd.q_init.flags |= cpu_to_le16(IONIC_QINIT_F_SG); 929 930 if (qcq->flags & IONIC_QCQ_F_CMB_RINGS) { 931 ctx.cmd.q_init.flags |= cpu_to_le16(IONIC_QINIT_F_CMB); 932 ctx.cmd.q_init.ring_base = cpu_to_le64(qcq->cmb_q_base_pa); 933 } 934 935 dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid); 936 dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index); 937 dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 938 dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 939 dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 940 dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver); 941 dev_dbg(dev, "rxq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 942 943 ionic_qcq_sanitize(qcq); 944 945 err = ionic_adminq_post_wait(lif, &ctx); 946 if (err) 947 return err; 948 949 q->hw_type = ctx.comp.q_init.hw_type; 950 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 951 q->dbval = IONIC_DBELL_QID(q->hw_index); 952 953 dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type); 954 dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index); 955 956 q->dbell_deadline = IONIC_RX_MIN_DOORBELL_DEADLINE; 957 q->dbell_jiffies = jiffies; 958 959 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 960 netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi); 961 else 962 netif_napi_add(lif->netdev, &qcq->napi, ionic_txrx_napi); 963 err = ionic_register_rxq_info(q, qcq->napi.napi_id); 964 if (err) { 965 netif_napi_del(&qcq->napi); 966 return err; 967 } 968 969 qcq->flags |= IONIC_QCQ_F_INITED; 970 971 return 0; 972 } 973 974 int ionic_lif_create_hwstamp_txq(struct ionic_lif *lif) 975 { 976 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz; 977 unsigned int txq_i, flags; 978 struct ionic_qcq *txq; 979 u64 features; 980 int err; 981 982 if (lif->hwstamp_txq) 983 return 0; 984 985 features = IONIC_Q_F_2X_CQ_DESC | IONIC_TXQ_F_HWSTAMP; 986 987 num_desc = IONIC_MIN_TXRX_DESC; 988 desc_sz = sizeof(struct ionic_txq_desc); 989 comp_sz = 2 * sizeof(struct ionic_txq_comp); 990 991 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 992 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == sizeof(struct ionic_txq_sg_desc_v1)) 993 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 994 else 995 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 996 997 txq_i = lif->ionic->ntxqs_per_lif; 998 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 999 1000 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, txq_i, "hwstamp_tx", flags, 1001 num_desc, desc_sz, comp_sz, sg_desc_sz, 1002 sizeof(struct ionic_tx_desc_info), 1003 lif->kern_pid, NULL, &txq); 1004 if (err) 1005 goto err_qcq_alloc; 1006 1007 txq->q.features = features; 1008 1009 ionic_link_qcq_interrupts(lif->adminqcq, txq); 1010 ionic_debugfs_add_qcq(lif, txq); 1011 1012 lif->hwstamp_txq = txq; 1013 1014 if (netif_running(lif->netdev)) { 1015 err = ionic_lif_txq_init(lif, txq); 1016 if (err) 1017 goto err_qcq_init; 1018 1019 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 1020 err = ionic_qcq_enable(txq); 1021 if (err) 1022 goto err_qcq_enable; 1023 } 1024 } 1025 1026 return 0; 1027 1028 err_qcq_enable: 1029 ionic_lif_qcq_deinit(lif, txq); 1030 err_qcq_init: 1031 lif->hwstamp_txq = NULL; 1032 ionic_debugfs_del_qcq(txq); 1033 ionic_qcq_free(lif, txq); 1034 devm_kfree(lif->ionic->dev, txq); 1035 err_qcq_alloc: 1036 return err; 1037 } 1038 1039 int ionic_lif_create_hwstamp_rxq(struct ionic_lif *lif) 1040 { 1041 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz; 1042 unsigned int rxq_i, flags; 1043 struct ionic_qcq *rxq; 1044 u64 features; 1045 int err; 1046 1047 if (lif->hwstamp_rxq) 1048 return 0; 1049 1050 features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP; 1051 1052 num_desc = IONIC_MIN_TXRX_DESC; 1053 desc_sz = sizeof(struct ionic_rxq_desc); 1054 comp_sz = 2 * sizeof(struct ionic_rxq_comp); 1055 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 1056 1057 rxq_i = lif->ionic->nrxqs_per_lif; 1058 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG; 1059 1060 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, rxq_i, "hwstamp_rx", flags, 1061 num_desc, desc_sz, comp_sz, sg_desc_sz, 1062 sizeof(struct ionic_rx_desc_info), 1063 lif->kern_pid, NULL, &rxq); 1064 if (err) 1065 goto err_qcq_alloc; 1066 1067 rxq->q.features = features; 1068 1069 ionic_link_qcq_interrupts(lif->adminqcq, rxq); 1070 ionic_debugfs_add_qcq(lif, rxq); 1071 1072 lif->hwstamp_rxq = rxq; 1073 1074 if (netif_running(lif->netdev)) { 1075 err = ionic_lif_rxq_init(lif, rxq); 1076 if (err) 1077 goto err_qcq_init; 1078 1079 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 1080 ionic_rx_fill(&rxq->q, NULL); 1081 err = ionic_qcq_enable(rxq); 1082 if (err) 1083 goto err_qcq_enable; 1084 } 1085 } 1086 1087 return 0; 1088 1089 err_qcq_enable: 1090 ionic_lif_qcq_deinit(lif, rxq); 1091 err_qcq_init: 1092 lif->hwstamp_rxq = NULL; 1093 ionic_debugfs_del_qcq(rxq); 1094 ionic_qcq_free(lif, rxq); 1095 devm_kfree(lif->ionic->dev, rxq); 1096 err_qcq_alloc: 1097 return err; 1098 } 1099 1100 int ionic_lif_config_hwstamp_rxq_all(struct ionic_lif *lif, bool rx_all) 1101 { 1102 struct ionic_queue_params qparam; 1103 1104 ionic_init_queue_params(lif, &qparam); 1105 1106 if (rx_all) 1107 qparam.rxq_features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP; 1108 else 1109 qparam.rxq_features = 0; 1110 1111 /* if we're not running, just set the values and return */ 1112 if (!netif_running(lif->netdev)) { 1113 lif->rxq_features = qparam.rxq_features; 1114 return 0; 1115 } 1116 1117 return ionic_reconfigure_queues(lif, &qparam); 1118 } 1119 1120 int ionic_lif_set_hwstamp_txmode(struct ionic_lif *lif, u16 txstamp_mode) 1121 { 1122 struct ionic_admin_ctx ctx = { 1123 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1124 .cmd.lif_setattr = { 1125 .opcode = IONIC_CMD_LIF_SETATTR, 1126 .index = cpu_to_le16(lif->index), 1127 .attr = IONIC_LIF_ATTR_TXSTAMP, 1128 .txstamp_mode = cpu_to_le16(txstamp_mode), 1129 }, 1130 }; 1131 1132 return ionic_adminq_post_wait(lif, &ctx); 1133 } 1134 1135 static void ionic_lif_del_hwstamp_rxfilt(struct ionic_lif *lif) 1136 { 1137 struct ionic_admin_ctx ctx = { 1138 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1139 .cmd.rx_filter_del = { 1140 .opcode = IONIC_CMD_RX_FILTER_DEL, 1141 .lif_index = cpu_to_le16(lif->index), 1142 }, 1143 }; 1144 struct ionic_rx_filter *f; 1145 u32 filter_id; 1146 int err; 1147 1148 spin_lock_bh(&lif->rx_filters.lock); 1149 1150 f = ionic_rx_filter_rxsteer(lif); 1151 if (!f) { 1152 spin_unlock_bh(&lif->rx_filters.lock); 1153 return; 1154 } 1155 1156 filter_id = f->filter_id; 1157 ionic_rx_filter_free(lif, f); 1158 1159 spin_unlock_bh(&lif->rx_filters.lock); 1160 1161 netdev_dbg(lif->netdev, "rx_filter del RXSTEER (id %d)\n", filter_id); 1162 1163 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(filter_id); 1164 1165 err = ionic_adminq_post_wait(lif, &ctx); 1166 if (err && err != -EEXIST) 1167 netdev_dbg(lif->netdev, "failed to delete rx_filter RXSTEER (id %d)\n", filter_id); 1168 } 1169 1170 static int ionic_lif_add_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class) 1171 { 1172 struct ionic_admin_ctx ctx = { 1173 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1174 .cmd.rx_filter_add = { 1175 .opcode = IONIC_CMD_RX_FILTER_ADD, 1176 .lif_index = cpu_to_le16(lif->index), 1177 .match = cpu_to_le16(IONIC_RX_FILTER_STEER_PKTCLASS), 1178 .pkt_class = cpu_to_le64(pkt_class), 1179 }, 1180 }; 1181 u8 qtype; 1182 u32 qid; 1183 int err; 1184 1185 if (!lif->hwstamp_rxq) 1186 return -EINVAL; 1187 1188 qtype = lif->hwstamp_rxq->q.type; 1189 ctx.cmd.rx_filter_add.qtype = qtype; 1190 1191 qid = lif->hwstamp_rxq->q.index; 1192 ctx.cmd.rx_filter_add.qid = cpu_to_le32(qid); 1193 1194 netdev_dbg(lif->netdev, "rx_filter add RXSTEER\n"); 1195 err = ionic_adminq_post_wait(lif, &ctx); 1196 if (err && err != -EEXIST) 1197 return err; 1198 1199 spin_lock_bh(&lif->rx_filters.lock); 1200 err = ionic_rx_filter_save(lif, 0, qid, 0, &ctx, IONIC_FILTER_STATE_SYNCED); 1201 spin_unlock_bh(&lif->rx_filters.lock); 1202 1203 return err; 1204 } 1205 1206 int ionic_lif_set_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class) 1207 { 1208 ionic_lif_del_hwstamp_rxfilt(lif); 1209 1210 if (!pkt_class) 1211 return 0; 1212 1213 return ionic_lif_add_hwstamp_rxfilt(lif, pkt_class); 1214 } 1215 1216 static int ionic_adminq_napi(struct napi_struct *napi, int budget) 1217 { 1218 struct ionic_intr_info *intr = napi_to_cq(napi)->bound_intr; 1219 struct ionic_lif *lif = napi_to_cq(napi)->lif; 1220 struct ionic_dev *idev = &lif->ionic->idev; 1221 unsigned long irqflags; 1222 unsigned int flags = 0; 1223 int rx_work = 0; 1224 int tx_work = 0; 1225 int n_work = 0; 1226 int a_work = 0; 1227 int work_done; 1228 int credits; 1229 1230 if (lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED) 1231 n_work = ionic_cq_service(&lif->notifyqcq->cq, budget, 1232 ionic_notifyq_service, NULL, NULL); 1233 1234 spin_lock_irqsave(&lif->adminq_lock, irqflags); 1235 if (lif->adminqcq && lif->adminqcq->flags & IONIC_QCQ_F_INITED) 1236 a_work = ionic_cq_service(&lif->adminqcq->cq, budget, 1237 ionic_adminq_service, NULL, NULL); 1238 1239 spin_unlock_irqrestore(&lif->adminq_lock, irqflags); 1240 1241 if (lif->hwstamp_rxq) 1242 rx_work = ionic_cq_service(&lif->hwstamp_rxq->cq, budget, 1243 ionic_rx_service, NULL, NULL); 1244 1245 if (lif->hwstamp_txq) 1246 tx_work = ionic_tx_cq_service(&lif->hwstamp_txq->cq, budget, !!budget); 1247 1248 work_done = max(max(n_work, a_work), max(rx_work, tx_work)); 1249 if (work_done < budget && napi_complete_done(napi, work_done)) { 1250 flags |= IONIC_INTR_CRED_UNMASK; 1251 intr->rearm_count++; 1252 } 1253 1254 if (work_done || flags) { 1255 flags |= IONIC_INTR_CRED_RESET_COALESCE; 1256 credits = n_work + a_work + rx_work + tx_work; 1257 ionic_intr_credits(idev->intr_ctrl, intr->index, credits, flags); 1258 } 1259 1260 if (lif->doorbell_wa) { 1261 if (!a_work) 1262 ionic_adminq_poke_doorbell(&lif->adminqcq->q); 1263 if (lif->hwstamp_rxq && !rx_work) 1264 ionic_rxq_poke_doorbell(&lif->hwstamp_rxq->q); 1265 if (lif->hwstamp_txq && !tx_work) 1266 ionic_txq_poke_doorbell(&lif->hwstamp_txq->q); 1267 } 1268 1269 return work_done; 1270 } 1271 1272 void ionic_get_stats64(struct net_device *netdev, 1273 struct rtnl_link_stats64 *ns) 1274 { 1275 struct ionic_lif *lif = netdev_priv(netdev); 1276 struct ionic_lif_stats *ls; 1277 1278 memset(ns, 0, sizeof(*ns)); 1279 ls = &lif->info->stats; 1280 1281 ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) + 1282 le64_to_cpu(ls->rx_mcast_packets) + 1283 le64_to_cpu(ls->rx_bcast_packets); 1284 1285 ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) + 1286 le64_to_cpu(ls->tx_mcast_packets) + 1287 le64_to_cpu(ls->tx_bcast_packets); 1288 1289 ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) + 1290 le64_to_cpu(ls->rx_mcast_bytes) + 1291 le64_to_cpu(ls->rx_bcast_bytes); 1292 1293 ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) + 1294 le64_to_cpu(ls->tx_mcast_bytes) + 1295 le64_to_cpu(ls->tx_bcast_bytes); 1296 1297 ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) + 1298 le64_to_cpu(ls->rx_mcast_drop_packets) + 1299 le64_to_cpu(ls->rx_bcast_drop_packets); 1300 1301 ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) + 1302 le64_to_cpu(ls->tx_mcast_drop_packets) + 1303 le64_to_cpu(ls->tx_bcast_drop_packets); 1304 1305 ns->multicast = le64_to_cpu(ls->rx_mcast_packets); 1306 1307 ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty); 1308 1309 ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) + 1310 le64_to_cpu(ls->rx_queue_disabled) + 1311 le64_to_cpu(ls->rx_desc_fetch_error) + 1312 le64_to_cpu(ls->rx_desc_data_error); 1313 1314 ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) + 1315 le64_to_cpu(ls->tx_queue_disabled) + 1316 le64_to_cpu(ls->tx_desc_fetch_error) + 1317 le64_to_cpu(ls->tx_desc_data_error); 1318 1319 ns->rx_errors = ns->rx_over_errors + 1320 ns->rx_missed_errors; 1321 1322 ns->tx_errors = ns->tx_aborted_errors; 1323 } 1324 1325 static int ionic_addr_add(struct net_device *netdev, const u8 *addr) 1326 { 1327 return ionic_lif_list_addr(netdev_priv(netdev), addr, ADD_ADDR); 1328 } 1329 1330 static int ionic_addr_del(struct net_device *netdev, const u8 *addr) 1331 { 1332 /* Don't delete our own address from the uc list */ 1333 if (ether_addr_equal(addr, netdev->dev_addr)) 1334 return 0; 1335 1336 return ionic_lif_list_addr(netdev_priv(netdev), addr, DEL_ADDR); 1337 } 1338 1339 void ionic_lif_rx_mode(struct ionic_lif *lif) 1340 { 1341 struct net_device *netdev = lif->netdev; 1342 unsigned int nfilters; 1343 unsigned int nd_flags; 1344 char buf[128]; 1345 u16 rx_mode; 1346 int i; 1347 #define REMAIN(__x) (sizeof(buf) - (__x)) 1348 1349 mutex_lock(&lif->config_lock); 1350 1351 /* grab the flags once for local use */ 1352 nd_flags = netdev->flags; 1353 1354 rx_mode = IONIC_RX_MODE_F_UNICAST; 1355 rx_mode |= (nd_flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0; 1356 rx_mode |= (nd_flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0; 1357 rx_mode |= (nd_flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0; 1358 rx_mode |= (nd_flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0; 1359 1360 /* sync the filters */ 1361 ionic_rx_filter_sync(lif); 1362 1363 /* check for overflow state 1364 * if so, we track that we overflowed and enable NIC PROMISC 1365 * else if the overflow is set and not needed 1366 * we remove our overflow flag and check the netdev flags 1367 * to see if we can disable NIC PROMISC 1368 */ 1369 nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters); 1370 1371 if (((lif->nucast + lif->nmcast) >= nfilters) || 1372 (lif->max_vlans && lif->nvlans >= lif->max_vlans)) { 1373 rx_mode |= IONIC_RX_MODE_F_PROMISC; 1374 rx_mode |= IONIC_RX_MODE_F_ALLMULTI; 1375 } else { 1376 if (!(nd_flags & IFF_PROMISC)) 1377 rx_mode &= ~IONIC_RX_MODE_F_PROMISC; 1378 if (!(nd_flags & IFF_ALLMULTI)) 1379 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI; 1380 } 1381 1382 i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:", 1383 lif->rx_mode, rx_mode); 1384 if (rx_mode & IONIC_RX_MODE_F_UNICAST) 1385 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST"); 1386 if (rx_mode & IONIC_RX_MODE_F_MULTICAST) 1387 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST"); 1388 if (rx_mode & IONIC_RX_MODE_F_BROADCAST) 1389 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST"); 1390 if (rx_mode & IONIC_RX_MODE_F_PROMISC) 1391 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC"); 1392 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI) 1393 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI"); 1394 if (rx_mode & IONIC_RX_MODE_F_RDMA_SNIFFER) 1395 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_RDMA_SNIFFER"); 1396 netdev_dbg(netdev, "lif%d %s\n", lif->index, buf); 1397 1398 if (lif->rx_mode != rx_mode) { 1399 struct ionic_admin_ctx ctx = { 1400 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1401 .cmd.rx_mode_set = { 1402 .opcode = IONIC_CMD_RX_MODE_SET, 1403 .lif_index = cpu_to_le16(lif->index), 1404 }, 1405 }; 1406 int err; 1407 1408 ctx.cmd.rx_mode_set.rx_mode = cpu_to_le16(rx_mode); 1409 err = ionic_adminq_post_wait(lif, &ctx); 1410 if (err) 1411 netdev_warn(netdev, "set rx_mode 0x%04x failed: %d\n", 1412 rx_mode, err); 1413 else 1414 lif->rx_mode = rx_mode; 1415 } 1416 1417 mutex_unlock(&lif->config_lock); 1418 } 1419 1420 static void ionic_ndo_set_rx_mode(struct net_device *netdev) 1421 { 1422 struct ionic_lif *lif = netdev_priv(netdev); 1423 struct ionic_deferred_work *work; 1424 1425 /* Sync the kernel filter list with the driver filter list */ 1426 __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del); 1427 __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del); 1428 1429 /* Shove off the rest of the rxmode work to the work task 1430 * which will include syncing the filters to the firmware. 1431 */ 1432 work = kzalloc_obj(*work, GFP_ATOMIC); 1433 if (!work) { 1434 netdev_err(lif->netdev, "rxmode change dropped\n"); 1435 return; 1436 } 1437 work->type = IONIC_DW_TYPE_RX_MODE; 1438 netdev_dbg(lif->netdev, "deferred: rx_mode\n"); 1439 ionic_lif_deferred_enqueue(lif, work); 1440 } 1441 1442 static __le64 ionic_netdev_features_to_nic(netdev_features_t features) 1443 { 1444 u64 wanted = 0; 1445 1446 if (features & NETIF_F_HW_VLAN_CTAG_TX) 1447 wanted |= IONIC_ETH_HW_VLAN_TX_TAG; 1448 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1449 wanted |= IONIC_ETH_HW_VLAN_RX_STRIP; 1450 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1451 wanted |= IONIC_ETH_HW_VLAN_RX_FILTER; 1452 if (features & NETIF_F_RXHASH) 1453 wanted |= IONIC_ETH_HW_RX_HASH; 1454 if (features & NETIF_F_RXCSUM) 1455 wanted |= IONIC_ETH_HW_RX_CSUM; 1456 if (features & NETIF_F_SG) 1457 wanted |= IONIC_ETH_HW_TX_SG; 1458 if (features & NETIF_F_HW_CSUM) 1459 wanted |= IONIC_ETH_HW_TX_CSUM; 1460 if (features & NETIF_F_TSO) 1461 wanted |= IONIC_ETH_HW_TSO; 1462 if (features & NETIF_F_TSO6) 1463 wanted |= IONIC_ETH_HW_TSO_IPV6; 1464 if (features & NETIF_F_TSO_ECN) 1465 wanted |= IONIC_ETH_HW_TSO_ECN; 1466 if (features & NETIF_F_GSO_GRE) 1467 wanted |= IONIC_ETH_HW_TSO_GRE; 1468 if (features & NETIF_F_GSO_GRE_CSUM) 1469 wanted |= IONIC_ETH_HW_TSO_GRE_CSUM; 1470 if (features & NETIF_F_GSO_IPXIP4) 1471 wanted |= IONIC_ETH_HW_TSO_IPXIP4; 1472 if (features & NETIF_F_GSO_IPXIP6) 1473 wanted |= IONIC_ETH_HW_TSO_IPXIP6; 1474 if (features & NETIF_F_GSO_UDP_TUNNEL) 1475 wanted |= IONIC_ETH_HW_TSO_UDP; 1476 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) 1477 wanted |= IONIC_ETH_HW_TSO_UDP_CSUM; 1478 1479 return cpu_to_le64(wanted); 1480 } 1481 1482 static int ionic_set_nic_features(struct ionic_lif *lif, 1483 netdev_features_t features) 1484 { 1485 struct device *dev = lif->ionic->dev; 1486 struct ionic_admin_ctx ctx = { 1487 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1488 .cmd.lif_setattr = { 1489 .opcode = IONIC_CMD_LIF_SETATTR, 1490 .index = cpu_to_le16(lif->index), 1491 .attr = IONIC_LIF_ATTR_FEATURES, 1492 }, 1493 }; 1494 u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG | 1495 IONIC_ETH_HW_VLAN_RX_STRIP | 1496 IONIC_ETH_HW_VLAN_RX_FILTER; 1497 u64 old_hw_features; 1498 int err; 1499 1500 ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features); 1501 1502 if (lif->phc) 1503 ctx.cmd.lif_setattr.features |= lif->ionic->ident.lif.eth.config.features & 1504 cpu_to_le64(IONIC_ETH_HW_TIMESTAMP | IONIC_ETH_HW_RDMA_TIMESTAMP); 1505 1506 err = ionic_adminq_post_wait(lif, &ctx); 1507 if (err) 1508 return err; 1509 1510 old_hw_features = lif->hw_features; 1511 lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features & 1512 ctx.comp.lif_setattr.features); 1513 1514 if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH) 1515 ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1516 1517 if ((vlan_flags & le64_to_cpu(ctx.cmd.lif_setattr.features)) && 1518 !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features))) 1519 dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n"); 1520 1521 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1522 dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n"); 1523 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1524 dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n"); 1525 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1526 dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n"); 1527 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1528 dev_dbg(dev, "feature ETH_HW_RX_HASH\n"); 1529 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1530 dev_dbg(dev, "feature ETH_HW_TX_SG\n"); 1531 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1532 dev_dbg(dev, "feature ETH_HW_TX_CSUM\n"); 1533 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1534 dev_dbg(dev, "feature ETH_HW_RX_CSUM\n"); 1535 if (lif->hw_features & IONIC_ETH_HW_TSO) 1536 dev_dbg(dev, "feature ETH_HW_TSO\n"); 1537 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1538 dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n"); 1539 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1540 dev_dbg(dev, "feature ETH_HW_TSO_ECN\n"); 1541 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1542 dev_dbg(dev, "feature ETH_HW_TSO_GRE\n"); 1543 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1544 dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n"); 1545 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1546 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n"); 1547 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1548 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n"); 1549 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1550 dev_dbg(dev, "feature ETH_HW_TSO_UDP\n"); 1551 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1552 dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n"); 1553 if (lif->hw_features & IONIC_ETH_HW_TIMESTAMP) 1554 dev_dbg(dev, "feature ETH_HW_TIMESTAMP\n"); 1555 if (lif->hw_features & IONIC_ETH_HW_RDMA_TIMESTAMP) 1556 dev_dbg(dev, "feature ETH_HW_RDMA_TIMESTAMP\n"); 1557 1558 return 0; 1559 } 1560 1561 static int ionic_init_nic_features(struct ionic_lif *lif) 1562 { 1563 struct net_device *netdev = lif->netdev; 1564 netdev_features_t features; 1565 int err; 1566 1567 /* set up what we expect to support by default */ 1568 features = NETIF_F_HW_VLAN_CTAG_TX | 1569 NETIF_F_HW_VLAN_CTAG_RX | 1570 NETIF_F_HW_VLAN_CTAG_FILTER | 1571 NETIF_F_SG | 1572 NETIF_F_HW_CSUM | 1573 NETIF_F_RXCSUM | 1574 NETIF_F_TSO | 1575 NETIF_F_TSO6 | 1576 NETIF_F_TSO_ECN | 1577 NETIF_F_GSO_GRE | 1578 NETIF_F_GSO_GRE_CSUM | 1579 NETIF_F_GSO_IPXIP4 | 1580 NETIF_F_GSO_IPXIP6 | 1581 NETIF_F_GSO_UDP_TUNNEL | 1582 NETIF_F_GSO_UDP_TUNNEL_CSUM; 1583 1584 if (lif->nxqs > 1) 1585 features |= NETIF_F_RXHASH; 1586 1587 err = ionic_set_nic_features(lif, features); 1588 if (err) 1589 return err; 1590 1591 /* tell the netdev what we actually can support */ 1592 netdev->features |= NETIF_F_HIGHDMA; 1593 1594 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1595 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 1596 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1597 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 1598 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1599 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1600 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1601 netdev->hw_features |= NETIF_F_RXHASH; 1602 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1603 netdev->hw_features |= NETIF_F_SG; 1604 1605 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1606 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 1607 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1608 netdev->hw_enc_features |= NETIF_F_RXCSUM; 1609 if (lif->hw_features & IONIC_ETH_HW_TSO) 1610 netdev->hw_enc_features |= NETIF_F_TSO; 1611 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1612 netdev->hw_enc_features |= NETIF_F_TSO6; 1613 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1614 netdev->hw_enc_features |= NETIF_F_TSO_ECN; 1615 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1616 netdev->hw_enc_features |= NETIF_F_GSO_GRE; 1617 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1618 netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM; 1619 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1620 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4; 1621 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1622 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6; 1623 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1624 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL; 1625 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1626 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 1627 1628 netdev->hw_features |= netdev->hw_enc_features; 1629 netdev->features |= netdev->hw_features; 1630 netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES; 1631 1632 netdev->priv_flags |= IFF_UNICAST_FLT | 1633 IFF_LIVE_ADDR_CHANGE; 1634 1635 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | 1636 NETDEV_XDP_ACT_REDIRECT | 1637 NETDEV_XDP_ACT_RX_SG | 1638 NETDEV_XDP_ACT_NDO_XMIT | 1639 NETDEV_XDP_ACT_NDO_XMIT_SG; 1640 1641 return 0; 1642 } 1643 1644 static int ionic_set_features(struct net_device *netdev, 1645 netdev_features_t features) 1646 { 1647 struct ionic_lif *lif = netdev_priv(netdev); 1648 int err; 1649 1650 netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n", 1651 __func__, (u64)lif->netdev->features, (u64)features); 1652 1653 err = ionic_set_nic_features(lif, features); 1654 1655 return err; 1656 } 1657 1658 static int ionic_set_attr_mac(struct ionic_lif *lif, u8 *mac) 1659 { 1660 struct ionic_admin_ctx ctx = { 1661 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1662 .cmd.lif_setattr = { 1663 .opcode = IONIC_CMD_LIF_SETATTR, 1664 .index = cpu_to_le16(lif->index), 1665 .attr = IONIC_LIF_ATTR_MAC, 1666 }, 1667 }; 1668 1669 ether_addr_copy(ctx.cmd.lif_setattr.mac, mac); 1670 return ionic_adminq_post_wait(lif, &ctx); 1671 } 1672 1673 static int ionic_get_attr_mac(struct ionic_lif *lif, u8 *mac_addr) 1674 { 1675 struct ionic_admin_ctx ctx = { 1676 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1677 .cmd.lif_getattr = { 1678 .opcode = IONIC_CMD_LIF_GETATTR, 1679 .index = cpu_to_le16(lif->index), 1680 .attr = IONIC_LIF_ATTR_MAC, 1681 }, 1682 }; 1683 int err; 1684 1685 err = ionic_adminq_post_wait(lif, &ctx); 1686 if (err) 1687 return err; 1688 1689 ether_addr_copy(mac_addr, ctx.comp.lif_getattr.mac); 1690 return 0; 1691 } 1692 1693 static int ionic_program_mac(struct ionic_lif *lif, u8 *mac) 1694 { 1695 u8 get_mac[ETH_ALEN]; 1696 int err; 1697 1698 err = ionic_set_attr_mac(lif, mac); 1699 if (err) 1700 return err; 1701 1702 err = ionic_get_attr_mac(lif, get_mac); 1703 if (err) 1704 return err; 1705 1706 /* To deal with older firmware that silently ignores the set attr mac: 1707 * doesn't actually change the mac and doesn't return an error, so we 1708 * do the get attr to verify whether or not the set actually happened 1709 */ 1710 if (!ether_addr_equal(get_mac, mac)) 1711 return 1; 1712 1713 return 0; 1714 } 1715 1716 static int ionic_set_mac_address(struct net_device *netdev, void *sa) 1717 { 1718 struct ionic_lif *lif = netdev_priv(netdev); 1719 struct sockaddr *addr = sa; 1720 u8 *mac; 1721 int err; 1722 1723 mac = (u8 *)addr->sa_data; 1724 if (ether_addr_equal(netdev->dev_addr, mac)) 1725 return 0; 1726 1727 /* Only program macs for virtual functions to avoid losing the permanent 1728 * Mac across warm reset/reboot. 1729 */ 1730 if (lif->ionic->pdev->is_virtfn) { 1731 err = ionic_program_mac(lif, mac); 1732 if (err < 0) 1733 return err; 1734 1735 if (err > 0) 1736 netdev_dbg(netdev, "%s: SET and GET ATTR Mac are not equal-due to old FW running\n", 1737 __func__); 1738 } 1739 1740 err = eth_prepare_mac_addr_change(netdev, addr); 1741 if (err) 1742 return err; 1743 1744 if (!is_zero_ether_addr(netdev->dev_addr)) { 1745 netdev_info(netdev, "deleting mac addr %pM\n", 1746 netdev->dev_addr); 1747 ionic_lif_addr_del(netdev_priv(netdev), netdev->dev_addr); 1748 } 1749 1750 eth_commit_mac_addr_change(netdev, addr); 1751 netdev_info(netdev, "updating mac addr %pM\n", mac); 1752 1753 return ionic_lif_addr_add(netdev_priv(netdev), mac); 1754 } 1755 1756 void ionic_stop_queues_reconfig(struct ionic_lif *lif) 1757 { 1758 /* Stop and clean the queues before reconfiguration */ 1759 netif_device_detach(lif->netdev); 1760 ionic_stop_queues(lif); 1761 ionic_txrx_deinit(lif); 1762 } 1763 1764 static int ionic_start_queues_reconfig(struct ionic_lif *lif) 1765 { 1766 int err; 1767 1768 /* Re-init the queues after reconfiguration */ 1769 1770 /* The only way txrx_init can fail here is if communication 1771 * with FW is suddenly broken. There's not much we can do 1772 * at this point - error messages have already been printed, 1773 * so we can continue on and the user can eventually do a 1774 * DOWN and UP to try to reset and clear the issue. 1775 */ 1776 err = ionic_txrx_init(lif); 1777 ionic_link_status_check_request(lif, CAN_NOT_SLEEP); 1778 netif_device_attach(lif->netdev); 1779 1780 return err; 1781 } 1782 1783 static bool ionic_xdp_is_valid_mtu(struct ionic_lif *lif, u32 mtu, 1784 struct bpf_prog *xdp_prog) 1785 { 1786 if (!xdp_prog) 1787 return true; 1788 1789 if (mtu <= IONIC_XDP_MAX_LINEAR_MTU) 1790 return true; 1791 1792 if (xdp_prog->aux && xdp_prog->aux->xdp_has_frags) 1793 return true; 1794 1795 return false; 1796 } 1797 1798 static int ionic_change_mtu(struct net_device *netdev, int new_mtu) 1799 { 1800 struct ionic_lif *lif = netdev_priv(netdev); 1801 struct ionic_admin_ctx ctx = { 1802 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1803 .cmd.lif_setattr = { 1804 .opcode = IONIC_CMD_LIF_SETATTR, 1805 .index = cpu_to_le16(lif->index), 1806 .attr = IONIC_LIF_ATTR_MTU, 1807 .mtu = cpu_to_le32(new_mtu), 1808 }, 1809 }; 1810 struct bpf_prog *xdp_prog; 1811 int err; 1812 1813 xdp_prog = READ_ONCE(lif->xdp_prog); 1814 if (!ionic_xdp_is_valid_mtu(lif, new_mtu, xdp_prog)) 1815 return -EINVAL; 1816 1817 err = ionic_adminq_post_wait(lif, &ctx); 1818 if (err) 1819 return err; 1820 1821 /* if we're not running, nothing more to do */ 1822 if (!netif_running(netdev)) { 1823 WRITE_ONCE(netdev->mtu, new_mtu); 1824 return 0; 1825 } 1826 1827 mutex_lock(&lif->queue_lock); 1828 ionic_stop_queues_reconfig(lif); 1829 WRITE_ONCE(netdev->mtu, new_mtu); 1830 err = ionic_start_queues_reconfig(lif); 1831 mutex_unlock(&lif->queue_lock); 1832 1833 return err; 1834 } 1835 1836 static void ionic_tx_timeout_work(struct work_struct *ws) 1837 { 1838 struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work); 1839 int err; 1840 1841 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 1842 return; 1843 1844 /* if we were stopped before this scheduled job was launched, 1845 * don't bother the queues as they are already stopped. 1846 */ 1847 if (!netif_running(lif->netdev)) 1848 return; 1849 1850 mutex_lock(&lif->queue_lock); 1851 ionic_stop_queues_reconfig(lif); 1852 err = ionic_start_queues_reconfig(lif); 1853 mutex_unlock(&lif->queue_lock); 1854 1855 if (err) 1856 dev_err(lif->ionic->dev, "%s: Restarting queues failed\n", __func__); 1857 } 1858 1859 static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1860 { 1861 struct ionic_lif *lif = netdev_priv(netdev); 1862 1863 netdev_info(lif->netdev, "Tx Timeout triggered - txq %d\n", txqueue); 1864 schedule_work(&lif->tx_timeout_work); 1865 } 1866 1867 static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, 1868 u16 vid) 1869 { 1870 struct ionic_lif *lif = netdev_priv(netdev); 1871 int err; 1872 1873 err = ionic_lif_vlan_add(lif, vid); 1874 if (err) 1875 return err; 1876 1877 ionic_lif_rx_mode(lif); 1878 1879 return 0; 1880 } 1881 1882 static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, 1883 u16 vid) 1884 { 1885 struct ionic_lif *lif = netdev_priv(netdev); 1886 int err; 1887 1888 err = ionic_lif_vlan_del(lif, vid); 1889 if (err) 1890 return err; 1891 1892 ionic_lif_rx_mode(lif); 1893 1894 return 0; 1895 } 1896 1897 int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types, 1898 const u8 *key, const u32 *indir) 1899 { 1900 struct ionic_admin_ctx ctx = { 1901 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1902 .cmd.lif_setattr = { 1903 .opcode = IONIC_CMD_LIF_SETATTR, 1904 .attr = IONIC_LIF_ATTR_RSS, 1905 .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa), 1906 }, 1907 }; 1908 unsigned int i, tbl_sz; 1909 1910 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) { 1911 lif->rss_types = types; 1912 ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types); 1913 } 1914 1915 if (key) 1916 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE); 1917 1918 if (indir) { 1919 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1920 for (i = 0; i < tbl_sz; i++) 1921 lif->rss_ind_tbl[i] = indir[i]; 1922 } 1923 1924 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key, 1925 IONIC_RSS_HASH_KEY_SIZE); 1926 1927 return ionic_adminq_post_wait(lif, &ctx); 1928 } 1929 1930 static int ionic_lif_rss_init(struct ionic_lif *lif) 1931 { 1932 unsigned int tbl_sz; 1933 unsigned int i; 1934 1935 lif->rss_types = IONIC_RSS_TYPE_IPV4 | 1936 IONIC_RSS_TYPE_IPV4_TCP | 1937 IONIC_RSS_TYPE_IPV4_UDP | 1938 IONIC_RSS_TYPE_IPV6 | 1939 IONIC_RSS_TYPE_IPV6_TCP | 1940 IONIC_RSS_TYPE_IPV6_UDP; 1941 1942 /* Fill indirection table with 'default' values */ 1943 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1944 for (i = 0; i < tbl_sz; i++) 1945 lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs); 1946 1947 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1948 } 1949 1950 static void ionic_lif_rss_deinit(struct ionic_lif *lif) 1951 { 1952 int tbl_sz; 1953 1954 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1955 memset(lif->rss_ind_tbl, 0, tbl_sz); 1956 memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE); 1957 1958 ionic_lif_rss_config(lif, 0x0, NULL, NULL); 1959 } 1960 1961 static void ionic_lif_quiesce(struct ionic_lif *lif) 1962 { 1963 struct ionic_admin_ctx ctx = { 1964 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1965 .cmd.lif_setattr = { 1966 .opcode = IONIC_CMD_LIF_SETATTR, 1967 .index = cpu_to_le16(lif->index), 1968 .attr = IONIC_LIF_ATTR_STATE, 1969 .state = IONIC_LIF_QUIESCE, 1970 }, 1971 }; 1972 int err; 1973 1974 err = ionic_adminq_post_wait(lif, &ctx); 1975 if (err) 1976 netdev_dbg(lif->netdev, "lif quiesce failed %d\n", err); 1977 } 1978 1979 static void ionic_txrx_disable(struct ionic_lif *lif) 1980 { 1981 unsigned int i; 1982 int err = 0; 1983 1984 if (lif->txqcqs) { 1985 for (i = 0; i < lif->nxqs; i++) 1986 err = ionic_qcq_disable(lif, lif->txqcqs[i], err); 1987 } 1988 1989 if (lif->hwstamp_txq) 1990 err = ionic_qcq_disable(lif, lif->hwstamp_txq, err); 1991 1992 if (lif->rxqcqs) { 1993 for (i = 0; i < lif->nxqs; i++) 1994 err = ionic_qcq_disable(lif, lif->rxqcqs[i], err); 1995 } 1996 1997 if (lif->hwstamp_rxq) 1998 err = ionic_qcq_disable(lif, lif->hwstamp_rxq, err); 1999 2000 ionic_lif_quiesce(lif); 2001 } 2002 2003 static void ionic_txrx_deinit(struct ionic_lif *lif) 2004 { 2005 unsigned int i; 2006 2007 if (lif->txqcqs) { 2008 for (i = 0; i < lif->nxqs && lif->txqcqs[i]; i++) { 2009 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 2010 ionic_tx_flush(&lif->txqcqs[i]->cq); 2011 ionic_tx_empty(&lif->txqcqs[i]->q); 2012 } 2013 } 2014 2015 if (lif->rxqcqs) { 2016 for (i = 0; i < lif->nxqs && lif->rxqcqs[i]; i++) { 2017 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 2018 ionic_rx_empty(&lif->rxqcqs[i]->q); 2019 } 2020 } 2021 lif->rx_mode = 0; 2022 2023 if (lif->hwstamp_txq) { 2024 ionic_lif_qcq_deinit(lif, lif->hwstamp_txq); 2025 ionic_tx_flush(&lif->hwstamp_txq->cq); 2026 ionic_tx_empty(&lif->hwstamp_txq->q); 2027 } 2028 2029 if (lif->hwstamp_rxq) { 2030 ionic_lif_qcq_deinit(lif, lif->hwstamp_rxq); 2031 ionic_rx_empty(&lif->hwstamp_rxq->q); 2032 } 2033 } 2034 2035 void ionic_txrx_free(struct ionic_lif *lif) 2036 { 2037 unsigned int i; 2038 2039 if (lif->txqcqs) { 2040 for (i = 0; i < lif->ionic->ntxqs_per_lif && lif->txqcqs[i]; i++) { 2041 ionic_qcq_free(lif, lif->txqcqs[i]); 2042 devm_kfree(lif->ionic->dev, lif->txqcqs[i]); 2043 lif->txqcqs[i] = NULL; 2044 } 2045 } 2046 2047 if (lif->rxqcqs) { 2048 for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) { 2049 ionic_qcq_free(lif, lif->rxqcqs[i]); 2050 devm_kfree(lif->ionic->dev, lif->rxqcqs[i]); 2051 lif->rxqcqs[i] = NULL; 2052 } 2053 } 2054 2055 if (lif->hwstamp_txq) { 2056 ionic_qcq_free(lif, lif->hwstamp_txq); 2057 devm_kfree(lif->ionic->dev, lif->hwstamp_txq); 2058 lif->hwstamp_txq = NULL; 2059 } 2060 2061 if (lif->hwstamp_rxq) { 2062 ionic_qcq_free(lif, lif->hwstamp_rxq); 2063 devm_kfree(lif->ionic->dev, lif->hwstamp_rxq); 2064 lif->hwstamp_rxq = NULL; 2065 } 2066 } 2067 2068 static int ionic_txrx_alloc(struct ionic_lif *lif) 2069 { 2070 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz; 2071 unsigned int flags, i; 2072 int err = 0; 2073 2074 num_desc = lif->ntxq_descs; 2075 desc_sz = sizeof(struct ionic_txq_desc); 2076 comp_sz = sizeof(struct ionic_txq_comp); 2077 2078 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 2079 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 2080 sizeof(struct ionic_txq_sg_desc_v1)) 2081 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 2082 else 2083 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 2084 2085 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 2086 2087 if (test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state)) 2088 flags |= IONIC_QCQ_F_CMB_RINGS; 2089 2090 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 2091 flags |= IONIC_QCQ_F_INTR; 2092 2093 for (i = 0; i < lif->nxqs; i++) { 2094 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 2095 num_desc, desc_sz, comp_sz, sg_desc_sz, 2096 sizeof(struct ionic_tx_desc_info), 2097 lif->kern_pid, NULL, &lif->txqcqs[i]); 2098 if (err) 2099 goto err_out; 2100 2101 if (flags & IONIC_QCQ_F_INTR) { 2102 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2103 lif->txqcqs[i]->intr.index, 2104 lif->tx_coalesce_hw); 2105 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 2106 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 2107 } 2108 2109 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 2110 } 2111 2112 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG | IONIC_QCQ_F_INTR; 2113 2114 if (test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state)) 2115 flags |= IONIC_QCQ_F_CMB_RINGS; 2116 2117 num_desc = lif->nrxq_descs; 2118 desc_sz = sizeof(struct ionic_rxq_desc); 2119 comp_sz = sizeof(struct ionic_rxq_comp); 2120 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 2121 2122 if (lif->rxq_features & IONIC_Q_F_2X_CQ_DESC) 2123 comp_sz *= 2; 2124 2125 for (i = 0; i < lif->nxqs; i++) { 2126 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 2127 num_desc, desc_sz, comp_sz, sg_desc_sz, 2128 sizeof(struct ionic_rx_desc_info), 2129 lif->kern_pid, lif->xdp_prog, 2130 &lif->rxqcqs[i]); 2131 if (err) 2132 goto err_out; 2133 2134 lif->rxqcqs[i]->q.features = lif->rxq_features; 2135 2136 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2137 lif->rxqcqs[i]->intr.index, 2138 lif->rx_coalesce_hw); 2139 if (test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state)) 2140 lif->rxqcqs[i]->intr.dim_coal_hw = lif->rx_coalesce_hw; 2141 2142 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 2143 ionic_link_qcq_interrupts(lif->rxqcqs[i], 2144 lif->txqcqs[i]); 2145 2146 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 2147 } 2148 2149 return 0; 2150 2151 err_out: 2152 ionic_txrx_free(lif); 2153 2154 return err; 2155 } 2156 2157 static int ionic_txrx_init(struct ionic_lif *lif) 2158 { 2159 unsigned int i; 2160 int err; 2161 2162 for (i = 0; i < lif->nxqs; i++) { 2163 err = ionic_lif_txq_init(lif, lif->txqcqs[i]); 2164 if (err) 2165 goto err_out; 2166 2167 err = ionic_lif_rxq_init(lif, lif->rxqcqs[i]); 2168 if (err) { 2169 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 2170 goto err_out; 2171 } 2172 } 2173 2174 if (lif->netdev->features & NETIF_F_RXHASH) 2175 ionic_lif_rss_init(lif); 2176 2177 ionic_lif_rx_mode(lif); 2178 2179 return 0; 2180 2181 err_out: 2182 while (i--) { 2183 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 2184 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 2185 } 2186 2187 return err; 2188 } 2189 2190 static int ionic_txrx_enable(struct ionic_lif *lif) 2191 { 2192 int derr = 0; 2193 int i, err; 2194 2195 ionic_xdp_rxqs_prog_update(lif); 2196 2197 for (i = 0; i < lif->nxqs; i++) { 2198 if (!(lif->rxqcqs[i] && lif->txqcqs[i])) { 2199 dev_err(lif->ionic->dev, "%s: bad qcq %d\n", __func__, i); 2200 err = -ENXIO; 2201 goto err_out; 2202 } 2203 2204 ionic_rx_fill(&lif->rxqcqs[i]->q, 2205 READ_ONCE(lif->rxqcqs[i]->q.xdp_prog)); 2206 err = ionic_qcq_enable(lif->rxqcqs[i]); 2207 if (err) 2208 goto err_out; 2209 2210 err = ionic_qcq_enable(lif->txqcqs[i]); 2211 if (err) { 2212 derr = ionic_qcq_disable(lif, lif->rxqcqs[i], err); 2213 goto err_out; 2214 } 2215 } 2216 2217 if (lif->hwstamp_rxq) { 2218 ionic_rx_fill(&lif->hwstamp_rxq->q, NULL); 2219 err = ionic_qcq_enable(lif->hwstamp_rxq); 2220 if (err) 2221 goto err_out_hwstamp_rx; 2222 } 2223 2224 if (lif->hwstamp_txq) { 2225 err = ionic_qcq_enable(lif->hwstamp_txq); 2226 if (err) 2227 goto err_out_hwstamp_tx; 2228 } 2229 2230 return 0; 2231 2232 err_out_hwstamp_tx: 2233 if (lif->hwstamp_rxq) 2234 derr = ionic_qcq_disable(lif, lif->hwstamp_rxq, derr); 2235 err_out_hwstamp_rx: 2236 i = lif->nxqs; 2237 err_out: 2238 while (i--) { 2239 derr = ionic_qcq_disable(lif, lif->txqcqs[i], derr); 2240 derr = ionic_qcq_disable(lif, lif->rxqcqs[i], derr); 2241 } 2242 2243 ionic_xdp_rxqs_prog_update(lif); 2244 2245 return err; 2246 } 2247 2248 static int ionic_start_queues(struct ionic_lif *lif) 2249 { 2250 int err; 2251 2252 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) 2253 return -EIO; 2254 2255 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2256 return -EBUSY; 2257 2258 if (test_and_set_bit(IONIC_LIF_F_UP, lif->state)) 2259 return 0; 2260 2261 err = ionic_txrx_enable(lif); 2262 if (err) { 2263 clear_bit(IONIC_LIF_F_UP, lif->state); 2264 return err; 2265 } 2266 netif_tx_wake_all_queues(lif->netdev); 2267 2268 return 0; 2269 } 2270 2271 static int ionic_open(struct net_device *netdev) 2272 { 2273 struct ionic_lif *lif = netdev_priv(netdev); 2274 int err; 2275 2276 /* If recovering from a broken state, clear the bit and we'll try again */ 2277 if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state)) 2278 netdev_info(netdev, "clearing broken state\n"); 2279 2280 mutex_lock(&lif->queue_lock); 2281 2282 err = ionic_txrx_alloc(lif); 2283 if (err) 2284 goto err_unlock; 2285 2286 err = ionic_txrx_init(lif); 2287 if (err) 2288 goto err_txrx_free; 2289 2290 err = netif_set_real_num_tx_queues(netdev, lif->nxqs); 2291 if (err) 2292 goto err_txrx_deinit; 2293 2294 err = netif_set_real_num_rx_queues(netdev, lif->nxqs); 2295 if (err) 2296 goto err_txrx_deinit; 2297 2298 /* don't start the queues until we have link */ 2299 if (netif_carrier_ok(netdev)) { 2300 err = ionic_start_queues(lif); 2301 if (err) 2302 goto err_txrx_deinit; 2303 } 2304 2305 /* If hardware timestamping is enabled, but the queues were freed by 2306 * ionic_stop, those need to be reallocated and initialized, too. 2307 */ 2308 ionic_lif_hwstamp_recreate_queues(lif); 2309 2310 mutex_unlock(&lif->queue_lock); 2311 2312 return 0; 2313 2314 err_txrx_deinit: 2315 ionic_txrx_deinit(lif); 2316 err_txrx_free: 2317 ionic_txrx_free(lif); 2318 err_unlock: 2319 mutex_unlock(&lif->queue_lock); 2320 return err; 2321 } 2322 2323 static void ionic_stop_queues(struct ionic_lif *lif) 2324 { 2325 if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state)) 2326 return; 2327 2328 netif_tx_disable(lif->netdev); 2329 ionic_txrx_disable(lif); 2330 } 2331 2332 static int ionic_stop(struct net_device *netdev) 2333 { 2334 struct ionic_lif *lif = netdev_priv(netdev); 2335 2336 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2337 return 0; 2338 2339 mutex_lock(&lif->queue_lock); 2340 ionic_stop_queues(lif); 2341 ionic_txrx_deinit(lif); 2342 ionic_txrx_free(lif); 2343 mutex_unlock(&lif->queue_lock); 2344 2345 return 0; 2346 } 2347 2348 static int ionic_get_vf_config(struct net_device *netdev, 2349 int vf, struct ifla_vf_info *ivf) 2350 { 2351 struct ionic_lif *lif = netdev_priv(netdev); 2352 struct ionic *ionic = lif->ionic; 2353 int ret = 0; 2354 2355 if (!netif_device_present(netdev)) 2356 return -EBUSY; 2357 2358 down_read(&ionic->vf_op_lock); 2359 2360 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2361 ret = -EINVAL; 2362 } else { 2363 struct ionic_vf *vfdata = &ionic->vfs[vf]; 2364 2365 ivf->vf = vf; 2366 ivf->qos = 0; 2367 ivf->vlan = le16_to_cpu(vfdata->vlanid); 2368 ivf->spoofchk = vfdata->spoofchk; 2369 ivf->linkstate = vfdata->linkstate; 2370 ivf->max_tx_rate = le32_to_cpu(vfdata->maxrate); 2371 ivf->trusted = vfdata->trusted; 2372 ether_addr_copy(ivf->mac, vfdata->macaddr); 2373 } 2374 2375 up_read(&ionic->vf_op_lock); 2376 return ret; 2377 } 2378 2379 static int ionic_get_vf_stats(struct net_device *netdev, int vf, 2380 struct ifla_vf_stats *vf_stats) 2381 { 2382 struct ionic_lif *lif = netdev_priv(netdev); 2383 struct ionic *ionic = lif->ionic; 2384 struct ionic_lif_stats *vs; 2385 int ret = 0; 2386 2387 if (!netif_device_present(netdev)) 2388 return -EBUSY; 2389 2390 down_read(&ionic->vf_op_lock); 2391 2392 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2393 ret = -EINVAL; 2394 } else { 2395 memset(vf_stats, 0, sizeof(*vf_stats)); 2396 vs = &ionic->vfs[vf].stats; 2397 2398 vf_stats->rx_packets = le64_to_cpu(vs->rx_ucast_packets); 2399 vf_stats->tx_packets = le64_to_cpu(vs->tx_ucast_packets); 2400 vf_stats->rx_bytes = le64_to_cpu(vs->rx_ucast_bytes); 2401 vf_stats->tx_bytes = le64_to_cpu(vs->tx_ucast_bytes); 2402 vf_stats->broadcast = le64_to_cpu(vs->rx_bcast_packets); 2403 vf_stats->multicast = le64_to_cpu(vs->rx_mcast_packets); 2404 vf_stats->rx_dropped = le64_to_cpu(vs->rx_ucast_drop_packets) + 2405 le64_to_cpu(vs->rx_mcast_drop_packets) + 2406 le64_to_cpu(vs->rx_bcast_drop_packets); 2407 vf_stats->tx_dropped = le64_to_cpu(vs->tx_ucast_drop_packets) + 2408 le64_to_cpu(vs->tx_mcast_drop_packets) + 2409 le64_to_cpu(vs->tx_bcast_drop_packets); 2410 } 2411 2412 up_read(&ionic->vf_op_lock); 2413 return ret; 2414 } 2415 2416 static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2417 { 2418 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_MAC }; 2419 struct ionic_lif *lif = netdev_priv(netdev); 2420 struct ionic *ionic = lif->ionic; 2421 int ret; 2422 2423 if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac))) 2424 return -EINVAL; 2425 2426 if (!netif_device_present(netdev)) 2427 return -EBUSY; 2428 2429 down_write(&ionic->vf_op_lock); 2430 2431 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2432 ret = -EINVAL; 2433 } else { 2434 ether_addr_copy(vfc.macaddr, mac); 2435 dev_dbg(ionic->dev, "%s: vf %d macaddr %pM\n", 2436 __func__, vf, vfc.macaddr); 2437 2438 ret = ionic_set_vf_config(ionic, vf, &vfc); 2439 if (!ret) 2440 ether_addr_copy(ionic->vfs[vf].macaddr, mac); 2441 } 2442 2443 up_write(&ionic->vf_op_lock); 2444 return ret; 2445 } 2446 2447 static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 2448 u8 qos, __be16 proto) 2449 { 2450 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_VLAN }; 2451 struct ionic_lif *lif = netdev_priv(netdev); 2452 struct ionic *ionic = lif->ionic; 2453 int ret; 2454 2455 /* until someday when we support qos */ 2456 if (qos) 2457 return -EINVAL; 2458 2459 if (vlan > 4095) 2460 return -EINVAL; 2461 2462 if (proto != htons(ETH_P_8021Q)) 2463 return -EPROTONOSUPPORT; 2464 2465 if (!netif_device_present(netdev)) 2466 return -EBUSY; 2467 2468 down_write(&ionic->vf_op_lock); 2469 2470 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2471 ret = -EINVAL; 2472 } else { 2473 vfc.vlanid = cpu_to_le16(vlan); 2474 dev_dbg(ionic->dev, "%s: vf %d vlan %d\n", 2475 __func__, vf, le16_to_cpu(vfc.vlanid)); 2476 2477 ret = ionic_set_vf_config(ionic, vf, &vfc); 2478 if (!ret) 2479 ionic->vfs[vf].vlanid = cpu_to_le16(vlan); 2480 } 2481 2482 up_write(&ionic->vf_op_lock); 2483 return ret; 2484 } 2485 2486 static int ionic_set_vf_rate(struct net_device *netdev, int vf, 2487 int tx_min, int tx_max) 2488 { 2489 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_RATE }; 2490 struct ionic_lif *lif = netdev_priv(netdev); 2491 struct ionic *ionic = lif->ionic; 2492 int ret; 2493 2494 /* setting the min just seems silly */ 2495 if (tx_min) 2496 return -EINVAL; 2497 2498 if (!netif_device_present(netdev)) 2499 return -EBUSY; 2500 2501 down_write(&ionic->vf_op_lock); 2502 2503 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2504 ret = -EINVAL; 2505 } else { 2506 vfc.maxrate = cpu_to_le32(tx_max); 2507 dev_dbg(ionic->dev, "%s: vf %d maxrate %d\n", 2508 __func__, vf, le32_to_cpu(vfc.maxrate)); 2509 2510 ret = ionic_set_vf_config(ionic, vf, &vfc); 2511 if (!ret) 2512 ionic->vfs[vf].maxrate = cpu_to_le32(tx_max); 2513 } 2514 2515 up_write(&ionic->vf_op_lock); 2516 return ret; 2517 } 2518 2519 static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set) 2520 { 2521 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_SPOOFCHK }; 2522 struct ionic_lif *lif = netdev_priv(netdev); 2523 struct ionic *ionic = lif->ionic; 2524 int ret; 2525 2526 if (!netif_device_present(netdev)) 2527 return -EBUSY; 2528 2529 down_write(&ionic->vf_op_lock); 2530 2531 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2532 ret = -EINVAL; 2533 } else { 2534 vfc.spoofchk = set; 2535 dev_dbg(ionic->dev, "%s: vf %d spoof %d\n", 2536 __func__, vf, vfc.spoofchk); 2537 2538 ret = ionic_set_vf_config(ionic, vf, &vfc); 2539 if (!ret) 2540 ionic->vfs[vf].spoofchk = set; 2541 } 2542 2543 up_write(&ionic->vf_op_lock); 2544 return ret; 2545 } 2546 2547 static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set) 2548 { 2549 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_TRUST }; 2550 struct ionic_lif *lif = netdev_priv(netdev); 2551 struct ionic *ionic = lif->ionic; 2552 int ret; 2553 2554 if (!netif_device_present(netdev)) 2555 return -EBUSY; 2556 2557 down_write(&ionic->vf_op_lock); 2558 2559 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2560 ret = -EINVAL; 2561 } else { 2562 vfc.trust = set; 2563 dev_dbg(ionic->dev, "%s: vf %d trust %d\n", 2564 __func__, vf, vfc.trust); 2565 2566 ret = ionic_set_vf_config(ionic, vf, &vfc); 2567 if (!ret) 2568 ionic->vfs[vf].trusted = set; 2569 } 2570 2571 up_write(&ionic->vf_op_lock); 2572 return ret; 2573 } 2574 2575 static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set) 2576 { 2577 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_LINKSTATE }; 2578 struct ionic_lif *lif = netdev_priv(netdev); 2579 struct ionic *ionic = lif->ionic; 2580 u8 vfls; 2581 int ret; 2582 2583 switch (set) { 2584 case IFLA_VF_LINK_STATE_ENABLE: 2585 vfls = IONIC_VF_LINK_STATUS_UP; 2586 break; 2587 case IFLA_VF_LINK_STATE_DISABLE: 2588 vfls = IONIC_VF_LINK_STATUS_DOWN; 2589 break; 2590 case IFLA_VF_LINK_STATE_AUTO: 2591 vfls = IONIC_VF_LINK_STATUS_AUTO; 2592 break; 2593 default: 2594 return -EINVAL; 2595 } 2596 2597 if (!netif_device_present(netdev)) 2598 return -EBUSY; 2599 2600 down_write(&ionic->vf_op_lock); 2601 2602 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2603 ret = -EINVAL; 2604 } else { 2605 vfc.linkstate = vfls; 2606 dev_dbg(ionic->dev, "%s: vf %d linkstate %d\n", 2607 __func__, vf, vfc.linkstate); 2608 2609 ret = ionic_set_vf_config(ionic, vf, &vfc); 2610 if (!ret) 2611 ionic->vfs[vf].linkstate = set; 2612 } 2613 2614 up_write(&ionic->vf_op_lock); 2615 return ret; 2616 } 2617 2618 static void ionic_vf_attr_replay(struct ionic_lif *lif) 2619 { 2620 struct ionic_vf_setattr_cmd vfc = { }; 2621 struct ionic *ionic = lif->ionic; 2622 struct ionic_vf *v; 2623 int i; 2624 2625 if (!ionic->vfs) 2626 return; 2627 2628 down_read(&ionic->vf_op_lock); 2629 2630 for (i = 0; i < ionic->num_vfs; i++) { 2631 v = &ionic->vfs[i]; 2632 2633 if (v->stats_pa) { 2634 vfc.attr = IONIC_VF_ATTR_STATSADDR; 2635 vfc.stats_pa = cpu_to_le64(v->stats_pa); 2636 ionic_set_vf_config(ionic, i, &vfc); 2637 vfc.stats_pa = 0; 2638 } 2639 2640 if (!is_zero_ether_addr(v->macaddr)) { 2641 vfc.attr = IONIC_VF_ATTR_MAC; 2642 ether_addr_copy(vfc.macaddr, v->macaddr); 2643 ionic_set_vf_config(ionic, i, &vfc); 2644 eth_zero_addr(vfc.macaddr); 2645 } 2646 2647 if (v->vlanid) { 2648 vfc.attr = IONIC_VF_ATTR_VLAN; 2649 vfc.vlanid = v->vlanid; 2650 ionic_set_vf_config(ionic, i, &vfc); 2651 vfc.vlanid = 0; 2652 } 2653 2654 if (v->maxrate) { 2655 vfc.attr = IONIC_VF_ATTR_RATE; 2656 vfc.maxrate = v->maxrate; 2657 ionic_set_vf_config(ionic, i, &vfc); 2658 vfc.maxrate = 0; 2659 } 2660 2661 if (v->spoofchk) { 2662 vfc.attr = IONIC_VF_ATTR_SPOOFCHK; 2663 vfc.spoofchk = v->spoofchk; 2664 ionic_set_vf_config(ionic, i, &vfc); 2665 vfc.spoofchk = 0; 2666 } 2667 2668 if (v->trusted) { 2669 vfc.attr = IONIC_VF_ATTR_TRUST; 2670 vfc.trust = v->trusted; 2671 ionic_set_vf_config(ionic, i, &vfc); 2672 vfc.trust = 0; 2673 } 2674 2675 if (v->linkstate) { 2676 vfc.attr = IONIC_VF_ATTR_LINKSTATE; 2677 vfc.linkstate = v->linkstate; 2678 ionic_set_vf_config(ionic, i, &vfc); 2679 vfc.linkstate = 0; 2680 } 2681 } 2682 2683 up_read(&ionic->vf_op_lock); 2684 2685 ionic_vf_start(ionic); 2686 } 2687 2688 static void ionic_unregister_rxq_info(struct ionic_queue *q) 2689 { 2690 struct xdp_rxq_info *xi; 2691 2692 if (!q->xdp_rxq_info) 2693 return; 2694 2695 xi = q->xdp_rxq_info; 2696 q->xdp_rxq_info = NULL; 2697 2698 xdp_rxq_info_unreg(xi); 2699 kfree(xi); 2700 } 2701 2702 static int ionic_register_rxq_info(struct ionic_queue *q, unsigned int napi_id) 2703 { 2704 struct xdp_rxq_info *rxq_info; 2705 int err; 2706 2707 rxq_info = kzalloc_obj(*rxq_info); 2708 if (!rxq_info) 2709 return -ENOMEM; 2710 2711 err = xdp_rxq_info_reg(rxq_info, q->lif->netdev, q->index, napi_id); 2712 if (err) { 2713 netdev_err(q->lif->netdev, "q%d xdp_rxq_info_reg failed, err %d\n", 2714 q->index, err); 2715 goto err_out; 2716 } 2717 2718 err = xdp_rxq_info_reg_mem_model(rxq_info, MEM_TYPE_PAGE_POOL, q->page_pool); 2719 if (err) { 2720 netdev_err(q->lif->netdev, "q%d xdp_rxq_info_reg_mem_model failed, err %d\n", 2721 q->index, err); 2722 xdp_rxq_info_unreg(rxq_info); 2723 goto err_out; 2724 } 2725 2726 q->xdp_rxq_info = rxq_info; 2727 2728 return 0; 2729 2730 err_out: 2731 kfree(rxq_info); 2732 return err; 2733 } 2734 2735 static void ionic_xdp_rxqs_prog_update(struct ionic_lif *lif) 2736 { 2737 struct bpf_prog *xdp_prog; 2738 unsigned int i; 2739 2740 if (!lif->rxqcqs) 2741 return; 2742 2743 xdp_prog = READ_ONCE(lif->xdp_prog); 2744 for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) { 2745 struct ionic_queue *q = &lif->rxqcqs[i]->q; 2746 2747 WRITE_ONCE(q->xdp_prog, xdp_prog); 2748 } 2749 } 2750 2751 static int ionic_xdp_config(struct net_device *netdev, struct netdev_bpf *bpf) 2752 { 2753 struct ionic_lif *lif = netdev_priv(netdev); 2754 struct bpf_prog *old_prog; 2755 u32 maxfs; 2756 2757 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) { 2758 #define XDP_ERR_SPLIT "XDP not available with split Tx/Rx interrupts" 2759 NL_SET_ERR_MSG_MOD(bpf->extack, XDP_ERR_SPLIT); 2760 netdev_info(lif->netdev, XDP_ERR_SPLIT); 2761 return -EOPNOTSUPP; 2762 } 2763 2764 if (!ionic_xdp_is_valid_mtu(lif, netdev->mtu, bpf->prog)) { 2765 #define XDP_ERR_MTU "MTU is too large for XDP without frags support" 2766 NL_SET_ERR_MSG_MOD(bpf->extack, XDP_ERR_MTU); 2767 netdev_info(lif->netdev, XDP_ERR_MTU); 2768 return -EINVAL; 2769 } 2770 2771 maxfs = __le32_to_cpu(lif->identity->eth.max_frame_size) - VLAN_ETH_HLEN; 2772 if (bpf->prog && !(bpf->prog->aux && bpf->prog->aux->xdp_has_frags)) 2773 maxfs = min_t(u32, maxfs, IONIC_XDP_MAX_LINEAR_MTU); 2774 netdev->max_mtu = maxfs; 2775 2776 if (!netif_running(netdev)) { 2777 old_prog = xchg(&lif->xdp_prog, bpf->prog); 2778 } else if (lif->xdp_prog && bpf->prog) { 2779 old_prog = xchg(&lif->xdp_prog, bpf->prog); 2780 ionic_xdp_rxqs_prog_update(lif); 2781 } else { 2782 struct ionic_queue_params qparams; 2783 2784 ionic_init_queue_params(lif, &qparams); 2785 qparams.xdp_prog = bpf->prog; 2786 mutex_lock(&lif->queue_lock); 2787 ionic_reconfigure_queues(lif, &qparams); 2788 old_prog = xchg(&lif->xdp_prog, bpf->prog); 2789 mutex_unlock(&lif->queue_lock); 2790 } 2791 2792 if (old_prog) 2793 bpf_prog_put(old_prog); 2794 2795 return 0; 2796 } 2797 2798 static int ionic_xdp(struct net_device *netdev, struct netdev_bpf *bpf) 2799 { 2800 switch (bpf->command) { 2801 case XDP_SETUP_PROG: 2802 return ionic_xdp_config(netdev, bpf); 2803 default: 2804 return -EINVAL; 2805 } 2806 } 2807 2808 static const struct net_device_ops ionic_netdev_ops = { 2809 .ndo_open = ionic_open, 2810 .ndo_stop = ionic_stop, 2811 .ndo_start_xmit = ionic_start_xmit, 2812 .ndo_bpf = ionic_xdp, 2813 .ndo_xdp_xmit = ionic_xdp_xmit, 2814 .ndo_get_stats64 = ionic_get_stats64, 2815 .ndo_set_rx_mode = ionic_ndo_set_rx_mode, 2816 .ndo_set_features = ionic_set_features, 2817 .ndo_set_mac_address = ionic_set_mac_address, 2818 .ndo_validate_addr = eth_validate_addr, 2819 .ndo_tx_timeout = ionic_tx_timeout, 2820 .ndo_change_mtu = ionic_change_mtu, 2821 .ndo_vlan_rx_add_vid = ionic_vlan_rx_add_vid, 2822 .ndo_vlan_rx_kill_vid = ionic_vlan_rx_kill_vid, 2823 .ndo_set_vf_vlan = ionic_set_vf_vlan, 2824 .ndo_set_vf_trust = ionic_set_vf_trust, 2825 .ndo_set_vf_mac = ionic_set_vf_mac, 2826 .ndo_set_vf_rate = ionic_set_vf_rate, 2827 .ndo_set_vf_spoofchk = ionic_set_vf_spoofchk, 2828 .ndo_get_vf_config = ionic_get_vf_config, 2829 .ndo_set_vf_link_state = ionic_set_vf_link_state, 2830 .ndo_get_vf_stats = ionic_get_vf_stats, 2831 .ndo_hwtstamp_get = ionic_hwstamp_get, 2832 .ndo_hwtstamp_set = ionic_hwstamp_set, 2833 }; 2834 2835 static int ionic_cmb_reconfig(struct ionic_lif *lif, 2836 struct ionic_queue_params *qparam) 2837 { 2838 struct ionic_queue_params start_qparams; 2839 int err = 0; 2840 2841 /* When changing CMB queue parameters, we're using limited 2842 * on-device memory and don't have extra memory to use for 2843 * duplicate allocations, so we free it all first then 2844 * re-allocate with the new parameters. 2845 */ 2846 2847 /* Checkpoint for possible unwind */ 2848 ionic_init_queue_params(lif, &start_qparams); 2849 2850 /* Stop and free the queues */ 2851 ionic_stop_queues_reconfig(lif); 2852 ionic_txrx_free(lif); 2853 2854 /* Set up new qparams */ 2855 ionic_set_queue_params(lif, qparam); 2856 2857 if (netif_running(lif->netdev)) { 2858 /* Alloc and start the new configuration */ 2859 err = ionic_txrx_alloc(lif); 2860 if (err) { 2861 dev_warn(lif->ionic->dev, 2862 "CMB reconfig failed, restoring values: %d\n", err); 2863 2864 /* Back out the changes */ 2865 ionic_set_queue_params(lif, &start_qparams); 2866 err = ionic_txrx_alloc(lif); 2867 if (err) { 2868 dev_err(lif->ionic->dev, 2869 "CMB restore failed: %d\n", err); 2870 goto err_out; 2871 } 2872 } 2873 2874 err = ionic_start_queues_reconfig(lif); 2875 if (err) { 2876 dev_err(lif->ionic->dev, 2877 "CMB reconfig failed: %d\n", err); 2878 goto err_out; 2879 } 2880 } 2881 2882 err_out: 2883 /* This was detached in ionic_stop_queues_reconfig() */ 2884 netif_device_attach(lif->netdev); 2885 2886 return err; 2887 } 2888 2889 static void ionic_swap_queues(struct ionic_qcq *a, struct ionic_qcq *b) 2890 { 2891 /* only swapping the queues and napi, not flags or other stuff */ 2892 swap(a->napi, b->napi); 2893 2894 if (a->q.type == IONIC_QTYPE_RXQ) { 2895 swap(a->q.page_pool, b->q.page_pool); 2896 a->q.page_pool->p.napi = &a->napi; 2897 if (b->q.page_pool) /* is NULL when increasing queue count */ 2898 b->q.page_pool->p.napi = &b->napi; 2899 } 2900 2901 swap(a->q.features, b->q.features); 2902 swap(a->q.num_descs, b->q.num_descs); 2903 swap(a->q.desc_size, b->q.desc_size); 2904 swap(a->q.base, b->q.base); 2905 swap(a->q.base_pa, b->q.base_pa); 2906 swap(a->q.info, b->q.info); 2907 swap(a->q.xdp_prog, b->q.xdp_prog); 2908 swap(a->q.xdp_rxq_info, b->q.xdp_rxq_info); 2909 swap(a->q.partner, b->q.partner); 2910 swap(a->q_base, b->q_base); 2911 swap(a->q_base_pa, b->q_base_pa); 2912 swap(a->q_size, b->q_size); 2913 2914 swap(a->q.sg_desc_size, b->q.sg_desc_size); 2915 swap(a->q.sg_base, b->q.sg_base); 2916 swap(a->q.sg_base_pa, b->q.sg_base_pa); 2917 swap(a->sg_base, b->sg_base); 2918 swap(a->sg_base_pa, b->sg_base_pa); 2919 swap(a->sg_size, b->sg_size); 2920 2921 swap(a->cq.num_descs, b->cq.num_descs); 2922 swap(a->cq.desc_size, b->cq.desc_size); 2923 swap(a->cq.base, b->cq.base); 2924 swap(a->cq.base_pa, b->cq.base_pa); 2925 swap(a->cq_base, b->cq_base); 2926 swap(a->cq_base_pa, b->cq_base_pa); 2927 swap(a->cq_size, b->cq_size); 2928 2929 ionic_debugfs_del_qcq(a); 2930 ionic_debugfs_add_qcq(a->q.lif, a); 2931 } 2932 2933 int ionic_reconfigure_queues(struct ionic_lif *lif, 2934 struct ionic_queue_params *qparam) 2935 { 2936 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz; 2937 struct ionic_qcq **tx_qcqs = NULL; 2938 struct ionic_qcq **rx_qcqs = NULL; 2939 unsigned int flags, i; 2940 int err = 0; 2941 2942 /* Are we changing q params while CMB is on */ 2943 if ((test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state) && qparam->cmb_tx) || 2944 (test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state) && qparam->cmb_rx)) 2945 return ionic_cmb_reconfig(lif, qparam); 2946 2947 /* allocate temporary qcq arrays to hold new queue structs */ 2948 if (qparam->nxqs != lif->nxqs || qparam->ntxq_descs != lif->ntxq_descs) { 2949 tx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->ntxqs_per_lif, 2950 sizeof(struct ionic_qcq *), GFP_KERNEL); 2951 if (!tx_qcqs) { 2952 err = -ENOMEM; 2953 goto err_out; 2954 } 2955 } 2956 if (qparam->nxqs != lif->nxqs || 2957 qparam->nrxq_descs != lif->nrxq_descs || 2958 qparam->rxq_features != lif->rxq_features || 2959 qparam->xdp_prog != lif->xdp_prog) { 2960 rx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->nrxqs_per_lif, 2961 sizeof(struct ionic_qcq *), GFP_KERNEL); 2962 if (!rx_qcqs) { 2963 err = -ENOMEM; 2964 goto err_out; 2965 } 2966 } 2967 2968 /* allocate new desc_info and rings, but leave the interrupt setup 2969 * until later so as to not mess with the still-running queues 2970 */ 2971 if (tx_qcqs) { 2972 num_desc = qparam->ntxq_descs; 2973 desc_sz = sizeof(struct ionic_txq_desc); 2974 comp_sz = sizeof(struct ionic_txq_comp); 2975 2976 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 2977 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 2978 sizeof(struct ionic_txq_sg_desc_v1)) 2979 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 2980 else 2981 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 2982 2983 for (i = 0; i < qparam->nxqs; i++) { 2984 /* If missing, short placeholder qcq needed for swap */ 2985 if (!lif->txqcqs[i]) { 2986 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 2987 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 2988 4, desc_sz, comp_sz, sg_desc_sz, 2989 sizeof(struct ionic_tx_desc_info), 2990 lif->kern_pid, NULL, &lif->txqcqs[i]); 2991 if (err) 2992 goto err_out; 2993 } 2994 2995 flags = lif->txqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2996 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 2997 num_desc, desc_sz, comp_sz, sg_desc_sz, 2998 sizeof(struct ionic_tx_desc_info), 2999 lif->kern_pid, NULL, &tx_qcqs[i]); 3000 if (err) 3001 goto err_out; 3002 } 3003 } 3004 3005 if (rx_qcqs) { 3006 num_desc = qparam->nrxq_descs; 3007 desc_sz = sizeof(struct ionic_rxq_desc); 3008 comp_sz = sizeof(struct ionic_rxq_comp); 3009 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 3010 3011 if (qparam->rxq_features & IONIC_Q_F_2X_CQ_DESC) 3012 comp_sz *= 2; 3013 3014 for (i = 0; i < qparam->nxqs; i++) { 3015 /* If missing, short placeholder qcq needed for swap */ 3016 if (!lif->rxqcqs[i]) { 3017 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG; 3018 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 3019 4, desc_sz, comp_sz, sg_desc_sz, 3020 sizeof(struct ionic_rx_desc_info), 3021 lif->kern_pid, NULL, &lif->rxqcqs[i]); 3022 if (err) 3023 goto err_out; 3024 } 3025 3026 flags = lif->rxqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 3027 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 3028 num_desc, desc_sz, comp_sz, sg_desc_sz, 3029 sizeof(struct ionic_rx_desc_info), 3030 lif->kern_pid, qparam->xdp_prog, &rx_qcqs[i]); 3031 if (err) 3032 goto err_out; 3033 3034 rx_qcqs[i]->q.features = qparam->rxq_features; 3035 rx_qcqs[i]->q.xdp_prog = qparam->xdp_prog; 3036 } 3037 } 3038 3039 /* stop and clean the queues */ 3040 ionic_stop_queues_reconfig(lif); 3041 3042 if (qparam->nxqs != lif->nxqs) { 3043 err = netif_set_real_num_tx_queues(lif->netdev, qparam->nxqs); 3044 if (err) 3045 goto err_out_reinit_unlock; 3046 err = netif_set_real_num_rx_queues(lif->netdev, qparam->nxqs); 3047 if (err) { 3048 netif_set_real_num_tx_queues(lif->netdev, lif->nxqs); 3049 goto err_out_reinit_unlock; 3050 } 3051 } 3052 3053 /* swap new desc_info and rings, keeping existing interrupt config */ 3054 if (tx_qcqs) { 3055 lif->ntxq_descs = qparam->ntxq_descs; 3056 for (i = 0; i < qparam->nxqs; i++) 3057 ionic_swap_queues(lif->txqcqs[i], tx_qcqs[i]); 3058 } 3059 3060 if (rx_qcqs) { 3061 lif->nrxq_descs = qparam->nrxq_descs; 3062 for (i = 0; i < qparam->nxqs; i++) 3063 ionic_swap_queues(lif->rxqcqs[i], rx_qcqs[i]); 3064 } 3065 3066 /* if we need to change the interrupt layout, this is the time */ 3067 if (qparam->intr_split != test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) || 3068 qparam->nxqs != lif->nxqs) { 3069 if (qparam->intr_split) { 3070 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 3071 } else { 3072 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 3073 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 3074 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 3075 } 3076 3077 /* Clear existing interrupt assignments. We check for NULL here 3078 * because we're checking the whole array for potential qcqs, not 3079 * just those qcqs that have just been set up. 3080 */ 3081 for (i = 0; i < lif->ionic->ntxqs_per_lif; i++) { 3082 if (lif->txqcqs[i]) 3083 ionic_qcq_intr_free(lif, lif->txqcqs[i]); 3084 if (lif->rxqcqs[i]) 3085 ionic_qcq_intr_free(lif, lif->rxqcqs[i]); 3086 } 3087 3088 /* re-assign the interrupts */ 3089 for (i = 0; i < qparam->nxqs; i++) { 3090 lif->rxqcqs[i]->flags |= IONIC_QCQ_F_INTR; 3091 err = ionic_alloc_qcq_interrupt(lif, lif->rxqcqs[i]); 3092 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 3093 lif->rxqcqs[i]->intr.index, 3094 lif->rx_coalesce_hw); 3095 3096 if (qparam->intr_split) { 3097 lif->txqcqs[i]->flags |= IONIC_QCQ_F_INTR; 3098 err = ionic_alloc_qcq_interrupt(lif, lif->txqcqs[i]); 3099 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 3100 lif->txqcqs[i]->intr.index, 3101 lif->tx_coalesce_hw); 3102 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 3103 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 3104 } else { 3105 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 3106 ionic_link_qcq_interrupts(lif->rxqcqs[i], lif->txqcqs[i]); 3107 } 3108 } 3109 } 3110 3111 /* now we can rework the debugfs mappings */ 3112 if (tx_qcqs) { 3113 for (i = 0; i < qparam->nxqs; i++) { 3114 ionic_debugfs_del_qcq(lif->txqcqs[i]); 3115 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 3116 } 3117 } 3118 3119 if (rx_qcqs) { 3120 for (i = 0; i < qparam->nxqs; i++) { 3121 ionic_debugfs_del_qcq(lif->rxqcqs[i]); 3122 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 3123 } 3124 } 3125 3126 swap(lif->nxqs, qparam->nxqs); 3127 swap(lif->rxq_features, qparam->rxq_features); 3128 3129 err_out_reinit_unlock: 3130 /* re-init the queues, but don't lose an error code */ 3131 if (err) 3132 ionic_start_queues_reconfig(lif); 3133 else 3134 err = ionic_start_queues_reconfig(lif); 3135 3136 err_out: 3137 /* free old allocs without cleaning intr */ 3138 for (i = 0; i < qparam->nxqs; i++) { 3139 if (tx_qcqs && tx_qcqs[i]) { 3140 tx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 3141 ionic_qcq_free(lif, tx_qcqs[i]); 3142 devm_kfree(lif->ionic->dev, tx_qcqs[i]); 3143 tx_qcqs[i] = NULL; 3144 } 3145 if (rx_qcqs && rx_qcqs[i]) { 3146 rx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 3147 ionic_qcq_free(lif, rx_qcqs[i]); 3148 devm_kfree(lif->ionic->dev, rx_qcqs[i]); 3149 rx_qcqs[i] = NULL; 3150 } 3151 } 3152 3153 /* free q array */ 3154 if (rx_qcqs) { 3155 devm_kfree(lif->ionic->dev, rx_qcqs); 3156 rx_qcqs = NULL; 3157 } 3158 if (tx_qcqs) { 3159 devm_kfree(lif->ionic->dev, tx_qcqs); 3160 tx_qcqs = NULL; 3161 } 3162 3163 /* clean the unused dma and info allocations when new set is smaller 3164 * than the full array, but leave the qcq shells in place 3165 */ 3166 for (i = lif->nxqs; i < lif->ionic->ntxqs_per_lif; i++) { 3167 if (lif->txqcqs && lif->txqcqs[i]) { 3168 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 3169 ionic_qcq_free(lif, lif->txqcqs[i]); 3170 } 3171 3172 if (lif->rxqcqs && lif->rxqcqs[i]) { 3173 lif->rxqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 3174 ionic_qcq_free(lif, lif->rxqcqs[i]); 3175 } 3176 } 3177 3178 if (err) 3179 netdev_info(lif->netdev, "%s: failed %d\n", __func__, err); 3180 3181 return err; 3182 } 3183 3184 static int ionic_affinity_masks_alloc(struct ionic *ionic) 3185 { 3186 cpumask_var_t *affinity_masks; 3187 int nintrs = ionic->nintrs; 3188 int i; 3189 3190 affinity_masks = kzalloc_objs(cpumask_var_t, nintrs); 3191 if (!affinity_masks) 3192 return -ENOMEM; 3193 3194 for (i = 0; i < nintrs; i++) { 3195 if (!zalloc_cpumask_var_node(&affinity_masks[i], GFP_KERNEL, 3196 dev_to_node(ionic->dev))) 3197 goto err_out; 3198 } 3199 3200 ionic->affinity_masks = affinity_masks; 3201 3202 return 0; 3203 3204 err_out: 3205 for (--i; i >= 0; i--) 3206 free_cpumask_var(affinity_masks[i]); 3207 kfree(affinity_masks); 3208 3209 return -ENOMEM; 3210 } 3211 3212 static void ionic_affinity_masks_free(struct ionic *ionic) 3213 { 3214 int i; 3215 3216 for (i = 0; i < ionic->nintrs; i++) 3217 free_cpumask_var(ionic->affinity_masks[i]); 3218 kfree(ionic->affinity_masks); 3219 ionic->affinity_masks = NULL; 3220 } 3221 3222 int ionic_lif_alloc(struct ionic *ionic) 3223 { 3224 struct device *dev = ionic->dev; 3225 union ionic_lif_identity *lid; 3226 struct net_device *netdev; 3227 struct ionic_lif *lif; 3228 int tbl_sz; 3229 int err; 3230 3231 lid = kzalloc_obj(*lid); 3232 if (!lid) 3233 return -ENOMEM; 3234 3235 netdev = alloc_etherdev_mqs(sizeof(*lif), 3236 ionic->ntxqs_per_lif, ionic->ntxqs_per_lif); 3237 if (!netdev) { 3238 dev_err(dev, "Cannot allocate netdev, aborting\n"); 3239 err = -ENOMEM; 3240 goto err_out_free_lid; 3241 } 3242 3243 SET_NETDEV_DEV(netdev, dev); 3244 3245 lif = netdev_priv(netdev); 3246 lif->netdev = netdev; 3247 ionic->lif = lif; 3248 lif->ionic = ionic; 3249 netdev->netdev_ops = &ionic_netdev_ops; 3250 ionic_ethtool_set_ops(netdev); 3251 3252 netdev->watchdog_timeo = 5 * HZ; 3253 netif_carrier_off(netdev); 3254 3255 lif->identity = lid; 3256 lif->lif_type = IONIC_LIF_TYPE_CLASSIC; 3257 err = ionic_lif_identify(ionic, lif->lif_type, lif->identity); 3258 if (err) { 3259 dev_err(ionic->dev, "Cannot identify type %d: %d\n", 3260 lif->lif_type, err); 3261 goto err_out_free_netdev; 3262 } 3263 lif->netdev->min_mtu = max_t(unsigned int, ETH_MIN_MTU, 3264 le32_to_cpu(lif->identity->eth.min_frame_size)); 3265 lif->netdev->max_mtu = 3266 le32_to_cpu(lif->identity->eth.max_frame_size) - VLAN_ETH_HLEN; 3267 3268 lif->neqs = ionic->neqs_per_lif; 3269 lif->nxqs = ionic->ntxqs_per_lif; 3270 3271 lif->index = 0; 3272 3273 if (is_kdump_kernel()) { 3274 lif->ntxq_descs = IONIC_MIN_TXRX_DESC; 3275 lif->nrxq_descs = IONIC_MIN_TXRX_DESC; 3276 } else { 3277 lif->ntxq_descs = IONIC_DEF_TXRX_DESC; 3278 lif->nrxq_descs = IONIC_DEF_TXRX_DESC; 3279 } 3280 3281 /* Convert the default coalesce value to actual hw resolution */ 3282 lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT; 3283 lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic, 3284 lif->rx_coalesce_usecs); 3285 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 3286 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 3287 set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 3288 set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 3289 3290 snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index); 3291 3292 mutex_init(&lif->queue_lock); 3293 mutex_init(&lif->config_lock); 3294 mutex_init(&lif->adev_lock); 3295 3296 spin_lock_init(&lif->adminq_lock); 3297 3298 spin_lock_init(&lif->deferred.lock); 3299 INIT_LIST_HEAD(&lif->deferred.list); 3300 INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work); 3301 3302 /* allocate lif info */ 3303 lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE); 3304 lif->info = dma_alloc_coherent(dev, lif->info_sz, 3305 &lif->info_pa, GFP_KERNEL); 3306 if (!lif->info) { 3307 dev_err(dev, "Failed to allocate lif info, aborting\n"); 3308 err = -ENOMEM; 3309 goto err_out_free_mutex; 3310 } 3311 3312 ionic_debugfs_add_lif(lif); 3313 3314 err = ionic_affinity_masks_alloc(ionic); 3315 if (err) 3316 goto err_out_free_lif_info; 3317 3318 /* allocate control queues and txrx queue arrays */ 3319 ionic_lif_queue_identify(lif); 3320 err = ionic_qcqs_alloc(lif); 3321 if (err) 3322 goto err_out_free_affinity_masks; 3323 3324 /* allocate rss indirection table */ 3325 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 3326 lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz; 3327 lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz, 3328 &lif->rss_ind_tbl_pa, 3329 GFP_KERNEL); 3330 3331 if (!lif->rss_ind_tbl) { 3332 err = -ENOMEM; 3333 dev_err(dev, "Failed to allocate rss indirection table, aborting\n"); 3334 goto err_out_free_qcqs; 3335 } 3336 netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE); 3337 3338 ionic_lif_alloc_phc(lif); 3339 3340 return 0; 3341 3342 err_out_free_qcqs: 3343 ionic_qcqs_free(lif); 3344 err_out_free_affinity_masks: 3345 ionic_affinity_masks_free(lif->ionic); 3346 err_out_free_lif_info: 3347 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 3348 lif->info = NULL; 3349 lif->info_pa = 0; 3350 err_out_free_mutex: 3351 mutex_destroy(&lif->adev_lock); 3352 mutex_destroy(&lif->config_lock); 3353 mutex_destroy(&lif->queue_lock); 3354 err_out_free_netdev: 3355 free_netdev(lif->netdev); 3356 lif = NULL; 3357 err_out_free_lid: 3358 kfree(lid); 3359 3360 return err; 3361 } 3362 3363 static void ionic_lif_reset(struct ionic_lif *lif) 3364 { 3365 struct ionic_dev *idev = &lif->ionic->idev; 3366 3367 if (!ionic_is_fw_running(idev)) 3368 return; 3369 3370 mutex_lock(&lif->ionic->dev_cmd_lock); 3371 ionic_dev_cmd_lif_reset(idev, lif->index); 3372 ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 3373 mutex_unlock(&lif->ionic->dev_cmd_lock); 3374 } 3375 3376 static void ionic_lif_handle_fw_down(struct ionic_lif *lif) 3377 { 3378 struct ionic *ionic = lif->ionic; 3379 3380 if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state)) 3381 return; 3382 3383 dev_info(ionic->dev, "FW Down: Stopping LIFs\n"); 3384 3385 netif_device_detach(lif->netdev); 3386 3387 ionic_auxbus_unregister(ionic->lif); 3388 mutex_lock(&lif->queue_lock); 3389 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 3390 dev_info(ionic->dev, "Surprise FW stop, stopping queues\n"); 3391 ionic_stop_queues(lif); 3392 } 3393 3394 if (netif_running(lif->netdev)) { 3395 ionic_txrx_deinit(lif); 3396 ionic_txrx_free(lif); 3397 } 3398 ionic_lif_deinit(lif); 3399 ionic_reset(ionic); 3400 ionic_qcqs_free(lif); 3401 3402 mutex_unlock(&lif->queue_lock); 3403 3404 clear_bit(IONIC_LIF_F_FW_STOPPING, lif->state); 3405 dev_info(ionic->dev, "FW Down: LIFs stopped\n"); 3406 } 3407 3408 int ionic_restart_lif(struct ionic_lif *lif) 3409 { 3410 struct ionic *ionic = lif->ionic; 3411 int err; 3412 3413 mutex_lock(&lif->queue_lock); 3414 3415 if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state)) 3416 dev_info(ionic->dev, "FW Up: clearing broken state\n"); 3417 3418 err = ionic_qcqs_alloc(lif); 3419 if (err) 3420 goto err_unlock; 3421 3422 err = ionic_lif_init(lif); 3423 if (err) 3424 goto err_qcqs_free; 3425 3426 ionic_vf_attr_replay(lif); 3427 3428 if (lif->registered) 3429 ionic_lif_set_netdev_info(lif); 3430 3431 ionic_rx_filter_replay(lif); 3432 3433 if (netif_running(lif->netdev)) { 3434 err = ionic_txrx_alloc(lif); 3435 if (err) 3436 goto err_lifs_deinit; 3437 3438 err = ionic_txrx_init(lif); 3439 if (err) 3440 goto err_txrx_free; 3441 } 3442 3443 mutex_unlock(&lif->queue_lock); 3444 3445 clear_bit(IONIC_LIF_F_FW_RESET, lif->state); 3446 ionic_link_status_check_request(lif, CAN_SLEEP); 3447 netif_device_attach(lif->netdev); 3448 ionic_queue_doorbell_check(ionic, IONIC_NAPI_DEADLINE); 3449 3450 ionic_auxbus_register(ionic->lif); 3451 3452 return 0; 3453 3454 err_txrx_free: 3455 ionic_txrx_free(lif); 3456 err_lifs_deinit: 3457 ionic_lif_deinit(lif); 3458 err_qcqs_free: 3459 ionic_qcqs_free(lif); 3460 err_unlock: 3461 mutex_unlock(&lif->queue_lock); 3462 3463 return err; 3464 } 3465 3466 static void ionic_lif_handle_fw_up(struct ionic_lif *lif) 3467 { 3468 struct ionic *ionic = lif->ionic; 3469 int err; 3470 3471 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 3472 return; 3473 3474 dev_info(ionic->dev, "FW Up: restarting LIFs\n"); 3475 3476 /* This is a little different from what happens at 3477 * probe time because the LIF already exists so we 3478 * just need to reanimate it. 3479 */ 3480 ionic_init_devinfo(ionic); 3481 ionic_reset(ionic); 3482 err = ionic_identify(ionic); 3483 if (err) 3484 goto err_out; 3485 err = ionic_port_identify(ionic); 3486 if (err) 3487 goto err_out; 3488 err = ionic_port_init(ionic); 3489 if (err) 3490 goto err_out; 3491 3492 err = ionic_restart_lif(lif); 3493 if (err) 3494 goto err_out; 3495 3496 dev_info(ionic->dev, "FW Up: LIFs restarted\n"); 3497 3498 /* restore the hardware timestamping queues */ 3499 ionic_lif_hwstamp_replay(lif); 3500 3501 return; 3502 3503 err_out: 3504 dev_err(ionic->dev, "FW Up: LIFs restart failed - err %d\n", err); 3505 } 3506 3507 void ionic_lif_free(struct ionic_lif *lif) 3508 { 3509 struct device *dev = lif->ionic->dev; 3510 3511 ionic_lif_free_phc(lif); 3512 3513 /* free rss indirection table */ 3514 dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl, 3515 lif->rss_ind_tbl_pa); 3516 lif->rss_ind_tbl = NULL; 3517 lif->rss_ind_tbl_pa = 0; 3518 3519 /* free queues */ 3520 ionic_qcqs_free(lif); 3521 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 3522 ionic_lif_reset(lif); 3523 3524 ionic_affinity_masks_free(lif->ionic); 3525 3526 /* free lif info */ 3527 kfree(lif->identity); 3528 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 3529 lif->info = NULL; 3530 lif->info_pa = 0; 3531 3532 mutex_destroy(&lif->config_lock); 3533 mutex_destroy(&lif->queue_lock); 3534 mutex_destroy(&lif->adev_lock); 3535 3536 /* free netdev & lif */ 3537 ionic_debugfs_del_lif(lif); 3538 free_netdev(lif->netdev); 3539 } 3540 3541 void ionic_lif_deinit(struct ionic_lif *lif) 3542 { 3543 if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state)) 3544 return; 3545 3546 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 3547 cancel_work_sync(&lif->deferred.work); 3548 cancel_work_sync(&lif->tx_timeout_work); 3549 ionic_rx_filters_deinit(lif); 3550 if (lif->netdev->features & NETIF_F_RXHASH) 3551 ionic_lif_rss_deinit(lif); 3552 } 3553 3554 napi_disable(&lif->adminqcq->napi); 3555 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 3556 ionic_lif_qcq_deinit(lif, lif->adminqcq); 3557 3558 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 3559 lif->kern_dbpage = NULL; 3560 3561 ionic_lif_reset(lif); 3562 } 3563 3564 static int ionic_lif_adminq_init(struct ionic_lif *lif) 3565 { 3566 struct device *dev = lif->ionic->dev; 3567 struct ionic_q_init_comp comp; 3568 struct ionic_dev *idev; 3569 struct ionic_qcq *qcq; 3570 struct ionic_queue *q; 3571 int err; 3572 3573 idev = &lif->ionic->idev; 3574 qcq = lif->adminqcq; 3575 q = &qcq->q; 3576 3577 mutex_lock(&lif->ionic->dev_cmd_lock); 3578 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index); 3579 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 3580 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 3581 mutex_unlock(&lif->ionic->dev_cmd_lock); 3582 if (err) { 3583 netdev_err(lif->netdev, "adminq init failed %d\n", err); 3584 return err; 3585 } 3586 3587 q->hw_type = comp.hw_type; 3588 q->hw_index = le32_to_cpu(comp.hw_index); 3589 q->dbval = IONIC_DBELL_QID(q->hw_index); 3590 3591 dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type); 3592 dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index); 3593 3594 q->dbell_deadline = IONIC_ADMIN_DOORBELL_DEADLINE; 3595 q->dbell_jiffies = jiffies; 3596 3597 netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi); 3598 3599 napi_enable(&qcq->napi); 3600 3601 if (qcq->flags & IONIC_QCQ_F_INTR) { 3602 irq_set_affinity_hint(qcq->intr.vector, 3603 *qcq->intr.affinity_mask); 3604 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 3605 IONIC_INTR_MASK_CLEAR); 3606 } 3607 3608 qcq->flags |= IONIC_QCQ_F_INITED; 3609 3610 return 0; 3611 } 3612 3613 static int ionic_lif_notifyq_init(struct ionic_lif *lif) 3614 { 3615 struct ionic_qcq *qcq = lif->notifyqcq; 3616 struct device *dev = lif->ionic->dev; 3617 struct ionic_queue *q = &qcq->q; 3618 int err; 3619 3620 struct ionic_admin_ctx ctx = { 3621 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3622 .cmd.q_init = { 3623 .opcode = IONIC_CMD_Q_INIT, 3624 .lif_index = cpu_to_le16(lif->index), 3625 .type = q->type, 3626 .ver = lif->qtype_info[q->type].version, 3627 .index = cpu_to_le32(q->index), 3628 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 3629 IONIC_QINIT_F_ENA), 3630 .intr_index = cpu_to_le16(lif->adminqcq->intr.index), 3631 .pid = cpu_to_le16(q->pid), 3632 .ring_size = ilog2(q->num_descs), 3633 .ring_base = cpu_to_le64(q->base_pa), 3634 } 3635 }; 3636 3637 dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid); 3638 dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index); 3639 dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 3640 dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 3641 3642 err = ionic_adminq_post_wait(lif, &ctx); 3643 if (err) 3644 return err; 3645 3646 lif->last_eid = 0; 3647 q->hw_type = ctx.comp.q_init.hw_type; 3648 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 3649 q->dbval = IONIC_DBELL_QID(q->hw_index); 3650 3651 dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type); 3652 dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index); 3653 3654 /* preset the callback info */ 3655 q->admin_info[0].ctx = lif; 3656 3657 qcq->flags |= IONIC_QCQ_F_INITED; 3658 3659 return 0; 3660 } 3661 3662 static int ionic_station_set(struct ionic_lif *lif) 3663 { 3664 struct net_device *netdev = lif->netdev; 3665 struct ionic_admin_ctx ctx = { 3666 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3667 .cmd.lif_getattr = { 3668 .opcode = IONIC_CMD_LIF_GETATTR, 3669 .index = cpu_to_le16(lif->index), 3670 .attr = IONIC_LIF_ATTR_MAC, 3671 }, 3672 }; 3673 u8 mac_address[ETH_ALEN]; 3674 struct sockaddr addr; 3675 int err; 3676 3677 err = ionic_adminq_post_wait(lif, &ctx); 3678 if (err) 3679 return err; 3680 netdev_dbg(lif->netdev, "found initial MAC addr %pM\n", 3681 ctx.comp.lif_getattr.mac); 3682 ether_addr_copy(mac_address, ctx.comp.lif_getattr.mac); 3683 3684 if (is_zero_ether_addr(mac_address)) { 3685 eth_hw_addr_random(netdev); 3686 netdev_dbg(netdev, "Random Mac generated: %pM\n", netdev->dev_addr); 3687 ether_addr_copy(mac_address, netdev->dev_addr); 3688 3689 err = ionic_program_mac(lif, mac_address); 3690 if (err < 0) 3691 return err; 3692 3693 if (err > 0) { 3694 netdev_dbg(netdev, "%s:SET/GET ATTR Mac are not same-due to old FW running\n", 3695 __func__); 3696 return 0; 3697 } 3698 } 3699 3700 if (!is_zero_ether_addr(netdev->dev_addr)) { 3701 /* If the netdev mac is non-zero and doesn't match the default 3702 * device address, it was set by something earlier and we're 3703 * likely here again after a fw-upgrade reset. We need to be 3704 * sure the netdev mac is in our filter list. 3705 */ 3706 if (!ether_addr_equal(mac_address, netdev->dev_addr)) 3707 ionic_lif_addr_add(lif, netdev->dev_addr); 3708 } else { 3709 /* Update the netdev mac with the device's mac */ 3710 ether_addr_copy(addr.sa_data, mac_address); 3711 addr.sa_family = AF_INET; 3712 err = eth_prepare_mac_addr_change(netdev, &addr); 3713 if (err) { 3714 netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n", 3715 addr.sa_data, err); 3716 return 0; 3717 } 3718 3719 eth_commit_mac_addr_change(netdev, &addr); 3720 } 3721 3722 netdev_dbg(lif->netdev, "adding station MAC addr %pM\n", 3723 netdev->dev_addr); 3724 ionic_lif_addr_add(lif, netdev->dev_addr); 3725 3726 return 0; 3727 } 3728 3729 int ionic_lif_init(struct ionic_lif *lif) 3730 { 3731 struct ionic_dev *idev = &lif->ionic->idev; 3732 struct device *dev = lif->ionic->dev; 3733 struct ionic_lif_init_comp comp; 3734 int dbpage_num; 3735 int err; 3736 3737 mutex_lock(&lif->ionic->dev_cmd_lock); 3738 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa); 3739 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 3740 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 3741 mutex_unlock(&lif->ionic->dev_cmd_lock); 3742 if (err) 3743 return err; 3744 3745 lif->hw_index = le16_to_cpu(comp.hw_index); 3746 3747 /* now that we have the hw_index we can figure out our doorbell page */ 3748 lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif); 3749 if (!lif->dbid_count) { 3750 dev_err(dev, "No doorbell pages, aborting\n"); 3751 return -EINVAL; 3752 } 3753 3754 lif->kern_pid = 0; 3755 dbpage_num = ionic_db_page_num(lif, lif->kern_pid); 3756 lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num); 3757 if (!lif->kern_dbpage) { 3758 dev_err(dev, "Cannot map dbpage, aborting\n"); 3759 return -ENOMEM; 3760 } 3761 3762 err = ionic_lif_adminq_init(lif); 3763 if (err) 3764 goto err_out_adminq_deinit; 3765 3766 if (lif->ionic->nnqs_per_lif) { 3767 err = ionic_lif_notifyq_init(lif); 3768 if (err) 3769 goto err_out_notifyq_deinit; 3770 } 3771 3772 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 3773 err = ionic_set_nic_features(lif, lif->netdev->features); 3774 else 3775 err = ionic_init_nic_features(lif); 3776 if (err) 3777 goto err_out_notifyq_deinit; 3778 3779 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 3780 err = ionic_rx_filters_init(lif); 3781 if (err) 3782 goto err_out_notifyq_deinit; 3783 } 3784 3785 err = ionic_station_set(lif); 3786 if (err) 3787 goto err_out_notifyq_deinit; 3788 3789 lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT; 3790 lif->doorbell_wa = ionic_doorbell_wa(lif->ionic); 3791 3792 set_bit(IONIC_LIF_F_INITED, lif->state); 3793 3794 INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work); 3795 3796 return 0; 3797 3798 err_out_notifyq_deinit: 3799 napi_disable(&lif->adminqcq->napi); 3800 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 3801 err_out_adminq_deinit: 3802 ionic_lif_qcq_deinit(lif, lif->adminqcq); 3803 ionic_lif_reset(lif); 3804 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 3805 lif->kern_dbpage = NULL; 3806 3807 return err; 3808 } 3809 3810 static void ionic_lif_set_netdev_info(struct ionic_lif *lif) 3811 { 3812 struct ionic_admin_ctx ctx = { 3813 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3814 .cmd.lif_setattr = { 3815 .opcode = IONIC_CMD_LIF_SETATTR, 3816 .index = cpu_to_le16(lif->index), 3817 .attr = IONIC_LIF_ATTR_NAME, 3818 }, 3819 }; 3820 3821 strscpy(ctx.cmd.lif_setattr.name, netdev_name(lif->netdev), 3822 sizeof(ctx.cmd.lif_setattr.name)); 3823 3824 ionic_adminq_post_wait(lif, &ctx); 3825 } 3826 3827 static struct ionic_lif *ionic_netdev_lif(struct net_device *netdev) 3828 { 3829 if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit) 3830 return NULL; 3831 3832 return netdev_priv(netdev); 3833 } 3834 3835 static int ionic_lif_notify(struct notifier_block *nb, 3836 unsigned long event, void *info) 3837 { 3838 struct net_device *ndev = netdev_notifier_info_to_dev(info); 3839 struct ionic *ionic = container_of(nb, struct ionic, nb); 3840 struct ionic_lif *lif = ionic_netdev_lif(ndev); 3841 3842 if (!lif || lif->ionic != ionic) 3843 return NOTIFY_DONE; 3844 3845 switch (event) { 3846 case NETDEV_CHANGENAME: 3847 ionic_lif_set_netdev_info(lif); 3848 break; 3849 } 3850 3851 return NOTIFY_DONE; 3852 } 3853 3854 int ionic_lif_register(struct ionic_lif *lif) 3855 { 3856 int err; 3857 3858 ionic_lif_register_phc(lif); 3859 3860 lif->ionic->nb.notifier_call = ionic_lif_notify; 3861 3862 err = register_netdevice_notifier(&lif->ionic->nb); 3863 if (err) 3864 lif->ionic->nb.notifier_call = NULL; 3865 3866 /* only register LIF0 for now */ 3867 err = register_netdev(lif->netdev); 3868 if (err) { 3869 dev_err(lif->ionic->dev, "Cannot register net device: %d, aborting\n", err); 3870 ionic_lif_unregister(lif); 3871 return err; 3872 } 3873 3874 ionic_link_status_check_request(lif, CAN_SLEEP); 3875 lif->registered = true; 3876 ionic_lif_set_netdev_info(lif); 3877 3878 return 0; 3879 } 3880 3881 void ionic_lif_unregister(struct ionic_lif *lif) 3882 { 3883 if (lif->ionic->nb.notifier_call) { 3884 unregister_netdevice_notifier(&lif->ionic->nb); 3885 lif->ionic->nb.notifier_call = NULL; 3886 } 3887 3888 if (lif->netdev->reg_state == NETREG_REGISTERED) 3889 unregister_netdev(lif->netdev); 3890 3891 ionic_lif_unregister_phc(lif); 3892 3893 lif->registered = false; 3894 } 3895 3896 static void ionic_lif_queue_identify(struct ionic_lif *lif) 3897 { 3898 union ionic_q_identity __iomem *q_ident; 3899 struct ionic *ionic = lif->ionic; 3900 struct ionic_dev *idev; 3901 u16 max_frags; 3902 int qtype; 3903 int err; 3904 3905 idev = &lif->ionic->idev; 3906 q_ident = (union ionic_q_identity __iomem *)&idev->dev_cmd_regs->data; 3907 3908 for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) { 3909 struct ionic_qtype_info *qti = &lif->qtype_info[qtype]; 3910 3911 /* filter out the ones we know about */ 3912 switch (qtype) { 3913 case IONIC_QTYPE_ADMINQ: 3914 case IONIC_QTYPE_NOTIFYQ: 3915 case IONIC_QTYPE_RXQ: 3916 case IONIC_QTYPE_TXQ: 3917 break; 3918 default: 3919 continue; 3920 } 3921 3922 memset(qti, 0, sizeof(*qti)); 3923 3924 mutex_lock(&ionic->dev_cmd_lock); 3925 ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype, 3926 ionic_qtype_versions[qtype]); 3927 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3928 if (!err) { 3929 qti->version = readb(&q_ident->version); 3930 qti->supported = readb(&q_ident->supported); 3931 qti->features = readq(&q_ident->features); 3932 qti->desc_sz = readw(&q_ident->desc_sz); 3933 qti->comp_sz = readw(&q_ident->comp_sz); 3934 qti->sg_desc_sz = readw(&q_ident->sg_desc_sz); 3935 qti->max_sg_elems = readw(&q_ident->max_sg_elems); 3936 qti->sg_desc_stride = readw(&q_ident->sg_desc_stride); 3937 } 3938 mutex_unlock(&ionic->dev_cmd_lock); 3939 3940 if (err == -EINVAL) { 3941 dev_err(ionic->dev, "qtype %d not supported\n", qtype); 3942 continue; 3943 } else if (err == -EIO) { 3944 dev_err(ionic->dev, "q_ident failed, not supported on older FW\n"); 3945 return; 3946 } else if (err) { 3947 dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n", 3948 qtype, err); 3949 return; 3950 } 3951 3952 dev_dbg(ionic->dev, " qtype[%d].version = %d\n", 3953 qtype, qti->version); 3954 dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n", 3955 qtype, qti->supported); 3956 dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n", 3957 qtype, qti->features); 3958 dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n", 3959 qtype, qti->desc_sz); 3960 dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n", 3961 qtype, qti->comp_sz); 3962 dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n", 3963 qtype, qti->sg_desc_sz); 3964 dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n", 3965 qtype, qti->max_sg_elems); 3966 dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n", 3967 qtype, qti->sg_desc_stride); 3968 3969 if (qtype == IONIC_QTYPE_TXQ) 3970 max_frags = IONIC_TX_MAX_FRAGS; 3971 else if (qtype == IONIC_QTYPE_RXQ) 3972 max_frags = IONIC_RX_MAX_FRAGS; 3973 else 3974 max_frags = 1; 3975 3976 qti->max_sg_elems = min_t(u16, max_frags - 1, MAX_SKB_FRAGS); 3977 dev_dbg(ionic->dev, "qtype %d max_sg_elems %d\n", 3978 qtype, qti->max_sg_elems); 3979 } 3980 } 3981 3982 int ionic_lif_identify(struct ionic *ionic, u8 lif_type, 3983 union ionic_lif_identity *lid) 3984 { 3985 struct ionic_dev *idev = &ionic->idev; 3986 size_t sz; 3987 int err; 3988 3989 sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data)); 3990 3991 mutex_lock(&ionic->dev_cmd_lock); 3992 ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1); 3993 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3994 memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz); 3995 mutex_unlock(&ionic->dev_cmd_lock); 3996 if (err) 3997 return (err); 3998 3999 dev_dbg(ionic->dev, "capabilities 0x%llx\n", 4000 le64_to_cpu(lid->capabilities)); 4001 4002 dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n", 4003 le32_to_cpu(lid->eth.max_ucast_filters)); 4004 dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n", 4005 le32_to_cpu(lid->eth.max_mcast_filters)); 4006 dev_dbg(ionic->dev, "eth.features 0x%llx\n", 4007 le64_to_cpu(lid->eth.config.features)); 4008 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n", 4009 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ])); 4010 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n", 4011 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ])); 4012 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n", 4013 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ])); 4014 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n", 4015 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ])); 4016 dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name); 4017 dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac); 4018 dev_dbg(ionic->dev, "eth.config.mtu %d\n", 4019 le32_to_cpu(lid->eth.config.mtu)); 4020 4021 return 0; 4022 } 4023 4024 int ionic_lif_size(struct ionic *ionic) 4025 { 4026 struct ionic_identity *ident = &ionic->ident; 4027 unsigned int nintrs, dev_nintrs; 4028 union ionic_lif_config *lc; 4029 unsigned int ntxqs_per_lif; 4030 unsigned int nrxqs_per_lif; 4031 unsigned int neqs_per_lif; 4032 unsigned int nnqs_per_lif; 4033 unsigned int nxqs, neqs; 4034 unsigned int min_intrs; 4035 int err; 4036 4037 /* retrieve basic values from FW */ 4038 lc = &ident->lif.eth.config; 4039 dev_nintrs = le32_to_cpu(ident->dev.nintrs); 4040 neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count); 4041 nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]); 4042 ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]); 4043 nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]); 4044 4045 /* limit values to play nice with kdump */ 4046 if (is_kdump_kernel()) { 4047 dev_nintrs = 2; 4048 neqs_per_lif = 0; 4049 nnqs_per_lif = 0; 4050 ntxqs_per_lif = 1; 4051 nrxqs_per_lif = 1; 4052 } 4053 4054 /* reserve last queue id for hardware timestamping */ 4055 if (lc->features & cpu_to_le64(IONIC_ETH_HW_TIMESTAMP)) { 4056 if (ntxqs_per_lif <= 1 || nrxqs_per_lif <= 1) { 4057 lc->features &= cpu_to_le64(~IONIC_ETH_HW_TIMESTAMP); 4058 } else { 4059 ntxqs_per_lif -= 1; 4060 nrxqs_per_lif -= 1; 4061 } 4062 } 4063 4064 nxqs = min(ntxqs_per_lif, nrxqs_per_lif); 4065 nxqs = min(nxqs, num_online_cpus()); 4066 neqs = min(neqs_per_lif, num_online_cpus()); 4067 4068 try_again: 4069 /* interrupt usage: 4070 * 1 for master lif adminq/notifyq 4071 * 1 for each CPU for master lif TxRx queue pairs 4072 * whatever's left is for RDMA queues 4073 */ 4074 nintrs = 1 + nxqs + neqs; 4075 min_intrs = 2; /* adminq + 1 TxRx queue pair */ 4076 4077 if (nintrs > dev_nintrs) 4078 goto try_fewer; 4079 4080 err = ionic_bus_alloc_irq_vectors(ionic, nintrs); 4081 if (err < 0 && err != -ENOSPC) { 4082 dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err); 4083 return err; 4084 } 4085 if (err == -ENOSPC) 4086 goto try_fewer; 4087 4088 if (err != nintrs) { 4089 ionic_bus_free_irq_vectors(ionic); 4090 goto try_fewer; 4091 } 4092 4093 ionic->nnqs_per_lif = nnqs_per_lif; 4094 ionic->neqs_per_lif = neqs; 4095 ionic->ntxqs_per_lif = nxqs; 4096 ionic->nrxqs_per_lif = nxqs; 4097 ionic->nintrs = nintrs; 4098 4099 ionic_debugfs_add_sizes(ionic); 4100 4101 return 0; 4102 4103 try_fewer: 4104 if (nnqs_per_lif > 1) { 4105 nnqs_per_lif >>= 1; 4106 goto try_again; 4107 } 4108 if (neqs > 1) { 4109 neqs >>= 1; 4110 goto try_again; 4111 } 4112 if (nxqs > 1) { 4113 nxqs >>= 1; 4114 goto try_again; 4115 } 4116 dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs); 4117 return -ENOSPC; 4118 } 4119