1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/ethtool.h> 5 #include <linux/printk.h> 6 #include <linux/dynamic_debug.h> 7 #include <linux/netdevice.h> 8 #include <linux/etherdevice.h> 9 #include <linux/if_vlan.h> 10 #include <linux/rtnetlink.h> 11 #include <linux/interrupt.h> 12 #include <linux/pci.h> 13 #include <linux/cpumask.h> 14 #include <linux/crash_dump.h> 15 #include <linux/vmalloc.h> 16 17 #include "ionic.h" 18 #include "ionic_bus.h" 19 #include "ionic_dev.h" 20 #include "ionic_lif.h" 21 #include "ionic_txrx.h" 22 #include "ionic_ethtool.h" 23 #include "ionic_debugfs.h" 24 25 /* queuetype support level */ 26 static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = { 27 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */ 28 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */ 29 [IONIC_QTYPE_RXQ] = 2, /* 0 = Base version with CQ+SG support 30 * 2 = ... with CMB rings 31 */ 32 [IONIC_QTYPE_TXQ] = 3, /* 0 = Base version with CQ+SG support 33 * 1 = ... with Tx SG version 1 34 * 3 = ... with CMB rings 35 */ 36 }; 37 38 static void ionic_link_status_check(struct ionic_lif *lif); 39 static void ionic_lif_handle_fw_down(struct ionic_lif *lif); 40 static void ionic_lif_handle_fw_up(struct ionic_lif *lif); 41 static void ionic_lif_set_netdev_info(struct ionic_lif *lif); 42 43 static void ionic_txrx_deinit(struct ionic_lif *lif); 44 static int ionic_txrx_init(struct ionic_lif *lif); 45 static int ionic_start_queues(struct ionic_lif *lif); 46 static void ionic_stop_queues(struct ionic_lif *lif); 47 static void ionic_lif_queue_identify(struct ionic_lif *lif); 48 49 static int ionic_xdp_queues_config(struct ionic_lif *lif); 50 static void ionic_xdp_unregister_rxq_info(struct ionic_queue *q); 51 52 static void ionic_dim_work(struct work_struct *work) 53 { 54 struct dim *dim = container_of(work, struct dim, work); 55 struct dim_cq_moder cur_moder; 56 struct ionic_intr_info *intr; 57 struct ionic_qcq *qcq; 58 struct ionic_lif *lif; 59 struct ionic_queue *q; 60 u32 new_coal; 61 62 qcq = container_of(dim, struct ionic_qcq, dim); 63 q = &qcq->q; 64 if (q->type == IONIC_QTYPE_RXQ) 65 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 66 else 67 cur_moder = net_dim_get_tx_moderation(dim->mode, dim->profile_ix); 68 lif = q->lif; 69 new_coal = ionic_coal_usec_to_hw(lif->ionic, cur_moder.usec); 70 new_coal = new_coal ? new_coal : 1; 71 72 intr = &qcq->intr; 73 if (intr->dim_coal_hw != new_coal) { 74 intr->dim_coal_hw = new_coal; 75 76 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 77 intr->index, intr->dim_coal_hw); 78 } 79 80 dim->state = DIM_START_MEASURE; 81 } 82 83 static void ionic_lif_deferred_work(struct work_struct *work) 84 { 85 struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work); 86 struct ionic_deferred *def = &lif->deferred; 87 struct ionic_deferred_work *w = NULL; 88 89 do { 90 spin_lock_bh(&def->lock); 91 if (!list_empty(&def->list)) { 92 w = list_first_entry(&def->list, 93 struct ionic_deferred_work, list); 94 list_del(&w->list); 95 } 96 spin_unlock_bh(&def->lock); 97 98 if (!w) 99 break; 100 101 switch (w->type) { 102 case IONIC_DW_TYPE_RX_MODE: 103 ionic_lif_rx_mode(lif); 104 break; 105 case IONIC_DW_TYPE_LINK_STATUS: 106 ionic_link_status_check(lif); 107 break; 108 case IONIC_DW_TYPE_LIF_RESET: 109 if (w->fw_status) { 110 ionic_lif_handle_fw_up(lif); 111 } else { 112 ionic_lif_handle_fw_down(lif); 113 114 /* Fire off another watchdog to see 115 * if the FW is already back rather than 116 * waiting another whole cycle 117 */ 118 mod_timer(&lif->ionic->watchdog_timer, jiffies + 1); 119 } 120 break; 121 default: 122 break; 123 } 124 kfree(w); 125 w = NULL; 126 } while (true); 127 } 128 129 void ionic_lif_deferred_enqueue(struct ionic_deferred *def, 130 struct ionic_deferred_work *work) 131 { 132 spin_lock_bh(&def->lock); 133 list_add_tail(&work->list, &def->list); 134 spin_unlock_bh(&def->lock); 135 schedule_work(&def->work); 136 } 137 138 static void ionic_link_status_check(struct ionic_lif *lif) 139 { 140 struct net_device *netdev = lif->netdev; 141 u16 link_status; 142 bool link_up; 143 144 if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 145 return; 146 147 /* Don't put carrier back up if we're in a broken state */ 148 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) { 149 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 150 return; 151 } 152 153 link_status = le16_to_cpu(lif->info->status.link_status); 154 link_up = link_status == IONIC_PORT_OPER_STATUS_UP; 155 156 if (link_up) { 157 int err = 0; 158 159 if (netdev->flags & IFF_UP && netif_running(netdev)) { 160 mutex_lock(&lif->queue_lock); 161 err = ionic_start_queues(lif); 162 if (err && err != -EBUSY) { 163 netdev_err(netdev, 164 "Failed to start queues: %d\n", err); 165 set_bit(IONIC_LIF_F_BROKEN, lif->state); 166 netif_carrier_off(lif->netdev); 167 } 168 mutex_unlock(&lif->queue_lock); 169 } 170 171 if (!err && !netif_carrier_ok(netdev)) { 172 ionic_port_identify(lif->ionic); 173 netdev_info(netdev, "Link up - %d Gbps\n", 174 le32_to_cpu(lif->info->status.link_speed) / 1000); 175 netif_carrier_on(netdev); 176 } 177 } else { 178 if (netif_carrier_ok(netdev)) { 179 lif->link_down_count++; 180 netdev_info(netdev, "Link down\n"); 181 netif_carrier_off(netdev); 182 } 183 184 if (netdev->flags & IFF_UP && netif_running(netdev)) { 185 mutex_lock(&lif->queue_lock); 186 ionic_stop_queues(lif); 187 mutex_unlock(&lif->queue_lock); 188 } 189 } 190 191 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 192 } 193 194 void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep) 195 { 196 struct ionic_deferred_work *work; 197 198 /* we only need one request outstanding at a time */ 199 if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 200 return; 201 202 if (!can_sleep) { 203 work = kzalloc(sizeof(*work), GFP_ATOMIC); 204 if (!work) { 205 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 206 return; 207 } 208 209 work->type = IONIC_DW_TYPE_LINK_STATUS; 210 ionic_lif_deferred_enqueue(&lif->deferred, work); 211 } else { 212 ionic_link_status_check(lif); 213 } 214 } 215 216 static void ionic_napi_deadline(struct timer_list *timer) 217 { 218 struct ionic_qcq *qcq = container_of(timer, struct ionic_qcq, napi_deadline); 219 220 napi_schedule(&qcq->napi); 221 } 222 223 static irqreturn_t ionic_isr(int irq, void *data) 224 { 225 struct napi_struct *napi = data; 226 227 napi_schedule_irqoff(napi); 228 229 return IRQ_HANDLED; 230 } 231 232 static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq) 233 { 234 struct ionic_intr_info *intr = &qcq->intr; 235 struct device *dev = lif->ionic->dev; 236 struct ionic_queue *q = &qcq->q; 237 const char *name; 238 239 if (lif->registered) 240 name = lif->netdev->name; 241 else 242 name = dev_name(dev); 243 244 snprintf(intr->name, sizeof(intr->name), 245 "%s-%s-%s", IONIC_DRV_NAME, name, q->name); 246 247 return devm_request_irq(dev, intr->vector, ionic_isr, 248 0, intr->name, &qcq->napi); 249 } 250 251 static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) 252 { 253 struct ionic *ionic = lif->ionic; 254 int index; 255 256 index = find_first_zero_bit(ionic->intrs, ionic->nintrs); 257 if (index == ionic->nintrs) { 258 netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n", 259 __func__, index, ionic->nintrs); 260 return -ENOSPC; 261 } 262 263 set_bit(index, ionic->intrs); 264 ionic_intr_init(&ionic->idev, intr, index); 265 266 return 0; 267 } 268 269 static void ionic_intr_free(struct ionic *ionic, int index) 270 { 271 if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < ionic->nintrs) 272 clear_bit(index, ionic->intrs); 273 } 274 275 static int ionic_qcq_enable(struct ionic_qcq *qcq) 276 { 277 struct ionic_queue *q = &qcq->q; 278 struct ionic_lif *lif = q->lif; 279 struct ionic_dev *idev; 280 struct device *dev; 281 282 struct ionic_admin_ctx ctx = { 283 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 284 .cmd.q_control = { 285 .opcode = IONIC_CMD_Q_CONTROL, 286 .lif_index = cpu_to_le16(lif->index), 287 .type = q->type, 288 .index = cpu_to_le32(q->index), 289 .oper = IONIC_Q_ENABLE, 290 }, 291 }; 292 int ret; 293 294 idev = &lif->ionic->idev; 295 dev = lif->ionic->dev; 296 297 dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n", 298 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 299 300 if (qcq->flags & IONIC_QCQ_F_INTR) 301 ionic_intr_clean(idev->intr_ctrl, qcq->intr.index); 302 303 ret = ionic_adminq_post_wait(lif, &ctx); 304 if (ret) 305 return ret; 306 307 if (qcq->flags & IONIC_QCQ_F_INTR) { 308 napi_enable(&qcq->napi); 309 irq_set_affinity_hint(qcq->intr.vector, 310 &qcq->intr.affinity_mask); 311 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 312 IONIC_INTR_MASK_CLEAR); 313 } 314 315 return 0; 316 } 317 318 static int ionic_qcq_disable(struct ionic_lif *lif, struct ionic_qcq *qcq, int fw_err) 319 { 320 struct ionic_queue *q; 321 322 struct ionic_admin_ctx ctx = { 323 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 324 .cmd.q_control = { 325 .opcode = IONIC_CMD_Q_CONTROL, 326 .oper = IONIC_Q_DISABLE, 327 }, 328 }; 329 330 if (!qcq) { 331 netdev_err(lif->netdev, "%s: bad qcq\n", __func__); 332 return -ENXIO; 333 } 334 335 q = &qcq->q; 336 337 if (qcq->flags & IONIC_QCQ_F_INTR) { 338 struct ionic_dev *idev = &lif->ionic->idev; 339 340 cancel_work_sync(&qcq->dim.work); 341 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 342 IONIC_INTR_MASK_SET); 343 synchronize_irq(qcq->intr.vector); 344 irq_set_affinity_hint(qcq->intr.vector, NULL); 345 napi_disable(&qcq->napi); 346 del_timer_sync(&qcq->napi_deadline); 347 } 348 349 /* If there was a previous fw communcation error, don't bother with 350 * sending the adminq command and just return the same error value. 351 */ 352 if (fw_err == -ETIMEDOUT || fw_err == -ENXIO) 353 return fw_err; 354 355 ctx.cmd.q_control.lif_index = cpu_to_le16(lif->index); 356 ctx.cmd.q_control.type = q->type; 357 ctx.cmd.q_control.index = cpu_to_le32(q->index); 358 dev_dbg(lif->ionic->dev, "q_disable.index %d q_disable.qtype %d\n", 359 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 360 361 return ionic_adminq_post_wait(lif, &ctx); 362 } 363 364 static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq) 365 { 366 struct ionic_dev *idev = &lif->ionic->idev; 367 368 if (!qcq) 369 return; 370 371 if (!(qcq->flags & IONIC_QCQ_F_INITED)) 372 return; 373 374 if (qcq->flags & IONIC_QCQ_F_INTR) { 375 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 376 IONIC_INTR_MASK_SET); 377 netif_napi_del(&qcq->napi); 378 } 379 380 qcq->flags &= ~IONIC_QCQ_F_INITED; 381 } 382 383 static void ionic_qcq_intr_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 384 { 385 if (!(qcq->flags & IONIC_QCQ_F_INTR) || qcq->intr.vector == 0) 386 return; 387 388 irq_set_affinity_hint(qcq->intr.vector, NULL); 389 devm_free_irq(lif->ionic->dev, qcq->intr.vector, &qcq->napi); 390 qcq->intr.vector = 0; 391 ionic_intr_free(lif->ionic, qcq->intr.index); 392 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 393 } 394 395 static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 396 { 397 struct device *dev = lif->ionic->dev; 398 399 if (!qcq) 400 return; 401 402 ionic_debugfs_del_qcq(qcq); 403 404 if (qcq->q_base) { 405 dma_free_coherent(dev, qcq->q_size, qcq->q_base, qcq->q_base_pa); 406 qcq->q_base = NULL; 407 qcq->q_base_pa = 0; 408 } 409 410 if (qcq->cmb_q_base) { 411 iounmap(qcq->cmb_q_base); 412 ionic_put_cmb(lif, qcq->cmb_pgid, qcq->cmb_order); 413 qcq->cmb_pgid = 0; 414 qcq->cmb_order = 0; 415 qcq->cmb_q_base = NULL; 416 qcq->cmb_q_base_pa = 0; 417 } 418 419 if (qcq->cq_base) { 420 dma_free_coherent(dev, qcq->cq_size, qcq->cq_base, qcq->cq_base_pa); 421 qcq->cq_base = NULL; 422 qcq->cq_base_pa = 0; 423 } 424 425 if (qcq->sg_base) { 426 dma_free_coherent(dev, qcq->sg_size, qcq->sg_base, qcq->sg_base_pa); 427 qcq->sg_base = NULL; 428 qcq->sg_base_pa = 0; 429 } 430 431 ionic_xdp_unregister_rxq_info(&qcq->q); 432 ionic_qcq_intr_free(lif, qcq); 433 434 vfree(qcq->q.info); 435 qcq->q.info = NULL; 436 } 437 438 void ionic_qcqs_free(struct ionic_lif *lif) 439 { 440 struct device *dev = lif->ionic->dev; 441 struct ionic_qcq *adminqcq; 442 unsigned long irqflags; 443 444 if (lif->notifyqcq) { 445 ionic_qcq_free(lif, lif->notifyqcq); 446 devm_kfree(dev, lif->notifyqcq); 447 lif->notifyqcq = NULL; 448 } 449 450 if (lif->adminqcq) { 451 spin_lock_irqsave(&lif->adminq_lock, irqflags); 452 adminqcq = READ_ONCE(lif->adminqcq); 453 lif->adminqcq = NULL; 454 spin_unlock_irqrestore(&lif->adminq_lock, irqflags); 455 if (adminqcq) { 456 ionic_qcq_free(lif, adminqcq); 457 devm_kfree(dev, adminqcq); 458 } 459 } 460 461 if (lif->rxqcqs) { 462 devm_kfree(dev, lif->rxqstats); 463 lif->rxqstats = NULL; 464 devm_kfree(dev, lif->rxqcqs); 465 lif->rxqcqs = NULL; 466 } 467 468 if (lif->txqcqs) { 469 devm_kfree(dev, lif->txqstats); 470 lif->txqstats = NULL; 471 devm_kfree(dev, lif->txqcqs); 472 lif->txqcqs = NULL; 473 } 474 } 475 476 static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq, 477 struct ionic_qcq *n_qcq) 478 { 479 n_qcq->intr.vector = src_qcq->intr.vector; 480 n_qcq->intr.index = src_qcq->intr.index; 481 n_qcq->napi_qcq = src_qcq->napi_qcq; 482 } 483 484 static int ionic_alloc_qcq_interrupt(struct ionic_lif *lif, struct ionic_qcq *qcq) 485 { 486 int err; 487 488 if (!(qcq->flags & IONIC_QCQ_F_INTR)) { 489 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 490 return 0; 491 } 492 493 err = ionic_intr_alloc(lif, &qcq->intr); 494 if (err) { 495 netdev_warn(lif->netdev, "no intr for %s: %d\n", 496 qcq->q.name, err); 497 goto err_out; 498 } 499 500 err = ionic_bus_get_irq(lif->ionic, qcq->intr.index); 501 if (err < 0) { 502 netdev_warn(lif->netdev, "no vector for %s: %d\n", 503 qcq->q.name, err); 504 goto err_out_free_intr; 505 } 506 qcq->intr.vector = err; 507 ionic_intr_mask_assert(lif->ionic->idev.intr_ctrl, qcq->intr.index, 508 IONIC_INTR_MASK_SET); 509 510 err = ionic_request_irq(lif, qcq); 511 if (err) { 512 netdev_warn(lif->netdev, "irq request failed %d\n", err); 513 goto err_out_free_intr; 514 } 515 516 /* try to get the irq on the local numa node first */ 517 qcq->intr.cpu = cpumask_local_spread(qcq->intr.index, 518 dev_to_node(lif->ionic->dev)); 519 if (qcq->intr.cpu != -1) 520 cpumask_set_cpu(qcq->intr.cpu, &qcq->intr.affinity_mask); 521 522 netdev_dbg(lif->netdev, "%s: Interrupt index %d\n", qcq->q.name, qcq->intr.index); 523 return 0; 524 525 err_out_free_intr: 526 ionic_intr_free(lif->ionic, qcq->intr.index); 527 err_out: 528 return err; 529 } 530 531 static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type, 532 unsigned int index, 533 const char *name, unsigned int flags, 534 unsigned int num_descs, unsigned int desc_size, 535 unsigned int cq_desc_size, 536 unsigned int sg_desc_size, 537 unsigned int desc_info_size, 538 unsigned int pid, struct ionic_qcq **qcq) 539 { 540 struct ionic_dev *idev = &lif->ionic->idev; 541 struct device *dev = lif->ionic->dev; 542 struct ionic_qcq *new; 543 int err; 544 545 *qcq = NULL; 546 547 new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL); 548 if (!new) { 549 netdev_err(lif->netdev, "Cannot allocate queue structure\n"); 550 err = -ENOMEM; 551 goto err_out; 552 } 553 554 new->q.dev = dev; 555 new->flags = flags; 556 557 new->q.info = vcalloc(num_descs, desc_info_size); 558 if (!new->q.info) { 559 netdev_err(lif->netdev, "Cannot allocate queue info\n"); 560 err = -ENOMEM; 561 goto err_out_free_qcq; 562 } 563 564 new->q.type = type; 565 new->q.max_sg_elems = lif->qtype_info[type].max_sg_elems; 566 567 err = ionic_q_init(lif, idev, &new->q, index, name, num_descs, 568 desc_size, sg_desc_size, pid); 569 if (err) { 570 netdev_err(lif->netdev, "Cannot initialize queue\n"); 571 goto err_out_free_q_info; 572 } 573 574 err = ionic_alloc_qcq_interrupt(lif, new); 575 if (err) 576 goto err_out_free_q_info; 577 578 err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size); 579 if (err) { 580 netdev_err(lif->netdev, "Cannot initialize completion queue\n"); 581 goto err_out_free_irq; 582 } 583 584 if (flags & IONIC_QCQ_F_NOTIFYQ) { 585 int q_size; 586 587 /* q & cq need to be contiguous in NotifyQ, so alloc it all in q 588 * and don't alloc qc. We leave new->qc_size and new->qc_base 589 * as 0 to be sure we don't try to free it later. 590 */ 591 q_size = ALIGN(num_descs * desc_size, PAGE_SIZE); 592 new->q_size = PAGE_SIZE + q_size + 593 ALIGN(num_descs * cq_desc_size, PAGE_SIZE); 594 new->q_base = dma_alloc_coherent(dev, new->q_size, 595 &new->q_base_pa, GFP_KERNEL); 596 if (!new->q_base) { 597 netdev_err(lif->netdev, "Cannot allocate qcq DMA memory\n"); 598 err = -ENOMEM; 599 goto err_out_free_irq; 600 } 601 new->q.base = PTR_ALIGN(new->q_base, PAGE_SIZE); 602 new->q.base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 603 604 /* Base the NotifyQ cq.base off of the ALIGNed q.base */ 605 new->cq.base = PTR_ALIGN(new->q.base + q_size, PAGE_SIZE); 606 new->cq.base_pa = ALIGN(new->q_base_pa + q_size, PAGE_SIZE); 607 new->cq.bound_q = &new->q; 608 } else { 609 /* regular DMA q descriptors */ 610 new->q_size = PAGE_SIZE + (num_descs * desc_size); 611 new->q_base = dma_alloc_coherent(dev, new->q_size, &new->q_base_pa, 612 GFP_KERNEL); 613 if (!new->q_base) { 614 netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n"); 615 err = -ENOMEM; 616 goto err_out_free_irq; 617 } 618 new->q.base = PTR_ALIGN(new->q_base, PAGE_SIZE); 619 new->q.base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 620 621 if (flags & IONIC_QCQ_F_CMB_RINGS) { 622 /* on-chip CMB q descriptors */ 623 new->cmb_q_size = num_descs * desc_size; 624 new->cmb_order = order_base_2(new->cmb_q_size / PAGE_SIZE); 625 626 err = ionic_get_cmb(lif, &new->cmb_pgid, &new->cmb_q_base_pa, 627 new->cmb_order); 628 if (err) { 629 netdev_err(lif->netdev, 630 "Cannot allocate queue order %d from cmb: err %d\n", 631 new->cmb_order, err); 632 goto err_out_free_q; 633 } 634 635 new->cmb_q_base = ioremap_wc(new->cmb_q_base_pa, new->cmb_q_size); 636 if (!new->cmb_q_base) { 637 netdev_err(lif->netdev, "Cannot map queue from cmb\n"); 638 ionic_put_cmb(lif, new->cmb_pgid, new->cmb_order); 639 err = -ENOMEM; 640 goto err_out_free_q; 641 } 642 643 new->cmb_q_base_pa -= idev->phy_cmb_pages; 644 new->q.cmb_base = new->cmb_q_base; 645 new->q.cmb_base_pa = new->cmb_q_base_pa; 646 } 647 648 /* cq DMA descriptors */ 649 new->cq_size = PAGE_SIZE + (num_descs * cq_desc_size); 650 new->cq_base = dma_alloc_coherent(dev, new->cq_size, &new->cq_base_pa, 651 GFP_KERNEL); 652 if (!new->cq_base) { 653 netdev_err(lif->netdev, "Cannot allocate cq DMA memory\n"); 654 err = -ENOMEM; 655 goto err_out_free_q; 656 } 657 new->cq.base = PTR_ALIGN(new->cq_base, PAGE_SIZE); 658 new->cq.base_pa = ALIGN(new->cq_base_pa, PAGE_SIZE); 659 new->cq.bound_q = &new->q; 660 } 661 662 if (flags & IONIC_QCQ_F_SG) { 663 new->sg_size = PAGE_SIZE + (num_descs * sg_desc_size); 664 new->sg_base = dma_alloc_coherent(dev, new->sg_size, &new->sg_base_pa, 665 GFP_KERNEL); 666 if (!new->sg_base) { 667 netdev_err(lif->netdev, "Cannot allocate sg DMA memory\n"); 668 err = -ENOMEM; 669 goto err_out_free_cq; 670 } 671 new->q.sg_base = PTR_ALIGN(new->sg_base, PAGE_SIZE); 672 new->q.sg_base_pa = ALIGN(new->sg_base_pa, PAGE_SIZE); 673 } 674 675 INIT_WORK(&new->dim.work, ionic_dim_work); 676 new->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; 677 678 *qcq = new; 679 680 return 0; 681 682 err_out_free_cq: 683 dma_free_coherent(dev, new->cq_size, new->cq_base, new->cq_base_pa); 684 err_out_free_q: 685 if (new->cmb_q_base) { 686 iounmap(new->cmb_q_base); 687 ionic_put_cmb(lif, new->cmb_pgid, new->cmb_order); 688 } 689 dma_free_coherent(dev, new->q_size, new->q_base, new->q_base_pa); 690 err_out_free_irq: 691 if (flags & IONIC_QCQ_F_INTR) { 692 devm_free_irq(dev, new->intr.vector, &new->napi); 693 ionic_intr_free(lif->ionic, new->intr.index); 694 } 695 err_out_free_q_info: 696 vfree(new->q.info); 697 err_out_free_qcq: 698 devm_kfree(dev, new); 699 err_out: 700 dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err); 701 return err; 702 } 703 704 static int ionic_qcqs_alloc(struct ionic_lif *lif) 705 { 706 struct device *dev = lif->ionic->dev; 707 unsigned int flags; 708 int err; 709 710 flags = IONIC_QCQ_F_INTR; 711 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags, 712 IONIC_ADMINQ_LENGTH, 713 sizeof(struct ionic_admin_cmd), 714 sizeof(struct ionic_admin_comp), 715 0, 716 sizeof(struct ionic_admin_desc_info), 717 lif->kern_pid, &lif->adminqcq); 718 if (err) 719 return err; 720 ionic_debugfs_add_qcq(lif, lif->adminqcq); 721 722 if (lif->ionic->nnqs_per_lif) { 723 flags = IONIC_QCQ_F_NOTIFYQ; 724 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq", 725 flags, IONIC_NOTIFYQ_LENGTH, 726 sizeof(struct ionic_notifyq_cmd), 727 sizeof(union ionic_notifyq_comp), 728 0, 729 sizeof(struct ionic_admin_desc_info), 730 lif->kern_pid, &lif->notifyqcq); 731 if (err) 732 goto err_out; 733 ionic_debugfs_add_qcq(lif, lif->notifyqcq); 734 735 /* Let the notifyq ride on the adminq interrupt */ 736 ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq); 737 } 738 739 err = -ENOMEM; 740 lif->txqcqs = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif, 741 sizeof(*lif->txqcqs), GFP_KERNEL); 742 if (!lif->txqcqs) 743 goto err_out; 744 lif->rxqcqs = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif, 745 sizeof(*lif->rxqcqs), GFP_KERNEL); 746 if (!lif->rxqcqs) 747 goto err_out; 748 749 lif->txqstats = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif + 1, 750 sizeof(*lif->txqstats), GFP_KERNEL); 751 if (!lif->txqstats) 752 goto err_out; 753 lif->rxqstats = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif + 1, 754 sizeof(*lif->rxqstats), GFP_KERNEL); 755 if (!lif->rxqstats) 756 goto err_out; 757 758 return 0; 759 760 err_out: 761 ionic_qcqs_free(lif); 762 return err; 763 } 764 765 static void ionic_qcq_sanitize(struct ionic_qcq *qcq) 766 { 767 qcq->q.tail_idx = 0; 768 qcq->q.head_idx = 0; 769 qcq->cq.tail_idx = 0; 770 qcq->cq.done_color = 1; 771 memset(qcq->q_base, 0, qcq->q_size); 772 if (qcq->cmb_q_base) 773 memset_io(qcq->cmb_q_base, 0, qcq->cmb_q_size); 774 memset(qcq->cq_base, 0, qcq->cq_size); 775 memset(qcq->sg_base, 0, qcq->sg_size); 776 } 777 778 static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 779 { 780 struct device *dev = lif->ionic->dev; 781 struct ionic_queue *q = &qcq->q; 782 struct ionic_cq *cq = &qcq->cq; 783 struct ionic_admin_ctx ctx = { 784 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 785 .cmd.q_init = { 786 .opcode = IONIC_CMD_Q_INIT, 787 .lif_index = cpu_to_le16(lif->index), 788 .type = q->type, 789 .ver = lif->qtype_info[q->type].version, 790 .index = cpu_to_le32(q->index), 791 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 792 IONIC_QINIT_F_SG), 793 .intr_index = cpu_to_le16(qcq->intr.index), 794 .pid = cpu_to_le16(q->pid), 795 .ring_size = ilog2(q->num_descs), 796 .ring_base = cpu_to_le64(q->base_pa), 797 .cq_ring_base = cpu_to_le64(cq->base_pa), 798 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 799 .features = cpu_to_le64(q->features), 800 }, 801 }; 802 int err; 803 804 if (qcq->flags & IONIC_QCQ_F_CMB_RINGS) { 805 ctx.cmd.q_init.flags |= cpu_to_le16(IONIC_QINIT_F_CMB); 806 ctx.cmd.q_init.ring_base = cpu_to_le64(qcq->cmb_q_base_pa); 807 } 808 809 dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid); 810 dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index); 811 dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 812 dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 813 dev_dbg(dev, "txq_init.cq_ring_base 0x%llx\n", ctx.cmd.q_init.cq_ring_base); 814 dev_dbg(dev, "txq_init.sg_ring_base 0x%llx\n", ctx.cmd.q_init.sg_ring_base); 815 dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 816 dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver); 817 dev_dbg(dev, "txq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 818 819 ionic_qcq_sanitize(qcq); 820 821 err = ionic_adminq_post_wait(lif, &ctx); 822 if (err) 823 return err; 824 825 q->hw_type = ctx.comp.q_init.hw_type; 826 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 827 q->dbval = IONIC_DBELL_QID(q->hw_index); 828 829 dev_dbg(dev, "txq->hw_type %d\n", q->hw_type); 830 dev_dbg(dev, "txq->hw_index %d\n", q->hw_index); 831 832 q->dbell_deadline = IONIC_TX_DOORBELL_DEADLINE; 833 q->dbell_jiffies = jiffies; 834 835 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) { 836 netif_napi_add(lif->netdev, &qcq->napi, ionic_tx_napi); 837 qcq->napi_qcq = qcq; 838 timer_setup(&qcq->napi_deadline, ionic_napi_deadline, 0); 839 } 840 841 qcq->flags |= IONIC_QCQ_F_INITED; 842 843 return 0; 844 } 845 846 static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 847 { 848 struct device *dev = lif->ionic->dev; 849 struct ionic_queue *q = &qcq->q; 850 struct ionic_cq *cq = &qcq->cq; 851 struct ionic_admin_ctx ctx = { 852 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 853 .cmd.q_init = { 854 .opcode = IONIC_CMD_Q_INIT, 855 .lif_index = cpu_to_le16(lif->index), 856 .type = q->type, 857 .ver = lif->qtype_info[q->type].version, 858 .index = cpu_to_le32(q->index), 859 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ), 860 .intr_index = cpu_to_le16(cq->bound_intr->index), 861 .pid = cpu_to_le16(q->pid), 862 .ring_size = ilog2(q->num_descs), 863 .ring_base = cpu_to_le64(q->base_pa), 864 .cq_ring_base = cpu_to_le64(cq->base_pa), 865 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 866 .features = cpu_to_le64(q->features), 867 }, 868 }; 869 int err; 870 871 q->partner = &lif->txqcqs[q->index]->q; 872 q->partner->partner = q; 873 874 if (!lif->xdp_prog || 875 (lif->xdp_prog->aux && lif->xdp_prog->aux->xdp_has_frags)) 876 ctx.cmd.q_init.flags |= cpu_to_le16(IONIC_QINIT_F_SG); 877 878 if (qcq->flags & IONIC_QCQ_F_CMB_RINGS) { 879 ctx.cmd.q_init.flags |= cpu_to_le16(IONIC_QINIT_F_CMB); 880 ctx.cmd.q_init.ring_base = cpu_to_le64(qcq->cmb_q_base_pa); 881 } 882 883 dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid); 884 dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index); 885 dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 886 dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 887 dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 888 dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver); 889 dev_dbg(dev, "rxq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 890 891 ionic_qcq_sanitize(qcq); 892 893 err = ionic_adminq_post_wait(lif, &ctx); 894 if (err) 895 return err; 896 897 q->hw_type = ctx.comp.q_init.hw_type; 898 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 899 q->dbval = IONIC_DBELL_QID(q->hw_index); 900 901 dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type); 902 dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index); 903 904 q->dbell_deadline = IONIC_RX_MIN_DOORBELL_DEADLINE; 905 q->dbell_jiffies = jiffies; 906 907 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 908 netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi); 909 else 910 netif_napi_add(lif->netdev, &qcq->napi, ionic_txrx_napi); 911 912 qcq->napi_qcq = qcq; 913 timer_setup(&qcq->napi_deadline, ionic_napi_deadline, 0); 914 915 qcq->flags |= IONIC_QCQ_F_INITED; 916 917 return 0; 918 } 919 920 int ionic_lif_create_hwstamp_txq(struct ionic_lif *lif) 921 { 922 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz; 923 unsigned int txq_i, flags; 924 struct ionic_qcq *txq; 925 u64 features; 926 int err; 927 928 if (lif->hwstamp_txq) 929 return 0; 930 931 features = IONIC_Q_F_2X_CQ_DESC | IONIC_TXQ_F_HWSTAMP; 932 933 num_desc = IONIC_MIN_TXRX_DESC; 934 desc_sz = sizeof(struct ionic_txq_desc); 935 comp_sz = 2 * sizeof(struct ionic_txq_comp); 936 937 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 938 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == sizeof(struct ionic_txq_sg_desc_v1)) 939 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 940 else 941 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 942 943 txq_i = lif->ionic->ntxqs_per_lif; 944 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 945 946 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, txq_i, "hwstamp_tx", flags, 947 num_desc, desc_sz, comp_sz, sg_desc_sz, 948 sizeof(struct ionic_tx_desc_info), 949 lif->kern_pid, &txq); 950 if (err) 951 goto err_qcq_alloc; 952 953 txq->q.features = features; 954 955 ionic_link_qcq_interrupts(lif->adminqcq, txq); 956 ionic_debugfs_add_qcq(lif, txq); 957 958 lif->hwstamp_txq = txq; 959 960 if (netif_running(lif->netdev)) { 961 err = ionic_lif_txq_init(lif, txq); 962 if (err) 963 goto err_qcq_init; 964 965 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 966 err = ionic_qcq_enable(txq); 967 if (err) 968 goto err_qcq_enable; 969 } 970 } 971 972 return 0; 973 974 err_qcq_enable: 975 ionic_lif_qcq_deinit(lif, txq); 976 err_qcq_init: 977 lif->hwstamp_txq = NULL; 978 ionic_debugfs_del_qcq(txq); 979 ionic_qcq_free(lif, txq); 980 devm_kfree(lif->ionic->dev, txq); 981 err_qcq_alloc: 982 return err; 983 } 984 985 int ionic_lif_create_hwstamp_rxq(struct ionic_lif *lif) 986 { 987 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz; 988 unsigned int rxq_i, flags; 989 struct ionic_qcq *rxq; 990 u64 features; 991 int err; 992 993 if (lif->hwstamp_rxq) 994 return 0; 995 996 features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP; 997 998 num_desc = IONIC_MIN_TXRX_DESC; 999 desc_sz = sizeof(struct ionic_rxq_desc); 1000 comp_sz = 2 * sizeof(struct ionic_rxq_comp); 1001 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 1002 1003 rxq_i = lif->ionic->nrxqs_per_lif; 1004 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG; 1005 1006 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, rxq_i, "hwstamp_rx", flags, 1007 num_desc, desc_sz, comp_sz, sg_desc_sz, 1008 sizeof(struct ionic_rx_desc_info), 1009 lif->kern_pid, &rxq); 1010 if (err) 1011 goto err_qcq_alloc; 1012 1013 rxq->q.features = features; 1014 1015 ionic_link_qcq_interrupts(lif->adminqcq, rxq); 1016 ionic_debugfs_add_qcq(lif, rxq); 1017 1018 lif->hwstamp_rxq = rxq; 1019 1020 if (netif_running(lif->netdev)) { 1021 err = ionic_lif_rxq_init(lif, rxq); 1022 if (err) 1023 goto err_qcq_init; 1024 1025 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 1026 ionic_rx_fill(&rxq->q); 1027 err = ionic_qcq_enable(rxq); 1028 if (err) 1029 goto err_qcq_enable; 1030 } 1031 } 1032 1033 return 0; 1034 1035 err_qcq_enable: 1036 ionic_lif_qcq_deinit(lif, rxq); 1037 err_qcq_init: 1038 lif->hwstamp_rxq = NULL; 1039 ionic_debugfs_del_qcq(rxq); 1040 ionic_qcq_free(lif, rxq); 1041 devm_kfree(lif->ionic->dev, rxq); 1042 err_qcq_alloc: 1043 return err; 1044 } 1045 1046 int ionic_lif_config_hwstamp_rxq_all(struct ionic_lif *lif, bool rx_all) 1047 { 1048 struct ionic_queue_params qparam; 1049 1050 ionic_init_queue_params(lif, &qparam); 1051 1052 if (rx_all) 1053 qparam.rxq_features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP; 1054 else 1055 qparam.rxq_features = 0; 1056 1057 /* if we're not running, just set the values and return */ 1058 if (!netif_running(lif->netdev)) { 1059 lif->rxq_features = qparam.rxq_features; 1060 return 0; 1061 } 1062 1063 return ionic_reconfigure_queues(lif, &qparam); 1064 } 1065 1066 int ionic_lif_set_hwstamp_txmode(struct ionic_lif *lif, u16 txstamp_mode) 1067 { 1068 struct ionic_admin_ctx ctx = { 1069 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1070 .cmd.lif_setattr = { 1071 .opcode = IONIC_CMD_LIF_SETATTR, 1072 .index = cpu_to_le16(lif->index), 1073 .attr = IONIC_LIF_ATTR_TXSTAMP, 1074 .txstamp_mode = cpu_to_le16(txstamp_mode), 1075 }, 1076 }; 1077 1078 return ionic_adminq_post_wait(lif, &ctx); 1079 } 1080 1081 static void ionic_lif_del_hwstamp_rxfilt(struct ionic_lif *lif) 1082 { 1083 struct ionic_admin_ctx ctx = { 1084 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1085 .cmd.rx_filter_del = { 1086 .opcode = IONIC_CMD_RX_FILTER_DEL, 1087 .lif_index = cpu_to_le16(lif->index), 1088 }, 1089 }; 1090 struct ionic_rx_filter *f; 1091 u32 filter_id; 1092 int err; 1093 1094 spin_lock_bh(&lif->rx_filters.lock); 1095 1096 f = ionic_rx_filter_rxsteer(lif); 1097 if (!f) { 1098 spin_unlock_bh(&lif->rx_filters.lock); 1099 return; 1100 } 1101 1102 filter_id = f->filter_id; 1103 ionic_rx_filter_free(lif, f); 1104 1105 spin_unlock_bh(&lif->rx_filters.lock); 1106 1107 netdev_dbg(lif->netdev, "rx_filter del RXSTEER (id %d)\n", filter_id); 1108 1109 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(filter_id); 1110 1111 err = ionic_adminq_post_wait(lif, &ctx); 1112 if (err && err != -EEXIST) 1113 netdev_dbg(lif->netdev, "failed to delete rx_filter RXSTEER (id %d)\n", filter_id); 1114 } 1115 1116 static int ionic_lif_add_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class) 1117 { 1118 struct ionic_admin_ctx ctx = { 1119 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1120 .cmd.rx_filter_add = { 1121 .opcode = IONIC_CMD_RX_FILTER_ADD, 1122 .lif_index = cpu_to_le16(lif->index), 1123 .match = cpu_to_le16(IONIC_RX_FILTER_STEER_PKTCLASS), 1124 .pkt_class = cpu_to_le64(pkt_class), 1125 }, 1126 }; 1127 u8 qtype; 1128 u32 qid; 1129 int err; 1130 1131 if (!lif->hwstamp_rxq) 1132 return -EINVAL; 1133 1134 qtype = lif->hwstamp_rxq->q.type; 1135 ctx.cmd.rx_filter_add.qtype = qtype; 1136 1137 qid = lif->hwstamp_rxq->q.index; 1138 ctx.cmd.rx_filter_add.qid = cpu_to_le32(qid); 1139 1140 netdev_dbg(lif->netdev, "rx_filter add RXSTEER\n"); 1141 err = ionic_adminq_post_wait(lif, &ctx); 1142 if (err && err != -EEXIST) 1143 return err; 1144 1145 spin_lock_bh(&lif->rx_filters.lock); 1146 err = ionic_rx_filter_save(lif, 0, qid, 0, &ctx, IONIC_FILTER_STATE_SYNCED); 1147 spin_unlock_bh(&lif->rx_filters.lock); 1148 1149 return err; 1150 } 1151 1152 int ionic_lif_set_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class) 1153 { 1154 ionic_lif_del_hwstamp_rxfilt(lif); 1155 1156 if (!pkt_class) 1157 return 0; 1158 1159 return ionic_lif_add_hwstamp_rxfilt(lif, pkt_class); 1160 } 1161 1162 static int ionic_adminq_napi(struct napi_struct *napi, int budget) 1163 { 1164 struct ionic_intr_info *intr = napi_to_cq(napi)->bound_intr; 1165 struct ionic_lif *lif = napi_to_cq(napi)->lif; 1166 struct ionic_dev *idev = &lif->ionic->idev; 1167 unsigned long irqflags; 1168 unsigned int flags = 0; 1169 bool resched = false; 1170 int rx_work = 0; 1171 int tx_work = 0; 1172 int n_work = 0; 1173 int a_work = 0; 1174 int work_done; 1175 int credits; 1176 1177 if (lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED) 1178 n_work = ionic_cq_service(&lif->notifyqcq->cq, budget, 1179 ionic_notifyq_service, NULL, NULL); 1180 1181 spin_lock_irqsave(&lif->adminq_lock, irqflags); 1182 if (lif->adminqcq && lif->adminqcq->flags & IONIC_QCQ_F_INITED) 1183 a_work = ionic_cq_service(&lif->adminqcq->cq, budget, 1184 ionic_adminq_service, NULL, NULL); 1185 spin_unlock_irqrestore(&lif->adminq_lock, irqflags); 1186 1187 if (lif->hwstamp_rxq) 1188 rx_work = ionic_cq_service(&lif->hwstamp_rxq->cq, budget, 1189 ionic_rx_service, NULL, NULL); 1190 1191 if (lif->hwstamp_txq) 1192 tx_work = ionic_tx_cq_service(&lif->hwstamp_txq->cq, budget, !!budget); 1193 1194 work_done = max(max(n_work, a_work), max(rx_work, tx_work)); 1195 if (work_done < budget && napi_complete_done(napi, work_done)) { 1196 flags |= IONIC_INTR_CRED_UNMASK; 1197 intr->rearm_count++; 1198 } 1199 1200 if (work_done || flags) { 1201 flags |= IONIC_INTR_CRED_RESET_COALESCE; 1202 credits = n_work + a_work + rx_work + tx_work; 1203 ionic_intr_credits(idev->intr_ctrl, intr->index, credits, flags); 1204 } 1205 1206 if (!a_work && ionic_adminq_poke_doorbell(&lif->adminqcq->q)) 1207 resched = true; 1208 if (lif->hwstamp_rxq && !rx_work && ionic_rxq_poke_doorbell(&lif->hwstamp_rxq->q)) 1209 resched = true; 1210 if (lif->hwstamp_txq && !tx_work && ionic_txq_poke_doorbell(&lif->hwstamp_txq->q)) 1211 resched = true; 1212 if (resched) 1213 mod_timer(&lif->adminqcq->napi_deadline, 1214 jiffies + IONIC_NAPI_DEADLINE); 1215 1216 return work_done; 1217 } 1218 1219 void ionic_get_stats64(struct net_device *netdev, 1220 struct rtnl_link_stats64 *ns) 1221 { 1222 struct ionic_lif *lif = netdev_priv(netdev); 1223 struct ionic_lif_stats *ls; 1224 1225 memset(ns, 0, sizeof(*ns)); 1226 ls = &lif->info->stats; 1227 1228 ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) + 1229 le64_to_cpu(ls->rx_mcast_packets) + 1230 le64_to_cpu(ls->rx_bcast_packets); 1231 1232 ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) + 1233 le64_to_cpu(ls->tx_mcast_packets) + 1234 le64_to_cpu(ls->tx_bcast_packets); 1235 1236 ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) + 1237 le64_to_cpu(ls->rx_mcast_bytes) + 1238 le64_to_cpu(ls->rx_bcast_bytes); 1239 1240 ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) + 1241 le64_to_cpu(ls->tx_mcast_bytes) + 1242 le64_to_cpu(ls->tx_bcast_bytes); 1243 1244 ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) + 1245 le64_to_cpu(ls->rx_mcast_drop_packets) + 1246 le64_to_cpu(ls->rx_bcast_drop_packets); 1247 1248 ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) + 1249 le64_to_cpu(ls->tx_mcast_drop_packets) + 1250 le64_to_cpu(ls->tx_bcast_drop_packets); 1251 1252 ns->multicast = le64_to_cpu(ls->rx_mcast_packets); 1253 1254 ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty); 1255 1256 ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) + 1257 le64_to_cpu(ls->rx_queue_disabled) + 1258 le64_to_cpu(ls->rx_desc_fetch_error) + 1259 le64_to_cpu(ls->rx_desc_data_error); 1260 1261 ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) + 1262 le64_to_cpu(ls->tx_queue_disabled) + 1263 le64_to_cpu(ls->tx_desc_fetch_error) + 1264 le64_to_cpu(ls->tx_desc_data_error); 1265 1266 ns->rx_errors = ns->rx_over_errors + 1267 ns->rx_missed_errors; 1268 1269 ns->tx_errors = ns->tx_aborted_errors; 1270 } 1271 1272 static int ionic_addr_add(struct net_device *netdev, const u8 *addr) 1273 { 1274 return ionic_lif_list_addr(netdev_priv(netdev), addr, ADD_ADDR); 1275 } 1276 1277 static int ionic_addr_del(struct net_device *netdev, const u8 *addr) 1278 { 1279 /* Don't delete our own address from the uc list */ 1280 if (ether_addr_equal(addr, netdev->dev_addr)) 1281 return 0; 1282 1283 return ionic_lif_list_addr(netdev_priv(netdev), addr, DEL_ADDR); 1284 } 1285 1286 void ionic_lif_rx_mode(struct ionic_lif *lif) 1287 { 1288 struct net_device *netdev = lif->netdev; 1289 unsigned int nfilters; 1290 unsigned int nd_flags; 1291 char buf[128]; 1292 u16 rx_mode; 1293 int i; 1294 #define REMAIN(__x) (sizeof(buf) - (__x)) 1295 1296 mutex_lock(&lif->config_lock); 1297 1298 /* grab the flags once for local use */ 1299 nd_flags = netdev->flags; 1300 1301 rx_mode = IONIC_RX_MODE_F_UNICAST; 1302 rx_mode |= (nd_flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0; 1303 rx_mode |= (nd_flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0; 1304 rx_mode |= (nd_flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0; 1305 rx_mode |= (nd_flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0; 1306 1307 /* sync the filters */ 1308 ionic_rx_filter_sync(lif); 1309 1310 /* check for overflow state 1311 * if so, we track that we overflowed and enable NIC PROMISC 1312 * else if the overflow is set and not needed 1313 * we remove our overflow flag and check the netdev flags 1314 * to see if we can disable NIC PROMISC 1315 */ 1316 nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters); 1317 1318 if (((lif->nucast + lif->nmcast) >= nfilters) || 1319 (lif->max_vlans && lif->nvlans >= lif->max_vlans)) { 1320 rx_mode |= IONIC_RX_MODE_F_PROMISC; 1321 rx_mode |= IONIC_RX_MODE_F_ALLMULTI; 1322 } else { 1323 if (!(nd_flags & IFF_PROMISC)) 1324 rx_mode &= ~IONIC_RX_MODE_F_PROMISC; 1325 if (!(nd_flags & IFF_ALLMULTI)) 1326 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI; 1327 } 1328 1329 i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:", 1330 lif->rx_mode, rx_mode); 1331 if (rx_mode & IONIC_RX_MODE_F_UNICAST) 1332 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST"); 1333 if (rx_mode & IONIC_RX_MODE_F_MULTICAST) 1334 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST"); 1335 if (rx_mode & IONIC_RX_MODE_F_BROADCAST) 1336 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST"); 1337 if (rx_mode & IONIC_RX_MODE_F_PROMISC) 1338 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC"); 1339 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI) 1340 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI"); 1341 if (rx_mode & IONIC_RX_MODE_F_RDMA_SNIFFER) 1342 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_RDMA_SNIFFER"); 1343 netdev_dbg(netdev, "lif%d %s\n", lif->index, buf); 1344 1345 if (lif->rx_mode != rx_mode) { 1346 struct ionic_admin_ctx ctx = { 1347 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1348 .cmd.rx_mode_set = { 1349 .opcode = IONIC_CMD_RX_MODE_SET, 1350 .lif_index = cpu_to_le16(lif->index), 1351 }, 1352 }; 1353 int err; 1354 1355 ctx.cmd.rx_mode_set.rx_mode = cpu_to_le16(rx_mode); 1356 err = ionic_adminq_post_wait(lif, &ctx); 1357 if (err) 1358 netdev_warn(netdev, "set rx_mode 0x%04x failed: %d\n", 1359 rx_mode, err); 1360 else 1361 lif->rx_mode = rx_mode; 1362 } 1363 1364 mutex_unlock(&lif->config_lock); 1365 } 1366 1367 static void ionic_ndo_set_rx_mode(struct net_device *netdev) 1368 { 1369 struct ionic_lif *lif = netdev_priv(netdev); 1370 struct ionic_deferred_work *work; 1371 1372 /* Sync the kernel filter list with the driver filter list */ 1373 __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del); 1374 __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del); 1375 1376 /* Shove off the rest of the rxmode work to the work task 1377 * which will include syncing the filters to the firmware. 1378 */ 1379 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1380 if (!work) { 1381 netdev_err(lif->netdev, "rxmode change dropped\n"); 1382 return; 1383 } 1384 work->type = IONIC_DW_TYPE_RX_MODE; 1385 netdev_dbg(lif->netdev, "deferred: rx_mode\n"); 1386 ionic_lif_deferred_enqueue(&lif->deferred, work); 1387 } 1388 1389 static __le64 ionic_netdev_features_to_nic(netdev_features_t features) 1390 { 1391 u64 wanted = 0; 1392 1393 if (features & NETIF_F_HW_VLAN_CTAG_TX) 1394 wanted |= IONIC_ETH_HW_VLAN_TX_TAG; 1395 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1396 wanted |= IONIC_ETH_HW_VLAN_RX_STRIP; 1397 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1398 wanted |= IONIC_ETH_HW_VLAN_RX_FILTER; 1399 if (features & NETIF_F_RXHASH) 1400 wanted |= IONIC_ETH_HW_RX_HASH; 1401 if (features & NETIF_F_RXCSUM) 1402 wanted |= IONIC_ETH_HW_RX_CSUM; 1403 if (features & NETIF_F_SG) 1404 wanted |= IONIC_ETH_HW_TX_SG; 1405 if (features & NETIF_F_HW_CSUM) 1406 wanted |= IONIC_ETH_HW_TX_CSUM; 1407 if (features & NETIF_F_TSO) 1408 wanted |= IONIC_ETH_HW_TSO; 1409 if (features & NETIF_F_TSO6) 1410 wanted |= IONIC_ETH_HW_TSO_IPV6; 1411 if (features & NETIF_F_TSO_ECN) 1412 wanted |= IONIC_ETH_HW_TSO_ECN; 1413 if (features & NETIF_F_GSO_GRE) 1414 wanted |= IONIC_ETH_HW_TSO_GRE; 1415 if (features & NETIF_F_GSO_GRE_CSUM) 1416 wanted |= IONIC_ETH_HW_TSO_GRE_CSUM; 1417 if (features & NETIF_F_GSO_IPXIP4) 1418 wanted |= IONIC_ETH_HW_TSO_IPXIP4; 1419 if (features & NETIF_F_GSO_IPXIP6) 1420 wanted |= IONIC_ETH_HW_TSO_IPXIP6; 1421 if (features & NETIF_F_GSO_UDP_TUNNEL) 1422 wanted |= IONIC_ETH_HW_TSO_UDP; 1423 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) 1424 wanted |= IONIC_ETH_HW_TSO_UDP_CSUM; 1425 1426 return cpu_to_le64(wanted); 1427 } 1428 1429 static int ionic_set_nic_features(struct ionic_lif *lif, 1430 netdev_features_t features) 1431 { 1432 struct device *dev = lif->ionic->dev; 1433 struct ionic_admin_ctx ctx = { 1434 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1435 .cmd.lif_setattr = { 1436 .opcode = IONIC_CMD_LIF_SETATTR, 1437 .index = cpu_to_le16(lif->index), 1438 .attr = IONIC_LIF_ATTR_FEATURES, 1439 }, 1440 }; 1441 u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG | 1442 IONIC_ETH_HW_VLAN_RX_STRIP | 1443 IONIC_ETH_HW_VLAN_RX_FILTER; 1444 u64 old_hw_features; 1445 int err; 1446 1447 ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features); 1448 1449 if (lif->phc) 1450 ctx.cmd.lif_setattr.features |= cpu_to_le64(IONIC_ETH_HW_TIMESTAMP); 1451 1452 err = ionic_adminq_post_wait(lif, &ctx); 1453 if (err) 1454 return err; 1455 1456 old_hw_features = lif->hw_features; 1457 lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features & 1458 ctx.comp.lif_setattr.features); 1459 1460 if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH) 1461 ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1462 1463 if ((vlan_flags & le64_to_cpu(ctx.cmd.lif_setattr.features)) && 1464 !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features))) 1465 dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n"); 1466 1467 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1468 dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n"); 1469 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1470 dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n"); 1471 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1472 dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n"); 1473 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1474 dev_dbg(dev, "feature ETH_HW_RX_HASH\n"); 1475 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1476 dev_dbg(dev, "feature ETH_HW_TX_SG\n"); 1477 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1478 dev_dbg(dev, "feature ETH_HW_TX_CSUM\n"); 1479 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1480 dev_dbg(dev, "feature ETH_HW_RX_CSUM\n"); 1481 if (lif->hw_features & IONIC_ETH_HW_TSO) 1482 dev_dbg(dev, "feature ETH_HW_TSO\n"); 1483 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1484 dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n"); 1485 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1486 dev_dbg(dev, "feature ETH_HW_TSO_ECN\n"); 1487 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1488 dev_dbg(dev, "feature ETH_HW_TSO_GRE\n"); 1489 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1490 dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n"); 1491 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1492 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n"); 1493 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1494 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n"); 1495 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1496 dev_dbg(dev, "feature ETH_HW_TSO_UDP\n"); 1497 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1498 dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n"); 1499 if (lif->hw_features & IONIC_ETH_HW_TIMESTAMP) 1500 dev_dbg(dev, "feature ETH_HW_TIMESTAMP\n"); 1501 1502 return 0; 1503 } 1504 1505 static int ionic_init_nic_features(struct ionic_lif *lif) 1506 { 1507 struct net_device *netdev = lif->netdev; 1508 netdev_features_t features; 1509 int err; 1510 1511 /* set up what we expect to support by default */ 1512 features = NETIF_F_HW_VLAN_CTAG_TX | 1513 NETIF_F_HW_VLAN_CTAG_RX | 1514 NETIF_F_HW_VLAN_CTAG_FILTER | 1515 NETIF_F_SG | 1516 NETIF_F_HW_CSUM | 1517 NETIF_F_RXCSUM | 1518 NETIF_F_TSO | 1519 NETIF_F_TSO6 | 1520 NETIF_F_TSO_ECN | 1521 NETIF_F_GSO_GRE | 1522 NETIF_F_GSO_GRE_CSUM | 1523 NETIF_F_GSO_IPXIP4 | 1524 NETIF_F_GSO_IPXIP6 | 1525 NETIF_F_GSO_UDP_TUNNEL | 1526 NETIF_F_GSO_UDP_TUNNEL_CSUM; 1527 1528 if (lif->nxqs > 1) 1529 features |= NETIF_F_RXHASH; 1530 1531 err = ionic_set_nic_features(lif, features); 1532 if (err) 1533 return err; 1534 1535 /* tell the netdev what we actually can support */ 1536 netdev->features |= NETIF_F_HIGHDMA; 1537 1538 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1539 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 1540 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1541 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 1542 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1543 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1544 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1545 netdev->hw_features |= NETIF_F_RXHASH; 1546 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1547 netdev->hw_features |= NETIF_F_SG; 1548 1549 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1550 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 1551 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1552 netdev->hw_enc_features |= NETIF_F_RXCSUM; 1553 if (lif->hw_features & IONIC_ETH_HW_TSO) 1554 netdev->hw_enc_features |= NETIF_F_TSO; 1555 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1556 netdev->hw_enc_features |= NETIF_F_TSO6; 1557 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1558 netdev->hw_enc_features |= NETIF_F_TSO_ECN; 1559 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1560 netdev->hw_enc_features |= NETIF_F_GSO_GRE; 1561 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1562 netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM; 1563 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1564 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4; 1565 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1566 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6; 1567 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1568 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL; 1569 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1570 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 1571 1572 netdev->hw_features |= netdev->hw_enc_features; 1573 netdev->features |= netdev->hw_features; 1574 netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES; 1575 1576 netdev->priv_flags |= IFF_UNICAST_FLT | 1577 IFF_LIVE_ADDR_CHANGE; 1578 1579 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | 1580 NETDEV_XDP_ACT_REDIRECT | 1581 NETDEV_XDP_ACT_RX_SG | 1582 NETDEV_XDP_ACT_NDO_XMIT | 1583 NETDEV_XDP_ACT_NDO_XMIT_SG; 1584 1585 return 0; 1586 } 1587 1588 static int ionic_set_features(struct net_device *netdev, 1589 netdev_features_t features) 1590 { 1591 struct ionic_lif *lif = netdev_priv(netdev); 1592 int err; 1593 1594 netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n", 1595 __func__, (u64)lif->netdev->features, (u64)features); 1596 1597 err = ionic_set_nic_features(lif, features); 1598 1599 return err; 1600 } 1601 1602 static int ionic_set_attr_mac(struct ionic_lif *lif, u8 *mac) 1603 { 1604 struct ionic_admin_ctx ctx = { 1605 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1606 .cmd.lif_setattr = { 1607 .opcode = IONIC_CMD_LIF_SETATTR, 1608 .index = cpu_to_le16(lif->index), 1609 .attr = IONIC_LIF_ATTR_MAC, 1610 }, 1611 }; 1612 1613 ether_addr_copy(ctx.cmd.lif_setattr.mac, mac); 1614 return ionic_adminq_post_wait(lif, &ctx); 1615 } 1616 1617 static int ionic_get_attr_mac(struct ionic_lif *lif, u8 *mac_addr) 1618 { 1619 struct ionic_admin_ctx ctx = { 1620 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1621 .cmd.lif_getattr = { 1622 .opcode = IONIC_CMD_LIF_GETATTR, 1623 .index = cpu_to_le16(lif->index), 1624 .attr = IONIC_LIF_ATTR_MAC, 1625 }, 1626 }; 1627 int err; 1628 1629 err = ionic_adminq_post_wait(lif, &ctx); 1630 if (err) 1631 return err; 1632 1633 ether_addr_copy(mac_addr, ctx.comp.lif_getattr.mac); 1634 return 0; 1635 } 1636 1637 static int ionic_program_mac(struct ionic_lif *lif, u8 *mac) 1638 { 1639 u8 get_mac[ETH_ALEN]; 1640 int err; 1641 1642 err = ionic_set_attr_mac(lif, mac); 1643 if (err) 1644 return err; 1645 1646 err = ionic_get_attr_mac(lif, get_mac); 1647 if (err) 1648 return err; 1649 1650 /* To deal with older firmware that silently ignores the set attr mac: 1651 * doesn't actually change the mac and doesn't return an error, so we 1652 * do the get attr to verify whether or not the set actually happened 1653 */ 1654 if (!ether_addr_equal(get_mac, mac)) 1655 return 1; 1656 1657 return 0; 1658 } 1659 1660 static int ionic_set_mac_address(struct net_device *netdev, void *sa) 1661 { 1662 struct ionic_lif *lif = netdev_priv(netdev); 1663 struct sockaddr *addr = sa; 1664 u8 *mac; 1665 int err; 1666 1667 mac = (u8 *)addr->sa_data; 1668 if (ether_addr_equal(netdev->dev_addr, mac)) 1669 return 0; 1670 1671 err = ionic_program_mac(lif, mac); 1672 if (err < 0) 1673 return err; 1674 1675 if (err > 0) 1676 netdev_dbg(netdev, "%s: SET and GET ATTR Mac are not equal-due to old FW running\n", 1677 __func__); 1678 1679 err = eth_prepare_mac_addr_change(netdev, addr); 1680 if (err) 1681 return err; 1682 1683 if (!is_zero_ether_addr(netdev->dev_addr)) { 1684 netdev_info(netdev, "deleting mac addr %pM\n", 1685 netdev->dev_addr); 1686 ionic_lif_addr_del(netdev_priv(netdev), netdev->dev_addr); 1687 } 1688 1689 eth_commit_mac_addr_change(netdev, addr); 1690 netdev_info(netdev, "updating mac addr %pM\n", mac); 1691 1692 return ionic_lif_addr_add(netdev_priv(netdev), mac); 1693 } 1694 1695 void ionic_stop_queues_reconfig(struct ionic_lif *lif) 1696 { 1697 /* Stop and clean the queues before reconfiguration */ 1698 netif_device_detach(lif->netdev); 1699 ionic_stop_queues(lif); 1700 ionic_txrx_deinit(lif); 1701 } 1702 1703 static int ionic_start_queues_reconfig(struct ionic_lif *lif) 1704 { 1705 int err; 1706 1707 /* Re-init the queues after reconfiguration */ 1708 1709 /* The only way txrx_init can fail here is if communication 1710 * with FW is suddenly broken. There's not much we can do 1711 * at this point - error messages have already been printed, 1712 * so we can continue on and the user can eventually do a 1713 * DOWN and UP to try to reset and clear the issue. 1714 */ 1715 err = ionic_txrx_init(lif); 1716 ionic_link_status_check_request(lif, CAN_NOT_SLEEP); 1717 netif_device_attach(lif->netdev); 1718 1719 return err; 1720 } 1721 1722 static bool ionic_xdp_is_valid_mtu(struct ionic_lif *lif, u32 mtu, 1723 struct bpf_prog *xdp_prog) 1724 { 1725 if (!xdp_prog) 1726 return true; 1727 1728 if (mtu <= IONIC_XDP_MAX_LINEAR_MTU) 1729 return true; 1730 1731 if (xdp_prog->aux && xdp_prog->aux->xdp_has_frags) 1732 return true; 1733 1734 return false; 1735 } 1736 1737 static int ionic_change_mtu(struct net_device *netdev, int new_mtu) 1738 { 1739 struct ionic_lif *lif = netdev_priv(netdev); 1740 struct ionic_admin_ctx ctx = { 1741 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1742 .cmd.lif_setattr = { 1743 .opcode = IONIC_CMD_LIF_SETATTR, 1744 .index = cpu_to_le16(lif->index), 1745 .attr = IONIC_LIF_ATTR_MTU, 1746 .mtu = cpu_to_le32(new_mtu), 1747 }, 1748 }; 1749 struct bpf_prog *xdp_prog; 1750 int err; 1751 1752 xdp_prog = READ_ONCE(lif->xdp_prog); 1753 if (!ionic_xdp_is_valid_mtu(lif, new_mtu, xdp_prog)) 1754 return -EINVAL; 1755 1756 err = ionic_adminq_post_wait(lif, &ctx); 1757 if (err) 1758 return err; 1759 1760 /* if we're not running, nothing more to do */ 1761 if (!netif_running(netdev)) { 1762 WRITE_ONCE(netdev->mtu, new_mtu); 1763 return 0; 1764 } 1765 1766 mutex_lock(&lif->queue_lock); 1767 ionic_stop_queues_reconfig(lif); 1768 WRITE_ONCE(netdev->mtu, new_mtu); 1769 err = ionic_start_queues_reconfig(lif); 1770 mutex_unlock(&lif->queue_lock); 1771 1772 return err; 1773 } 1774 1775 static void ionic_tx_timeout_work(struct work_struct *ws) 1776 { 1777 struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work); 1778 int err; 1779 1780 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 1781 return; 1782 1783 /* if we were stopped before this scheduled job was launched, 1784 * don't bother the queues as they are already stopped. 1785 */ 1786 if (!netif_running(lif->netdev)) 1787 return; 1788 1789 mutex_lock(&lif->queue_lock); 1790 ionic_stop_queues_reconfig(lif); 1791 err = ionic_start_queues_reconfig(lif); 1792 mutex_unlock(&lif->queue_lock); 1793 1794 if (err) 1795 dev_err(lif->ionic->dev, "%s: Restarting queues failed\n", __func__); 1796 } 1797 1798 static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1799 { 1800 struct ionic_lif *lif = netdev_priv(netdev); 1801 1802 netdev_info(lif->netdev, "Tx Timeout triggered - txq %d\n", txqueue); 1803 schedule_work(&lif->tx_timeout_work); 1804 } 1805 1806 static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, 1807 u16 vid) 1808 { 1809 struct ionic_lif *lif = netdev_priv(netdev); 1810 int err; 1811 1812 err = ionic_lif_vlan_add(lif, vid); 1813 if (err) 1814 return err; 1815 1816 ionic_lif_rx_mode(lif); 1817 1818 return 0; 1819 } 1820 1821 static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, 1822 u16 vid) 1823 { 1824 struct ionic_lif *lif = netdev_priv(netdev); 1825 int err; 1826 1827 err = ionic_lif_vlan_del(lif, vid); 1828 if (err) 1829 return err; 1830 1831 ionic_lif_rx_mode(lif); 1832 1833 return 0; 1834 } 1835 1836 int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types, 1837 const u8 *key, const u32 *indir) 1838 { 1839 struct ionic_admin_ctx ctx = { 1840 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1841 .cmd.lif_setattr = { 1842 .opcode = IONIC_CMD_LIF_SETATTR, 1843 .attr = IONIC_LIF_ATTR_RSS, 1844 .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa), 1845 }, 1846 }; 1847 unsigned int i, tbl_sz; 1848 1849 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) { 1850 lif->rss_types = types; 1851 ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types); 1852 } 1853 1854 if (key) 1855 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE); 1856 1857 if (indir) { 1858 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1859 for (i = 0; i < tbl_sz; i++) 1860 lif->rss_ind_tbl[i] = indir[i]; 1861 } 1862 1863 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key, 1864 IONIC_RSS_HASH_KEY_SIZE); 1865 1866 return ionic_adminq_post_wait(lif, &ctx); 1867 } 1868 1869 static int ionic_lif_rss_init(struct ionic_lif *lif) 1870 { 1871 unsigned int tbl_sz; 1872 unsigned int i; 1873 1874 lif->rss_types = IONIC_RSS_TYPE_IPV4 | 1875 IONIC_RSS_TYPE_IPV4_TCP | 1876 IONIC_RSS_TYPE_IPV4_UDP | 1877 IONIC_RSS_TYPE_IPV6 | 1878 IONIC_RSS_TYPE_IPV6_TCP | 1879 IONIC_RSS_TYPE_IPV6_UDP; 1880 1881 /* Fill indirection table with 'default' values */ 1882 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1883 for (i = 0; i < tbl_sz; i++) 1884 lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs); 1885 1886 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1887 } 1888 1889 static void ionic_lif_rss_deinit(struct ionic_lif *lif) 1890 { 1891 int tbl_sz; 1892 1893 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1894 memset(lif->rss_ind_tbl, 0, tbl_sz); 1895 memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE); 1896 1897 ionic_lif_rss_config(lif, 0x0, NULL, NULL); 1898 } 1899 1900 static void ionic_lif_quiesce(struct ionic_lif *lif) 1901 { 1902 struct ionic_admin_ctx ctx = { 1903 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1904 .cmd.lif_setattr = { 1905 .opcode = IONIC_CMD_LIF_SETATTR, 1906 .index = cpu_to_le16(lif->index), 1907 .attr = IONIC_LIF_ATTR_STATE, 1908 .state = IONIC_LIF_QUIESCE, 1909 }, 1910 }; 1911 int err; 1912 1913 err = ionic_adminq_post_wait(lif, &ctx); 1914 if (err) 1915 netdev_dbg(lif->netdev, "lif quiesce failed %d\n", err); 1916 } 1917 1918 static void ionic_txrx_disable(struct ionic_lif *lif) 1919 { 1920 unsigned int i; 1921 int err = 0; 1922 1923 if (lif->txqcqs) { 1924 for (i = 0; i < lif->nxqs; i++) 1925 err = ionic_qcq_disable(lif, lif->txqcqs[i], err); 1926 } 1927 1928 if (lif->hwstamp_txq) 1929 err = ionic_qcq_disable(lif, lif->hwstamp_txq, err); 1930 1931 if (lif->rxqcqs) { 1932 for (i = 0; i < lif->nxqs; i++) 1933 err = ionic_qcq_disable(lif, lif->rxqcqs[i], err); 1934 } 1935 1936 if (lif->hwstamp_rxq) 1937 err = ionic_qcq_disable(lif, lif->hwstamp_rxq, err); 1938 1939 ionic_lif_quiesce(lif); 1940 } 1941 1942 static void ionic_txrx_deinit(struct ionic_lif *lif) 1943 { 1944 unsigned int i; 1945 1946 if (lif->txqcqs) { 1947 for (i = 0; i < lif->nxqs && lif->txqcqs[i]; i++) { 1948 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 1949 ionic_tx_flush(&lif->txqcqs[i]->cq); 1950 ionic_tx_empty(&lif->txqcqs[i]->q); 1951 } 1952 } 1953 1954 if (lif->rxqcqs) { 1955 for (i = 0; i < lif->nxqs && lif->rxqcqs[i]; i++) { 1956 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 1957 ionic_rx_empty(&lif->rxqcqs[i]->q); 1958 } 1959 } 1960 lif->rx_mode = 0; 1961 1962 if (lif->hwstamp_txq) { 1963 ionic_lif_qcq_deinit(lif, lif->hwstamp_txq); 1964 ionic_tx_flush(&lif->hwstamp_txq->cq); 1965 ionic_tx_empty(&lif->hwstamp_txq->q); 1966 } 1967 1968 if (lif->hwstamp_rxq) { 1969 ionic_lif_qcq_deinit(lif, lif->hwstamp_rxq); 1970 ionic_rx_empty(&lif->hwstamp_rxq->q); 1971 } 1972 } 1973 1974 void ionic_txrx_free(struct ionic_lif *lif) 1975 { 1976 unsigned int i; 1977 1978 if (lif->txqcqs) { 1979 for (i = 0; i < lif->ionic->ntxqs_per_lif && lif->txqcqs[i]; i++) { 1980 ionic_qcq_free(lif, lif->txqcqs[i]); 1981 devm_kfree(lif->ionic->dev, lif->txqcqs[i]); 1982 lif->txqcqs[i] = NULL; 1983 } 1984 } 1985 1986 if (lif->rxqcqs) { 1987 for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) { 1988 ionic_qcq_free(lif, lif->rxqcqs[i]); 1989 devm_kfree(lif->ionic->dev, lif->rxqcqs[i]); 1990 lif->rxqcqs[i] = NULL; 1991 } 1992 } 1993 1994 if (lif->hwstamp_txq) { 1995 ionic_qcq_free(lif, lif->hwstamp_txq); 1996 devm_kfree(lif->ionic->dev, lif->hwstamp_txq); 1997 lif->hwstamp_txq = NULL; 1998 } 1999 2000 if (lif->hwstamp_rxq) { 2001 ionic_qcq_free(lif, lif->hwstamp_rxq); 2002 devm_kfree(lif->ionic->dev, lif->hwstamp_rxq); 2003 lif->hwstamp_rxq = NULL; 2004 } 2005 } 2006 2007 static int ionic_txrx_alloc(struct ionic_lif *lif) 2008 { 2009 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz; 2010 unsigned int flags, i; 2011 int err = 0; 2012 2013 num_desc = lif->ntxq_descs; 2014 desc_sz = sizeof(struct ionic_txq_desc); 2015 comp_sz = sizeof(struct ionic_txq_comp); 2016 2017 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 2018 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 2019 sizeof(struct ionic_txq_sg_desc_v1)) 2020 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 2021 else 2022 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 2023 2024 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 2025 2026 if (test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state)) 2027 flags |= IONIC_QCQ_F_CMB_RINGS; 2028 2029 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 2030 flags |= IONIC_QCQ_F_INTR; 2031 2032 for (i = 0; i < lif->nxqs; i++) { 2033 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 2034 num_desc, desc_sz, comp_sz, sg_desc_sz, 2035 sizeof(struct ionic_tx_desc_info), 2036 lif->kern_pid, &lif->txqcqs[i]); 2037 if (err) 2038 goto err_out; 2039 2040 if (flags & IONIC_QCQ_F_INTR) { 2041 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2042 lif->txqcqs[i]->intr.index, 2043 lif->tx_coalesce_hw); 2044 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 2045 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 2046 } 2047 2048 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 2049 } 2050 2051 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG | IONIC_QCQ_F_INTR; 2052 2053 if (test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state)) 2054 flags |= IONIC_QCQ_F_CMB_RINGS; 2055 2056 num_desc = lif->nrxq_descs; 2057 desc_sz = sizeof(struct ionic_rxq_desc); 2058 comp_sz = sizeof(struct ionic_rxq_comp); 2059 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 2060 2061 if (lif->rxq_features & IONIC_Q_F_2X_CQ_DESC) 2062 comp_sz *= 2; 2063 2064 for (i = 0; i < lif->nxqs; i++) { 2065 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 2066 num_desc, desc_sz, comp_sz, sg_desc_sz, 2067 sizeof(struct ionic_rx_desc_info), 2068 lif->kern_pid, &lif->rxqcqs[i]); 2069 if (err) 2070 goto err_out; 2071 2072 lif->rxqcqs[i]->q.features = lif->rxq_features; 2073 2074 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2075 lif->rxqcqs[i]->intr.index, 2076 lif->rx_coalesce_hw); 2077 if (test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state)) 2078 lif->rxqcqs[i]->intr.dim_coal_hw = lif->rx_coalesce_hw; 2079 2080 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 2081 ionic_link_qcq_interrupts(lif->rxqcqs[i], 2082 lif->txqcqs[i]); 2083 2084 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 2085 } 2086 2087 return 0; 2088 2089 err_out: 2090 ionic_txrx_free(lif); 2091 2092 return err; 2093 } 2094 2095 static int ionic_txrx_init(struct ionic_lif *lif) 2096 { 2097 unsigned int i; 2098 int err; 2099 2100 for (i = 0; i < lif->nxqs; i++) { 2101 err = ionic_lif_txq_init(lif, lif->txqcqs[i]); 2102 if (err) 2103 goto err_out; 2104 2105 err = ionic_lif_rxq_init(lif, lif->rxqcqs[i]); 2106 if (err) { 2107 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 2108 goto err_out; 2109 } 2110 } 2111 2112 if (lif->netdev->features & NETIF_F_RXHASH) 2113 ionic_lif_rss_init(lif); 2114 2115 ionic_lif_rx_mode(lif); 2116 2117 return 0; 2118 2119 err_out: 2120 while (i--) { 2121 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 2122 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 2123 } 2124 2125 return err; 2126 } 2127 2128 static int ionic_txrx_enable(struct ionic_lif *lif) 2129 { 2130 int derr = 0; 2131 int i, err; 2132 2133 err = ionic_xdp_queues_config(lif); 2134 if (err) 2135 return err; 2136 2137 for (i = 0; i < lif->nxqs; i++) { 2138 if (!(lif->rxqcqs[i] && lif->txqcqs[i])) { 2139 dev_err(lif->ionic->dev, "%s: bad qcq %d\n", __func__, i); 2140 err = -ENXIO; 2141 goto err_out; 2142 } 2143 2144 ionic_rx_fill(&lif->rxqcqs[i]->q); 2145 err = ionic_qcq_enable(lif->rxqcqs[i]); 2146 if (err) 2147 goto err_out; 2148 2149 err = ionic_qcq_enable(lif->txqcqs[i]); 2150 if (err) { 2151 derr = ionic_qcq_disable(lif, lif->rxqcqs[i], err); 2152 goto err_out; 2153 } 2154 } 2155 2156 if (lif->hwstamp_rxq) { 2157 ionic_rx_fill(&lif->hwstamp_rxq->q); 2158 err = ionic_qcq_enable(lif->hwstamp_rxq); 2159 if (err) 2160 goto err_out_hwstamp_rx; 2161 } 2162 2163 if (lif->hwstamp_txq) { 2164 err = ionic_qcq_enable(lif->hwstamp_txq); 2165 if (err) 2166 goto err_out_hwstamp_tx; 2167 } 2168 2169 return 0; 2170 2171 err_out_hwstamp_tx: 2172 if (lif->hwstamp_rxq) 2173 derr = ionic_qcq_disable(lif, lif->hwstamp_rxq, derr); 2174 err_out_hwstamp_rx: 2175 i = lif->nxqs; 2176 err_out: 2177 while (i--) { 2178 derr = ionic_qcq_disable(lif, lif->txqcqs[i], derr); 2179 derr = ionic_qcq_disable(lif, lif->rxqcqs[i], derr); 2180 } 2181 2182 ionic_xdp_queues_config(lif); 2183 2184 return err; 2185 } 2186 2187 static int ionic_start_queues(struct ionic_lif *lif) 2188 { 2189 int err; 2190 2191 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) 2192 return -EIO; 2193 2194 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2195 return -EBUSY; 2196 2197 if (test_and_set_bit(IONIC_LIF_F_UP, lif->state)) 2198 return 0; 2199 2200 err = ionic_txrx_enable(lif); 2201 if (err) { 2202 clear_bit(IONIC_LIF_F_UP, lif->state); 2203 return err; 2204 } 2205 netif_tx_wake_all_queues(lif->netdev); 2206 2207 return 0; 2208 } 2209 2210 static int ionic_open(struct net_device *netdev) 2211 { 2212 struct ionic_lif *lif = netdev_priv(netdev); 2213 int err; 2214 2215 /* If recovering from a broken state, clear the bit and we'll try again */ 2216 if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state)) 2217 netdev_info(netdev, "clearing broken state\n"); 2218 2219 mutex_lock(&lif->queue_lock); 2220 2221 err = ionic_txrx_alloc(lif); 2222 if (err) 2223 goto err_unlock; 2224 2225 err = ionic_txrx_init(lif); 2226 if (err) 2227 goto err_txrx_free; 2228 2229 err = netif_set_real_num_tx_queues(netdev, lif->nxqs); 2230 if (err) 2231 goto err_txrx_deinit; 2232 2233 err = netif_set_real_num_rx_queues(netdev, lif->nxqs); 2234 if (err) 2235 goto err_txrx_deinit; 2236 2237 /* don't start the queues until we have link */ 2238 if (netif_carrier_ok(netdev)) { 2239 err = ionic_start_queues(lif); 2240 if (err) 2241 goto err_txrx_deinit; 2242 } 2243 2244 /* If hardware timestamping is enabled, but the queues were freed by 2245 * ionic_stop, those need to be reallocated and initialized, too. 2246 */ 2247 ionic_lif_hwstamp_recreate_queues(lif); 2248 2249 mutex_unlock(&lif->queue_lock); 2250 2251 return 0; 2252 2253 err_txrx_deinit: 2254 ionic_txrx_deinit(lif); 2255 err_txrx_free: 2256 ionic_txrx_free(lif); 2257 err_unlock: 2258 mutex_unlock(&lif->queue_lock); 2259 return err; 2260 } 2261 2262 static void ionic_stop_queues(struct ionic_lif *lif) 2263 { 2264 if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state)) 2265 return; 2266 2267 netif_tx_disable(lif->netdev); 2268 ionic_txrx_disable(lif); 2269 } 2270 2271 static int ionic_stop(struct net_device *netdev) 2272 { 2273 struct ionic_lif *lif = netdev_priv(netdev); 2274 2275 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2276 return 0; 2277 2278 mutex_lock(&lif->queue_lock); 2279 ionic_stop_queues(lif); 2280 ionic_txrx_deinit(lif); 2281 ionic_txrx_free(lif); 2282 mutex_unlock(&lif->queue_lock); 2283 2284 return 0; 2285 } 2286 2287 static int ionic_eth_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 2288 { 2289 struct ionic_lif *lif = netdev_priv(netdev); 2290 2291 switch (cmd) { 2292 case SIOCSHWTSTAMP: 2293 return ionic_lif_hwstamp_set(lif, ifr); 2294 case SIOCGHWTSTAMP: 2295 return ionic_lif_hwstamp_get(lif, ifr); 2296 default: 2297 return -EOPNOTSUPP; 2298 } 2299 } 2300 2301 static int ionic_get_vf_config(struct net_device *netdev, 2302 int vf, struct ifla_vf_info *ivf) 2303 { 2304 struct ionic_lif *lif = netdev_priv(netdev); 2305 struct ionic *ionic = lif->ionic; 2306 int ret = 0; 2307 2308 if (!netif_device_present(netdev)) 2309 return -EBUSY; 2310 2311 down_read(&ionic->vf_op_lock); 2312 2313 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2314 ret = -EINVAL; 2315 } else { 2316 struct ionic_vf *vfdata = &ionic->vfs[vf]; 2317 2318 ivf->vf = vf; 2319 ivf->qos = 0; 2320 ivf->vlan = le16_to_cpu(vfdata->vlanid); 2321 ivf->spoofchk = vfdata->spoofchk; 2322 ivf->linkstate = vfdata->linkstate; 2323 ivf->max_tx_rate = le32_to_cpu(vfdata->maxrate); 2324 ivf->trusted = vfdata->trusted; 2325 ether_addr_copy(ivf->mac, vfdata->macaddr); 2326 } 2327 2328 up_read(&ionic->vf_op_lock); 2329 return ret; 2330 } 2331 2332 static int ionic_get_vf_stats(struct net_device *netdev, int vf, 2333 struct ifla_vf_stats *vf_stats) 2334 { 2335 struct ionic_lif *lif = netdev_priv(netdev); 2336 struct ionic *ionic = lif->ionic; 2337 struct ionic_lif_stats *vs; 2338 int ret = 0; 2339 2340 if (!netif_device_present(netdev)) 2341 return -EBUSY; 2342 2343 down_read(&ionic->vf_op_lock); 2344 2345 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2346 ret = -EINVAL; 2347 } else { 2348 memset(vf_stats, 0, sizeof(*vf_stats)); 2349 vs = &ionic->vfs[vf].stats; 2350 2351 vf_stats->rx_packets = le64_to_cpu(vs->rx_ucast_packets); 2352 vf_stats->tx_packets = le64_to_cpu(vs->tx_ucast_packets); 2353 vf_stats->rx_bytes = le64_to_cpu(vs->rx_ucast_bytes); 2354 vf_stats->tx_bytes = le64_to_cpu(vs->tx_ucast_bytes); 2355 vf_stats->broadcast = le64_to_cpu(vs->rx_bcast_packets); 2356 vf_stats->multicast = le64_to_cpu(vs->rx_mcast_packets); 2357 vf_stats->rx_dropped = le64_to_cpu(vs->rx_ucast_drop_packets) + 2358 le64_to_cpu(vs->rx_mcast_drop_packets) + 2359 le64_to_cpu(vs->rx_bcast_drop_packets); 2360 vf_stats->tx_dropped = le64_to_cpu(vs->tx_ucast_drop_packets) + 2361 le64_to_cpu(vs->tx_mcast_drop_packets) + 2362 le64_to_cpu(vs->tx_bcast_drop_packets); 2363 } 2364 2365 up_read(&ionic->vf_op_lock); 2366 return ret; 2367 } 2368 2369 static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2370 { 2371 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_MAC }; 2372 struct ionic_lif *lif = netdev_priv(netdev); 2373 struct ionic *ionic = lif->ionic; 2374 int ret; 2375 2376 if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac))) 2377 return -EINVAL; 2378 2379 if (!netif_device_present(netdev)) 2380 return -EBUSY; 2381 2382 down_write(&ionic->vf_op_lock); 2383 2384 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2385 ret = -EINVAL; 2386 } else { 2387 ether_addr_copy(vfc.macaddr, mac); 2388 dev_dbg(ionic->dev, "%s: vf %d macaddr %pM\n", 2389 __func__, vf, vfc.macaddr); 2390 2391 ret = ionic_set_vf_config(ionic, vf, &vfc); 2392 if (!ret) 2393 ether_addr_copy(ionic->vfs[vf].macaddr, mac); 2394 } 2395 2396 up_write(&ionic->vf_op_lock); 2397 return ret; 2398 } 2399 2400 static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 2401 u8 qos, __be16 proto) 2402 { 2403 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_VLAN }; 2404 struct ionic_lif *lif = netdev_priv(netdev); 2405 struct ionic *ionic = lif->ionic; 2406 int ret; 2407 2408 /* until someday when we support qos */ 2409 if (qos) 2410 return -EINVAL; 2411 2412 if (vlan > 4095) 2413 return -EINVAL; 2414 2415 if (proto != htons(ETH_P_8021Q)) 2416 return -EPROTONOSUPPORT; 2417 2418 if (!netif_device_present(netdev)) 2419 return -EBUSY; 2420 2421 down_write(&ionic->vf_op_lock); 2422 2423 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2424 ret = -EINVAL; 2425 } else { 2426 vfc.vlanid = cpu_to_le16(vlan); 2427 dev_dbg(ionic->dev, "%s: vf %d vlan %d\n", 2428 __func__, vf, le16_to_cpu(vfc.vlanid)); 2429 2430 ret = ionic_set_vf_config(ionic, vf, &vfc); 2431 if (!ret) 2432 ionic->vfs[vf].vlanid = cpu_to_le16(vlan); 2433 } 2434 2435 up_write(&ionic->vf_op_lock); 2436 return ret; 2437 } 2438 2439 static int ionic_set_vf_rate(struct net_device *netdev, int vf, 2440 int tx_min, int tx_max) 2441 { 2442 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_RATE }; 2443 struct ionic_lif *lif = netdev_priv(netdev); 2444 struct ionic *ionic = lif->ionic; 2445 int ret; 2446 2447 /* setting the min just seems silly */ 2448 if (tx_min) 2449 return -EINVAL; 2450 2451 if (!netif_device_present(netdev)) 2452 return -EBUSY; 2453 2454 down_write(&ionic->vf_op_lock); 2455 2456 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2457 ret = -EINVAL; 2458 } else { 2459 vfc.maxrate = cpu_to_le32(tx_max); 2460 dev_dbg(ionic->dev, "%s: vf %d maxrate %d\n", 2461 __func__, vf, le32_to_cpu(vfc.maxrate)); 2462 2463 ret = ionic_set_vf_config(ionic, vf, &vfc); 2464 if (!ret) 2465 ionic->vfs[vf].maxrate = cpu_to_le32(tx_max); 2466 } 2467 2468 up_write(&ionic->vf_op_lock); 2469 return ret; 2470 } 2471 2472 static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set) 2473 { 2474 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_SPOOFCHK }; 2475 struct ionic_lif *lif = netdev_priv(netdev); 2476 struct ionic *ionic = lif->ionic; 2477 int ret; 2478 2479 if (!netif_device_present(netdev)) 2480 return -EBUSY; 2481 2482 down_write(&ionic->vf_op_lock); 2483 2484 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2485 ret = -EINVAL; 2486 } else { 2487 vfc.spoofchk = set; 2488 dev_dbg(ionic->dev, "%s: vf %d spoof %d\n", 2489 __func__, vf, vfc.spoofchk); 2490 2491 ret = ionic_set_vf_config(ionic, vf, &vfc); 2492 if (!ret) 2493 ionic->vfs[vf].spoofchk = set; 2494 } 2495 2496 up_write(&ionic->vf_op_lock); 2497 return ret; 2498 } 2499 2500 static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set) 2501 { 2502 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_TRUST }; 2503 struct ionic_lif *lif = netdev_priv(netdev); 2504 struct ionic *ionic = lif->ionic; 2505 int ret; 2506 2507 if (!netif_device_present(netdev)) 2508 return -EBUSY; 2509 2510 down_write(&ionic->vf_op_lock); 2511 2512 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2513 ret = -EINVAL; 2514 } else { 2515 vfc.trust = set; 2516 dev_dbg(ionic->dev, "%s: vf %d trust %d\n", 2517 __func__, vf, vfc.trust); 2518 2519 ret = ionic_set_vf_config(ionic, vf, &vfc); 2520 if (!ret) 2521 ionic->vfs[vf].trusted = set; 2522 } 2523 2524 up_write(&ionic->vf_op_lock); 2525 return ret; 2526 } 2527 2528 static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set) 2529 { 2530 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_LINKSTATE }; 2531 struct ionic_lif *lif = netdev_priv(netdev); 2532 struct ionic *ionic = lif->ionic; 2533 u8 vfls; 2534 int ret; 2535 2536 switch (set) { 2537 case IFLA_VF_LINK_STATE_ENABLE: 2538 vfls = IONIC_VF_LINK_STATUS_UP; 2539 break; 2540 case IFLA_VF_LINK_STATE_DISABLE: 2541 vfls = IONIC_VF_LINK_STATUS_DOWN; 2542 break; 2543 case IFLA_VF_LINK_STATE_AUTO: 2544 vfls = IONIC_VF_LINK_STATUS_AUTO; 2545 break; 2546 default: 2547 return -EINVAL; 2548 } 2549 2550 if (!netif_device_present(netdev)) 2551 return -EBUSY; 2552 2553 down_write(&ionic->vf_op_lock); 2554 2555 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2556 ret = -EINVAL; 2557 } else { 2558 vfc.linkstate = vfls; 2559 dev_dbg(ionic->dev, "%s: vf %d linkstate %d\n", 2560 __func__, vf, vfc.linkstate); 2561 2562 ret = ionic_set_vf_config(ionic, vf, &vfc); 2563 if (!ret) 2564 ionic->vfs[vf].linkstate = set; 2565 } 2566 2567 up_write(&ionic->vf_op_lock); 2568 return ret; 2569 } 2570 2571 static void ionic_vf_attr_replay(struct ionic_lif *lif) 2572 { 2573 struct ionic_vf_setattr_cmd vfc = { }; 2574 struct ionic *ionic = lif->ionic; 2575 struct ionic_vf *v; 2576 int i; 2577 2578 if (!ionic->vfs) 2579 return; 2580 2581 down_read(&ionic->vf_op_lock); 2582 2583 for (i = 0; i < ionic->num_vfs; i++) { 2584 v = &ionic->vfs[i]; 2585 2586 if (v->stats_pa) { 2587 vfc.attr = IONIC_VF_ATTR_STATSADDR; 2588 vfc.stats_pa = cpu_to_le64(v->stats_pa); 2589 ionic_set_vf_config(ionic, i, &vfc); 2590 vfc.stats_pa = 0; 2591 } 2592 2593 if (!is_zero_ether_addr(v->macaddr)) { 2594 vfc.attr = IONIC_VF_ATTR_MAC; 2595 ether_addr_copy(vfc.macaddr, v->macaddr); 2596 ionic_set_vf_config(ionic, i, &vfc); 2597 eth_zero_addr(vfc.macaddr); 2598 } 2599 2600 if (v->vlanid) { 2601 vfc.attr = IONIC_VF_ATTR_VLAN; 2602 vfc.vlanid = v->vlanid; 2603 ionic_set_vf_config(ionic, i, &vfc); 2604 vfc.vlanid = 0; 2605 } 2606 2607 if (v->maxrate) { 2608 vfc.attr = IONIC_VF_ATTR_RATE; 2609 vfc.maxrate = v->maxrate; 2610 ionic_set_vf_config(ionic, i, &vfc); 2611 vfc.maxrate = 0; 2612 } 2613 2614 if (v->spoofchk) { 2615 vfc.attr = IONIC_VF_ATTR_SPOOFCHK; 2616 vfc.spoofchk = v->spoofchk; 2617 ionic_set_vf_config(ionic, i, &vfc); 2618 vfc.spoofchk = 0; 2619 } 2620 2621 if (v->trusted) { 2622 vfc.attr = IONIC_VF_ATTR_TRUST; 2623 vfc.trust = v->trusted; 2624 ionic_set_vf_config(ionic, i, &vfc); 2625 vfc.trust = 0; 2626 } 2627 2628 if (v->linkstate) { 2629 vfc.attr = IONIC_VF_ATTR_LINKSTATE; 2630 vfc.linkstate = v->linkstate; 2631 ionic_set_vf_config(ionic, i, &vfc); 2632 vfc.linkstate = 0; 2633 } 2634 } 2635 2636 up_read(&ionic->vf_op_lock); 2637 2638 ionic_vf_start(ionic); 2639 } 2640 2641 static void ionic_xdp_unregister_rxq_info(struct ionic_queue *q) 2642 { 2643 struct xdp_rxq_info *xi; 2644 2645 if (!q->xdp_rxq_info) 2646 return; 2647 2648 xi = q->xdp_rxq_info; 2649 q->xdp_rxq_info = NULL; 2650 2651 xdp_rxq_info_unreg(xi); 2652 kfree(xi); 2653 } 2654 2655 static int ionic_xdp_register_rxq_info(struct ionic_queue *q, unsigned int napi_id) 2656 { 2657 struct xdp_rxq_info *rxq_info; 2658 int err; 2659 2660 rxq_info = kzalloc(sizeof(*rxq_info), GFP_KERNEL); 2661 if (!rxq_info) 2662 return -ENOMEM; 2663 2664 err = xdp_rxq_info_reg(rxq_info, q->lif->netdev, q->index, napi_id); 2665 if (err) { 2666 dev_err(q->dev, "Queue %d xdp_rxq_info_reg failed, err %d\n", 2667 q->index, err); 2668 goto err_out; 2669 } 2670 2671 err = xdp_rxq_info_reg_mem_model(rxq_info, MEM_TYPE_PAGE_ORDER0, NULL); 2672 if (err) { 2673 dev_err(q->dev, "Queue %d xdp_rxq_info_reg_mem_model failed, err %d\n", 2674 q->index, err); 2675 xdp_rxq_info_unreg(rxq_info); 2676 goto err_out; 2677 } 2678 2679 q->xdp_rxq_info = rxq_info; 2680 2681 return 0; 2682 2683 err_out: 2684 kfree(rxq_info); 2685 return err; 2686 } 2687 2688 static int ionic_xdp_queues_config(struct ionic_lif *lif) 2689 { 2690 unsigned int i; 2691 int err; 2692 2693 if (!lif->rxqcqs) 2694 return 0; 2695 2696 /* There's no need to rework memory if not going to/from NULL program. 2697 * If there is no lif->xdp_prog, there should also be no q.xdp_rxq_info 2698 * This way we don't need to keep an *xdp_prog in every queue struct. 2699 */ 2700 if (!lif->xdp_prog == !lif->rxqcqs[0]->q.xdp_rxq_info) 2701 return 0; 2702 2703 for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) { 2704 struct ionic_queue *q = &lif->rxqcqs[i]->q; 2705 2706 if (q->xdp_rxq_info) { 2707 ionic_xdp_unregister_rxq_info(q); 2708 continue; 2709 } 2710 2711 err = ionic_xdp_register_rxq_info(q, lif->rxqcqs[i]->napi.napi_id); 2712 if (err) { 2713 dev_err(lif->ionic->dev, "failed to register RX queue %d info for XDP, err %d\n", 2714 i, err); 2715 goto err_out; 2716 } 2717 } 2718 2719 return 0; 2720 2721 err_out: 2722 for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) 2723 ionic_xdp_unregister_rxq_info(&lif->rxqcqs[i]->q); 2724 2725 return err; 2726 } 2727 2728 static int ionic_xdp_config(struct net_device *netdev, struct netdev_bpf *bpf) 2729 { 2730 struct ionic_lif *lif = netdev_priv(netdev); 2731 struct bpf_prog *old_prog; 2732 u32 maxfs; 2733 2734 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) { 2735 #define XDP_ERR_SPLIT "XDP not available with split Tx/Rx interrupts" 2736 NL_SET_ERR_MSG_MOD(bpf->extack, XDP_ERR_SPLIT); 2737 netdev_info(lif->netdev, XDP_ERR_SPLIT); 2738 return -EOPNOTSUPP; 2739 } 2740 2741 if (!ionic_xdp_is_valid_mtu(lif, netdev->mtu, bpf->prog)) { 2742 #define XDP_ERR_MTU "MTU is too large for XDP without frags support" 2743 NL_SET_ERR_MSG_MOD(bpf->extack, XDP_ERR_MTU); 2744 netdev_info(lif->netdev, XDP_ERR_MTU); 2745 return -EINVAL; 2746 } 2747 2748 maxfs = __le32_to_cpu(lif->identity->eth.max_frame_size) - VLAN_ETH_HLEN; 2749 if (bpf->prog && !(bpf->prog->aux && bpf->prog->aux->xdp_has_frags)) 2750 maxfs = min_t(u32, maxfs, IONIC_XDP_MAX_LINEAR_MTU); 2751 netdev->max_mtu = maxfs; 2752 2753 if (!netif_running(netdev)) { 2754 old_prog = xchg(&lif->xdp_prog, bpf->prog); 2755 } else { 2756 mutex_lock(&lif->queue_lock); 2757 ionic_stop_queues_reconfig(lif); 2758 old_prog = xchg(&lif->xdp_prog, bpf->prog); 2759 ionic_start_queues_reconfig(lif); 2760 mutex_unlock(&lif->queue_lock); 2761 } 2762 2763 if (old_prog) 2764 bpf_prog_put(old_prog); 2765 2766 return 0; 2767 } 2768 2769 static int ionic_xdp(struct net_device *netdev, struct netdev_bpf *bpf) 2770 { 2771 switch (bpf->command) { 2772 case XDP_SETUP_PROG: 2773 return ionic_xdp_config(netdev, bpf); 2774 default: 2775 return -EINVAL; 2776 } 2777 } 2778 2779 static const struct net_device_ops ionic_netdev_ops = { 2780 .ndo_open = ionic_open, 2781 .ndo_stop = ionic_stop, 2782 .ndo_eth_ioctl = ionic_eth_ioctl, 2783 .ndo_start_xmit = ionic_start_xmit, 2784 .ndo_bpf = ionic_xdp, 2785 .ndo_xdp_xmit = ionic_xdp_xmit, 2786 .ndo_get_stats64 = ionic_get_stats64, 2787 .ndo_set_rx_mode = ionic_ndo_set_rx_mode, 2788 .ndo_set_features = ionic_set_features, 2789 .ndo_set_mac_address = ionic_set_mac_address, 2790 .ndo_validate_addr = eth_validate_addr, 2791 .ndo_tx_timeout = ionic_tx_timeout, 2792 .ndo_change_mtu = ionic_change_mtu, 2793 .ndo_vlan_rx_add_vid = ionic_vlan_rx_add_vid, 2794 .ndo_vlan_rx_kill_vid = ionic_vlan_rx_kill_vid, 2795 .ndo_set_vf_vlan = ionic_set_vf_vlan, 2796 .ndo_set_vf_trust = ionic_set_vf_trust, 2797 .ndo_set_vf_mac = ionic_set_vf_mac, 2798 .ndo_set_vf_rate = ionic_set_vf_rate, 2799 .ndo_set_vf_spoofchk = ionic_set_vf_spoofchk, 2800 .ndo_get_vf_config = ionic_get_vf_config, 2801 .ndo_set_vf_link_state = ionic_set_vf_link_state, 2802 .ndo_get_vf_stats = ionic_get_vf_stats, 2803 }; 2804 2805 static int ionic_cmb_reconfig(struct ionic_lif *lif, 2806 struct ionic_queue_params *qparam) 2807 { 2808 struct ionic_queue_params start_qparams; 2809 int err = 0; 2810 2811 /* When changing CMB queue parameters, we're using limited 2812 * on-device memory and don't have extra memory to use for 2813 * duplicate allocations, so we free it all first then 2814 * re-allocate with the new parameters. 2815 */ 2816 2817 /* Checkpoint for possible unwind */ 2818 ionic_init_queue_params(lif, &start_qparams); 2819 2820 /* Stop and free the queues */ 2821 ionic_stop_queues_reconfig(lif); 2822 ionic_txrx_free(lif); 2823 2824 /* Set up new qparams */ 2825 ionic_set_queue_params(lif, qparam); 2826 2827 if (netif_running(lif->netdev)) { 2828 /* Alloc and start the new configuration */ 2829 err = ionic_txrx_alloc(lif); 2830 if (err) { 2831 dev_warn(lif->ionic->dev, 2832 "CMB reconfig failed, restoring values: %d\n", err); 2833 2834 /* Back out the changes */ 2835 ionic_set_queue_params(lif, &start_qparams); 2836 err = ionic_txrx_alloc(lif); 2837 if (err) { 2838 dev_err(lif->ionic->dev, 2839 "CMB restore failed: %d\n", err); 2840 goto err_out; 2841 } 2842 } 2843 2844 err = ionic_start_queues_reconfig(lif); 2845 if (err) { 2846 dev_err(lif->ionic->dev, 2847 "CMB reconfig failed: %d\n", err); 2848 goto err_out; 2849 } 2850 } 2851 2852 err_out: 2853 /* This was detached in ionic_stop_queues_reconfig() */ 2854 netif_device_attach(lif->netdev); 2855 2856 return err; 2857 } 2858 2859 static void ionic_swap_queues(struct ionic_qcq *a, struct ionic_qcq *b) 2860 { 2861 /* only swapping the queues, not the napi, flags, or other stuff */ 2862 swap(a->q.features, b->q.features); 2863 swap(a->q.num_descs, b->q.num_descs); 2864 swap(a->q.desc_size, b->q.desc_size); 2865 swap(a->q.base, b->q.base); 2866 swap(a->q.base_pa, b->q.base_pa); 2867 swap(a->q.info, b->q.info); 2868 swap(a->q.xdp_rxq_info, b->q.xdp_rxq_info); 2869 swap(a->q.partner, b->q.partner); 2870 swap(a->q_base, b->q_base); 2871 swap(a->q_base_pa, b->q_base_pa); 2872 swap(a->q_size, b->q_size); 2873 2874 swap(a->q.sg_desc_size, b->q.sg_desc_size); 2875 swap(a->q.sg_base, b->q.sg_base); 2876 swap(a->q.sg_base_pa, b->q.sg_base_pa); 2877 swap(a->sg_base, b->sg_base); 2878 swap(a->sg_base_pa, b->sg_base_pa); 2879 swap(a->sg_size, b->sg_size); 2880 2881 swap(a->cq.num_descs, b->cq.num_descs); 2882 swap(a->cq.desc_size, b->cq.desc_size); 2883 swap(a->cq.base, b->cq.base); 2884 swap(a->cq.base_pa, b->cq.base_pa); 2885 swap(a->cq_base, b->cq_base); 2886 swap(a->cq_base_pa, b->cq_base_pa); 2887 swap(a->cq_size, b->cq_size); 2888 2889 ionic_debugfs_del_qcq(a); 2890 ionic_debugfs_add_qcq(a->q.lif, a); 2891 } 2892 2893 int ionic_reconfigure_queues(struct ionic_lif *lif, 2894 struct ionic_queue_params *qparam) 2895 { 2896 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz; 2897 struct ionic_qcq **tx_qcqs = NULL; 2898 struct ionic_qcq **rx_qcqs = NULL; 2899 unsigned int flags, i; 2900 int err = 0; 2901 2902 /* Are we changing q params while CMB is on */ 2903 if ((test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state) && qparam->cmb_tx) || 2904 (test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state) && qparam->cmb_rx)) 2905 return ionic_cmb_reconfig(lif, qparam); 2906 2907 /* allocate temporary qcq arrays to hold new queue structs */ 2908 if (qparam->nxqs != lif->nxqs || qparam->ntxq_descs != lif->ntxq_descs) { 2909 tx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->ntxqs_per_lif, 2910 sizeof(struct ionic_qcq *), GFP_KERNEL); 2911 if (!tx_qcqs) { 2912 err = -ENOMEM; 2913 goto err_out; 2914 } 2915 } 2916 if (qparam->nxqs != lif->nxqs || 2917 qparam->nrxq_descs != lif->nrxq_descs || 2918 qparam->rxq_features != lif->rxq_features) { 2919 rx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->nrxqs_per_lif, 2920 sizeof(struct ionic_qcq *), GFP_KERNEL); 2921 if (!rx_qcqs) { 2922 err = -ENOMEM; 2923 goto err_out; 2924 } 2925 } 2926 2927 /* allocate new desc_info and rings, but leave the interrupt setup 2928 * until later so as to not mess with the still-running queues 2929 */ 2930 if (tx_qcqs) { 2931 num_desc = qparam->ntxq_descs; 2932 desc_sz = sizeof(struct ionic_txq_desc); 2933 comp_sz = sizeof(struct ionic_txq_comp); 2934 2935 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 2936 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 2937 sizeof(struct ionic_txq_sg_desc_v1)) 2938 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 2939 else 2940 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 2941 2942 for (i = 0; i < qparam->nxqs; i++) { 2943 /* If missing, short placeholder qcq needed for swap */ 2944 if (!lif->txqcqs[i]) { 2945 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 2946 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 2947 4, desc_sz, comp_sz, sg_desc_sz, 2948 sizeof(struct ionic_tx_desc_info), 2949 lif->kern_pid, &lif->txqcqs[i]); 2950 if (err) 2951 goto err_out; 2952 } 2953 2954 flags = lif->txqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2955 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 2956 num_desc, desc_sz, comp_sz, sg_desc_sz, 2957 sizeof(struct ionic_tx_desc_info), 2958 lif->kern_pid, &tx_qcqs[i]); 2959 if (err) 2960 goto err_out; 2961 } 2962 } 2963 2964 if (rx_qcqs) { 2965 num_desc = qparam->nrxq_descs; 2966 desc_sz = sizeof(struct ionic_rxq_desc); 2967 comp_sz = sizeof(struct ionic_rxq_comp); 2968 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 2969 2970 if (qparam->rxq_features & IONIC_Q_F_2X_CQ_DESC) 2971 comp_sz *= 2; 2972 2973 for (i = 0; i < qparam->nxqs; i++) { 2974 /* If missing, short placeholder qcq needed for swap */ 2975 if (!lif->rxqcqs[i]) { 2976 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG; 2977 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 2978 4, desc_sz, comp_sz, sg_desc_sz, 2979 sizeof(struct ionic_rx_desc_info), 2980 lif->kern_pid, &lif->rxqcqs[i]); 2981 if (err) 2982 goto err_out; 2983 } 2984 2985 flags = lif->rxqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2986 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 2987 num_desc, desc_sz, comp_sz, sg_desc_sz, 2988 sizeof(struct ionic_rx_desc_info), 2989 lif->kern_pid, &rx_qcqs[i]); 2990 if (err) 2991 goto err_out; 2992 2993 rx_qcqs[i]->q.features = qparam->rxq_features; 2994 } 2995 } 2996 2997 /* stop and clean the queues */ 2998 ionic_stop_queues_reconfig(lif); 2999 3000 if (qparam->nxqs != lif->nxqs) { 3001 err = netif_set_real_num_tx_queues(lif->netdev, qparam->nxqs); 3002 if (err) 3003 goto err_out_reinit_unlock; 3004 err = netif_set_real_num_rx_queues(lif->netdev, qparam->nxqs); 3005 if (err) { 3006 netif_set_real_num_tx_queues(lif->netdev, lif->nxqs); 3007 goto err_out_reinit_unlock; 3008 } 3009 } 3010 3011 /* swap new desc_info and rings, keeping existing interrupt config */ 3012 if (tx_qcqs) { 3013 lif->ntxq_descs = qparam->ntxq_descs; 3014 for (i = 0; i < qparam->nxqs; i++) 3015 ionic_swap_queues(lif->txqcqs[i], tx_qcqs[i]); 3016 } 3017 3018 if (rx_qcqs) { 3019 lif->nrxq_descs = qparam->nrxq_descs; 3020 for (i = 0; i < qparam->nxqs; i++) 3021 ionic_swap_queues(lif->rxqcqs[i], rx_qcqs[i]); 3022 } 3023 3024 /* if we need to change the interrupt layout, this is the time */ 3025 if (qparam->intr_split != test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) || 3026 qparam->nxqs != lif->nxqs) { 3027 if (qparam->intr_split) { 3028 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 3029 } else { 3030 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 3031 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 3032 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 3033 } 3034 3035 /* Clear existing interrupt assignments. We check for NULL here 3036 * because we're checking the whole array for potential qcqs, not 3037 * just those qcqs that have just been set up. 3038 */ 3039 for (i = 0; i < lif->ionic->ntxqs_per_lif; i++) { 3040 if (lif->txqcqs[i]) 3041 ionic_qcq_intr_free(lif, lif->txqcqs[i]); 3042 if (lif->rxqcqs[i]) 3043 ionic_qcq_intr_free(lif, lif->rxqcqs[i]); 3044 } 3045 3046 /* re-assign the interrupts */ 3047 for (i = 0; i < qparam->nxqs; i++) { 3048 lif->rxqcqs[i]->flags |= IONIC_QCQ_F_INTR; 3049 err = ionic_alloc_qcq_interrupt(lif, lif->rxqcqs[i]); 3050 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 3051 lif->rxqcqs[i]->intr.index, 3052 lif->rx_coalesce_hw); 3053 3054 if (qparam->intr_split) { 3055 lif->txqcqs[i]->flags |= IONIC_QCQ_F_INTR; 3056 err = ionic_alloc_qcq_interrupt(lif, lif->txqcqs[i]); 3057 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 3058 lif->txqcqs[i]->intr.index, 3059 lif->tx_coalesce_hw); 3060 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 3061 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 3062 } else { 3063 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 3064 ionic_link_qcq_interrupts(lif->rxqcqs[i], lif->txqcqs[i]); 3065 } 3066 } 3067 } 3068 3069 /* now we can rework the debugfs mappings */ 3070 if (tx_qcqs) { 3071 for (i = 0; i < qparam->nxqs; i++) { 3072 ionic_debugfs_del_qcq(lif->txqcqs[i]); 3073 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 3074 } 3075 } 3076 3077 if (rx_qcqs) { 3078 for (i = 0; i < qparam->nxqs; i++) { 3079 ionic_debugfs_del_qcq(lif->rxqcqs[i]); 3080 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 3081 } 3082 } 3083 3084 swap(lif->nxqs, qparam->nxqs); 3085 swap(lif->rxq_features, qparam->rxq_features); 3086 3087 err_out_reinit_unlock: 3088 /* re-init the queues, but don't lose an error code */ 3089 if (err) 3090 ionic_start_queues_reconfig(lif); 3091 else 3092 err = ionic_start_queues_reconfig(lif); 3093 3094 err_out: 3095 /* free old allocs without cleaning intr */ 3096 for (i = 0; i < qparam->nxqs; i++) { 3097 if (tx_qcqs && tx_qcqs[i]) { 3098 tx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 3099 ionic_qcq_free(lif, tx_qcqs[i]); 3100 devm_kfree(lif->ionic->dev, tx_qcqs[i]); 3101 tx_qcqs[i] = NULL; 3102 } 3103 if (rx_qcqs && rx_qcqs[i]) { 3104 rx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 3105 ionic_qcq_free(lif, rx_qcqs[i]); 3106 devm_kfree(lif->ionic->dev, rx_qcqs[i]); 3107 rx_qcqs[i] = NULL; 3108 } 3109 } 3110 3111 /* free q array */ 3112 if (rx_qcqs) { 3113 devm_kfree(lif->ionic->dev, rx_qcqs); 3114 rx_qcqs = NULL; 3115 } 3116 if (tx_qcqs) { 3117 devm_kfree(lif->ionic->dev, tx_qcqs); 3118 tx_qcqs = NULL; 3119 } 3120 3121 /* clean the unused dma and info allocations when new set is smaller 3122 * than the full array, but leave the qcq shells in place 3123 */ 3124 for (i = lif->nxqs; i < lif->ionic->ntxqs_per_lif; i++) { 3125 if (lif->txqcqs && lif->txqcqs[i]) { 3126 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 3127 ionic_qcq_free(lif, lif->txqcqs[i]); 3128 } 3129 3130 if (lif->rxqcqs && lif->rxqcqs[i]) { 3131 lif->rxqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 3132 ionic_qcq_free(lif, lif->rxqcqs[i]); 3133 } 3134 } 3135 3136 if (err) 3137 netdev_info(lif->netdev, "%s: failed %d\n", __func__, err); 3138 3139 return err; 3140 } 3141 3142 int ionic_lif_alloc(struct ionic *ionic) 3143 { 3144 struct device *dev = ionic->dev; 3145 union ionic_lif_identity *lid; 3146 struct net_device *netdev; 3147 struct ionic_lif *lif; 3148 int tbl_sz; 3149 int err; 3150 3151 lid = kzalloc(sizeof(*lid), GFP_KERNEL); 3152 if (!lid) 3153 return -ENOMEM; 3154 3155 netdev = alloc_etherdev_mqs(sizeof(*lif), 3156 ionic->ntxqs_per_lif, ionic->ntxqs_per_lif); 3157 if (!netdev) { 3158 dev_err(dev, "Cannot allocate netdev, aborting\n"); 3159 err = -ENOMEM; 3160 goto err_out_free_lid; 3161 } 3162 3163 SET_NETDEV_DEV(netdev, dev); 3164 3165 lif = netdev_priv(netdev); 3166 lif->netdev = netdev; 3167 ionic->lif = lif; 3168 lif->ionic = ionic; 3169 netdev->netdev_ops = &ionic_netdev_ops; 3170 ionic_ethtool_set_ops(netdev); 3171 3172 netdev->watchdog_timeo = 2 * HZ; 3173 netif_carrier_off(netdev); 3174 3175 lif->identity = lid; 3176 lif->lif_type = IONIC_LIF_TYPE_CLASSIC; 3177 err = ionic_lif_identify(ionic, lif->lif_type, lif->identity); 3178 if (err) { 3179 dev_err(ionic->dev, "Cannot identify type %d: %d\n", 3180 lif->lif_type, err); 3181 goto err_out_free_netdev; 3182 } 3183 lif->netdev->min_mtu = max_t(unsigned int, ETH_MIN_MTU, 3184 le32_to_cpu(lif->identity->eth.min_frame_size)); 3185 lif->netdev->max_mtu = 3186 le32_to_cpu(lif->identity->eth.max_frame_size) - ETH_HLEN - VLAN_HLEN; 3187 3188 lif->neqs = ionic->neqs_per_lif; 3189 lif->nxqs = ionic->ntxqs_per_lif; 3190 3191 lif->index = 0; 3192 3193 if (is_kdump_kernel()) { 3194 lif->ntxq_descs = IONIC_MIN_TXRX_DESC; 3195 lif->nrxq_descs = IONIC_MIN_TXRX_DESC; 3196 } else { 3197 lif->ntxq_descs = IONIC_DEF_TXRX_DESC; 3198 lif->nrxq_descs = IONIC_DEF_TXRX_DESC; 3199 } 3200 3201 /* Convert the default coalesce value to actual hw resolution */ 3202 lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT; 3203 lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic, 3204 lif->rx_coalesce_usecs); 3205 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 3206 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 3207 set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 3208 set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 3209 3210 snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index); 3211 3212 mutex_init(&lif->queue_lock); 3213 mutex_init(&lif->config_lock); 3214 3215 spin_lock_init(&lif->adminq_lock); 3216 3217 spin_lock_init(&lif->deferred.lock); 3218 INIT_LIST_HEAD(&lif->deferred.list); 3219 INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work); 3220 3221 /* allocate lif info */ 3222 lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE); 3223 lif->info = dma_alloc_coherent(dev, lif->info_sz, 3224 &lif->info_pa, GFP_KERNEL); 3225 if (!lif->info) { 3226 dev_err(dev, "Failed to allocate lif info, aborting\n"); 3227 err = -ENOMEM; 3228 goto err_out_free_mutex; 3229 } 3230 3231 ionic_debugfs_add_lif(lif); 3232 3233 /* allocate control queues and txrx queue arrays */ 3234 ionic_lif_queue_identify(lif); 3235 err = ionic_qcqs_alloc(lif); 3236 if (err) 3237 goto err_out_free_lif_info; 3238 3239 /* allocate rss indirection table */ 3240 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 3241 lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz; 3242 lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz, 3243 &lif->rss_ind_tbl_pa, 3244 GFP_KERNEL); 3245 3246 if (!lif->rss_ind_tbl) { 3247 err = -ENOMEM; 3248 dev_err(dev, "Failed to allocate rss indirection table, aborting\n"); 3249 goto err_out_free_qcqs; 3250 } 3251 netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE); 3252 3253 ionic_lif_alloc_phc(lif); 3254 3255 return 0; 3256 3257 err_out_free_qcqs: 3258 ionic_qcqs_free(lif); 3259 err_out_free_lif_info: 3260 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 3261 lif->info = NULL; 3262 lif->info_pa = 0; 3263 err_out_free_mutex: 3264 mutex_destroy(&lif->config_lock); 3265 mutex_destroy(&lif->queue_lock); 3266 err_out_free_netdev: 3267 free_netdev(lif->netdev); 3268 lif = NULL; 3269 err_out_free_lid: 3270 kfree(lid); 3271 3272 return err; 3273 } 3274 3275 static void ionic_lif_reset(struct ionic_lif *lif) 3276 { 3277 struct ionic_dev *idev = &lif->ionic->idev; 3278 3279 if (!ionic_is_fw_running(idev)) 3280 return; 3281 3282 mutex_lock(&lif->ionic->dev_cmd_lock); 3283 ionic_dev_cmd_lif_reset(idev, lif->index); 3284 ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 3285 mutex_unlock(&lif->ionic->dev_cmd_lock); 3286 } 3287 3288 static void ionic_lif_handle_fw_down(struct ionic_lif *lif) 3289 { 3290 struct ionic *ionic = lif->ionic; 3291 3292 if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state)) 3293 return; 3294 3295 dev_info(ionic->dev, "FW Down: Stopping LIFs\n"); 3296 3297 netif_device_detach(lif->netdev); 3298 3299 mutex_lock(&lif->queue_lock); 3300 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 3301 dev_info(ionic->dev, "Surprise FW stop, stopping queues\n"); 3302 ionic_stop_queues(lif); 3303 } 3304 3305 if (netif_running(lif->netdev)) { 3306 ionic_txrx_deinit(lif); 3307 ionic_txrx_free(lif); 3308 } 3309 ionic_lif_deinit(lif); 3310 ionic_reset(ionic); 3311 ionic_qcqs_free(lif); 3312 3313 mutex_unlock(&lif->queue_lock); 3314 3315 clear_bit(IONIC_LIF_F_FW_STOPPING, lif->state); 3316 dev_info(ionic->dev, "FW Down: LIFs stopped\n"); 3317 } 3318 3319 int ionic_restart_lif(struct ionic_lif *lif) 3320 { 3321 struct ionic *ionic = lif->ionic; 3322 int err; 3323 3324 mutex_lock(&lif->queue_lock); 3325 3326 if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state)) 3327 dev_info(ionic->dev, "FW Up: clearing broken state\n"); 3328 3329 err = ionic_qcqs_alloc(lif); 3330 if (err) 3331 goto err_unlock; 3332 3333 err = ionic_lif_init(lif); 3334 if (err) 3335 goto err_qcqs_free; 3336 3337 ionic_vf_attr_replay(lif); 3338 3339 if (lif->registered) 3340 ionic_lif_set_netdev_info(lif); 3341 3342 ionic_rx_filter_replay(lif); 3343 3344 if (netif_running(lif->netdev)) { 3345 err = ionic_txrx_alloc(lif); 3346 if (err) 3347 goto err_lifs_deinit; 3348 3349 err = ionic_txrx_init(lif); 3350 if (err) 3351 goto err_txrx_free; 3352 } 3353 3354 mutex_unlock(&lif->queue_lock); 3355 3356 clear_bit(IONIC_LIF_F_FW_RESET, lif->state); 3357 ionic_link_status_check_request(lif, CAN_SLEEP); 3358 netif_device_attach(lif->netdev); 3359 3360 return 0; 3361 3362 err_txrx_free: 3363 ionic_txrx_free(lif); 3364 err_lifs_deinit: 3365 ionic_lif_deinit(lif); 3366 err_qcqs_free: 3367 ionic_qcqs_free(lif); 3368 err_unlock: 3369 mutex_unlock(&lif->queue_lock); 3370 3371 return err; 3372 } 3373 3374 static void ionic_lif_handle_fw_up(struct ionic_lif *lif) 3375 { 3376 struct ionic *ionic = lif->ionic; 3377 int err; 3378 3379 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 3380 return; 3381 3382 dev_info(ionic->dev, "FW Up: restarting LIFs\n"); 3383 3384 /* This is a little different from what happens at 3385 * probe time because the LIF already exists so we 3386 * just need to reanimate it. 3387 */ 3388 ionic_init_devinfo(ionic); 3389 err = ionic_identify(ionic); 3390 if (err) 3391 goto err_out; 3392 err = ionic_port_identify(ionic); 3393 if (err) 3394 goto err_out; 3395 err = ionic_port_init(ionic); 3396 if (err) 3397 goto err_out; 3398 3399 err = ionic_restart_lif(lif); 3400 if (err) 3401 goto err_out; 3402 3403 dev_info(ionic->dev, "FW Up: LIFs restarted\n"); 3404 3405 /* restore the hardware timestamping queues */ 3406 ionic_lif_hwstamp_replay(lif); 3407 3408 return; 3409 3410 err_out: 3411 dev_err(ionic->dev, "FW Up: LIFs restart failed - err %d\n", err); 3412 } 3413 3414 void ionic_lif_free(struct ionic_lif *lif) 3415 { 3416 struct device *dev = lif->ionic->dev; 3417 3418 ionic_lif_free_phc(lif); 3419 3420 /* free rss indirection table */ 3421 dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl, 3422 lif->rss_ind_tbl_pa); 3423 lif->rss_ind_tbl = NULL; 3424 lif->rss_ind_tbl_pa = 0; 3425 3426 /* free queues */ 3427 ionic_qcqs_free(lif); 3428 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 3429 ionic_lif_reset(lif); 3430 3431 /* free lif info */ 3432 kfree(lif->identity); 3433 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 3434 lif->info = NULL; 3435 lif->info_pa = 0; 3436 3437 /* unmap doorbell page */ 3438 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 3439 lif->kern_dbpage = NULL; 3440 3441 mutex_destroy(&lif->config_lock); 3442 mutex_destroy(&lif->queue_lock); 3443 3444 /* free netdev & lif */ 3445 ionic_debugfs_del_lif(lif); 3446 free_netdev(lif->netdev); 3447 } 3448 3449 void ionic_lif_deinit(struct ionic_lif *lif) 3450 { 3451 if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state)) 3452 return; 3453 3454 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 3455 cancel_work_sync(&lif->deferred.work); 3456 cancel_work_sync(&lif->tx_timeout_work); 3457 ionic_rx_filters_deinit(lif); 3458 if (lif->netdev->features & NETIF_F_RXHASH) 3459 ionic_lif_rss_deinit(lif); 3460 } 3461 3462 napi_disable(&lif->adminqcq->napi); 3463 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 3464 ionic_lif_qcq_deinit(lif, lif->adminqcq); 3465 3466 ionic_lif_reset(lif); 3467 } 3468 3469 static int ionic_lif_adminq_init(struct ionic_lif *lif) 3470 { 3471 struct device *dev = lif->ionic->dev; 3472 struct ionic_q_init_comp comp; 3473 struct ionic_dev *idev; 3474 struct ionic_qcq *qcq; 3475 struct ionic_queue *q; 3476 int err; 3477 3478 idev = &lif->ionic->idev; 3479 qcq = lif->adminqcq; 3480 q = &qcq->q; 3481 3482 mutex_lock(&lif->ionic->dev_cmd_lock); 3483 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index); 3484 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 3485 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 3486 mutex_unlock(&lif->ionic->dev_cmd_lock); 3487 if (err) { 3488 netdev_err(lif->netdev, "adminq init failed %d\n", err); 3489 return err; 3490 } 3491 3492 q->hw_type = comp.hw_type; 3493 q->hw_index = le32_to_cpu(comp.hw_index); 3494 q->dbval = IONIC_DBELL_QID(q->hw_index); 3495 3496 dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type); 3497 dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index); 3498 3499 q->dbell_deadline = IONIC_ADMIN_DOORBELL_DEADLINE; 3500 q->dbell_jiffies = jiffies; 3501 3502 netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi); 3503 3504 qcq->napi_qcq = qcq; 3505 timer_setup(&qcq->napi_deadline, ionic_napi_deadline, 0); 3506 3507 napi_enable(&qcq->napi); 3508 3509 if (qcq->flags & IONIC_QCQ_F_INTR) { 3510 irq_set_affinity_hint(qcq->intr.vector, 3511 &qcq->intr.affinity_mask); 3512 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 3513 IONIC_INTR_MASK_CLEAR); 3514 } 3515 3516 qcq->flags |= IONIC_QCQ_F_INITED; 3517 3518 return 0; 3519 } 3520 3521 static int ionic_lif_notifyq_init(struct ionic_lif *lif) 3522 { 3523 struct ionic_qcq *qcq = lif->notifyqcq; 3524 struct device *dev = lif->ionic->dev; 3525 struct ionic_queue *q = &qcq->q; 3526 int err; 3527 3528 struct ionic_admin_ctx ctx = { 3529 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3530 .cmd.q_init = { 3531 .opcode = IONIC_CMD_Q_INIT, 3532 .lif_index = cpu_to_le16(lif->index), 3533 .type = q->type, 3534 .ver = lif->qtype_info[q->type].version, 3535 .index = cpu_to_le32(q->index), 3536 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 3537 IONIC_QINIT_F_ENA), 3538 .intr_index = cpu_to_le16(lif->adminqcq->intr.index), 3539 .pid = cpu_to_le16(q->pid), 3540 .ring_size = ilog2(q->num_descs), 3541 .ring_base = cpu_to_le64(q->base_pa), 3542 } 3543 }; 3544 3545 dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid); 3546 dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index); 3547 dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 3548 dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 3549 3550 err = ionic_adminq_post_wait(lif, &ctx); 3551 if (err) 3552 return err; 3553 3554 lif->last_eid = 0; 3555 q->hw_type = ctx.comp.q_init.hw_type; 3556 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 3557 q->dbval = IONIC_DBELL_QID(q->hw_index); 3558 3559 dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type); 3560 dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index); 3561 3562 /* preset the callback info */ 3563 q->admin_info[0].ctx = lif; 3564 3565 qcq->flags |= IONIC_QCQ_F_INITED; 3566 3567 return 0; 3568 } 3569 3570 static int ionic_station_set(struct ionic_lif *lif) 3571 { 3572 struct net_device *netdev = lif->netdev; 3573 struct ionic_admin_ctx ctx = { 3574 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3575 .cmd.lif_getattr = { 3576 .opcode = IONIC_CMD_LIF_GETATTR, 3577 .index = cpu_to_le16(lif->index), 3578 .attr = IONIC_LIF_ATTR_MAC, 3579 }, 3580 }; 3581 u8 mac_address[ETH_ALEN]; 3582 struct sockaddr addr; 3583 int err; 3584 3585 err = ionic_adminq_post_wait(lif, &ctx); 3586 if (err) 3587 return err; 3588 netdev_dbg(lif->netdev, "found initial MAC addr %pM\n", 3589 ctx.comp.lif_getattr.mac); 3590 ether_addr_copy(mac_address, ctx.comp.lif_getattr.mac); 3591 3592 if (is_zero_ether_addr(mac_address)) { 3593 eth_hw_addr_random(netdev); 3594 netdev_dbg(netdev, "Random Mac generated: %pM\n", netdev->dev_addr); 3595 ether_addr_copy(mac_address, netdev->dev_addr); 3596 3597 err = ionic_program_mac(lif, mac_address); 3598 if (err < 0) 3599 return err; 3600 3601 if (err > 0) { 3602 netdev_dbg(netdev, "%s:SET/GET ATTR Mac are not same-due to old FW running\n", 3603 __func__); 3604 return 0; 3605 } 3606 } 3607 3608 if (!is_zero_ether_addr(netdev->dev_addr)) { 3609 /* If the netdev mac is non-zero and doesn't match the default 3610 * device address, it was set by something earlier and we're 3611 * likely here again after a fw-upgrade reset. We need to be 3612 * sure the netdev mac is in our filter list. 3613 */ 3614 if (!ether_addr_equal(mac_address, netdev->dev_addr)) 3615 ionic_lif_addr_add(lif, netdev->dev_addr); 3616 } else { 3617 /* Update the netdev mac with the device's mac */ 3618 ether_addr_copy(addr.sa_data, mac_address); 3619 addr.sa_family = AF_INET; 3620 err = eth_prepare_mac_addr_change(netdev, &addr); 3621 if (err) { 3622 netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n", 3623 addr.sa_data, err); 3624 return 0; 3625 } 3626 3627 eth_commit_mac_addr_change(netdev, &addr); 3628 } 3629 3630 netdev_dbg(lif->netdev, "adding station MAC addr %pM\n", 3631 netdev->dev_addr); 3632 ionic_lif_addr_add(lif, netdev->dev_addr); 3633 3634 return 0; 3635 } 3636 3637 int ionic_lif_init(struct ionic_lif *lif) 3638 { 3639 struct ionic_dev *idev = &lif->ionic->idev; 3640 struct device *dev = lif->ionic->dev; 3641 struct ionic_lif_init_comp comp; 3642 int dbpage_num; 3643 int err; 3644 3645 mutex_lock(&lif->ionic->dev_cmd_lock); 3646 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa); 3647 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 3648 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 3649 mutex_unlock(&lif->ionic->dev_cmd_lock); 3650 if (err) 3651 return err; 3652 3653 lif->hw_index = le16_to_cpu(comp.hw_index); 3654 3655 /* now that we have the hw_index we can figure out our doorbell page */ 3656 lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif); 3657 if (!lif->dbid_count) { 3658 dev_err(dev, "No doorbell pages, aborting\n"); 3659 return -EINVAL; 3660 } 3661 3662 lif->kern_pid = 0; 3663 dbpage_num = ionic_db_page_num(lif, lif->kern_pid); 3664 lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num); 3665 if (!lif->kern_dbpage) { 3666 dev_err(dev, "Cannot map dbpage, aborting\n"); 3667 return -ENOMEM; 3668 } 3669 3670 err = ionic_lif_adminq_init(lif); 3671 if (err) 3672 goto err_out_adminq_deinit; 3673 3674 if (lif->ionic->nnqs_per_lif) { 3675 err = ionic_lif_notifyq_init(lif); 3676 if (err) 3677 goto err_out_notifyq_deinit; 3678 } 3679 3680 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 3681 err = ionic_set_nic_features(lif, lif->netdev->features); 3682 else 3683 err = ionic_init_nic_features(lif); 3684 if (err) 3685 goto err_out_notifyq_deinit; 3686 3687 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 3688 err = ionic_rx_filters_init(lif); 3689 if (err) 3690 goto err_out_notifyq_deinit; 3691 } 3692 3693 err = ionic_station_set(lif); 3694 if (err) 3695 goto err_out_notifyq_deinit; 3696 3697 lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT; 3698 3699 set_bit(IONIC_LIF_F_INITED, lif->state); 3700 3701 INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work); 3702 3703 return 0; 3704 3705 err_out_notifyq_deinit: 3706 napi_disable(&lif->adminqcq->napi); 3707 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 3708 err_out_adminq_deinit: 3709 ionic_lif_qcq_deinit(lif, lif->adminqcq); 3710 ionic_lif_reset(lif); 3711 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 3712 lif->kern_dbpage = NULL; 3713 3714 return err; 3715 } 3716 3717 static void ionic_lif_notify_work(struct work_struct *ws) 3718 { 3719 } 3720 3721 static void ionic_lif_set_netdev_info(struct ionic_lif *lif) 3722 { 3723 struct ionic_admin_ctx ctx = { 3724 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3725 .cmd.lif_setattr = { 3726 .opcode = IONIC_CMD_LIF_SETATTR, 3727 .index = cpu_to_le16(lif->index), 3728 .attr = IONIC_LIF_ATTR_NAME, 3729 }, 3730 }; 3731 3732 strscpy(ctx.cmd.lif_setattr.name, lif->netdev->name, 3733 sizeof(ctx.cmd.lif_setattr.name)); 3734 3735 ionic_adminq_post_wait(lif, &ctx); 3736 } 3737 3738 static struct ionic_lif *ionic_netdev_lif(struct net_device *netdev) 3739 { 3740 if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit) 3741 return NULL; 3742 3743 return netdev_priv(netdev); 3744 } 3745 3746 static int ionic_lif_notify(struct notifier_block *nb, 3747 unsigned long event, void *info) 3748 { 3749 struct net_device *ndev = netdev_notifier_info_to_dev(info); 3750 struct ionic *ionic = container_of(nb, struct ionic, nb); 3751 struct ionic_lif *lif = ionic_netdev_lif(ndev); 3752 3753 if (!lif || lif->ionic != ionic) 3754 return NOTIFY_DONE; 3755 3756 switch (event) { 3757 case NETDEV_CHANGENAME: 3758 ionic_lif_set_netdev_info(lif); 3759 break; 3760 } 3761 3762 return NOTIFY_DONE; 3763 } 3764 3765 int ionic_lif_register(struct ionic_lif *lif) 3766 { 3767 int err; 3768 3769 ionic_lif_register_phc(lif); 3770 3771 INIT_WORK(&lif->ionic->nb_work, ionic_lif_notify_work); 3772 3773 lif->ionic->nb.notifier_call = ionic_lif_notify; 3774 3775 err = register_netdevice_notifier(&lif->ionic->nb); 3776 if (err) 3777 lif->ionic->nb.notifier_call = NULL; 3778 3779 /* only register LIF0 for now */ 3780 err = register_netdev(lif->netdev); 3781 if (err) { 3782 dev_err(lif->ionic->dev, "Cannot register net device, aborting\n"); 3783 ionic_lif_unregister_phc(lif); 3784 return err; 3785 } 3786 3787 ionic_link_status_check_request(lif, CAN_SLEEP); 3788 lif->registered = true; 3789 ionic_lif_set_netdev_info(lif); 3790 3791 return 0; 3792 } 3793 3794 void ionic_lif_unregister(struct ionic_lif *lif) 3795 { 3796 if (lif->ionic->nb.notifier_call) { 3797 unregister_netdevice_notifier(&lif->ionic->nb); 3798 cancel_work_sync(&lif->ionic->nb_work); 3799 lif->ionic->nb.notifier_call = NULL; 3800 } 3801 3802 if (lif->netdev->reg_state == NETREG_REGISTERED) 3803 unregister_netdev(lif->netdev); 3804 3805 ionic_lif_unregister_phc(lif); 3806 3807 lif->registered = false; 3808 } 3809 3810 static void ionic_lif_queue_identify(struct ionic_lif *lif) 3811 { 3812 union ionic_q_identity __iomem *q_ident; 3813 struct ionic *ionic = lif->ionic; 3814 struct ionic_dev *idev; 3815 u16 max_frags; 3816 int qtype; 3817 int err; 3818 3819 idev = &lif->ionic->idev; 3820 q_ident = (union ionic_q_identity __iomem *)&idev->dev_cmd_regs->data; 3821 3822 for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) { 3823 struct ionic_qtype_info *qti = &lif->qtype_info[qtype]; 3824 3825 /* filter out the ones we know about */ 3826 switch (qtype) { 3827 case IONIC_QTYPE_ADMINQ: 3828 case IONIC_QTYPE_NOTIFYQ: 3829 case IONIC_QTYPE_RXQ: 3830 case IONIC_QTYPE_TXQ: 3831 break; 3832 default: 3833 continue; 3834 } 3835 3836 memset(qti, 0, sizeof(*qti)); 3837 3838 mutex_lock(&ionic->dev_cmd_lock); 3839 ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype, 3840 ionic_qtype_versions[qtype]); 3841 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3842 if (!err) { 3843 qti->version = readb(&q_ident->version); 3844 qti->supported = readb(&q_ident->supported); 3845 qti->features = readq(&q_ident->features); 3846 qti->desc_sz = readw(&q_ident->desc_sz); 3847 qti->comp_sz = readw(&q_ident->comp_sz); 3848 qti->sg_desc_sz = readw(&q_ident->sg_desc_sz); 3849 qti->max_sg_elems = readw(&q_ident->max_sg_elems); 3850 qti->sg_desc_stride = readw(&q_ident->sg_desc_stride); 3851 } 3852 mutex_unlock(&ionic->dev_cmd_lock); 3853 3854 if (err == -EINVAL) { 3855 dev_err(ionic->dev, "qtype %d not supported\n", qtype); 3856 continue; 3857 } else if (err == -EIO) { 3858 dev_err(ionic->dev, "q_ident failed, not supported on older FW\n"); 3859 return; 3860 } else if (err) { 3861 dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n", 3862 qtype, err); 3863 return; 3864 } 3865 3866 dev_dbg(ionic->dev, " qtype[%d].version = %d\n", 3867 qtype, qti->version); 3868 dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n", 3869 qtype, qti->supported); 3870 dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n", 3871 qtype, qti->features); 3872 dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n", 3873 qtype, qti->desc_sz); 3874 dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n", 3875 qtype, qti->comp_sz); 3876 dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n", 3877 qtype, qti->sg_desc_sz); 3878 dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n", 3879 qtype, qti->max_sg_elems); 3880 dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n", 3881 qtype, qti->sg_desc_stride); 3882 3883 if (qtype == IONIC_QTYPE_TXQ) 3884 max_frags = IONIC_TX_MAX_FRAGS; 3885 else if (qtype == IONIC_QTYPE_RXQ) 3886 max_frags = IONIC_RX_MAX_FRAGS; 3887 else 3888 max_frags = 1; 3889 3890 qti->max_sg_elems = min_t(u16, max_frags - 1, MAX_SKB_FRAGS); 3891 dev_dbg(ionic->dev, "qtype %d max_sg_elems %d\n", 3892 qtype, qti->max_sg_elems); 3893 } 3894 } 3895 3896 int ionic_lif_identify(struct ionic *ionic, u8 lif_type, 3897 union ionic_lif_identity *lid) 3898 { 3899 struct ionic_dev *idev = &ionic->idev; 3900 size_t sz; 3901 int err; 3902 3903 sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data)); 3904 3905 mutex_lock(&ionic->dev_cmd_lock); 3906 ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1); 3907 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3908 memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz); 3909 mutex_unlock(&ionic->dev_cmd_lock); 3910 if (err) 3911 return (err); 3912 3913 dev_dbg(ionic->dev, "capabilities 0x%llx\n", 3914 le64_to_cpu(lid->capabilities)); 3915 3916 dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n", 3917 le32_to_cpu(lid->eth.max_ucast_filters)); 3918 dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n", 3919 le32_to_cpu(lid->eth.max_mcast_filters)); 3920 dev_dbg(ionic->dev, "eth.features 0x%llx\n", 3921 le64_to_cpu(lid->eth.config.features)); 3922 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n", 3923 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ])); 3924 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n", 3925 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ])); 3926 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n", 3927 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ])); 3928 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n", 3929 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ])); 3930 dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name); 3931 dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac); 3932 dev_dbg(ionic->dev, "eth.config.mtu %d\n", 3933 le32_to_cpu(lid->eth.config.mtu)); 3934 3935 return 0; 3936 } 3937 3938 int ionic_lif_size(struct ionic *ionic) 3939 { 3940 struct ionic_identity *ident = &ionic->ident; 3941 unsigned int nintrs, dev_nintrs; 3942 union ionic_lif_config *lc; 3943 unsigned int ntxqs_per_lif; 3944 unsigned int nrxqs_per_lif; 3945 unsigned int neqs_per_lif; 3946 unsigned int nnqs_per_lif; 3947 unsigned int nxqs, neqs; 3948 unsigned int min_intrs; 3949 int err; 3950 3951 /* retrieve basic values from FW */ 3952 lc = &ident->lif.eth.config; 3953 dev_nintrs = le32_to_cpu(ident->dev.nintrs); 3954 neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count); 3955 nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]); 3956 ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]); 3957 nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]); 3958 3959 /* limit values to play nice with kdump */ 3960 if (is_kdump_kernel()) { 3961 dev_nintrs = 2; 3962 neqs_per_lif = 0; 3963 nnqs_per_lif = 0; 3964 ntxqs_per_lif = 1; 3965 nrxqs_per_lif = 1; 3966 } 3967 3968 /* reserve last queue id for hardware timestamping */ 3969 if (lc->features & cpu_to_le64(IONIC_ETH_HW_TIMESTAMP)) { 3970 if (ntxqs_per_lif <= 1 || nrxqs_per_lif <= 1) { 3971 lc->features &= cpu_to_le64(~IONIC_ETH_HW_TIMESTAMP); 3972 } else { 3973 ntxqs_per_lif -= 1; 3974 nrxqs_per_lif -= 1; 3975 } 3976 } 3977 3978 nxqs = min(ntxqs_per_lif, nrxqs_per_lif); 3979 nxqs = min(nxqs, num_online_cpus()); 3980 neqs = min(neqs_per_lif, num_online_cpus()); 3981 3982 try_again: 3983 /* interrupt usage: 3984 * 1 for master lif adminq/notifyq 3985 * 1 for each CPU for master lif TxRx queue pairs 3986 * whatever's left is for RDMA queues 3987 */ 3988 nintrs = 1 + nxqs + neqs; 3989 min_intrs = 2; /* adminq + 1 TxRx queue pair */ 3990 3991 if (nintrs > dev_nintrs) 3992 goto try_fewer; 3993 3994 err = ionic_bus_alloc_irq_vectors(ionic, nintrs); 3995 if (err < 0 && err != -ENOSPC) { 3996 dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err); 3997 return err; 3998 } 3999 if (err == -ENOSPC) 4000 goto try_fewer; 4001 4002 if (err != nintrs) { 4003 ionic_bus_free_irq_vectors(ionic); 4004 goto try_fewer; 4005 } 4006 4007 ionic->nnqs_per_lif = nnqs_per_lif; 4008 ionic->neqs_per_lif = neqs; 4009 ionic->ntxqs_per_lif = nxqs; 4010 ionic->nrxqs_per_lif = nxqs; 4011 ionic->nintrs = nintrs; 4012 4013 ionic_debugfs_add_sizes(ionic); 4014 4015 return 0; 4016 4017 try_fewer: 4018 if (nnqs_per_lif > 1) { 4019 nnqs_per_lif >>= 1; 4020 goto try_again; 4021 } 4022 if (neqs > 1) { 4023 neqs >>= 1; 4024 goto try_again; 4025 } 4026 if (nxqs > 1) { 4027 nxqs >>= 1; 4028 goto try_again; 4029 } 4030 dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs); 4031 return -ENOSPC; 4032 } 4033