1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/ethtool.h> 5 #include <linux/printk.h> 6 #include <linux/dynamic_debug.h> 7 #include <linux/netdevice.h> 8 #include <linux/etherdevice.h> 9 #include <linux/if_vlan.h> 10 #include <linux/rtnetlink.h> 11 #include <linux/interrupt.h> 12 #include <linux/pci.h> 13 #include <linux/cpumask.h> 14 #include <linux/crash_dump.h> 15 16 #include "ionic.h" 17 #include "ionic_bus.h" 18 #include "ionic_lif.h" 19 #include "ionic_txrx.h" 20 #include "ionic_ethtool.h" 21 #include "ionic_debugfs.h" 22 23 /* queuetype support level */ 24 static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = { 25 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */ 26 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */ 27 [IONIC_QTYPE_RXQ] = 0, /* 0 = Base version with CQ+SG support */ 28 [IONIC_QTYPE_TXQ] = 1, /* 0 = Base version with CQ+SG support 29 * 1 = ... with Tx SG version 1 30 */ 31 }; 32 33 static void ionic_link_status_check(struct ionic_lif *lif); 34 static void ionic_lif_handle_fw_down(struct ionic_lif *lif); 35 static void ionic_lif_handle_fw_up(struct ionic_lif *lif); 36 static void ionic_lif_set_netdev_info(struct ionic_lif *lif); 37 38 static void ionic_txrx_deinit(struct ionic_lif *lif); 39 static int ionic_txrx_init(struct ionic_lif *lif); 40 static int ionic_start_queues(struct ionic_lif *lif); 41 static void ionic_stop_queues(struct ionic_lif *lif); 42 static void ionic_lif_queue_identify(struct ionic_lif *lif); 43 44 static void ionic_dim_work(struct work_struct *work) 45 { 46 struct dim *dim = container_of(work, struct dim, work); 47 struct dim_cq_moder cur_moder; 48 struct ionic_qcq *qcq; 49 u32 new_coal; 50 51 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 52 qcq = container_of(dim, struct ionic_qcq, dim); 53 new_coal = ionic_coal_usec_to_hw(qcq->q.lif->ionic, cur_moder.usec); 54 new_coal = new_coal ? new_coal : 1; 55 56 if (qcq->intr.dim_coal_hw != new_coal) { 57 unsigned int qi = qcq->cq.bound_q->index; 58 struct ionic_lif *lif = qcq->q.lif; 59 60 qcq->intr.dim_coal_hw = new_coal; 61 62 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 63 lif->rxqcqs[qi]->intr.index, 64 qcq->intr.dim_coal_hw); 65 } 66 67 dim->state = DIM_START_MEASURE; 68 } 69 70 static void ionic_lif_deferred_work(struct work_struct *work) 71 { 72 struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work); 73 struct ionic_deferred *def = &lif->deferred; 74 struct ionic_deferred_work *w = NULL; 75 76 do { 77 spin_lock_bh(&def->lock); 78 if (!list_empty(&def->list)) { 79 w = list_first_entry(&def->list, 80 struct ionic_deferred_work, list); 81 list_del(&w->list); 82 } 83 spin_unlock_bh(&def->lock); 84 85 if (!w) 86 break; 87 88 switch (w->type) { 89 case IONIC_DW_TYPE_RX_MODE: 90 ionic_lif_rx_mode(lif); 91 break; 92 case IONIC_DW_TYPE_LINK_STATUS: 93 ionic_link_status_check(lif); 94 break; 95 case IONIC_DW_TYPE_LIF_RESET: 96 if (w->fw_status) { 97 ionic_lif_handle_fw_up(lif); 98 } else { 99 ionic_lif_handle_fw_down(lif); 100 101 /* Fire off another watchdog to see 102 * if the FW is already back rather than 103 * waiting another whole cycle 104 */ 105 mod_timer(&lif->ionic->watchdog_timer, jiffies + 1); 106 } 107 break; 108 default: 109 break; 110 } 111 kfree(w); 112 w = NULL; 113 } while (true); 114 } 115 116 void ionic_lif_deferred_enqueue(struct ionic_deferred *def, 117 struct ionic_deferred_work *work) 118 { 119 spin_lock_bh(&def->lock); 120 list_add_tail(&work->list, &def->list); 121 spin_unlock_bh(&def->lock); 122 schedule_work(&def->work); 123 } 124 125 static void ionic_link_status_check(struct ionic_lif *lif) 126 { 127 struct net_device *netdev = lif->netdev; 128 u16 link_status; 129 bool link_up; 130 131 if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 132 return; 133 134 /* Don't put carrier back up if we're in a broken state */ 135 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) { 136 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 137 return; 138 } 139 140 link_status = le16_to_cpu(lif->info->status.link_status); 141 link_up = link_status == IONIC_PORT_OPER_STATUS_UP; 142 143 if (link_up) { 144 int err = 0; 145 146 if (netdev->flags & IFF_UP && netif_running(netdev)) { 147 mutex_lock(&lif->queue_lock); 148 err = ionic_start_queues(lif); 149 if (err && err != -EBUSY) { 150 netdev_err(lif->netdev, 151 "Failed to start queues: %d\n", err); 152 set_bit(IONIC_LIF_F_BROKEN, lif->state); 153 netif_carrier_off(lif->netdev); 154 } 155 mutex_unlock(&lif->queue_lock); 156 } 157 158 if (!err && !netif_carrier_ok(netdev)) { 159 ionic_port_identify(lif->ionic); 160 netdev_info(netdev, "Link up - %d Gbps\n", 161 le32_to_cpu(lif->info->status.link_speed) / 1000); 162 netif_carrier_on(netdev); 163 } 164 } else { 165 if (netif_carrier_ok(netdev)) { 166 netdev_info(netdev, "Link down\n"); 167 netif_carrier_off(netdev); 168 } 169 170 if (netdev->flags & IFF_UP && netif_running(netdev)) { 171 mutex_lock(&lif->queue_lock); 172 ionic_stop_queues(lif); 173 mutex_unlock(&lif->queue_lock); 174 } 175 } 176 177 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 178 } 179 180 void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep) 181 { 182 struct ionic_deferred_work *work; 183 184 /* we only need one request outstanding at a time */ 185 if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 186 return; 187 188 if (!can_sleep) { 189 work = kzalloc(sizeof(*work), GFP_ATOMIC); 190 if (!work) { 191 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 192 return; 193 } 194 195 work->type = IONIC_DW_TYPE_LINK_STATUS; 196 ionic_lif_deferred_enqueue(&lif->deferred, work); 197 } else { 198 ionic_link_status_check(lif); 199 } 200 } 201 202 static irqreturn_t ionic_isr(int irq, void *data) 203 { 204 struct napi_struct *napi = data; 205 206 napi_schedule_irqoff(napi); 207 208 return IRQ_HANDLED; 209 } 210 211 static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq) 212 { 213 struct ionic_intr_info *intr = &qcq->intr; 214 struct device *dev = lif->ionic->dev; 215 struct ionic_queue *q = &qcq->q; 216 const char *name; 217 218 if (lif->registered) 219 name = lif->netdev->name; 220 else 221 name = dev_name(dev); 222 223 snprintf(intr->name, sizeof(intr->name), 224 "%s-%s-%s", IONIC_DRV_NAME, name, q->name); 225 226 return devm_request_irq(dev, intr->vector, ionic_isr, 227 0, intr->name, &qcq->napi); 228 } 229 230 static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) 231 { 232 struct ionic *ionic = lif->ionic; 233 int index; 234 235 index = find_first_zero_bit(ionic->intrs, ionic->nintrs); 236 if (index == ionic->nintrs) { 237 netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n", 238 __func__, index, ionic->nintrs); 239 return -ENOSPC; 240 } 241 242 set_bit(index, ionic->intrs); 243 ionic_intr_init(&ionic->idev, intr, index); 244 245 return 0; 246 } 247 248 static void ionic_intr_free(struct ionic *ionic, int index) 249 { 250 if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < ionic->nintrs) 251 clear_bit(index, ionic->intrs); 252 } 253 254 static int ionic_qcq_enable(struct ionic_qcq *qcq) 255 { 256 struct ionic_queue *q = &qcq->q; 257 struct ionic_lif *lif = q->lif; 258 struct ionic_dev *idev; 259 struct device *dev; 260 261 struct ionic_admin_ctx ctx = { 262 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 263 .cmd.q_control = { 264 .opcode = IONIC_CMD_Q_CONTROL, 265 .lif_index = cpu_to_le16(lif->index), 266 .type = q->type, 267 .index = cpu_to_le32(q->index), 268 .oper = IONIC_Q_ENABLE, 269 }, 270 }; 271 272 idev = &lif->ionic->idev; 273 dev = lif->ionic->dev; 274 275 dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n", 276 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 277 278 if (qcq->flags & IONIC_QCQ_F_INTR) { 279 irq_set_affinity_hint(qcq->intr.vector, 280 &qcq->intr.affinity_mask); 281 napi_enable(&qcq->napi); 282 ionic_intr_clean(idev->intr_ctrl, qcq->intr.index); 283 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 284 IONIC_INTR_MASK_CLEAR); 285 } 286 287 return ionic_adminq_post_wait(lif, &ctx); 288 } 289 290 static int ionic_qcq_disable(struct ionic_lif *lif, struct ionic_qcq *qcq, int fw_err) 291 { 292 struct ionic_queue *q; 293 294 struct ionic_admin_ctx ctx = { 295 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 296 .cmd.q_control = { 297 .opcode = IONIC_CMD_Q_CONTROL, 298 .oper = IONIC_Q_DISABLE, 299 }, 300 }; 301 302 if (!qcq) { 303 netdev_err(lif->netdev, "%s: bad qcq\n", __func__); 304 return -ENXIO; 305 } 306 307 q = &qcq->q; 308 309 if (qcq->flags & IONIC_QCQ_F_INTR) { 310 struct ionic_dev *idev = &lif->ionic->idev; 311 312 cancel_work_sync(&qcq->dim.work); 313 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 314 IONIC_INTR_MASK_SET); 315 synchronize_irq(qcq->intr.vector); 316 irq_set_affinity_hint(qcq->intr.vector, NULL); 317 napi_disable(&qcq->napi); 318 } 319 320 /* If there was a previous fw communcation error, don't bother with 321 * sending the adminq command and just return the same error value. 322 */ 323 if (fw_err == -ETIMEDOUT || fw_err == -ENXIO) 324 return fw_err; 325 326 ctx.cmd.q_control.lif_index = cpu_to_le16(lif->index); 327 ctx.cmd.q_control.type = q->type; 328 ctx.cmd.q_control.index = cpu_to_le32(q->index); 329 dev_dbg(lif->ionic->dev, "q_disable.index %d q_disable.qtype %d\n", 330 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 331 332 return ionic_adminq_post_wait(lif, &ctx); 333 } 334 335 static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq) 336 { 337 struct ionic_dev *idev = &lif->ionic->idev; 338 339 if (!qcq) 340 return; 341 342 if (!(qcq->flags & IONIC_QCQ_F_INITED)) 343 return; 344 345 if (qcq->flags & IONIC_QCQ_F_INTR) { 346 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 347 IONIC_INTR_MASK_SET); 348 netif_napi_del(&qcq->napi); 349 } 350 351 qcq->flags &= ~IONIC_QCQ_F_INITED; 352 } 353 354 static void ionic_qcq_intr_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 355 { 356 if (!(qcq->flags & IONIC_QCQ_F_INTR) || qcq->intr.vector == 0) 357 return; 358 359 irq_set_affinity_hint(qcq->intr.vector, NULL); 360 devm_free_irq(lif->ionic->dev, qcq->intr.vector, &qcq->napi); 361 qcq->intr.vector = 0; 362 ionic_intr_free(lif->ionic, qcq->intr.index); 363 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 364 } 365 366 static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 367 { 368 struct device *dev = lif->ionic->dev; 369 370 if (!qcq) 371 return; 372 373 ionic_debugfs_del_qcq(qcq); 374 375 if (qcq->q_base) { 376 dma_free_coherent(dev, qcq->q_size, qcq->q_base, qcq->q_base_pa); 377 qcq->q_base = NULL; 378 qcq->q_base_pa = 0; 379 } 380 381 if (qcq->cq_base) { 382 dma_free_coherent(dev, qcq->cq_size, qcq->cq_base, qcq->cq_base_pa); 383 qcq->cq_base = NULL; 384 qcq->cq_base_pa = 0; 385 } 386 387 if (qcq->sg_base) { 388 dma_free_coherent(dev, qcq->sg_size, qcq->sg_base, qcq->sg_base_pa); 389 qcq->sg_base = NULL; 390 qcq->sg_base_pa = 0; 391 } 392 393 ionic_qcq_intr_free(lif, qcq); 394 395 if (qcq->cq.info) { 396 devm_kfree(dev, qcq->cq.info); 397 qcq->cq.info = NULL; 398 } 399 if (qcq->q.info) { 400 devm_kfree(dev, qcq->q.info); 401 qcq->q.info = NULL; 402 } 403 } 404 405 static void ionic_qcqs_free(struct ionic_lif *lif) 406 { 407 struct device *dev = lif->ionic->dev; 408 struct ionic_qcq *adminqcq; 409 unsigned long irqflags; 410 411 if (lif->notifyqcq) { 412 ionic_qcq_free(lif, lif->notifyqcq); 413 devm_kfree(dev, lif->notifyqcq); 414 lif->notifyqcq = NULL; 415 } 416 417 if (lif->adminqcq) { 418 spin_lock_irqsave(&lif->adminq_lock, irqflags); 419 adminqcq = READ_ONCE(lif->adminqcq); 420 lif->adminqcq = NULL; 421 spin_unlock_irqrestore(&lif->adminq_lock, irqflags); 422 if (adminqcq) { 423 ionic_qcq_free(lif, adminqcq); 424 devm_kfree(dev, adminqcq); 425 } 426 } 427 428 if (lif->rxqcqs) { 429 devm_kfree(dev, lif->rxqstats); 430 lif->rxqstats = NULL; 431 devm_kfree(dev, lif->rxqcqs); 432 lif->rxqcqs = NULL; 433 } 434 435 if (lif->txqcqs) { 436 devm_kfree(dev, lif->txqstats); 437 lif->txqstats = NULL; 438 devm_kfree(dev, lif->txqcqs); 439 lif->txqcqs = NULL; 440 } 441 } 442 443 static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq, 444 struct ionic_qcq *n_qcq) 445 { 446 if (WARN_ON(n_qcq->flags & IONIC_QCQ_F_INTR)) { 447 ionic_intr_free(n_qcq->cq.lif->ionic, n_qcq->intr.index); 448 n_qcq->flags &= ~IONIC_QCQ_F_INTR; 449 } 450 451 n_qcq->intr.vector = src_qcq->intr.vector; 452 n_qcq->intr.index = src_qcq->intr.index; 453 } 454 455 static int ionic_alloc_qcq_interrupt(struct ionic_lif *lif, struct ionic_qcq *qcq) 456 { 457 int err; 458 459 if (!(qcq->flags & IONIC_QCQ_F_INTR)) { 460 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 461 return 0; 462 } 463 464 err = ionic_intr_alloc(lif, &qcq->intr); 465 if (err) { 466 netdev_warn(lif->netdev, "no intr for %s: %d\n", 467 qcq->q.name, err); 468 goto err_out; 469 } 470 471 err = ionic_bus_get_irq(lif->ionic, qcq->intr.index); 472 if (err < 0) { 473 netdev_warn(lif->netdev, "no vector for %s: %d\n", 474 qcq->q.name, err); 475 goto err_out_free_intr; 476 } 477 qcq->intr.vector = err; 478 ionic_intr_mask_assert(lif->ionic->idev.intr_ctrl, qcq->intr.index, 479 IONIC_INTR_MASK_SET); 480 481 err = ionic_request_irq(lif, qcq); 482 if (err) { 483 netdev_warn(lif->netdev, "irq request failed %d\n", err); 484 goto err_out_free_intr; 485 } 486 487 /* try to get the irq on the local numa node first */ 488 qcq->intr.cpu = cpumask_local_spread(qcq->intr.index, 489 dev_to_node(lif->ionic->dev)); 490 if (qcq->intr.cpu != -1) 491 cpumask_set_cpu(qcq->intr.cpu, &qcq->intr.affinity_mask); 492 493 netdev_dbg(lif->netdev, "%s: Interrupt index %d\n", qcq->q.name, qcq->intr.index); 494 return 0; 495 496 err_out_free_intr: 497 ionic_intr_free(lif->ionic, qcq->intr.index); 498 err_out: 499 return err; 500 } 501 502 static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type, 503 unsigned int index, 504 const char *name, unsigned int flags, 505 unsigned int num_descs, unsigned int desc_size, 506 unsigned int cq_desc_size, 507 unsigned int sg_desc_size, 508 unsigned int pid, struct ionic_qcq **qcq) 509 { 510 struct ionic_dev *idev = &lif->ionic->idev; 511 struct device *dev = lif->ionic->dev; 512 void *q_base, *cq_base, *sg_base; 513 dma_addr_t cq_base_pa = 0; 514 dma_addr_t sg_base_pa = 0; 515 dma_addr_t q_base_pa = 0; 516 struct ionic_qcq *new; 517 int err; 518 519 *qcq = NULL; 520 521 new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL); 522 if (!new) { 523 netdev_err(lif->netdev, "Cannot allocate queue structure\n"); 524 err = -ENOMEM; 525 goto err_out; 526 } 527 528 new->q.dev = dev; 529 new->flags = flags; 530 531 new->q.info = devm_kcalloc(dev, num_descs, sizeof(*new->q.info), 532 GFP_KERNEL); 533 if (!new->q.info) { 534 netdev_err(lif->netdev, "Cannot allocate queue info\n"); 535 err = -ENOMEM; 536 goto err_out_free_qcq; 537 } 538 539 new->q.type = type; 540 new->q.max_sg_elems = lif->qtype_info[type].max_sg_elems; 541 542 err = ionic_q_init(lif, idev, &new->q, index, name, num_descs, 543 desc_size, sg_desc_size, pid); 544 if (err) { 545 netdev_err(lif->netdev, "Cannot initialize queue\n"); 546 goto err_out_free_q_info; 547 } 548 549 err = ionic_alloc_qcq_interrupt(lif, new); 550 if (err) 551 goto err_out; 552 553 new->cq.info = devm_kcalloc(dev, num_descs, sizeof(*new->cq.info), 554 GFP_KERNEL); 555 if (!new->cq.info) { 556 netdev_err(lif->netdev, "Cannot allocate completion queue info\n"); 557 err = -ENOMEM; 558 goto err_out_free_irq; 559 } 560 561 err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size); 562 if (err) { 563 netdev_err(lif->netdev, "Cannot initialize completion queue\n"); 564 goto err_out_free_cq_info; 565 } 566 567 if (flags & IONIC_QCQ_F_NOTIFYQ) { 568 int q_size, cq_size; 569 570 /* q & cq need to be contiguous in case of notifyq */ 571 q_size = ALIGN(num_descs * desc_size, PAGE_SIZE); 572 cq_size = ALIGN(num_descs * cq_desc_size, PAGE_SIZE); 573 574 new->q_size = PAGE_SIZE + q_size + cq_size; 575 new->q_base = dma_alloc_coherent(dev, new->q_size, 576 &new->q_base_pa, GFP_KERNEL); 577 if (!new->q_base) { 578 netdev_err(lif->netdev, "Cannot allocate qcq DMA memory\n"); 579 err = -ENOMEM; 580 goto err_out_free_cq_info; 581 } 582 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE); 583 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 584 ionic_q_map(&new->q, q_base, q_base_pa); 585 586 cq_base = PTR_ALIGN(q_base + q_size, PAGE_SIZE); 587 cq_base_pa = ALIGN(new->q_base_pa + q_size, PAGE_SIZE); 588 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 589 ionic_cq_bind(&new->cq, &new->q); 590 } else { 591 new->q_size = PAGE_SIZE + (num_descs * desc_size); 592 new->q_base = dma_alloc_coherent(dev, new->q_size, &new->q_base_pa, 593 GFP_KERNEL); 594 if (!new->q_base) { 595 netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n"); 596 err = -ENOMEM; 597 goto err_out_free_cq_info; 598 } 599 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE); 600 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 601 ionic_q_map(&new->q, q_base, q_base_pa); 602 603 new->cq_size = PAGE_SIZE + (num_descs * cq_desc_size); 604 new->cq_base = dma_alloc_coherent(dev, new->cq_size, &new->cq_base_pa, 605 GFP_KERNEL); 606 if (!new->cq_base) { 607 netdev_err(lif->netdev, "Cannot allocate cq DMA memory\n"); 608 err = -ENOMEM; 609 goto err_out_free_q; 610 } 611 cq_base = PTR_ALIGN(new->cq_base, PAGE_SIZE); 612 cq_base_pa = ALIGN(new->cq_base_pa, PAGE_SIZE); 613 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 614 ionic_cq_bind(&new->cq, &new->q); 615 } 616 617 if (flags & IONIC_QCQ_F_SG) { 618 new->sg_size = PAGE_SIZE + (num_descs * sg_desc_size); 619 new->sg_base = dma_alloc_coherent(dev, new->sg_size, &new->sg_base_pa, 620 GFP_KERNEL); 621 if (!new->sg_base) { 622 netdev_err(lif->netdev, "Cannot allocate sg DMA memory\n"); 623 err = -ENOMEM; 624 goto err_out_free_cq; 625 } 626 sg_base = PTR_ALIGN(new->sg_base, PAGE_SIZE); 627 sg_base_pa = ALIGN(new->sg_base_pa, PAGE_SIZE); 628 ionic_q_sg_map(&new->q, sg_base, sg_base_pa); 629 } 630 631 INIT_WORK(&new->dim.work, ionic_dim_work); 632 new->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 633 634 *qcq = new; 635 636 return 0; 637 638 err_out_free_cq: 639 dma_free_coherent(dev, new->cq_size, new->cq_base, new->cq_base_pa); 640 err_out_free_q: 641 dma_free_coherent(dev, new->q_size, new->q_base, new->q_base_pa); 642 err_out_free_cq_info: 643 devm_kfree(dev, new->cq.info); 644 err_out_free_irq: 645 if (flags & IONIC_QCQ_F_INTR) { 646 devm_free_irq(dev, new->intr.vector, &new->napi); 647 ionic_intr_free(lif->ionic, new->intr.index); 648 } 649 err_out_free_q_info: 650 devm_kfree(dev, new->q.info); 651 err_out_free_qcq: 652 devm_kfree(dev, new); 653 err_out: 654 dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err); 655 return err; 656 } 657 658 static int ionic_qcqs_alloc(struct ionic_lif *lif) 659 { 660 struct device *dev = lif->ionic->dev; 661 unsigned int flags; 662 int err; 663 664 flags = IONIC_QCQ_F_INTR; 665 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags, 666 IONIC_ADMINQ_LENGTH, 667 sizeof(struct ionic_admin_cmd), 668 sizeof(struct ionic_admin_comp), 669 0, lif->kern_pid, &lif->adminqcq); 670 if (err) 671 return err; 672 ionic_debugfs_add_qcq(lif, lif->adminqcq); 673 674 if (lif->ionic->nnqs_per_lif) { 675 flags = IONIC_QCQ_F_NOTIFYQ; 676 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq", 677 flags, IONIC_NOTIFYQ_LENGTH, 678 sizeof(struct ionic_notifyq_cmd), 679 sizeof(union ionic_notifyq_comp), 680 0, lif->kern_pid, &lif->notifyqcq); 681 if (err) 682 goto err_out; 683 ionic_debugfs_add_qcq(lif, lif->notifyqcq); 684 685 /* Let the notifyq ride on the adminq interrupt */ 686 ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq); 687 } 688 689 err = -ENOMEM; 690 lif->txqcqs = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif, 691 sizeof(*lif->txqcqs), GFP_KERNEL); 692 if (!lif->txqcqs) 693 goto err_out; 694 lif->rxqcqs = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif, 695 sizeof(*lif->rxqcqs), GFP_KERNEL); 696 if (!lif->rxqcqs) 697 goto err_out; 698 699 lif->txqstats = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif + 1, 700 sizeof(*lif->txqstats), GFP_KERNEL); 701 if (!lif->txqstats) 702 goto err_out; 703 lif->rxqstats = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif + 1, 704 sizeof(*lif->rxqstats), GFP_KERNEL); 705 if (!lif->rxqstats) 706 goto err_out; 707 708 return 0; 709 710 err_out: 711 ionic_qcqs_free(lif); 712 return err; 713 } 714 715 static void ionic_qcq_sanitize(struct ionic_qcq *qcq) 716 { 717 qcq->q.tail_idx = 0; 718 qcq->q.head_idx = 0; 719 qcq->cq.tail_idx = 0; 720 qcq->cq.done_color = 1; 721 memset(qcq->q_base, 0, qcq->q_size); 722 memset(qcq->cq_base, 0, qcq->cq_size); 723 memset(qcq->sg_base, 0, qcq->sg_size); 724 } 725 726 static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 727 { 728 struct device *dev = lif->ionic->dev; 729 struct ionic_queue *q = &qcq->q; 730 struct ionic_cq *cq = &qcq->cq; 731 struct ionic_admin_ctx ctx = { 732 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 733 .cmd.q_init = { 734 .opcode = IONIC_CMD_Q_INIT, 735 .lif_index = cpu_to_le16(lif->index), 736 .type = q->type, 737 .ver = lif->qtype_info[q->type].version, 738 .index = cpu_to_le32(q->index), 739 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 740 IONIC_QINIT_F_SG), 741 .pid = cpu_to_le16(q->pid), 742 .ring_size = ilog2(q->num_descs), 743 .ring_base = cpu_to_le64(q->base_pa), 744 .cq_ring_base = cpu_to_le64(cq->base_pa), 745 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 746 .features = cpu_to_le64(q->features), 747 }, 748 }; 749 unsigned int intr_index; 750 int err; 751 752 intr_index = qcq->intr.index; 753 754 ctx.cmd.q_init.intr_index = cpu_to_le16(intr_index); 755 756 dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid); 757 dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index); 758 dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 759 dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 760 dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 761 dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver); 762 dev_dbg(dev, "txq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 763 764 ionic_qcq_sanitize(qcq); 765 766 err = ionic_adminq_post_wait(lif, &ctx); 767 if (err) 768 return err; 769 770 q->hw_type = ctx.comp.q_init.hw_type; 771 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 772 q->dbval = IONIC_DBELL_QID(q->hw_index); 773 774 dev_dbg(dev, "txq->hw_type %d\n", q->hw_type); 775 dev_dbg(dev, "txq->hw_index %d\n", q->hw_index); 776 777 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 778 netif_napi_add(lif->netdev, &qcq->napi, ionic_tx_napi, 779 NAPI_POLL_WEIGHT); 780 781 qcq->flags |= IONIC_QCQ_F_INITED; 782 783 return 0; 784 } 785 786 static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 787 { 788 struct device *dev = lif->ionic->dev; 789 struct ionic_queue *q = &qcq->q; 790 struct ionic_cq *cq = &qcq->cq; 791 struct ionic_admin_ctx ctx = { 792 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 793 .cmd.q_init = { 794 .opcode = IONIC_CMD_Q_INIT, 795 .lif_index = cpu_to_le16(lif->index), 796 .type = q->type, 797 .ver = lif->qtype_info[q->type].version, 798 .index = cpu_to_le32(q->index), 799 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 800 IONIC_QINIT_F_SG), 801 .intr_index = cpu_to_le16(cq->bound_intr->index), 802 .pid = cpu_to_le16(q->pid), 803 .ring_size = ilog2(q->num_descs), 804 .ring_base = cpu_to_le64(q->base_pa), 805 .cq_ring_base = cpu_to_le64(cq->base_pa), 806 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 807 .features = cpu_to_le64(q->features), 808 }, 809 }; 810 int err; 811 812 dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid); 813 dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index); 814 dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 815 dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 816 dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 817 dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver); 818 dev_dbg(dev, "rxq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 819 820 ionic_qcq_sanitize(qcq); 821 822 err = ionic_adminq_post_wait(lif, &ctx); 823 if (err) 824 return err; 825 826 q->hw_type = ctx.comp.q_init.hw_type; 827 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 828 q->dbval = IONIC_DBELL_QID(q->hw_index); 829 830 dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type); 831 dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index); 832 833 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 834 netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi, 835 NAPI_POLL_WEIGHT); 836 else 837 netif_napi_add(lif->netdev, &qcq->napi, ionic_txrx_napi, 838 NAPI_POLL_WEIGHT); 839 840 qcq->flags |= IONIC_QCQ_F_INITED; 841 842 return 0; 843 } 844 845 int ionic_lif_create_hwstamp_txq(struct ionic_lif *lif) 846 { 847 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz; 848 unsigned int txq_i, flags; 849 struct ionic_qcq *txq; 850 u64 features; 851 int err; 852 853 if (lif->hwstamp_txq) 854 return 0; 855 856 features = IONIC_Q_F_2X_CQ_DESC | IONIC_TXQ_F_HWSTAMP; 857 858 num_desc = IONIC_MIN_TXRX_DESC; 859 desc_sz = sizeof(struct ionic_txq_desc); 860 comp_sz = 2 * sizeof(struct ionic_txq_comp); 861 862 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 863 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == sizeof(struct ionic_txq_sg_desc_v1)) 864 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 865 else 866 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 867 868 txq_i = lif->ionic->ntxqs_per_lif; 869 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 870 871 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, txq_i, "hwstamp_tx", flags, 872 num_desc, desc_sz, comp_sz, sg_desc_sz, 873 lif->kern_pid, &txq); 874 if (err) 875 goto err_qcq_alloc; 876 877 txq->q.features = features; 878 879 ionic_link_qcq_interrupts(lif->adminqcq, txq); 880 ionic_debugfs_add_qcq(lif, txq); 881 882 lif->hwstamp_txq = txq; 883 884 if (netif_running(lif->netdev)) { 885 err = ionic_lif_txq_init(lif, txq); 886 if (err) 887 goto err_qcq_init; 888 889 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 890 err = ionic_qcq_enable(txq); 891 if (err) 892 goto err_qcq_enable; 893 } 894 } 895 896 return 0; 897 898 err_qcq_enable: 899 ionic_lif_qcq_deinit(lif, txq); 900 err_qcq_init: 901 lif->hwstamp_txq = NULL; 902 ionic_debugfs_del_qcq(txq); 903 ionic_qcq_free(lif, txq); 904 devm_kfree(lif->ionic->dev, txq); 905 err_qcq_alloc: 906 return err; 907 } 908 909 int ionic_lif_create_hwstamp_rxq(struct ionic_lif *lif) 910 { 911 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz; 912 unsigned int rxq_i, flags; 913 struct ionic_qcq *rxq; 914 u64 features; 915 int err; 916 917 if (lif->hwstamp_rxq) 918 return 0; 919 920 features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP; 921 922 num_desc = IONIC_MIN_TXRX_DESC; 923 desc_sz = sizeof(struct ionic_rxq_desc); 924 comp_sz = 2 * sizeof(struct ionic_rxq_comp); 925 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 926 927 rxq_i = lif->ionic->nrxqs_per_lif; 928 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG; 929 930 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, rxq_i, "hwstamp_rx", flags, 931 num_desc, desc_sz, comp_sz, sg_desc_sz, 932 lif->kern_pid, &rxq); 933 if (err) 934 goto err_qcq_alloc; 935 936 rxq->q.features = features; 937 938 ionic_link_qcq_interrupts(lif->adminqcq, rxq); 939 ionic_debugfs_add_qcq(lif, rxq); 940 941 lif->hwstamp_rxq = rxq; 942 943 if (netif_running(lif->netdev)) { 944 err = ionic_lif_rxq_init(lif, rxq); 945 if (err) 946 goto err_qcq_init; 947 948 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 949 ionic_rx_fill(&rxq->q); 950 err = ionic_qcq_enable(rxq); 951 if (err) 952 goto err_qcq_enable; 953 } 954 } 955 956 return 0; 957 958 err_qcq_enable: 959 ionic_lif_qcq_deinit(lif, rxq); 960 err_qcq_init: 961 lif->hwstamp_rxq = NULL; 962 ionic_debugfs_del_qcq(rxq); 963 ionic_qcq_free(lif, rxq); 964 devm_kfree(lif->ionic->dev, rxq); 965 err_qcq_alloc: 966 return err; 967 } 968 969 int ionic_lif_config_hwstamp_rxq_all(struct ionic_lif *lif, bool rx_all) 970 { 971 struct ionic_queue_params qparam; 972 973 ionic_init_queue_params(lif, &qparam); 974 975 if (rx_all) 976 qparam.rxq_features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP; 977 else 978 qparam.rxq_features = 0; 979 980 /* if we're not running, just set the values and return */ 981 if (!netif_running(lif->netdev)) { 982 lif->rxq_features = qparam.rxq_features; 983 return 0; 984 } 985 986 return ionic_reconfigure_queues(lif, &qparam); 987 } 988 989 int ionic_lif_set_hwstamp_txmode(struct ionic_lif *lif, u16 txstamp_mode) 990 { 991 struct ionic_admin_ctx ctx = { 992 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 993 .cmd.lif_setattr = { 994 .opcode = IONIC_CMD_LIF_SETATTR, 995 .index = cpu_to_le16(lif->index), 996 .attr = IONIC_LIF_ATTR_TXSTAMP, 997 .txstamp_mode = cpu_to_le16(txstamp_mode), 998 }, 999 }; 1000 1001 return ionic_adminq_post_wait(lif, &ctx); 1002 } 1003 1004 static void ionic_lif_del_hwstamp_rxfilt(struct ionic_lif *lif) 1005 { 1006 struct ionic_admin_ctx ctx = { 1007 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1008 .cmd.rx_filter_del = { 1009 .opcode = IONIC_CMD_RX_FILTER_DEL, 1010 .lif_index = cpu_to_le16(lif->index), 1011 }, 1012 }; 1013 struct ionic_rx_filter *f; 1014 u32 filter_id; 1015 int err; 1016 1017 spin_lock_bh(&lif->rx_filters.lock); 1018 1019 f = ionic_rx_filter_rxsteer(lif); 1020 if (!f) { 1021 spin_unlock_bh(&lif->rx_filters.lock); 1022 return; 1023 } 1024 1025 filter_id = f->filter_id; 1026 ionic_rx_filter_free(lif, f); 1027 1028 spin_unlock_bh(&lif->rx_filters.lock); 1029 1030 netdev_dbg(lif->netdev, "rx_filter del RXSTEER (id %d)\n", filter_id); 1031 1032 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(filter_id); 1033 1034 err = ionic_adminq_post_wait(lif, &ctx); 1035 if (err && err != -EEXIST) 1036 netdev_dbg(lif->netdev, "failed to delete rx_filter RXSTEER (id %d)\n", filter_id); 1037 } 1038 1039 static int ionic_lif_add_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class) 1040 { 1041 struct ionic_admin_ctx ctx = { 1042 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1043 .cmd.rx_filter_add = { 1044 .opcode = IONIC_CMD_RX_FILTER_ADD, 1045 .lif_index = cpu_to_le16(lif->index), 1046 .match = cpu_to_le16(IONIC_RX_FILTER_STEER_PKTCLASS), 1047 .pkt_class = cpu_to_le64(pkt_class), 1048 }, 1049 }; 1050 u8 qtype; 1051 u32 qid; 1052 int err; 1053 1054 if (!lif->hwstamp_rxq) 1055 return -EINVAL; 1056 1057 qtype = lif->hwstamp_rxq->q.type; 1058 ctx.cmd.rx_filter_add.qtype = qtype; 1059 1060 qid = lif->hwstamp_rxq->q.index; 1061 ctx.cmd.rx_filter_add.qid = cpu_to_le32(qid); 1062 1063 netdev_dbg(lif->netdev, "rx_filter add RXSTEER\n"); 1064 err = ionic_adminq_post_wait(lif, &ctx); 1065 if (err && err != -EEXIST) 1066 return err; 1067 1068 spin_lock_bh(&lif->rx_filters.lock); 1069 err = ionic_rx_filter_save(lif, 0, qid, 0, &ctx, IONIC_FILTER_STATE_SYNCED); 1070 spin_unlock_bh(&lif->rx_filters.lock); 1071 1072 return err; 1073 } 1074 1075 int ionic_lif_set_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class) 1076 { 1077 ionic_lif_del_hwstamp_rxfilt(lif); 1078 1079 if (!pkt_class) 1080 return 0; 1081 1082 return ionic_lif_add_hwstamp_rxfilt(lif, pkt_class); 1083 } 1084 1085 static bool ionic_notifyq_service(struct ionic_cq *cq, 1086 struct ionic_cq_info *cq_info) 1087 { 1088 union ionic_notifyq_comp *comp = cq_info->cq_desc; 1089 struct ionic_deferred_work *work; 1090 struct net_device *netdev; 1091 struct ionic_queue *q; 1092 struct ionic_lif *lif; 1093 u64 eid; 1094 1095 q = cq->bound_q; 1096 lif = q->info[0].cb_arg; 1097 netdev = lif->netdev; 1098 eid = le64_to_cpu(comp->event.eid); 1099 1100 /* Have we run out of new completions to process? */ 1101 if ((s64)(eid - lif->last_eid) <= 0) 1102 return false; 1103 1104 lif->last_eid = eid; 1105 1106 dev_dbg(lif->ionic->dev, "notifyq event:\n"); 1107 dynamic_hex_dump("event ", DUMP_PREFIX_OFFSET, 16, 1, 1108 comp, sizeof(*comp), true); 1109 1110 switch (le16_to_cpu(comp->event.ecode)) { 1111 case IONIC_EVENT_LINK_CHANGE: 1112 ionic_link_status_check_request(lif, CAN_NOT_SLEEP); 1113 break; 1114 case IONIC_EVENT_RESET: 1115 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1116 if (!work) { 1117 netdev_err(lif->netdev, "Reset event dropped\n"); 1118 } else { 1119 work->type = IONIC_DW_TYPE_LIF_RESET; 1120 ionic_lif_deferred_enqueue(&lif->deferred, work); 1121 } 1122 break; 1123 default: 1124 netdev_warn(netdev, "Notifyq event ecode=%d eid=%lld\n", 1125 comp->event.ecode, eid); 1126 break; 1127 } 1128 1129 return true; 1130 } 1131 1132 static bool ionic_adminq_service(struct ionic_cq *cq, 1133 struct ionic_cq_info *cq_info) 1134 { 1135 struct ionic_admin_comp *comp = cq_info->cq_desc; 1136 1137 if (!color_match(comp->color, cq->done_color)) 1138 return false; 1139 1140 ionic_q_service(cq->bound_q, cq_info, le16_to_cpu(comp->comp_index)); 1141 1142 return true; 1143 } 1144 1145 static int ionic_adminq_napi(struct napi_struct *napi, int budget) 1146 { 1147 struct ionic_intr_info *intr = napi_to_cq(napi)->bound_intr; 1148 struct ionic_lif *lif = napi_to_cq(napi)->lif; 1149 struct ionic_dev *idev = &lif->ionic->idev; 1150 unsigned long irqflags; 1151 unsigned int flags = 0; 1152 int rx_work = 0; 1153 int tx_work = 0; 1154 int n_work = 0; 1155 int a_work = 0; 1156 int work_done; 1157 int credits; 1158 1159 if (lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED) 1160 n_work = ionic_cq_service(&lif->notifyqcq->cq, budget, 1161 ionic_notifyq_service, NULL, NULL); 1162 1163 spin_lock_irqsave(&lif->adminq_lock, irqflags); 1164 if (lif->adminqcq && lif->adminqcq->flags & IONIC_QCQ_F_INITED) 1165 a_work = ionic_cq_service(&lif->adminqcq->cq, budget, 1166 ionic_adminq_service, NULL, NULL); 1167 spin_unlock_irqrestore(&lif->adminq_lock, irqflags); 1168 1169 if (lif->hwstamp_rxq) 1170 rx_work = ionic_cq_service(&lif->hwstamp_rxq->cq, budget, 1171 ionic_rx_service, NULL, NULL); 1172 1173 if (lif->hwstamp_txq) 1174 tx_work = ionic_cq_service(&lif->hwstamp_txq->cq, budget, 1175 ionic_tx_service, NULL, NULL); 1176 1177 work_done = max(max(n_work, a_work), max(rx_work, tx_work)); 1178 if (work_done < budget && napi_complete_done(napi, work_done)) { 1179 flags |= IONIC_INTR_CRED_UNMASK; 1180 intr->rearm_count++; 1181 } 1182 1183 if (work_done || flags) { 1184 flags |= IONIC_INTR_CRED_RESET_COALESCE; 1185 credits = n_work + a_work + rx_work + tx_work; 1186 ionic_intr_credits(idev->intr_ctrl, intr->index, credits, flags); 1187 } 1188 1189 return work_done; 1190 } 1191 1192 void ionic_get_stats64(struct net_device *netdev, 1193 struct rtnl_link_stats64 *ns) 1194 { 1195 struct ionic_lif *lif = netdev_priv(netdev); 1196 struct ionic_lif_stats *ls; 1197 1198 memset(ns, 0, sizeof(*ns)); 1199 ls = &lif->info->stats; 1200 1201 ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) + 1202 le64_to_cpu(ls->rx_mcast_packets) + 1203 le64_to_cpu(ls->rx_bcast_packets); 1204 1205 ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) + 1206 le64_to_cpu(ls->tx_mcast_packets) + 1207 le64_to_cpu(ls->tx_bcast_packets); 1208 1209 ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) + 1210 le64_to_cpu(ls->rx_mcast_bytes) + 1211 le64_to_cpu(ls->rx_bcast_bytes); 1212 1213 ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) + 1214 le64_to_cpu(ls->tx_mcast_bytes) + 1215 le64_to_cpu(ls->tx_bcast_bytes); 1216 1217 ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) + 1218 le64_to_cpu(ls->rx_mcast_drop_packets) + 1219 le64_to_cpu(ls->rx_bcast_drop_packets); 1220 1221 ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) + 1222 le64_to_cpu(ls->tx_mcast_drop_packets) + 1223 le64_to_cpu(ls->tx_bcast_drop_packets); 1224 1225 ns->multicast = le64_to_cpu(ls->rx_mcast_packets); 1226 1227 ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty); 1228 1229 ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) + 1230 le64_to_cpu(ls->rx_queue_disabled) + 1231 le64_to_cpu(ls->rx_desc_fetch_error) + 1232 le64_to_cpu(ls->rx_desc_data_error); 1233 1234 ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) + 1235 le64_to_cpu(ls->tx_queue_disabled) + 1236 le64_to_cpu(ls->tx_desc_fetch_error) + 1237 le64_to_cpu(ls->tx_desc_data_error); 1238 1239 ns->rx_errors = ns->rx_over_errors + 1240 ns->rx_missed_errors; 1241 1242 ns->tx_errors = ns->tx_aborted_errors; 1243 } 1244 1245 static int ionic_addr_add(struct net_device *netdev, const u8 *addr) 1246 { 1247 return ionic_lif_list_addr(netdev_priv(netdev), addr, ADD_ADDR); 1248 } 1249 1250 static int ionic_addr_del(struct net_device *netdev, const u8 *addr) 1251 { 1252 /* Don't delete our own address from the uc list */ 1253 if (ether_addr_equal(addr, netdev->dev_addr)) 1254 return 0; 1255 1256 return ionic_lif_list_addr(netdev_priv(netdev), addr, DEL_ADDR); 1257 } 1258 1259 void ionic_lif_rx_mode(struct ionic_lif *lif) 1260 { 1261 struct net_device *netdev = lif->netdev; 1262 unsigned int nfilters; 1263 unsigned int nd_flags; 1264 char buf[128]; 1265 u16 rx_mode; 1266 int i; 1267 #define REMAIN(__x) (sizeof(buf) - (__x)) 1268 1269 mutex_lock(&lif->config_lock); 1270 1271 /* grab the flags once for local use */ 1272 nd_flags = netdev->flags; 1273 1274 rx_mode = IONIC_RX_MODE_F_UNICAST; 1275 rx_mode |= (nd_flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0; 1276 rx_mode |= (nd_flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0; 1277 rx_mode |= (nd_flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0; 1278 rx_mode |= (nd_flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0; 1279 1280 /* sync the filters */ 1281 ionic_rx_filter_sync(lif); 1282 1283 /* check for overflow state 1284 * if so, we track that we overflowed and enable NIC PROMISC 1285 * else if the overflow is set and not needed 1286 * we remove our overflow flag and check the netdev flags 1287 * to see if we can disable NIC PROMISC 1288 */ 1289 nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters); 1290 1291 if (((lif->nucast + lif->nmcast) >= nfilters) || 1292 (lif->max_vlans && lif->nvlans >= lif->max_vlans)) { 1293 rx_mode |= IONIC_RX_MODE_F_PROMISC; 1294 rx_mode |= IONIC_RX_MODE_F_ALLMULTI; 1295 } else { 1296 if (!(nd_flags & IFF_PROMISC)) 1297 rx_mode &= ~IONIC_RX_MODE_F_PROMISC; 1298 if (!(nd_flags & IFF_ALLMULTI)) 1299 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI; 1300 } 1301 1302 i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:", 1303 lif->rx_mode, rx_mode); 1304 if (rx_mode & IONIC_RX_MODE_F_UNICAST) 1305 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST"); 1306 if (rx_mode & IONIC_RX_MODE_F_MULTICAST) 1307 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST"); 1308 if (rx_mode & IONIC_RX_MODE_F_BROADCAST) 1309 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST"); 1310 if (rx_mode & IONIC_RX_MODE_F_PROMISC) 1311 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC"); 1312 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI) 1313 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI"); 1314 if (rx_mode & IONIC_RX_MODE_F_RDMA_SNIFFER) 1315 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_RDMA_SNIFFER"); 1316 netdev_dbg(netdev, "lif%d %s\n", lif->index, buf); 1317 1318 if (lif->rx_mode != rx_mode) { 1319 struct ionic_admin_ctx ctx = { 1320 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1321 .cmd.rx_mode_set = { 1322 .opcode = IONIC_CMD_RX_MODE_SET, 1323 .lif_index = cpu_to_le16(lif->index), 1324 }, 1325 }; 1326 int err; 1327 1328 ctx.cmd.rx_mode_set.rx_mode = cpu_to_le16(rx_mode); 1329 err = ionic_adminq_post_wait(lif, &ctx); 1330 if (err) 1331 netdev_warn(netdev, "set rx_mode 0x%04x failed: %d\n", 1332 rx_mode, err); 1333 else 1334 lif->rx_mode = rx_mode; 1335 } 1336 1337 mutex_unlock(&lif->config_lock); 1338 } 1339 1340 static void ionic_ndo_set_rx_mode(struct net_device *netdev) 1341 { 1342 struct ionic_lif *lif = netdev_priv(netdev); 1343 struct ionic_deferred_work *work; 1344 1345 /* Sync the kernel filter list with the driver filter list */ 1346 __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del); 1347 __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del); 1348 1349 /* Shove off the rest of the rxmode work to the work task 1350 * which will include syncing the filters to the firmware. 1351 */ 1352 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1353 if (!work) { 1354 netdev_err(lif->netdev, "rxmode change dropped\n"); 1355 return; 1356 } 1357 work->type = IONIC_DW_TYPE_RX_MODE; 1358 netdev_dbg(lif->netdev, "deferred: rx_mode\n"); 1359 ionic_lif_deferred_enqueue(&lif->deferred, work); 1360 } 1361 1362 static __le64 ionic_netdev_features_to_nic(netdev_features_t features) 1363 { 1364 u64 wanted = 0; 1365 1366 if (features & NETIF_F_HW_VLAN_CTAG_TX) 1367 wanted |= IONIC_ETH_HW_VLAN_TX_TAG; 1368 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1369 wanted |= IONIC_ETH_HW_VLAN_RX_STRIP; 1370 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1371 wanted |= IONIC_ETH_HW_VLAN_RX_FILTER; 1372 if (features & NETIF_F_RXHASH) 1373 wanted |= IONIC_ETH_HW_RX_HASH; 1374 if (features & NETIF_F_RXCSUM) 1375 wanted |= IONIC_ETH_HW_RX_CSUM; 1376 if (features & NETIF_F_SG) 1377 wanted |= IONIC_ETH_HW_TX_SG; 1378 if (features & NETIF_F_HW_CSUM) 1379 wanted |= IONIC_ETH_HW_TX_CSUM; 1380 if (features & NETIF_F_TSO) 1381 wanted |= IONIC_ETH_HW_TSO; 1382 if (features & NETIF_F_TSO6) 1383 wanted |= IONIC_ETH_HW_TSO_IPV6; 1384 if (features & NETIF_F_TSO_ECN) 1385 wanted |= IONIC_ETH_HW_TSO_ECN; 1386 if (features & NETIF_F_GSO_GRE) 1387 wanted |= IONIC_ETH_HW_TSO_GRE; 1388 if (features & NETIF_F_GSO_GRE_CSUM) 1389 wanted |= IONIC_ETH_HW_TSO_GRE_CSUM; 1390 if (features & NETIF_F_GSO_IPXIP4) 1391 wanted |= IONIC_ETH_HW_TSO_IPXIP4; 1392 if (features & NETIF_F_GSO_IPXIP6) 1393 wanted |= IONIC_ETH_HW_TSO_IPXIP6; 1394 if (features & NETIF_F_GSO_UDP_TUNNEL) 1395 wanted |= IONIC_ETH_HW_TSO_UDP; 1396 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) 1397 wanted |= IONIC_ETH_HW_TSO_UDP_CSUM; 1398 1399 return cpu_to_le64(wanted); 1400 } 1401 1402 static int ionic_set_nic_features(struct ionic_lif *lif, 1403 netdev_features_t features) 1404 { 1405 struct device *dev = lif->ionic->dev; 1406 struct ionic_admin_ctx ctx = { 1407 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1408 .cmd.lif_setattr = { 1409 .opcode = IONIC_CMD_LIF_SETATTR, 1410 .index = cpu_to_le16(lif->index), 1411 .attr = IONIC_LIF_ATTR_FEATURES, 1412 }, 1413 }; 1414 u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG | 1415 IONIC_ETH_HW_VLAN_RX_STRIP | 1416 IONIC_ETH_HW_VLAN_RX_FILTER; 1417 u64 old_hw_features; 1418 int err; 1419 1420 ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features); 1421 1422 if (lif->phc) 1423 ctx.cmd.lif_setattr.features |= cpu_to_le64(IONIC_ETH_HW_TIMESTAMP); 1424 1425 err = ionic_adminq_post_wait(lif, &ctx); 1426 if (err) 1427 return err; 1428 1429 old_hw_features = lif->hw_features; 1430 lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features & 1431 ctx.comp.lif_setattr.features); 1432 1433 if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH) 1434 ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1435 1436 if ((vlan_flags & features) && 1437 !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features))) 1438 dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n"); 1439 1440 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1441 dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n"); 1442 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1443 dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n"); 1444 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1445 dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n"); 1446 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1447 dev_dbg(dev, "feature ETH_HW_RX_HASH\n"); 1448 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1449 dev_dbg(dev, "feature ETH_HW_TX_SG\n"); 1450 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1451 dev_dbg(dev, "feature ETH_HW_TX_CSUM\n"); 1452 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1453 dev_dbg(dev, "feature ETH_HW_RX_CSUM\n"); 1454 if (lif->hw_features & IONIC_ETH_HW_TSO) 1455 dev_dbg(dev, "feature ETH_HW_TSO\n"); 1456 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1457 dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n"); 1458 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1459 dev_dbg(dev, "feature ETH_HW_TSO_ECN\n"); 1460 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1461 dev_dbg(dev, "feature ETH_HW_TSO_GRE\n"); 1462 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1463 dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n"); 1464 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1465 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n"); 1466 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1467 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n"); 1468 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1469 dev_dbg(dev, "feature ETH_HW_TSO_UDP\n"); 1470 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1471 dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n"); 1472 if (lif->hw_features & IONIC_ETH_HW_TIMESTAMP) 1473 dev_dbg(dev, "feature ETH_HW_TIMESTAMP\n"); 1474 1475 return 0; 1476 } 1477 1478 static int ionic_init_nic_features(struct ionic_lif *lif) 1479 { 1480 struct net_device *netdev = lif->netdev; 1481 netdev_features_t features; 1482 int err; 1483 1484 /* set up what we expect to support by default */ 1485 features = NETIF_F_HW_VLAN_CTAG_TX | 1486 NETIF_F_HW_VLAN_CTAG_RX | 1487 NETIF_F_HW_VLAN_CTAG_FILTER | 1488 NETIF_F_SG | 1489 NETIF_F_HW_CSUM | 1490 NETIF_F_RXCSUM | 1491 NETIF_F_TSO | 1492 NETIF_F_TSO6 | 1493 NETIF_F_TSO_ECN; 1494 1495 if (lif->nxqs > 1) 1496 features |= NETIF_F_RXHASH; 1497 1498 err = ionic_set_nic_features(lif, features); 1499 if (err) 1500 return err; 1501 1502 /* tell the netdev what we actually can support */ 1503 netdev->features |= NETIF_F_HIGHDMA; 1504 1505 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1506 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 1507 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1508 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 1509 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1510 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1511 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1512 netdev->hw_features |= NETIF_F_RXHASH; 1513 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1514 netdev->hw_features |= NETIF_F_SG; 1515 1516 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1517 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 1518 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1519 netdev->hw_enc_features |= NETIF_F_RXCSUM; 1520 if (lif->hw_features & IONIC_ETH_HW_TSO) 1521 netdev->hw_enc_features |= NETIF_F_TSO; 1522 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1523 netdev->hw_enc_features |= NETIF_F_TSO6; 1524 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1525 netdev->hw_enc_features |= NETIF_F_TSO_ECN; 1526 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1527 netdev->hw_enc_features |= NETIF_F_GSO_GRE; 1528 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1529 netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM; 1530 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1531 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4; 1532 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1533 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6; 1534 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1535 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL; 1536 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1537 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 1538 1539 netdev->hw_features |= netdev->hw_enc_features; 1540 netdev->features |= netdev->hw_features; 1541 netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES; 1542 1543 netdev->priv_flags |= IFF_UNICAST_FLT | 1544 IFF_LIVE_ADDR_CHANGE; 1545 1546 return 0; 1547 } 1548 1549 static int ionic_set_features(struct net_device *netdev, 1550 netdev_features_t features) 1551 { 1552 struct ionic_lif *lif = netdev_priv(netdev); 1553 int err; 1554 1555 netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n", 1556 __func__, (u64)lif->netdev->features, (u64)features); 1557 1558 err = ionic_set_nic_features(lif, features); 1559 1560 return err; 1561 } 1562 1563 static int ionic_set_mac_address(struct net_device *netdev, void *sa) 1564 { 1565 struct sockaddr *addr = sa; 1566 u8 *mac; 1567 int err; 1568 1569 mac = (u8 *)addr->sa_data; 1570 if (ether_addr_equal(netdev->dev_addr, mac)) 1571 return 0; 1572 1573 err = eth_prepare_mac_addr_change(netdev, addr); 1574 if (err) 1575 return err; 1576 1577 if (!is_zero_ether_addr(netdev->dev_addr)) { 1578 netdev_info(netdev, "deleting mac addr %pM\n", 1579 netdev->dev_addr); 1580 ionic_lif_addr_del(netdev_priv(netdev), netdev->dev_addr); 1581 } 1582 1583 eth_commit_mac_addr_change(netdev, addr); 1584 netdev_info(netdev, "updating mac addr %pM\n", mac); 1585 1586 return ionic_lif_addr_add(netdev_priv(netdev), mac); 1587 } 1588 1589 static void ionic_stop_queues_reconfig(struct ionic_lif *lif) 1590 { 1591 /* Stop and clean the queues before reconfiguration */ 1592 netif_device_detach(lif->netdev); 1593 ionic_stop_queues(lif); 1594 ionic_txrx_deinit(lif); 1595 } 1596 1597 static int ionic_start_queues_reconfig(struct ionic_lif *lif) 1598 { 1599 int err; 1600 1601 /* Re-init the queues after reconfiguration */ 1602 1603 /* The only way txrx_init can fail here is if communication 1604 * with FW is suddenly broken. There's not much we can do 1605 * at this point - error messages have already been printed, 1606 * so we can continue on and the user can eventually do a 1607 * DOWN and UP to try to reset and clear the issue. 1608 */ 1609 err = ionic_txrx_init(lif); 1610 ionic_link_status_check_request(lif, CAN_NOT_SLEEP); 1611 netif_device_attach(lif->netdev); 1612 1613 return err; 1614 } 1615 1616 static int ionic_change_mtu(struct net_device *netdev, int new_mtu) 1617 { 1618 struct ionic_lif *lif = netdev_priv(netdev); 1619 struct ionic_admin_ctx ctx = { 1620 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1621 .cmd.lif_setattr = { 1622 .opcode = IONIC_CMD_LIF_SETATTR, 1623 .index = cpu_to_le16(lif->index), 1624 .attr = IONIC_LIF_ATTR_MTU, 1625 .mtu = cpu_to_le32(new_mtu), 1626 }, 1627 }; 1628 int err; 1629 1630 err = ionic_adminq_post_wait(lif, &ctx); 1631 if (err) 1632 return err; 1633 1634 /* if we're not running, nothing more to do */ 1635 if (!netif_running(netdev)) { 1636 netdev->mtu = new_mtu; 1637 return 0; 1638 } 1639 1640 mutex_lock(&lif->queue_lock); 1641 ionic_stop_queues_reconfig(lif); 1642 netdev->mtu = new_mtu; 1643 err = ionic_start_queues_reconfig(lif); 1644 mutex_unlock(&lif->queue_lock); 1645 1646 return err; 1647 } 1648 1649 static void ionic_tx_timeout_work(struct work_struct *ws) 1650 { 1651 struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work); 1652 1653 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 1654 return; 1655 1656 /* if we were stopped before this scheduled job was launched, 1657 * don't bother the queues as they are already stopped. 1658 */ 1659 if (!netif_running(lif->netdev)) 1660 return; 1661 1662 mutex_lock(&lif->queue_lock); 1663 ionic_stop_queues_reconfig(lif); 1664 ionic_start_queues_reconfig(lif); 1665 mutex_unlock(&lif->queue_lock); 1666 } 1667 1668 static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1669 { 1670 struct ionic_lif *lif = netdev_priv(netdev); 1671 1672 netdev_info(lif->netdev, "Tx Timeout triggered - txq %d\n", txqueue); 1673 schedule_work(&lif->tx_timeout_work); 1674 } 1675 1676 static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, 1677 u16 vid) 1678 { 1679 struct ionic_lif *lif = netdev_priv(netdev); 1680 int err; 1681 1682 err = ionic_lif_vlan_add(lif, vid); 1683 if (err) 1684 return err; 1685 1686 ionic_lif_rx_mode(lif); 1687 1688 return 0; 1689 } 1690 1691 static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, 1692 u16 vid) 1693 { 1694 struct ionic_lif *lif = netdev_priv(netdev); 1695 int err; 1696 1697 err = ionic_lif_vlan_del(lif, vid); 1698 if (err) 1699 return err; 1700 1701 ionic_lif_rx_mode(lif); 1702 1703 return 0; 1704 } 1705 1706 int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types, 1707 const u8 *key, const u32 *indir) 1708 { 1709 struct ionic_admin_ctx ctx = { 1710 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1711 .cmd.lif_setattr = { 1712 .opcode = IONIC_CMD_LIF_SETATTR, 1713 .attr = IONIC_LIF_ATTR_RSS, 1714 .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa), 1715 }, 1716 }; 1717 unsigned int i, tbl_sz; 1718 1719 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) { 1720 lif->rss_types = types; 1721 ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types); 1722 } 1723 1724 if (key) 1725 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE); 1726 1727 if (indir) { 1728 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1729 for (i = 0; i < tbl_sz; i++) 1730 lif->rss_ind_tbl[i] = indir[i]; 1731 } 1732 1733 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key, 1734 IONIC_RSS_HASH_KEY_SIZE); 1735 1736 return ionic_adminq_post_wait(lif, &ctx); 1737 } 1738 1739 static int ionic_lif_rss_init(struct ionic_lif *lif) 1740 { 1741 unsigned int tbl_sz; 1742 unsigned int i; 1743 1744 lif->rss_types = IONIC_RSS_TYPE_IPV4 | 1745 IONIC_RSS_TYPE_IPV4_TCP | 1746 IONIC_RSS_TYPE_IPV4_UDP | 1747 IONIC_RSS_TYPE_IPV6 | 1748 IONIC_RSS_TYPE_IPV6_TCP | 1749 IONIC_RSS_TYPE_IPV6_UDP; 1750 1751 /* Fill indirection table with 'default' values */ 1752 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1753 for (i = 0; i < tbl_sz; i++) 1754 lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs); 1755 1756 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1757 } 1758 1759 static void ionic_lif_rss_deinit(struct ionic_lif *lif) 1760 { 1761 int tbl_sz; 1762 1763 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1764 memset(lif->rss_ind_tbl, 0, tbl_sz); 1765 memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE); 1766 1767 ionic_lif_rss_config(lif, 0x0, NULL, NULL); 1768 } 1769 1770 static void ionic_lif_quiesce(struct ionic_lif *lif) 1771 { 1772 struct ionic_admin_ctx ctx = { 1773 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1774 .cmd.lif_setattr = { 1775 .opcode = IONIC_CMD_LIF_SETATTR, 1776 .index = cpu_to_le16(lif->index), 1777 .attr = IONIC_LIF_ATTR_STATE, 1778 .state = IONIC_LIF_QUIESCE, 1779 }, 1780 }; 1781 int err; 1782 1783 err = ionic_adminq_post_wait(lif, &ctx); 1784 if (err) 1785 netdev_err(lif->netdev, "lif quiesce failed %d\n", err); 1786 } 1787 1788 static void ionic_txrx_disable(struct ionic_lif *lif) 1789 { 1790 unsigned int i; 1791 int err = 0; 1792 1793 if (lif->txqcqs) { 1794 for (i = 0; i < lif->nxqs; i++) 1795 err = ionic_qcq_disable(lif, lif->txqcqs[i], err); 1796 } 1797 1798 if (lif->hwstamp_txq) 1799 err = ionic_qcq_disable(lif, lif->hwstamp_txq, err); 1800 1801 if (lif->rxqcqs) { 1802 for (i = 0; i < lif->nxqs; i++) 1803 err = ionic_qcq_disable(lif, lif->rxqcqs[i], err); 1804 } 1805 1806 if (lif->hwstamp_rxq) 1807 err = ionic_qcq_disable(lif, lif->hwstamp_rxq, err); 1808 1809 ionic_lif_quiesce(lif); 1810 } 1811 1812 static void ionic_txrx_deinit(struct ionic_lif *lif) 1813 { 1814 unsigned int i; 1815 1816 if (lif->txqcqs) { 1817 for (i = 0; i < lif->nxqs && lif->txqcqs[i]; i++) { 1818 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 1819 ionic_tx_flush(&lif->txqcqs[i]->cq); 1820 ionic_tx_empty(&lif->txqcqs[i]->q); 1821 } 1822 } 1823 1824 if (lif->rxqcqs) { 1825 for (i = 0; i < lif->nxqs && lif->rxqcqs[i]; i++) { 1826 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 1827 ionic_rx_empty(&lif->rxqcqs[i]->q); 1828 } 1829 } 1830 lif->rx_mode = 0; 1831 1832 if (lif->hwstamp_txq) { 1833 ionic_lif_qcq_deinit(lif, lif->hwstamp_txq); 1834 ionic_tx_flush(&lif->hwstamp_txq->cq); 1835 ionic_tx_empty(&lif->hwstamp_txq->q); 1836 } 1837 1838 if (lif->hwstamp_rxq) { 1839 ionic_lif_qcq_deinit(lif, lif->hwstamp_rxq); 1840 ionic_rx_empty(&lif->hwstamp_rxq->q); 1841 } 1842 } 1843 1844 static void ionic_txrx_free(struct ionic_lif *lif) 1845 { 1846 unsigned int i; 1847 1848 if (lif->txqcqs) { 1849 for (i = 0; i < lif->ionic->ntxqs_per_lif && lif->txqcqs[i]; i++) { 1850 ionic_qcq_free(lif, lif->txqcqs[i]); 1851 devm_kfree(lif->ionic->dev, lif->txqcqs[i]); 1852 lif->txqcqs[i] = NULL; 1853 } 1854 } 1855 1856 if (lif->rxqcqs) { 1857 for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) { 1858 ionic_qcq_free(lif, lif->rxqcqs[i]); 1859 devm_kfree(lif->ionic->dev, lif->rxqcqs[i]); 1860 lif->rxqcqs[i] = NULL; 1861 } 1862 } 1863 1864 if (lif->hwstamp_txq) { 1865 ionic_qcq_free(lif, lif->hwstamp_txq); 1866 devm_kfree(lif->ionic->dev, lif->hwstamp_txq); 1867 lif->hwstamp_txq = NULL; 1868 } 1869 1870 if (lif->hwstamp_rxq) { 1871 ionic_qcq_free(lif, lif->hwstamp_rxq); 1872 devm_kfree(lif->ionic->dev, lif->hwstamp_rxq); 1873 lif->hwstamp_rxq = NULL; 1874 } 1875 } 1876 1877 static int ionic_txrx_alloc(struct ionic_lif *lif) 1878 { 1879 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz; 1880 unsigned int flags, i; 1881 int err = 0; 1882 1883 num_desc = lif->ntxq_descs; 1884 desc_sz = sizeof(struct ionic_txq_desc); 1885 comp_sz = sizeof(struct ionic_txq_comp); 1886 1887 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 1888 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 1889 sizeof(struct ionic_txq_sg_desc_v1)) 1890 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 1891 else 1892 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 1893 1894 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 1895 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 1896 flags |= IONIC_QCQ_F_INTR; 1897 for (i = 0; i < lif->nxqs; i++) { 1898 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 1899 num_desc, desc_sz, comp_sz, sg_desc_sz, 1900 lif->kern_pid, &lif->txqcqs[i]); 1901 if (err) 1902 goto err_out; 1903 1904 if (flags & IONIC_QCQ_F_INTR) { 1905 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 1906 lif->txqcqs[i]->intr.index, 1907 lif->tx_coalesce_hw); 1908 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 1909 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 1910 } 1911 1912 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 1913 } 1914 1915 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG | IONIC_QCQ_F_INTR; 1916 1917 num_desc = lif->nrxq_descs; 1918 desc_sz = sizeof(struct ionic_rxq_desc); 1919 comp_sz = sizeof(struct ionic_rxq_comp); 1920 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 1921 1922 if (lif->rxq_features & IONIC_Q_F_2X_CQ_DESC) 1923 comp_sz *= 2; 1924 1925 for (i = 0; i < lif->nxqs; i++) { 1926 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 1927 num_desc, desc_sz, comp_sz, sg_desc_sz, 1928 lif->kern_pid, &lif->rxqcqs[i]); 1929 if (err) 1930 goto err_out; 1931 1932 lif->rxqcqs[i]->q.features = lif->rxq_features; 1933 1934 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 1935 lif->rxqcqs[i]->intr.index, 1936 lif->rx_coalesce_hw); 1937 if (test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state)) 1938 lif->rxqcqs[i]->intr.dim_coal_hw = lif->rx_coalesce_hw; 1939 1940 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 1941 ionic_link_qcq_interrupts(lif->rxqcqs[i], 1942 lif->txqcqs[i]); 1943 1944 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 1945 } 1946 1947 return 0; 1948 1949 err_out: 1950 ionic_txrx_free(lif); 1951 1952 return err; 1953 } 1954 1955 static int ionic_txrx_init(struct ionic_lif *lif) 1956 { 1957 unsigned int i; 1958 int err; 1959 1960 for (i = 0; i < lif->nxqs; i++) { 1961 err = ionic_lif_txq_init(lif, lif->txqcqs[i]); 1962 if (err) 1963 goto err_out; 1964 1965 err = ionic_lif_rxq_init(lif, lif->rxqcqs[i]); 1966 if (err) { 1967 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 1968 goto err_out; 1969 } 1970 } 1971 1972 if (lif->netdev->features & NETIF_F_RXHASH) 1973 ionic_lif_rss_init(lif); 1974 1975 ionic_lif_rx_mode(lif); 1976 1977 return 0; 1978 1979 err_out: 1980 while (i--) { 1981 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 1982 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 1983 } 1984 1985 return err; 1986 } 1987 1988 static int ionic_txrx_enable(struct ionic_lif *lif) 1989 { 1990 int derr = 0; 1991 int i, err; 1992 1993 for (i = 0; i < lif->nxqs; i++) { 1994 if (!(lif->rxqcqs[i] && lif->txqcqs[i])) { 1995 dev_err(lif->ionic->dev, "%s: bad qcq %d\n", __func__, i); 1996 err = -ENXIO; 1997 goto err_out; 1998 } 1999 2000 ionic_rx_fill(&lif->rxqcqs[i]->q); 2001 err = ionic_qcq_enable(lif->rxqcqs[i]); 2002 if (err) 2003 goto err_out; 2004 2005 err = ionic_qcq_enable(lif->txqcqs[i]); 2006 if (err) { 2007 derr = ionic_qcq_disable(lif, lif->rxqcqs[i], err); 2008 goto err_out; 2009 } 2010 } 2011 2012 if (lif->hwstamp_rxq) { 2013 ionic_rx_fill(&lif->hwstamp_rxq->q); 2014 err = ionic_qcq_enable(lif->hwstamp_rxq); 2015 if (err) 2016 goto err_out_hwstamp_rx; 2017 } 2018 2019 if (lif->hwstamp_txq) { 2020 err = ionic_qcq_enable(lif->hwstamp_txq); 2021 if (err) 2022 goto err_out_hwstamp_tx; 2023 } 2024 2025 return 0; 2026 2027 err_out_hwstamp_tx: 2028 if (lif->hwstamp_rxq) 2029 derr = ionic_qcq_disable(lif, lif->hwstamp_rxq, derr); 2030 err_out_hwstamp_rx: 2031 i = lif->nxqs; 2032 err_out: 2033 while (i--) { 2034 derr = ionic_qcq_disable(lif, lif->txqcqs[i], derr); 2035 derr = ionic_qcq_disable(lif, lif->rxqcqs[i], derr); 2036 } 2037 2038 return err; 2039 } 2040 2041 static int ionic_start_queues(struct ionic_lif *lif) 2042 { 2043 int err; 2044 2045 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) 2046 return -EIO; 2047 2048 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2049 return -EBUSY; 2050 2051 if (test_and_set_bit(IONIC_LIF_F_UP, lif->state)) 2052 return 0; 2053 2054 err = ionic_txrx_enable(lif); 2055 if (err) { 2056 clear_bit(IONIC_LIF_F_UP, lif->state); 2057 return err; 2058 } 2059 netif_tx_wake_all_queues(lif->netdev); 2060 2061 return 0; 2062 } 2063 2064 static int ionic_open(struct net_device *netdev) 2065 { 2066 struct ionic_lif *lif = netdev_priv(netdev); 2067 int err; 2068 2069 /* If recovering from a broken state, clear the bit and we'll try again */ 2070 if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state)) 2071 netdev_info(netdev, "clearing broken state\n"); 2072 2073 mutex_lock(&lif->queue_lock); 2074 2075 err = ionic_txrx_alloc(lif); 2076 if (err) 2077 goto err_unlock; 2078 2079 err = ionic_txrx_init(lif); 2080 if (err) 2081 goto err_txrx_free; 2082 2083 err = netif_set_real_num_tx_queues(netdev, lif->nxqs); 2084 if (err) 2085 goto err_txrx_deinit; 2086 2087 err = netif_set_real_num_rx_queues(netdev, lif->nxqs); 2088 if (err) 2089 goto err_txrx_deinit; 2090 2091 /* don't start the queues until we have link */ 2092 if (netif_carrier_ok(netdev)) { 2093 err = ionic_start_queues(lif); 2094 if (err) 2095 goto err_txrx_deinit; 2096 } 2097 2098 /* If hardware timestamping is enabled, but the queues were freed by 2099 * ionic_stop, those need to be reallocated and initialized, too. 2100 */ 2101 ionic_lif_hwstamp_recreate_queues(lif); 2102 2103 mutex_unlock(&lif->queue_lock); 2104 2105 return 0; 2106 2107 err_txrx_deinit: 2108 ionic_txrx_deinit(lif); 2109 err_txrx_free: 2110 ionic_txrx_free(lif); 2111 err_unlock: 2112 mutex_unlock(&lif->queue_lock); 2113 return err; 2114 } 2115 2116 static void ionic_stop_queues(struct ionic_lif *lif) 2117 { 2118 if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state)) 2119 return; 2120 2121 netif_tx_disable(lif->netdev); 2122 ionic_txrx_disable(lif); 2123 } 2124 2125 static int ionic_stop(struct net_device *netdev) 2126 { 2127 struct ionic_lif *lif = netdev_priv(netdev); 2128 2129 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2130 return 0; 2131 2132 mutex_lock(&lif->queue_lock); 2133 ionic_stop_queues(lif); 2134 ionic_txrx_deinit(lif); 2135 ionic_txrx_free(lif); 2136 mutex_unlock(&lif->queue_lock); 2137 2138 return 0; 2139 } 2140 2141 static int ionic_eth_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 2142 { 2143 struct ionic_lif *lif = netdev_priv(netdev); 2144 2145 switch (cmd) { 2146 case SIOCSHWTSTAMP: 2147 return ionic_lif_hwstamp_set(lif, ifr); 2148 case SIOCGHWTSTAMP: 2149 return ionic_lif_hwstamp_get(lif, ifr); 2150 default: 2151 return -EOPNOTSUPP; 2152 } 2153 } 2154 2155 static int ionic_get_vf_config(struct net_device *netdev, 2156 int vf, struct ifla_vf_info *ivf) 2157 { 2158 struct ionic_lif *lif = netdev_priv(netdev); 2159 struct ionic *ionic = lif->ionic; 2160 int ret = 0; 2161 2162 if (!netif_device_present(netdev)) 2163 return -EBUSY; 2164 2165 down_read(&ionic->vf_op_lock); 2166 2167 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2168 ret = -EINVAL; 2169 } else { 2170 ivf->vf = vf; 2171 ivf->vlan = le16_to_cpu(ionic->vfs[vf].vlanid); 2172 ivf->qos = 0; 2173 ivf->spoofchk = ionic->vfs[vf].spoofchk; 2174 ivf->linkstate = ionic->vfs[vf].linkstate; 2175 ivf->max_tx_rate = le32_to_cpu(ionic->vfs[vf].maxrate); 2176 ivf->trusted = ionic->vfs[vf].trusted; 2177 ether_addr_copy(ivf->mac, ionic->vfs[vf].macaddr); 2178 } 2179 2180 up_read(&ionic->vf_op_lock); 2181 return ret; 2182 } 2183 2184 static int ionic_get_vf_stats(struct net_device *netdev, int vf, 2185 struct ifla_vf_stats *vf_stats) 2186 { 2187 struct ionic_lif *lif = netdev_priv(netdev); 2188 struct ionic *ionic = lif->ionic; 2189 struct ionic_lif_stats *vs; 2190 int ret = 0; 2191 2192 if (!netif_device_present(netdev)) 2193 return -EBUSY; 2194 2195 down_read(&ionic->vf_op_lock); 2196 2197 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2198 ret = -EINVAL; 2199 } else { 2200 memset(vf_stats, 0, sizeof(*vf_stats)); 2201 vs = &ionic->vfs[vf].stats; 2202 2203 vf_stats->rx_packets = le64_to_cpu(vs->rx_ucast_packets); 2204 vf_stats->tx_packets = le64_to_cpu(vs->tx_ucast_packets); 2205 vf_stats->rx_bytes = le64_to_cpu(vs->rx_ucast_bytes); 2206 vf_stats->tx_bytes = le64_to_cpu(vs->tx_ucast_bytes); 2207 vf_stats->broadcast = le64_to_cpu(vs->rx_bcast_packets); 2208 vf_stats->multicast = le64_to_cpu(vs->rx_mcast_packets); 2209 vf_stats->rx_dropped = le64_to_cpu(vs->rx_ucast_drop_packets) + 2210 le64_to_cpu(vs->rx_mcast_drop_packets) + 2211 le64_to_cpu(vs->rx_bcast_drop_packets); 2212 vf_stats->tx_dropped = le64_to_cpu(vs->tx_ucast_drop_packets) + 2213 le64_to_cpu(vs->tx_mcast_drop_packets) + 2214 le64_to_cpu(vs->tx_bcast_drop_packets); 2215 } 2216 2217 up_read(&ionic->vf_op_lock); 2218 return ret; 2219 } 2220 2221 static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2222 { 2223 struct ionic_lif *lif = netdev_priv(netdev); 2224 struct ionic *ionic = lif->ionic; 2225 int ret; 2226 2227 if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac))) 2228 return -EINVAL; 2229 2230 if (!netif_device_present(netdev)) 2231 return -EBUSY; 2232 2233 down_write(&ionic->vf_op_lock); 2234 2235 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2236 ret = -EINVAL; 2237 } else { 2238 ret = ionic_set_vf_config(ionic, vf, IONIC_VF_ATTR_MAC, mac); 2239 if (!ret) 2240 ether_addr_copy(ionic->vfs[vf].macaddr, mac); 2241 } 2242 2243 up_write(&ionic->vf_op_lock); 2244 return ret; 2245 } 2246 2247 static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 2248 u8 qos, __be16 proto) 2249 { 2250 struct ionic_lif *lif = netdev_priv(netdev); 2251 struct ionic *ionic = lif->ionic; 2252 int ret; 2253 2254 /* until someday when we support qos */ 2255 if (qos) 2256 return -EINVAL; 2257 2258 if (vlan > 4095) 2259 return -EINVAL; 2260 2261 if (proto != htons(ETH_P_8021Q)) 2262 return -EPROTONOSUPPORT; 2263 2264 if (!netif_device_present(netdev)) 2265 return -EBUSY; 2266 2267 down_write(&ionic->vf_op_lock); 2268 2269 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2270 ret = -EINVAL; 2271 } else { 2272 ret = ionic_set_vf_config(ionic, vf, 2273 IONIC_VF_ATTR_VLAN, (u8 *)&vlan); 2274 if (!ret) 2275 ionic->vfs[vf].vlanid = cpu_to_le16(vlan); 2276 } 2277 2278 up_write(&ionic->vf_op_lock); 2279 return ret; 2280 } 2281 2282 static int ionic_set_vf_rate(struct net_device *netdev, int vf, 2283 int tx_min, int tx_max) 2284 { 2285 struct ionic_lif *lif = netdev_priv(netdev); 2286 struct ionic *ionic = lif->ionic; 2287 int ret; 2288 2289 /* setting the min just seems silly */ 2290 if (tx_min) 2291 return -EINVAL; 2292 2293 if (!netif_device_present(netdev)) 2294 return -EBUSY; 2295 2296 down_write(&ionic->vf_op_lock); 2297 2298 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2299 ret = -EINVAL; 2300 } else { 2301 ret = ionic_set_vf_config(ionic, vf, 2302 IONIC_VF_ATTR_RATE, (u8 *)&tx_max); 2303 if (!ret) 2304 lif->ionic->vfs[vf].maxrate = cpu_to_le32(tx_max); 2305 } 2306 2307 up_write(&ionic->vf_op_lock); 2308 return ret; 2309 } 2310 2311 static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set) 2312 { 2313 struct ionic_lif *lif = netdev_priv(netdev); 2314 struct ionic *ionic = lif->ionic; 2315 u8 data = set; /* convert to u8 for config */ 2316 int ret; 2317 2318 if (!netif_device_present(netdev)) 2319 return -EBUSY; 2320 2321 down_write(&ionic->vf_op_lock); 2322 2323 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2324 ret = -EINVAL; 2325 } else { 2326 ret = ionic_set_vf_config(ionic, vf, 2327 IONIC_VF_ATTR_SPOOFCHK, &data); 2328 if (!ret) 2329 ionic->vfs[vf].spoofchk = data; 2330 } 2331 2332 up_write(&ionic->vf_op_lock); 2333 return ret; 2334 } 2335 2336 static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set) 2337 { 2338 struct ionic_lif *lif = netdev_priv(netdev); 2339 struct ionic *ionic = lif->ionic; 2340 u8 data = set; /* convert to u8 for config */ 2341 int ret; 2342 2343 if (!netif_device_present(netdev)) 2344 return -EBUSY; 2345 2346 down_write(&ionic->vf_op_lock); 2347 2348 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2349 ret = -EINVAL; 2350 } else { 2351 ret = ionic_set_vf_config(ionic, vf, 2352 IONIC_VF_ATTR_TRUST, &data); 2353 if (!ret) 2354 ionic->vfs[vf].trusted = data; 2355 } 2356 2357 up_write(&ionic->vf_op_lock); 2358 return ret; 2359 } 2360 2361 static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set) 2362 { 2363 struct ionic_lif *lif = netdev_priv(netdev); 2364 struct ionic *ionic = lif->ionic; 2365 u8 data; 2366 int ret; 2367 2368 switch (set) { 2369 case IFLA_VF_LINK_STATE_ENABLE: 2370 data = IONIC_VF_LINK_STATUS_UP; 2371 break; 2372 case IFLA_VF_LINK_STATE_DISABLE: 2373 data = IONIC_VF_LINK_STATUS_DOWN; 2374 break; 2375 case IFLA_VF_LINK_STATE_AUTO: 2376 data = IONIC_VF_LINK_STATUS_AUTO; 2377 break; 2378 default: 2379 return -EINVAL; 2380 } 2381 2382 if (!netif_device_present(netdev)) 2383 return -EBUSY; 2384 2385 down_write(&ionic->vf_op_lock); 2386 2387 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2388 ret = -EINVAL; 2389 } else { 2390 ret = ionic_set_vf_config(ionic, vf, 2391 IONIC_VF_ATTR_LINKSTATE, &data); 2392 if (!ret) 2393 ionic->vfs[vf].linkstate = set; 2394 } 2395 2396 up_write(&ionic->vf_op_lock); 2397 return ret; 2398 } 2399 2400 static const struct net_device_ops ionic_netdev_ops = { 2401 .ndo_open = ionic_open, 2402 .ndo_stop = ionic_stop, 2403 .ndo_eth_ioctl = ionic_eth_ioctl, 2404 .ndo_start_xmit = ionic_start_xmit, 2405 .ndo_get_stats64 = ionic_get_stats64, 2406 .ndo_set_rx_mode = ionic_ndo_set_rx_mode, 2407 .ndo_set_features = ionic_set_features, 2408 .ndo_set_mac_address = ionic_set_mac_address, 2409 .ndo_validate_addr = eth_validate_addr, 2410 .ndo_tx_timeout = ionic_tx_timeout, 2411 .ndo_change_mtu = ionic_change_mtu, 2412 .ndo_vlan_rx_add_vid = ionic_vlan_rx_add_vid, 2413 .ndo_vlan_rx_kill_vid = ionic_vlan_rx_kill_vid, 2414 .ndo_set_vf_vlan = ionic_set_vf_vlan, 2415 .ndo_set_vf_trust = ionic_set_vf_trust, 2416 .ndo_set_vf_mac = ionic_set_vf_mac, 2417 .ndo_set_vf_rate = ionic_set_vf_rate, 2418 .ndo_set_vf_spoofchk = ionic_set_vf_spoofchk, 2419 .ndo_get_vf_config = ionic_get_vf_config, 2420 .ndo_set_vf_link_state = ionic_set_vf_link_state, 2421 .ndo_get_vf_stats = ionic_get_vf_stats, 2422 }; 2423 2424 static void ionic_swap_queues(struct ionic_qcq *a, struct ionic_qcq *b) 2425 { 2426 /* only swapping the queues, not the napi, flags, or other stuff */ 2427 swap(a->q.features, b->q.features); 2428 swap(a->q.num_descs, b->q.num_descs); 2429 swap(a->q.desc_size, b->q.desc_size); 2430 swap(a->q.base, b->q.base); 2431 swap(a->q.base_pa, b->q.base_pa); 2432 swap(a->q.info, b->q.info); 2433 swap(a->q_base, b->q_base); 2434 swap(a->q_base_pa, b->q_base_pa); 2435 swap(a->q_size, b->q_size); 2436 2437 swap(a->q.sg_desc_size, b->q.sg_desc_size); 2438 swap(a->q.sg_base, b->q.sg_base); 2439 swap(a->q.sg_base_pa, b->q.sg_base_pa); 2440 swap(a->sg_base, b->sg_base); 2441 swap(a->sg_base_pa, b->sg_base_pa); 2442 swap(a->sg_size, b->sg_size); 2443 2444 swap(a->cq.num_descs, b->cq.num_descs); 2445 swap(a->cq.desc_size, b->cq.desc_size); 2446 swap(a->cq.base, b->cq.base); 2447 swap(a->cq.base_pa, b->cq.base_pa); 2448 swap(a->cq.info, b->cq.info); 2449 swap(a->cq_base, b->cq_base); 2450 swap(a->cq_base_pa, b->cq_base_pa); 2451 swap(a->cq_size, b->cq_size); 2452 2453 ionic_debugfs_del_qcq(a); 2454 ionic_debugfs_add_qcq(a->q.lif, a); 2455 } 2456 2457 int ionic_reconfigure_queues(struct ionic_lif *lif, 2458 struct ionic_queue_params *qparam) 2459 { 2460 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz; 2461 struct ionic_qcq **tx_qcqs = NULL; 2462 struct ionic_qcq **rx_qcqs = NULL; 2463 unsigned int flags, i; 2464 int err = 0; 2465 2466 /* allocate temporary qcq arrays to hold new queue structs */ 2467 if (qparam->nxqs != lif->nxqs || qparam->ntxq_descs != lif->ntxq_descs) { 2468 tx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->ntxqs_per_lif, 2469 sizeof(struct ionic_qcq *), GFP_KERNEL); 2470 if (!tx_qcqs) { 2471 err = -ENOMEM; 2472 goto err_out; 2473 } 2474 } 2475 if (qparam->nxqs != lif->nxqs || 2476 qparam->nrxq_descs != lif->nrxq_descs || 2477 qparam->rxq_features != lif->rxq_features) { 2478 rx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->nrxqs_per_lif, 2479 sizeof(struct ionic_qcq *), GFP_KERNEL); 2480 if (!rx_qcqs) { 2481 err = -ENOMEM; 2482 goto err_out; 2483 } 2484 } 2485 2486 /* allocate new desc_info and rings, but leave the interrupt setup 2487 * until later so as to not mess with the still-running queues 2488 */ 2489 if (tx_qcqs) { 2490 num_desc = qparam->ntxq_descs; 2491 desc_sz = sizeof(struct ionic_txq_desc); 2492 comp_sz = sizeof(struct ionic_txq_comp); 2493 2494 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 2495 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 2496 sizeof(struct ionic_txq_sg_desc_v1)) 2497 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 2498 else 2499 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 2500 2501 for (i = 0; i < qparam->nxqs; i++) { 2502 flags = lif->txqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2503 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 2504 num_desc, desc_sz, comp_sz, sg_desc_sz, 2505 lif->kern_pid, &tx_qcqs[i]); 2506 if (err) 2507 goto err_out; 2508 } 2509 } 2510 2511 if (rx_qcqs) { 2512 num_desc = qparam->nrxq_descs; 2513 desc_sz = sizeof(struct ionic_rxq_desc); 2514 comp_sz = sizeof(struct ionic_rxq_comp); 2515 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 2516 2517 if (qparam->rxq_features & IONIC_Q_F_2X_CQ_DESC) 2518 comp_sz *= 2; 2519 2520 for (i = 0; i < qparam->nxqs; i++) { 2521 flags = lif->rxqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2522 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 2523 num_desc, desc_sz, comp_sz, sg_desc_sz, 2524 lif->kern_pid, &rx_qcqs[i]); 2525 if (err) 2526 goto err_out; 2527 2528 rx_qcqs[i]->q.features = qparam->rxq_features; 2529 } 2530 } 2531 2532 /* stop and clean the queues */ 2533 ionic_stop_queues_reconfig(lif); 2534 2535 if (qparam->nxqs != lif->nxqs) { 2536 err = netif_set_real_num_tx_queues(lif->netdev, qparam->nxqs); 2537 if (err) 2538 goto err_out_reinit_unlock; 2539 err = netif_set_real_num_rx_queues(lif->netdev, qparam->nxqs); 2540 if (err) { 2541 netif_set_real_num_tx_queues(lif->netdev, lif->nxqs); 2542 goto err_out_reinit_unlock; 2543 } 2544 } 2545 2546 /* swap new desc_info and rings, keeping existing interrupt config */ 2547 if (tx_qcqs) { 2548 lif->ntxq_descs = qparam->ntxq_descs; 2549 for (i = 0; i < qparam->nxqs; i++) 2550 ionic_swap_queues(lif->txqcqs[i], tx_qcqs[i]); 2551 } 2552 2553 if (rx_qcqs) { 2554 lif->nrxq_descs = qparam->nrxq_descs; 2555 for (i = 0; i < qparam->nxqs; i++) 2556 ionic_swap_queues(lif->rxqcqs[i], rx_qcqs[i]); 2557 } 2558 2559 /* if we need to change the interrupt layout, this is the time */ 2560 if (qparam->intr_split != test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) || 2561 qparam->nxqs != lif->nxqs) { 2562 if (qparam->intr_split) { 2563 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 2564 } else { 2565 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 2566 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 2567 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 2568 } 2569 2570 /* clear existing interrupt assignments */ 2571 for (i = 0; i < lif->ionic->ntxqs_per_lif; i++) { 2572 ionic_qcq_intr_free(lif, lif->txqcqs[i]); 2573 ionic_qcq_intr_free(lif, lif->rxqcqs[i]); 2574 } 2575 2576 /* re-assign the interrupts */ 2577 for (i = 0; i < qparam->nxqs; i++) { 2578 lif->rxqcqs[i]->flags |= IONIC_QCQ_F_INTR; 2579 err = ionic_alloc_qcq_interrupt(lif, lif->rxqcqs[i]); 2580 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2581 lif->rxqcqs[i]->intr.index, 2582 lif->rx_coalesce_hw); 2583 2584 if (qparam->intr_split) { 2585 lif->txqcqs[i]->flags |= IONIC_QCQ_F_INTR; 2586 err = ionic_alloc_qcq_interrupt(lif, lif->txqcqs[i]); 2587 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2588 lif->txqcqs[i]->intr.index, 2589 lif->tx_coalesce_hw); 2590 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 2591 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 2592 } else { 2593 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2594 ionic_link_qcq_interrupts(lif->rxqcqs[i], lif->txqcqs[i]); 2595 } 2596 } 2597 } 2598 2599 /* now we can rework the debugfs mappings */ 2600 if (tx_qcqs) { 2601 for (i = 0; i < qparam->nxqs; i++) { 2602 ionic_debugfs_del_qcq(lif->txqcqs[i]); 2603 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 2604 } 2605 } 2606 2607 if (rx_qcqs) { 2608 for (i = 0; i < qparam->nxqs; i++) { 2609 ionic_debugfs_del_qcq(lif->rxqcqs[i]); 2610 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 2611 } 2612 } 2613 2614 swap(lif->nxqs, qparam->nxqs); 2615 swap(lif->rxq_features, qparam->rxq_features); 2616 2617 err_out_reinit_unlock: 2618 /* re-init the queues, but don't lose an error code */ 2619 if (err) 2620 ionic_start_queues_reconfig(lif); 2621 else 2622 err = ionic_start_queues_reconfig(lif); 2623 2624 err_out: 2625 /* free old allocs without cleaning intr */ 2626 for (i = 0; i < qparam->nxqs; i++) { 2627 if (tx_qcqs && tx_qcqs[i]) { 2628 tx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2629 ionic_qcq_free(lif, tx_qcqs[i]); 2630 devm_kfree(lif->ionic->dev, tx_qcqs[i]); 2631 tx_qcqs[i] = NULL; 2632 } 2633 if (rx_qcqs && rx_qcqs[i]) { 2634 rx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2635 ionic_qcq_free(lif, rx_qcqs[i]); 2636 devm_kfree(lif->ionic->dev, rx_qcqs[i]); 2637 rx_qcqs[i] = NULL; 2638 } 2639 } 2640 2641 /* free q array */ 2642 if (rx_qcqs) { 2643 devm_kfree(lif->ionic->dev, rx_qcqs); 2644 rx_qcqs = NULL; 2645 } 2646 if (tx_qcqs) { 2647 devm_kfree(lif->ionic->dev, tx_qcqs); 2648 tx_qcqs = NULL; 2649 } 2650 2651 /* clean the unused dma and info allocations when new set is smaller 2652 * than the full array, but leave the qcq shells in place 2653 */ 2654 for (i = lif->nxqs; i < lif->ionic->ntxqs_per_lif; i++) { 2655 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2656 ionic_qcq_free(lif, lif->txqcqs[i]); 2657 2658 lif->rxqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2659 ionic_qcq_free(lif, lif->rxqcqs[i]); 2660 } 2661 2662 if (err) 2663 netdev_info(lif->netdev, "%s: failed %d\n", __func__, err); 2664 2665 return err; 2666 } 2667 2668 int ionic_lif_alloc(struct ionic *ionic) 2669 { 2670 struct device *dev = ionic->dev; 2671 union ionic_lif_identity *lid; 2672 struct net_device *netdev; 2673 struct ionic_lif *lif; 2674 int tbl_sz; 2675 int err; 2676 2677 lid = kzalloc(sizeof(*lid), GFP_KERNEL); 2678 if (!lid) 2679 return -ENOMEM; 2680 2681 netdev = alloc_etherdev_mqs(sizeof(*lif), 2682 ionic->ntxqs_per_lif, ionic->ntxqs_per_lif); 2683 if (!netdev) { 2684 dev_err(dev, "Cannot allocate netdev, aborting\n"); 2685 err = -ENOMEM; 2686 goto err_out_free_lid; 2687 } 2688 2689 SET_NETDEV_DEV(netdev, dev); 2690 2691 lif = netdev_priv(netdev); 2692 lif->netdev = netdev; 2693 ionic->lif = lif; 2694 netdev->netdev_ops = &ionic_netdev_ops; 2695 ionic_ethtool_set_ops(netdev); 2696 2697 netdev->watchdog_timeo = 2 * HZ; 2698 netif_carrier_off(netdev); 2699 2700 lif->identity = lid; 2701 lif->lif_type = IONIC_LIF_TYPE_CLASSIC; 2702 err = ionic_lif_identify(ionic, lif->lif_type, lif->identity); 2703 if (err) { 2704 dev_err(ionic->dev, "Cannot identify type %d: %d\n", 2705 lif->lif_type, err); 2706 goto err_out_free_netdev; 2707 } 2708 lif->netdev->min_mtu = max_t(unsigned int, ETH_MIN_MTU, 2709 le32_to_cpu(lif->identity->eth.min_frame_size)); 2710 lif->netdev->max_mtu = 2711 le32_to_cpu(lif->identity->eth.max_frame_size) - ETH_HLEN - VLAN_HLEN; 2712 2713 lif->neqs = ionic->neqs_per_lif; 2714 lif->nxqs = ionic->ntxqs_per_lif; 2715 2716 lif->ionic = ionic; 2717 lif->index = 0; 2718 2719 if (is_kdump_kernel()) { 2720 lif->ntxq_descs = IONIC_MIN_TXRX_DESC; 2721 lif->nrxq_descs = IONIC_MIN_TXRX_DESC; 2722 } else { 2723 lif->ntxq_descs = IONIC_DEF_TXRX_DESC; 2724 lif->nrxq_descs = IONIC_DEF_TXRX_DESC; 2725 } 2726 2727 /* Convert the default coalesce value to actual hw resolution */ 2728 lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT; 2729 lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic, 2730 lif->rx_coalesce_usecs); 2731 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 2732 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 2733 set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 2734 set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 2735 2736 snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index); 2737 2738 mutex_init(&lif->queue_lock); 2739 mutex_init(&lif->config_lock); 2740 2741 spin_lock_init(&lif->adminq_lock); 2742 2743 spin_lock_init(&lif->deferred.lock); 2744 INIT_LIST_HEAD(&lif->deferred.list); 2745 INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work); 2746 2747 /* allocate lif info */ 2748 lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE); 2749 lif->info = dma_alloc_coherent(dev, lif->info_sz, 2750 &lif->info_pa, GFP_KERNEL); 2751 if (!lif->info) { 2752 dev_err(dev, "Failed to allocate lif info, aborting\n"); 2753 err = -ENOMEM; 2754 goto err_out_free_mutex; 2755 } 2756 2757 ionic_debugfs_add_lif(lif); 2758 2759 /* allocate control queues and txrx queue arrays */ 2760 ionic_lif_queue_identify(lif); 2761 err = ionic_qcqs_alloc(lif); 2762 if (err) 2763 goto err_out_free_lif_info; 2764 2765 /* allocate rss indirection table */ 2766 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 2767 lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz; 2768 lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz, 2769 &lif->rss_ind_tbl_pa, 2770 GFP_KERNEL); 2771 2772 if (!lif->rss_ind_tbl) { 2773 err = -ENOMEM; 2774 dev_err(dev, "Failed to allocate rss indirection table, aborting\n"); 2775 goto err_out_free_qcqs; 2776 } 2777 netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE); 2778 2779 ionic_lif_alloc_phc(lif); 2780 2781 return 0; 2782 2783 err_out_free_qcqs: 2784 ionic_qcqs_free(lif); 2785 err_out_free_lif_info: 2786 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 2787 lif->info = NULL; 2788 lif->info_pa = 0; 2789 err_out_free_mutex: 2790 mutex_destroy(&lif->config_lock); 2791 mutex_destroy(&lif->queue_lock); 2792 err_out_free_netdev: 2793 free_netdev(lif->netdev); 2794 lif = NULL; 2795 err_out_free_lid: 2796 kfree(lid); 2797 2798 return err; 2799 } 2800 2801 static void ionic_lif_reset(struct ionic_lif *lif) 2802 { 2803 struct ionic_dev *idev = &lif->ionic->idev; 2804 2805 mutex_lock(&lif->ionic->dev_cmd_lock); 2806 ionic_dev_cmd_lif_reset(idev, lif->index); 2807 ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2808 mutex_unlock(&lif->ionic->dev_cmd_lock); 2809 } 2810 2811 static void ionic_lif_handle_fw_down(struct ionic_lif *lif) 2812 { 2813 struct ionic *ionic = lif->ionic; 2814 2815 if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2816 return; 2817 2818 dev_info(ionic->dev, "FW Down: Stopping LIFs\n"); 2819 2820 netif_device_detach(lif->netdev); 2821 2822 mutex_lock(&lif->queue_lock); 2823 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 2824 dev_info(ionic->dev, "Surprise FW stop, stopping queues\n"); 2825 ionic_stop_queues(lif); 2826 } 2827 2828 if (netif_running(lif->netdev)) { 2829 ionic_txrx_deinit(lif); 2830 ionic_txrx_free(lif); 2831 } 2832 ionic_lif_deinit(lif); 2833 ionic_reset(ionic); 2834 ionic_qcqs_free(lif); 2835 2836 mutex_unlock(&lif->queue_lock); 2837 2838 dev_info(ionic->dev, "FW Down: LIFs stopped\n"); 2839 } 2840 2841 static void ionic_lif_handle_fw_up(struct ionic_lif *lif) 2842 { 2843 struct ionic *ionic = lif->ionic; 2844 int err; 2845 2846 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2847 return; 2848 2849 dev_info(ionic->dev, "FW Up: restarting LIFs\n"); 2850 2851 ionic_init_devinfo(ionic); 2852 err = ionic_identify(ionic); 2853 if (err) 2854 goto err_out; 2855 err = ionic_port_identify(ionic); 2856 if (err) 2857 goto err_out; 2858 err = ionic_port_init(ionic); 2859 if (err) 2860 goto err_out; 2861 2862 mutex_lock(&lif->queue_lock); 2863 2864 err = ionic_qcqs_alloc(lif); 2865 if (err) 2866 goto err_unlock; 2867 2868 err = ionic_lif_init(lif); 2869 if (err) 2870 goto err_qcqs_free; 2871 2872 if (lif->registered) 2873 ionic_lif_set_netdev_info(lif); 2874 2875 ionic_rx_filter_replay(lif); 2876 2877 if (netif_running(lif->netdev)) { 2878 err = ionic_txrx_alloc(lif); 2879 if (err) 2880 goto err_lifs_deinit; 2881 2882 err = ionic_txrx_init(lif); 2883 if (err) 2884 goto err_txrx_free; 2885 } 2886 2887 mutex_unlock(&lif->queue_lock); 2888 2889 clear_bit(IONIC_LIF_F_FW_RESET, lif->state); 2890 ionic_link_status_check_request(lif, CAN_SLEEP); 2891 netif_device_attach(lif->netdev); 2892 dev_info(ionic->dev, "FW Up: LIFs restarted\n"); 2893 2894 /* restore the hardware timestamping queues */ 2895 ionic_lif_hwstamp_replay(lif); 2896 2897 return; 2898 2899 err_txrx_free: 2900 ionic_txrx_free(lif); 2901 err_lifs_deinit: 2902 ionic_lif_deinit(lif); 2903 err_qcqs_free: 2904 ionic_qcqs_free(lif); 2905 err_unlock: 2906 mutex_unlock(&lif->queue_lock); 2907 err_out: 2908 dev_err(ionic->dev, "FW Up: LIFs restart failed - err %d\n", err); 2909 } 2910 2911 void ionic_lif_free(struct ionic_lif *lif) 2912 { 2913 struct device *dev = lif->ionic->dev; 2914 2915 ionic_lif_free_phc(lif); 2916 2917 /* free rss indirection table */ 2918 dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl, 2919 lif->rss_ind_tbl_pa); 2920 lif->rss_ind_tbl = NULL; 2921 lif->rss_ind_tbl_pa = 0; 2922 2923 /* free queues */ 2924 ionic_qcqs_free(lif); 2925 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2926 ionic_lif_reset(lif); 2927 2928 /* free lif info */ 2929 kfree(lif->identity); 2930 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 2931 lif->info = NULL; 2932 lif->info_pa = 0; 2933 2934 /* unmap doorbell page */ 2935 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 2936 lif->kern_dbpage = NULL; 2937 kfree(lif->dbid_inuse); 2938 lif->dbid_inuse = NULL; 2939 2940 mutex_destroy(&lif->config_lock); 2941 mutex_destroy(&lif->queue_lock); 2942 2943 /* free netdev & lif */ 2944 ionic_debugfs_del_lif(lif); 2945 free_netdev(lif->netdev); 2946 } 2947 2948 void ionic_lif_deinit(struct ionic_lif *lif) 2949 { 2950 if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state)) 2951 return; 2952 2953 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 2954 cancel_work_sync(&lif->deferred.work); 2955 cancel_work_sync(&lif->tx_timeout_work); 2956 ionic_rx_filters_deinit(lif); 2957 if (lif->netdev->features & NETIF_F_RXHASH) 2958 ionic_lif_rss_deinit(lif); 2959 } 2960 2961 napi_disable(&lif->adminqcq->napi); 2962 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 2963 ionic_lif_qcq_deinit(lif, lif->adminqcq); 2964 2965 ionic_lif_reset(lif); 2966 } 2967 2968 static int ionic_lif_adminq_init(struct ionic_lif *lif) 2969 { 2970 struct device *dev = lif->ionic->dev; 2971 struct ionic_q_init_comp comp; 2972 struct ionic_dev *idev; 2973 struct ionic_qcq *qcq; 2974 struct ionic_queue *q; 2975 int err; 2976 2977 idev = &lif->ionic->idev; 2978 qcq = lif->adminqcq; 2979 q = &qcq->q; 2980 2981 mutex_lock(&lif->ionic->dev_cmd_lock); 2982 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index); 2983 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2984 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 2985 mutex_unlock(&lif->ionic->dev_cmd_lock); 2986 if (err) { 2987 netdev_err(lif->netdev, "adminq init failed %d\n", err); 2988 return err; 2989 } 2990 2991 q->hw_type = comp.hw_type; 2992 q->hw_index = le32_to_cpu(comp.hw_index); 2993 q->dbval = IONIC_DBELL_QID(q->hw_index); 2994 2995 dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type); 2996 dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index); 2997 2998 netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi, 2999 NAPI_POLL_WEIGHT); 3000 3001 napi_enable(&qcq->napi); 3002 3003 if (qcq->flags & IONIC_QCQ_F_INTR) 3004 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 3005 IONIC_INTR_MASK_CLEAR); 3006 3007 qcq->flags |= IONIC_QCQ_F_INITED; 3008 3009 return 0; 3010 } 3011 3012 static int ionic_lif_notifyq_init(struct ionic_lif *lif) 3013 { 3014 struct ionic_qcq *qcq = lif->notifyqcq; 3015 struct device *dev = lif->ionic->dev; 3016 struct ionic_queue *q = &qcq->q; 3017 int err; 3018 3019 struct ionic_admin_ctx ctx = { 3020 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3021 .cmd.q_init = { 3022 .opcode = IONIC_CMD_Q_INIT, 3023 .lif_index = cpu_to_le16(lif->index), 3024 .type = q->type, 3025 .ver = lif->qtype_info[q->type].version, 3026 .index = cpu_to_le32(q->index), 3027 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 3028 IONIC_QINIT_F_ENA), 3029 .intr_index = cpu_to_le16(lif->adminqcq->intr.index), 3030 .pid = cpu_to_le16(q->pid), 3031 .ring_size = ilog2(q->num_descs), 3032 .ring_base = cpu_to_le64(q->base_pa), 3033 } 3034 }; 3035 3036 dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid); 3037 dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index); 3038 dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 3039 dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 3040 3041 err = ionic_adminq_post_wait(lif, &ctx); 3042 if (err) 3043 return err; 3044 3045 lif->last_eid = 0; 3046 q->hw_type = ctx.comp.q_init.hw_type; 3047 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 3048 q->dbval = IONIC_DBELL_QID(q->hw_index); 3049 3050 dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type); 3051 dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index); 3052 3053 /* preset the callback info */ 3054 q->info[0].cb_arg = lif; 3055 3056 qcq->flags |= IONIC_QCQ_F_INITED; 3057 3058 return 0; 3059 } 3060 3061 static int ionic_station_set(struct ionic_lif *lif) 3062 { 3063 struct net_device *netdev = lif->netdev; 3064 struct ionic_admin_ctx ctx = { 3065 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3066 .cmd.lif_getattr = { 3067 .opcode = IONIC_CMD_LIF_GETATTR, 3068 .index = cpu_to_le16(lif->index), 3069 .attr = IONIC_LIF_ATTR_MAC, 3070 }, 3071 }; 3072 struct sockaddr addr; 3073 int err; 3074 3075 err = ionic_adminq_post_wait(lif, &ctx); 3076 if (err) 3077 return err; 3078 netdev_dbg(lif->netdev, "found initial MAC addr %pM\n", 3079 ctx.comp.lif_getattr.mac); 3080 if (is_zero_ether_addr(ctx.comp.lif_getattr.mac)) 3081 return 0; 3082 3083 if (!is_zero_ether_addr(netdev->dev_addr)) { 3084 /* If the netdev mac is non-zero and doesn't match the default 3085 * device address, it was set by something earlier and we're 3086 * likely here again after a fw-upgrade reset. We need to be 3087 * sure the netdev mac is in our filter list. 3088 */ 3089 if (!ether_addr_equal(ctx.comp.lif_getattr.mac, 3090 netdev->dev_addr)) 3091 ionic_lif_addr_add(lif, netdev->dev_addr); 3092 } else { 3093 /* Update the netdev mac with the device's mac */ 3094 memcpy(addr.sa_data, ctx.comp.lif_getattr.mac, netdev->addr_len); 3095 addr.sa_family = AF_INET; 3096 err = eth_prepare_mac_addr_change(netdev, &addr); 3097 if (err) { 3098 netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n", 3099 addr.sa_data, err); 3100 return 0; 3101 } 3102 3103 eth_commit_mac_addr_change(netdev, &addr); 3104 } 3105 3106 netdev_dbg(lif->netdev, "adding station MAC addr %pM\n", 3107 netdev->dev_addr); 3108 ionic_lif_addr_add(lif, netdev->dev_addr); 3109 3110 return 0; 3111 } 3112 3113 int ionic_lif_init(struct ionic_lif *lif) 3114 { 3115 struct ionic_dev *idev = &lif->ionic->idev; 3116 struct device *dev = lif->ionic->dev; 3117 struct ionic_lif_init_comp comp; 3118 int dbpage_num; 3119 int err; 3120 3121 mutex_lock(&lif->ionic->dev_cmd_lock); 3122 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa); 3123 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 3124 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 3125 mutex_unlock(&lif->ionic->dev_cmd_lock); 3126 if (err) 3127 return err; 3128 3129 lif->hw_index = le16_to_cpu(comp.hw_index); 3130 3131 /* now that we have the hw_index we can figure out our doorbell page */ 3132 lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif); 3133 if (!lif->dbid_count) { 3134 dev_err(dev, "No doorbell pages, aborting\n"); 3135 return -EINVAL; 3136 } 3137 3138 lif->dbid_inuse = bitmap_alloc(lif->dbid_count, GFP_KERNEL); 3139 if (!lif->dbid_inuse) { 3140 dev_err(dev, "Failed alloc doorbell id bitmap, aborting\n"); 3141 return -ENOMEM; 3142 } 3143 3144 /* first doorbell id reserved for kernel (dbid aka pid == zero) */ 3145 set_bit(0, lif->dbid_inuse); 3146 lif->kern_pid = 0; 3147 3148 dbpage_num = ionic_db_page_num(lif, lif->kern_pid); 3149 lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num); 3150 if (!lif->kern_dbpage) { 3151 dev_err(dev, "Cannot map dbpage, aborting\n"); 3152 err = -ENOMEM; 3153 goto err_out_free_dbid; 3154 } 3155 3156 err = ionic_lif_adminq_init(lif); 3157 if (err) 3158 goto err_out_adminq_deinit; 3159 3160 if (lif->ionic->nnqs_per_lif) { 3161 err = ionic_lif_notifyq_init(lif); 3162 if (err) 3163 goto err_out_notifyq_deinit; 3164 } 3165 3166 err = ionic_init_nic_features(lif); 3167 if (err) 3168 goto err_out_notifyq_deinit; 3169 3170 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 3171 err = ionic_rx_filters_init(lif); 3172 if (err) 3173 goto err_out_notifyq_deinit; 3174 } 3175 3176 err = ionic_station_set(lif); 3177 if (err) 3178 goto err_out_notifyq_deinit; 3179 3180 lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT; 3181 3182 set_bit(IONIC_LIF_F_INITED, lif->state); 3183 3184 INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work); 3185 3186 return 0; 3187 3188 err_out_notifyq_deinit: 3189 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 3190 err_out_adminq_deinit: 3191 ionic_lif_qcq_deinit(lif, lif->adminqcq); 3192 ionic_lif_reset(lif); 3193 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 3194 lif->kern_dbpage = NULL; 3195 err_out_free_dbid: 3196 kfree(lif->dbid_inuse); 3197 lif->dbid_inuse = NULL; 3198 3199 return err; 3200 } 3201 3202 static void ionic_lif_notify_work(struct work_struct *ws) 3203 { 3204 } 3205 3206 static void ionic_lif_set_netdev_info(struct ionic_lif *lif) 3207 { 3208 struct ionic_admin_ctx ctx = { 3209 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3210 .cmd.lif_setattr = { 3211 .opcode = IONIC_CMD_LIF_SETATTR, 3212 .index = cpu_to_le16(lif->index), 3213 .attr = IONIC_LIF_ATTR_NAME, 3214 }, 3215 }; 3216 3217 strlcpy(ctx.cmd.lif_setattr.name, lif->netdev->name, 3218 sizeof(ctx.cmd.lif_setattr.name)); 3219 3220 ionic_adminq_post_wait(lif, &ctx); 3221 } 3222 3223 static struct ionic_lif *ionic_netdev_lif(struct net_device *netdev) 3224 { 3225 if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit) 3226 return NULL; 3227 3228 return netdev_priv(netdev); 3229 } 3230 3231 static int ionic_lif_notify(struct notifier_block *nb, 3232 unsigned long event, void *info) 3233 { 3234 struct net_device *ndev = netdev_notifier_info_to_dev(info); 3235 struct ionic *ionic = container_of(nb, struct ionic, nb); 3236 struct ionic_lif *lif = ionic_netdev_lif(ndev); 3237 3238 if (!lif || lif->ionic != ionic) 3239 return NOTIFY_DONE; 3240 3241 switch (event) { 3242 case NETDEV_CHANGENAME: 3243 ionic_lif_set_netdev_info(lif); 3244 break; 3245 } 3246 3247 return NOTIFY_DONE; 3248 } 3249 3250 int ionic_lif_register(struct ionic_lif *lif) 3251 { 3252 int err; 3253 3254 ionic_lif_register_phc(lif); 3255 3256 INIT_WORK(&lif->ionic->nb_work, ionic_lif_notify_work); 3257 3258 lif->ionic->nb.notifier_call = ionic_lif_notify; 3259 3260 err = register_netdevice_notifier(&lif->ionic->nb); 3261 if (err) 3262 lif->ionic->nb.notifier_call = NULL; 3263 3264 /* only register LIF0 for now */ 3265 err = register_netdev(lif->netdev); 3266 if (err) { 3267 dev_err(lif->ionic->dev, "Cannot register net device, aborting\n"); 3268 ionic_lif_unregister_phc(lif); 3269 return err; 3270 } 3271 3272 ionic_link_status_check_request(lif, CAN_SLEEP); 3273 lif->registered = true; 3274 ionic_lif_set_netdev_info(lif); 3275 3276 return 0; 3277 } 3278 3279 void ionic_lif_unregister(struct ionic_lif *lif) 3280 { 3281 if (lif->ionic->nb.notifier_call) { 3282 unregister_netdevice_notifier(&lif->ionic->nb); 3283 cancel_work_sync(&lif->ionic->nb_work); 3284 lif->ionic->nb.notifier_call = NULL; 3285 } 3286 3287 if (lif->netdev->reg_state == NETREG_REGISTERED) 3288 unregister_netdev(lif->netdev); 3289 3290 ionic_lif_unregister_phc(lif); 3291 3292 lif->registered = false; 3293 } 3294 3295 static void ionic_lif_queue_identify(struct ionic_lif *lif) 3296 { 3297 union ionic_q_identity __iomem *q_ident; 3298 struct ionic *ionic = lif->ionic; 3299 struct ionic_dev *idev; 3300 int qtype; 3301 int err; 3302 3303 idev = &lif->ionic->idev; 3304 q_ident = (union ionic_q_identity __iomem *)&idev->dev_cmd_regs->data; 3305 3306 for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) { 3307 struct ionic_qtype_info *qti = &lif->qtype_info[qtype]; 3308 3309 /* filter out the ones we know about */ 3310 switch (qtype) { 3311 case IONIC_QTYPE_ADMINQ: 3312 case IONIC_QTYPE_NOTIFYQ: 3313 case IONIC_QTYPE_RXQ: 3314 case IONIC_QTYPE_TXQ: 3315 break; 3316 default: 3317 continue; 3318 } 3319 3320 memset(qti, 0, sizeof(*qti)); 3321 3322 mutex_lock(&ionic->dev_cmd_lock); 3323 ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype, 3324 ionic_qtype_versions[qtype]); 3325 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3326 if (!err) { 3327 qti->version = readb(&q_ident->version); 3328 qti->supported = readb(&q_ident->supported); 3329 qti->features = readq(&q_ident->features); 3330 qti->desc_sz = readw(&q_ident->desc_sz); 3331 qti->comp_sz = readw(&q_ident->comp_sz); 3332 qti->sg_desc_sz = readw(&q_ident->sg_desc_sz); 3333 qti->max_sg_elems = readw(&q_ident->max_sg_elems); 3334 qti->sg_desc_stride = readw(&q_ident->sg_desc_stride); 3335 } 3336 mutex_unlock(&ionic->dev_cmd_lock); 3337 3338 if (err == -EINVAL) { 3339 dev_err(ionic->dev, "qtype %d not supported\n", qtype); 3340 continue; 3341 } else if (err == -EIO) { 3342 dev_err(ionic->dev, "q_ident failed, not supported on older FW\n"); 3343 return; 3344 } else if (err) { 3345 dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n", 3346 qtype, err); 3347 return; 3348 } 3349 3350 dev_dbg(ionic->dev, " qtype[%d].version = %d\n", 3351 qtype, qti->version); 3352 dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n", 3353 qtype, qti->supported); 3354 dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n", 3355 qtype, qti->features); 3356 dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n", 3357 qtype, qti->desc_sz); 3358 dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n", 3359 qtype, qti->comp_sz); 3360 dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n", 3361 qtype, qti->sg_desc_sz); 3362 dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n", 3363 qtype, qti->max_sg_elems); 3364 dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n", 3365 qtype, qti->sg_desc_stride); 3366 } 3367 } 3368 3369 int ionic_lif_identify(struct ionic *ionic, u8 lif_type, 3370 union ionic_lif_identity *lid) 3371 { 3372 struct ionic_dev *idev = &ionic->idev; 3373 size_t sz; 3374 int err; 3375 3376 sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data)); 3377 3378 mutex_lock(&ionic->dev_cmd_lock); 3379 ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1); 3380 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3381 memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz); 3382 mutex_unlock(&ionic->dev_cmd_lock); 3383 if (err) 3384 return (err); 3385 3386 dev_dbg(ionic->dev, "capabilities 0x%llx\n", 3387 le64_to_cpu(lid->capabilities)); 3388 3389 dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n", 3390 le32_to_cpu(lid->eth.max_ucast_filters)); 3391 dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n", 3392 le32_to_cpu(lid->eth.max_mcast_filters)); 3393 dev_dbg(ionic->dev, "eth.features 0x%llx\n", 3394 le64_to_cpu(lid->eth.config.features)); 3395 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n", 3396 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ])); 3397 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n", 3398 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ])); 3399 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n", 3400 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ])); 3401 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n", 3402 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ])); 3403 dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name); 3404 dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac); 3405 dev_dbg(ionic->dev, "eth.config.mtu %d\n", 3406 le32_to_cpu(lid->eth.config.mtu)); 3407 3408 return 0; 3409 } 3410 3411 int ionic_lif_size(struct ionic *ionic) 3412 { 3413 struct ionic_identity *ident = &ionic->ident; 3414 unsigned int nintrs, dev_nintrs; 3415 union ionic_lif_config *lc; 3416 unsigned int ntxqs_per_lif; 3417 unsigned int nrxqs_per_lif; 3418 unsigned int neqs_per_lif; 3419 unsigned int nnqs_per_lif; 3420 unsigned int nxqs, neqs; 3421 unsigned int min_intrs; 3422 int err; 3423 3424 /* retrieve basic values from FW */ 3425 lc = &ident->lif.eth.config; 3426 dev_nintrs = le32_to_cpu(ident->dev.nintrs); 3427 neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count); 3428 nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]); 3429 ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]); 3430 nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]); 3431 3432 /* limit values to play nice with kdump */ 3433 if (is_kdump_kernel()) { 3434 dev_nintrs = 2; 3435 neqs_per_lif = 0; 3436 nnqs_per_lif = 0; 3437 ntxqs_per_lif = 1; 3438 nrxqs_per_lif = 1; 3439 } 3440 3441 /* reserve last queue id for hardware timestamping */ 3442 if (lc->features & cpu_to_le64(IONIC_ETH_HW_TIMESTAMP)) { 3443 if (ntxqs_per_lif <= 1 || nrxqs_per_lif <= 1) { 3444 lc->features &= cpu_to_le64(~IONIC_ETH_HW_TIMESTAMP); 3445 } else { 3446 ntxqs_per_lif -= 1; 3447 nrxqs_per_lif -= 1; 3448 } 3449 } 3450 3451 nxqs = min(ntxqs_per_lif, nrxqs_per_lif); 3452 nxqs = min(nxqs, num_online_cpus()); 3453 neqs = min(neqs_per_lif, num_online_cpus()); 3454 3455 try_again: 3456 /* interrupt usage: 3457 * 1 for master lif adminq/notifyq 3458 * 1 for each CPU for master lif TxRx queue pairs 3459 * whatever's left is for RDMA queues 3460 */ 3461 nintrs = 1 + nxqs + neqs; 3462 min_intrs = 2; /* adminq + 1 TxRx queue pair */ 3463 3464 if (nintrs > dev_nintrs) 3465 goto try_fewer; 3466 3467 err = ionic_bus_alloc_irq_vectors(ionic, nintrs); 3468 if (err < 0 && err != -ENOSPC) { 3469 dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err); 3470 return err; 3471 } 3472 if (err == -ENOSPC) 3473 goto try_fewer; 3474 3475 if (err != nintrs) { 3476 ionic_bus_free_irq_vectors(ionic); 3477 goto try_fewer; 3478 } 3479 3480 ionic->nnqs_per_lif = nnqs_per_lif; 3481 ionic->neqs_per_lif = neqs; 3482 ionic->ntxqs_per_lif = nxqs; 3483 ionic->nrxqs_per_lif = nxqs; 3484 ionic->nintrs = nintrs; 3485 3486 ionic_debugfs_add_sizes(ionic); 3487 3488 return 0; 3489 3490 try_fewer: 3491 if (nnqs_per_lif > 1) { 3492 nnqs_per_lif >>= 1; 3493 goto try_again; 3494 } 3495 if (neqs > 1) { 3496 neqs >>= 1; 3497 goto try_again; 3498 } 3499 if (nxqs > 1) { 3500 nxqs >>= 1; 3501 goto try_again; 3502 } 3503 dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs); 3504 return -ENOSPC; 3505 } 3506