1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/ethtool.h> 5 #include <linux/printk.h> 6 #include <linux/dynamic_debug.h> 7 #include <linux/netdevice.h> 8 #include <linux/etherdevice.h> 9 #include <linux/if_vlan.h> 10 #include <linux/rtnetlink.h> 11 #include <linux/interrupt.h> 12 #include <linux/pci.h> 13 #include <linux/cpumask.h> 14 #include <linux/crash_dump.h> 15 16 #include "ionic.h" 17 #include "ionic_bus.h" 18 #include "ionic_lif.h" 19 #include "ionic_txrx.h" 20 #include "ionic_ethtool.h" 21 #include "ionic_debugfs.h" 22 23 /* queuetype support level */ 24 static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = { 25 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */ 26 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */ 27 [IONIC_QTYPE_RXQ] = 0, /* 0 = Base version with CQ+SG support */ 28 [IONIC_QTYPE_TXQ] = 1, /* 0 = Base version with CQ+SG support 29 * 1 = ... with Tx SG version 1 30 */ 31 }; 32 33 static void ionic_link_status_check(struct ionic_lif *lif); 34 static void ionic_lif_handle_fw_down(struct ionic_lif *lif); 35 static void ionic_lif_handle_fw_up(struct ionic_lif *lif); 36 static void ionic_lif_set_netdev_info(struct ionic_lif *lif); 37 38 static void ionic_txrx_deinit(struct ionic_lif *lif); 39 static int ionic_txrx_init(struct ionic_lif *lif); 40 static int ionic_start_queues(struct ionic_lif *lif); 41 static void ionic_stop_queues(struct ionic_lif *lif); 42 static void ionic_lif_queue_identify(struct ionic_lif *lif); 43 44 static void ionic_dim_work(struct work_struct *work) 45 { 46 struct dim *dim = container_of(work, struct dim, work); 47 struct dim_cq_moder cur_moder; 48 struct ionic_qcq *qcq; 49 u32 new_coal; 50 51 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 52 qcq = container_of(dim, struct ionic_qcq, dim); 53 new_coal = ionic_coal_usec_to_hw(qcq->q.lif->ionic, cur_moder.usec); 54 new_coal = new_coal ? new_coal : 1; 55 56 if (qcq->intr.dim_coal_hw != new_coal) { 57 unsigned int qi = qcq->cq.bound_q->index; 58 struct ionic_lif *lif = qcq->q.lif; 59 60 qcq->intr.dim_coal_hw = new_coal; 61 62 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 63 lif->rxqcqs[qi]->intr.index, 64 qcq->intr.dim_coal_hw); 65 } 66 67 dim->state = DIM_START_MEASURE; 68 } 69 70 static void ionic_lif_deferred_work(struct work_struct *work) 71 { 72 struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work); 73 struct ionic_deferred *def = &lif->deferred; 74 struct ionic_deferred_work *w = NULL; 75 76 do { 77 spin_lock_bh(&def->lock); 78 if (!list_empty(&def->list)) { 79 w = list_first_entry(&def->list, 80 struct ionic_deferred_work, list); 81 list_del(&w->list); 82 } 83 spin_unlock_bh(&def->lock); 84 85 if (!w) 86 break; 87 88 switch (w->type) { 89 case IONIC_DW_TYPE_RX_MODE: 90 ionic_lif_rx_mode(lif); 91 break; 92 case IONIC_DW_TYPE_LINK_STATUS: 93 ionic_link_status_check(lif); 94 break; 95 case IONIC_DW_TYPE_LIF_RESET: 96 if (w->fw_status) { 97 ionic_lif_handle_fw_up(lif); 98 } else { 99 ionic_lif_handle_fw_down(lif); 100 101 /* Fire off another watchdog to see 102 * if the FW is already back rather than 103 * waiting another whole cycle 104 */ 105 mod_timer(&lif->ionic->watchdog_timer, jiffies + 1); 106 } 107 break; 108 default: 109 break; 110 } 111 kfree(w); 112 w = NULL; 113 } while (true); 114 } 115 116 void ionic_lif_deferred_enqueue(struct ionic_deferred *def, 117 struct ionic_deferred_work *work) 118 { 119 spin_lock_bh(&def->lock); 120 list_add_tail(&work->list, &def->list); 121 spin_unlock_bh(&def->lock); 122 schedule_work(&def->work); 123 } 124 125 static void ionic_link_status_check(struct ionic_lif *lif) 126 { 127 struct net_device *netdev = lif->netdev; 128 u16 link_status; 129 bool link_up; 130 131 if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 132 return; 133 134 /* Don't put carrier back up if we're in a broken state */ 135 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) { 136 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 137 return; 138 } 139 140 link_status = le16_to_cpu(lif->info->status.link_status); 141 link_up = link_status == IONIC_PORT_OPER_STATUS_UP; 142 143 if (link_up) { 144 int err = 0; 145 146 if (netdev->flags & IFF_UP && netif_running(netdev)) { 147 mutex_lock(&lif->queue_lock); 148 err = ionic_start_queues(lif); 149 if (err && err != -EBUSY) { 150 netdev_err(lif->netdev, 151 "Failed to start queues: %d\n", err); 152 set_bit(IONIC_LIF_F_BROKEN, lif->state); 153 netif_carrier_off(lif->netdev); 154 } 155 mutex_unlock(&lif->queue_lock); 156 } 157 158 if (!err && !netif_carrier_ok(netdev)) { 159 ionic_port_identify(lif->ionic); 160 netdev_info(netdev, "Link up - %d Gbps\n", 161 le32_to_cpu(lif->info->status.link_speed) / 1000); 162 netif_carrier_on(netdev); 163 } 164 } else { 165 if (netif_carrier_ok(netdev)) { 166 netdev_info(netdev, "Link down\n"); 167 netif_carrier_off(netdev); 168 } 169 170 if (netdev->flags & IFF_UP && netif_running(netdev)) { 171 mutex_lock(&lif->queue_lock); 172 ionic_stop_queues(lif); 173 mutex_unlock(&lif->queue_lock); 174 } 175 } 176 177 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 178 } 179 180 void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep) 181 { 182 struct ionic_deferred_work *work; 183 184 /* we only need one request outstanding at a time */ 185 if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 186 return; 187 188 if (!can_sleep) { 189 work = kzalloc(sizeof(*work), GFP_ATOMIC); 190 if (!work) { 191 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 192 return; 193 } 194 195 work->type = IONIC_DW_TYPE_LINK_STATUS; 196 ionic_lif_deferred_enqueue(&lif->deferred, work); 197 } else { 198 ionic_link_status_check(lif); 199 } 200 } 201 202 static irqreturn_t ionic_isr(int irq, void *data) 203 { 204 struct napi_struct *napi = data; 205 206 napi_schedule_irqoff(napi); 207 208 return IRQ_HANDLED; 209 } 210 211 static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq) 212 { 213 struct ionic_intr_info *intr = &qcq->intr; 214 struct device *dev = lif->ionic->dev; 215 struct ionic_queue *q = &qcq->q; 216 const char *name; 217 218 if (lif->registered) 219 name = lif->netdev->name; 220 else 221 name = dev_name(dev); 222 223 snprintf(intr->name, sizeof(intr->name), 224 "%s-%s-%s", IONIC_DRV_NAME, name, q->name); 225 226 return devm_request_irq(dev, intr->vector, ionic_isr, 227 0, intr->name, &qcq->napi); 228 } 229 230 static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) 231 { 232 struct ionic *ionic = lif->ionic; 233 int index; 234 235 index = find_first_zero_bit(ionic->intrs, ionic->nintrs); 236 if (index == ionic->nintrs) { 237 netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n", 238 __func__, index, ionic->nintrs); 239 return -ENOSPC; 240 } 241 242 set_bit(index, ionic->intrs); 243 ionic_intr_init(&ionic->idev, intr, index); 244 245 return 0; 246 } 247 248 static void ionic_intr_free(struct ionic *ionic, int index) 249 { 250 if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < ionic->nintrs) 251 clear_bit(index, ionic->intrs); 252 } 253 254 static int ionic_qcq_enable(struct ionic_qcq *qcq) 255 { 256 struct ionic_queue *q = &qcq->q; 257 struct ionic_lif *lif = q->lif; 258 struct ionic_dev *idev; 259 struct device *dev; 260 261 struct ionic_admin_ctx ctx = { 262 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 263 .cmd.q_control = { 264 .opcode = IONIC_CMD_Q_CONTROL, 265 .lif_index = cpu_to_le16(lif->index), 266 .type = q->type, 267 .index = cpu_to_le32(q->index), 268 .oper = IONIC_Q_ENABLE, 269 }, 270 }; 271 272 idev = &lif->ionic->idev; 273 dev = lif->ionic->dev; 274 275 dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n", 276 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 277 278 if (qcq->flags & IONIC_QCQ_F_INTR) { 279 irq_set_affinity_hint(qcq->intr.vector, 280 &qcq->intr.affinity_mask); 281 napi_enable(&qcq->napi); 282 ionic_intr_clean(idev->intr_ctrl, qcq->intr.index); 283 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 284 IONIC_INTR_MASK_CLEAR); 285 } 286 287 return ionic_adminq_post_wait(lif, &ctx); 288 } 289 290 static int ionic_qcq_disable(struct ionic_qcq *qcq, bool send_to_hw) 291 { 292 struct ionic_queue *q; 293 struct ionic_lif *lif; 294 int err = 0; 295 296 struct ionic_admin_ctx ctx = { 297 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 298 .cmd.q_control = { 299 .opcode = IONIC_CMD_Q_CONTROL, 300 .oper = IONIC_Q_DISABLE, 301 }, 302 }; 303 304 if (!qcq) 305 return -ENXIO; 306 307 q = &qcq->q; 308 lif = q->lif; 309 310 if (qcq->flags & IONIC_QCQ_F_INTR) { 311 struct ionic_dev *idev = &lif->ionic->idev; 312 313 cancel_work_sync(&qcq->dim.work); 314 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 315 IONIC_INTR_MASK_SET); 316 synchronize_irq(qcq->intr.vector); 317 irq_set_affinity_hint(qcq->intr.vector, NULL); 318 napi_disable(&qcq->napi); 319 } 320 321 if (send_to_hw) { 322 ctx.cmd.q_control.lif_index = cpu_to_le16(lif->index); 323 ctx.cmd.q_control.type = q->type; 324 ctx.cmd.q_control.index = cpu_to_le32(q->index); 325 dev_dbg(lif->ionic->dev, "q_disable.index %d q_disable.qtype %d\n", 326 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 327 328 err = ionic_adminq_post_wait(lif, &ctx); 329 } 330 331 return err; 332 } 333 334 static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq) 335 { 336 struct ionic_dev *idev = &lif->ionic->idev; 337 338 if (!qcq) 339 return; 340 341 if (!(qcq->flags & IONIC_QCQ_F_INITED)) 342 return; 343 344 if (qcq->flags & IONIC_QCQ_F_INTR) { 345 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 346 IONIC_INTR_MASK_SET); 347 netif_napi_del(&qcq->napi); 348 } 349 350 qcq->flags &= ~IONIC_QCQ_F_INITED; 351 } 352 353 static void ionic_qcq_intr_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 354 { 355 if (!(qcq->flags & IONIC_QCQ_F_INTR) || qcq->intr.vector == 0) 356 return; 357 358 irq_set_affinity_hint(qcq->intr.vector, NULL); 359 devm_free_irq(lif->ionic->dev, qcq->intr.vector, &qcq->napi); 360 qcq->intr.vector = 0; 361 ionic_intr_free(lif->ionic, qcq->intr.index); 362 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 363 } 364 365 static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 366 { 367 struct device *dev = lif->ionic->dev; 368 369 if (!qcq) 370 return; 371 372 ionic_debugfs_del_qcq(qcq); 373 374 if (qcq->q_base) { 375 dma_free_coherent(dev, qcq->q_size, qcq->q_base, qcq->q_base_pa); 376 qcq->q_base = NULL; 377 qcq->q_base_pa = 0; 378 } 379 380 if (qcq->cq_base) { 381 dma_free_coherent(dev, qcq->cq_size, qcq->cq_base, qcq->cq_base_pa); 382 qcq->cq_base = NULL; 383 qcq->cq_base_pa = 0; 384 } 385 386 if (qcq->sg_base) { 387 dma_free_coherent(dev, qcq->sg_size, qcq->sg_base, qcq->sg_base_pa); 388 qcq->sg_base = NULL; 389 qcq->sg_base_pa = 0; 390 } 391 392 ionic_qcq_intr_free(lif, qcq); 393 394 if (qcq->cq.info) { 395 devm_kfree(dev, qcq->cq.info); 396 qcq->cq.info = NULL; 397 } 398 if (qcq->q.info) { 399 devm_kfree(dev, qcq->q.info); 400 qcq->q.info = NULL; 401 } 402 } 403 404 static void ionic_qcqs_free(struct ionic_lif *lif) 405 { 406 struct device *dev = lif->ionic->dev; 407 struct ionic_qcq *adminqcq; 408 unsigned long irqflags; 409 410 if (lif->notifyqcq) { 411 ionic_qcq_free(lif, lif->notifyqcq); 412 devm_kfree(dev, lif->notifyqcq); 413 lif->notifyqcq = NULL; 414 } 415 416 if (lif->adminqcq) { 417 spin_lock_irqsave(&lif->adminq_lock, irqflags); 418 adminqcq = READ_ONCE(lif->adminqcq); 419 lif->adminqcq = NULL; 420 spin_unlock_irqrestore(&lif->adminq_lock, irqflags); 421 if (adminqcq) { 422 ionic_qcq_free(lif, adminqcq); 423 devm_kfree(dev, adminqcq); 424 } 425 } 426 427 if (lif->rxqcqs) { 428 devm_kfree(dev, lif->rxqstats); 429 lif->rxqstats = NULL; 430 devm_kfree(dev, lif->rxqcqs); 431 lif->rxqcqs = NULL; 432 } 433 434 if (lif->txqcqs) { 435 devm_kfree(dev, lif->txqstats); 436 lif->txqstats = NULL; 437 devm_kfree(dev, lif->txqcqs); 438 lif->txqcqs = NULL; 439 } 440 } 441 442 static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq, 443 struct ionic_qcq *n_qcq) 444 { 445 if (WARN_ON(n_qcq->flags & IONIC_QCQ_F_INTR)) { 446 ionic_intr_free(n_qcq->cq.lif->ionic, n_qcq->intr.index); 447 n_qcq->flags &= ~IONIC_QCQ_F_INTR; 448 } 449 450 n_qcq->intr.vector = src_qcq->intr.vector; 451 n_qcq->intr.index = src_qcq->intr.index; 452 } 453 454 static int ionic_alloc_qcq_interrupt(struct ionic_lif *lif, struct ionic_qcq *qcq) 455 { 456 int err; 457 458 if (!(qcq->flags & IONIC_QCQ_F_INTR)) { 459 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 460 return 0; 461 } 462 463 err = ionic_intr_alloc(lif, &qcq->intr); 464 if (err) { 465 netdev_warn(lif->netdev, "no intr for %s: %d\n", 466 qcq->q.name, err); 467 goto err_out; 468 } 469 470 err = ionic_bus_get_irq(lif->ionic, qcq->intr.index); 471 if (err < 0) { 472 netdev_warn(lif->netdev, "no vector for %s: %d\n", 473 qcq->q.name, err); 474 goto err_out_free_intr; 475 } 476 qcq->intr.vector = err; 477 ionic_intr_mask_assert(lif->ionic->idev.intr_ctrl, qcq->intr.index, 478 IONIC_INTR_MASK_SET); 479 480 err = ionic_request_irq(lif, qcq); 481 if (err) { 482 netdev_warn(lif->netdev, "irq request failed %d\n", err); 483 goto err_out_free_intr; 484 } 485 486 /* try to get the irq on the local numa node first */ 487 qcq->intr.cpu = cpumask_local_spread(qcq->intr.index, 488 dev_to_node(lif->ionic->dev)); 489 if (qcq->intr.cpu != -1) 490 cpumask_set_cpu(qcq->intr.cpu, &qcq->intr.affinity_mask); 491 492 netdev_dbg(lif->netdev, "%s: Interrupt index %d\n", qcq->q.name, qcq->intr.index); 493 return 0; 494 495 err_out_free_intr: 496 ionic_intr_free(lif->ionic, qcq->intr.index); 497 err_out: 498 return err; 499 } 500 501 static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type, 502 unsigned int index, 503 const char *name, unsigned int flags, 504 unsigned int num_descs, unsigned int desc_size, 505 unsigned int cq_desc_size, 506 unsigned int sg_desc_size, 507 unsigned int pid, struct ionic_qcq **qcq) 508 { 509 struct ionic_dev *idev = &lif->ionic->idev; 510 struct device *dev = lif->ionic->dev; 511 void *q_base, *cq_base, *sg_base; 512 dma_addr_t cq_base_pa = 0; 513 dma_addr_t sg_base_pa = 0; 514 dma_addr_t q_base_pa = 0; 515 struct ionic_qcq *new; 516 int err; 517 518 *qcq = NULL; 519 520 new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL); 521 if (!new) { 522 netdev_err(lif->netdev, "Cannot allocate queue structure\n"); 523 err = -ENOMEM; 524 goto err_out; 525 } 526 527 new->q.dev = dev; 528 new->flags = flags; 529 530 new->q.info = devm_kcalloc(dev, num_descs, sizeof(*new->q.info), 531 GFP_KERNEL); 532 if (!new->q.info) { 533 netdev_err(lif->netdev, "Cannot allocate queue info\n"); 534 err = -ENOMEM; 535 goto err_out_free_qcq; 536 } 537 538 new->q.type = type; 539 new->q.max_sg_elems = lif->qtype_info[type].max_sg_elems; 540 541 err = ionic_q_init(lif, idev, &new->q, index, name, num_descs, 542 desc_size, sg_desc_size, pid); 543 if (err) { 544 netdev_err(lif->netdev, "Cannot initialize queue\n"); 545 goto err_out_free_q_info; 546 } 547 548 err = ionic_alloc_qcq_interrupt(lif, new); 549 if (err) 550 goto err_out; 551 552 new->cq.info = devm_kcalloc(dev, num_descs, sizeof(*new->cq.info), 553 GFP_KERNEL); 554 if (!new->cq.info) { 555 netdev_err(lif->netdev, "Cannot allocate completion queue info\n"); 556 err = -ENOMEM; 557 goto err_out_free_irq; 558 } 559 560 err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size); 561 if (err) { 562 netdev_err(lif->netdev, "Cannot initialize completion queue\n"); 563 goto err_out_free_cq_info; 564 } 565 566 if (flags & IONIC_QCQ_F_NOTIFYQ) { 567 int q_size, cq_size; 568 569 /* q & cq need to be contiguous in case of notifyq */ 570 q_size = ALIGN(num_descs * desc_size, PAGE_SIZE); 571 cq_size = ALIGN(num_descs * cq_desc_size, PAGE_SIZE); 572 573 new->q_size = PAGE_SIZE + q_size + cq_size; 574 new->q_base = dma_alloc_coherent(dev, new->q_size, 575 &new->q_base_pa, GFP_KERNEL); 576 if (!new->q_base) { 577 netdev_err(lif->netdev, "Cannot allocate qcq DMA memory\n"); 578 err = -ENOMEM; 579 goto err_out_free_cq_info; 580 } 581 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE); 582 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 583 ionic_q_map(&new->q, q_base, q_base_pa); 584 585 cq_base = PTR_ALIGN(q_base + q_size, PAGE_SIZE); 586 cq_base_pa = ALIGN(new->q_base_pa + q_size, PAGE_SIZE); 587 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 588 ionic_cq_bind(&new->cq, &new->q); 589 } else { 590 new->q_size = PAGE_SIZE + (num_descs * desc_size); 591 new->q_base = dma_alloc_coherent(dev, new->q_size, &new->q_base_pa, 592 GFP_KERNEL); 593 if (!new->q_base) { 594 netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n"); 595 err = -ENOMEM; 596 goto err_out_free_cq_info; 597 } 598 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE); 599 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 600 ionic_q_map(&new->q, q_base, q_base_pa); 601 602 new->cq_size = PAGE_SIZE + (num_descs * cq_desc_size); 603 new->cq_base = dma_alloc_coherent(dev, new->cq_size, &new->cq_base_pa, 604 GFP_KERNEL); 605 if (!new->cq_base) { 606 netdev_err(lif->netdev, "Cannot allocate cq DMA memory\n"); 607 err = -ENOMEM; 608 goto err_out_free_q; 609 } 610 cq_base = PTR_ALIGN(new->cq_base, PAGE_SIZE); 611 cq_base_pa = ALIGN(new->cq_base_pa, PAGE_SIZE); 612 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 613 ionic_cq_bind(&new->cq, &new->q); 614 } 615 616 if (flags & IONIC_QCQ_F_SG) { 617 new->sg_size = PAGE_SIZE + (num_descs * sg_desc_size); 618 new->sg_base = dma_alloc_coherent(dev, new->sg_size, &new->sg_base_pa, 619 GFP_KERNEL); 620 if (!new->sg_base) { 621 netdev_err(lif->netdev, "Cannot allocate sg DMA memory\n"); 622 err = -ENOMEM; 623 goto err_out_free_cq; 624 } 625 sg_base = PTR_ALIGN(new->sg_base, PAGE_SIZE); 626 sg_base_pa = ALIGN(new->sg_base_pa, PAGE_SIZE); 627 ionic_q_sg_map(&new->q, sg_base, sg_base_pa); 628 } 629 630 INIT_WORK(&new->dim.work, ionic_dim_work); 631 new->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 632 633 *qcq = new; 634 635 return 0; 636 637 err_out_free_cq: 638 dma_free_coherent(dev, new->cq_size, new->cq_base, new->cq_base_pa); 639 err_out_free_q: 640 dma_free_coherent(dev, new->q_size, new->q_base, new->q_base_pa); 641 err_out_free_cq_info: 642 devm_kfree(dev, new->cq.info); 643 err_out_free_irq: 644 if (flags & IONIC_QCQ_F_INTR) { 645 devm_free_irq(dev, new->intr.vector, &new->napi); 646 ionic_intr_free(lif->ionic, new->intr.index); 647 } 648 err_out_free_q_info: 649 devm_kfree(dev, new->q.info); 650 err_out_free_qcq: 651 devm_kfree(dev, new); 652 err_out: 653 dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err); 654 return err; 655 } 656 657 static int ionic_qcqs_alloc(struct ionic_lif *lif) 658 { 659 struct device *dev = lif->ionic->dev; 660 unsigned int flags; 661 int err; 662 663 flags = IONIC_QCQ_F_INTR; 664 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags, 665 IONIC_ADMINQ_LENGTH, 666 sizeof(struct ionic_admin_cmd), 667 sizeof(struct ionic_admin_comp), 668 0, lif->kern_pid, &lif->adminqcq); 669 if (err) 670 return err; 671 ionic_debugfs_add_qcq(lif, lif->adminqcq); 672 673 if (lif->ionic->nnqs_per_lif) { 674 flags = IONIC_QCQ_F_NOTIFYQ; 675 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq", 676 flags, IONIC_NOTIFYQ_LENGTH, 677 sizeof(struct ionic_notifyq_cmd), 678 sizeof(union ionic_notifyq_comp), 679 0, lif->kern_pid, &lif->notifyqcq); 680 if (err) 681 goto err_out; 682 ionic_debugfs_add_qcq(lif, lif->notifyqcq); 683 684 /* Let the notifyq ride on the adminq interrupt */ 685 ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq); 686 } 687 688 err = -ENOMEM; 689 lif->txqcqs = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif, 690 sizeof(*lif->txqcqs), GFP_KERNEL); 691 if (!lif->txqcqs) 692 goto err_out; 693 lif->rxqcqs = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif, 694 sizeof(*lif->rxqcqs), GFP_KERNEL); 695 if (!lif->rxqcqs) 696 goto err_out; 697 698 lif->txqstats = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif + 1, 699 sizeof(*lif->txqstats), GFP_KERNEL); 700 if (!lif->txqstats) 701 goto err_out; 702 lif->rxqstats = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif + 1, 703 sizeof(*lif->rxqstats), GFP_KERNEL); 704 if (!lif->rxqstats) 705 goto err_out; 706 707 return 0; 708 709 err_out: 710 ionic_qcqs_free(lif); 711 return err; 712 } 713 714 static void ionic_qcq_sanitize(struct ionic_qcq *qcq) 715 { 716 qcq->q.tail_idx = 0; 717 qcq->q.head_idx = 0; 718 qcq->cq.tail_idx = 0; 719 qcq->cq.done_color = 1; 720 memset(qcq->q_base, 0, qcq->q_size); 721 memset(qcq->cq_base, 0, qcq->cq_size); 722 memset(qcq->sg_base, 0, qcq->sg_size); 723 } 724 725 static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 726 { 727 struct device *dev = lif->ionic->dev; 728 struct ionic_queue *q = &qcq->q; 729 struct ionic_cq *cq = &qcq->cq; 730 struct ionic_admin_ctx ctx = { 731 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 732 .cmd.q_init = { 733 .opcode = IONIC_CMD_Q_INIT, 734 .lif_index = cpu_to_le16(lif->index), 735 .type = q->type, 736 .ver = lif->qtype_info[q->type].version, 737 .index = cpu_to_le32(q->index), 738 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 739 IONIC_QINIT_F_SG), 740 .pid = cpu_to_le16(q->pid), 741 .ring_size = ilog2(q->num_descs), 742 .ring_base = cpu_to_le64(q->base_pa), 743 .cq_ring_base = cpu_to_le64(cq->base_pa), 744 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 745 .features = cpu_to_le64(q->features), 746 }, 747 }; 748 unsigned int intr_index; 749 int err; 750 751 intr_index = qcq->intr.index; 752 753 ctx.cmd.q_init.intr_index = cpu_to_le16(intr_index); 754 755 dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid); 756 dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index); 757 dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 758 dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 759 dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 760 dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver); 761 dev_dbg(dev, "txq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 762 763 ionic_qcq_sanitize(qcq); 764 765 err = ionic_adminq_post_wait(lif, &ctx); 766 if (err) 767 return err; 768 769 q->hw_type = ctx.comp.q_init.hw_type; 770 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 771 q->dbval = IONIC_DBELL_QID(q->hw_index); 772 773 dev_dbg(dev, "txq->hw_type %d\n", q->hw_type); 774 dev_dbg(dev, "txq->hw_index %d\n", q->hw_index); 775 776 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 777 netif_napi_add(lif->netdev, &qcq->napi, ionic_tx_napi, 778 NAPI_POLL_WEIGHT); 779 780 qcq->flags |= IONIC_QCQ_F_INITED; 781 782 return 0; 783 } 784 785 static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 786 { 787 struct device *dev = lif->ionic->dev; 788 struct ionic_queue *q = &qcq->q; 789 struct ionic_cq *cq = &qcq->cq; 790 struct ionic_admin_ctx ctx = { 791 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 792 .cmd.q_init = { 793 .opcode = IONIC_CMD_Q_INIT, 794 .lif_index = cpu_to_le16(lif->index), 795 .type = q->type, 796 .ver = lif->qtype_info[q->type].version, 797 .index = cpu_to_le32(q->index), 798 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 799 IONIC_QINIT_F_SG), 800 .intr_index = cpu_to_le16(cq->bound_intr->index), 801 .pid = cpu_to_le16(q->pid), 802 .ring_size = ilog2(q->num_descs), 803 .ring_base = cpu_to_le64(q->base_pa), 804 .cq_ring_base = cpu_to_le64(cq->base_pa), 805 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 806 .features = cpu_to_le64(q->features), 807 }, 808 }; 809 int err; 810 811 dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid); 812 dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index); 813 dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 814 dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 815 dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 816 dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver); 817 dev_dbg(dev, "rxq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 818 819 ionic_qcq_sanitize(qcq); 820 821 err = ionic_adminq_post_wait(lif, &ctx); 822 if (err) 823 return err; 824 825 q->hw_type = ctx.comp.q_init.hw_type; 826 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 827 q->dbval = IONIC_DBELL_QID(q->hw_index); 828 829 dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type); 830 dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index); 831 832 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 833 netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi, 834 NAPI_POLL_WEIGHT); 835 else 836 netif_napi_add(lif->netdev, &qcq->napi, ionic_txrx_napi, 837 NAPI_POLL_WEIGHT); 838 839 qcq->flags |= IONIC_QCQ_F_INITED; 840 841 return 0; 842 } 843 844 int ionic_lif_create_hwstamp_txq(struct ionic_lif *lif) 845 { 846 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz; 847 unsigned int txq_i, flags; 848 struct ionic_qcq *txq; 849 u64 features; 850 int err; 851 852 if (lif->hwstamp_txq) 853 return 0; 854 855 features = IONIC_Q_F_2X_CQ_DESC | IONIC_TXQ_F_HWSTAMP; 856 857 num_desc = IONIC_MIN_TXRX_DESC; 858 desc_sz = sizeof(struct ionic_txq_desc); 859 comp_sz = 2 * sizeof(struct ionic_txq_comp); 860 861 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 862 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == sizeof(struct ionic_txq_sg_desc_v1)) 863 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 864 else 865 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 866 867 txq_i = lif->ionic->ntxqs_per_lif; 868 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 869 870 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, txq_i, "hwstamp_tx", flags, 871 num_desc, desc_sz, comp_sz, sg_desc_sz, 872 lif->kern_pid, &txq); 873 if (err) 874 goto err_qcq_alloc; 875 876 txq->q.features = features; 877 878 ionic_link_qcq_interrupts(lif->adminqcq, txq); 879 ionic_debugfs_add_qcq(lif, txq); 880 881 lif->hwstamp_txq = txq; 882 883 if (netif_running(lif->netdev)) { 884 err = ionic_lif_txq_init(lif, txq); 885 if (err) 886 goto err_qcq_init; 887 888 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 889 err = ionic_qcq_enable(txq); 890 if (err) 891 goto err_qcq_enable; 892 } 893 } 894 895 return 0; 896 897 err_qcq_enable: 898 ionic_lif_qcq_deinit(lif, txq); 899 err_qcq_init: 900 lif->hwstamp_txq = NULL; 901 ionic_debugfs_del_qcq(txq); 902 ionic_qcq_free(lif, txq); 903 devm_kfree(lif->ionic->dev, txq); 904 err_qcq_alloc: 905 return err; 906 } 907 908 int ionic_lif_create_hwstamp_rxq(struct ionic_lif *lif) 909 { 910 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz; 911 unsigned int rxq_i, flags; 912 struct ionic_qcq *rxq; 913 u64 features; 914 int err; 915 916 if (lif->hwstamp_rxq) 917 return 0; 918 919 features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP; 920 921 num_desc = IONIC_MIN_TXRX_DESC; 922 desc_sz = sizeof(struct ionic_rxq_desc); 923 comp_sz = 2 * sizeof(struct ionic_rxq_comp); 924 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 925 926 rxq_i = lif->ionic->nrxqs_per_lif; 927 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG; 928 929 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, rxq_i, "hwstamp_rx", flags, 930 num_desc, desc_sz, comp_sz, sg_desc_sz, 931 lif->kern_pid, &rxq); 932 if (err) 933 goto err_qcq_alloc; 934 935 rxq->q.features = features; 936 937 ionic_link_qcq_interrupts(lif->adminqcq, rxq); 938 ionic_debugfs_add_qcq(lif, rxq); 939 940 lif->hwstamp_rxq = rxq; 941 942 if (netif_running(lif->netdev)) { 943 err = ionic_lif_rxq_init(lif, rxq); 944 if (err) 945 goto err_qcq_init; 946 947 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 948 ionic_rx_fill(&rxq->q); 949 err = ionic_qcq_enable(rxq); 950 if (err) 951 goto err_qcq_enable; 952 } 953 } 954 955 return 0; 956 957 err_qcq_enable: 958 ionic_lif_qcq_deinit(lif, rxq); 959 err_qcq_init: 960 lif->hwstamp_rxq = NULL; 961 ionic_debugfs_del_qcq(rxq); 962 ionic_qcq_free(lif, rxq); 963 devm_kfree(lif->ionic->dev, rxq); 964 err_qcq_alloc: 965 return err; 966 } 967 968 int ionic_lif_config_hwstamp_rxq_all(struct ionic_lif *lif, bool rx_all) 969 { 970 struct ionic_queue_params qparam; 971 972 ionic_init_queue_params(lif, &qparam); 973 974 if (rx_all) 975 qparam.rxq_features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP; 976 else 977 qparam.rxq_features = 0; 978 979 /* if we're not running, just set the values and return */ 980 if (!netif_running(lif->netdev)) { 981 lif->rxq_features = qparam.rxq_features; 982 return 0; 983 } 984 985 return ionic_reconfigure_queues(lif, &qparam); 986 } 987 988 int ionic_lif_set_hwstamp_txmode(struct ionic_lif *lif, u16 txstamp_mode) 989 { 990 struct ionic_admin_ctx ctx = { 991 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 992 .cmd.lif_setattr = { 993 .opcode = IONIC_CMD_LIF_SETATTR, 994 .index = cpu_to_le16(lif->index), 995 .attr = IONIC_LIF_ATTR_TXSTAMP, 996 .txstamp_mode = cpu_to_le16(txstamp_mode), 997 }, 998 }; 999 1000 return ionic_adminq_post_wait(lif, &ctx); 1001 } 1002 1003 static void ionic_lif_del_hwstamp_rxfilt(struct ionic_lif *lif) 1004 { 1005 struct ionic_admin_ctx ctx = { 1006 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1007 .cmd.rx_filter_del = { 1008 .opcode = IONIC_CMD_RX_FILTER_DEL, 1009 .lif_index = cpu_to_le16(lif->index), 1010 }, 1011 }; 1012 struct ionic_rx_filter *f; 1013 u32 filter_id; 1014 int err; 1015 1016 spin_lock_bh(&lif->rx_filters.lock); 1017 1018 f = ionic_rx_filter_rxsteer(lif); 1019 if (!f) { 1020 spin_unlock_bh(&lif->rx_filters.lock); 1021 return; 1022 } 1023 1024 filter_id = f->filter_id; 1025 ionic_rx_filter_free(lif, f); 1026 1027 spin_unlock_bh(&lif->rx_filters.lock); 1028 1029 netdev_dbg(lif->netdev, "rx_filter del RXSTEER (id %d)\n", filter_id); 1030 1031 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(filter_id); 1032 1033 err = ionic_adminq_post_wait(lif, &ctx); 1034 if (err && err != -EEXIST) 1035 netdev_dbg(lif->netdev, "failed to delete rx_filter RXSTEER (id %d)\n", filter_id); 1036 } 1037 1038 static int ionic_lif_add_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class) 1039 { 1040 struct ionic_admin_ctx ctx = { 1041 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1042 .cmd.rx_filter_add = { 1043 .opcode = IONIC_CMD_RX_FILTER_ADD, 1044 .lif_index = cpu_to_le16(lif->index), 1045 .match = cpu_to_le16(IONIC_RX_FILTER_STEER_PKTCLASS), 1046 .pkt_class = cpu_to_le64(pkt_class), 1047 }, 1048 }; 1049 u8 qtype; 1050 u32 qid; 1051 int err; 1052 1053 if (!lif->hwstamp_rxq) 1054 return -EINVAL; 1055 1056 qtype = lif->hwstamp_rxq->q.type; 1057 ctx.cmd.rx_filter_add.qtype = qtype; 1058 1059 qid = lif->hwstamp_rxq->q.index; 1060 ctx.cmd.rx_filter_add.qid = cpu_to_le32(qid); 1061 1062 netdev_dbg(lif->netdev, "rx_filter add RXSTEER\n"); 1063 err = ionic_adminq_post_wait(lif, &ctx); 1064 if (err && err != -EEXIST) 1065 return err; 1066 1067 spin_lock_bh(&lif->rx_filters.lock); 1068 err = ionic_rx_filter_save(lif, 0, qid, 0, &ctx, IONIC_FILTER_STATE_SYNCED); 1069 spin_unlock_bh(&lif->rx_filters.lock); 1070 1071 return err; 1072 } 1073 1074 int ionic_lif_set_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class) 1075 { 1076 ionic_lif_del_hwstamp_rxfilt(lif); 1077 1078 if (!pkt_class) 1079 return 0; 1080 1081 return ionic_lif_add_hwstamp_rxfilt(lif, pkt_class); 1082 } 1083 1084 static bool ionic_notifyq_service(struct ionic_cq *cq, 1085 struct ionic_cq_info *cq_info) 1086 { 1087 union ionic_notifyq_comp *comp = cq_info->cq_desc; 1088 struct ionic_deferred_work *work; 1089 struct net_device *netdev; 1090 struct ionic_queue *q; 1091 struct ionic_lif *lif; 1092 u64 eid; 1093 1094 q = cq->bound_q; 1095 lif = q->info[0].cb_arg; 1096 netdev = lif->netdev; 1097 eid = le64_to_cpu(comp->event.eid); 1098 1099 /* Have we run out of new completions to process? */ 1100 if ((s64)(eid - lif->last_eid) <= 0) 1101 return false; 1102 1103 lif->last_eid = eid; 1104 1105 dev_dbg(lif->ionic->dev, "notifyq event:\n"); 1106 dynamic_hex_dump("event ", DUMP_PREFIX_OFFSET, 16, 1, 1107 comp, sizeof(*comp), true); 1108 1109 switch (le16_to_cpu(comp->event.ecode)) { 1110 case IONIC_EVENT_LINK_CHANGE: 1111 ionic_link_status_check_request(lif, CAN_NOT_SLEEP); 1112 break; 1113 case IONIC_EVENT_RESET: 1114 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1115 if (!work) { 1116 netdev_err(lif->netdev, "Reset event dropped\n"); 1117 } else { 1118 work->type = IONIC_DW_TYPE_LIF_RESET; 1119 ionic_lif_deferred_enqueue(&lif->deferred, work); 1120 } 1121 break; 1122 default: 1123 netdev_warn(netdev, "Notifyq event ecode=%d eid=%lld\n", 1124 comp->event.ecode, eid); 1125 break; 1126 } 1127 1128 return true; 1129 } 1130 1131 static bool ionic_adminq_service(struct ionic_cq *cq, 1132 struct ionic_cq_info *cq_info) 1133 { 1134 struct ionic_admin_comp *comp = cq_info->cq_desc; 1135 1136 if (!color_match(comp->color, cq->done_color)) 1137 return false; 1138 1139 ionic_q_service(cq->bound_q, cq_info, le16_to_cpu(comp->comp_index)); 1140 1141 return true; 1142 } 1143 1144 static int ionic_adminq_napi(struct napi_struct *napi, int budget) 1145 { 1146 struct ionic_intr_info *intr = napi_to_cq(napi)->bound_intr; 1147 struct ionic_lif *lif = napi_to_cq(napi)->lif; 1148 struct ionic_dev *idev = &lif->ionic->idev; 1149 unsigned long irqflags; 1150 unsigned int flags = 0; 1151 int rx_work = 0; 1152 int tx_work = 0; 1153 int n_work = 0; 1154 int a_work = 0; 1155 int work_done; 1156 int credits; 1157 1158 if (lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED) 1159 n_work = ionic_cq_service(&lif->notifyqcq->cq, budget, 1160 ionic_notifyq_service, NULL, NULL); 1161 1162 spin_lock_irqsave(&lif->adminq_lock, irqflags); 1163 if (lif->adminqcq && lif->adminqcq->flags & IONIC_QCQ_F_INITED) 1164 a_work = ionic_cq_service(&lif->adminqcq->cq, budget, 1165 ionic_adminq_service, NULL, NULL); 1166 spin_unlock_irqrestore(&lif->adminq_lock, irqflags); 1167 1168 if (lif->hwstamp_rxq) 1169 rx_work = ionic_cq_service(&lif->hwstamp_rxq->cq, budget, 1170 ionic_rx_service, NULL, NULL); 1171 1172 if (lif->hwstamp_txq) 1173 tx_work = ionic_cq_service(&lif->hwstamp_txq->cq, budget, 1174 ionic_tx_service, NULL, NULL); 1175 1176 work_done = max(max(n_work, a_work), max(rx_work, tx_work)); 1177 if (work_done < budget && napi_complete_done(napi, work_done)) { 1178 flags |= IONIC_INTR_CRED_UNMASK; 1179 intr->rearm_count++; 1180 } 1181 1182 if (work_done || flags) { 1183 flags |= IONIC_INTR_CRED_RESET_COALESCE; 1184 credits = n_work + a_work + rx_work + tx_work; 1185 ionic_intr_credits(idev->intr_ctrl, intr->index, credits, flags); 1186 } 1187 1188 return work_done; 1189 } 1190 1191 void ionic_get_stats64(struct net_device *netdev, 1192 struct rtnl_link_stats64 *ns) 1193 { 1194 struct ionic_lif *lif = netdev_priv(netdev); 1195 struct ionic_lif_stats *ls; 1196 1197 memset(ns, 0, sizeof(*ns)); 1198 ls = &lif->info->stats; 1199 1200 ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) + 1201 le64_to_cpu(ls->rx_mcast_packets) + 1202 le64_to_cpu(ls->rx_bcast_packets); 1203 1204 ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) + 1205 le64_to_cpu(ls->tx_mcast_packets) + 1206 le64_to_cpu(ls->tx_bcast_packets); 1207 1208 ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) + 1209 le64_to_cpu(ls->rx_mcast_bytes) + 1210 le64_to_cpu(ls->rx_bcast_bytes); 1211 1212 ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) + 1213 le64_to_cpu(ls->tx_mcast_bytes) + 1214 le64_to_cpu(ls->tx_bcast_bytes); 1215 1216 ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) + 1217 le64_to_cpu(ls->rx_mcast_drop_packets) + 1218 le64_to_cpu(ls->rx_bcast_drop_packets); 1219 1220 ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) + 1221 le64_to_cpu(ls->tx_mcast_drop_packets) + 1222 le64_to_cpu(ls->tx_bcast_drop_packets); 1223 1224 ns->multicast = le64_to_cpu(ls->rx_mcast_packets); 1225 1226 ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty); 1227 1228 ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) + 1229 le64_to_cpu(ls->rx_queue_disabled) + 1230 le64_to_cpu(ls->rx_desc_fetch_error) + 1231 le64_to_cpu(ls->rx_desc_data_error); 1232 1233 ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) + 1234 le64_to_cpu(ls->tx_queue_disabled) + 1235 le64_to_cpu(ls->tx_desc_fetch_error) + 1236 le64_to_cpu(ls->tx_desc_data_error); 1237 1238 ns->rx_errors = ns->rx_over_errors + 1239 ns->rx_missed_errors; 1240 1241 ns->tx_errors = ns->tx_aborted_errors; 1242 } 1243 1244 int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr) 1245 { 1246 struct ionic_admin_ctx ctx = { 1247 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1248 .cmd.rx_filter_add = { 1249 .opcode = IONIC_CMD_RX_FILTER_ADD, 1250 .lif_index = cpu_to_le16(lif->index), 1251 .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_MAC), 1252 }, 1253 }; 1254 int nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters); 1255 bool mc = is_multicast_ether_addr(addr); 1256 struct ionic_rx_filter *f; 1257 int err = 0; 1258 1259 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, ETH_ALEN); 1260 1261 spin_lock_bh(&lif->rx_filters.lock); 1262 f = ionic_rx_filter_by_addr(lif, addr); 1263 if (f) { 1264 /* don't bother if we already have it and it is sync'd */ 1265 if (f->state == IONIC_FILTER_STATE_SYNCED) { 1266 spin_unlock_bh(&lif->rx_filters.lock); 1267 return 0; 1268 } 1269 1270 /* mark preemptively as sync'd to block any parallel attempts */ 1271 f->state = IONIC_FILTER_STATE_SYNCED; 1272 } else { 1273 /* save as SYNCED to catch any DEL requests while processing */ 1274 err = ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx, 1275 IONIC_FILTER_STATE_SYNCED); 1276 } 1277 spin_unlock_bh(&lif->rx_filters.lock); 1278 if (err) 1279 return err; 1280 1281 netdev_dbg(lif->netdev, "rx_filter add ADDR %pM\n", addr); 1282 1283 /* Don't bother with the write to FW if we know there's no room, 1284 * we can try again on the next sync attempt. 1285 */ 1286 if ((lif->nucast + lif->nmcast) >= nfilters) 1287 err = -ENOSPC; 1288 else 1289 err = ionic_adminq_post_wait(lif, &ctx); 1290 1291 spin_lock_bh(&lif->rx_filters.lock); 1292 if (err && err != -EEXIST) { 1293 /* set the state back to NEW so we can try again later */ 1294 f = ionic_rx_filter_by_addr(lif, addr); 1295 if (f && f->state == IONIC_FILTER_STATE_SYNCED) { 1296 f->state = IONIC_FILTER_STATE_NEW; 1297 set_bit(IONIC_LIF_F_FILTER_SYNC_NEEDED, lif->state); 1298 } 1299 1300 spin_unlock_bh(&lif->rx_filters.lock); 1301 1302 if (err == -ENOSPC) 1303 return 0; 1304 else 1305 return err; 1306 } 1307 1308 if (mc) 1309 lif->nmcast++; 1310 else 1311 lif->nucast++; 1312 1313 f = ionic_rx_filter_by_addr(lif, addr); 1314 if (f && f->state == IONIC_FILTER_STATE_OLD) { 1315 /* Someone requested a delete while we were adding 1316 * so update the filter info with the results from the add 1317 * and the data will be there for the delete on the next 1318 * sync cycle. 1319 */ 1320 err = ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx, 1321 IONIC_FILTER_STATE_OLD); 1322 } else { 1323 err = ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx, 1324 IONIC_FILTER_STATE_SYNCED); 1325 } 1326 1327 spin_unlock_bh(&lif->rx_filters.lock); 1328 1329 return err; 1330 } 1331 1332 int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr) 1333 { 1334 struct ionic_admin_ctx ctx = { 1335 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1336 .cmd.rx_filter_del = { 1337 .opcode = IONIC_CMD_RX_FILTER_DEL, 1338 .lif_index = cpu_to_le16(lif->index), 1339 }, 1340 }; 1341 struct ionic_rx_filter *f; 1342 int state; 1343 int err; 1344 1345 spin_lock_bh(&lif->rx_filters.lock); 1346 f = ionic_rx_filter_by_addr(lif, addr); 1347 if (!f) { 1348 spin_unlock_bh(&lif->rx_filters.lock); 1349 return -ENOENT; 1350 } 1351 1352 netdev_dbg(lif->netdev, "rx_filter del ADDR %pM (id %d)\n", 1353 addr, f->filter_id); 1354 1355 state = f->state; 1356 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id); 1357 ionic_rx_filter_free(lif, f); 1358 1359 if (is_multicast_ether_addr(addr) && lif->nmcast) 1360 lif->nmcast--; 1361 else if (!is_multicast_ether_addr(addr) && lif->nucast) 1362 lif->nucast--; 1363 1364 spin_unlock_bh(&lif->rx_filters.lock); 1365 1366 if (state != IONIC_FILTER_STATE_NEW) { 1367 err = ionic_adminq_post_wait(lif, &ctx); 1368 if (err && err != -EEXIST) 1369 return err; 1370 } 1371 1372 return 0; 1373 } 1374 1375 static int ionic_addr_add(struct net_device *netdev, const u8 *addr) 1376 { 1377 return ionic_lif_list_addr(netdev_priv(netdev), addr, ADD_ADDR); 1378 } 1379 1380 static int ionic_addr_del(struct net_device *netdev, const u8 *addr) 1381 { 1382 return ionic_lif_list_addr(netdev_priv(netdev), addr, DEL_ADDR); 1383 } 1384 1385 void ionic_lif_rx_mode(struct ionic_lif *lif) 1386 { 1387 struct net_device *netdev = lif->netdev; 1388 unsigned int nfilters; 1389 unsigned int nd_flags; 1390 char buf[128]; 1391 u16 rx_mode; 1392 int i; 1393 #define REMAIN(__x) (sizeof(buf) - (__x)) 1394 1395 mutex_lock(&lif->config_lock); 1396 1397 /* grab the flags once for local use */ 1398 nd_flags = netdev->flags; 1399 1400 rx_mode = IONIC_RX_MODE_F_UNICAST; 1401 rx_mode |= (nd_flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0; 1402 rx_mode |= (nd_flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0; 1403 rx_mode |= (nd_flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0; 1404 rx_mode |= (nd_flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0; 1405 1406 /* sync the mac filters */ 1407 ionic_rx_filter_sync(lif); 1408 1409 /* check for overflow state 1410 * if so, we track that we overflowed and enable NIC PROMISC 1411 * else if the overflow is set and not needed 1412 * we remove our overflow flag and check the netdev flags 1413 * to see if we can disable NIC PROMISC 1414 */ 1415 nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters); 1416 if ((lif->nucast + lif->nmcast) >= nfilters) { 1417 rx_mode |= IONIC_RX_MODE_F_PROMISC; 1418 rx_mode |= IONIC_RX_MODE_F_ALLMULTI; 1419 lif->uc_overflow = true; 1420 lif->mc_overflow = true; 1421 } else if (lif->uc_overflow) { 1422 lif->uc_overflow = false; 1423 lif->mc_overflow = false; 1424 if (!(nd_flags & IFF_PROMISC)) 1425 rx_mode &= ~IONIC_RX_MODE_F_PROMISC; 1426 if (!(nd_flags & IFF_ALLMULTI)) 1427 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI; 1428 } 1429 1430 i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:", 1431 lif->rx_mode, rx_mode); 1432 if (rx_mode & IONIC_RX_MODE_F_UNICAST) 1433 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST"); 1434 if (rx_mode & IONIC_RX_MODE_F_MULTICAST) 1435 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST"); 1436 if (rx_mode & IONIC_RX_MODE_F_BROADCAST) 1437 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST"); 1438 if (rx_mode & IONIC_RX_MODE_F_PROMISC) 1439 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC"); 1440 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI) 1441 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI"); 1442 if (rx_mode & IONIC_RX_MODE_F_RDMA_SNIFFER) 1443 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_RDMA_SNIFFER"); 1444 netdev_dbg(netdev, "lif%d %s\n", lif->index, buf); 1445 1446 if (lif->rx_mode != rx_mode) { 1447 struct ionic_admin_ctx ctx = { 1448 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1449 .cmd.rx_mode_set = { 1450 .opcode = IONIC_CMD_RX_MODE_SET, 1451 .lif_index = cpu_to_le16(lif->index), 1452 }, 1453 }; 1454 int err; 1455 1456 ctx.cmd.rx_mode_set.rx_mode = cpu_to_le16(rx_mode); 1457 err = ionic_adminq_post_wait(lif, &ctx); 1458 if (err) 1459 netdev_warn(netdev, "set rx_mode 0x%04x failed: %d\n", 1460 rx_mode, err); 1461 else 1462 lif->rx_mode = rx_mode; 1463 } 1464 1465 mutex_unlock(&lif->config_lock); 1466 } 1467 1468 static void ionic_ndo_set_rx_mode(struct net_device *netdev) 1469 { 1470 struct ionic_lif *lif = netdev_priv(netdev); 1471 struct ionic_deferred_work *work; 1472 1473 /* Sync the kernel filter list with the driver filter list */ 1474 __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del); 1475 __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del); 1476 1477 /* Shove off the rest of the rxmode work to the work task 1478 * which will include syncing the filters to the firmware. 1479 */ 1480 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1481 if (!work) { 1482 netdev_err(lif->netdev, "rxmode change dropped\n"); 1483 return; 1484 } 1485 work->type = IONIC_DW_TYPE_RX_MODE; 1486 netdev_dbg(lif->netdev, "deferred: rx_mode\n"); 1487 ionic_lif_deferred_enqueue(&lif->deferred, work); 1488 } 1489 1490 static __le64 ionic_netdev_features_to_nic(netdev_features_t features) 1491 { 1492 u64 wanted = 0; 1493 1494 if (features & NETIF_F_HW_VLAN_CTAG_TX) 1495 wanted |= IONIC_ETH_HW_VLAN_TX_TAG; 1496 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1497 wanted |= IONIC_ETH_HW_VLAN_RX_STRIP; 1498 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1499 wanted |= IONIC_ETH_HW_VLAN_RX_FILTER; 1500 if (features & NETIF_F_RXHASH) 1501 wanted |= IONIC_ETH_HW_RX_HASH; 1502 if (features & NETIF_F_RXCSUM) 1503 wanted |= IONIC_ETH_HW_RX_CSUM; 1504 if (features & NETIF_F_SG) 1505 wanted |= IONIC_ETH_HW_TX_SG; 1506 if (features & NETIF_F_HW_CSUM) 1507 wanted |= IONIC_ETH_HW_TX_CSUM; 1508 if (features & NETIF_F_TSO) 1509 wanted |= IONIC_ETH_HW_TSO; 1510 if (features & NETIF_F_TSO6) 1511 wanted |= IONIC_ETH_HW_TSO_IPV6; 1512 if (features & NETIF_F_TSO_ECN) 1513 wanted |= IONIC_ETH_HW_TSO_ECN; 1514 if (features & NETIF_F_GSO_GRE) 1515 wanted |= IONIC_ETH_HW_TSO_GRE; 1516 if (features & NETIF_F_GSO_GRE_CSUM) 1517 wanted |= IONIC_ETH_HW_TSO_GRE_CSUM; 1518 if (features & NETIF_F_GSO_IPXIP4) 1519 wanted |= IONIC_ETH_HW_TSO_IPXIP4; 1520 if (features & NETIF_F_GSO_IPXIP6) 1521 wanted |= IONIC_ETH_HW_TSO_IPXIP6; 1522 if (features & NETIF_F_GSO_UDP_TUNNEL) 1523 wanted |= IONIC_ETH_HW_TSO_UDP; 1524 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) 1525 wanted |= IONIC_ETH_HW_TSO_UDP_CSUM; 1526 1527 return cpu_to_le64(wanted); 1528 } 1529 1530 static int ionic_set_nic_features(struct ionic_lif *lif, 1531 netdev_features_t features) 1532 { 1533 struct device *dev = lif->ionic->dev; 1534 struct ionic_admin_ctx ctx = { 1535 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1536 .cmd.lif_setattr = { 1537 .opcode = IONIC_CMD_LIF_SETATTR, 1538 .index = cpu_to_le16(lif->index), 1539 .attr = IONIC_LIF_ATTR_FEATURES, 1540 }, 1541 }; 1542 u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG | 1543 IONIC_ETH_HW_VLAN_RX_STRIP | 1544 IONIC_ETH_HW_VLAN_RX_FILTER; 1545 u64 old_hw_features; 1546 int err; 1547 1548 ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features); 1549 1550 if (lif->phc) 1551 ctx.cmd.lif_setattr.features |= cpu_to_le64(IONIC_ETH_HW_TIMESTAMP); 1552 1553 err = ionic_adminq_post_wait(lif, &ctx); 1554 if (err) 1555 return err; 1556 1557 old_hw_features = lif->hw_features; 1558 lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features & 1559 ctx.comp.lif_setattr.features); 1560 1561 if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH) 1562 ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1563 1564 if ((vlan_flags & features) && 1565 !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features))) 1566 dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n"); 1567 1568 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1569 dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n"); 1570 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1571 dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n"); 1572 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1573 dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n"); 1574 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1575 dev_dbg(dev, "feature ETH_HW_RX_HASH\n"); 1576 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1577 dev_dbg(dev, "feature ETH_HW_TX_SG\n"); 1578 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1579 dev_dbg(dev, "feature ETH_HW_TX_CSUM\n"); 1580 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1581 dev_dbg(dev, "feature ETH_HW_RX_CSUM\n"); 1582 if (lif->hw_features & IONIC_ETH_HW_TSO) 1583 dev_dbg(dev, "feature ETH_HW_TSO\n"); 1584 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1585 dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n"); 1586 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1587 dev_dbg(dev, "feature ETH_HW_TSO_ECN\n"); 1588 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1589 dev_dbg(dev, "feature ETH_HW_TSO_GRE\n"); 1590 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1591 dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n"); 1592 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1593 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n"); 1594 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1595 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n"); 1596 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1597 dev_dbg(dev, "feature ETH_HW_TSO_UDP\n"); 1598 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1599 dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n"); 1600 if (lif->hw_features & IONIC_ETH_HW_TIMESTAMP) 1601 dev_dbg(dev, "feature ETH_HW_TIMESTAMP\n"); 1602 1603 return 0; 1604 } 1605 1606 static int ionic_init_nic_features(struct ionic_lif *lif) 1607 { 1608 struct net_device *netdev = lif->netdev; 1609 netdev_features_t features; 1610 int err; 1611 1612 /* set up what we expect to support by default */ 1613 features = NETIF_F_HW_VLAN_CTAG_TX | 1614 NETIF_F_HW_VLAN_CTAG_RX | 1615 NETIF_F_HW_VLAN_CTAG_FILTER | 1616 NETIF_F_SG | 1617 NETIF_F_HW_CSUM | 1618 NETIF_F_RXCSUM | 1619 NETIF_F_TSO | 1620 NETIF_F_TSO6 | 1621 NETIF_F_TSO_ECN; 1622 1623 if (lif->nxqs > 1) 1624 features |= NETIF_F_RXHASH; 1625 1626 err = ionic_set_nic_features(lif, features); 1627 if (err) 1628 return err; 1629 1630 /* tell the netdev what we actually can support */ 1631 netdev->features |= NETIF_F_HIGHDMA; 1632 1633 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1634 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 1635 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1636 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 1637 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1638 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1639 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1640 netdev->hw_features |= NETIF_F_RXHASH; 1641 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1642 netdev->hw_features |= NETIF_F_SG; 1643 1644 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1645 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 1646 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1647 netdev->hw_enc_features |= NETIF_F_RXCSUM; 1648 if (lif->hw_features & IONIC_ETH_HW_TSO) 1649 netdev->hw_enc_features |= NETIF_F_TSO; 1650 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1651 netdev->hw_enc_features |= NETIF_F_TSO6; 1652 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1653 netdev->hw_enc_features |= NETIF_F_TSO_ECN; 1654 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1655 netdev->hw_enc_features |= NETIF_F_GSO_GRE; 1656 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1657 netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM; 1658 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1659 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4; 1660 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1661 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6; 1662 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1663 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL; 1664 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1665 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 1666 1667 netdev->hw_features |= netdev->hw_enc_features; 1668 netdev->features |= netdev->hw_features; 1669 netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES; 1670 1671 netdev->priv_flags |= IFF_UNICAST_FLT | 1672 IFF_LIVE_ADDR_CHANGE; 1673 1674 return 0; 1675 } 1676 1677 static int ionic_set_features(struct net_device *netdev, 1678 netdev_features_t features) 1679 { 1680 struct ionic_lif *lif = netdev_priv(netdev); 1681 int err; 1682 1683 netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n", 1684 __func__, (u64)lif->netdev->features, (u64)features); 1685 1686 err = ionic_set_nic_features(lif, features); 1687 1688 return err; 1689 } 1690 1691 static int ionic_set_mac_address(struct net_device *netdev, void *sa) 1692 { 1693 struct sockaddr *addr = sa; 1694 u8 *mac; 1695 int err; 1696 1697 mac = (u8 *)addr->sa_data; 1698 if (ether_addr_equal(netdev->dev_addr, mac)) 1699 return 0; 1700 1701 err = eth_prepare_mac_addr_change(netdev, addr); 1702 if (err) 1703 return err; 1704 1705 if (!is_zero_ether_addr(netdev->dev_addr)) { 1706 netdev_info(netdev, "deleting mac addr %pM\n", 1707 netdev->dev_addr); 1708 ionic_lif_addr_del(netdev_priv(netdev), netdev->dev_addr); 1709 } 1710 1711 eth_commit_mac_addr_change(netdev, addr); 1712 netdev_info(netdev, "updating mac addr %pM\n", mac); 1713 1714 return ionic_lif_addr_add(netdev_priv(netdev), mac); 1715 } 1716 1717 static void ionic_stop_queues_reconfig(struct ionic_lif *lif) 1718 { 1719 /* Stop and clean the queues before reconfiguration */ 1720 netif_device_detach(lif->netdev); 1721 ionic_stop_queues(lif); 1722 ionic_txrx_deinit(lif); 1723 } 1724 1725 static int ionic_start_queues_reconfig(struct ionic_lif *lif) 1726 { 1727 int err; 1728 1729 /* Re-init the queues after reconfiguration */ 1730 1731 /* The only way txrx_init can fail here is if communication 1732 * with FW is suddenly broken. There's not much we can do 1733 * at this point - error messages have already been printed, 1734 * so we can continue on and the user can eventually do a 1735 * DOWN and UP to try to reset and clear the issue. 1736 */ 1737 err = ionic_txrx_init(lif); 1738 ionic_link_status_check_request(lif, CAN_NOT_SLEEP); 1739 netif_device_attach(lif->netdev); 1740 1741 return err; 1742 } 1743 1744 static int ionic_change_mtu(struct net_device *netdev, int new_mtu) 1745 { 1746 struct ionic_lif *lif = netdev_priv(netdev); 1747 struct ionic_admin_ctx ctx = { 1748 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1749 .cmd.lif_setattr = { 1750 .opcode = IONIC_CMD_LIF_SETATTR, 1751 .index = cpu_to_le16(lif->index), 1752 .attr = IONIC_LIF_ATTR_MTU, 1753 .mtu = cpu_to_le32(new_mtu), 1754 }, 1755 }; 1756 int err; 1757 1758 err = ionic_adminq_post_wait(lif, &ctx); 1759 if (err) 1760 return err; 1761 1762 /* if we're not running, nothing more to do */ 1763 if (!netif_running(netdev)) { 1764 netdev->mtu = new_mtu; 1765 return 0; 1766 } 1767 1768 mutex_lock(&lif->queue_lock); 1769 ionic_stop_queues_reconfig(lif); 1770 netdev->mtu = new_mtu; 1771 err = ionic_start_queues_reconfig(lif); 1772 mutex_unlock(&lif->queue_lock); 1773 1774 return err; 1775 } 1776 1777 static void ionic_tx_timeout_work(struct work_struct *ws) 1778 { 1779 struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work); 1780 1781 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 1782 return; 1783 1784 /* if we were stopped before this scheduled job was launched, 1785 * don't bother the queues as they are already stopped. 1786 */ 1787 if (!netif_running(lif->netdev)) 1788 return; 1789 1790 mutex_lock(&lif->queue_lock); 1791 ionic_stop_queues_reconfig(lif); 1792 ionic_start_queues_reconfig(lif); 1793 mutex_unlock(&lif->queue_lock); 1794 } 1795 1796 static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1797 { 1798 struct ionic_lif *lif = netdev_priv(netdev); 1799 1800 netdev_info(lif->netdev, "Tx Timeout triggered - txq %d\n", txqueue); 1801 schedule_work(&lif->tx_timeout_work); 1802 } 1803 1804 static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, 1805 u16 vid) 1806 { 1807 struct ionic_lif *lif = netdev_priv(netdev); 1808 struct ionic_admin_ctx ctx = { 1809 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1810 .cmd.rx_filter_add = { 1811 .opcode = IONIC_CMD_RX_FILTER_ADD, 1812 .lif_index = cpu_to_le16(lif->index), 1813 .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_VLAN), 1814 .vlan.vlan = cpu_to_le16(vid), 1815 }, 1816 }; 1817 int err; 1818 1819 netdev_dbg(netdev, "rx_filter add VLAN %d\n", vid); 1820 err = ionic_adminq_post_wait(lif, &ctx); 1821 if (err) 1822 return err; 1823 1824 spin_lock_bh(&lif->rx_filters.lock); 1825 err = ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx, 1826 IONIC_FILTER_STATE_SYNCED); 1827 spin_unlock_bh(&lif->rx_filters.lock); 1828 1829 return err; 1830 } 1831 1832 static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, 1833 u16 vid) 1834 { 1835 struct ionic_lif *lif = netdev_priv(netdev); 1836 struct ionic_admin_ctx ctx = { 1837 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1838 .cmd.rx_filter_del = { 1839 .opcode = IONIC_CMD_RX_FILTER_DEL, 1840 .lif_index = cpu_to_le16(lif->index), 1841 }, 1842 }; 1843 struct ionic_rx_filter *f; 1844 1845 spin_lock_bh(&lif->rx_filters.lock); 1846 1847 f = ionic_rx_filter_by_vlan(lif, vid); 1848 if (!f) { 1849 spin_unlock_bh(&lif->rx_filters.lock); 1850 return -ENOENT; 1851 } 1852 1853 netdev_dbg(netdev, "rx_filter del VLAN %d (id %d)\n", 1854 vid, f->filter_id); 1855 1856 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id); 1857 ionic_rx_filter_free(lif, f); 1858 spin_unlock_bh(&lif->rx_filters.lock); 1859 1860 return ionic_adminq_post_wait(lif, &ctx); 1861 } 1862 1863 int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types, 1864 const u8 *key, const u32 *indir) 1865 { 1866 struct ionic_admin_ctx ctx = { 1867 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1868 .cmd.lif_setattr = { 1869 .opcode = IONIC_CMD_LIF_SETATTR, 1870 .attr = IONIC_LIF_ATTR_RSS, 1871 .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa), 1872 }, 1873 }; 1874 unsigned int i, tbl_sz; 1875 1876 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) { 1877 lif->rss_types = types; 1878 ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types); 1879 } 1880 1881 if (key) 1882 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE); 1883 1884 if (indir) { 1885 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1886 for (i = 0; i < tbl_sz; i++) 1887 lif->rss_ind_tbl[i] = indir[i]; 1888 } 1889 1890 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key, 1891 IONIC_RSS_HASH_KEY_SIZE); 1892 1893 return ionic_adminq_post_wait(lif, &ctx); 1894 } 1895 1896 static int ionic_lif_rss_init(struct ionic_lif *lif) 1897 { 1898 unsigned int tbl_sz; 1899 unsigned int i; 1900 1901 lif->rss_types = IONIC_RSS_TYPE_IPV4 | 1902 IONIC_RSS_TYPE_IPV4_TCP | 1903 IONIC_RSS_TYPE_IPV4_UDP | 1904 IONIC_RSS_TYPE_IPV6 | 1905 IONIC_RSS_TYPE_IPV6_TCP | 1906 IONIC_RSS_TYPE_IPV6_UDP; 1907 1908 /* Fill indirection table with 'default' values */ 1909 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1910 for (i = 0; i < tbl_sz; i++) 1911 lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs); 1912 1913 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1914 } 1915 1916 static void ionic_lif_rss_deinit(struct ionic_lif *lif) 1917 { 1918 int tbl_sz; 1919 1920 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1921 memset(lif->rss_ind_tbl, 0, tbl_sz); 1922 memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE); 1923 1924 ionic_lif_rss_config(lif, 0x0, NULL, NULL); 1925 } 1926 1927 static void ionic_lif_quiesce(struct ionic_lif *lif) 1928 { 1929 struct ionic_admin_ctx ctx = { 1930 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1931 .cmd.lif_setattr = { 1932 .opcode = IONIC_CMD_LIF_SETATTR, 1933 .index = cpu_to_le16(lif->index), 1934 .attr = IONIC_LIF_ATTR_STATE, 1935 .state = IONIC_LIF_QUIESCE, 1936 }, 1937 }; 1938 int err; 1939 1940 err = ionic_adminq_post_wait(lif, &ctx); 1941 if (err) 1942 netdev_err(lif->netdev, "lif quiesce failed %d\n", err); 1943 } 1944 1945 static void ionic_txrx_disable(struct ionic_lif *lif) 1946 { 1947 unsigned int i; 1948 int err = 0; 1949 1950 if (lif->txqcqs) { 1951 for (i = 0; i < lif->nxqs; i++) 1952 err = ionic_qcq_disable(lif->txqcqs[i], (err != -ETIMEDOUT)); 1953 } 1954 1955 if (lif->hwstamp_txq) 1956 err = ionic_qcq_disable(lif->hwstamp_txq, (err != -ETIMEDOUT)); 1957 1958 if (lif->rxqcqs) { 1959 for (i = 0; i < lif->nxqs; i++) 1960 err = ionic_qcq_disable(lif->rxqcqs[i], (err != -ETIMEDOUT)); 1961 } 1962 1963 if (lif->hwstamp_rxq) 1964 err = ionic_qcq_disable(lif->hwstamp_rxq, (err != -ETIMEDOUT)); 1965 1966 ionic_lif_quiesce(lif); 1967 } 1968 1969 static void ionic_txrx_deinit(struct ionic_lif *lif) 1970 { 1971 unsigned int i; 1972 1973 if (lif->txqcqs) { 1974 for (i = 0; i < lif->nxqs && lif->txqcqs[i]; i++) { 1975 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 1976 ionic_tx_flush(&lif->txqcqs[i]->cq); 1977 ionic_tx_empty(&lif->txqcqs[i]->q); 1978 } 1979 } 1980 1981 if (lif->rxqcqs) { 1982 for (i = 0; i < lif->nxqs && lif->rxqcqs[i]; i++) { 1983 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 1984 ionic_rx_empty(&lif->rxqcqs[i]->q); 1985 } 1986 } 1987 lif->rx_mode = 0; 1988 1989 if (lif->hwstamp_txq) { 1990 ionic_lif_qcq_deinit(lif, lif->hwstamp_txq); 1991 ionic_tx_flush(&lif->hwstamp_txq->cq); 1992 ionic_tx_empty(&lif->hwstamp_txq->q); 1993 } 1994 1995 if (lif->hwstamp_rxq) { 1996 ionic_lif_qcq_deinit(lif, lif->hwstamp_rxq); 1997 ionic_rx_empty(&lif->hwstamp_rxq->q); 1998 } 1999 } 2000 2001 static void ionic_txrx_free(struct ionic_lif *lif) 2002 { 2003 unsigned int i; 2004 2005 if (lif->txqcqs) { 2006 for (i = 0; i < lif->ionic->ntxqs_per_lif && lif->txqcqs[i]; i++) { 2007 ionic_qcq_free(lif, lif->txqcqs[i]); 2008 devm_kfree(lif->ionic->dev, lif->txqcqs[i]); 2009 lif->txqcqs[i] = NULL; 2010 } 2011 } 2012 2013 if (lif->rxqcqs) { 2014 for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) { 2015 ionic_qcq_free(lif, lif->rxqcqs[i]); 2016 devm_kfree(lif->ionic->dev, lif->rxqcqs[i]); 2017 lif->rxqcqs[i] = NULL; 2018 } 2019 } 2020 2021 if (lif->hwstamp_txq) { 2022 ionic_qcq_free(lif, lif->hwstamp_txq); 2023 devm_kfree(lif->ionic->dev, lif->hwstamp_txq); 2024 lif->hwstamp_txq = NULL; 2025 } 2026 2027 if (lif->hwstamp_rxq) { 2028 ionic_qcq_free(lif, lif->hwstamp_rxq); 2029 devm_kfree(lif->ionic->dev, lif->hwstamp_rxq); 2030 lif->hwstamp_rxq = NULL; 2031 } 2032 } 2033 2034 static int ionic_txrx_alloc(struct ionic_lif *lif) 2035 { 2036 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz; 2037 unsigned int flags, i; 2038 int err = 0; 2039 2040 num_desc = lif->ntxq_descs; 2041 desc_sz = sizeof(struct ionic_txq_desc); 2042 comp_sz = sizeof(struct ionic_txq_comp); 2043 2044 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 2045 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 2046 sizeof(struct ionic_txq_sg_desc_v1)) 2047 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 2048 else 2049 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 2050 2051 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 2052 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 2053 flags |= IONIC_QCQ_F_INTR; 2054 for (i = 0; i < lif->nxqs; i++) { 2055 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 2056 num_desc, desc_sz, comp_sz, sg_desc_sz, 2057 lif->kern_pid, &lif->txqcqs[i]); 2058 if (err) 2059 goto err_out; 2060 2061 if (flags & IONIC_QCQ_F_INTR) { 2062 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2063 lif->txqcqs[i]->intr.index, 2064 lif->tx_coalesce_hw); 2065 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 2066 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 2067 } 2068 2069 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 2070 } 2071 2072 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG | IONIC_QCQ_F_INTR; 2073 2074 num_desc = lif->nrxq_descs; 2075 desc_sz = sizeof(struct ionic_rxq_desc); 2076 comp_sz = sizeof(struct ionic_rxq_comp); 2077 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 2078 2079 if (lif->rxq_features & IONIC_Q_F_2X_CQ_DESC) 2080 comp_sz *= 2; 2081 2082 for (i = 0; i < lif->nxqs; i++) { 2083 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 2084 num_desc, desc_sz, comp_sz, sg_desc_sz, 2085 lif->kern_pid, &lif->rxqcqs[i]); 2086 if (err) 2087 goto err_out; 2088 2089 lif->rxqcqs[i]->q.features = lif->rxq_features; 2090 2091 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2092 lif->rxqcqs[i]->intr.index, 2093 lif->rx_coalesce_hw); 2094 if (test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state)) 2095 lif->rxqcqs[i]->intr.dim_coal_hw = lif->rx_coalesce_hw; 2096 2097 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 2098 ionic_link_qcq_interrupts(lif->rxqcqs[i], 2099 lif->txqcqs[i]); 2100 2101 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 2102 } 2103 2104 return 0; 2105 2106 err_out: 2107 ionic_txrx_free(lif); 2108 2109 return err; 2110 } 2111 2112 static int ionic_txrx_init(struct ionic_lif *lif) 2113 { 2114 unsigned int i; 2115 int err; 2116 2117 for (i = 0; i < lif->nxqs; i++) { 2118 err = ionic_lif_txq_init(lif, lif->txqcqs[i]); 2119 if (err) 2120 goto err_out; 2121 2122 err = ionic_lif_rxq_init(lif, lif->rxqcqs[i]); 2123 if (err) { 2124 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 2125 goto err_out; 2126 } 2127 } 2128 2129 if (lif->netdev->features & NETIF_F_RXHASH) 2130 ionic_lif_rss_init(lif); 2131 2132 ionic_lif_rx_mode(lif); 2133 2134 return 0; 2135 2136 err_out: 2137 while (i--) { 2138 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 2139 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 2140 } 2141 2142 return err; 2143 } 2144 2145 static int ionic_txrx_enable(struct ionic_lif *lif) 2146 { 2147 int derr = 0; 2148 int i, err; 2149 2150 for (i = 0; i < lif->nxqs; i++) { 2151 if (!(lif->rxqcqs[i] && lif->txqcqs[i])) { 2152 dev_err(lif->ionic->dev, "%s: bad qcq %d\n", __func__, i); 2153 err = -ENXIO; 2154 goto err_out; 2155 } 2156 2157 ionic_rx_fill(&lif->rxqcqs[i]->q); 2158 err = ionic_qcq_enable(lif->rxqcqs[i]); 2159 if (err) 2160 goto err_out; 2161 2162 err = ionic_qcq_enable(lif->txqcqs[i]); 2163 if (err) { 2164 derr = ionic_qcq_disable(lif->rxqcqs[i], (err != -ETIMEDOUT)); 2165 goto err_out; 2166 } 2167 } 2168 2169 if (lif->hwstamp_rxq) { 2170 ionic_rx_fill(&lif->hwstamp_rxq->q); 2171 err = ionic_qcq_enable(lif->hwstamp_rxq); 2172 if (err) 2173 goto err_out_hwstamp_rx; 2174 } 2175 2176 if (lif->hwstamp_txq) { 2177 err = ionic_qcq_enable(lif->hwstamp_txq); 2178 if (err) 2179 goto err_out_hwstamp_tx; 2180 } 2181 2182 return 0; 2183 2184 err_out_hwstamp_tx: 2185 if (lif->hwstamp_rxq) 2186 derr = ionic_qcq_disable(lif->hwstamp_rxq, (derr != -ETIMEDOUT)); 2187 err_out_hwstamp_rx: 2188 i = lif->nxqs; 2189 err_out: 2190 while (i--) { 2191 derr = ionic_qcq_disable(lif->txqcqs[i], (derr != -ETIMEDOUT)); 2192 derr = ionic_qcq_disable(lif->rxqcqs[i], (derr != -ETIMEDOUT)); 2193 } 2194 2195 return err; 2196 } 2197 2198 static int ionic_start_queues(struct ionic_lif *lif) 2199 { 2200 int err; 2201 2202 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) 2203 return -EIO; 2204 2205 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2206 return -EBUSY; 2207 2208 if (test_and_set_bit(IONIC_LIF_F_UP, lif->state)) 2209 return 0; 2210 2211 err = ionic_txrx_enable(lif); 2212 if (err) { 2213 clear_bit(IONIC_LIF_F_UP, lif->state); 2214 return err; 2215 } 2216 netif_tx_wake_all_queues(lif->netdev); 2217 2218 return 0; 2219 } 2220 2221 static int ionic_open(struct net_device *netdev) 2222 { 2223 struct ionic_lif *lif = netdev_priv(netdev); 2224 int err; 2225 2226 /* If recovering from a broken state, clear the bit and we'll try again */ 2227 if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state)) 2228 netdev_info(netdev, "clearing broken state\n"); 2229 2230 mutex_lock(&lif->queue_lock); 2231 2232 err = ionic_txrx_alloc(lif); 2233 if (err) 2234 goto err_unlock; 2235 2236 err = ionic_txrx_init(lif); 2237 if (err) 2238 goto err_txrx_free; 2239 2240 err = netif_set_real_num_tx_queues(netdev, lif->nxqs); 2241 if (err) 2242 goto err_txrx_deinit; 2243 2244 err = netif_set_real_num_rx_queues(netdev, lif->nxqs); 2245 if (err) 2246 goto err_txrx_deinit; 2247 2248 /* don't start the queues until we have link */ 2249 if (netif_carrier_ok(netdev)) { 2250 err = ionic_start_queues(lif); 2251 if (err) 2252 goto err_txrx_deinit; 2253 } 2254 2255 /* If hardware timestamping is enabled, but the queues were freed by 2256 * ionic_stop, those need to be reallocated and initialized, too. 2257 */ 2258 ionic_lif_hwstamp_recreate_queues(lif); 2259 2260 mutex_unlock(&lif->queue_lock); 2261 2262 return 0; 2263 2264 err_txrx_deinit: 2265 ionic_txrx_deinit(lif); 2266 err_txrx_free: 2267 ionic_txrx_free(lif); 2268 err_unlock: 2269 mutex_unlock(&lif->queue_lock); 2270 return err; 2271 } 2272 2273 static void ionic_stop_queues(struct ionic_lif *lif) 2274 { 2275 if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state)) 2276 return; 2277 2278 netif_tx_disable(lif->netdev); 2279 ionic_txrx_disable(lif); 2280 } 2281 2282 static int ionic_stop(struct net_device *netdev) 2283 { 2284 struct ionic_lif *lif = netdev_priv(netdev); 2285 2286 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2287 return 0; 2288 2289 mutex_lock(&lif->queue_lock); 2290 ionic_stop_queues(lif); 2291 ionic_txrx_deinit(lif); 2292 ionic_txrx_free(lif); 2293 mutex_unlock(&lif->queue_lock); 2294 2295 return 0; 2296 } 2297 2298 static int ionic_eth_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 2299 { 2300 struct ionic_lif *lif = netdev_priv(netdev); 2301 2302 switch (cmd) { 2303 case SIOCSHWTSTAMP: 2304 return ionic_lif_hwstamp_set(lif, ifr); 2305 case SIOCGHWTSTAMP: 2306 return ionic_lif_hwstamp_get(lif, ifr); 2307 default: 2308 return -EOPNOTSUPP; 2309 } 2310 } 2311 2312 static int ionic_get_vf_config(struct net_device *netdev, 2313 int vf, struct ifla_vf_info *ivf) 2314 { 2315 struct ionic_lif *lif = netdev_priv(netdev); 2316 struct ionic *ionic = lif->ionic; 2317 int ret = 0; 2318 2319 if (!netif_device_present(netdev)) 2320 return -EBUSY; 2321 2322 down_read(&ionic->vf_op_lock); 2323 2324 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2325 ret = -EINVAL; 2326 } else { 2327 ivf->vf = vf; 2328 ivf->vlan = le16_to_cpu(ionic->vfs[vf].vlanid); 2329 ivf->qos = 0; 2330 ivf->spoofchk = ionic->vfs[vf].spoofchk; 2331 ivf->linkstate = ionic->vfs[vf].linkstate; 2332 ivf->max_tx_rate = le32_to_cpu(ionic->vfs[vf].maxrate); 2333 ivf->trusted = ionic->vfs[vf].trusted; 2334 ether_addr_copy(ivf->mac, ionic->vfs[vf].macaddr); 2335 } 2336 2337 up_read(&ionic->vf_op_lock); 2338 return ret; 2339 } 2340 2341 static int ionic_get_vf_stats(struct net_device *netdev, int vf, 2342 struct ifla_vf_stats *vf_stats) 2343 { 2344 struct ionic_lif *lif = netdev_priv(netdev); 2345 struct ionic *ionic = lif->ionic; 2346 struct ionic_lif_stats *vs; 2347 int ret = 0; 2348 2349 if (!netif_device_present(netdev)) 2350 return -EBUSY; 2351 2352 down_read(&ionic->vf_op_lock); 2353 2354 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2355 ret = -EINVAL; 2356 } else { 2357 memset(vf_stats, 0, sizeof(*vf_stats)); 2358 vs = &ionic->vfs[vf].stats; 2359 2360 vf_stats->rx_packets = le64_to_cpu(vs->rx_ucast_packets); 2361 vf_stats->tx_packets = le64_to_cpu(vs->tx_ucast_packets); 2362 vf_stats->rx_bytes = le64_to_cpu(vs->rx_ucast_bytes); 2363 vf_stats->tx_bytes = le64_to_cpu(vs->tx_ucast_bytes); 2364 vf_stats->broadcast = le64_to_cpu(vs->rx_bcast_packets); 2365 vf_stats->multicast = le64_to_cpu(vs->rx_mcast_packets); 2366 vf_stats->rx_dropped = le64_to_cpu(vs->rx_ucast_drop_packets) + 2367 le64_to_cpu(vs->rx_mcast_drop_packets) + 2368 le64_to_cpu(vs->rx_bcast_drop_packets); 2369 vf_stats->tx_dropped = le64_to_cpu(vs->tx_ucast_drop_packets) + 2370 le64_to_cpu(vs->tx_mcast_drop_packets) + 2371 le64_to_cpu(vs->tx_bcast_drop_packets); 2372 } 2373 2374 up_read(&ionic->vf_op_lock); 2375 return ret; 2376 } 2377 2378 static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2379 { 2380 struct ionic_lif *lif = netdev_priv(netdev); 2381 struct ionic *ionic = lif->ionic; 2382 int ret; 2383 2384 if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac))) 2385 return -EINVAL; 2386 2387 if (!netif_device_present(netdev)) 2388 return -EBUSY; 2389 2390 down_write(&ionic->vf_op_lock); 2391 2392 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2393 ret = -EINVAL; 2394 } else { 2395 ret = ionic_set_vf_config(ionic, vf, IONIC_VF_ATTR_MAC, mac); 2396 if (!ret) 2397 ether_addr_copy(ionic->vfs[vf].macaddr, mac); 2398 } 2399 2400 up_write(&ionic->vf_op_lock); 2401 return ret; 2402 } 2403 2404 static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 2405 u8 qos, __be16 proto) 2406 { 2407 struct ionic_lif *lif = netdev_priv(netdev); 2408 struct ionic *ionic = lif->ionic; 2409 int ret; 2410 2411 /* until someday when we support qos */ 2412 if (qos) 2413 return -EINVAL; 2414 2415 if (vlan > 4095) 2416 return -EINVAL; 2417 2418 if (proto != htons(ETH_P_8021Q)) 2419 return -EPROTONOSUPPORT; 2420 2421 if (!netif_device_present(netdev)) 2422 return -EBUSY; 2423 2424 down_write(&ionic->vf_op_lock); 2425 2426 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2427 ret = -EINVAL; 2428 } else { 2429 ret = ionic_set_vf_config(ionic, vf, 2430 IONIC_VF_ATTR_VLAN, (u8 *)&vlan); 2431 if (!ret) 2432 ionic->vfs[vf].vlanid = cpu_to_le16(vlan); 2433 } 2434 2435 up_write(&ionic->vf_op_lock); 2436 return ret; 2437 } 2438 2439 static int ionic_set_vf_rate(struct net_device *netdev, int vf, 2440 int tx_min, int tx_max) 2441 { 2442 struct ionic_lif *lif = netdev_priv(netdev); 2443 struct ionic *ionic = lif->ionic; 2444 int ret; 2445 2446 /* setting the min just seems silly */ 2447 if (tx_min) 2448 return -EINVAL; 2449 2450 if (!netif_device_present(netdev)) 2451 return -EBUSY; 2452 2453 down_write(&ionic->vf_op_lock); 2454 2455 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2456 ret = -EINVAL; 2457 } else { 2458 ret = ionic_set_vf_config(ionic, vf, 2459 IONIC_VF_ATTR_RATE, (u8 *)&tx_max); 2460 if (!ret) 2461 lif->ionic->vfs[vf].maxrate = cpu_to_le32(tx_max); 2462 } 2463 2464 up_write(&ionic->vf_op_lock); 2465 return ret; 2466 } 2467 2468 static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set) 2469 { 2470 struct ionic_lif *lif = netdev_priv(netdev); 2471 struct ionic *ionic = lif->ionic; 2472 u8 data = set; /* convert to u8 for config */ 2473 int ret; 2474 2475 if (!netif_device_present(netdev)) 2476 return -EBUSY; 2477 2478 down_write(&ionic->vf_op_lock); 2479 2480 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2481 ret = -EINVAL; 2482 } else { 2483 ret = ionic_set_vf_config(ionic, vf, 2484 IONIC_VF_ATTR_SPOOFCHK, &data); 2485 if (!ret) 2486 ionic->vfs[vf].spoofchk = data; 2487 } 2488 2489 up_write(&ionic->vf_op_lock); 2490 return ret; 2491 } 2492 2493 static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set) 2494 { 2495 struct ionic_lif *lif = netdev_priv(netdev); 2496 struct ionic *ionic = lif->ionic; 2497 u8 data = set; /* convert to u8 for config */ 2498 int ret; 2499 2500 if (!netif_device_present(netdev)) 2501 return -EBUSY; 2502 2503 down_write(&ionic->vf_op_lock); 2504 2505 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2506 ret = -EINVAL; 2507 } else { 2508 ret = ionic_set_vf_config(ionic, vf, 2509 IONIC_VF_ATTR_TRUST, &data); 2510 if (!ret) 2511 ionic->vfs[vf].trusted = data; 2512 } 2513 2514 up_write(&ionic->vf_op_lock); 2515 return ret; 2516 } 2517 2518 static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set) 2519 { 2520 struct ionic_lif *lif = netdev_priv(netdev); 2521 struct ionic *ionic = lif->ionic; 2522 u8 data; 2523 int ret; 2524 2525 switch (set) { 2526 case IFLA_VF_LINK_STATE_ENABLE: 2527 data = IONIC_VF_LINK_STATUS_UP; 2528 break; 2529 case IFLA_VF_LINK_STATE_DISABLE: 2530 data = IONIC_VF_LINK_STATUS_DOWN; 2531 break; 2532 case IFLA_VF_LINK_STATE_AUTO: 2533 data = IONIC_VF_LINK_STATUS_AUTO; 2534 break; 2535 default: 2536 return -EINVAL; 2537 } 2538 2539 if (!netif_device_present(netdev)) 2540 return -EBUSY; 2541 2542 down_write(&ionic->vf_op_lock); 2543 2544 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2545 ret = -EINVAL; 2546 } else { 2547 ret = ionic_set_vf_config(ionic, vf, 2548 IONIC_VF_ATTR_LINKSTATE, &data); 2549 if (!ret) 2550 ionic->vfs[vf].linkstate = set; 2551 } 2552 2553 up_write(&ionic->vf_op_lock); 2554 return ret; 2555 } 2556 2557 static const struct net_device_ops ionic_netdev_ops = { 2558 .ndo_open = ionic_open, 2559 .ndo_stop = ionic_stop, 2560 .ndo_eth_ioctl = ionic_eth_ioctl, 2561 .ndo_start_xmit = ionic_start_xmit, 2562 .ndo_get_stats64 = ionic_get_stats64, 2563 .ndo_set_rx_mode = ionic_ndo_set_rx_mode, 2564 .ndo_set_features = ionic_set_features, 2565 .ndo_set_mac_address = ionic_set_mac_address, 2566 .ndo_validate_addr = eth_validate_addr, 2567 .ndo_tx_timeout = ionic_tx_timeout, 2568 .ndo_change_mtu = ionic_change_mtu, 2569 .ndo_vlan_rx_add_vid = ionic_vlan_rx_add_vid, 2570 .ndo_vlan_rx_kill_vid = ionic_vlan_rx_kill_vid, 2571 .ndo_set_vf_vlan = ionic_set_vf_vlan, 2572 .ndo_set_vf_trust = ionic_set_vf_trust, 2573 .ndo_set_vf_mac = ionic_set_vf_mac, 2574 .ndo_set_vf_rate = ionic_set_vf_rate, 2575 .ndo_set_vf_spoofchk = ionic_set_vf_spoofchk, 2576 .ndo_get_vf_config = ionic_get_vf_config, 2577 .ndo_set_vf_link_state = ionic_set_vf_link_state, 2578 .ndo_get_vf_stats = ionic_get_vf_stats, 2579 }; 2580 2581 static void ionic_swap_queues(struct ionic_qcq *a, struct ionic_qcq *b) 2582 { 2583 /* only swapping the queues, not the napi, flags, or other stuff */ 2584 swap(a->q.features, b->q.features); 2585 swap(a->q.num_descs, b->q.num_descs); 2586 swap(a->q.desc_size, b->q.desc_size); 2587 swap(a->q.base, b->q.base); 2588 swap(a->q.base_pa, b->q.base_pa); 2589 swap(a->q.info, b->q.info); 2590 swap(a->q_base, b->q_base); 2591 swap(a->q_base_pa, b->q_base_pa); 2592 swap(a->q_size, b->q_size); 2593 2594 swap(a->q.sg_desc_size, b->q.sg_desc_size); 2595 swap(a->q.sg_base, b->q.sg_base); 2596 swap(a->q.sg_base_pa, b->q.sg_base_pa); 2597 swap(a->sg_base, b->sg_base); 2598 swap(a->sg_base_pa, b->sg_base_pa); 2599 swap(a->sg_size, b->sg_size); 2600 2601 swap(a->cq.num_descs, b->cq.num_descs); 2602 swap(a->cq.desc_size, b->cq.desc_size); 2603 swap(a->cq.base, b->cq.base); 2604 swap(a->cq.base_pa, b->cq.base_pa); 2605 swap(a->cq.info, b->cq.info); 2606 swap(a->cq_base, b->cq_base); 2607 swap(a->cq_base_pa, b->cq_base_pa); 2608 swap(a->cq_size, b->cq_size); 2609 2610 ionic_debugfs_del_qcq(a); 2611 ionic_debugfs_add_qcq(a->q.lif, a); 2612 } 2613 2614 int ionic_reconfigure_queues(struct ionic_lif *lif, 2615 struct ionic_queue_params *qparam) 2616 { 2617 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz; 2618 struct ionic_qcq **tx_qcqs = NULL; 2619 struct ionic_qcq **rx_qcqs = NULL; 2620 unsigned int flags, i; 2621 int err = 0; 2622 2623 /* allocate temporary qcq arrays to hold new queue structs */ 2624 if (qparam->nxqs != lif->nxqs || qparam->ntxq_descs != lif->ntxq_descs) { 2625 tx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->ntxqs_per_lif, 2626 sizeof(struct ionic_qcq *), GFP_KERNEL); 2627 if (!tx_qcqs) { 2628 err = -ENOMEM; 2629 goto err_out; 2630 } 2631 } 2632 if (qparam->nxqs != lif->nxqs || 2633 qparam->nrxq_descs != lif->nrxq_descs || 2634 qparam->rxq_features != lif->rxq_features) { 2635 rx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->nrxqs_per_lif, 2636 sizeof(struct ionic_qcq *), GFP_KERNEL); 2637 if (!rx_qcqs) { 2638 err = -ENOMEM; 2639 goto err_out; 2640 } 2641 } 2642 2643 /* allocate new desc_info and rings, but leave the interrupt setup 2644 * until later so as to not mess with the still-running queues 2645 */ 2646 if (tx_qcqs) { 2647 num_desc = qparam->ntxq_descs; 2648 desc_sz = sizeof(struct ionic_txq_desc); 2649 comp_sz = sizeof(struct ionic_txq_comp); 2650 2651 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 2652 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 2653 sizeof(struct ionic_txq_sg_desc_v1)) 2654 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 2655 else 2656 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 2657 2658 for (i = 0; i < qparam->nxqs; i++) { 2659 flags = lif->txqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2660 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 2661 num_desc, desc_sz, comp_sz, sg_desc_sz, 2662 lif->kern_pid, &tx_qcqs[i]); 2663 if (err) 2664 goto err_out; 2665 } 2666 } 2667 2668 if (rx_qcqs) { 2669 num_desc = qparam->nrxq_descs; 2670 desc_sz = sizeof(struct ionic_rxq_desc); 2671 comp_sz = sizeof(struct ionic_rxq_comp); 2672 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 2673 2674 if (qparam->rxq_features & IONIC_Q_F_2X_CQ_DESC) 2675 comp_sz *= 2; 2676 2677 for (i = 0; i < qparam->nxqs; i++) { 2678 flags = lif->rxqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2679 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 2680 num_desc, desc_sz, comp_sz, sg_desc_sz, 2681 lif->kern_pid, &rx_qcqs[i]); 2682 if (err) 2683 goto err_out; 2684 2685 rx_qcqs[i]->q.features = qparam->rxq_features; 2686 } 2687 } 2688 2689 /* stop and clean the queues */ 2690 ionic_stop_queues_reconfig(lif); 2691 2692 if (qparam->nxqs != lif->nxqs) { 2693 err = netif_set_real_num_tx_queues(lif->netdev, qparam->nxqs); 2694 if (err) 2695 goto err_out_reinit_unlock; 2696 err = netif_set_real_num_rx_queues(lif->netdev, qparam->nxqs); 2697 if (err) { 2698 netif_set_real_num_tx_queues(lif->netdev, lif->nxqs); 2699 goto err_out_reinit_unlock; 2700 } 2701 } 2702 2703 /* swap new desc_info and rings, keeping existing interrupt config */ 2704 if (tx_qcqs) { 2705 lif->ntxq_descs = qparam->ntxq_descs; 2706 for (i = 0; i < qparam->nxqs; i++) 2707 ionic_swap_queues(lif->txqcqs[i], tx_qcqs[i]); 2708 } 2709 2710 if (rx_qcqs) { 2711 lif->nrxq_descs = qparam->nrxq_descs; 2712 for (i = 0; i < qparam->nxqs; i++) 2713 ionic_swap_queues(lif->rxqcqs[i], rx_qcqs[i]); 2714 } 2715 2716 /* if we need to change the interrupt layout, this is the time */ 2717 if (qparam->intr_split != test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) || 2718 qparam->nxqs != lif->nxqs) { 2719 if (qparam->intr_split) { 2720 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 2721 } else { 2722 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 2723 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 2724 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 2725 } 2726 2727 /* clear existing interrupt assignments */ 2728 for (i = 0; i < lif->ionic->ntxqs_per_lif; i++) { 2729 ionic_qcq_intr_free(lif, lif->txqcqs[i]); 2730 ionic_qcq_intr_free(lif, lif->rxqcqs[i]); 2731 } 2732 2733 /* re-assign the interrupts */ 2734 for (i = 0; i < qparam->nxqs; i++) { 2735 lif->rxqcqs[i]->flags |= IONIC_QCQ_F_INTR; 2736 err = ionic_alloc_qcq_interrupt(lif, lif->rxqcqs[i]); 2737 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2738 lif->rxqcqs[i]->intr.index, 2739 lif->rx_coalesce_hw); 2740 2741 if (qparam->intr_split) { 2742 lif->txqcqs[i]->flags |= IONIC_QCQ_F_INTR; 2743 err = ionic_alloc_qcq_interrupt(lif, lif->txqcqs[i]); 2744 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2745 lif->txqcqs[i]->intr.index, 2746 lif->tx_coalesce_hw); 2747 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 2748 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 2749 } else { 2750 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2751 ionic_link_qcq_interrupts(lif->rxqcqs[i], lif->txqcqs[i]); 2752 } 2753 } 2754 } 2755 2756 /* now we can rework the debugfs mappings */ 2757 if (tx_qcqs) { 2758 for (i = 0; i < qparam->nxqs; i++) { 2759 ionic_debugfs_del_qcq(lif->txqcqs[i]); 2760 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 2761 } 2762 } 2763 2764 if (rx_qcqs) { 2765 for (i = 0; i < qparam->nxqs; i++) { 2766 ionic_debugfs_del_qcq(lif->rxqcqs[i]); 2767 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 2768 } 2769 } 2770 2771 swap(lif->nxqs, qparam->nxqs); 2772 swap(lif->rxq_features, qparam->rxq_features); 2773 2774 err_out_reinit_unlock: 2775 /* re-init the queues, but don't lose an error code */ 2776 if (err) 2777 ionic_start_queues_reconfig(lif); 2778 else 2779 err = ionic_start_queues_reconfig(lif); 2780 2781 err_out: 2782 /* free old allocs without cleaning intr */ 2783 for (i = 0; i < qparam->nxqs; i++) { 2784 if (tx_qcqs && tx_qcqs[i]) { 2785 tx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2786 ionic_qcq_free(lif, tx_qcqs[i]); 2787 devm_kfree(lif->ionic->dev, tx_qcqs[i]); 2788 tx_qcqs[i] = NULL; 2789 } 2790 if (rx_qcqs && rx_qcqs[i]) { 2791 rx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2792 ionic_qcq_free(lif, rx_qcqs[i]); 2793 devm_kfree(lif->ionic->dev, rx_qcqs[i]); 2794 rx_qcqs[i] = NULL; 2795 } 2796 } 2797 2798 /* free q array */ 2799 if (rx_qcqs) { 2800 devm_kfree(lif->ionic->dev, rx_qcqs); 2801 rx_qcqs = NULL; 2802 } 2803 if (tx_qcqs) { 2804 devm_kfree(lif->ionic->dev, tx_qcqs); 2805 tx_qcqs = NULL; 2806 } 2807 2808 /* clean the unused dma and info allocations when new set is smaller 2809 * than the full array, but leave the qcq shells in place 2810 */ 2811 for (i = lif->nxqs; i < lif->ionic->ntxqs_per_lif; i++) { 2812 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2813 ionic_qcq_free(lif, lif->txqcqs[i]); 2814 2815 lif->rxqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2816 ionic_qcq_free(lif, lif->rxqcqs[i]); 2817 } 2818 2819 if (err) 2820 netdev_info(lif->netdev, "%s: failed %d\n", __func__, err); 2821 2822 return err; 2823 } 2824 2825 int ionic_lif_alloc(struct ionic *ionic) 2826 { 2827 struct device *dev = ionic->dev; 2828 union ionic_lif_identity *lid; 2829 struct net_device *netdev; 2830 struct ionic_lif *lif; 2831 int tbl_sz; 2832 int err; 2833 2834 lid = kzalloc(sizeof(*lid), GFP_KERNEL); 2835 if (!lid) 2836 return -ENOMEM; 2837 2838 netdev = alloc_etherdev_mqs(sizeof(*lif), 2839 ionic->ntxqs_per_lif, ionic->ntxqs_per_lif); 2840 if (!netdev) { 2841 dev_err(dev, "Cannot allocate netdev, aborting\n"); 2842 err = -ENOMEM; 2843 goto err_out_free_lid; 2844 } 2845 2846 SET_NETDEV_DEV(netdev, dev); 2847 2848 lif = netdev_priv(netdev); 2849 lif->netdev = netdev; 2850 ionic->lif = lif; 2851 netdev->netdev_ops = &ionic_netdev_ops; 2852 ionic_ethtool_set_ops(netdev); 2853 2854 netdev->watchdog_timeo = 2 * HZ; 2855 netif_carrier_off(netdev); 2856 2857 lif->identity = lid; 2858 lif->lif_type = IONIC_LIF_TYPE_CLASSIC; 2859 err = ionic_lif_identify(ionic, lif->lif_type, lif->identity); 2860 if (err) { 2861 dev_err(ionic->dev, "Cannot identify type %d: %d\n", 2862 lif->lif_type, err); 2863 goto err_out_free_netdev; 2864 } 2865 lif->netdev->min_mtu = max_t(unsigned int, ETH_MIN_MTU, 2866 le32_to_cpu(lif->identity->eth.min_frame_size)); 2867 lif->netdev->max_mtu = 2868 le32_to_cpu(lif->identity->eth.max_frame_size) - ETH_HLEN - VLAN_HLEN; 2869 2870 lif->neqs = ionic->neqs_per_lif; 2871 lif->nxqs = ionic->ntxqs_per_lif; 2872 2873 lif->ionic = ionic; 2874 lif->index = 0; 2875 2876 if (is_kdump_kernel()) { 2877 lif->ntxq_descs = IONIC_MIN_TXRX_DESC; 2878 lif->nrxq_descs = IONIC_MIN_TXRX_DESC; 2879 } else { 2880 lif->ntxq_descs = IONIC_DEF_TXRX_DESC; 2881 lif->nrxq_descs = IONIC_DEF_TXRX_DESC; 2882 } 2883 2884 /* Convert the default coalesce value to actual hw resolution */ 2885 lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT; 2886 lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic, 2887 lif->rx_coalesce_usecs); 2888 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 2889 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 2890 set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 2891 set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 2892 2893 snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index); 2894 2895 spin_lock_init(&lif->adminq_lock); 2896 2897 spin_lock_init(&lif->deferred.lock); 2898 INIT_LIST_HEAD(&lif->deferred.list); 2899 INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work); 2900 2901 /* allocate lif info */ 2902 lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE); 2903 lif->info = dma_alloc_coherent(dev, lif->info_sz, 2904 &lif->info_pa, GFP_KERNEL); 2905 if (!lif->info) { 2906 dev_err(dev, "Failed to allocate lif info, aborting\n"); 2907 err = -ENOMEM; 2908 goto err_out_free_netdev; 2909 } 2910 2911 ionic_debugfs_add_lif(lif); 2912 2913 /* allocate control queues and txrx queue arrays */ 2914 ionic_lif_queue_identify(lif); 2915 err = ionic_qcqs_alloc(lif); 2916 if (err) 2917 goto err_out_free_lif_info; 2918 2919 /* allocate rss indirection table */ 2920 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 2921 lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz; 2922 lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz, 2923 &lif->rss_ind_tbl_pa, 2924 GFP_KERNEL); 2925 2926 if (!lif->rss_ind_tbl) { 2927 err = -ENOMEM; 2928 dev_err(dev, "Failed to allocate rss indirection table, aborting\n"); 2929 goto err_out_free_qcqs; 2930 } 2931 netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE); 2932 2933 ionic_lif_alloc_phc(lif); 2934 2935 return 0; 2936 2937 err_out_free_qcqs: 2938 ionic_qcqs_free(lif); 2939 err_out_free_lif_info: 2940 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 2941 lif->info = NULL; 2942 lif->info_pa = 0; 2943 err_out_free_netdev: 2944 free_netdev(lif->netdev); 2945 lif = NULL; 2946 err_out_free_lid: 2947 kfree(lid); 2948 2949 return err; 2950 } 2951 2952 static void ionic_lif_reset(struct ionic_lif *lif) 2953 { 2954 struct ionic_dev *idev = &lif->ionic->idev; 2955 2956 mutex_lock(&lif->ionic->dev_cmd_lock); 2957 ionic_dev_cmd_lif_reset(idev, lif->index); 2958 ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2959 mutex_unlock(&lif->ionic->dev_cmd_lock); 2960 } 2961 2962 static void ionic_lif_handle_fw_down(struct ionic_lif *lif) 2963 { 2964 struct ionic *ionic = lif->ionic; 2965 2966 if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2967 return; 2968 2969 dev_info(ionic->dev, "FW Down: Stopping LIFs\n"); 2970 2971 netif_device_detach(lif->netdev); 2972 2973 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 2974 dev_info(ionic->dev, "Surprise FW stop, stopping queues\n"); 2975 mutex_lock(&lif->queue_lock); 2976 ionic_stop_queues(lif); 2977 mutex_unlock(&lif->queue_lock); 2978 } 2979 2980 if (netif_running(lif->netdev)) { 2981 ionic_txrx_deinit(lif); 2982 ionic_txrx_free(lif); 2983 } 2984 ionic_lif_deinit(lif); 2985 ionic_reset(ionic); 2986 ionic_qcqs_free(lif); 2987 2988 dev_info(ionic->dev, "FW Down: LIFs stopped\n"); 2989 } 2990 2991 static void ionic_lif_handle_fw_up(struct ionic_lif *lif) 2992 { 2993 struct ionic *ionic = lif->ionic; 2994 int err; 2995 2996 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2997 return; 2998 2999 dev_info(ionic->dev, "FW Up: restarting LIFs\n"); 3000 3001 ionic_init_devinfo(ionic); 3002 err = ionic_identify(ionic); 3003 if (err) 3004 goto err_out; 3005 err = ionic_port_identify(ionic); 3006 if (err) 3007 goto err_out; 3008 err = ionic_port_init(ionic); 3009 if (err) 3010 goto err_out; 3011 err = ionic_qcqs_alloc(lif); 3012 if (err) 3013 goto err_out; 3014 3015 err = ionic_lif_init(lif); 3016 if (err) 3017 goto err_qcqs_free; 3018 3019 if (lif->registered) 3020 ionic_lif_set_netdev_info(lif); 3021 3022 ionic_rx_filter_replay(lif); 3023 3024 if (netif_running(lif->netdev)) { 3025 err = ionic_txrx_alloc(lif); 3026 if (err) 3027 goto err_lifs_deinit; 3028 3029 err = ionic_txrx_init(lif); 3030 if (err) 3031 goto err_txrx_free; 3032 } 3033 3034 clear_bit(IONIC_LIF_F_FW_RESET, lif->state); 3035 ionic_link_status_check_request(lif, CAN_SLEEP); 3036 netif_device_attach(lif->netdev); 3037 dev_info(ionic->dev, "FW Up: LIFs restarted\n"); 3038 3039 /* restore the hardware timestamping queues */ 3040 ionic_lif_hwstamp_replay(lif); 3041 3042 return; 3043 3044 err_txrx_free: 3045 ionic_txrx_free(lif); 3046 err_lifs_deinit: 3047 ionic_lif_deinit(lif); 3048 err_qcqs_free: 3049 ionic_qcqs_free(lif); 3050 err_out: 3051 dev_err(ionic->dev, "FW Up: LIFs restart failed - err %d\n", err); 3052 } 3053 3054 void ionic_lif_free(struct ionic_lif *lif) 3055 { 3056 struct device *dev = lif->ionic->dev; 3057 3058 ionic_lif_free_phc(lif); 3059 3060 /* free rss indirection table */ 3061 dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl, 3062 lif->rss_ind_tbl_pa); 3063 lif->rss_ind_tbl = NULL; 3064 lif->rss_ind_tbl_pa = 0; 3065 3066 /* free queues */ 3067 ionic_qcqs_free(lif); 3068 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 3069 ionic_lif_reset(lif); 3070 3071 /* free lif info */ 3072 kfree(lif->identity); 3073 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 3074 lif->info = NULL; 3075 lif->info_pa = 0; 3076 3077 /* unmap doorbell page */ 3078 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 3079 lif->kern_dbpage = NULL; 3080 kfree(lif->dbid_inuse); 3081 lif->dbid_inuse = NULL; 3082 3083 /* free netdev & lif */ 3084 ionic_debugfs_del_lif(lif); 3085 free_netdev(lif->netdev); 3086 } 3087 3088 void ionic_lif_deinit(struct ionic_lif *lif) 3089 { 3090 if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state)) 3091 return; 3092 3093 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 3094 cancel_work_sync(&lif->deferred.work); 3095 cancel_work_sync(&lif->tx_timeout_work); 3096 ionic_rx_filters_deinit(lif); 3097 if (lif->netdev->features & NETIF_F_RXHASH) 3098 ionic_lif_rss_deinit(lif); 3099 } 3100 3101 napi_disable(&lif->adminqcq->napi); 3102 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 3103 ionic_lif_qcq_deinit(lif, lif->adminqcq); 3104 3105 mutex_destroy(&lif->config_lock); 3106 mutex_destroy(&lif->queue_lock); 3107 ionic_lif_reset(lif); 3108 } 3109 3110 static int ionic_lif_adminq_init(struct ionic_lif *lif) 3111 { 3112 struct device *dev = lif->ionic->dev; 3113 struct ionic_q_init_comp comp; 3114 struct ionic_dev *idev; 3115 struct ionic_qcq *qcq; 3116 struct ionic_queue *q; 3117 int err; 3118 3119 idev = &lif->ionic->idev; 3120 qcq = lif->adminqcq; 3121 q = &qcq->q; 3122 3123 mutex_lock(&lif->ionic->dev_cmd_lock); 3124 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index); 3125 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 3126 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 3127 mutex_unlock(&lif->ionic->dev_cmd_lock); 3128 if (err) { 3129 netdev_err(lif->netdev, "adminq init failed %d\n", err); 3130 return err; 3131 } 3132 3133 q->hw_type = comp.hw_type; 3134 q->hw_index = le32_to_cpu(comp.hw_index); 3135 q->dbval = IONIC_DBELL_QID(q->hw_index); 3136 3137 dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type); 3138 dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index); 3139 3140 netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi, 3141 NAPI_POLL_WEIGHT); 3142 3143 napi_enable(&qcq->napi); 3144 3145 if (qcq->flags & IONIC_QCQ_F_INTR) 3146 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 3147 IONIC_INTR_MASK_CLEAR); 3148 3149 qcq->flags |= IONIC_QCQ_F_INITED; 3150 3151 return 0; 3152 } 3153 3154 static int ionic_lif_notifyq_init(struct ionic_lif *lif) 3155 { 3156 struct ionic_qcq *qcq = lif->notifyqcq; 3157 struct device *dev = lif->ionic->dev; 3158 struct ionic_queue *q = &qcq->q; 3159 int err; 3160 3161 struct ionic_admin_ctx ctx = { 3162 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3163 .cmd.q_init = { 3164 .opcode = IONIC_CMD_Q_INIT, 3165 .lif_index = cpu_to_le16(lif->index), 3166 .type = q->type, 3167 .ver = lif->qtype_info[q->type].version, 3168 .index = cpu_to_le32(q->index), 3169 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 3170 IONIC_QINIT_F_ENA), 3171 .intr_index = cpu_to_le16(lif->adminqcq->intr.index), 3172 .pid = cpu_to_le16(q->pid), 3173 .ring_size = ilog2(q->num_descs), 3174 .ring_base = cpu_to_le64(q->base_pa), 3175 } 3176 }; 3177 3178 dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid); 3179 dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index); 3180 dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 3181 dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 3182 3183 err = ionic_adminq_post_wait(lif, &ctx); 3184 if (err) 3185 return err; 3186 3187 lif->last_eid = 0; 3188 q->hw_type = ctx.comp.q_init.hw_type; 3189 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 3190 q->dbval = IONIC_DBELL_QID(q->hw_index); 3191 3192 dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type); 3193 dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index); 3194 3195 /* preset the callback info */ 3196 q->info[0].cb_arg = lif; 3197 3198 qcq->flags |= IONIC_QCQ_F_INITED; 3199 3200 return 0; 3201 } 3202 3203 static int ionic_station_set(struct ionic_lif *lif) 3204 { 3205 struct net_device *netdev = lif->netdev; 3206 struct ionic_admin_ctx ctx = { 3207 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3208 .cmd.lif_getattr = { 3209 .opcode = IONIC_CMD_LIF_GETATTR, 3210 .index = cpu_to_le16(lif->index), 3211 .attr = IONIC_LIF_ATTR_MAC, 3212 }, 3213 }; 3214 struct sockaddr addr; 3215 int err; 3216 3217 err = ionic_adminq_post_wait(lif, &ctx); 3218 if (err) 3219 return err; 3220 netdev_dbg(lif->netdev, "found initial MAC addr %pM\n", 3221 ctx.comp.lif_getattr.mac); 3222 if (is_zero_ether_addr(ctx.comp.lif_getattr.mac)) 3223 return 0; 3224 3225 if (!is_zero_ether_addr(netdev->dev_addr)) { 3226 /* If the netdev mac is non-zero and doesn't match the default 3227 * device address, it was set by something earlier and we're 3228 * likely here again after a fw-upgrade reset. We need to be 3229 * sure the netdev mac is in our filter list. 3230 */ 3231 if (!ether_addr_equal(ctx.comp.lif_getattr.mac, 3232 netdev->dev_addr)) 3233 ionic_lif_addr_add(lif, netdev->dev_addr); 3234 } else { 3235 /* Update the netdev mac with the device's mac */ 3236 memcpy(addr.sa_data, ctx.comp.lif_getattr.mac, netdev->addr_len); 3237 addr.sa_family = AF_INET; 3238 err = eth_prepare_mac_addr_change(netdev, &addr); 3239 if (err) { 3240 netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n", 3241 addr.sa_data, err); 3242 return 0; 3243 } 3244 3245 eth_commit_mac_addr_change(netdev, &addr); 3246 } 3247 3248 netdev_dbg(lif->netdev, "adding station MAC addr %pM\n", 3249 netdev->dev_addr); 3250 ionic_lif_addr_add(lif, netdev->dev_addr); 3251 3252 return 0; 3253 } 3254 3255 int ionic_lif_init(struct ionic_lif *lif) 3256 { 3257 struct ionic_dev *idev = &lif->ionic->idev; 3258 struct device *dev = lif->ionic->dev; 3259 struct ionic_lif_init_comp comp; 3260 int dbpage_num; 3261 int err; 3262 3263 mutex_lock(&lif->ionic->dev_cmd_lock); 3264 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa); 3265 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 3266 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 3267 mutex_unlock(&lif->ionic->dev_cmd_lock); 3268 if (err) 3269 return err; 3270 3271 lif->hw_index = le16_to_cpu(comp.hw_index); 3272 mutex_init(&lif->queue_lock); 3273 mutex_init(&lif->config_lock); 3274 3275 /* now that we have the hw_index we can figure out our doorbell page */ 3276 lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif); 3277 if (!lif->dbid_count) { 3278 dev_err(dev, "No doorbell pages, aborting\n"); 3279 return -EINVAL; 3280 } 3281 3282 lif->dbid_inuse = bitmap_alloc(lif->dbid_count, GFP_KERNEL); 3283 if (!lif->dbid_inuse) { 3284 dev_err(dev, "Failed alloc doorbell id bitmap, aborting\n"); 3285 return -ENOMEM; 3286 } 3287 3288 /* first doorbell id reserved for kernel (dbid aka pid == zero) */ 3289 set_bit(0, lif->dbid_inuse); 3290 lif->kern_pid = 0; 3291 3292 dbpage_num = ionic_db_page_num(lif, lif->kern_pid); 3293 lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num); 3294 if (!lif->kern_dbpage) { 3295 dev_err(dev, "Cannot map dbpage, aborting\n"); 3296 err = -ENOMEM; 3297 goto err_out_free_dbid; 3298 } 3299 3300 err = ionic_lif_adminq_init(lif); 3301 if (err) 3302 goto err_out_adminq_deinit; 3303 3304 if (lif->ionic->nnqs_per_lif) { 3305 err = ionic_lif_notifyq_init(lif); 3306 if (err) 3307 goto err_out_notifyq_deinit; 3308 } 3309 3310 err = ionic_init_nic_features(lif); 3311 if (err) 3312 goto err_out_notifyq_deinit; 3313 3314 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 3315 err = ionic_rx_filters_init(lif); 3316 if (err) 3317 goto err_out_notifyq_deinit; 3318 } 3319 3320 err = ionic_station_set(lif); 3321 if (err) 3322 goto err_out_notifyq_deinit; 3323 3324 lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT; 3325 3326 set_bit(IONIC_LIF_F_INITED, lif->state); 3327 3328 INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work); 3329 3330 return 0; 3331 3332 err_out_notifyq_deinit: 3333 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 3334 err_out_adminq_deinit: 3335 ionic_lif_qcq_deinit(lif, lif->adminqcq); 3336 ionic_lif_reset(lif); 3337 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 3338 lif->kern_dbpage = NULL; 3339 err_out_free_dbid: 3340 kfree(lif->dbid_inuse); 3341 lif->dbid_inuse = NULL; 3342 3343 return err; 3344 } 3345 3346 static void ionic_lif_notify_work(struct work_struct *ws) 3347 { 3348 } 3349 3350 static void ionic_lif_set_netdev_info(struct ionic_lif *lif) 3351 { 3352 struct ionic_admin_ctx ctx = { 3353 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3354 .cmd.lif_setattr = { 3355 .opcode = IONIC_CMD_LIF_SETATTR, 3356 .index = cpu_to_le16(lif->index), 3357 .attr = IONIC_LIF_ATTR_NAME, 3358 }, 3359 }; 3360 3361 strlcpy(ctx.cmd.lif_setattr.name, lif->netdev->name, 3362 sizeof(ctx.cmd.lif_setattr.name)); 3363 3364 ionic_adminq_post_wait(lif, &ctx); 3365 } 3366 3367 static struct ionic_lif *ionic_netdev_lif(struct net_device *netdev) 3368 { 3369 if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit) 3370 return NULL; 3371 3372 return netdev_priv(netdev); 3373 } 3374 3375 static int ionic_lif_notify(struct notifier_block *nb, 3376 unsigned long event, void *info) 3377 { 3378 struct net_device *ndev = netdev_notifier_info_to_dev(info); 3379 struct ionic *ionic = container_of(nb, struct ionic, nb); 3380 struct ionic_lif *lif = ionic_netdev_lif(ndev); 3381 3382 if (!lif || lif->ionic != ionic) 3383 return NOTIFY_DONE; 3384 3385 switch (event) { 3386 case NETDEV_CHANGENAME: 3387 ionic_lif_set_netdev_info(lif); 3388 break; 3389 } 3390 3391 return NOTIFY_DONE; 3392 } 3393 3394 int ionic_lif_register(struct ionic_lif *lif) 3395 { 3396 int err; 3397 3398 ionic_lif_register_phc(lif); 3399 3400 INIT_WORK(&lif->ionic->nb_work, ionic_lif_notify_work); 3401 3402 lif->ionic->nb.notifier_call = ionic_lif_notify; 3403 3404 err = register_netdevice_notifier(&lif->ionic->nb); 3405 if (err) 3406 lif->ionic->nb.notifier_call = NULL; 3407 3408 /* only register LIF0 for now */ 3409 err = register_netdev(lif->netdev); 3410 if (err) { 3411 dev_err(lif->ionic->dev, "Cannot register net device, aborting\n"); 3412 ionic_lif_unregister_phc(lif); 3413 return err; 3414 } 3415 3416 ionic_link_status_check_request(lif, CAN_SLEEP); 3417 lif->registered = true; 3418 ionic_lif_set_netdev_info(lif); 3419 3420 return 0; 3421 } 3422 3423 void ionic_lif_unregister(struct ionic_lif *lif) 3424 { 3425 if (lif->ionic->nb.notifier_call) { 3426 unregister_netdevice_notifier(&lif->ionic->nb); 3427 cancel_work_sync(&lif->ionic->nb_work); 3428 lif->ionic->nb.notifier_call = NULL; 3429 } 3430 3431 if (lif->netdev->reg_state == NETREG_REGISTERED) 3432 unregister_netdev(lif->netdev); 3433 3434 ionic_lif_unregister_phc(lif); 3435 3436 lif->registered = false; 3437 } 3438 3439 static void ionic_lif_queue_identify(struct ionic_lif *lif) 3440 { 3441 union ionic_q_identity __iomem *q_ident; 3442 struct ionic *ionic = lif->ionic; 3443 struct ionic_dev *idev; 3444 int qtype; 3445 int err; 3446 3447 idev = &lif->ionic->idev; 3448 q_ident = (union ionic_q_identity __iomem *)&idev->dev_cmd_regs->data; 3449 3450 for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) { 3451 struct ionic_qtype_info *qti = &lif->qtype_info[qtype]; 3452 3453 /* filter out the ones we know about */ 3454 switch (qtype) { 3455 case IONIC_QTYPE_ADMINQ: 3456 case IONIC_QTYPE_NOTIFYQ: 3457 case IONIC_QTYPE_RXQ: 3458 case IONIC_QTYPE_TXQ: 3459 break; 3460 default: 3461 continue; 3462 } 3463 3464 memset(qti, 0, sizeof(*qti)); 3465 3466 mutex_lock(&ionic->dev_cmd_lock); 3467 ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype, 3468 ionic_qtype_versions[qtype]); 3469 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3470 if (!err) { 3471 qti->version = readb(&q_ident->version); 3472 qti->supported = readb(&q_ident->supported); 3473 qti->features = readq(&q_ident->features); 3474 qti->desc_sz = readw(&q_ident->desc_sz); 3475 qti->comp_sz = readw(&q_ident->comp_sz); 3476 qti->sg_desc_sz = readw(&q_ident->sg_desc_sz); 3477 qti->max_sg_elems = readw(&q_ident->max_sg_elems); 3478 qti->sg_desc_stride = readw(&q_ident->sg_desc_stride); 3479 } 3480 mutex_unlock(&ionic->dev_cmd_lock); 3481 3482 if (err == -EINVAL) { 3483 dev_err(ionic->dev, "qtype %d not supported\n", qtype); 3484 continue; 3485 } else if (err == -EIO) { 3486 dev_err(ionic->dev, "q_ident failed, not supported on older FW\n"); 3487 return; 3488 } else if (err) { 3489 dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n", 3490 qtype, err); 3491 return; 3492 } 3493 3494 dev_dbg(ionic->dev, " qtype[%d].version = %d\n", 3495 qtype, qti->version); 3496 dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n", 3497 qtype, qti->supported); 3498 dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n", 3499 qtype, qti->features); 3500 dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n", 3501 qtype, qti->desc_sz); 3502 dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n", 3503 qtype, qti->comp_sz); 3504 dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n", 3505 qtype, qti->sg_desc_sz); 3506 dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n", 3507 qtype, qti->max_sg_elems); 3508 dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n", 3509 qtype, qti->sg_desc_stride); 3510 } 3511 } 3512 3513 int ionic_lif_identify(struct ionic *ionic, u8 lif_type, 3514 union ionic_lif_identity *lid) 3515 { 3516 struct ionic_dev *idev = &ionic->idev; 3517 size_t sz; 3518 int err; 3519 3520 sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data)); 3521 3522 mutex_lock(&ionic->dev_cmd_lock); 3523 ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1); 3524 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3525 memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz); 3526 mutex_unlock(&ionic->dev_cmd_lock); 3527 if (err) 3528 return (err); 3529 3530 dev_dbg(ionic->dev, "capabilities 0x%llx\n", 3531 le64_to_cpu(lid->capabilities)); 3532 3533 dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n", 3534 le32_to_cpu(lid->eth.max_ucast_filters)); 3535 dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n", 3536 le32_to_cpu(lid->eth.max_mcast_filters)); 3537 dev_dbg(ionic->dev, "eth.features 0x%llx\n", 3538 le64_to_cpu(lid->eth.config.features)); 3539 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n", 3540 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ])); 3541 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n", 3542 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ])); 3543 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n", 3544 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ])); 3545 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n", 3546 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ])); 3547 dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name); 3548 dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac); 3549 dev_dbg(ionic->dev, "eth.config.mtu %d\n", 3550 le32_to_cpu(lid->eth.config.mtu)); 3551 3552 return 0; 3553 } 3554 3555 int ionic_lif_size(struct ionic *ionic) 3556 { 3557 struct ionic_identity *ident = &ionic->ident; 3558 unsigned int nintrs, dev_nintrs; 3559 union ionic_lif_config *lc; 3560 unsigned int ntxqs_per_lif; 3561 unsigned int nrxqs_per_lif; 3562 unsigned int neqs_per_lif; 3563 unsigned int nnqs_per_lif; 3564 unsigned int nxqs, neqs; 3565 unsigned int min_intrs; 3566 int err; 3567 3568 /* retrieve basic values from FW */ 3569 lc = &ident->lif.eth.config; 3570 dev_nintrs = le32_to_cpu(ident->dev.nintrs); 3571 neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count); 3572 nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]); 3573 ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]); 3574 nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]); 3575 3576 /* limit values to play nice with kdump */ 3577 if (is_kdump_kernel()) { 3578 dev_nintrs = 2; 3579 neqs_per_lif = 0; 3580 nnqs_per_lif = 0; 3581 ntxqs_per_lif = 1; 3582 nrxqs_per_lif = 1; 3583 } 3584 3585 /* reserve last queue id for hardware timestamping */ 3586 if (lc->features & cpu_to_le64(IONIC_ETH_HW_TIMESTAMP)) { 3587 if (ntxqs_per_lif <= 1 || nrxqs_per_lif <= 1) { 3588 lc->features &= cpu_to_le64(~IONIC_ETH_HW_TIMESTAMP); 3589 } else { 3590 ntxqs_per_lif -= 1; 3591 nrxqs_per_lif -= 1; 3592 } 3593 } 3594 3595 nxqs = min(ntxqs_per_lif, nrxqs_per_lif); 3596 nxqs = min(nxqs, num_online_cpus()); 3597 neqs = min(neqs_per_lif, num_online_cpus()); 3598 3599 try_again: 3600 /* interrupt usage: 3601 * 1 for master lif adminq/notifyq 3602 * 1 for each CPU for master lif TxRx queue pairs 3603 * whatever's left is for RDMA queues 3604 */ 3605 nintrs = 1 + nxqs + neqs; 3606 min_intrs = 2; /* adminq + 1 TxRx queue pair */ 3607 3608 if (nintrs > dev_nintrs) 3609 goto try_fewer; 3610 3611 err = ionic_bus_alloc_irq_vectors(ionic, nintrs); 3612 if (err < 0 && err != -ENOSPC) { 3613 dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err); 3614 return err; 3615 } 3616 if (err == -ENOSPC) 3617 goto try_fewer; 3618 3619 if (err != nintrs) { 3620 ionic_bus_free_irq_vectors(ionic); 3621 goto try_fewer; 3622 } 3623 3624 ionic->nnqs_per_lif = nnqs_per_lif; 3625 ionic->neqs_per_lif = neqs; 3626 ionic->ntxqs_per_lif = nxqs; 3627 ionic->nrxqs_per_lif = nxqs; 3628 ionic->nintrs = nintrs; 3629 3630 ionic_debugfs_add_sizes(ionic); 3631 3632 return 0; 3633 3634 try_fewer: 3635 if (nnqs_per_lif > 1) { 3636 nnqs_per_lif >>= 1; 3637 goto try_again; 3638 } 3639 if (neqs > 1) { 3640 neqs >>= 1; 3641 goto try_again; 3642 } 3643 if (nxqs > 1) { 3644 nxqs >>= 1; 3645 goto try_again; 3646 } 3647 dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs); 3648 return -ENOSPC; 3649 } 3650