1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/ethtool.h> 5 #include <linux/printk.h> 6 #include <linux/dynamic_debug.h> 7 #include <linux/netdevice.h> 8 #include <linux/etherdevice.h> 9 #include <linux/if_vlan.h> 10 #include <linux/rtnetlink.h> 11 #include <linux/interrupt.h> 12 #include <linux/pci.h> 13 #include <linux/cpumask.h> 14 #include <linux/crash_dump.h> 15 16 #include "ionic.h" 17 #include "ionic_bus.h" 18 #include "ionic_lif.h" 19 #include "ionic_txrx.h" 20 #include "ionic_ethtool.h" 21 #include "ionic_debugfs.h" 22 23 /* queuetype support level */ 24 static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = { 25 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */ 26 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */ 27 [IONIC_QTYPE_RXQ] = 0, /* 0 = Base version with CQ+SG support */ 28 [IONIC_QTYPE_TXQ] = 1, /* 0 = Base version with CQ+SG support 29 * 1 = ... with Tx SG version 1 30 */ 31 }; 32 33 static void ionic_link_status_check(struct ionic_lif *lif); 34 static void ionic_lif_handle_fw_down(struct ionic_lif *lif); 35 static void ionic_lif_handle_fw_up(struct ionic_lif *lif); 36 static void ionic_lif_set_netdev_info(struct ionic_lif *lif); 37 38 static void ionic_txrx_deinit(struct ionic_lif *lif); 39 static int ionic_txrx_init(struct ionic_lif *lif); 40 static int ionic_start_queues(struct ionic_lif *lif); 41 static void ionic_stop_queues(struct ionic_lif *lif); 42 static void ionic_lif_queue_identify(struct ionic_lif *lif); 43 44 static void ionic_dim_work(struct work_struct *work) 45 { 46 struct dim *dim = container_of(work, struct dim, work); 47 struct dim_cq_moder cur_moder; 48 struct ionic_qcq *qcq; 49 u32 new_coal; 50 51 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 52 qcq = container_of(dim, struct ionic_qcq, dim); 53 new_coal = ionic_coal_usec_to_hw(qcq->q.lif->ionic, cur_moder.usec); 54 new_coal = new_coal ? new_coal : 1; 55 56 if (qcq->intr.dim_coal_hw != new_coal) { 57 unsigned int qi = qcq->cq.bound_q->index; 58 struct ionic_lif *lif = qcq->q.lif; 59 60 qcq->intr.dim_coal_hw = new_coal; 61 62 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 63 lif->rxqcqs[qi]->intr.index, 64 qcq->intr.dim_coal_hw); 65 } 66 67 dim->state = DIM_START_MEASURE; 68 } 69 70 static void ionic_lif_deferred_work(struct work_struct *work) 71 { 72 struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work); 73 struct ionic_deferred *def = &lif->deferred; 74 struct ionic_deferred_work *w = NULL; 75 76 do { 77 spin_lock_bh(&def->lock); 78 if (!list_empty(&def->list)) { 79 w = list_first_entry(&def->list, 80 struct ionic_deferred_work, list); 81 list_del(&w->list); 82 } 83 spin_unlock_bh(&def->lock); 84 85 if (!w) 86 break; 87 88 switch (w->type) { 89 case IONIC_DW_TYPE_RX_MODE: 90 ionic_lif_rx_mode(lif); 91 break; 92 case IONIC_DW_TYPE_LINK_STATUS: 93 ionic_link_status_check(lif); 94 break; 95 case IONIC_DW_TYPE_LIF_RESET: 96 if (w->fw_status) { 97 ionic_lif_handle_fw_up(lif); 98 } else { 99 ionic_lif_handle_fw_down(lif); 100 101 /* Fire off another watchdog to see 102 * if the FW is already back rather than 103 * waiting another whole cycle 104 */ 105 mod_timer(&lif->ionic->watchdog_timer, jiffies + 1); 106 } 107 break; 108 default: 109 break; 110 } 111 kfree(w); 112 w = NULL; 113 } while (true); 114 } 115 116 void ionic_lif_deferred_enqueue(struct ionic_deferred *def, 117 struct ionic_deferred_work *work) 118 { 119 spin_lock_bh(&def->lock); 120 list_add_tail(&work->list, &def->list); 121 spin_unlock_bh(&def->lock); 122 schedule_work(&def->work); 123 } 124 125 static void ionic_link_status_check(struct ionic_lif *lif) 126 { 127 struct net_device *netdev = lif->netdev; 128 u16 link_status; 129 bool link_up; 130 131 if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 132 return; 133 134 /* Don't put carrier back up if we're in a broken state */ 135 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) { 136 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 137 return; 138 } 139 140 link_status = le16_to_cpu(lif->info->status.link_status); 141 link_up = link_status == IONIC_PORT_OPER_STATUS_UP; 142 143 if (link_up) { 144 int err = 0; 145 146 if (netdev->flags & IFF_UP && netif_running(netdev)) { 147 mutex_lock(&lif->queue_lock); 148 err = ionic_start_queues(lif); 149 if (err && err != -EBUSY) { 150 netdev_err(lif->netdev, 151 "Failed to start queues: %d\n", err); 152 set_bit(IONIC_LIF_F_BROKEN, lif->state); 153 netif_carrier_off(lif->netdev); 154 } 155 mutex_unlock(&lif->queue_lock); 156 } 157 158 if (!err && !netif_carrier_ok(netdev)) { 159 ionic_port_identify(lif->ionic); 160 netdev_info(netdev, "Link up - %d Gbps\n", 161 le32_to_cpu(lif->info->status.link_speed) / 1000); 162 netif_carrier_on(netdev); 163 } 164 } else { 165 if (netif_carrier_ok(netdev)) { 166 netdev_info(netdev, "Link down\n"); 167 netif_carrier_off(netdev); 168 } 169 170 if (netdev->flags & IFF_UP && netif_running(netdev)) { 171 mutex_lock(&lif->queue_lock); 172 ionic_stop_queues(lif); 173 mutex_unlock(&lif->queue_lock); 174 } 175 } 176 177 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 178 } 179 180 void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep) 181 { 182 struct ionic_deferred_work *work; 183 184 /* we only need one request outstanding at a time */ 185 if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 186 return; 187 188 if (!can_sleep) { 189 work = kzalloc(sizeof(*work), GFP_ATOMIC); 190 if (!work) { 191 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 192 return; 193 } 194 195 work->type = IONIC_DW_TYPE_LINK_STATUS; 196 ionic_lif_deferred_enqueue(&lif->deferred, work); 197 } else { 198 ionic_link_status_check(lif); 199 } 200 } 201 202 static irqreturn_t ionic_isr(int irq, void *data) 203 { 204 struct napi_struct *napi = data; 205 206 napi_schedule_irqoff(napi); 207 208 return IRQ_HANDLED; 209 } 210 211 static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq) 212 { 213 struct ionic_intr_info *intr = &qcq->intr; 214 struct device *dev = lif->ionic->dev; 215 struct ionic_queue *q = &qcq->q; 216 const char *name; 217 218 if (lif->registered) 219 name = lif->netdev->name; 220 else 221 name = dev_name(dev); 222 223 snprintf(intr->name, sizeof(intr->name), 224 "%s-%s-%s", IONIC_DRV_NAME, name, q->name); 225 226 return devm_request_irq(dev, intr->vector, ionic_isr, 227 0, intr->name, &qcq->napi); 228 } 229 230 static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) 231 { 232 struct ionic *ionic = lif->ionic; 233 int index; 234 235 index = find_first_zero_bit(ionic->intrs, ionic->nintrs); 236 if (index == ionic->nintrs) { 237 netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n", 238 __func__, index, ionic->nintrs); 239 return -ENOSPC; 240 } 241 242 set_bit(index, ionic->intrs); 243 ionic_intr_init(&ionic->idev, intr, index); 244 245 return 0; 246 } 247 248 static void ionic_intr_free(struct ionic *ionic, int index) 249 { 250 if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < ionic->nintrs) 251 clear_bit(index, ionic->intrs); 252 } 253 254 static int ionic_qcq_enable(struct ionic_qcq *qcq) 255 { 256 struct ionic_queue *q = &qcq->q; 257 struct ionic_lif *lif = q->lif; 258 struct ionic_dev *idev; 259 struct device *dev; 260 261 struct ionic_admin_ctx ctx = { 262 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 263 .cmd.q_control = { 264 .opcode = IONIC_CMD_Q_CONTROL, 265 .lif_index = cpu_to_le16(lif->index), 266 .type = q->type, 267 .index = cpu_to_le32(q->index), 268 .oper = IONIC_Q_ENABLE, 269 }, 270 }; 271 272 idev = &lif->ionic->idev; 273 dev = lif->ionic->dev; 274 275 dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n", 276 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 277 278 if (qcq->flags & IONIC_QCQ_F_INTR) { 279 irq_set_affinity_hint(qcq->intr.vector, 280 &qcq->intr.affinity_mask); 281 napi_enable(&qcq->napi); 282 ionic_intr_clean(idev->intr_ctrl, qcq->intr.index); 283 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 284 IONIC_INTR_MASK_CLEAR); 285 } 286 287 return ionic_adminq_post_wait(lif, &ctx); 288 } 289 290 static int ionic_qcq_disable(struct ionic_lif *lif, struct ionic_qcq *qcq, int fw_err) 291 { 292 struct ionic_queue *q; 293 294 struct ionic_admin_ctx ctx = { 295 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 296 .cmd.q_control = { 297 .opcode = IONIC_CMD_Q_CONTROL, 298 .oper = IONIC_Q_DISABLE, 299 }, 300 }; 301 302 if (!qcq) { 303 netdev_err(lif->netdev, "%s: bad qcq\n", __func__); 304 return -ENXIO; 305 } 306 307 q = &qcq->q; 308 309 if (qcq->flags & IONIC_QCQ_F_INTR) { 310 struct ionic_dev *idev = &lif->ionic->idev; 311 312 cancel_work_sync(&qcq->dim.work); 313 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 314 IONIC_INTR_MASK_SET); 315 synchronize_irq(qcq->intr.vector); 316 irq_set_affinity_hint(qcq->intr.vector, NULL); 317 napi_disable(&qcq->napi); 318 } 319 320 /* If there was a previous fw communcation error, don't bother with 321 * sending the adminq command and just return the same error value. 322 */ 323 if (fw_err == -ETIMEDOUT || fw_err == -ENXIO) 324 return fw_err; 325 326 ctx.cmd.q_control.lif_index = cpu_to_le16(lif->index); 327 ctx.cmd.q_control.type = q->type; 328 ctx.cmd.q_control.index = cpu_to_le32(q->index); 329 dev_dbg(lif->ionic->dev, "q_disable.index %d q_disable.qtype %d\n", 330 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 331 332 return ionic_adminq_post_wait(lif, &ctx); 333 } 334 335 static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq) 336 { 337 struct ionic_dev *idev = &lif->ionic->idev; 338 339 if (!qcq) 340 return; 341 342 if (!(qcq->flags & IONIC_QCQ_F_INITED)) 343 return; 344 345 if (qcq->flags & IONIC_QCQ_F_INTR) { 346 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 347 IONIC_INTR_MASK_SET); 348 netif_napi_del(&qcq->napi); 349 } 350 351 qcq->flags &= ~IONIC_QCQ_F_INITED; 352 } 353 354 static void ionic_qcq_intr_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 355 { 356 if (!(qcq->flags & IONIC_QCQ_F_INTR) || qcq->intr.vector == 0) 357 return; 358 359 irq_set_affinity_hint(qcq->intr.vector, NULL); 360 devm_free_irq(lif->ionic->dev, qcq->intr.vector, &qcq->napi); 361 qcq->intr.vector = 0; 362 ionic_intr_free(lif->ionic, qcq->intr.index); 363 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 364 } 365 366 static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 367 { 368 struct device *dev = lif->ionic->dev; 369 370 if (!qcq) 371 return; 372 373 ionic_debugfs_del_qcq(qcq); 374 375 if (qcq->q_base) { 376 dma_free_coherent(dev, qcq->q_size, qcq->q_base, qcq->q_base_pa); 377 qcq->q_base = NULL; 378 qcq->q_base_pa = 0; 379 } 380 381 if (qcq->cq_base) { 382 dma_free_coherent(dev, qcq->cq_size, qcq->cq_base, qcq->cq_base_pa); 383 qcq->cq_base = NULL; 384 qcq->cq_base_pa = 0; 385 } 386 387 if (qcq->sg_base) { 388 dma_free_coherent(dev, qcq->sg_size, qcq->sg_base, qcq->sg_base_pa); 389 qcq->sg_base = NULL; 390 qcq->sg_base_pa = 0; 391 } 392 393 ionic_qcq_intr_free(lif, qcq); 394 395 if (qcq->cq.info) { 396 devm_kfree(dev, qcq->cq.info); 397 qcq->cq.info = NULL; 398 } 399 if (qcq->q.info) { 400 devm_kfree(dev, qcq->q.info); 401 qcq->q.info = NULL; 402 } 403 } 404 405 static void ionic_qcqs_free(struct ionic_lif *lif) 406 { 407 struct device *dev = lif->ionic->dev; 408 struct ionic_qcq *adminqcq; 409 unsigned long irqflags; 410 411 if (lif->notifyqcq) { 412 ionic_qcq_free(lif, lif->notifyqcq); 413 devm_kfree(dev, lif->notifyqcq); 414 lif->notifyqcq = NULL; 415 } 416 417 if (lif->adminqcq) { 418 spin_lock_irqsave(&lif->adminq_lock, irqflags); 419 adminqcq = READ_ONCE(lif->adminqcq); 420 lif->adminqcq = NULL; 421 spin_unlock_irqrestore(&lif->adminq_lock, irqflags); 422 if (adminqcq) { 423 ionic_qcq_free(lif, adminqcq); 424 devm_kfree(dev, adminqcq); 425 } 426 } 427 428 if (lif->rxqcqs) { 429 devm_kfree(dev, lif->rxqstats); 430 lif->rxqstats = NULL; 431 devm_kfree(dev, lif->rxqcqs); 432 lif->rxqcqs = NULL; 433 } 434 435 if (lif->txqcqs) { 436 devm_kfree(dev, lif->txqstats); 437 lif->txqstats = NULL; 438 devm_kfree(dev, lif->txqcqs); 439 lif->txqcqs = NULL; 440 } 441 } 442 443 static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq, 444 struct ionic_qcq *n_qcq) 445 { 446 if (WARN_ON(n_qcq->flags & IONIC_QCQ_F_INTR)) { 447 ionic_intr_free(n_qcq->cq.lif->ionic, n_qcq->intr.index); 448 n_qcq->flags &= ~IONIC_QCQ_F_INTR; 449 } 450 451 n_qcq->intr.vector = src_qcq->intr.vector; 452 n_qcq->intr.index = src_qcq->intr.index; 453 } 454 455 static int ionic_alloc_qcq_interrupt(struct ionic_lif *lif, struct ionic_qcq *qcq) 456 { 457 int err; 458 459 if (!(qcq->flags & IONIC_QCQ_F_INTR)) { 460 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 461 return 0; 462 } 463 464 err = ionic_intr_alloc(lif, &qcq->intr); 465 if (err) { 466 netdev_warn(lif->netdev, "no intr for %s: %d\n", 467 qcq->q.name, err); 468 goto err_out; 469 } 470 471 err = ionic_bus_get_irq(lif->ionic, qcq->intr.index); 472 if (err < 0) { 473 netdev_warn(lif->netdev, "no vector for %s: %d\n", 474 qcq->q.name, err); 475 goto err_out_free_intr; 476 } 477 qcq->intr.vector = err; 478 ionic_intr_mask_assert(lif->ionic->idev.intr_ctrl, qcq->intr.index, 479 IONIC_INTR_MASK_SET); 480 481 err = ionic_request_irq(lif, qcq); 482 if (err) { 483 netdev_warn(lif->netdev, "irq request failed %d\n", err); 484 goto err_out_free_intr; 485 } 486 487 /* try to get the irq on the local numa node first */ 488 qcq->intr.cpu = cpumask_local_spread(qcq->intr.index, 489 dev_to_node(lif->ionic->dev)); 490 if (qcq->intr.cpu != -1) 491 cpumask_set_cpu(qcq->intr.cpu, &qcq->intr.affinity_mask); 492 493 netdev_dbg(lif->netdev, "%s: Interrupt index %d\n", qcq->q.name, qcq->intr.index); 494 return 0; 495 496 err_out_free_intr: 497 ionic_intr_free(lif->ionic, qcq->intr.index); 498 err_out: 499 return err; 500 } 501 502 static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type, 503 unsigned int index, 504 const char *name, unsigned int flags, 505 unsigned int num_descs, unsigned int desc_size, 506 unsigned int cq_desc_size, 507 unsigned int sg_desc_size, 508 unsigned int pid, struct ionic_qcq **qcq) 509 { 510 struct ionic_dev *idev = &lif->ionic->idev; 511 struct device *dev = lif->ionic->dev; 512 void *q_base, *cq_base, *sg_base; 513 dma_addr_t cq_base_pa = 0; 514 dma_addr_t sg_base_pa = 0; 515 dma_addr_t q_base_pa = 0; 516 struct ionic_qcq *new; 517 int err; 518 519 *qcq = NULL; 520 521 new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL); 522 if (!new) { 523 netdev_err(lif->netdev, "Cannot allocate queue structure\n"); 524 err = -ENOMEM; 525 goto err_out; 526 } 527 528 new->q.dev = dev; 529 new->flags = flags; 530 531 new->q.info = devm_kcalloc(dev, num_descs, sizeof(*new->q.info), 532 GFP_KERNEL); 533 if (!new->q.info) { 534 netdev_err(lif->netdev, "Cannot allocate queue info\n"); 535 err = -ENOMEM; 536 goto err_out_free_qcq; 537 } 538 539 new->q.type = type; 540 new->q.max_sg_elems = lif->qtype_info[type].max_sg_elems; 541 542 err = ionic_q_init(lif, idev, &new->q, index, name, num_descs, 543 desc_size, sg_desc_size, pid); 544 if (err) { 545 netdev_err(lif->netdev, "Cannot initialize queue\n"); 546 goto err_out_free_q_info; 547 } 548 549 err = ionic_alloc_qcq_interrupt(lif, new); 550 if (err) 551 goto err_out; 552 553 new->cq.info = devm_kcalloc(dev, num_descs, sizeof(*new->cq.info), 554 GFP_KERNEL); 555 if (!new->cq.info) { 556 netdev_err(lif->netdev, "Cannot allocate completion queue info\n"); 557 err = -ENOMEM; 558 goto err_out_free_irq; 559 } 560 561 err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size); 562 if (err) { 563 netdev_err(lif->netdev, "Cannot initialize completion queue\n"); 564 goto err_out_free_cq_info; 565 } 566 567 if (flags & IONIC_QCQ_F_NOTIFYQ) { 568 int q_size, cq_size; 569 570 /* q & cq need to be contiguous in case of notifyq */ 571 q_size = ALIGN(num_descs * desc_size, PAGE_SIZE); 572 cq_size = ALIGN(num_descs * cq_desc_size, PAGE_SIZE); 573 574 new->q_size = PAGE_SIZE + q_size + cq_size; 575 new->q_base = dma_alloc_coherent(dev, new->q_size, 576 &new->q_base_pa, GFP_KERNEL); 577 if (!new->q_base) { 578 netdev_err(lif->netdev, "Cannot allocate qcq DMA memory\n"); 579 err = -ENOMEM; 580 goto err_out_free_cq_info; 581 } 582 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE); 583 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 584 ionic_q_map(&new->q, q_base, q_base_pa); 585 586 cq_base = PTR_ALIGN(q_base + q_size, PAGE_SIZE); 587 cq_base_pa = ALIGN(new->q_base_pa + q_size, PAGE_SIZE); 588 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 589 ionic_cq_bind(&new->cq, &new->q); 590 } else { 591 new->q_size = PAGE_SIZE + (num_descs * desc_size); 592 new->q_base = dma_alloc_coherent(dev, new->q_size, &new->q_base_pa, 593 GFP_KERNEL); 594 if (!new->q_base) { 595 netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n"); 596 err = -ENOMEM; 597 goto err_out_free_cq_info; 598 } 599 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE); 600 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 601 ionic_q_map(&new->q, q_base, q_base_pa); 602 603 new->cq_size = PAGE_SIZE + (num_descs * cq_desc_size); 604 new->cq_base = dma_alloc_coherent(dev, new->cq_size, &new->cq_base_pa, 605 GFP_KERNEL); 606 if (!new->cq_base) { 607 netdev_err(lif->netdev, "Cannot allocate cq DMA memory\n"); 608 err = -ENOMEM; 609 goto err_out_free_q; 610 } 611 cq_base = PTR_ALIGN(new->cq_base, PAGE_SIZE); 612 cq_base_pa = ALIGN(new->cq_base_pa, PAGE_SIZE); 613 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 614 ionic_cq_bind(&new->cq, &new->q); 615 } 616 617 if (flags & IONIC_QCQ_F_SG) { 618 new->sg_size = PAGE_SIZE + (num_descs * sg_desc_size); 619 new->sg_base = dma_alloc_coherent(dev, new->sg_size, &new->sg_base_pa, 620 GFP_KERNEL); 621 if (!new->sg_base) { 622 netdev_err(lif->netdev, "Cannot allocate sg DMA memory\n"); 623 err = -ENOMEM; 624 goto err_out_free_cq; 625 } 626 sg_base = PTR_ALIGN(new->sg_base, PAGE_SIZE); 627 sg_base_pa = ALIGN(new->sg_base_pa, PAGE_SIZE); 628 ionic_q_sg_map(&new->q, sg_base, sg_base_pa); 629 } 630 631 INIT_WORK(&new->dim.work, ionic_dim_work); 632 new->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 633 634 *qcq = new; 635 636 return 0; 637 638 err_out_free_cq: 639 dma_free_coherent(dev, new->cq_size, new->cq_base, new->cq_base_pa); 640 err_out_free_q: 641 dma_free_coherent(dev, new->q_size, new->q_base, new->q_base_pa); 642 err_out_free_cq_info: 643 devm_kfree(dev, new->cq.info); 644 err_out_free_irq: 645 if (flags & IONIC_QCQ_F_INTR) { 646 devm_free_irq(dev, new->intr.vector, &new->napi); 647 ionic_intr_free(lif->ionic, new->intr.index); 648 } 649 err_out_free_q_info: 650 devm_kfree(dev, new->q.info); 651 err_out_free_qcq: 652 devm_kfree(dev, new); 653 err_out: 654 dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err); 655 return err; 656 } 657 658 static int ionic_qcqs_alloc(struct ionic_lif *lif) 659 { 660 struct device *dev = lif->ionic->dev; 661 unsigned int flags; 662 int err; 663 664 flags = IONIC_QCQ_F_INTR; 665 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags, 666 IONIC_ADMINQ_LENGTH, 667 sizeof(struct ionic_admin_cmd), 668 sizeof(struct ionic_admin_comp), 669 0, lif->kern_pid, &lif->adminqcq); 670 if (err) 671 return err; 672 ionic_debugfs_add_qcq(lif, lif->adminqcq); 673 674 if (lif->ionic->nnqs_per_lif) { 675 flags = IONIC_QCQ_F_NOTIFYQ; 676 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq", 677 flags, IONIC_NOTIFYQ_LENGTH, 678 sizeof(struct ionic_notifyq_cmd), 679 sizeof(union ionic_notifyq_comp), 680 0, lif->kern_pid, &lif->notifyqcq); 681 if (err) 682 goto err_out; 683 ionic_debugfs_add_qcq(lif, lif->notifyqcq); 684 685 /* Let the notifyq ride on the adminq interrupt */ 686 ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq); 687 } 688 689 err = -ENOMEM; 690 lif->txqcqs = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif, 691 sizeof(*lif->txqcqs), GFP_KERNEL); 692 if (!lif->txqcqs) 693 goto err_out; 694 lif->rxqcqs = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif, 695 sizeof(*lif->rxqcqs), GFP_KERNEL); 696 if (!lif->rxqcqs) 697 goto err_out; 698 699 lif->txqstats = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif + 1, 700 sizeof(*lif->txqstats), GFP_KERNEL); 701 if (!lif->txqstats) 702 goto err_out; 703 lif->rxqstats = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif + 1, 704 sizeof(*lif->rxqstats), GFP_KERNEL); 705 if (!lif->rxqstats) 706 goto err_out; 707 708 return 0; 709 710 err_out: 711 ionic_qcqs_free(lif); 712 return err; 713 } 714 715 static void ionic_qcq_sanitize(struct ionic_qcq *qcq) 716 { 717 qcq->q.tail_idx = 0; 718 qcq->q.head_idx = 0; 719 qcq->cq.tail_idx = 0; 720 qcq->cq.done_color = 1; 721 memset(qcq->q_base, 0, qcq->q_size); 722 memset(qcq->cq_base, 0, qcq->cq_size); 723 memset(qcq->sg_base, 0, qcq->sg_size); 724 } 725 726 static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 727 { 728 struct device *dev = lif->ionic->dev; 729 struct ionic_queue *q = &qcq->q; 730 struct ionic_cq *cq = &qcq->cq; 731 struct ionic_admin_ctx ctx = { 732 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 733 .cmd.q_init = { 734 .opcode = IONIC_CMD_Q_INIT, 735 .lif_index = cpu_to_le16(lif->index), 736 .type = q->type, 737 .ver = lif->qtype_info[q->type].version, 738 .index = cpu_to_le32(q->index), 739 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 740 IONIC_QINIT_F_SG), 741 .pid = cpu_to_le16(q->pid), 742 .ring_size = ilog2(q->num_descs), 743 .ring_base = cpu_to_le64(q->base_pa), 744 .cq_ring_base = cpu_to_le64(cq->base_pa), 745 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 746 .features = cpu_to_le64(q->features), 747 }, 748 }; 749 unsigned int intr_index; 750 int err; 751 752 intr_index = qcq->intr.index; 753 754 ctx.cmd.q_init.intr_index = cpu_to_le16(intr_index); 755 756 dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid); 757 dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index); 758 dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 759 dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 760 dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 761 dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver); 762 dev_dbg(dev, "txq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 763 764 ionic_qcq_sanitize(qcq); 765 766 err = ionic_adminq_post_wait(lif, &ctx); 767 if (err) 768 return err; 769 770 q->hw_type = ctx.comp.q_init.hw_type; 771 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 772 q->dbval = IONIC_DBELL_QID(q->hw_index); 773 774 dev_dbg(dev, "txq->hw_type %d\n", q->hw_type); 775 dev_dbg(dev, "txq->hw_index %d\n", q->hw_index); 776 777 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 778 netif_napi_add(lif->netdev, &qcq->napi, ionic_tx_napi, 779 NAPI_POLL_WEIGHT); 780 781 qcq->flags |= IONIC_QCQ_F_INITED; 782 783 return 0; 784 } 785 786 static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 787 { 788 struct device *dev = lif->ionic->dev; 789 struct ionic_queue *q = &qcq->q; 790 struct ionic_cq *cq = &qcq->cq; 791 struct ionic_admin_ctx ctx = { 792 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 793 .cmd.q_init = { 794 .opcode = IONIC_CMD_Q_INIT, 795 .lif_index = cpu_to_le16(lif->index), 796 .type = q->type, 797 .ver = lif->qtype_info[q->type].version, 798 .index = cpu_to_le32(q->index), 799 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 800 IONIC_QINIT_F_SG), 801 .intr_index = cpu_to_le16(cq->bound_intr->index), 802 .pid = cpu_to_le16(q->pid), 803 .ring_size = ilog2(q->num_descs), 804 .ring_base = cpu_to_le64(q->base_pa), 805 .cq_ring_base = cpu_to_le64(cq->base_pa), 806 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 807 .features = cpu_to_le64(q->features), 808 }, 809 }; 810 int err; 811 812 dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid); 813 dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index); 814 dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 815 dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 816 dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 817 dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver); 818 dev_dbg(dev, "rxq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 819 820 ionic_qcq_sanitize(qcq); 821 822 err = ionic_adminq_post_wait(lif, &ctx); 823 if (err) 824 return err; 825 826 q->hw_type = ctx.comp.q_init.hw_type; 827 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 828 q->dbval = IONIC_DBELL_QID(q->hw_index); 829 830 dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type); 831 dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index); 832 833 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 834 netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi, 835 NAPI_POLL_WEIGHT); 836 else 837 netif_napi_add(lif->netdev, &qcq->napi, ionic_txrx_napi, 838 NAPI_POLL_WEIGHT); 839 840 qcq->flags |= IONIC_QCQ_F_INITED; 841 842 return 0; 843 } 844 845 int ionic_lif_create_hwstamp_txq(struct ionic_lif *lif) 846 { 847 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz; 848 unsigned int txq_i, flags; 849 struct ionic_qcq *txq; 850 u64 features; 851 int err; 852 853 if (lif->hwstamp_txq) 854 return 0; 855 856 features = IONIC_Q_F_2X_CQ_DESC | IONIC_TXQ_F_HWSTAMP; 857 858 num_desc = IONIC_MIN_TXRX_DESC; 859 desc_sz = sizeof(struct ionic_txq_desc); 860 comp_sz = 2 * sizeof(struct ionic_txq_comp); 861 862 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 863 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == sizeof(struct ionic_txq_sg_desc_v1)) 864 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 865 else 866 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 867 868 txq_i = lif->ionic->ntxqs_per_lif; 869 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 870 871 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, txq_i, "hwstamp_tx", flags, 872 num_desc, desc_sz, comp_sz, sg_desc_sz, 873 lif->kern_pid, &txq); 874 if (err) 875 goto err_qcq_alloc; 876 877 txq->q.features = features; 878 879 ionic_link_qcq_interrupts(lif->adminqcq, txq); 880 ionic_debugfs_add_qcq(lif, txq); 881 882 lif->hwstamp_txq = txq; 883 884 if (netif_running(lif->netdev)) { 885 err = ionic_lif_txq_init(lif, txq); 886 if (err) 887 goto err_qcq_init; 888 889 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 890 err = ionic_qcq_enable(txq); 891 if (err) 892 goto err_qcq_enable; 893 } 894 } 895 896 return 0; 897 898 err_qcq_enable: 899 ionic_lif_qcq_deinit(lif, txq); 900 err_qcq_init: 901 lif->hwstamp_txq = NULL; 902 ionic_debugfs_del_qcq(txq); 903 ionic_qcq_free(lif, txq); 904 devm_kfree(lif->ionic->dev, txq); 905 err_qcq_alloc: 906 return err; 907 } 908 909 int ionic_lif_create_hwstamp_rxq(struct ionic_lif *lif) 910 { 911 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz; 912 unsigned int rxq_i, flags; 913 struct ionic_qcq *rxq; 914 u64 features; 915 int err; 916 917 if (lif->hwstamp_rxq) 918 return 0; 919 920 features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP; 921 922 num_desc = IONIC_MIN_TXRX_DESC; 923 desc_sz = sizeof(struct ionic_rxq_desc); 924 comp_sz = 2 * sizeof(struct ionic_rxq_comp); 925 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 926 927 rxq_i = lif->ionic->nrxqs_per_lif; 928 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG; 929 930 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, rxq_i, "hwstamp_rx", flags, 931 num_desc, desc_sz, comp_sz, sg_desc_sz, 932 lif->kern_pid, &rxq); 933 if (err) 934 goto err_qcq_alloc; 935 936 rxq->q.features = features; 937 938 ionic_link_qcq_interrupts(lif->adminqcq, rxq); 939 ionic_debugfs_add_qcq(lif, rxq); 940 941 lif->hwstamp_rxq = rxq; 942 943 if (netif_running(lif->netdev)) { 944 err = ionic_lif_rxq_init(lif, rxq); 945 if (err) 946 goto err_qcq_init; 947 948 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 949 ionic_rx_fill(&rxq->q); 950 err = ionic_qcq_enable(rxq); 951 if (err) 952 goto err_qcq_enable; 953 } 954 } 955 956 return 0; 957 958 err_qcq_enable: 959 ionic_lif_qcq_deinit(lif, rxq); 960 err_qcq_init: 961 lif->hwstamp_rxq = NULL; 962 ionic_debugfs_del_qcq(rxq); 963 ionic_qcq_free(lif, rxq); 964 devm_kfree(lif->ionic->dev, rxq); 965 err_qcq_alloc: 966 return err; 967 } 968 969 int ionic_lif_config_hwstamp_rxq_all(struct ionic_lif *lif, bool rx_all) 970 { 971 struct ionic_queue_params qparam; 972 973 ionic_init_queue_params(lif, &qparam); 974 975 if (rx_all) 976 qparam.rxq_features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP; 977 else 978 qparam.rxq_features = 0; 979 980 /* if we're not running, just set the values and return */ 981 if (!netif_running(lif->netdev)) { 982 lif->rxq_features = qparam.rxq_features; 983 return 0; 984 } 985 986 return ionic_reconfigure_queues(lif, &qparam); 987 } 988 989 int ionic_lif_set_hwstamp_txmode(struct ionic_lif *lif, u16 txstamp_mode) 990 { 991 struct ionic_admin_ctx ctx = { 992 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 993 .cmd.lif_setattr = { 994 .opcode = IONIC_CMD_LIF_SETATTR, 995 .index = cpu_to_le16(lif->index), 996 .attr = IONIC_LIF_ATTR_TXSTAMP, 997 .txstamp_mode = cpu_to_le16(txstamp_mode), 998 }, 999 }; 1000 1001 return ionic_adminq_post_wait(lif, &ctx); 1002 } 1003 1004 static void ionic_lif_del_hwstamp_rxfilt(struct ionic_lif *lif) 1005 { 1006 struct ionic_admin_ctx ctx = { 1007 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1008 .cmd.rx_filter_del = { 1009 .opcode = IONIC_CMD_RX_FILTER_DEL, 1010 .lif_index = cpu_to_le16(lif->index), 1011 }, 1012 }; 1013 struct ionic_rx_filter *f; 1014 u32 filter_id; 1015 int err; 1016 1017 spin_lock_bh(&lif->rx_filters.lock); 1018 1019 f = ionic_rx_filter_rxsteer(lif); 1020 if (!f) { 1021 spin_unlock_bh(&lif->rx_filters.lock); 1022 return; 1023 } 1024 1025 filter_id = f->filter_id; 1026 ionic_rx_filter_free(lif, f); 1027 1028 spin_unlock_bh(&lif->rx_filters.lock); 1029 1030 netdev_dbg(lif->netdev, "rx_filter del RXSTEER (id %d)\n", filter_id); 1031 1032 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(filter_id); 1033 1034 err = ionic_adminq_post_wait(lif, &ctx); 1035 if (err && err != -EEXIST) 1036 netdev_dbg(lif->netdev, "failed to delete rx_filter RXSTEER (id %d)\n", filter_id); 1037 } 1038 1039 static int ionic_lif_add_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class) 1040 { 1041 struct ionic_admin_ctx ctx = { 1042 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1043 .cmd.rx_filter_add = { 1044 .opcode = IONIC_CMD_RX_FILTER_ADD, 1045 .lif_index = cpu_to_le16(lif->index), 1046 .match = cpu_to_le16(IONIC_RX_FILTER_STEER_PKTCLASS), 1047 .pkt_class = cpu_to_le64(pkt_class), 1048 }, 1049 }; 1050 u8 qtype; 1051 u32 qid; 1052 int err; 1053 1054 if (!lif->hwstamp_rxq) 1055 return -EINVAL; 1056 1057 qtype = lif->hwstamp_rxq->q.type; 1058 ctx.cmd.rx_filter_add.qtype = qtype; 1059 1060 qid = lif->hwstamp_rxq->q.index; 1061 ctx.cmd.rx_filter_add.qid = cpu_to_le32(qid); 1062 1063 netdev_dbg(lif->netdev, "rx_filter add RXSTEER\n"); 1064 err = ionic_adminq_post_wait(lif, &ctx); 1065 if (err && err != -EEXIST) 1066 return err; 1067 1068 spin_lock_bh(&lif->rx_filters.lock); 1069 err = ionic_rx_filter_save(lif, 0, qid, 0, &ctx, IONIC_FILTER_STATE_SYNCED); 1070 spin_unlock_bh(&lif->rx_filters.lock); 1071 1072 return err; 1073 } 1074 1075 int ionic_lif_set_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class) 1076 { 1077 ionic_lif_del_hwstamp_rxfilt(lif); 1078 1079 if (!pkt_class) 1080 return 0; 1081 1082 return ionic_lif_add_hwstamp_rxfilt(lif, pkt_class); 1083 } 1084 1085 static bool ionic_notifyq_service(struct ionic_cq *cq, 1086 struct ionic_cq_info *cq_info) 1087 { 1088 union ionic_notifyq_comp *comp = cq_info->cq_desc; 1089 struct ionic_deferred_work *work; 1090 struct net_device *netdev; 1091 struct ionic_queue *q; 1092 struct ionic_lif *lif; 1093 u64 eid; 1094 1095 q = cq->bound_q; 1096 lif = q->info[0].cb_arg; 1097 netdev = lif->netdev; 1098 eid = le64_to_cpu(comp->event.eid); 1099 1100 /* Have we run out of new completions to process? */ 1101 if ((s64)(eid - lif->last_eid) <= 0) 1102 return false; 1103 1104 lif->last_eid = eid; 1105 1106 dev_dbg(lif->ionic->dev, "notifyq event:\n"); 1107 dynamic_hex_dump("event ", DUMP_PREFIX_OFFSET, 16, 1, 1108 comp, sizeof(*comp), true); 1109 1110 switch (le16_to_cpu(comp->event.ecode)) { 1111 case IONIC_EVENT_LINK_CHANGE: 1112 ionic_link_status_check_request(lif, CAN_NOT_SLEEP); 1113 break; 1114 case IONIC_EVENT_RESET: 1115 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1116 if (!work) { 1117 netdev_err(lif->netdev, "Reset event dropped\n"); 1118 } else { 1119 work->type = IONIC_DW_TYPE_LIF_RESET; 1120 ionic_lif_deferred_enqueue(&lif->deferred, work); 1121 } 1122 break; 1123 default: 1124 netdev_warn(netdev, "Notifyq event ecode=%d eid=%lld\n", 1125 comp->event.ecode, eid); 1126 break; 1127 } 1128 1129 return true; 1130 } 1131 1132 static bool ionic_adminq_service(struct ionic_cq *cq, 1133 struct ionic_cq_info *cq_info) 1134 { 1135 struct ionic_admin_comp *comp = cq_info->cq_desc; 1136 1137 if (!color_match(comp->color, cq->done_color)) 1138 return false; 1139 1140 ionic_q_service(cq->bound_q, cq_info, le16_to_cpu(comp->comp_index)); 1141 1142 return true; 1143 } 1144 1145 static int ionic_adminq_napi(struct napi_struct *napi, int budget) 1146 { 1147 struct ionic_intr_info *intr = napi_to_cq(napi)->bound_intr; 1148 struct ionic_lif *lif = napi_to_cq(napi)->lif; 1149 struct ionic_dev *idev = &lif->ionic->idev; 1150 unsigned long irqflags; 1151 unsigned int flags = 0; 1152 int rx_work = 0; 1153 int tx_work = 0; 1154 int n_work = 0; 1155 int a_work = 0; 1156 int work_done; 1157 int credits; 1158 1159 if (lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED) 1160 n_work = ionic_cq_service(&lif->notifyqcq->cq, budget, 1161 ionic_notifyq_service, NULL, NULL); 1162 1163 spin_lock_irqsave(&lif->adminq_lock, irqflags); 1164 if (lif->adminqcq && lif->adminqcq->flags & IONIC_QCQ_F_INITED) 1165 a_work = ionic_cq_service(&lif->adminqcq->cq, budget, 1166 ionic_adminq_service, NULL, NULL); 1167 spin_unlock_irqrestore(&lif->adminq_lock, irqflags); 1168 1169 if (lif->hwstamp_rxq) 1170 rx_work = ionic_cq_service(&lif->hwstamp_rxq->cq, budget, 1171 ionic_rx_service, NULL, NULL); 1172 1173 if (lif->hwstamp_txq) 1174 tx_work = ionic_cq_service(&lif->hwstamp_txq->cq, budget, 1175 ionic_tx_service, NULL, NULL); 1176 1177 work_done = max(max(n_work, a_work), max(rx_work, tx_work)); 1178 if (work_done < budget && napi_complete_done(napi, work_done)) { 1179 flags |= IONIC_INTR_CRED_UNMASK; 1180 intr->rearm_count++; 1181 } 1182 1183 if (work_done || flags) { 1184 flags |= IONIC_INTR_CRED_RESET_COALESCE; 1185 credits = n_work + a_work + rx_work + tx_work; 1186 ionic_intr_credits(idev->intr_ctrl, intr->index, credits, flags); 1187 } 1188 1189 return work_done; 1190 } 1191 1192 void ionic_get_stats64(struct net_device *netdev, 1193 struct rtnl_link_stats64 *ns) 1194 { 1195 struct ionic_lif *lif = netdev_priv(netdev); 1196 struct ionic_lif_stats *ls; 1197 1198 memset(ns, 0, sizeof(*ns)); 1199 ls = &lif->info->stats; 1200 1201 ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) + 1202 le64_to_cpu(ls->rx_mcast_packets) + 1203 le64_to_cpu(ls->rx_bcast_packets); 1204 1205 ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) + 1206 le64_to_cpu(ls->tx_mcast_packets) + 1207 le64_to_cpu(ls->tx_bcast_packets); 1208 1209 ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) + 1210 le64_to_cpu(ls->rx_mcast_bytes) + 1211 le64_to_cpu(ls->rx_bcast_bytes); 1212 1213 ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) + 1214 le64_to_cpu(ls->tx_mcast_bytes) + 1215 le64_to_cpu(ls->tx_bcast_bytes); 1216 1217 ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) + 1218 le64_to_cpu(ls->rx_mcast_drop_packets) + 1219 le64_to_cpu(ls->rx_bcast_drop_packets); 1220 1221 ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) + 1222 le64_to_cpu(ls->tx_mcast_drop_packets) + 1223 le64_to_cpu(ls->tx_bcast_drop_packets); 1224 1225 ns->multicast = le64_to_cpu(ls->rx_mcast_packets); 1226 1227 ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty); 1228 1229 ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) + 1230 le64_to_cpu(ls->rx_queue_disabled) + 1231 le64_to_cpu(ls->rx_desc_fetch_error) + 1232 le64_to_cpu(ls->rx_desc_data_error); 1233 1234 ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) + 1235 le64_to_cpu(ls->tx_queue_disabled) + 1236 le64_to_cpu(ls->tx_desc_fetch_error) + 1237 le64_to_cpu(ls->tx_desc_data_error); 1238 1239 ns->rx_errors = ns->rx_over_errors + 1240 ns->rx_missed_errors; 1241 1242 ns->tx_errors = ns->tx_aborted_errors; 1243 } 1244 1245 static int ionic_addr_add(struct net_device *netdev, const u8 *addr) 1246 { 1247 return ionic_lif_list_addr(netdev_priv(netdev), addr, ADD_ADDR); 1248 } 1249 1250 static int ionic_addr_del(struct net_device *netdev, const u8 *addr) 1251 { 1252 return ionic_lif_list_addr(netdev_priv(netdev), addr, DEL_ADDR); 1253 } 1254 1255 void ionic_lif_rx_mode(struct ionic_lif *lif) 1256 { 1257 struct net_device *netdev = lif->netdev; 1258 unsigned int nfilters; 1259 unsigned int nd_flags; 1260 char buf[128]; 1261 u16 rx_mode; 1262 int i; 1263 #define REMAIN(__x) (sizeof(buf) - (__x)) 1264 1265 mutex_lock(&lif->config_lock); 1266 1267 /* grab the flags once for local use */ 1268 nd_flags = netdev->flags; 1269 1270 rx_mode = IONIC_RX_MODE_F_UNICAST; 1271 rx_mode |= (nd_flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0; 1272 rx_mode |= (nd_flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0; 1273 rx_mode |= (nd_flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0; 1274 rx_mode |= (nd_flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0; 1275 1276 /* sync the filters */ 1277 ionic_rx_filter_sync(lif); 1278 1279 /* check for overflow state 1280 * if so, we track that we overflowed and enable NIC PROMISC 1281 * else if the overflow is set and not needed 1282 * we remove our overflow flag and check the netdev flags 1283 * to see if we can disable NIC PROMISC 1284 */ 1285 nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters); 1286 1287 if (((lif->nucast + lif->nmcast) >= nfilters) || 1288 (lif->max_vlans && lif->nvlans >= lif->max_vlans)) { 1289 rx_mode |= IONIC_RX_MODE_F_PROMISC; 1290 rx_mode |= IONIC_RX_MODE_F_ALLMULTI; 1291 } else { 1292 if (!(nd_flags & IFF_PROMISC)) 1293 rx_mode &= ~IONIC_RX_MODE_F_PROMISC; 1294 if (!(nd_flags & IFF_ALLMULTI)) 1295 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI; 1296 } 1297 1298 i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:", 1299 lif->rx_mode, rx_mode); 1300 if (rx_mode & IONIC_RX_MODE_F_UNICAST) 1301 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST"); 1302 if (rx_mode & IONIC_RX_MODE_F_MULTICAST) 1303 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST"); 1304 if (rx_mode & IONIC_RX_MODE_F_BROADCAST) 1305 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST"); 1306 if (rx_mode & IONIC_RX_MODE_F_PROMISC) 1307 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC"); 1308 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI) 1309 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI"); 1310 if (rx_mode & IONIC_RX_MODE_F_RDMA_SNIFFER) 1311 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_RDMA_SNIFFER"); 1312 netdev_dbg(netdev, "lif%d %s\n", lif->index, buf); 1313 1314 if (lif->rx_mode != rx_mode) { 1315 struct ionic_admin_ctx ctx = { 1316 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1317 .cmd.rx_mode_set = { 1318 .opcode = IONIC_CMD_RX_MODE_SET, 1319 .lif_index = cpu_to_le16(lif->index), 1320 }, 1321 }; 1322 int err; 1323 1324 ctx.cmd.rx_mode_set.rx_mode = cpu_to_le16(rx_mode); 1325 err = ionic_adminq_post_wait(lif, &ctx); 1326 if (err) 1327 netdev_warn(netdev, "set rx_mode 0x%04x failed: %d\n", 1328 rx_mode, err); 1329 else 1330 lif->rx_mode = rx_mode; 1331 } 1332 1333 mutex_unlock(&lif->config_lock); 1334 } 1335 1336 static void ionic_ndo_set_rx_mode(struct net_device *netdev) 1337 { 1338 struct ionic_lif *lif = netdev_priv(netdev); 1339 struct ionic_deferred_work *work; 1340 1341 /* Sync the kernel filter list with the driver filter list */ 1342 __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del); 1343 __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del); 1344 1345 /* Shove off the rest of the rxmode work to the work task 1346 * which will include syncing the filters to the firmware. 1347 */ 1348 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1349 if (!work) { 1350 netdev_err(lif->netdev, "rxmode change dropped\n"); 1351 return; 1352 } 1353 work->type = IONIC_DW_TYPE_RX_MODE; 1354 netdev_dbg(lif->netdev, "deferred: rx_mode\n"); 1355 ionic_lif_deferred_enqueue(&lif->deferred, work); 1356 } 1357 1358 static __le64 ionic_netdev_features_to_nic(netdev_features_t features) 1359 { 1360 u64 wanted = 0; 1361 1362 if (features & NETIF_F_HW_VLAN_CTAG_TX) 1363 wanted |= IONIC_ETH_HW_VLAN_TX_TAG; 1364 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1365 wanted |= IONIC_ETH_HW_VLAN_RX_STRIP; 1366 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1367 wanted |= IONIC_ETH_HW_VLAN_RX_FILTER; 1368 if (features & NETIF_F_RXHASH) 1369 wanted |= IONIC_ETH_HW_RX_HASH; 1370 if (features & NETIF_F_RXCSUM) 1371 wanted |= IONIC_ETH_HW_RX_CSUM; 1372 if (features & NETIF_F_SG) 1373 wanted |= IONIC_ETH_HW_TX_SG; 1374 if (features & NETIF_F_HW_CSUM) 1375 wanted |= IONIC_ETH_HW_TX_CSUM; 1376 if (features & NETIF_F_TSO) 1377 wanted |= IONIC_ETH_HW_TSO; 1378 if (features & NETIF_F_TSO6) 1379 wanted |= IONIC_ETH_HW_TSO_IPV6; 1380 if (features & NETIF_F_TSO_ECN) 1381 wanted |= IONIC_ETH_HW_TSO_ECN; 1382 if (features & NETIF_F_GSO_GRE) 1383 wanted |= IONIC_ETH_HW_TSO_GRE; 1384 if (features & NETIF_F_GSO_GRE_CSUM) 1385 wanted |= IONIC_ETH_HW_TSO_GRE_CSUM; 1386 if (features & NETIF_F_GSO_IPXIP4) 1387 wanted |= IONIC_ETH_HW_TSO_IPXIP4; 1388 if (features & NETIF_F_GSO_IPXIP6) 1389 wanted |= IONIC_ETH_HW_TSO_IPXIP6; 1390 if (features & NETIF_F_GSO_UDP_TUNNEL) 1391 wanted |= IONIC_ETH_HW_TSO_UDP; 1392 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) 1393 wanted |= IONIC_ETH_HW_TSO_UDP_CSUM; 1394 1395 return cpu_to_le64(wanted); 1396 } 1397 1398 static int ionic_set_nic_features(struct ionic_lif *lif, 1399 netdev_features_t features) 1400 { 1401 struct device *dev = lif->ionic->dev; 1402 struct ionic_admin_ctx ctx = { 1403 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1404 .cmd.lif_setattr = { 1405 .opcode = IONIC_CMD_LIF_SETATTR, 1406 .index = cpu_to_le16(lif->index), 1407 .attr = IONIC_LIF_ATTR_FEATURES, 1408 }, 1409 }; 1410 u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG | 1411 IONIC_ETH_HW_VLAN_RX_STRIP | 1412 IONIC_ETH_HW_VLAN_RX_FILTER; 1413 u64 old_hw_features; 1414 int err; 1415 1416 ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features); 1417 1418 if (lif->phc) 1419 ctx.cmd.lif_setattr.features |= cpu_to_le64(IONIC_ETH_HW_TIMESTAMP); 1420 1421 err = ionic_adminq_post_wait(lif, &ctx); 1422 if (err) 1423 return err; 1424 1425 old_hw_features = lif->hw_features; 1426 lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features & 1427 ctx.comp.lif_setattr.features); 1428 1429 if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH) 1430 ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1431 1432 if ((vlan_flags & features) && 1433 !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features))) 1434 dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n"); 1435 1436 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1437 dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n"); 1438 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1439 dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n"); 1440 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1441 dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n"); 1442 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1443 dev_dbg(dev, "feature ETH_HW_RX_HASH\n"); 1444 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1445 dev_dbg(dev, "feature ETH_HW_TX_SG\n"); 1446 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1447 dev_dbg(dev, "feature ETH_HW_TX_CSUM\n"); 1448 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1449 dev_dbg(dev, "feature ETH_HW_RX_CSUM\n"); 1450 if (lif->hw_features & IONIC_ETH_HW_TSO) 1451 dev_dbg(dev, "feature ETH_HW_TSO\n"); 1452 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1453 dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n"); 1454 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1455 dev_dbg(dev, "feature ETH_HW_TSO_ECN\n"); 1456 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1457 dev_dbg(dev, "feature ETH_HW_TSO_GRE\n"); 1458 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1459 dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n"); 1460 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1461 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n"); 1462 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1463 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n"); 1464 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1465 dev_dbg(dev, "feature ETH_HW_TSO_UDP\n"); 1466 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1467 dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n"); 1468 if (lif->hw_features & IONIC_ETH_HW_TIMESTAMP) 1469 dev_dbg(dev, "feature ETH_HW_TIMESTAMP\n"); 1470 1471 return 0; 1472 } 1473 1474 static int ionic_init_nic_features(struct ionic_lif *lif) 1475 { 1476 struct net_device *netdev = lif->netdev; 1477 netdev_features_t features; 1478 int err; 1479 1480 /* set up what we expect to support by default */ 1481 features = NETIF_F_HW_VLAN_CTAG_TX | 1482 NETIF_F_HW_VLAN_CTAG_RX | 1483 NETIF_F_HW_VLAN_CTAG_FILTER | 1484 NETIF_F_SG | 1485 NETIF_F_HW_CSUM | 1486 NETIF_F_RXCSUM | 1487 NETIF_F_TSO | 1488 NETIF_F_TSO6 | 1489 NETIF_F_TSO_ECN; 1490 1491 if (lif->nxqs > 1) 1492 features |= NETIF_F_RXHASH; 1493 1494 err = ionic_set_nic_features(lif, features); 1495 if (err) 1496 return err; 1497 1498 /* tell the netdev what we actually can support */ 1499 netdev->features |= NETIF_F_HIGHDMA; 1500 1501 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1502 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 1503 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1504 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 1505 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1506 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1507 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1508 netdev->hw_features |= NETIF_F_RXHASH; 1509 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1510 netdev->hw_features |= NETIF_F_SG; 1511 1512 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1513 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 1514 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1515 netdev->hw_enc_features |= NETIF_F_RXCSUM; 1516 if (lif->hw_features & IONIC_ETH_HW_TSO) 1517 netdev->hw_enc_features |= NETIF_F_TSO; 1518 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1519 netdev->hw_enc_features |= NETIF_F_TSO6; 1520 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1521 netdev->hw_enc_features |= NETIF_F_TSO_ECN; 1522 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1523 netdev->hw_enc_features |= NETIF_F_GSO_GRE; 1524 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1525 netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM; 1526 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1527 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4; 1528 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1529 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6; 1530 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1531 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL; 1532 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1533 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 1534 1535 netdev->hw_features |= netdev->hw_enc_features; 1536 netdev->features |= netdev->hw_features; 1537 netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES; 1538 1539 netdev->priv_flags |= IFF_UNICAST_FLT | 1540 IFF_LIVE_ADDR_CHANGE; 1541 1542 return 0; 1543 } 1544 1545 static int ionic_set_features(struct net_device *netdev, 1546 netdev_features_t features) 1547 { 1548 struct ionic_lif *lif = netdev_priv(netdev); 1549 int err; 1550 1551 netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n", 1552 __func__, (u64)lif->netdev->features, (u64)features); 1553 1554 err = ionic_set_nic_features(lif, features); 1555 1556 return err; 1557 } 1558 1559 static int ionic_set_mac_address(struct net_device *netdev, void *sa) 1560 { 1561 struct sockaddr *addr = sa; 1562 u8 *mac; 1563 int err; 1564 1565 mac = (u8 *)addr->sa_data; 1566 if (ether_addr_equal(netdev->dev_addr, mac)) 1567 return 0; 1568 1569 err = eth_prepare_mac_addr_change(netdev, addr); 1570 if (err) 1571 return err; 1572 1573 if (!is_zero_ether_addr(netdev->dev_addr)) { 1574 netdev_info(netdev, "deleting mac addr %pM\n", 1575 netdev->dev_addr); 1576 ionic_lif_addr_del(netdev_priv(netdev), netdev->dev_addr); 1577 } 1578 1579 eth_commit_mac_addr_change(netdev, addr); 1580 netdev_info(netdev, "updating mac addr %pM\n", mac); 1581 1582 return ionic_lif_addr_add(netdev_priv(netdev), mac); 1583 } 1584 1585 static void ionic_stop_queues_reconfig(struct ionic_lif *lif) 1586 { 1587 /* Stop and clean the queues before reconfiguration */ 1588 netif_device_detach(lif->netdev); 1589 ionic_stop_queues(lif); 1590 ionic_txrx_deinit(lif); 1591 } 1592 1593 static int ionic_start_queues_reconfig(struct ionic_lif *lif) 1594 { 1595 int err; 1596 1597 /* Re-init the queues after reconfiguration */ 1598 1599 /* The only way txrx_init can fail here is if communication 1600 * with FW is suddenly broken. There's not much we can do 1601 * at this point - error messages have already been printed, 1602 * so we can continue on and the user can eventually do a 1603 * DOWN and UP to try to reset and clear the issue. 1604 */ 1605 err = ionic_txrx_init(lif); 1606 ionic_link_status_check_request(lif, CAN_NOT_SLEEP); 1607 netif_device_attach(lif->netdev); 1608 1609 return err; 1610 } 1611 1612 static int ionic_change_mtu(struct net_device *netdev, int new_mtu) 1613 { 1614 struct ionic_lif *lif = netdev_priv(netdev); 1615 struct ionic_admin_ctx ctx = { 1616 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1617 .cmd.lif_setattr = { 1618 .opcode = IONIC_CMD_LIF_SETATTR, 1619 .index = cpu_to_le16(lif->index), 1620 .attr = IONIC_LIF_ATTR_MTU, 1621 .mtu = cpu_to_le32(new_mtu), 1622 }, 1623 }; 1624 int err; 1625 1626 err = ionic_adminq_post_wait(lif, &ctx); 1627 if (err) 1628 return err; 1629 1630 /* if we're not running, nothing more to do */ 1631 if (!netif_running(netdev)) { 1632 netdev->mtu = new_mtu; 1633 return 0; 1634 } 1635 1636 mutex_lock(&lif->queue_lock); 1637 ionic_stop_queues_reconfig(lif); 1638 netdev->mtu = new_mtu; 1639 err = ionic_start_queues_reconfig(lif); 1640 mutex_unlock(&lif->queue_lock); 1641 1642 return err; 1643 } 1644 1645 static void ionic_tx_timeout_work(struct work_struct *ws) 1646 { 1647 struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work); 1648 1649 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 1650 return; 1651 1652 /* if we were stopped before this scheduled job was launched, 1653 * don't bother the queues as they are already stopped. 1654 */ 1655 if (!netif_running(lif->netdev)) 1656 return; 1657 1658 mutex_lock(&lif->queue_lock); 1659 ionic_stop_queues_reconfig(lif); 1660 ionic_start_queues_reconfig(lif); 1661 mutex_unlock(&lif->queue_lock); 1662 } 1663 1664 static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1665 { 1666 struct ionic_lif *lif = netdev_priv(netdev); 1667 1668 netdev_info(lif->netdev, "Tx Timeout triggered - txq %d\n", txqueue); 1669 schedule_work(&lif->tx_timeout_work); 1670 } 1671 1672 static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, 1673 u16 vid) 1674 { 1675 struct ionic_lif *lif = netdev_priv(netdev); 1676 int err; 1677 1678 err = ionic_lif_vlan_add(lif, vid); 1679 if (err) 1680 return err; 1681 1682 ionic_lif_rx_mode(lif); 1683 1684 return 0; 1685 } 1686 1687 static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, 1688 u16 vid) 1689 { 1690 struct ionic_lif *lif = netdev_priv(netdev); 1691 int err; 1692 1693 err = ionic_lif_vlan_del(lif, vid); 1694 if (err) 1695 return err; 1696 1697 ionic_lif_rx_mode(lif); 1698 1699 return 0; 1700 } 1701 1702 int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types, 1703 const u8 *key, const u32 *indir) 1704 { 1705 struct ionic_admin_ctx ctx = { 1706 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1707 .cmd.lif_setattr = { 1708 .opcode = IONIC_CMD_LIF_SETATTR, 1709 .attr = IONIC_LIF_ATTR_RSS, 1710 .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa), 1711 }, 1712 }; 1713 unsigned int i, tbl_sz; 1714 1715 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) { 1716 lif->rss_types = types; 1717 ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types); 1718 } 1719 1720 if (key) 1721 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE); 1722 1723 if (indir) { 1724 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1725 for (i = 0; i < tbl_sz; i++) 1726 lif->rss_ind_tbl[i] = indir[i]; 1727 } 1728 1729 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key, 1730 IONIC_RSS_HASH_KEY_SIZE); 1731 1732 return ionic_adminq_post_wait(lif, &ctx); 1733 } 1734 1735 static int ionic_lif_rss_init(struct ionic_lif *lif) 1736 { 1737 unsigned int tbl_sz; 1738 unsigned int i; 1739 1740 lif->rss_types = IONIC_RSS_TYPE_IPV4 | 1741 IONIC_RSS_TYPE_IPV4_TCP | 1742 IONIC_RSS_TYPE_IPV4_UDP | 1743 IONIC_RSS_TYPE_IPV6 | 1744 IONIC_RSS_TYPE_IPV6_TCP | 1745 IONIC_RSS_TYPE_IPV6_UDP; 1746 1747 /* Fill indirection table with 'default' values */ 1748 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1749 for (i = 0; i < tbl_sz; i++) 1750 lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs); 1751 1752 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1753 } 1754 1755 static void ionic_lif_rss_deinit(struct ionic_lif *lif) 1756 { 1757 int tbl_sz; 1758 1759 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1760 memset(lif->rss_ind_tbl, 0, tbl_sz); 1761 memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE); 1762 1763 ionic_lif_rss_config(lif, 0x0, NULL, NULL); 1764 } 1765 1766 static void ionic_lif_quiesce(struct ionic_lif *lif) 1767 { 1768 struct ionic_admin_ctx ctx = { 1769 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1770 .cmd.lif_setattr = { 1771 .opcode = IONIC_CMD_LIF_SETATTR, 1772 .index = cpu_to_le16(lif->index), 1773 .attr = IONIC_LIF_ATTR_STATE, 1774 .state = IONIC_LIF_QUIESCE, 1775 }, 1776 }; 1777 int err; 1778 1779 err = ionic_adminq_post_wait(lif, &ctx); 1780 if (err) 1781 netdev_err(lif->netdev, "lif quiesce failed %d\n", err); 1782 } 1783 1784 static void ionic_txrx_disable(struct ionic_lif *lif) 1785 { 1786 unsigned int i; 1787 int err = 0; 1788 1789 if (lif->txqcqs) { 1790 for (i = 0; i < lif->nxqs; i++) 1791 err = ionic_qcq_disable(lif, lif->txqcqs[i], err); 1792 } 1793 1794 if (lif->hwstamp_txq) 1795 err = ionic_qcq_disable(lif, lif->hwstamp_txq, err); 1796 1797 if (lif->rxqcqs) { 1798 for (i = 0; i < lif->nxqs; i++) 1799 err = ionic_qcq_disable(lif, lif->rxqcqs[i], err); 1800 } 1801 1802 if (lif->hwstamp_rxq) 1803 err = ionic_qcq_disable(lif, lif->hwstamp_rxq, err); 1804 1805 ionic_lif_quiesce(lif); 1806 } 1807 1808 static void ionic_txrx_deinit(struct ionic_lif *lif) 1809 { 1810 unsigned int i; 1811 1812 if (lif->txqcqs) { 1813 for (i = 0; i < lif->nxqs && lif->txqcqs[i]; i++) { 1814 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 1815 ionic_tx_flush(&lif->txqcqs[i]->cq); 1816 ionic_tx_empty(&lif->txqcqs[i]->q); 1817 } 1818 } 1819 1820 if (lif->rxqcqs) { 1821 for (i = 0; i < lif->nxqs && lif->rxqcqs[i]; i++) { 1822 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 1823 ionic_rx_empty(&lif->rxqcqs[i]->q); 1824 } 1825 } 1826 lif->rx_mode = 0; 1827 1828 if (lif->hwstamp_txq) { 1829 ionic_lif_qcq_deinit(lif, lif->hwstamp_txq); 1830 ionic_tx_flush(&lif->hwstamp_txq->cq); 1831 ionic_tx_empty(&lif->hwstamp_txq->q); 1832 } 1833 1834 if (lif->hwstamp_rxq) { 1835 ionic_lif_qcq_deinit(lif, lif->hwstamp_rxq); 1836 ionic_rx_empty(&lif->hwstamp_rxq->q); 1837 } 1838 } 1839 1840 static void ionic_txrx_free(struct ionic_lif *lif) 1841 { 1842 unsigned int i; 1843 1844 if (lif->txqcqs) { 1845 for (i = 0; i < lif->ionic->ntxqs_per_lif && lif->txqcqs[i]; i++) { 1846 ionic_qcq_free(lif, lif->txqcqs[i]); 1847 devm_kfree(lif->ionic->dev, lif->txqcqs[i]); 1848 lif->txqcqs[i] = NULL; 1849 } 1850 } 1851 1852 if (lif->rxqcqs) { 1853 for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) { 1854 ionic_qcq_free(lif, lif->rxqcqs[i]); 1855 devm_kfree(lif->ionic->dev, lif->rxqcqs[i]); 1856 lif->rxqcqs[i] = NULL; 1857 } 1858 } 1859 1860 if (lif->hwstamp_txq) { 1861 ionic_qcq_free(lif, lif->hwstamp_txq); 1862 devm_kfree(lif->ionic->dev, lif->hwstamp_txq); 1863 lif->hwstamp_txq = NULL; 1864 } 1865 1866 if (lif->hwstamp_rxq) { 1867 ionic_qcq_free(lif, lif->hwstamp_rxq); 1868 devm_kfree(lif->ionic->dev, lif->hwstamp_rxq); 1869 lif->hwstamp_rxq = NULL; 1870 } 1871 } 1872 1873 static int ionic_txrx_alloc(struct ionic_lif *lif) 1874 { 1875 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz; 1876 unsigned int flags, i; 1877 int err = 0; 1878 1879 num_desc = lif->ntxq_descs; 1880 desc_sz = sizeof(struct ionic_txq_desc); 1881 comp_sz = sizeof(struct ionic_txq_comp); 1882 1883 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 1884 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 1885 sizeof(struct ionic_txq_sg_desc_v1)) 1886 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 1887 else 1888 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 1889 1890 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 1891 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 1892 flags |= IONIC_QCQ_F_INTR; 1893 for (i = 0; i < lif->nxqs; i++) { 1894 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 1895 num_desc, desc_sz, comp_sz, sg_desc_sz, 1896 lif->kern_pid, &lif->txqcqs[i]); 1897 if (err) 1898 goto err_out; 1899 1900 if (flags & IONIC_QCQ_F_INTR) { 1901 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 1902 lif->txqcqs[i]->intr.index, 1903 lif->tx_coalesce_hw); 1904 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 1905 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 1906 } 1907 1908 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 1909 } 1910 1911 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG | IONIC_QCQ_F_INTR; 1912 1913 num_desc = lif->nrxq_descs; 1914 desc_sz = sizeof(struct ionic_rxq_desc); 1915 comp_sz = sizeof(struct ionic_rxq_comp); 1916 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 1917 1918 if (lif->rxq_features & IONIC_Q_F_2X_CQ_DESC) 1919 comp_sz *= 2; 1920 1921 for (i = 0; i < lif->nxqs; i++) { 1922 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 1923 num_desc, desc_sz, comp_sz, sg_desc_sz, 1924 lif->kern_pid, &lif->rxqcqs[i]); 1925 if (err) 1926 goto err_out; 1927 1928 lif->rxqcqs[i]->q.features = lif->rxq_features; 1929 1930 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 1931 lif->rxqcqs[i]->intr.index, 1932 lif->rx_coalesce_hw); 1933 if (test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state)) 1934 lif->rxqcqs[i]->intr.dim_coal_hw = lif->rx_coalesce_hw; 1935 1936 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 1937 ionic_link_qcq_interrupts(lif->rxqcqs[i], 1938 lif->txqcqs[i]); 1939 1940 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 1941 } 1942 1943 return 0; 1944 1945 err_out: 1946 ionic_txrx_free(lif); 1947 1948 return err; 1949 } 1950 1951 static int ionic_txrx_init(struct ionic_lif *lif) 1952 { 1953 unsigned int i; 1954 int err; 1955 1956 for (i = 0; i < lif->nxqs; i++) { 1957 err = ionic_lif_txq_init(lif, lif->txqcqs[i]); 1958 if (err) 1959 goto err_out; 1960 1961 err = ionic_lif_rxq_init(lif, lif->rxqcqs[i]); 1962 if (err) { 1963 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 1964 goto err_out; 1965 } 1966 } 1967 1968 if (lif->netdev->features & NETIF_F_RXHASH) 1969 ionic_lif_rss_init(lif); 1970 1971 ionic_lif_rx_mode(lif); 1972 1973 return 0; 1974 1975 err_out: 1976 while (i--) { 1977 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 1978 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 1979 } 1980 1981 return err; 1982 } 1983 1984 static int ionic_txrx_enable(struct ionic_lif *lif) 1985 { 1986 int derr = 0; 1987 int i, err; 1988 1989 for (i = 0; i < lif->nxqs; i++) { 1990 if (!(lif->rxqcqs[i] && lif->txqcqs[i])) { 1991 dev_err(lif->ionic->dev, "%s: bad qcq %d\n", __func__, i); 1992 err = -ENXIO; 1993 goto err_out; 1994 } 1995 1996 ionic_rx_fill(&lif->rxqcqs[i]->q); 1997 err = ionic_qcq_enable(lif->rxqcqs[i]); 1998 if (err) 1999 goto err_out; 2000 2001 err = ionic_qcq_enable(lif->txqcqs[i]); 2002 if (err) { 2003 derr = ionic_qcq_disable(lif, lif->rxqcqs[i], err); 2004 goto err_out; 2005 } 2006 } 2007 2008 if (lif->hwstamp_rxq) { 2009 ionic_rx_fill(&lif->hwstamp_rxq->q); 2010 err = ionic_qcq_enable(lif->hwstamp_rxq); 2011 if (err) 2012 goto err_out_hwstamp_rx; 2013 } 2014 2015 if (lif->hwstamp_txq) { 2016 err = ionic_qcq_enable(lif->hwstamp_txq); 2017 if (err) 2018 goto err_out_hwstamp_tx; 2019 } 2020 2021 return 0; 2022 2023 err_out_hwstamp_tx: 2024 if (lif->hwstamp_rxq) 2025 derr = ionic_qcq_disable(lif, lif->hwstamp_rxq, derr); 2026 err_out_hwstamp_rx: 2027 i = lif->nxqs; 2028 err_out: 2029 while (i--) { 2030 derr = ionic_qcq_disable(lif, lif->txqcqs[i], derr); 2031 derr = ionic_qcq_disable(lif, lif->rxqcqs[i], derr); 2032 } 2033 2034 return err; 2035 } 2036 2037 static int ionic_start_queues(struct ionic_lif *lif) 2038 { 2039 int err; 2040 2041 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) 2042 return -EIO; 2043 2044 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2045 return -EBUSY; 2046 2047 if (test_and_set_bit(IONIC_LIF_F_UP, lif->state)) 2048 return 0; 2049 2050 err = ionic_txrx_enable(lif); 2051 if (err) { 2052 clear_bit(IONIC_LIF_F_UP, lif->state); 2053 return err; 2054 } 2055 netif_tx_wake_all_queues(lif->netdev); 2056 2057 return 0; 2058 } 2059 2060 static int ionic_open(struct net_device *netdev) 2061 { 2062 struct ionic_lif *lif = netdev_priv(netdev); 2063 int err; 2064 2065 /* If recovering from a broken state, clear the bit and we'll try again */ 2066 if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state)) 2067 netdev_info(netdev, "clearing broken state\n"); 2068 2069 mutex_lock(&lif->queue_lock); 2070 2071 err = ionic_txrx_alloc(lif); 2072 if (err) 2073 goto err_unlock; 2074 2075 err = ionic_txrx_init(lif); 2076 if (err) 2077 goto err_txrx_free; 2078 2079 err = netif_set_real_num_tx_queues(netdev, lif->nxqs); 2080 if (err) 2081 goto err_txrx_deinit; 2082 2083 err = netif_set_real_num_rx_queues(netdev, lif->nxqs); 2084 if (err) 2085 goto err_txrx_deinit; 2086 2087 /* don't start the queues until we have link */ 2088 if (netif_carrier_ok(netdev)) { 2089 err = ionic_start_queues(lif); 2090 if (err) 2091 goto err_txrx_deinit; 2092 } 2093 2094 /* If hardware timestamping is enabled, but the queues were freed by 2095 * ionic_stop, those need to be reallocated and initialized, too. 2096 */ 2097 ionic_lif_hwstamp_recreate_queues(lif); 2098 2099 mutex_unlock(&lif->queue_lock); 2100 2101 return 0; 2102 2103 err_txrx_deinit: 2104 ionic_txrx_deinit(lif); 2105 err_txrx_free: 2106 ionic_txrx_free(lif); 2107 err_unlock: 2108 mutex_unlock(&lif->queue_lock); 2109 return err; 2110 } 2111 2112 static void ionic_stop_queues(struct ionic_lif *lif) 2113 { 2114 if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state)) 2115 return; 2116 2117 netif_tx_disable(lif->netdev); 2118 ionic_txrx_disable(lif); 2119 } 2120 2121 static int ionic_stop(struct net_device *netdev) 2122 { 2123 struct ionic_lif *lif = netdev_priv(netdev); 2124 2125 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2126 return 0; 2127 2128 mutex_lock(&lif->queue_lock); 2129 ionic_stop_queues(lif); 2130 ionic_txrx_deinit(lif); 2131 ionic_txrx_free(lif); 2132 mutex_unlock(&lif->queue_lock); 2133 2134 return 0; 2135 } 2136 2137 static int ionic_eth_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 2138 { 2139 struct ionic_lif *lif = netdev_priv(netdev); 2140 2141 switch (cmd) { 2142 case SIOCSHWTSTAMP: 2143 return ionic_lif_hwstamp_set(lif, ifr); 2144 case SIOCGHWTSTAMP: 2145 return ionic_lif_hwstamp_get(lif, ifr); 2146 default: 2147 return -EOPNOTSUPP; 2148 } 2149 } 2150 2151 static int ionic_get_vf_config(struct net_device *netdev, 2152 int vf, struct ifla_vf_info *ivf) 2153 { 2154 struct ionic_lif *lif = netdev_priv(netdev); 2155 struct ionic *ionic = lif->ionic; 2156 int ret = 0; 2157 2158 if (!netif_device_present(netdev)) 2159 return -EBUSY; 2160 2161 down_read(&ionic->vf_op_lock); 2162 2163 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2164 ret = -EINVAL; 2165 } else { 2166 ivf->vf = vf; 2167 ivf->vlan = le16_to_cpu(ionic->vfs[vf].vlanid); 2168 ivf->qos = 0; 2169 ivf->spoofchk = ionic->vfs[vf].spoofchk; 2170 ivf->linkstate = ionic->vfs[vf].linkstate; 2171 ivf->max_tx_rate = le32_to_cpu(ionic->vfs[vf].maxrate); 2172 ivf->trusted = ionic->vfs[vf].trusted; 2173 ether_addr_copy(ivf->mac, ionic->vfs[vf].macaddr); 2174 } 2175 2176 up_read(&ionic->vf_op_lock); 2177 return ret; 2178 } 2179 2180 static int ionic_get_vf_stats(struct net_device *netdev, int vf, 2181 struct ifla_vf_stats *vf_stats) 2182 { 2183 struct ionic_lif *lif = netdev_priv(netdev); 2184 struct ionic *ionic = lif->ionic; 2185 struct ionic_lif_stats *vs; 2186 int ret = 0; 2187 2188 if (!netif_device_present(netdev)) 2189 return -EBUSY; 2190 2191 down_read(&ionic->vf_op_lock); 2192 2193 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2194 ret = -EINVAL; 2195 } else { 2196 memset(vf_stats, 0, sizeof(*vf_stats)); 2197 vs = &ionic->vfs[vf].stats; 2198 2199 vf_stats->rx_packets = le64_to_cpu(vs->rx_ucast_packets); 2200 vf_stats->tx_packets = le64_to_cpu(vs->tx_ucast_packets); 2201 vf_stats->rx_bytes = le64_to_cpu(vs->rx_ucast_bytes); 2202 vf_stats->tx_bytes = le64_to_cpu(vs->tx_ucast_bytes); 2203 vf_stats->broadcast = le64_to_cpu(vs->rx_bcast_packets); 2204 vf_stats->multicast = le64_to_cpu(vs->rx_mcast_packets); 2205 vf_stats->rx_dropped = le64_to_cpu(vs->rx_ucast_drop_packets) + 2206 le64_to_cpu(vs->rx_mcast_drop_packets) + 2207 le64_to_cpu(vs->rx_bcast_drop_packets); 2208 vf_stats->tx_dropped = le64_to_cpu(vs->tx_ucast_drop_packets) + 2209 le64_to_cpu(vs->tx_mcast_drop_packets) + 2210 le64_to_cpu(vs->tx_bcast_drop_packets); 2211 } 2212 2213 up_read(&ionic->vf_op_lock); 2214 return ret; 2215 } 2216 2217 static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2218 { 2219 struct ionic_lif *lif = netdev_priv(netdev); 2220 struct ionic *ionic = lif->ionic; 2221 int ret; 2222 2223 if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac))) 2224 return -EINVAL; 2225 2226 if (!netif_device_present(netdev)) 2227 return -EBUSY; 2228 2229 down_write(&ionic->vf_op_lock); 2230 2231 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2232 ret = -EINVAL; 2233 } else { 2234 ret = ionic_set_vf_config(ionic, vf, IONIC_VF_ATTR_MAC, mac); 2235 if (!ret) 2236 ether_addr_copy(ionic->vfs[vf].macaddr, mac); 2237 } 2238 2239 up_write(&ionic->vf_op_lock); 2240 return ret; 2241 } 2242 2243 static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 2244 u8 qos, __be16 proto) 2245 { 2246 struct ionic_lif *lif = netdev_priv(netdev); 2247 struct ionic *ionic = lif->ionic; 2248 int ret; 2249 2250 /* until someday when we support qos */ 2251 if (qos) 2252 return -EINVAL; 2253 2254 if (vlan > 4095) 2255 return -EINVAL; 2256 2257 if (proto != htons(ETH_P_8021Q)) 2258 return -EPROTONOSUPPORT; 2259 2260 if (!netif_device_present(netdev)) 2261 return -EBUSY; 2262 2263 down_write(&ionic->vf_op_lock); 2264 2265 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2266 ret = -EINVAL; 2267 } else { 2268 ret = ionic_set_vf_config(ionic, vf, 2269 IONIC_VF_ATTR_VLAN, (u8 *)&vlan); 2270 if (!ret) 2271 ionic->vfs[vf].vlanid = cpu_to_le16(vlan); 2272 } 2273 2274 up_write(&ionic->vf_op_lock); 2275 return ret; 2276 } 2277 2278 static int ionic_set_vf_rate(struct net_device *netdev, int vf, 2279 int tx_min, int tx_max) 2280 { 2281 struct ionic_lif *lif = netdev_priv(netdev); 2282 struct ionic *ionic = lif->ionic; 2283 int ret; 2284 2285 /* setting the min just seems silly */ 2286 if (tx_min) 2287 return -EINVAL; 2288 2289 if (!netif_device_present(netdev)) 2290 return -EBUSY; 2291 2292 down_write(&ionic->vf_op_lock); 2293 2294 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2295 ret = -EINVAL; 2296 } else { 2297 ret = ionic_set_vf_config(ionic, vf, 2298 IONIC_VF_ATTR_RATE, (u8 *)&tx_max); 2299 if (!ret) 2300 lif->ionic->vfs[vf].maxrate = cpu_to_le32(tx_max); 2301 } 2302 2303 up_write(&ionic->vf_op_lock); 2304 return ret; 2305 } 2306 2307 static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set) 2308 { 2309 struct ionic_lif *lif = netdev_priv(netdev); 2310 struct ionic *ionic = lif->ionic; 2311 u8 data = set; /* convert to u8 for config */ 2312 int ret; 2313 2314 if (!netif_device_present(netdev)) 2315 return -EBUSY; 2316 2317 down_write(&ionic->vf_op_lock); 2318 2319 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2320 ret = -EINVAL; 2321 } else { 2322 ret = ionic_set_vf_config(ionic, vf, 2323 IONIC_VF_ATTR_SPOOFCHK, &data); 2324 if (!ret) 2325 ionic->vfs[vf].spoofchk = data; 2326 } 2327 2328 up_write(&ionic->vf_op_lock); 2329 return ret; 2330 } 2331 2332 static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set) 2333 { 2334 struct ionic_lif *lif = netdev_priv(netdev); 2335 struct ionic *ionic = lif->ionic; 2336 u8 data = set; /* convert to u8 for config */ 2337 int ret; 2338 2339 if (!netif_device_present(netdev)) 2340 return -EBUSY; 2341 2342 down_write(&ionic->vf_op_lock); 2343 2344 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2345 ret = -EINVAL; 2346 } else { 2347 ret = ionic_set_vf_config(ionic, vf, 2348 IONIC_VF_ATTR_TRUST, &data); 2349 if (!ret) 2350 ionic->vfs[vf].trusted = data; 2351 } 2352 2353 up_write(&ionic->vf_op_lock); 2354 return ret; 2355 } 2356 2357 static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set) 2358 { 2359 struct ionic_lif *lif = netdev_priv(netdev); 2360 struct ionic *ionic = lif->ionic; 2361 u8 data; 2362 int ret; 2363 2364 switch (set) { 2365 case IFLA_VF_LINK_STATE_ENABLE: 2366 data = IONIC_VF_LINK_STATUS_UP; 2367 break; 2368 case IFLA_VF_LINK_STATE_DISABLE: 2369 data = IONIC_VF_LINK_STATUS_DOWN; 2370 break; 2371 case IFLA_VF_LINK_STATE_AUTO: 2372 data = IONIC_VF_LINK_STATUS_AUTO; 2373 break; 2374 default: 2375 return -EINVAL; 2376 } 2377 2378 if (!netif_device_present(netdev)) 2379 return -EBUSY; 2380 2381 down_write(&ionic->vf_op_lock); 2382 2383 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2384 ret = -EINVAL; 2385 } else { 2386 ret = ionic_set_vf_config(ionic, vf, 2387 IONIC_VF_ATTR_LINKSTATE, &data); 2388 if (!ret) 2389 ionic->vfs[vf].linkstate = set; 2390 } 2391 2392 up_write(&ionic->vf_op_lock); 2393 return ret; 2394 } 2395 2396 static const struct net_device_ops ionic_netdev_ops = { 2397 .ndo_open = ionic_open, 2398 .ndo_stop = ionic_stop, 2399 .ndo_eth_ioctl = ionic_eth_ioctl, 2400 .ndo_start_xmit = ionic_start_xmit, 2401 .ndo_get_stats64 = ionic_get_stats64, 2402 .ndo_set_rx_mode = ionic_ndo_set_rx_mode, 2403 .ndo_set_features = ionic_set_features, 2404 .ndo_set_mac_address = ionic_set_mac_address, 2405 .ndo_validate_addr = eth_validate_addr, 2406 .ndo_tx_timeout = ionic_tx_timeout, 2407 .ndo_change_mtu = ionic_change_mtu, 2408 .ndo_vlan_rx_add_vid = ionic_vlan_rx_add_vid, 2409 .ndo_vlan_rx_kill_vid = ionic_vlan_rx_kill_vid, 2410 .ndo_set_vf_vlan = ionic_set_vf_vlan, 2411 .ndo_set_vf_trust = ionic_set_vf_trust, 2412 .ndo_set_vf_mac = ionic_set_vf_mac, 2413 .ndo_set_vf_rate = ionic_set_vf_rate, 2414 .ndo_set_vf_spoofchk = ionic_set_vf_spoofchk, 2415 .ndo_get_vf_config = ionic_get_vf_config, 2416 .ndo_set_vf_link_state = ionic_set_vf_link_state, 2417 .ndo_get_vf_stats = ionic_get_vf_stats, 2418 }; 2419 2420 static void ionic_swap_queues(struct ionic_qcq *a, struct ionic_qcq *b) 2421 { 2422 /* only swapping the queues, not the napi, flags, or other stuff */ 2423 swap(a->q.features, b->q.features); 2424 swap(a->q.num_descs, b->q.num_descs); 2425 swap(a->q.desc_size, b->q.desc_size); 2426 swap(a->q.base, b->q.base); 2427 swap(a->q.base_pa, b->q.base_pa); 2428 swap(a->q.info, b->q.info); 2429 swap(a->q_base, b->q_base); 2430 swap(a->q_base_pa, b->q_base_pa); 2431 swap(a->q_size, b->q_size); 2432 2433 swap(a->q.sg_desc_size, b->q.sg_desc_size); 2434 swap(a->q.sg_base, b->q.sg_base); 2435 swap(a->q.sg_base_pa, b->q.sg_base_pa); 2436 swap(a->sg_base, b->sg_base); 2437 swap(a->sg_base_pa, b->sg_base_pa); 2438 swap(a->sg_size, b->sg_size); 2439 2440 swap(a->cq.num_descs, b->cq.num_descs); 2441 swap(a->cq.desc_size, b->cq.desc_size); 2442 swap(a->cq.base, b->cq.base); 2443 swap(a->cq.base_pa, b->cq.base_pa); 2444 swap(a->cq.info, b->cq.info); 2445 swap(a->cq_base, b->cq_base); 2446 swap(a->cq_base_pa, b->cq_base_pa); 2447 swap(a->cq_size, b->cq_size); 2448 2449 ionic_debugfs_del_qcq(a); 2450 ionic_debugfs_add_qcq(a->q.lif, a); 2451 } 2452 2453 int ionic_reconfigure_queues(struct ionic_lif *lif, 2454 struct ionic_queue_params *qparam) 2455 { 2456 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz; 2457 struct ionic_qcq **tx_qcqs = NULL; 2458 struct ionic_qcq **rx_qcqs = NULL; 2459 unsigned int flags, i; 2460 int err = 0; 2461 2462 /* allocate temporary qcq arrays to hold new queue structs */ 2463 if (qparam->nxqs != lif->nxqs || qparam->ntxq_descs != lif->ntxq_descs) { 2464 tx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->ntxqs_per_lif, 2465 sizeof(struct ionic_qcq *), GFP_KERNEL); 2466 if (!tx_qcqs) { 2467 err = -ENOMEM; 2468 goto err_out; 2469 } 2470 } 2471 if (qparam->nxqs != lif->nxqs || 2472 qparam->nrxq_descs != lif->nrxq_descs || 2473 qparam->rxq_features != lif->rxq_features) { 2474 rx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->nrxqs_per_lif, 2475 sizeof(struct ionic_qcq *), GFP_KERNEL); 2476 if (!rx_qcqs) { 2477 err = -ENOMEM; 2478 goto err_out; 2479 } 2480 } 2481 2482 /* allocate new desc_info and rings, but leave the interrupt setup 2483 * until later so as to not mess with the still-running queues 2484 */ 2485 if (tx_qcqs) { 2486 num_desc = qparam->ntxq_descs; 2487 desc_sz = sizeof(struct ionic_txq_desc); 2488 comp_sz = sizeof(struct ionic_txq_comp); 2489 2490 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 2491 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 2492 sizeof(struct ionic_txq_sg_desc_v1)) 2493 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 2494 else 2495 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 2496 2497 for (i = 0; i < qparam->nxqs; i++) { 2498 flags = lif->txqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2499 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 2500 num_desc, desc_sz, comp_sz, sg_desc_sz, 2501 lif->kern_pid, &tx_qcqs[i]); 2502 if (err) 2503 goto err_out; 2504 } 2505 } 2506 2507 if (rx_qcqs) { 2508 num_desc = qparam->nrxq_descs; 2509 desc_sz = sizeof(struct ionic_rxq_desc); 2510 comp_sz = sizeof(struct ionic_rxq_comp); 2511 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 2512 2513 if (qparam->rxq_features & IONIC_Q_F_2X_CQ_DESC) 2514 comp_sz *= 2; 2515 2516 for (i = 0; i < qparam->nxqs; i++) { 2517 flags = lif->rxqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2518 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 2519 num_desc, desc_sz, comp_sz, sg_desc_sz, 2520 lif->kern_pid, &rx_qcqs[i]); 2521 if (err) 2522 goto err_out; 2523 2524 rx_qcqs[i]->q.features = qparam->rxq_features; 2525 } 2526 } 2527 2528 /* stop and clean the queues */ 2529 ionic_stop_queues_reconfig(lif); 2530 2531 if (qparam->nxqs != lif->nxqs) { 2532 err = netif_set_real_num_tx_queues(lif->netdev, qparam->nxqs); 2533 if (err) 2534 goto err_out_reinit_unlock; 2535 err = netif_set_real_num_rx_queues(lif->netdev, qparam->nxqs); 2536 if (err) { 2537 netif_set_real_num_tx_queues(lif->netdev, lif->nxqs); 2538 goto err_out_reinit_unlock; 2539 } 2540 } 2541 2542 /* swap new desc_info and rings, keeping existing interrupt config */ 2543 if (tx_qcqs) { 2544 lif->ntxq_descs = qparam->ntxq_descs; 2545 for (i = 0; i < qparam->nxqs; i++) 2546 ionic_swap_queues(lif->txqcqs[i], tx_qcqs[i]); 2547 } 2548 2549 if (rx_qcqs) { 2550 lif->nrxq_descs = qparam->nrxq_descs; 2551 for (i = 0; i < qparam->nxqs; i++) 2552 ionic_swap_queues(lif->rxqcqs[i], rx_qcqs[i]); 2553 } 2554 2555 /* if we need to change the interrupt layout, this is the time */ 2556 if (qparam->intr_split != test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) || 2557 qparam->nxqs != lif->nxqs) { 2558 if (qparam->intr_split) { 2559 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 2560 } else { 2561 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 2562 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 2563 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 2564 } 2565 2566 /* clear existing interrupt assignments */ 2567 for (i = 0; i < lif->ionic->ntxqs_per_lif; i++) { 2568 ionic_qcq_intr_free(lif, lif->txqcqs[i]); 2569 ionic_qcq_intr_free(lif, lif->rxqcqs[i]); 2570 } 2571 2572 /* re-assign the interrupts */ 2573 for (i = 0; i < qparam->nxqs; i++) { 2574 lif->rxqcqs[i]->flags |= IONIC_QCQ_F_INTR; 2575 err = ionic_alloc_qcq_interrupt(lif, lif->rxqcqs[i]); 2576 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2577 lif->rxqcqs[i]->intr.index, 2578 lif->rx_coalesce_hw); 2579 2580 if (qparam->intr_split) { 2581 lif->txqcqs[i]->flags |= IONIC_QCQ_F_INTR; 2582 err = ionic_alloc_qcq_interrupt(lif, lif->txqcqs[i]); 2583 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2584 lif->txqcqs[i]->intr.index, 2585 lif->tx_coalesce_hw); 2586 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 2587 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 2588 } else { 2589 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2590 ionic_link_qcq_interrupts(lif->rxqcqs[i], lif->txqcqs[i]); 2591 } 2592 } 2593 } 2594 2595 /* now we can rework the debugfs mappings */ 2596 if (tx_qcqs) { 2597 for (i = 0; i < qparam->nxqs; i++) { 2598 ionic_debugfs_del_qcq(lif->txqcqs[i]); 2599 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 2600 } 2601 } 2602 2603 if (rx_qcqs) { 2604 for (i = 0; i < qparam->nxqs; i++) { 2605 ionic_debugfs_del_qcq(lif->rxqcqs[i]); 2606 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 2607 } 2608 } 2609 2610 swap(lif->nxqs, qparam->nxqs); 2611 swap(lif->rxq_features, qparam->rxq_features); 2612 2613 err_out_reinit_unlock: 2614 /* re-init the queues, but don't lose an error code */ 2615 if (err) 2616 ionic_start_queues_reconfig(lif); 2617 else 2618 err = ionic_start_queues_reconfig(lif); 2619 2620 err_out: 2621 /* free old allocs without cleaning intr */ 2622 for (i = 0; i < qparam->nxqs; i++) { 2623 if (tx_qcqs && tx_qcqs[i]) { 2624 tx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2625 ionic_qcq_free(lif, tx_qcqs[i]); 2626 devm_kfree(lif->ionic->dev, tx_qcqs[i]); 2627 tx_qcqs[i] = NULL; 2628 } 2629 if (rx_qcqs && rx_qcqs[i]) { 2630 rx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2631 ionic_qcq_free(lif, rx_qcqs[i]); 2632 devm_kfree(lif->ionic->dev, rx_qcqs[i]); 2633 rx_qcqs[i] = NULL; 2634 } 2635 } 2636 2637 /* free q array */ 2638 if (rx_qcqs) { 2639 devm_kfree(lif->ionic->dev, rx_qcqs); 2640 rx_qcqs = NULL; 2641 } 2642 if (tx_qcqs) { 2643 devm_kfree(lif->ionic->dev, tx_qcqs); 2644 tx_qcqs = NULL; 2645 } 2646 2647 /* clean the unused dma and info allocations when new set is smaller 2648 * than the full array, but leave the qcq shells in place 2649 */ 2650 for (i = lif->nxqs; i < lif->ionic->ntxqs_per_lif; i++) { 2651 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2652 ionic_qcq_free(lif, lif->txqcqs[i]); 2653 2654 lif->rxqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2655 ionic_qcq_free(lif, lif->rxqcqs[i]); 2656 } 2657 2658 if (err) 2659 netdev_info(lif->netdev, "%s: failed %d\n", __func__, err); 2660 2661 return err; 2662 } 2663 2664 int ionic_lif_alloc(struct ionic *ionic) 2665 { 2666 struct device *dev = ionic->dev; 2667 union ionic_lif_identity *lid; 2668 struct net_device *netdev; 2669 struct ionic_lif *lif; 2670 int tbl_sz; 2671 int err; 2672 2673 lid = kzalloc(sizeof(*lid), GFP_KERNEL); 2674 if (!lid) 2675 return -ENOMEM; 2676 2677 netdev = alloc_etherdev_mqs(sizeof(*lif), 2678 ionic->ntxqs_per_lif, ionic->ntxqs_per_lif); 2679 if (!netdev) { 2680 dev_err(dev, "Cannot allocate netdev, aborting\n"); 2681 err = -ENOMEM; 2682 goto err_out_free_lid; 2683 } 2684 2685 SET_NETDEV_DEV(netdev, dev); 2686 2687 lif = netdev_priv(netdev); 2688 lif->netdev = netdev; 2689 ionic->lif = lif; 2690 netdev->netdev_ops = &ionic_netdev_ops; 2691 ionic_ethtool_set_ops(netdev); 2692 2693 netdev->watchdog_timeo = 2 * HZ; 2694 netif_carrier_off(netdev); 2695 2696 lif->identity = lid; 2697 lif->lif_type = IONIC_LIF_TYPE_CLASSIC; 2698 err = ionic_lif_identify(ionic, lif->lif_type, lif->identity); 2699 if (err) { 2700 dev_err(ionic->dev, "Cannot identify type %d: %d\n", 2701 lif->lif_type, err); 2702 goto err_out_free_netdev; 2703 } 2704 lif->netdev->min_mtu = max_t(unsigned int, ETH_MIN_MTU, 2705 le32_to_cpu(lif->identity->eth.min_frame_size)); 2706 lif->netdev->max_mtu = 2707 le32_to_cpu(lif->identity->eth.max_frame_size) - ETH_HLEN - VLAN_HLEN; 2708 2709 lif->neqs = ionic->neqs_per_lif; 2710 lif->nxqs = ionic->ntxqs_per_lif; 2711 2712 lif->ionic = ionic; 2713 lif->index = 0; 2714 2715 if (is_kdump_kernel()) { 2716 lif->ntxq_descs = IONIC_MIN_TXRX_DESC; 2717 lif->nrxq_descs = IONIC_MIN_TXRX_DESC; 2718 } else { 2719 lif->ntxq_descs = IONIC_DEF_TXRX_DESC; 2720 lif->nrxq_descs = IONIC_DEF_TXRX_DESC; 2721 } 2722 2723 /* Convert the default coalesce value to actual hw resolution */ 2724 lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT; 2725 lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic, 2726 lif->rx_coalesce_usecs); 2727 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 2728 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 2729 set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 2730 set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 2731 2732 snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index); 2733 2734 mutex_init(&lif->queue_lock); 2735 mutex_init(&lif->config_lock); 2736 2737 spin_lock_init(&lif->adminq_lock); 2738 2739 spin_lock_init(&lif->deferred.lock); 2740 INIT_LIST_HEAD(&lif->deferred.list); 2741 INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work); 2742 2743 /* allocate lif info */ 2744 lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE); 2745 lif->info = dma_alloc_coherent(dev, lif->info_sz, 2746 &lif->info_pa, GFP_KERNEL); 2747 if (!lif->info) { 2748 dev_err(dev, "Failed to allocate lif info, aborting\n"); 2749 err = -ENOMEM; 2750 goto err_out_free_mutex; 2751 } 2752 2753 ionic_debugfs_add_lif(lif); 2754 2755 /* allocate control queues and txrx queue arrays */ 2756 ionic_lif_queue_identify(lif); 2757 err = ionic_qcqs_alloc(lif); 2758 if (err) 2759 goto err_out_free_lif_info; 2760 2761 /* allocate rss indirection table */ 2762 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 2763 lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz; 2764 lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz, 2765 &lif->rss_ind_tbl_pa, 2766 GFP_KERNEL); 2767 2768 if (!lif->rss_ind_tbl) { 2769 err = -ENOMEM; 2770 dev_err(dev, "Failed to allocate rss indirection table, aborting\n"); 2771 goto err_out_free_qcqs; 2772 } 2773 netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE); 2774 2775 ionic_lif_alloc_phc(lif); 2776 2777 return 0; 2778 2779 err_out_free_qcqs: 2780 ionic_qcqs_free(lif); 2781 err_out_free_lif_info: 2782 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 2783 lif->info = NULL; 2784 lif->info_pa = 0; 2785 err_out_free_mutex: 2786 mutex_destroy(&lif->config_lock); 2787 mutex_destroy(&lif->queue_lock); 2788 err_out_free_netdev: 2789 free_netdev(lif->netdev); 2790 lif = NULL; 2791 err_out_free_lid: 2792 kfree(lid); 2793 2794 return err; 2795 } 2796 2797 static void ionic_lif_reset(struct ionic_lif *lif) 2798 { 2799 struct ionic_dev *idev = &lif->ionic->idev; 2800 2801 mutex_lock(&lif->ionic->dev_cmd_lock); 2802 ionic_dev_cmd_lif_reset(idev, lif->index); 2803 ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2804 mutex_unlock(&lif->ionic->dev_cmd_lock); 2805 } 2806 2807 static void ionic_lif_handle_fw_down(struct ionic_lif *lif) 2808 { 2809 struct ionic *ionic = lif->ionic; 2810 2811 if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2812 return; 2813 2814 dev_info(ionic->dev, "FW Down: Stopping LIFs\n"); 2815 2816 netif_device_detach(lif->netdev); 2817 2818 mutex_lock(&lif->queue_lock); 2819 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 2820 dev_info(ionic->dev, "Surprise FW stop, stopping queues\n"); 2821 ionic_stop_queues(lif); 2822 } 2823 2824 if (netif_running(lif->netdev)) { 2825 ionic_txrx_deinit(lif); 2826 ionic_txrx_free(lif); 2827 } 2828 ionic_lif_deinit(lif); 2829 ionic_reset(ionic); 2830 ionic_qcqs_free(lif); 2831 2832 mutex_unlock(&lif->queue_lock); 2833 2834 dev_info(ionic->dev, "FW Down: LIFs stopped\n"); 2835 } 2836 2837 static void ionic_lif_handle_fw_up(struct ionic_lif *lif) 2838 { 2839 struct ionic *ionic = lif->ionic; 2840 int err; 2841 2842 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2843 return; 2844 2845 dev_info(ionic->dev, "FW Up: restarting LIFs\n"); 2846 2847 ionic_init_devinfo(ionic); 2848 err = ionic_identify(ionic); 2849 if (err) 2850 goto err_out; 2851 err = ionic_port_identify(ionic); 2852 if (err) 2853 goto err_out; 2854 err = ionic_port_init(ionic); 2855 if (err) 2856 goto err_out; 2857 2858 mutex_lock(&lif->queue_lock); 2859 2860 err = ionic_qcqs_alloc(lif); 2861 if (err) 2862 goto err_unlock; 2863 2864 err = ionic_lif_init(lif); 2865 if (err) 2866 goto err_qcqs_free; 2867 2868 if (lif->registered) 2869 ionic_lif_set_netdev_info(lif); 2870 2871 ionic_rx_filter_replay(lif); 2872 2873 if (netif_running(lif->netdev)) { 2874 err = ionic_txrx_alloc(lif); 2875 if (err) 2876 goto err_lifs_deinit; 2877 2878 err = ionic_txrx_init(lif); 2879 if (err) 2880 goto err_txrx_free; 2881 } 2882 2883 mutex_unlock(&lif->queue_lock); 2884 2885 clear_bit(IONIC_LIF_F_FW_RESET, lif->state); 2886 ionic_link_status_check_request(lif, CAN_SLEEP); 2887 netif_device_attach(lif->netdev); 2888 dev_info(ionic->dev, "FW Up: LIFs restarted\n"); 2889 2890 /* restore the hardware timestamping queues */ 2891 ionic_lif_hwstamp_replay(lif); 2892 2893 return; 2894 2895 err_txrx_free: 2896 ionic_txrx_free(lif); 2897 err_lifs_deinit: 2898 ionic_lif_deinit(lif); 2899 err_qcqs_free: 2900 ionic_qcqs_free(lif); 2901 err_unlock: 2902 mutex_unlock(&lif->queue_lock); 2903 err_out: 2904 dev_err(ionic->dev, "FW Up: LIFs restart failed - err %d\n", err); 2905 } 2906 2907 void ionic_lif_free(struct ionic_lif *lif) 2908 { 2909 struct device *dev = lif->ionic->dev; 2910 2911 ionic_lif_free_phc(lif); 2912 2913 /* free rss indirection table */ 2914 dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl, 2915 lif->rss_ind_tbl_pa); 2916 lif->rss_ind_tbl = NULL; 2917 lif->rss_ind_tbl_pa = 0; 2918 2919 /* free queues */ 2920 ionic_qcqs_free(lif); 2921 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2922 ionic_lif_reset(lif); 2923 2924 /* free lif info */ 2925 kfree(lif->identity); 2926 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 2927 lif->info = NULL; 2928 lif->info_pa = 0; 2929 2930 /* unmap doorbell page */ 2931 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 2932 lif->kern_dbpage = NULL; 2933 kfree(lif->dbid_inuse); 2934 lif->dbid_inuse = NULL; 2935 2936 mutex_destroy(&lif->config_lock); 2937 mutex_destroy(&lif->queue_lock); 2938 2939 /* free netdev & lif */ 2940 ionic_debugfs_del_lif(lif); 2941 free_netdev(lif->netdev); 2942 } 2943 2944 void ionic_lif_deinit(struct ionic_lif *lif) 2945 { 2946 if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state)) 2947 return; 2948 2949 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 2950 cancel_work_sync(&lif->deferred.work); 2951 cancel_work_sync(&lif->tx_timeout_work); 2952 ionic_rx_filters_deinit(lif); 2953 if (lif->netdev->features & NETIF_F_RXHASH) 2954 ionic_lif_rss_deinit(lif); 2955 } 2956 2957 napi_disable(&lif->adminqcq->napi); 2958 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 2959 ionic_lif_qcq_deinit(lif, lif->adminqcq); 2960 2961 ionic_lif_reset(lif); 2962 } 2963 2964 static int ionic_lif_adminq_init(struct ionic_lif *lif) 2965 { 2966 struct device *dev = lif->ionic->dev; 2967 struct ionic_q_init_comp comp; 2968 struct ionic_dev *idev; 2969 struct ionic_qcq *qcq; 2970 struct ionic_queue *q; 2971 int err; 2972 2973 idev = &lif->ionic->idev; 2974 qcq = lif->adminqcq; 2975 q = &qcq->q; 2976 2977 mutex_lock(&lif->ionic->dev_cmd_lock); 2978 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index); 2979 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2980 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 2981 mutex_unlock(&lif->ionic->dev_cmd_lock); 2982 if (err) { 2983 netdev_err(lif->netdev, "adminq init failed %d\n", err); 2984 return err; 2985 } 2986 2987 q->hw_type = comp.hw_type; 2988 q->hw_index = le32_to_cpu(comp.hw_index); 2989 q->dbval = IONIC_DBELL_QID(q->hw_index); 2990 2991 dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type); 2992 dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index); 2993 2994 netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi, 2995 NAPI_POLL_WEIGHT); 2996 2997 napi_enable(&qcq->napi); 2998 2999 if (qcq->flags & IONIC_QCQ_F_INTR) 3000 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 3001 IONIC_INTR_MASK_CLEAR); 3002 3003 qcq->flags |= IONIC_QCQ_F_INITED; 3004 3005 return 0; 3006 } 3007 3008 static int ionic_lif_notifyq_init(struct ionic_lif *lif) 3009 { 3010 struct ionic_qcq *qcq = lif->notifyqcq; 3011 struct device *dev = lif->ionic->dev; 3012 struct ionic_queue *q = &qcq->q; 3013 int err; 3014 3015 struct ionic_admin_ctx ctx = { 3016 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3017 .cmd.q_init = { 3018 .opcode = IONIC_CMD_Q_INIT, 3019 .lif_index = cpu_to_le16(lif->index), 3020 .type = q->type, 3021 .ver = lif->qtype_info[q->type].version, 3022 .index = cpu_to_le32(q->index), 3023 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 3024 IONIC_QINIT_F_ENA), 3025 .intr_index = cpu_to_le16(lif->adminqcq->intr.index), 3026 .pid = cpu_to_le16(q->pid), 3027 .ring_size = ilog2(q->num_descs), 3028 .ring_base = cpu_to_le64(q->base_pa), 3029 } 3030 }; 3031 3032 dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid); 3033 dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index); 3034 dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 3035 dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 3036 3037 err = ionic_adminq_post_wait(lif, &ctx); 3038 if (err) 3039 return err; 3040 3041 lif->last_eid = 0; 3042 q->hw_type = ctx.comp.q_init.hw_type; 3043 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 3044 q->dbval = IONIC_DBELL_QID(q->hw_index); 3045 3046 dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type); 3047 dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index); 3048 3049 /* preset the callback info */ 3050 q->info[0].cb_arg = lif; 3051 3052 qcq->flags |= IONIC_QCQ_F_INITED; 3053 3054 return 0; 3055 } 3056 3057 static int ionic_station_set(struct ionic_lif *lif) 3058 { 3059 struct net_device *netdev = lif->netdev; 3060 struct ionic_admin_ctx ctx = { 3061 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3062 .cmd.lif_getattr = { 3063 .opcode = IONIC_CMD_LIF_GETATTR, 3064 .index = cpu_to_le16(lif->index), 3065 .attr = IONIC_LIF_ATTR_MAC, 3066 }, 3067 }; 3068 struct sockaddr addr; 3069 int err; 3070 3071 err = ionic_adminq_post_wait(lif, &ctx); 3072 if (err) 3073 return err; 3074 netdev_dbg(lif->netdev, "found initial MAC addr %pM\n", 3075 ctx.comp.lif_getattr.mac); 3076 if (is_zero_ether_addr(ctx.comp.lif_getattr.mac)) 3077 return 0; 3078 3079 if (!is_zero_ether_addr(netdev->dev_addr)) { 3080 /* If the netdev mac is non-zero and doesn't match the default 3081 * device address, it was set by something earlier and we're 3082 * likely here again after a fw-upgrade reset. We need to be 3083 * sure the netdev mac is in our filter list. 3084 */ 3085 if (!ether_addr_equal(ctx.comp.lif_getattr.mac, 3086 netdev->dev_addr)) 3087 ionic_lif_addr_add(lif, netdev->dev_addr); 3088 } else { 3089 /* Update the netdev mac with the device's mac */ 3090 memcpy(addr.sa_data, ctx.comp.lif_getattr.mac, netdev->addr_len); 3091 addr.sa_family = AF_INET; 3092 err = eth_prepare_mac_addr_change(netdev, &addr); 3093 if (err) { 3094 netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n", 3095 addr.sa_data, err); 3096 return 0; 3097 } 3098 3099 eth_commit_mac_addr_change(netdev, &addr); 3100 } 3101 3102 netdev_dbg(lif->netdev, "adding station MAC addr %pM\n", 3103 netdev->dev_addr); 3104 ionic_lif_addr_add(lif, netdev->dev_addr); 3105 3106 return 0; 3107 } 3108 3109 int ionic_lif_init(struct ionic_lif *lif) 3110 { 3111 struct ionic_dev *idev = &lif->ionic->idev; 3112 struct device *dev = lif->ionic->dev; 3113 struct ionic_lif_init_comp comp; 3114 int dbpage_num; 3115 int err; 3116 3117 mutex_lock(&lif->ionic->dev_cmd_lock); 3118 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa); 3119 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 3120 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 3121 mutex_unlock(&lif->ionic->dev_cmd_lock); 3122 if (err) 3123 return err; 3124 3125 lif->hw_index = le16_to_cpu(comp.hw_index); 3126 3127 /* now that we have the hw_index we can figure out our doorbell page */ 3128 lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif); 3129 if (!lif->dbid_count) { 3130 dev_err(dev, "No doorbell pages, aborting\n"); 3131 return -EINVAL; 3132 } 3133 3134 lif->dbid_inuse = bitmap_alloc(lif->dbid_count, GFP_KERNEL); 3135 if (!lif->dbid_inuse) { 3136 dev_err(dev, "Failed alloc doorbell id bitmap, aborting\n"); 3137 return -ENOMEM; 3138 } 3139 3140 /* first doorbell id reserved for kernel (dbid aka pid == zero) */ 3141 set_bit(0, lif->dbid_inuse); 3142 lif->kern_pid = 0; 3143 3144 dbpage_num = ionic_db_page_num(lif, lif->kern_pid); 3145 lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num); 3146 if (!lif->kern_dbpage) { 3147 dev_err(dev, "Cannot map dbpage, aborting\n"); 3148 err = -ENOMEM; 3149 goto err_out_free_dbid; 3150 } 3151 3152 err = ionic_lif_adminq_init(lif); 3153 if (err) 3154 goto err_out_adminq_deinit; 3155 3156 if (lif->ionic->nnqs_per_lif) { 3157 err = ionic_lif_notifyq_init(lif); 3158 if (err) 3159 goto err_out_notifyq_deinit; 3160 } 3161 3162 err = ionic_init_nic_features(lif); 3163 if (err) 3164 goto err_out_notifyq_deinit; 3165 3166 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 3167 err = ionic_rx_filters_init(lif); 3168 if (err) 3169 goto err_out_notifyq_deinit; 3170 } 3171 3172 err = ionic_station_set(lif); 3173 if (err) 3174 goto err_out_notifyq_deinit; 3175 3176 lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT; 3177 3178 set_bit(IONIC_LIF_F_INITED, lif->state); 3179 3180 INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work); 3181 3182 return 0; 3183 3184 err_out_notifyq_deinit: 3185 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 3186 err_out_adminq_deinit: 3187 ionic_lif_qcq_deinit(lif, lif->adminqcq); 3188 ionic_lif_reset(lif); 3189 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 3190 lif->kern_dbpage = NULL; 3191 err_out_free_dbid: 3192 kfree(lif->dbid_inuse); 3193 lif->dbid_inuse = NULL; 3194 3195 return err; 3196 } 3197 3198 static void ionic_lif_notify_work(struct work_struct *ws) 3199 { 3200 } 3201 3202 static void ionic_lif_set_netdev_info(struct ionic_lif *lif) 3203 { 3204 struct ionic_admin_ctx ctx = { 3205 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3206 .cmd.lif_setattr = { 3207 .opcode = IONIC_CMD_LIF_SETATTR, 3208 .index = cpu_to_le16(lif->index), 3209 .attr = IONIC_LIF_ATTR_NAME, 3210 }, 3211 }; 3212 3213 strlcpy(ctx.cmd.lif_setattr.name, lif->netdev->name, 3214 sizeof(ctx.cmd.lif_setattr.name)); 3215 3216 ionic_adminq_post_wait(lif, &ctx); 3217 } 3218 3219 static struct ionic_lif *ionic_netdev_lif(struct net_device *netdev) 3220 { 3221 if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit) 3222 return NULL; 3223 3224 return netdev_priv(netdev); 3225 } 3226 3227 static int ionic_lif_notify(struct notifier_block *nb, 3228 unsigned long event, void *info) 3229 { 3230 struct net_device *ndev = netdev_notifier_info_to_dev(info); 3231 struct ionic *ionic = container_of(nb, struct ionic, nb); 3232 struct ionic_lif *lif = ionic_netdev_lif(ndev); 3233 3234 if (!lif || lif->ionic != ionic) 3235 return NOTIFY_DONE; 3236 3237 switch (event) { 3238 case NETDEV_CHANGENAME: 3239 ionic_lif_set_netdev_info(lif); 3240 break; 3241 } 3242 3243 return NOTIFY_DONE; 3244 } 3245 3246 int ionic_lif_register(struct ionic_lif *lif) 3247 { 3248 int err; 3249 3250 ionic_lif_register_phc(lif); 3251 3252 INIT_WORK(&lif->ionic->nb_work, ionic_lif_notify_work); 3253 3254 lif->ionic->nb.notifier_call = ionic_lif_notify; 3255 3256 err = register_netdevice_notifier(&lif->ionic->nb); 3257 if (err) 3258 lif->ionic->nb.notifier_call = NULL; 3259 3260 /* only register LIF0 for now */ 3261 err = register_netdev(lif->netdev); 3262 if (err) { 3263 dev_err(lif->ionic->dev, "Cannot register net device, aborting\n"); 3264 ionic_lif_unregister_phc(lif); 3265 return err; 3266 } 3267 3268 ionic_link_status_check_request(lif, CAN_SLEEP); 3269 lif->registered = true; 3270 ionic_lif_set_netdev_info(lif); 3271 3272 return 0; 3273 } 3274 3275 void ionic_lif_unregister(struct ionic_lif *lif) 3276 { 3277 if (lif->ionic->nb.notifier_call) { 3278 unregister_netdevice_notifier(&lif->ionic->nb); 3279 cancel_work_sync(&lif->ionic->nb_work); 3280 lif->ionic->nb.notifier_call = NULL; 3281 } 3282 3283 if (lif->netdev->reg_state == NETREG_REGISTERED) 3284 unregister_netdev(lif->netdev); 3285 3286 ionic_lif_unregister_phc(lif); 3287 3288 lif->registered = false; 3289 } 3290 3291 static void ionic_lif_queue_identify(struct ionic_lif *lif) 3292 { 3293 union ionic_q_identity __iomem *q_ident; 3294 struct ionic *ionic = lif->ionic; 3295 struct ionic_dev *idev; 3296 int qtype; 3297 int err; 3298 3299 idev = &lif->ionic->idev; 3300 q_ident = (union ionic_q_identity __iomem *)&idev->dev_cmd_regs->data; 3301 3302 for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) { 3303 struct ionic_qtype_info *qti = &lif->qtype_info[qtype]; 3304 3305 /* filter out the ones we know about */ 3306 switch (qtype) { 3307 case IONIC_QTYPE_ADMINQ: 3308 case IONIC_QTYPE_NOTIFYQ: 3309 case IONIC_QTYPE_RXQ: 3310 case IONIC_QTYPE_TXQ: 3311 break; 3312 default: 3313 continue; 3314 } 3315 3316 memset(qti, 0, sizeof(*qti)); 3317 3318 mutex_lock(&ionic->dev_cmd_lock); 3319 ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype, 3320 ionic_qtype_versions[qtype]); 3321 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3322 if (!err) { 3323 qti->version = readb(&q_ident->version); 3324 qti->supported = readb(&q_ident->supported); 3325 qti->features = readq(&q_ident->features); 3326 qti->desc_sz = readw(&q_ident->desc_sz); 3327 qti->comp_sz = readw(&q_ident->comp_sz); 3328 qti->sg_desc_sz = readw(&q_ident->sg_desc_sz); 3329 qti->max_sg_elems = readw(&q_ident->max_sg_elems); 3330 qti->sg_desc_stride = readw(&q_ident->sg_desc_stride); 3331 } 3332 mutex_unlock(&ionic->dev_cmd_lock); 3333 3334 if (err == -EINVAL) { 3335 dev_err(ionic->dev, "qtype %d not supported\n", qtype); 3336 continue; 3337 } else if (err == -EIO) { 3338 dev_err(ionic->dev, "q_ident failed, not supported on older FW\n"); 3339 return; 3340 } else if (err) { 3341 dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n", 3342 qtype, err); 3343 return; 3344 } 3345 3346 dev_dbg(ionic->dev, " qtype[%d].version = %d\n", 3347 qtype, qti->version); 3348 dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n", 3349 qtype, qti->supported); 3350 dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n", 3351 qtype, qti->features); 3352 dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n", 3353 qtype, qti->desc_sz); 3354 dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n", 3355 qtype, qti->comp_sz); 3356 dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n", 3357 qtype, qti->sg_desc_sz); 3358 dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n", 3359 qtype, qti->max_sg_elems); 3360 dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n", 3361 qtype, qti->sg_desc_stride); 3362 } 3363 } 3364 3365 int ionic_lif_identify(struct ionic *ionic, u8 lif_type, 3366 union ionic_lif_identity *lid) 3367 { 3368 struct ionic_dev *idev = &ionic->idev; 3369 size_t sz; 3370 int err; 3371 3372 sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data)); 3373 3374 mutex_lock(&ionic->dev_cmd_lock); 3375 ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1); 3376 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3377 memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz); 3378 mutex_unlock(&ionic->dev_cmd_lock); 3379 if (err) 3380 return (err); 3381 3382 dev_dbg(ionic->dev, "capabilities 0x%llx\n", 3383 le64_to_cpu(lid->capabilities)); 3384 3385 dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n", 3386 le32_to_cpu(lid->eth.max_ucast_filters)); 3387 dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n", 3388 le32_to_cpu(lid->eth.max_mcast_filters)); 3389 dev_dbg(ionic->dev, "eth.features 0x%llx\n", 3390 le64_to_cpu(lid->eth.config.features)); 3391 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n", 3392 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ])); 3393 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n", 3394 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ])); 3395 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n", 3396 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ])); 3397 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n", 3398 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ])); 3399 dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name); 3400 dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac); 3401 dev_dbg(ionic->dev, "eth.config.mtu %d\n", 3402 le32_to_cpu(lid->eth.config.mtu)); 3403 3404 return 0; 3405 } 3406 3407 int ionic_lif_size(struct ionic *ionic) 3408 { 3409 struct ionic_identity *ident = &ionic->ident; 3410 unsigned int nintrs, dev_nintrs; 3411 union ionic_lif_config *lc; 3412 unsigned int ntxqs_per_lif; 3413 unsigned int nrxqs_per_lif; 3414 unsigned int neqs_per_lif; 3415 unsigned int nnqs_per_lif; 3416 unsigned int nxqs, neqs; 3417 unsigned int min_intrs; 3418 int err; 3419 3420 /* retrieve basic values from FW */ 3421 lc = &ident->lif.eth.config; 3422 dev_nintrs = le32_to_cpu(ident->dev.nintrs); 3423 neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count); 3424 nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]); 3425 ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]); 3426 nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]); 3427 3428 /* limit values to play nice with kdump */ 3429 if (is_kdump_kernel()) { 3430 dev_nintrs = 2; 3431 neqs_per_lif = 0; 3432 nnqs_per_lif = 0; 3433 ntxqs_per_lif = 1; 3434 nrxqs_per_lif = 1; 3435 } 3436 3437 /* reserve last queue id for hardware timestamping */ 3438 if (lc->features & cpu_to_le64(IONIC_ETH_HW_TIMESTAMP)) { 3439 if (ntxqs_per_lif <= 1 || nrxqs_per_lif <= 1) { 3440 lc->features &= cpu_to_le64(~IONIC_ETH_HW_TIMESTAMP); 3441 } else { 3442 ntxqs_per_lif -= 1; 3443 nrxqs_per_lif -= 1; 3444 } 3445 } 3446 3447 nxqs = min(ntxqs_per_lif, nrxqs_per_lif); 3448 nxqs = min(nxqs, num_online_cpus()); 3449 neqs = min(neqs_per_lif, num_online_cpus()); 3450 3451 try_again: 3452 /* interrupt usage: 3453 * 1 for master lif adminq/notifyq 3454 * 1 for each CPU for master lif TxRx queue pairs 3455 * whatever's left is for RDMA queues 3456 */ 3457 nintrs = 1 + nxqs + neqs; 3458 min_intrs = 2; /* adminq + 1 TxRx queue pair */ 3459 3460 if (nintrs > dev_nintrs) 3461 goto try_fewer; 3462 3463 err = ionic_bus_alloc_irq_vectors(ionic, nintrs); 3464 if (err < 0 && err != -ENOSPC) { 3465 dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err); 3466 return err; 3467 } 3468 if (err == -ENOSPC) 3469 goto try_fewer; 3470 3471 if (err != nintrs) { 3472 ionic_bus_free_irq_vectors(ionic); 3473 goto try_fewer; 3474 } 3475 3476 ionic->nnqs_per_lif = nnqs_per_lif; 3477 ionic->neqs_per_lif = neqs; 3478 ionic->ntxqs_per_lif = nxqs; 3479 ionic->nrxqs_per_lif = nxqs; 3480 ionic->nintrs = nintrs; 3481 3482 ionic_debugfs_add_sizes(ionic); 3483 3484 return 0; 3485 3486 try_fewer: 3487 if (nnqs_per_lif > 1) { 3488 nnqs_per_lif >>= 1; 3489 goto try_again; 3490 } 3491 if (neqs > 1) { 3492 neqs >>= 1; 3493 goto try_again; 3494 } 3495 if (nxqs > 1) { 3496 nxqs >>= 1; 3497 goto try_again; 3498 } 3499 dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs); 3500 return -ENOSPC; 3501 } 3502