1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/ethtool.h> 5 #include <linux/printk.h> 6 #include <linux/dynamic_debug.h> 7 #include <linux/netdevice.h> 8 #include <linux/etherdevice.h> 9 #include <linux/if_vlan.h> 10 #include <linux/rtnetlink.h> 11 #include <linux/interrupt.h> 12 #include <linux/pci.h> 13 #include <linux/cpumask.h> 14 #include <linux/crash_dump.h> 15 #include <linux/vmalloc.h> 16 17 #include "ionic.h" 18 #include "ionic_bus.h" 19 #include "ionic_dev.h" 20 #include "ionic_lif.h" 21 #include "ionic_txrx.h" 22 #include "ionic_ethtool.h" 23 #include "ionic_debugfs.h" 24 25 /* queuetype support level */ 26 static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = { 27 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */ 28 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */ 29 [IONIC_QTYPE_RXQ] = 2, /* 0 = Base version with CQ+SG support 30 * 2 = ... with CMB rings 31 */ 32 [IONIC_QTYPE_TXQ] = 3, /* 0 = Base version with CQ+SG support 33 * 1 = ... with Tx SG version 1 34 * 3 = ... with CMB rings 35 */ 36 }; 37 38 static void ionic_link_status_check(struct ionic_lif *lif); 39 static void ionic_lif_handle_fw_down(struct ionic_lif *lif); 40 static void ionic_lif_handle_fw_up(struct ionic_lif *lif); 41 static void ionic_lif_set_netdev_info(struct ionic_lif *lif); 42 43 static void ionic_txrx_deinit(struct ionic_lif *lif); 44 static int ionic_txrx_init(struct ionic_lif *lif); 45 static int ionic_start_queues(struct ionic_lif *lif); 46 static void ionic_stop_queues(struct ionic_lif *lif); 47 static void ionic_lif_queue_identify(struct ionic_lif *lif); 48 49 static void ionic_dim_work(struct work_struct *work) 50 { 51 struct dim *dim = container_of(work, struct dim, work); 52 struct dim_cq_moder cur_moder; 53 struct ionic_qcq *qcq; 54 u32 new_coal; 55 56 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 57 qcq = container_of(dim, struct ionic_qcq, dim); 58 new_coal = ionic_coal_usec_to_hw(qcq->q.lif->ionic, cur_moder.usec); 59 new_coal = new_coal ? new_coal : 1; 60 61 if (qcq->intr.dim_coal_hw != new_coal) { 62 unsigned int qi = qcq->cq.bound_q->index; 63 struct ionic_lif *lif = qcq->q.lif; 64 65 qcq->intr.dim_coal_hw = new_coal; 66 67 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 68 lif->rxqcqs[qi]->intr.index, 69 qcq->intr.dim_coal_hw); 70 } 71 72 dim->state = DIM_START_MEASURE; 73 } 74 75 static void ionic_lif_deferred_work(struct work_struct *work) 76 { 77 struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work); 78 struct ionic_deferred *def = &lif->deferred; 79 struct ionic_deferred_work *w = NULL; 80 81 do { 82 spin_lock_bh(&def->lock); 83 if (!list_empty(&def->list)) { 84 w = list_first_entry(&def->list, 85 struct ionic_deferred_work, list); 86 list_del(&w->list); 87 } 88 spin_unlock_bh(&def->lock); 89 90 if (!w) 91 break; 92 93 switch (w->type) { 94 case IONIC_DW_TYPE_RX_MODE: 95 ionic_lif_rx_mode(lif); 96 break; 97 case IONIC_DW_TYPE_LINK_STATUS: 98 ionic_link_status_check(lif); 99 break; 100 case IONIC_DW_TYPE_LIF_RESET: 101 if (w->fw_status) { 102 ionic_lif_handle_fw_up(lif); 103 } else { 104 ionic_lif_handle_fw_down(lif); 105 106 /* Fire off another watchdog to see 107 * if the FW is already back rather than 108 * waiting another whole cycle 109 */ 110 mod_timer(&lif->ionic->watchdog_timer, jiffies + 1); 111 } 112 break; 113 default: 114 break; 115 } 116 kfree(w); 117 w = NULL; 118 } while (true); 119 } 120 121 void ionic_lif_deferred_enqueue(struct ionic_deferred *def, 122 struct ionic_deferred_work *work) 123 { 124 spin_lock_bh(&def->lock); 125 list_add_tail(&work->list, &def->list); 126 spin_unlock_bh(&def->lock); 127 schedule_work(&def->work); 128 } 129 130 static void ionic_link_status_check(struct ionic_lif *lif) 131 { 132 struct net_device *netdev = lif->netdev; 133 u16 link_status; 134 bool link_up; 135 136 if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 137 return; 138 139 /* Don't put carrier back up if we're in a broken state */ 140 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) { 141 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 142 return; 143 } 144 145 link_status = le16_to_cpu(lif->info->status.link_status); 146 link_up = link_status == IONIC_PORT_OPER_STATUS_UP; 147 148 if (link_up) { 149 int err = 0; 150 151 if (netdev->flags & IFF_UP && netif_running(netdev)) { 152 mutex_lock(&lif->queue_lock); 153 err = ionic_start_queues(lif); 154 if (err && err != -EBUSY) { 155 netdev_err(netdev, 156 "Failed to start queues: %d\n", err); 157 set_bit(IONIC_LIF_F_BROKEN, lif->state); 158 netif_carrier_off(lif->netdev); 159 } 160 mutex_unlock(&lif->queue_lock); 161 } 162 163 if (!err && !netif_carrier_ok(netdev)) { 164 ionic_port_identify(lif->ionic); 165 netdev_info(netdev, "Link up - %d Gbps\n", 166 le32_to_cpu(lif->info->status.link_speed) / 1000); 167 netif_carrier_on(netdev); 168 } 169 } else { 170 if (netif_carrier_ok(netdev)) { 171 netdev_info(netdev, "Link down\n"); 172 netif_carrier_off(netdev); 173 } 174 175 if (netdev->flags & IFF_UP && netif_running(netdev)) { 176 mutex_lock(&lif->queue_lock); 177 ionic_stop_queues(lif); 178 mutex_unlock(&lif->queue_lock); 179 } 180 } 181 182 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 183 } 184 185 void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep) 186 { 187 struct ionic_deferred_work *work; 188 189 /* we only need one request outstanding at a time */ 190 if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 191 return; 192 193 if (!can_sleep) { 194 work = kzalloc(sizeof(*work), GFP_ATOMIC); 195 if (!work) { 196 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 197 return; 198 } 199 200 work->type = IONIC_DW_TYPE_LINK_STATUS; 201 ionic_lif_deferred_enqueue(&lif->deferred, work); 202 } else { 203 ionic_link_status_check(lif); 204 } 205 } 206 207 static void ionic_napi_deadline(struct timer_list *timer) 208 { 209 struct ionic_qcq *qcq = container_of(timer, struct ionic_qcq, napi_deadline); 210 211 napi_schedule(&qcq->napi); 212 } 213 214 static irqreturn_t ionic_isr(int irq, void *data) 215 { 216 struct napi_struct *napi = data; 217 218 napi_schedule_irqoff(napi); 219 220 return IRQ_HANDLED; 221 } 222 223 static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq) 224 { 225 struct ionic_intr_info *intr = &qcq->intr; 226 struct device *dev = lif->ionic->dev; 227 struct ionic_queue *q = &qcq->q; 228 const char *name; 229 230 if (lif->registered) 231 name = lif->netdev->name; 232 else 233 name = dev_name(dev); 234 235 snprintf(intr->name, sizeof(intr->name), 236 "%s-%s-%s", IONIC_DRV_NAME, name, q->name); 237 238 return devm_request_irq(dev, intr->vector, ionic_isr, 239 0, intr->name, &qcq->napi); 240 } 241 242 static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) 243 { 244 struct ionic *ionic = lif->ionic; 245 int index; 246 247 index = find_first_zero_bit(ionic->intrs, ionic->nintrs); 248 if (index == ionic->nintrs) { 249 netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n", 250 __func__, index, ionic->nintrs); 251 return -ENOSPC; 252 } 253 254 set_bit(index, ionic->intrs); 255 ionic_intr_init(&ionic->idev, intr, index); 256 257 return 0; 258 } 259 260 static void ionic_intr_free(struct ionic *ionic, int index) 261 { 262 if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < ionic->nintrs) 263 clear_bit(index, ionic->intrs); 264 } 265 266 static int ionic_qcq_enable(struct ionic_qcq *qcq) 267 { 268 struct ionic_queue *q = &qcq->q; 269 struct ionic_lif *lif = q->lif; 270 struct ionic_dev *idev; 271 struct device *dev; 272 273 struct ionic_admin_ctx ctx = { 274 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 275 .cmd.q_control = { 276 .opcode = IONIC_CMD_Q_CONTROL, 277 .lif_index = cpu_to_le16(lif->index), 278 .type = q->type, 279 .index = cpu_to_le32(q->index), 280 .oper = IONIC_Q_ENABLE, 281 }, 282 }; 283 int ret; 284 285 idev = &lif->ionic->idev; 286 dev = lif->ionic->dev; 287 288 dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n", 289 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 290 291 if (qcq->flags & IONIC_QCQ_F_INTR) 292 ionic_intr_clean(idev->intr_ctrl, qcq->intr.index); 293 294 ret = ionic_adminq_post_wait(lif, &ctx); 295 if (ret) 296 return ret; 297 298 if (qcq->napi.poll) 299 napi_enable(&qcq->napi); 300 301 if (qcq->flags & IONIC_QCQ_F_INTR) { 302 irq_set_affinity_hint(qcq->intr.vector, 303 &qcq->intr.affinity_mask); 304 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 305 IONIC_INTR_MASK_CLEAR); 306 } 307 308 return 0; 309 } 310 311 static int ionic_qcq_disable(struct ionic_lif *lif, struct ionic_qcq *qcq, int fw_err) 312 { 313 struct ionic_queue *q; 314 315 struct ionic_admin_ctx ctx = { 316 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 317 .cmd.q_control = { 318 .opcode = IONIC_CMD_Q_CONTROL, 319 .oper = IONIC_Q_DISABLE, 320 }, 321 }; 322 323 if (!qcq) { 324 netdev_err(lif->netdev, "%s: bad qcq\n", __func__); 325 return -ENXIO; 326 } 327 328 q = &qcq->q; 329 330 if (qcq->flags & IONIC_QCQ_F_INTR) { 331 struct ionic_dev *idev = &lif->ionic->idev; 332 333 cancel_work_sync(&qcq->dim.work); 334 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 335 IONIC_INTR_MASK_SET); 336 synchronize_irq(qcq->intr.vector); 337 irq_set_affinity_hint(qcq->intr.vector, NULL); 338 napi_disable(&qcq->napi); 339 del_timer_sync(&qcq->napi_deadline); 340 } 341 342 /* If there was a previous fw communcation error, don't bother with 343 * sending the adminq command and just return the same error value. 344 */ 345 if (fw_err == -ETIMEDOUT || fw_err == -ENXIO) 346 return fw_err; 347 348 ctx.cmd.q_control.lif_index = cpu_to_le16(lif->index); 349 ctx.cmd.q_control.type = q->type; 350 ctx.cmd.q_control.index = cpu_to_le32(q->index); 351 dev_dbg(lif->ionic->dev, "q_disable.index %d q_disable.qtype %d\n", 352 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 353 354 return ionic_adminq_post_wait(lif, &ctx); 355 } 356 357 static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq) 358 { 359 struct ionic_dev *idev = &lif->ionic->idev; 360 361 if (!qcq) 362 return; 363 364 if (!(qcq->flags & IONIC_QCQ_F_INITED)) 365 return; 366 367 if (qcq->flags & IONIC_QCQ_F_INTR) { 368 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 369 IONIC_INTR_MASK_SET); 370 netif_napi_del(&qcq->napi); 371 } 372 373 qcq->flags &= ~IONIC_QCQ_F_INITED; 374 } 375 376 static void ionic_qcq_intr_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 377 { 378 if (!(qcq->flags & IONIC_QCQ_F_INTR) || qcq->intr.vector == 0) 379 return; 380 381 irq_set_affinity_hint(qcq->intr.vector, NULL); 382 devm_free_irq(lif->ionic->dev, qcq->intr.vector, &qcq->napi); 383 qcq->intr.vector = 0; 384 ionic_intr_free(lif->ionic, qcq->intr.index); 385 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 386 } 387 388 static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 389 { 390 struct device *dev = lif->ionic->dev; 391 392 if (!qcq) 393 return; 394 395 ionic_debugfs_del_qcq(qcq); 396 397 if (qcq->q_base) { 398 dma_free_coherent(dev, qcq->q_size, qcq->q_base, qcq->q_base_pa); 399 qcq->q_base = NULL; 400 qcq->q_base_pa = 0; 401 } 402 403 if (qcq->cmb_q_base) { 404 iounmap(qcq->cmb_q_base); 405 ionic_put_cmb(lif, qcq->cmb_pgid, qcq->cmb_order); 406 qcq->cmb_pgid = 0; 407 qcq->cmb_order = 0; 408 qcq->cmb_q_base = NULL; 409 qcq->cmb_q_base_pa = 0; 410 } 411 412 if (qcq->cq_base) { 413 dma_free_coherent(dev, qcq->cq_size, qcq->cq_base, qcq->cq_base_pa); 414 qcq->cq_base = NULL; 415 qcq->cq_base_pa = 0; 416 } 417 418 if (qcq->sg_base) { 419 dma_free_coherent(dev, qcq->sg_size, qcq->sg_base, qcq->sg_base_pa); 420 qcq->sg_base = NULL; 421 qcq->sg_base_pa = 0; 422 } 423 424 ionic_qcq_intr_free(lif, qcq); 425 426 if (qcq->cq.info) { 427 vfree(qcq->cq.info); 428 qcq->cq.info = NULL; 429 } 430 if (qcq->q.info) { 431 vfree(qcq->q.info); 432 qcq->q.info = NULL; 433 } 434 } 435 436 static void ionic_qcqs_free(struct ionic_lif *lif) 437 { 438 struct device *dev = lif->ionic->dev; 439 struct ionic_qcq *adminqcq; 440 unsigned long irqflags; 441 442 if (lif->notifyqcq) { 443 ionic_qcq_free(lif, lif->notifyqcq); 444 devm_kfree(dev, lif->notifyqcq); 445 lif->notifyqcq = NULL; 446 } 447 448 if (lif->adminqcq) { 449 spin_lock_irqsave(&lif->adminq_lock, irqflags); 450 adminqcq = READ_ONCE(lif->adminqcq); 451 lif->adminqcq = NULL; 452 spin_unlock_irqrestore(&lif->adminq_lock, irqflags); 453 if (adminqcq) { 454 ionic_qcq_free(lif, adminqcq); 455 devm_kfree(dev, adminqcq); 456 } 457 } 458 459 if (lif->rxqcqs) { 460 devm_kfree(dev, lif->rxqstats); 461 lif->rxqstats = NULL; 462 devm_kfree(dev, lif->rxqcqs); 463 lif->rxqcqs = NULL; 464 } 465 466 if (lif->txqcqs) { 467 devm_kfree(dev, lif->txqstats); 468 lif->txqstats = NULL; 469 devm_kfree(dev, lif->txqcqs); 470 lif->txqcqs = NULL; 471 } 472 } 473 474 static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq, 475 struct ionic_qcq *n_qcq) 476 { 477 if (WARN_ON(n_qcq->flags & IONIC_QCQ_F_INTR)) { 478 ionic_intr_free(n_qcq->cq.lif->ionic, n_qcq->intr.index); 479 n_qcq->flags &= ~IONIC_QCQ_F_INTR; 480 } 481 482 n_qcq->intr.vector = src_qcq->intr.vector; 483 n_qcq->intr.index = src_qcq->intr.index; 484 n_qcq->napi_qcq = src_qcq->napi_qcq; 485 } 486 487 static int ionic_alloc_qcq_interrupt(struct ionic_lif *lif, struct ionic_qcq *qcq) 488 { 489 int err; 490 491 if (!(qcq->flags & IONIC_QCQ_F_INTR)) { 492 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 493 return 0; 494 } 495 496 err = ionic_intr_alloc(lif, &qcq->intr); 497 if (err) { 498 netdev_warn(lif->netdev, "no intr for %s: %d\n", 499 qcq->q.name, err); 500 goto err_out; 501 } 502 503 err = ionic_bus_get_irq(lif->ionic, qcq->intr.index); 504 if (err < 0) { 505 netdev_warn(lif->netdev, "no vector for %s: %d\n", 506 qcq->q.name, err); 507 goto err_out_free_intr; 508 } 509 qcq->intr.vector = err; 510 ionic_intr_mask_assert(lif->ionic->idev.intr_ctrl, qcq->intr.index, 511 IONIC_INTR_MASK_SET); 512 513 err = ionic_request_irq(lif, qcq); 514 if (err) { 515 netdev_warn(lif->netdev, "irq request failed %d\n", err); 516 goto err_out_free_intr; 517 } 518 519 /* try to get the irq on the local numa node first */ 520 qcq->intr.cpu = cpumask_local_spread(qcq->intr.index, 521 dev_to_node(lif->ionic->dev)); 522 if (qcq->intr.cpu != -1) 523 cpumask_set_cpu(qcq->intr.cpu, &qcq->intr.affinity_mask); 524 525 netdev_dbg(lif->netdev, "%s: Interrupt index %d\n", qcq->q.name, qcq->intr.index); 526 return 0; 527 528 err_out_free_intr: 529 ionic_intr_free(lif->ionic, qcq->intr.index); 530 err_out: 531 return err; 532 } 533 534 static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type, 535 unsigned int index, 536 const char *name, unsigned int flags, 537 unsigned int num_descs, unsigned int desc_size, 538 unsigned int cq_desc_size, 539 unsigned int sg_desc_size, 540 unsigned int pid, struct ionic_qcq **qcq) 541 { 542 struct ionic_dev *idev = &lif->ionic->idev; 543 struct device *dev = lif->ionic->dev; 544 void *q_base, *cq_base, *sg_base; 545 dma_addr_t cq_base_pa = 0; 546 dma_addr_t sg_base_pa = 0; 547 dma_addr_t q_base_pa = 0; 548 struct ionic_qcq *new; 549 int err; 550 551 *qcq = NULL; 552 553 new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL); 554 if (!new) { 555 netdev_err(lif->netdev, "Cannot allocate queue structure\n"); 556 err = -ENOMEM; 557 goto err_out; 558 } 559 560 new->q.dev = dev; 561 new->flags = flags; 562 563 new->q.info = vzalloc(num_descs * sizeof(*new->q.info)); 564 if (!new->q.info) { 565 netdev_err(lif->netdev, "Cannot allocate queue info\n"); 566 err = -ENOMEM; 567 goto err_out_free_qcq; 568 } 569 570 new->q.type = type; 571 new->q.max_sg_elems = lif->qtype_info[type].max_sg_elems; 572 573 err = ionic_q_init(lif, idev, &new->q, index, name, num_descs, 574 desc_size, sg_desc_size, pid); 575 if (err) { 576 netdev_err(lif->netdev, "Cannot initialize queue\n"); 577 goto err_out_free_q_info; 578 } 579 580 err = ionic_alloc_qcq_interrupt(lif, new); 581 if (err) 582 goto err_out; 583 584 new->cq.info = vzalloc(num_descs * sizeof(*new->cq.info)); 585 if (!new->cq.info) { 586 netdev_err(lif->netdev, "Cannot allocate completion queue info\n"); 587 err = -ENOMEM; 588 goto err_out_free_irq; 589 } 590 591 err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size); 592 if (err) { 593 netdev_err(lif->netdev, "Cannot initialize completion queue\n"); 594 goto err_out_free_cq_info; 595 } 596 597 if (flags & IONIC_QCQ_F_NOTIFYQ) { 598 int q_size; 599 600 /* q & cq need to be contiguous in NotifyQ, so alloc it all in q 601 * and don't alloc qc. We leave new->qc_size and new->qc_base 602 * as 0 to be sure we don't try to free it later. 603 */ 604 q_size = ALIGN(num_descs * desc_size, PAGE_SIZE); 605 new->q_size = PAGE_SIZE + q_size + 606 ALIGN(num_descs * cq_desc_size, PAGE_SIZE); 607 new->q_base = dma_alloc_coherent(dev, new->q_size, 608 &new->q_base_pa, GFP_KERNEL); 609 if (!new->q_base) { 610 netdev_err(lif->netdev, "Cannot allocate qcq DMA memory\n"); 611 err = -ENOMEM; 612 goto err_out_free_cq_info; 613 } 614 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE); 615 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 616 ionic_q_map(&new->q, q_base, q_base_pa); 617 618 cq_base = PTR_ALIGN(q_base + q_size, PAGE_SIZE); 619 cq_base_pa = ALIGN(new->q_base_pa + q_size, PAGE_SIZE); 620 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 621 ionic_cq_bind(&new->cq, &new->q); 622 } else { 623 /* regular DMA q descriptors */ 624 new->q_size = PAGE_SIZE + (num_descs * desc_size); 625 new->q_base = dma_alloc_coherent(dev, new->q_size, &new->q_base_pa, 626 GFP_KERNEL); 627 if (!new->q_base) { 628 netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n"); 629 err = -ENOMEM; 630 goto err_out_free_cq_info; 631 } 632 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE); 633 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 634 ionic_q_map(&new->q, q_base, q_base_pa); 635 636 if (flags & IONIC_QCQ_F_CMB_RINGS) { 637 /* on-chip CMB q descriptors */ 638 new->cmb_q_size = num_descs * desc_size; 639 new->cmb_order = order_base_2(new->cmb_q_size / PAGE_SIZE); 640 641 err = ionic_get_cmb(lif, &new->cmb_pgid, &new->cmb_q_base_pa, 642 new->cmb_order); 643 if (err) { 644 netdev_err(lif->netdev, 645 "Cannot allocate queue order %d from cmb: err %d\n", 646 new->cmb_order, err); 647 goto err_out_free_q; 648 } 649 650 new->cmb_q_base = ioremap_wc(new->cmb_q_base_pa, new->cmb_q_size); 651 if (!new->cmb_q_base) { 652 netdev_err(lif->netdev, "Cannot map queue from cmb\n"); 653 ionic_put_cmb(lif, new->cmb_pgid, new->cmb_order); 654 err = -ENOMEM; 655 goto err_out_free_q; 656 } 657 658 new->cmb_q_base_pa -= idev->phy_cmb_pages; 659 ionic_q_cmb_map(&new->q, new->cmb_q_base, new->cmb_q_base_pa); 660 } 661 662 /* cq DMA descriptors */ 663 new->cq_size = PAGE_SIZE + (num_descs * cq_desc_size); 664 new->cq_base = dma_alloc_coherent(dev, new->cq_size, &new->cq_base_pa, 665 GFP_KERNEL); 666 if (!new->cq_base) { 667 netdev_err(lif->netdev, "Cannot allocate cq DMA memory\n"); 668 err = -ENOMEM; 669 goto err_out_free_q; 670 } 671 cq_base = PTR_ALIGN(new->cq_base, PAGE_SIZE); 672 cq_base_pa = ALIGN(new->cq_base_pa, PAGE_SIZE); 673 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 674 ionic_cq_bind(&new->cq, &new->q); 675 } 676 677 if (flags & IONIC_QCQ_F_SG) { 678 new->sg_size = PAGE_SIZE + (num_descs * sg_desc_size); 679 new->sg_base = dma_alloc_coherent(dev, new->sg_size, &new->sg_base_pa, 680 GFP_KERNEL); 681 if (!new->sg_base) { 682 netdev_err(lif->netdev, "Cannot allocate sg DMA memory\n"); 683 err = -ENOMEM; 684 goto err_out_free_cq; 685 } 686 sg_base = PTR_ALIGN(new->sg_base, PAGE_SIZE); 687 sg_base_pa = ALIGN(new->sg_base_pa, PAGE_SIZE); 688 ionic_q_sg_map(&new->q, sg_base, sg_base_pa); 689 } 690 691 INIT_WORK(&new->dim.work, ionic_dim_work); 692 new->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 693 694 *qcq = new; 695 696 return 0; 697 698 err_out_free_cq: 699 dma_free_coherent(dev, new->cq_size, new->cq_base, new->cq_base_pa); 700 err_out_free_q: 701 if (new->cmb_q_base) { 702 iounmap(new->cmb_q_base); 703 ionic_put_cmb(lif, new->cmb_pgid, new->cmb_order); 704 } 705 dma_free_coherent(dev, new->q_size, new->q_base, new->q_base_pa); 706 err_out_free_cq_info: 707 vfree(new->cq.info); 708 err_out_free_irq: 709 if (flags & IONIC_QCQ_F_INTR) { 710 devm_free_irq(dev, new->intr.vector, &new->napi); 711 ionic_intr_free(lif->ionic, new->intr.index); 712 } 713 err_out_free_q_info: 714 vfree(new->q.info); 715 err_out_free_qcq: 716 devm_kfree(dev, new); 717 err_out: 718 dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err); 719 return err; 720 } 721 722 static int ionic_qcqs_alloc(struct ionic_lif *lif) 723 { 724 struct device *dev = lif->ionic->dev; 725 unsigned int flags; 726 int err; 727 728 flags = IONIC_QCQ_F_INTR; 729 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags, 730 IONIC_ADMINQ_LENGTH, 731 sizeof(struct ionic_admin_cmd), 732 sizeof(struct ionic_admin_comp), 733 0, lif->kern_pid, &lif->adminqcq); 734 if (err) 735 return err; 736 ionic_debugfs_add_qcq(lif, lif->adminqcq); 737 738 if (lif->ionic->nnqs_per_lif) { 739 flags = IONIC_QCQ_F_NOTIFYQ; 740 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq", 741 flags, IONIC_NOTIFYQ_LENGTH, 742 sizeof(struct ionic_notifyq_cmd), 743 sizeof(union ionic_notifyq_comp), 744 0, lif->kern_pid, &lif->notifyqcq); 745 if (err) 746 goto err_out; 747 ionic_debugfs_add_qcq(lif, lif->notifyqcq); 748 749 /* Let the notifyq ride on the adminq interrupt */ 750 ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq); 751 } 752 753 err = -ENOMEM; 754 lif->txqcqs = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif, 755 sizeof(*lif->txqcqs), GFP_KERNEL); 756 if (!lif->txqcqs) 757 goto err_out; 758 lif->rxqcqs = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif, 759 sizeof(*lif->rxqcqs), GFP_KERNEL); 760 if (!lif->rxqcqs) 761 goto err_out; 762 763 lif->txqstats = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif + 1, 764 sizeof(*lif->txqstats), GFP_KERNEL); 765 if (!lif->txqstats) 766 goto err_out; 767 lif->rxqstats = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif + 1, 768 sizeof(*lif->rxqstats), GFP_KERNEL); 769 if (!lif->rxqstats) 770 goto err_out; 771 772 return 0; 773 774 err_out: 775 ionic_qcqs_free(lif); 776 return err; 777 } 778 779 static void ionic_qcq_sanitize(struct ionic_qcq *qcq) 780 { 781 qcq->q.tail_idx = 0; 782 qcq->q.head_idx = 0; 783 qcq->cq.tail_idx = 0; 784 qcq->cq.done_color = 1; 785 memset(qcq->q_base, 0, qcq->q_size); 786 if (qcq->cmb_q_base) 787 memset_io(qcq->cmb_q_base, 0, qcq->cmb_q_size); 788 memset(qcq->cq_base, 0, qcq->cq_size); 789 memset(qcq->sg_base, 0, qcq->sg_size); 790 } 791 792 static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 793 { 794 struct device *dev = lif->ionic->dev; 795 struct ionic_queue *q = &qcq->q; 796 struct ionic_cq *cq = &qcq->cq; 797 struct ionic_admin_ctx ctx = { 798 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 799 .cmd.q_init = { 800 .opcode = IONIC_CMD_Q_INIT, 801 .lif_index = cpu_to_le16(lif->index), 802 .type = q->type, 803 .ver = lif->qtype_info[q->type].version, 804 .index = cpu_to_le32(q->index), 805 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 806 IONIC_QINIT_F_SG), 807 .intr_index = cpu_to_le16(qcq->intr.index), 808 .pid = cpu_to_le16(q->pid), 809 .ring_size = ilog2(q->num_descs), 810 .ring_base = cpu_to_le64(q->base_pa), 811 .cq_ring_base = cpu_to_le64(cq->base_pa), 812 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 813 .features = cpu_to_le64(q->features), 814 }, 815 }; 816 int err; 817 818 if (qcq->flags & IONIC_QCQ_F_CMB_RINGS) { 819 ctx.cmd.q_init.flags |= cpu_to_le16(IONIC_QINIT_F_CMB); 820 ctx.cmd.q_init.ring_base = cpu_to_le64(qcq->cmb_q_base_pa); 821 } 822 823 dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid); 824 dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index); 825 dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 826 dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 827 dev_dbg(dev, "txq_init.cq_ring_base 0x%llx\n", ctx.cmd.q_init.cq_ring_base); 828 dev_dbg(dev, "txq_init.sg_ring_base 0x%llx\n", ctx.cmd.q_init.sg_ring_base); 829 dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 830 dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver); 831 dev_dbg(dev, "txq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 832 833 ionic_qcq_sanitize(qcq); 834 835 err = ionic_adminq_post_wait(lif, &ctx); 836 if (err) 837 return err; 838 839 q->hw_type = ctx.comp.q_init.hw_type; 840 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 841 q->dbval = IONIC_DBELL_QID(q->hw_index); 842 843 dev_dbg(dev, "txq->hw_type %d\n", q->hw_type); 844 dev_dbg(dev, "txq->hw_index %d\n", q->hw_index); 845 846 q->dbell_deadline = IONIC_TX_DOORBELL_DEADLINE; 847 q->dbell_jiffies = jiffies; 848 849 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) { 850 netif_napi_add(lif->netdev, &qcq->napi, ionic_tx_napi); 851 qcq->napi_qcq = qcq; 852 timer_setup(&qcq->napi_deadline, ionic_napi_deadline, 0); 853 } 854 855 qcq->flags |= IONIC_QCQ_F_INITED; 856 857 return 0; 858 } 859 860 static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 861 { 862 struct device *dev = lif->ionic->dev; 863 struct ionic_queue *q = &qcq->q; 864 struct ionic_cq *cq = &qcq->cq; 865 struct ionic_admin_ctx ctx = { 866 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 867 .cmd.q_init = { 868 .opcode = IONIC_CMD_Q_INIT, 869 .lif_index = cpu_to_le16(lif->index), 870 .type = q->type, 871 .ver = lif->qtype_info[q->type].version, 872 .index = cpu_to_le32(q->index), 873 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 874 IONIC_QINIT_F_SG), 875 .intr_index = cpu_to_le16(cq->bound_intr->index), 876 .pid = cpu_to_le16(q->pid), 877 .ring_size = ilog2(q->num_descs), 878 .ring_base = cpu_to_le64(q->base_pa), 879 .cq_ring_base = cpu_to_le64(cq->base_pa), 880 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 881 .features = cpu_to_le64(q->features), 882 }, 883 }; 884 int err; 885 886 if (qcq->flags & IONIC_QCQ_F_CMB_RINGS) { 887 ctx.cmd.q_init.flags |= cpu_to_le16(IONIC_QINIT_F_CMB); 888 ctx.cmd.q_init.ring_base = cpu_to_le64(qcq->cmb_q_base_pa); 889 } 890 891 dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid); 892 dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index); 893 dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 894 dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 895 dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 896 dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver); 897 dev_dbg(dev, "rxq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 898 899 ionic_qcq_sanitize(qcq); 900 901 err = ionic_adminq_post_wait(lif, &ctx); 902 if (err) 903 return err; 904 905 q->hw_type = ctx.comp.q_init.hw_type; 906 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 907 q->dbval = IONIC_DBELL_QID(q->hw_index); 908 909 dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type); 910 dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index); 911 912 q->dbell_deadline = IONIC_RX_MIN_DOORBELL_DEADLINE; 913 q->dbell_jiffies = jiffies; 914 915 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 916 netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi); 917 else 918 netif_napi_add(lif->netdev, &qcq->napi, ionic_txrx_napi); 919 920 qcq->napi_qcq = qcq; 921 timer_setup(&qcq->napi_deadline, ionic_napi_deadline, 0); 922 923 qcq->flags |= IONIC_QCQ_F_INITED; 924 925 return 0; 926 } 927 928 int ionic_lif_create_hwstamp_txq(struct ionic_lif *lif) 929 { 930 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz; 931 unsigned int txq_i, flags; 932 struct ionic_qcq *txq; 933 u64 features; 934 int err; 935 936 if (lif->hwstamp_txq) 937 return 0; 938 939 features = IONIC_Q_F_2X_CQ_DESC | IONIC_TXQ_F_HWSTAMP; 940 941 num_desc = IONIC_MIN_TXRX_DESC; 942 desc_sz = sizeof(struct ionic_txq_desc); 943 comp_sz = 2 * sizeof(struct ionic_txq_comp); 944 945 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 946 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == sizeof(struct ionic_txq_sg_desc_v1)) 947 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 948 else 949 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 950 951 txq_i = lif->ionic->ntxqs_per_lif; 952 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 953 954 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, txq_i, "hwstamp_tx", flags, 955 num_desc, desc_sz, comp_sz, sg_desc_sz, 956 lif->kern_pid, &txq); 957 if (err) 958 goto err_qcq_alloc; 959 960 txq->q.features = features; 961 962 ionic_link_qcq_interrupts(lif->adminqcq, txq); 963 ionic_debugfs_add_qcq(lif, txq); 964 965 lif->hwstamp_txq = txq; 966 967 if (netif_running(lif->netdev)) { 968 err = ionic_lif_txq_init(lif, txq); 969 if (err) 970 goto err_qcq_init; 971 972 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 973 err = ionic_qcq_enable(txq); 974 if (err) 975 goto err_qcq_enable; 976 } 977 } 978 979 return 0; 980 981 err_qcq_enable: 982 ionic_lif_qcq_deinit(lif, txq); 983 err_qcq_init: 984 lif->hwstamp_txq = NULL; 985 ionic_debugfs_del_qcq(txq); 986 ionic_qcq_free(lif, txq); 987 devm_kfree(lif->ionic->dev, txq); 988 err_qcq_alloc: 989 return err; 990 } 991 992 int ionic_lif_create_hwstamp_rxq(struct ionic_lif *lif) 993 { 994 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz; 995 unsigned int rxq_i, flags; 996 struct ionic_qcq *rxq; 997 u64 features; 998 int err; 999 1000 if (lif->hwstamp_rxq) 1001 return 0; 1002 1003 features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP; 1004 1005 num_desc = IONIC_MIN_TXRX_DESC; 1006 desc_sz = sizeof(struct ionic_rxq_desc); 1007 comp_sz = 2 * sizeof(struct ionic_rxq_comp); 1008 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 1009 1010 rxq_i = lif->ionic->nrxqs_per_lif; 1011 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG; 1012 1013 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, rxq_i, "hwstamp_rx", flags, 1014 num_desc, desc_sz, comp_sz, sg_desc_sz, 1015 lif->kern_pid, &rxq); 1016 if (err) 1017 goto err_qcq_alloc; 1018 1019 rxq->q.features = features; 1020 1021 ionic_link_qcq_interrupts(lif->adminqcq, rxq); 1022 ionic_debugfs_add_qcq(lif, rxq); 1023 1024 lif->hwstamp_rxq = rxq; 1025 1026 if (netif_running(lif->netdev)) { 1027 err = ionic_lif_rxq_init(lif, rxq); 1028 if (err) 1029 goto err_qcq_init; 1030 1031 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 1032 ionic_rx_fill(&rxq->q); 1033 err = ionic_qcq_enable(rxq); 1034 if (err) 1035 goto err_qcq_enable; 1036 } 1037 } 1038 1039 return 0; 1040 1041 err_qcq_enable: 1042 ionic_lif_qcq_deinit(lif, rxq); 1043 err_qcq_init: 1044 lif->hwstamp_rxq = NULL; 1045 ionic_debugfs_del_qcq(rxq); 1046 ionic_qcq_free(lif, rxq); 1047 devm_kfree(lif->ionic->dev, rxq); 1048 err_qcq_alloc: 1049 return err; 1050 } 1051 1052 int ionic_lif_config_hwstamp_rxq_all(struct ionic_lif *lif, bool rx_all) 1053 { 1054 struct ionic_queue_params qparam; 1055 1056 ionic_init_queue_params(lif, &qparam); 1057 1058 if (rx_all) 1059 qparam.rxq_features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP; 1060 else 1061 qparam.rxq_features = 0; 1062 1063 /* if we're not running, just set the values and return */ 1064 if (!netif_running(lif->netdev)) { 1065 lif->rxq_features = qparam.rxq_features; 1066 return 0; 1067 } 1068 1069 return ionic_reconfigure_queues(lif, &qparam); 1070 } 1071 1072 int ionic_lif_set_hwstamp_txmode(struct ionic_lif *lif, u16 txstamp_mode) 1073 { 1074 struct ionic_admin_ctx ctx = { 1075 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1076 .cmd.lif_setattr = { 1077 .opcode = IONIC_CMD_LIF_SETATTR, 1078 .index = cpu_to_le16(lif->index), 1079 .attr = IONIC_LIF_ATTR_TXSTAMP, 1080 .txstamp_mode = cpu_to_le16(txstamp_mode), 1081 }, 1082 }; 1083 1084 return ionic_adminq_post_wait(lif, &ctx); 1085 } 1086 1087 static void ionic_lif_del_hwstamp_rxfilt(struct ionic_lif *lif) 1088 { 1089 struct ionic_admin_ctx ctx = { 1090 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1091 .cmd.rx_filter_del = { 1092 .opcode = IONIC_CMD_RX_FILTER_DEL, 1093 .lif_index = cpu_to_le16(lif->index), 1094 }, 1095 }; 1096 struct ionic_rx_filter *f; 1097 u32 filter_id; 1098 int err; 1099 1100 spin_lock_bh(&lif->rx_filters.lock); 1101 1102 f = ionic_rx_filter_rxsteer(lif); 1103 if (!f) { 1104 spin_unlock_bh(&lif->rx_filters.lock); 1105 return; 1106 } 1107 1108 filter_id = f->filter_id; 1109 ionic_rx_filter_free(lif, f); 1110 1111 spin_unlock_bh(&lif->rx_filters.lock); 1112 1113 netdev_dbg(lif->netdev, "rx_filter del RXSTEER (id %d)\n", filter_id); 1114 1115 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(filter_id); 1116 1117 err = ionic_adminq_post_wait(lif, &ctx); 1118 if (err && err != -EEXIST) 1119 netdev_dbg(lif->netdev, "failed to delete rx_filter RXSTEER (id %d)\n", filter_id); 1120 } 1121 1122 static int ionic_lif_add_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class) 1123 { 1124 struct ionic_admin_ctx ctx = { 1125 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1126 .cmd.rx_filter_add = { 1127 .opcode = IONIC_CMD_RX_FILTER_ADD, 1128 .lif_index = cpu_to_le16(lif->index), 1129 .match = cpu_to_le16(IONIC_RX_FILTER_STEER_PKTCLASS), 1130 .pkt_class = cpu_to_le64(pkt_class), 1131 }, 1132 }; 1133 u8 qtype; 1134 u32 qid; 1135 int err; 1136 1137 if (!lif->hwstamp_rxq) 1138 return -EINVAL; 1139 1140 qtype = lif->hwstamp_rxq->q.type; 1141 ctx.cmd.rx_filter_add.qtype = qtype; 1142 1143 qid = lif->hwstamp_rxq->q.index; 1144 ctx.cmd.rx_filter_add.qid = cpu_to_le32(qid); 1145 1146 netdev_dbg(lif->netdev, "rx_filter add RXSTEER\n"); 1147 err = ionic_adminq_post_wait(lif, &ctx); 1148 if (err && err != -EEXIST) 1149 return err; 1150 1151 spin_lock_bh(&lif->rx_filters.lock); 1152 err = ionic_rx_filter_save(lif, 0, qid, 0, &ctx, IONIC_FILTER_STATE_SYNCED); 1153 spin_unlock_bh(&lif->rx_filters.lock); 1154 1155 return err; 1156 } 1157 1158 int ionic_lif_set_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class) 1159 { 1160 ionic_lif_del_hwstamp_rxfilt(lif); 1161 1162 if (!pkt_class) 1163 return 0; 1164 1165 return ionic_lif_add_hwstamp_rxfilt(lif, pkt_class); 1166 } 1167 1168 static bool ionic_notifyq_service(struct ionic_cq *cq, 1169 struct ionic_cq_info *cq_info) 1170 { 1171 union ionic_notifyq_comp *comp = cq_info->cq_desc; 1172 struct ionic_deferred_work *work; 1173 struct net_device *netdev; 1174 struct ionic_queue *q; 1175 struct ionic_lif *lif; 1176 u64 eid; 1177 1178 q = cq->bound_q; 1179 lif = q->info[0].cb_arg; 1180 netdev = lif->netdev; 1181 eid = le64_to_cpu(comp->event.eid); 1182 1183 /* Have we run out of new completions to process? */ 1184 if ((s64)(eid - lif->last_eid) <= 0) 1185 return false; 1186 1187 lif->last_eid = eid; 1188 1189 dev_dbg(lif->ionic->dev, "notifyq event:\n"); 1190 dynamic_hex_dump("event ", DUMP_PREFIX_OFFSET, 16, 1, 1191 comp, sizeof(*comp), true); 1192 1193 switch (le16_to_cpu(comp->event.ecode)) { 1194 case IONIC_EVENT_LINK_CHANGE: 1195 ionic_link_status_check_request(lif, CAN_NOT_SLEEP); 1196 break; 1197 case IONIC_EVENT_RESET: 1198 if (lif->ionic->idev.fw_status_ready && 1199 !test_bit(IONIC_LIF_F_FW_RESET, lif->state) && 1200 !test_and_set_bit(IONIC_LIF_F_FW_STOPPING, lif->state)) { 1201 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1202 if (!work) { 1203 netdev_err(lif->netdev, "Reset event dropped\n"); 1204 clear_bit(IONIC_LIF_F_FW_STOPPING, lif->state); 1205 } else { 1206 work->type = IONIC_DW_TYPE_LIF_RESET; 1207 ionic_lif_deferred_enqueue(&lif->deferred, work); 1208 } 1209 } 1210 break; 1211 default: 1212 netdev_warn(netdev, "Notifyq event ecode=%d eid=%lld\n", 1213 comp->event.ecode, eid); 1214 break; 1215 } 1216 1217 return true; 1218 } 1219 1220 static bool ionic_adminq_service(struct ionic_cq *cq, 1221 struct ionic_cq_info *cq_info) 1222 { 1223 struct ionic_admin_comp *comp = cq_info->cq_desc; 1224 1225 if (!color_match(comp->color, cq->done_color)) 1226 return false; 1227 1228 ionic_q_service(cq->bound_q, cq_info, le16_to_cpu(comp->comp_index)); 1229 1230 return true; 1231 } 1232 1233 static int ionic_adminq_napi(struct napi_struct *napi, int budget) 1234 { 1235 struct ionic_intr_info *intr = napi_to_cq(napi)->bound_intr; 1236 struct ionic_lif *lif = napi_to_cq(napi)->lif; 1237 struct ionic_dev *idev = &lif->ionic->idev; 1238 unsigned long irqflags; 1239 unsigned int flags = 0; 1240 bool resched = false; 1241 int rx_work = 0; 1242 int tx_work = 0; 1243 int n_work = 0; 1244 int a_work = 0; 1245 int work_done; 1246 int credits; 1247 1248 if (lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED) 1249 n_work = ionic_cq_service(&lif->notifyqcq->cq, budget, 1250 ionic_notifyq_service, NULL, NULL); 1251 1252 spin_lock_irqsave(&lif->adminq_lock, irqflags); 1253 if (lif->adminqcq && lif->adminqcq->flags & IONIC_QCQ_F_INITED) 1254 a_work = ionic_cq_service(&lif->adminqcq->cq, budget, 1255 ionic_adminq_service, NULL, NULL); 1256 spin_unlock_irqrestore(&lif->adminq_lock, irqflags); 1257 1258 if (lif->hwstamp_rxq) 1259 rx_work = ionic_cq_service(&lif->hwstamp_rxq->cq, budget, 1260 ionic_rx_service, NULL, NULL); 1261 1262 if (lif->hwstamp_txq) 1263 tx_work = ionic_cq_service(&lif->hwstamp_txq->cq, budget, 1264 ionic_tx_service, NULL, NULL); 1265 1266 work_done = max(max(n_work, a_work), max(rx_work, tx_work)); 1267 if (work_done < budget && napi_complete_done(napi, work_done)) { 1268 flags |= IONIC_INTR_CRED_UNMASK; 1269 intr->rearm_count++; 1270 } 1271 1272 if (work_done || flags) { 1273 flags |= IONIC_INTR_CRED_RESET_COALESCE; 1274 credits = n_work + a_work + rx_work + tx_work; 1275 ionic_intr_credits(idev->intr_ctrl, intr->index, credits, flags); 1276 } 1277 1278 if (!a_work && ionic_adminq_poke_doorbell(&lif->adminqcq->q)) 1279 resched = true; 1280 if (lif->hwstamp_rxq && !rx_work && ionic_rxq_poke_doorbell(&lif->hwstamp_rxq->q)) 1281 resched = true; 1282 if (lif->hwstamp_txq && !tx_work && ionic_txq_poke_doorbell(&lif->hwstamp_txq->q)) 1283 resched = true; 1284 if (resched) 1285 mod_timer(&lif->adminqcq->napi_deadline, 1286 jiffies + IONIC_NAPI_DEADLINE); 1287 1288 return work_done; 1289 } 1290 1291 void ionic_get_stats64(struct net_device *netdev, 1292 struct rtnl_link_stats64 *ns) 1293 { 1294 struct ionic_lif *lif = netdev_priv(netdev); 1295 struct ionic_lif_stats *ls; 1296 1297 memset(ns, 0, sizeof(*ns)); 1298 ls = &lif->info->stats; 1299 1300 ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) + 1301 le64_to_cpu(ls->rx_mcast_packets) + 1302 le64_to_cpu(ls->rx_bcast_packets); 1303 1304 ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) + 1305 le64_to_cpu(ls->tx_mcast_packets) + 1306 le64_to_cpu(ls->tx_bcast_packets); 1307 1308 ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) + 1309 le64_to_cpu(ls->rx_mcast_bytes) + 1310 le64_to_cpu(ls->rx_bcast_bytes); 1311 1312 ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) + 1313 le64_to_cpu(ls->tx_mcast_bytes) + 1314 le64_to_cpu(ls->tx_bcast_bytes); 1315 1316 ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) + 1317 le64_to_cpu(ls->rx_mcast_drop_packets) + 1318 le64_to_cpu(ls->rx_bcast_drop_packets); 1319 1320 ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) + 1321 le64_to_cpu(ls->tx_mcast_drop_packets) + 1322 le64_to_cpu(ls->tx_bcast_drop_packets); 1323 1324 ns->multicast = le64_to_cpu(ls->rx_mcast_packets); 1325 1326 ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty); 1327 1328 ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) + 1329 le64_to_cpu(ls->rx_queue_disabled) + 1330 le64_to_cpu(ls->rx_desc_fetch_error) + 1331 le64_to_cpu(ls->rx_desc_data_error); 1332 1333 ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) + 1334 le64_to_cpu(ls->tx_queue_disabled) + 1335 le64_to_cpu(ls->tx_desc_fetch_error) + 1336 le64_to_cpu(ls->tx_desc_data_error); 1337 1338 ns->rx_errors = ns->rx_over_errors + 1339 ns->rx_missed_errors; 1340 1341 ns->tx_errors = ns->tx_aborted_errors; 1342 } 1343 1344 static int ionic_addr_add(struct net_device *netdev, const u8 *addr) 1345 { 1346 return ionic_lif_list_addr(netdev_priv(netdev), addr, ADD_ADDR); 1347 } 1348 1349 static int ionic_addr_del(struct net_device *netdev, const u8 *addr) 1350 { 1351 /* Don't delete our own address from the uc list */ 1352 if (ether_addr_equal(addr, netdev->dev_addr)) 1353 return 0; 1354 1355 return ionic_lif_list_addr(netdev_priv(netdev), addr, DEL_ADDR); 1356 } 1357 1358 void ionic_lif_rx_mode(struct ionic_lif *lif) 1359 { 1360 struct net_device *netdev = lif->netdev; 1361 unsigned int nfilters; 1362 unsigned int nd_flags; 1363 char buf[128]; 1364 u16 rx_mode; 1365 int i; 1366 #define REMAIN(__x) (sizeof(buf) - (__x)) 1367 1368 mutex_lock(&lif->config_lock); 1369 1370 /* grab the flags once for local use */ 1371 nd_flags = netdev->flags; 1372 1373 rx_mode = IONIC_RX_MODE_F_UNICAST; 1374 rx_mode |= (nd_flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0; 1375 rx_mode |= (nd_flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0; 1376 rx_mode |= (nd_flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0; 1377 rx_mode |= (nd_flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0; 1378 1379 /* sync the filters */ 1380 ionic_rx_filter_sync(lif); 1381 1382 /* check for overflow state 1383 * if so, we track that we overflowed and enable NIC PROMISC 1384 * else if the overflow is set and not needed 1385 * we remove our overflow flag and check the netdev flags 1386 * to see if we can disable NIC PROMISC 1387 */ 1388 nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters); 1389 1390 if (((lif->nucast + lif->nmcast) >= nfilters) || 1391 (lif->max_vlans && lif->nvlans >= lif->max_vlans)) { 1392 rx_mode |= IONIC_RX_MODE_F_PROMISC; 1393 rx_mode |= IONIC_RX_MODE_F_ALLMULTI; 1394 } else { 1395 if (!(nd_flags & IFF_PROMISC)) 1396 rx_mode &= ~IONIC_RX_MODE_F_PROMISC; 1397 if (!(nd_flags & IFF_ALLMULTI)) 1398 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI; 1399 } 1400 1401 i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:", 1402 lif->rx_mode, rx_mode); 1403 if (rx_mode & IONIC_RX_MODE_F_UNICAST) 1404 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST"); 1405 if (rx_mode & IONIC_RX_MODE_F_MULTICAST) 1406 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST"); 1407 if (rx_mode & IONIC_RX_MODE_F_BROADCAST) 1408 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST"); 1409 if (rx_mode & IONIC_RX_MODE_F_PROMISC) 1410 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC"); 1411 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI) 1412 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI"); 1413 if (rx_mode & IONIC_RX_MODE_F_RDMA_SNIFFER) 1414 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_RDMA_SNIFFER"); 1415 netdev_dbg(netdev, "lif%d %s\n", lif->index, buf); 1416 1417 if (lif->rx_mode != rx_mode) { 1418 struct ionic_admin_ctx ctx = { 1419 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1420 .cmd.rx_mode_set = { 1421 .opcode = IONIC_CMD_RX_MODE_SET, 1422 .lif_index = cpu_to_le16(lif->index), 1423 }, 1424 }; 1425 int err; 1426 1427 ctx.cmd.rx_mode_set.rx_mode = cpu_to_le16(rx_mode); 1428 err = ionic_adminq_post_wait(lif, &ctx); 1429 if (err) 1430 netdev_warn(netdev, "set rx_mode 0x%04x failed: %d\n", 1431 rx_mode, err); 1432 else 1433 lif->rx_mode = rx_mode; 1434 } 1435 1436 mutex_unlock(&lif->config_lock); 1437 } 1438 1439 static void ionic_ndo_set_rx_mode(struct net_device *netdev) 1440 { 1441 struct ionic_lif *lif = netdev_priv(netdev); 1442 struct ionic_deferred_work *work; 1443 1444 /* Sync the kernel filter list with the driver filter list */ 1445 __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del); 1446 __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del); 1447 1448 /* Shove off the rest of the rxmode work to the work task 1449 * which will include syncing the filters to the firmware. 1450 */ 1451 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1452 if (!work) { 1453 netdev_err(lif->netdev, "rxmode change dropped\n"); 1454 return; 1455 } 1456 work->type = IONIC_DW_TYPE_RX_MODE; 1457 netdev_dbg(lif->netdev, "deferred: rx_mode\n"); 1458 ionic_lif_deferred_enqueue(&lif->deferred, work); 1459 } 1460 1461 static __le64 ionic_netdev_features_to_nic(netdev_features_t features) 1462 { 1463 u64 wanted = 0; 1464 1465 if (features & NETIF_F_HW_VLAN_CTAG_TX) 1466 wanted |= IONIC_ETH_HW_VLAN_TX_TAG; 1467 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1468 wanted |= IONIC_ETH_HW_VLAN_RX_STRIP; 1469 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1470 wanted |= IONIC_ETH_HW_VLAN_RX_FILTER; 1471 if (features & NETIF_F_RXHASH) 1472 wanted |= IONIC_ETH_HW_RX_HASH; 1473 if (features & NETIF_F_RXCSUM) 1474 wanted |= IONIC_ETH_HW_RX_CSUM; 1475 if (features & NETIF_F_SG) 1476 wanted |= IONIC_ETH_HW_TX_SG; 1477 if (features & NETIF_F_HW_CSUM) 1478 wanted |= IONIC_ETH_HW_TX_CSUM; 1479 if (features & NETIF_F_TSO) 1480 wanted |= IONIC_ETH_HW_TSO; 1481 if (features & NETIF_F_TSO6) 1482 wanted |= IONIC_ETH_HW_TSO_IPV6; 1483 if (features & NETIF_F_TSO_ECN) 1484 wanted |= IONIC_ETH_HW_TSO_ECN; 1485 if (features & NETIF_F_GSO_GRE) 1486 wanted |= IONIC_ETH_HW_TSO_GRE; 1487 if (features & NETIF_F_GSO_GRE_CSUM) 1488 wanted |= IONIC_ETH_HW_TSO_GRE_CSUM; 1489 if (features & NETIF_F_GSO_IPXIP4) 1490 wanted |= IONIC_ETH_HW_TSO_IPXIP4; 1491 if (features & NETIF_F_GSO_IPXIP6) 1492 wanted |= IONIC_ETH_HW_TSO_IPXIP6; 1493 if (features & NETIF_F_GSO_UDP_TUNNEL) 1494 wanted |= IONIC_ETH_HW_TSO_UDP; 1495 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) 1496 wanted |= IONIC_ETH_HW_TSO_UDP_CSUM; 1497 1498 return cpu_to_le64(wanted); 1499 } 1500 1501 static int ionic_set_nic_features(struct ionic_lif *lif, 1502 netdev_features_t features) 1503 { 1504 struct device *dev = lif->ionic->dev; 1505 struct ionic_admin_ctx ctx = { 1506 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1507 .cmd.lif_setattr = { 1508 .opcode = IONIC_CMD_LIF_SETATTR, 1509 .index = cpu_to_le16(lif->index), 1510 .attr = IONIC_LIF_ATTR_FEATURES, 1511 }, 1512 }; 1513 u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG | 1514 IONIC_ETH_HW_VLAN_RX_STRIP | 1515 IONIC_ETH_HW_VLAN_RX_FILTER; 1516 u64 old_hw_features; 1517 int err; 1518 1519 ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features); 1520 1521 if (lif->phc) 1522 ctx.cmd.lif_setattr.features |= cpu_to_le64(IONIC_ETH_HW_TIMESTAMP); 1523 1524 err = ionic_adminq_post_wait(lif, &ctx); 1525 if (err) 1526 return err; 1527 1528 old_hw_features = lif->hw_features; 1529 lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features & 1530 ctx.comp.lif_setattr.features); 1531 1532 if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH) 1533 ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1534 1535 if ((vlan_flags & le64_to_cpu(ctx.cmd.lif_setattr.features)) && 1536 !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features))) 1537 dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n"); 1538 1539 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1540 dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n"); 1541 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1542 dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n"); 1543 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1544 dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n"); 1545 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1546 dev_dbg(dev, "feature ETH_HW_RX_HASH\n"); 1547 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1548 dev_dbg(dev, "feature ETH_HW_TX_SG\n"); 1549 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1550 dev_dbg(dev, "feature ETH_HW_TX_CSUM\n"); 1551 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1552 dev_dbg(dev, "feature ETH_HW_RX_CSUM\n"); 1553 if (lif->hw_features & IONIC_ETH_HW_TSO) 1554 dev_dbg(dev, "feature ETH_HW_TSO\n"); 1555 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1556 dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n"); 1557 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1558 dev_dbg(dev, "feature ETH_HW_TSO_ECN\n"); 1559 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1560 dev_dbg(dev, "feature ETH_HW_TSO_GRE\n"); 1561 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1562 dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n"); 1563 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1564 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n"); 1565 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1566 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n"); 1567 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1568 dev_dbg(dev, "feature ETH_HW_TSO_UDP\n"); 1569 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1570 dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n"); 1571 if (lif->hw_features & IONIC_ETH_HW_TIMESTAMP) 1572 dev_dbg(dev, "feature ETH_HW_TIMESTAMP\n"); 1573 1574 return 0; 1575 } 1576 1577 static int ionic_init_nic_features(struct ionic_lif *lif) 1578 { 1579 struct net_device *netdev = lif->netdev; 1580 netdev_features_t features; 1581 int err; 1582 1583 /* set up what we expect to support by default */ 1584 features = NETIF_F_HW_VLAN_CTAG_TX | 1585 NETIF_F_HW_VLAN_CTAG_RX | 1586 NETIF_F_HW_VLAN_CTAG_FILTER | 1587 NETIF_F_SG | 1588 NETIF_F_HW_CSUM | 1589 NETIF_F_RXCSUM | 1590 NETIF_F_TSO | 1591 NETIF_F_TSO6 | 1592 NETIF_F_TSO_ECN | 1593 NETIF_F_GSO_GRE | 1594 NETIF_F_GSO_GRE_CSUM | 1595 NETIF_F_GSO_IPXIP4 | 1596 NETIF_F_GSO_IPXIP6 | 1597 NETIF_F_GSO_UDP_TUNNEL | 1598 NETIF_F_GSO_UDP_TUNNEL_CSUM; 1599 1600 if (lif->nxqs > 1) 1601 features |= NETIF_F_RXHASH; 1602 1603 err = ionic_set_nic_features(lif, features); 1604 if (err) 1605 return err; 1606 1607 /* tell the netdev what we actually can support */ 1608 netdev->features |= NETIF_F_HIGHDMA; 1609 1610 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1611 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 1612 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1613 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 1614 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1615 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1616 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1617 netdev->hw_features |= NETIF_F_RXHASH; 1618 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1619 netdev->hw_features |= NETIF_F_SG; 1620 1621 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1622 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 1623 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1624 netdev->hw_enc_features |= NETIF_F_RXCSUM; 1625 if (lif->hw_features & IONIC_ETH_HW_TSO) 1626 netdev->hw_enc_features |= NETIF_F_TSO; 1627 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1628 netdev->hw_enc_features |= NETIF_F_TSO6; 1629 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1630 netdev->hw_enc_features |= NETIF_F_TSO_ECN; 1631 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1632 netdev->hw_enc_features |= NETIF_F_GSO_GRE; 1633 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1634 netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM; 1635 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1636 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4; 1637 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1638 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6; 1639 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1640 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL; 1641 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1642 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 1643 1644 netdev->hw_features |= netdev->hw_enc_features; 1645 netdev->features |= netdev->hw_features; 1646 netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES; 1647 1648 netdev->priv_flags |= IFF_UNICAST_FLT | 1649 IFF_LIVE_ADDR_CHANGE; 1650 1651 return 0; 1652 } 1653 1654 static int ionic_set_features(struct net_device *netdev, 1655 netdev_features_t features) 1656 { 1657 struct ionic_lif *lif = netdev_priv(netdev); 1658 int err; 1659 1660 netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n", 1661 __func__, (u64)lif->netdev->features, (u64)features); 1662 1663 err = ionic_set_nic_features(lif, features); 1664 1665 return err; 1666 } 1667 1668 static int ionic_set_attr_mac(struct ionic_lif *lif, u8 *mac) 1669 { 1670 struct ionic_admin_ctx ctx = { 1671 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1672 .cmd.lif_setattr = { 1673 .opcode = IONIC_CMD_LIF_SETATTR, 1674 .index = cpu_to_le16(lif->index), 1675 .attr = IONIC_LIF_ATTR_MAC, 1676 }, 1677 }; 1678 1679 ether_addr_copy(ctx.cmd.lif_setattr.mac, mac); 1680 return ionic_adminq_post_wait(lif, &ctx); 1681 } 1682 1683 static int ionic_get_attr_mac(struct ionic_lif *lif, u8 *mac_addr) 1684 { 1685 struct ionic_admin_ctx ctx = { 1686 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1687 .cmd.lif_getattr = { 1688 .opcode = IONIC_CMD_LIF_GETATTR, 1689 .index = cpu_to_le16(lif->index), 1690 .attr = IONIC_LIF_ATTR_MAC, 1691 }, 1692 }; 1693 int err; 1694 1695 err = ionic_adminq_post_wait(lif, &ctx); 1696 if (err) 1697 return err; 1698 1699 ether_addr_copy(mac_addr, ctx.comp.lif_getattr.mac); 1700 return 0; 1701 } 1702 1703 static int ionic_program_mac(struct ionic_lif *lif, u8 *mac) 1704 { 1705 u8 get_mac[ETH_ALEN]; 1706 int err; 1707 1708 err = ionic_set_attr_mac(lif, mac); 1709 if (err) 1710 return err; 1711 1712 err = ionic_get_attr_mac(lif, get_mac); 1713 if (err) 1714 return err; 1715 1716 /* To deal with older firmware that silently ignores the set attr mac: 1717 * doesn't actually change the mac and doesn't return an error, so we 1718 * do the get attr to verify whether or not the set actually happened 1719 */ 1720 if (!ether_addr_equal(get_mac, mac)) 1721 return 1; 1722 1723 return 0; 1724 } 1725 1726 static int ionic_set_mac_address(struct net_device *netdev, void *sa) 1727 { 1728 struct ionic_lif *lif = netdev_priv(netdev); 1729 struct sockaddr *addr = sa; 1730 u8 *mac; 1731 int err; 1732 1733 mac = (u8 *)addr->sa_data; 1734 if (ether_addr_equal(netdev->dev_addr, mac)) 1735 return 0; 1736 1737 err = ionic_program_mac(lif, mac); 1738 if (err < 0) 1739 return err; 1740 1741 if (err > 0) 1742 netdev_dbg(netdev, "%s: SET and GET ATTR Mac are not equal-due to old FW running\n", 1743 __func__); 1744 1745 err = eth_prepare_mac_addr_change(netdev, addr); 1746 if (err) 1747 return err; 1748 1749 if (!is_zero_ether_addr(netdev->dev_addr)) { 1750 netdev_info(netdev, "deleting mac addr %pM\n", 1751 netdev->dev_addr); 1752 ionic_lif_addr_del(netdev_priv(netdev), netdev->dev_addr); 1753 } 1754 1755 eth_commit_mac_addr_change(netdev, addr); 1756 netdev_info(netdev, "updating mac addr %pM\n", mac); 1757 1758 return ionic_lif_addr_add(netdev_priv(netdev), mac); 1759 } 1760 1761 static void ionic_stop_queues_reconfig(struct ionic_lif *lif) 1762 { 1763 /* Stop and clean the queues before reconfiguration */ 1764 netif_device_detach(lif->netdev); 1765 ionic_stop_queues(lif); 1766 ionic_txrx_deinit(lif); 1767 } 1768 1769 static int ionic_start_queues_reconfig(struct ionic_lif *lif) 1770 { 1771 int err; 1772 1773 /* Re-init the queues after reconfiguration */ 1774 1775 /* The only way txrx_init can fail here is if communication 1776 * with FW is suddenly broken. There's not much we can do 1777 * at this point - error messages have already been printed, 1778 * so we can continue on and the user can eventually do a 1779 * DOWN and UP to try to reset and clear the issue. 1780 */ 1781 err = ionic_txrx_init(lif); 1782 ionic_link_status_check_request(lif, CAN_NOT_SLEEP); 1783 netif_device_attach(lif->netdev); 1784 1785 return err; 1786 } 1787 1788 static int ionic_change_mtu(struct net_device *netdev, int new_mtu) 1789 { 1790 struct ionic_lif *lif = netdev_priv(netdev); 1791 struct ionic_admin_ctx ctx = { 1792 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1793 .cmd.lif_setattr = { 1794 .opcode = IONIC_CMD_LIF_SETATTR, 1795 .index = cpu_to_le16(lif->index), 1796 .attr = IONIC_LIF_ATTR_MTU, 1797 .mtu = cpu_to_le32(new_mtu), 1798 }, 1799 }; 1800 int err; 1801 1802 err = ionic_adminq_post_wait(lif, &ctx); 1803 if (err) 1804 return err; 1805 1806 /* if we're not running, nothing more to do */ 1807 if (!netif_running(netdev)) { 1808 netdev->mtu = new_mtu; 1809 return 0; 1810 } 1811 1812 mutex_lock(&lif->queue_lock); 1813 ionic_stop_queues_reconfig(lif); 1814 netdev->mtu = new_mtu; 1815 err = ionic_start_queues_reconfig(lif); 1816 mutex_unlock(&lif->queue_lock); 1817 1818 return err; 1819 } 1820 1821 static void ionic_tx_timeout_work(struct work_struct *ws) 1822 { 1823 struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work); 1824 1825 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 1826 return; 1827 1828 /* if we were stopped before this scheduled job was launched, 1829 * don't bother the queues as they are already stopped. 1830 */ 1831 if (!netif_running(lif->netdev)) 1832 return; 1833 1834 mutex_lock(&lif->queue_lock); 1835 ionic_stop_queues_reconfig(lif); 1836 ionic_start_queues_reconfig(lif); 1837 mutex_unlock(&lif->queue_lock); 1838 } 1839 1840 static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1841 { 1842 struct ionic_lif *lif = netdev_priv(netdev); 1843 1844 netdev_info(lif->netdev, "Tx Timeout triggered - txq %d\n", txqueue); 1845 schedule_work(&lif->tx_timeout_work); 1846 } 1847 1848 static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, 1849 u16 vid) 1850 { 1851 struct ionic_lif *lif = netdev_priv(netdev); 1852 int err; 1853 1854 err = ionic_lif_vlan_add(lif, vid); 1855 if (err) 1856 return err; 1857 1858 ionic_lif_rx_mode(lif); 1859 1860 return 0; 1861 } 1862 1863 static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, 1864 u16 vid) 1865 { 1866 struct ionic_lif *lif = netdev_priv(netdev); 1867 int err; 1868 1869 err = ionic_lif_vlan_del(lif, vid); 1870 if (err) 1871 return err; 1872 1873 ionic_lif_rx_mode(lif); 1874 1875 return 0; 1876 } 1877 1878 int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types, 1879 const u8 *key, const u32 *indir) 1880 { 1881 struct ionic_admin_ctx ctx = { 1882 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1883 .cmd.lif_setattr = { 1884 .opcode = IONIC_CMD_LIF_SETATTR, 1885 .attr = IONIC_LIF_ATTR_RSS, 1886 .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa), 1887 }, 1888 }; 1889 unsigned int i, tbl_sz; 1890 1891 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) { 1892 lif->rss_types = types; 1893 ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types); 1894 } 1895 1896 if (key) 1897 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE); 1898 1899 if (indir) { 1900 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1901 for (i = 0; i < tbl_sz; i++) 1902 lif->rss_ind_tbl[i] = indir[i]; 1903 } 1904 1905 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key, 1906 IONIC_RSS_HASH_KEY_SIZE); 1907 1908 return ionic_adminq_post_wait(lif, &ctx); 1909 } 1910 1911 static int ionic_lif_rss_init(struct ionic_lif *lif) 1912 { 1913 unsigned int tbl_sz; 1914 unsigned int i; 1915 1916 lif->rss_types = IONIC_RSS_TYPE_IPV4 | 1917 IONIC_RSS_TYPE_IPV4_TCP | 1918 IONIC_RSS_TYPE_IPV4_UDP | 1919 IONIC_RSS_TYPE_IPV6 | 1920 IONIC_RSS_TYPE_IPV6_TCP | 1921 IONIC_RSS_TYPE_IPV6_UDP; 1922 1923 /* Fill indirection table with 'default' values */ 1924 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1925 for (i = 0; i < tbl_sz; i++) 1926 lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs); 1927 1928 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1929 } 1930 1931 static void ionic_lif_rss_deinit(struct ionic_lif *lif) 1932 { 1933 int tbl_sz; 1934 1935 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1936 memset(lif->rss_ind_tbl, 0, tbl_sz); 1937 memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE); 1938 1939 ionic_lif_rss_config(lif, 0x0, NULL, NULL); 1940 } 1941 1942 static void ionic_lif_quiesce(struct ionic_lif *lif) 1943 { 1944 struct ionic_admin_ctx ctx = { 1945 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1946 .cmd.lif_setattr = { 1947 .opcode = IONIC_CMD_LIF_SETATTR, 1948 .index = cpu_to_le16(lif->index), 1949 .attr = IONIC_LIF_ATTR_STATE, 1950 .state = IONIC_LIF_QUIESCE, 1951 }, 1952 }; 1953 int err; 1954 1955 err = ionic_adminq_post_wait(lif, &ctx); 1956 if (err) 1957 netdev_dbg(lif->netdev, "lif quiesce failed %d\n", err); 1958 } 1959 1960 static void ionic_txrx_disable(struct ionic_lif *lif) 1961 { 1962 unsigned int i; 1963 int err = 0; 1964 1965 if (lif->txqcqs) { 1966 for (i = 0; i < lif->nxqs; i++) 1967 err = ionic_qcq_disable(lif, lif->txqcqs[i], err); 1968 } 1969 1970 if (lif->hwstamp_txq) 1971 err = ionic_qcq_disable(lif, lif->hwstamp_txq, err); 1972 1973 if (lif->rxqcqs) { 1974 for (i = 0; i < lif->nxqs; i++) 1975 err = ionic_qcq_disable(lif, lif->rxqcqs[i], err); 1976 } 1977 1978 if (lif->hwstamp_rxq) 1979 err = ionic_qcq_disable(lif, lif->hwstamp_rxq, err); 1980 1981 ionic_lif_quiesce(lif); 1982 } 1983 1984 static void ionic_txrx_deinit(struct ionic_lif *lif) 1985 { 1986 unsigned int i; 1987 1988 if (lif->txqcqs) { 1989 for (i = 0; i < lif->nxqs && lif->txqcqs[i]; i++) { 1990 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 1991 ionic_tx_flush(&lif->txqcqs[i]->cq); 1992 ionic_tx_empty(&lif->txqcqs[i]->q); 1993 } 1994 } 1995 1996 if (lif->rxqcqs) { 1997 for (i = 0; i < lif->nxqs && lif->rxqcqs[i]; i++) { 1998 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 1999 ionic_rx_empty(&lif->rxqcqs[i]->q); 2000 } 2001 } 2002 lif->rx_mode = 0; 2003 2004 if (lif->hwstamp_txq) { 2005 ionic_lif_qcq_deinit(lif, lif->hwstamp_txq); 2006 ionic_tx_flush(&lif->hwstamp_txq->cq); 2007 ionic_tx_empty(&lif->hwstamp_txq->q); 2008 } 2009 2010 if (lif->hwstamp_rxq) { 2011 ionic_lif_qcq_deinit(lif, lif->hwstamp_rxq); 2012 ionic_rx_empty(&lif->hwstamp_rxq->q); 2013 } 2014 } 2015 2016 static void ionic_txrx_free(struct ionic_lif *lif) 2017 { 2018 unsigned int i; 2019 2020 if (lif->txqcqs) { 2021 for (i = 0; i < lif->ionic->ntxqs_per_lif && lif->txqcqs[i]; i++) { 2022 ionic_qcq_free(lif, lif->txqcqs[i]); 2023 devm_kfree(lif->ionic->dev, lif->txqcqs[i]); 2024 lif->txqcqs[i] = NULL; 2025 } 2026 } 2027 2028 if (lif->rxqcqs) { 2029 for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) { 2030 ionic_qcq_free(lif, lif->rxqcqs[i]); 2031 devm_kfree(lif->ionic->dev, lif->rxqcqs[i]); 2032 lif->rxqcqs[i] = NULL; 2033 } 2034 } 2035 2036 if (lif->hwstamp_txq) { 2037 ionic_qcq_free(lif, lif->hwstamp_txq); 2038 devm_kfree(lif->ionic->dev, lif->hwstamp_txq); 2039 lif->hwstamp_txq = NULL; 2040 } 2041 2042 if (lif->hwstamp_rxq) { 2043 ionic_qcq_free(lif, lif->hwstamp_rxq); 2044 devm_kfree(lif->ionic->dev, lif->hwstamp_rxq); 2045 lif->hwstamp_rxq = NULL; 2046 } 2047 } 2048 2049 static int ionic_txrx_alloc(struct ionic_lif *lif) 2050 { 2051 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz; 2052 unsigned int flags, i; 2053 int err = 0; 2054 2055 num_desc = lif->ntxq_descs; 2056 desc_sz = sizeof(struct ionic_txq_desc); 2057 comp_sz = sizeof(struct ionic_txq_comp); 2058 2059 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 2060 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 2061 sizeof(struct ionic_txq_sg_desc_v1)) 2062 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 2063 else 2064 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 2065 2066 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 2067 2068 if (test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state)) 2069 flags |= IONIC_QCQ_F_CMB_RINGS; 2070 2071 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 2072 flags |= IONIC_QCQ_F_INTR; 2073 2074 for (i = 0; i < lif->nxqs; i++) { 2075 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 2076 num_desc, desc_sz, comp_sz, sg_desc_sz, 2077 lif->kern_pid, &lif->txqcqs[i]); 2078 if (err) 2079 goto err_out; 2080 2081 if (flags & IONIC_QCQ_F_INTR) { 2082 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2083 lif->txqcqs[i]->intr.index, 2084 lif->tx_coalesce_hw); 2085 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 2086 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 2087 } 2088 2089 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 2090 } 2091 2092 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG | IONIC_QCQ_F_INTR; 2093 2094 if (test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state)) 2095 flags |= IONIC_QCQ_F_CMB_RINGS; 2096 2097 num_desc = lif->nrxq_descs; 2098 desc_sz = sizeof(struct ionic_rxq_desc); 2099 comp_sz = sizeof(struct ionic_rxq_comp); 2100 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 2101 2102 if (lif->rxq_features & IONIC_Q_F_2X_CQ_DESC) 2103 comp_sz *= 2; 2104 2105 for (i = 0; i < lif->nxqs; i++) { 2106 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 2107 num_desc, desc_sz, comp_sz, sg_desc_sz, 2108 lif->kern_pid, &lif->rxqcqs[i]); 2109 if (err) 2110 goto err_out; 2111 2112 lif->rxqcqs[i]->q.features = lif->rxq_features; 2113 2114 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2115 lif->rxqcqs[i]->intr.index, 2116 lif->rx_coalesce_hw); 2117 if (test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state)) 2118 lif->rxqcqs[i]->intr.dim_coal_hw = lif->rx_coalesce_hw; 2119 2120 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 2121 ionic_link_qcq_interrupts(lif->rxqcqs[i], 2122 lif->txqcqs[i]); 2123 2124 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 2125 } 2126 2127 return 0; 2128 2129 err_out: 2130 ionic_txrx_free(lif); 2131 2132 return err; 2133 } 2134 2135 static int ionic_txrx_init(struct ionic_lif *lif) 2136 { 2137 unsigned int i; 2138 int err; 2139 2140 for (i = 0; i < lif->nxqs; i++) { 2141 err = ionic_lif_txq_init(lif, lif->txqcqs[i]); 2142 if (err) 2143 goto err_out; 2144 2145 err = ionic_lif_rxq_init(lif, lif->rxqcqs[i]); 2146 if (err) { 2147 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 2148 goto err_out; 2149 } 2150 } 2151 2152 if (lif->netdev->features & NETIF_F_RXHASH) 2153 ionic_lif_rss_init(lif); 2154 2155 ionic_lif_rx_mode(lif); 2156 2157 return 0; 2158 2159 err_out: 2160 while (i--) { 2161 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 2162 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 2163 } 2164 2165 return err; 2166 } 2167 2168 static int ionic_txrx_enable(struct ionic_lif *lif) 2169 { 2170 int derr = 0; 2171 int i, err; 2172 2173 for (i = 0; i < lif->nxqs; i++) { 2174 if (!(lif->rxqcqs[i] && lif->txqcqs[i])) { 2175 dev_err(lif->ionic->dev, "%s: bad qcq %d\n", __func__, i); 2176 err = -ENXIO; 2177 goto err_out; 2178 } 2179 2180 ionic_rx_fill(&lif->rxqcqs[i]->q); 2181 err = ionic_qcq_enable(lif->rxqcqs[i]); 2182 if (err) 2183 goto err_out; 2184 2185 err = ionic_qcq_enable(lif->txqcqs[i]); 2186 if (err) { 2187 derr = ionic_qcq_disable(lif, lif->rxqcqs[i], err); 2188 goto err_out; 2189 } 2190 } 2191 2192 if (lif->hwstamp_rxq) { 2193 ionic_rx_fill(&lif->hwstamp_rxq->q); 2194 err = ionic_qcq_enable(lif->hwstamp_rxq); 2195 if (err) 2196 goto err_out_hwstamp_rx; 2197 } 2198 2199 if (lif->hwstamp_txq) { 2200 err = ionic_qcq_enable(lif->hwstamp_txq); 2201 if (err) 2202 goto err_out_hwstamp_tx; 2203 } 2204 2205 return 0; 2206 2207 err_out_hwstamp_tx: 2208 if (lif->hwstamp_rxq) 2209 derr = ionic_qcq_disable(lif, lif->hwstamp_rxq, derr); 2210 err_out_hwstamp_rx: 2211 i = lif->nxqs; 2212 err_out: 2213 while (i--) { 2214 derr = ionic_qcq_disable(lif, lif->txqcqs[i], derr); 2215 derr = ionic_qcq_disable(lif, lif->rxqcqs[i], derr); 2216 } 2217 2218 return err; 2219 } 2220 2221 static int ionic_start_queues(struct ionic_lif *lif) 2222 { 2223 int err; 2224 2225 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) 2226 return -EIO; 2227 2228 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2229 return -EBUSY; 2230 2231 if (test_and_set_bit(IONIC_LIF_F_UP, lif->state)) 2232 return 0; 2233 2234 err = ionic_txrx_enable(lif); 2235 if (err) { 2236 clear_bit(IONIC_LIF_F_UP, lif->state); 2237 return err; 2238 } 2239 netif_tx_wake_all_queues(lif->netdev); 2240 2241 return 0; 2242 } 2243 2244 static int ionic_open(struct net_device *netdev) 2245 { 2246 struct ionic_lif *lif = netdev_priv(netdev); 2247 int err; 2248 2249 /* If recovering from a broken state, clear the bit and we'll try again */ 2250 if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state)) 2251 netdev_info(netdev, "clearing broken state\n"); 2252 2253 mutex_lock(&lif->queue_lock); 2254 2255 err = ionic_txrx_alloc(lif); 2256 if (err) 2257 goto err_unlock; 2258 2259 err = ionic_txrx_init(lif); 2260 if (err) 2261 goto err_txrx_free; 2262 2263 err = netif_set_real_num_tx_queues(netdev, lif->nxqs); 2264 if (err) 2265 goto err_txrx_deinit; 2266 2267 err = netif_set_real_num_rx_queues(netdev, lif->nxqs); 2268 if (err) 2269 goto err_txrx_deinit; 2270 2271 /* don't start the queues until we have link */ 2272 if (netif_carrier_ok(netdev)) { 2273 err = ionic_start_queues(lif); 2274 if (err) 2275 goto err_txrx_deinit; 2276 } 2277 2278 /* If hardware timestamping is enabled, but the queues were freed by 2279 * ionic_stop, those need to be reallocated and initialized, too. 2280 */ 2281 ionic_lif_hwstamp_recreate_queues(lif); 2282 2283 mutex_unlock(&lif->queue_lock); 2284 2285 return 0; 2286 2287 err_txrx_deinit: 2288 ionic_txrx_deinit(lif); 2289 err_txrx_free: 2290 ionic_txrx_free(lif); 2291 err_unlock: 2292 mutex_unlock(&lif->queue_lock); 2293 return err; 2294 } 2295 2296 static void ionic_stop_queues(struct ionic_lif *lif) 2297 { 2298 if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state)) 2299 return; 2300 2301 netif_tx_disable(lif->netdev); 2302 ionic_txrx_disable(lif); 2303 } 2304 2305 static int ionic_stop(struct net_device *netdev) 2306 { 2307 struct ionic_lif *lif = netdev_priv(netdev); 2308 2309 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2310 return 0; 2311 2312 mutex_lock(&lif->queue_lock); 2313 ionic_stop_queues(lif); 2314 ionic_txrx_deinit(lif); 2315 ionic_txrx_free(lif); 2316 mutex_unlock(&lif->queue_lock); 2317 2318 return 0; 2319 } 2320 2321 static int ionic_eth_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 2322 { 2323 struct ionic_lif *lif = netdev_priv(netdev); 2324 2325 switch (cmd) { 2326 case SIOCSHWTSTAMP: 2327 return ionic_lif_hwstamp_set(lif, ifr); 2328 case SIOCGHWTSTAMP: 2329 return ionic_lif_hwstamp_get(lif, ifr); 2330 default: 2331 return -EOPNOTSUPP; 2332 } 2333 } 2334 2335 static int ionic_get_fw_vf_config(struct ionic *ionic, int vf, struct ionic_vf *vfdata) 2336 { 2337 struct ionic_vf_getattr_comp comp = { 0 }; 2338 int err; 2339 u8 attr; 2340 2341 attr = IONIC_VF_ATTR_VLAN; 2342 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp); 2343 if (err && comp.status != IONIC_RC_ENOSUPP) 2344 goto err_out; 2345 if (!err) 2346 vfdata->vlanid = comp.vlanid; 2347 2348 attr = IONIC_VF_ATTR_SPOOFCHK; 2349 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp); 2350 if (err && comp.status != IONIC_RC_ENOSUPP) 2351 goto err_out; 2352 if (!err) 2353 vfdata->spoofchk = comp.spoofchk; 2354 2355 attr = IONIC_VF_ATTR_LINKSTATE; 2356 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp); 2357 if (err && comp.status != IONIC_RC_ENOSUPP) 2358 goto err_out; 2359 if (!err) { 2360 switch (comp.linkstate) { 2361 case IONIC_VF_LINK_STATUS_UP: 2362 vfdata->linkstate = IFLA_VF_LINK_STATE_ENABLE; 2363 break; 2364 case IONIC_VF_LINK_STATUS_DOWN: 2365 vfdata->linkstate = IFLA_VF_LINK_STATE_DISABLE; 2366 break; 2367 case IONIC_VF_LINK_STATUS_AUTO: 2368 vfdata->linkstate = IFLA_VF_LINK_STATE_AUTO; 2369 break; 2370 default: 2371 dev_warn(ionic->dev, "Unexpected link state %u\n", comp.linkstate); 2372 break; 2373 } 2374 } 2375 2376 attr = IONIC_VF_ATTR_RATE; 2377 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp); 2378 if (err && comp.status != IONIC_RC_ENOSUPP) 2379 goto err_out; 2380 if (!err) 2381 vfdata->maxrate = comp.maxrate; 2382 2383 attr = IONIC_VF_ATTR_TRUST; 2384 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp); 2385 if (err && comp.status != IONIC_RC_ENOSUPP) 2386 goto err_out; 2387 if (!err) 2388 vfdata->trusted = comp.trust; 2389 2390 attr = IONIC_VF_ATTR_MAC; 2391 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp); 2392 if (err && comp.status != IONIC_RC_ENOSUPP) 2393 goto err_out; 2394 if (!err) 2395 ether_addr_copy(vfdata->macaddr, comp.macaddr); 2396 2397 err_out: 2398 if (err) 2399 dev_err(ionic->dev, "Failed to get %s for VF %d\n", 2400 ionic_vf_attr_to_str(attr), vf); 2401 2402 return err; 2403 } 2404 2405 static int ionic_get_vf_config(struct net_device *netdev, 2406 int vf, struct ifla_vf_info *ivf) 2407 { 2408 struct ionic_lif *lif = netdev_priv(netdev); 2409 struct ionic *ionic = lif->ionic; 2410 struct ionic_vf vfdata = { 0 }; 2411 int ret = 0; 2412 2413 if (!netif_device_present(netdev)) 2414 return -EBUSY; 2415 2416 down_read(&ionic->vf_op_lock); 2417 2418 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2419 ret = -EINVAL; 2420 } else { 2421 ivf->vf = vf; 2422 ivf->qos = 0; 2423 2424 ret = ionic_get_fw_vf_config(ionic, vf, &vfdata); 2425 if (!ret) { 2426 ivf->vlan = le16_to_cpu(vfdata.vlanid); 2427 ivf->spoofchk = vfdata.spoofchk; 2428 ivf->linkstate = vfdata.linkstate; 2429 ivf->max_tx_rate = le32_to_cpu(vfdata.maxrate); 2430 ivf->trusted = vfdata.trusted; 2431 ether_addr_copy(ivf->mac, vfdata.macaddr); 2432 } 2433 } 2434 2435 up_read(&ionic->vf_op_lock); 2436 return ret; 2437 } 2438 2439 static int ionic_get_vf_stats(struct net_device *netdev, int vf, 2440 struct ifla_vf_stats *vf_stats) 2441 { 2442 struct ionic_lif *lif = netdev_priv(netdev); 2443 struct ionic *ionic = lif->ionic; 2444 struct ionic_lif_stats *vs; 2445 int ret = 0; 2446 2447 if (!netif_device_present(netdev)) 2448 return -EBUSY; 2449 2450 down_read(&ionic->vf_op_lock); 2451 2452 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2453 ret = -EINVAL; 2454 } else { 2455 memset(vf_stats, 0, sizeof(*vf_stats)); 2456 vs = &ionic->vfs[vf].stats; 2457 2458 vf_stats->rx_packets = le64_to_cpu(vs->rx_ucast_packets); 2459 vf_stats->tx_packets = le64_to_cpu(vs->tx_ucast_packets); 2460 vf_stats->rx_bytes = le64_to_cpu(vs->rx_ucast_bytes); 2461 vf_stats->tx_bytes = le64_to_cpu(vs->tx_ucast_bytes); 2462 vf_stats->broadcast = le64_to_cpu(vs->rx_bcast_packets); 2463 vf_stats->multicast = le64_to_cpu(vs->rx_mcast_packets); 2464 vf_stats->rx_dropped = le64_to_cpu(vs->rx_ucast_drop_packets) + 2465 le64_to_cpu(vs->rx_mcast_drop_packets) + 2466 le64_to_cpu(vs->rx_bcast_drop_packets); 2467 vf_stats->tx_dropped = le64_to_cpu(vs->tx_ucast_drop_packets) + 2468 le64_to_cpu(vs->tx_mcast_drop_packets) + 2469 le64_to_cpu(vs->tx_bcast_drop_packets); 2470 } 2471 2472 up_read(&ionic->vf_op_lock); 2473 return ret; 2474 } 2475 2476 static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2477 { 2478 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_MAC }; 2479 struct ionic_lif *lif = netdev_priv(netdev); 2480 struct ionic *ionic = lif->ionic; 2481 int ret; 2482 2483 if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac))) 2484 return -EINVAL; 2485 2486 if (!netif_device_present(netdev)) 2487 return -EBUSY; 2488 2489 down_write(&ionic->vf_op_lock); 2490 2491 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2492 ret = -EINVAL; 2493 } else { 2494 ether_addr_copy(vfc.macaddr, mac); 2495 dev_dbg(ionic->dev, "%s: vf %d macaddr %pM\n", 2496 __func__, vf, vfc.macaddr); 2497 2498 ret = ionic_set_vf_config(ionic, vf, &vfc); 2499 if (!ret) 2500 ether_addr_copy(ionic->vfs[vf].macaddr, mac); 2501 } 2502 2503 up_write(&ionic->vf_op_lock); 2504 return ret; 2505 } 2506 2507 static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 2508 u8 qos, __be16 proto) 2509 { 2510 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_VLAN }; 2511 struct ionic_lif *lif = netdev_priv(netdev); 2512 struct ionic *ionic = lif->ionic; 2513 int ret; 2514 2515 /* until someday when we support qos */ 2516 if (qos) 2517 return -EINVAL; 2518 2519 if (vlan > 4095) 2520 return -EINVAL; 2521 2522 if (proto != htons(ETH_P_8021Q)) 2523 return -EPROTONOSUPPORT; 2524 2525 if (!netif_device_present(netdev)) 2526 return -EBUSY; 2527 2528 down_write(&ionic->vf_op_lock); 2529 2530 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2531 ret = -EINVAL; 2532 } else { 2533 vfc.vlanid = cpu_to_le16(vlan); 2534 dev_dbg(ionic->dev, "%s: vf %d vlan %d\n", 2535 __func__, vf, le16_to_cpu(vfc.vlanid)); 2536 2537 ret = ionic_set_vf_config(ionic, vf, &vfc); 2538 if (!ret) 2539 ionic->vfs[vf].vlanid = cpu_to_le16(vlan); 2540 } 2541 2542 up_write(&ionic->vf_op_lock); 2543 return ret; 2544 } 2545 2546 static int ionic_set_vf_rate(struct net_device *netdev, int vf, 2547 int tx_min, int tx_max) 2548 { 2549 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_RATE }; 2550 struct ionic_lif *lif = netdev_priv(netdev); 2551 struct ionic *ionic = lif->ionic; 2552 int ret; 2553 2554 /* setting the min just seems silly */ 2555 if (tx_min) 2556 return -EINVAL; 2557 2558 if (!netif_device_present(netdev)) 2559 return -EBUSY; 2560 2561 down_write(&ionic->vf_op_lock); 2562 2563 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2564 ret = -EINVAL; 2565 } else { 2566 vfc.maxrate = cpu_to_le32(tx_max); 2567 dev_dbg(ionic->dev, "%s: vf %d maxrate %d\n", 2568 __func__, vf, le32_to_cpu(vfc.maxrate)); 2569 2570 ret = ionic_set_vf_config(ionic, vf, &vfc); 2571 if (!ret) 2572 ionic->vfs[vf].maxrate = cpu_to_le32(tx_max); 2573 } 2574 2575 up_write(&ionic->vf_op_lock); 2576 return ret; 2577 } 2578 2579 static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set) 2580 { 2581 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_SPOOFCHK }; 2582 struct ionic_lif *lif = netdev_priv(netdev); 2583 struct ionic *ionic = lif->ionic; 2584 int ret; 2585 2586 if (!netif_device_present(netdev)) 2587 return -EBUSY; 2588 2589 down_write(&ionic->vf_op_lock); 2590 2591 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2592 ret = -EINVAL; 2593 } else { 2594 vfc.spoofchk = set; 2595 dev_dbg(ionic->dev, "%s: vf %d spoof %d\n", 2596 __func__, vf, vfc.spoofchk); 2597 2598 ret = ionic_set_vf_config(ionic, vf, &vfc); 2599 if (!ret) 2600 ionic->vfs[vf].spoofchk = set; 2601 } 2602 2603 up_write(&ionic->vf_op_lock); 2604 return ret; 2605 } 2606 2607 static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set) 2608 { 2609 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_TRUST }; 2610 struct ionic_lif *lif = netdev_priv(netdev); 2611 struct ionic *ionic = lif->ionic; 2612 int ret; 2613 2614 if (!netif_device_present(netdev)) 2615 return -EBUSY; 2616 2617 down_write(&ionic->vf_op_lock); 2618 2619 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2620 ret = -EINVAL; 2621 } else { 2622 vfc.trust = set; 2623 dev_dbg(ionic->dev, "%s: vf %d trust %d\n", 2624 __func__, vf, vfc.trust); 2625 2626 ret = ionic_set_vf_config(ionic, vf, &vfc); 2627 if (!ret) 2628 ionic->vfs[vf].trusted = set; 2629 } 2630 2631 up_write(&ionic->vf_op_lock); 2632 return ret; 2633 } 2634 2635 static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set) 2636 { 2637 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_LINKSTATE }; 2638 struct ionic_lif *lif = netdev_priv(netdev); 2639 struct ionic *ionic = lif->ionic; 2640 u8 vfls; 2641 int ret; 2642 2643 switch (set) { 2644 case IFLA_VF_LINK_STATE_ENABLE: 2645 vfls = IONIC_VF_LINK_STATUS_UP; 2646 break; 2647 case IFLA_VF_LINK_STATE_DISABLE: 2648 vfls = IONIC_VF_LINK_STATUS_DOWN; 2649 break; 2650 case IFLA_VF_LINK_STATE_AUTO: 2651 vfls = IONIC_VF_LINK_STATUS_AUTO; 2652 break; 2653 default: 2654 return -EINVAL; 2655 } 2656 2657 if (!netif_device_present(netdev)) 2658 return -EBUSY; 2659 2660 down_write(&ionic->vf_op_lock); 2661 2662 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2663 ret = -EINVAL; 2664 } else { 2665 vfc.linkstate = vfls; 2666 dev_dbg(ionic->dev, "%s: vf %d linkstate %d\n", 2667 __func__, vf, vfc.linkstate); 2668 2669 ret = ionic_set_vf_config(ionic, vf, &vfc); 2670 if (!ret) 2671 ionic->vfs[vf].linkstate = set; 2672 } 2673 2674 up_write(&ionic->vf_op_lock); 2675 return ret; 2676 } 2677 2678 static void ionic_vf_attr_replay(struct ionic_lif *lif) 2679 { 2680 struct ionic_vf_setattr_cmd vfc = { }; 2681 struct ionic *ionic = lif->ionic; 2682 struct ionic_vf *v; 2683 int i; 2684 2685 if (!ionic->vfs) 2686 return; 2687 2688 down_read(&ionic->vf_op_lock); 2689 2690 for (i = 0; i < ionic->num_vfs; i++) { 2691 v = &ionic->vfs[i]; 2692 2693 if (v->stats_pa) { 2694 vfc.attr = IONIC_VF_ATTR_STATSADDR; 2695 vfc.stats_pa = cpu_to_le64(v->stats_pa); 2696 ionic_set_vf_config(ionic, i, &vfc); 2697 vfc.stats_pa = 0; 2698 } 2699 2700 if (!is_zero_ether_addr(v->macaddr)) { 2701 vfc.attr = IONIC_VF_ATTR_MAC; 2702 ether_addr_copy(vfc.macaddr, v->macaddr); 2703 ionic_set_vf_config(ionic, i, &vfc); 2704 eth_zero_addr(vfc.macaddr); 2705 } 2706 2707 if (v->vlanid) { 2708 vfc.attr = IONIC_VF_ATTR_VLAN; 2709 vfc.vlanid = v->vlanid; 2710 ionic_set_vf_config(ionic, i, &vfc); 2711 vfc.vlanid = 0; 2712 } 2713 2714 if (v->maxrate) { 2715 vfc.attr = IONIC_VF_ATTR_RATE; 2716 vfc.maxrate = v->maxrate; 2717 ionic_set_vf_config(ionic, i, &vfc); 2718 vfc.maxrate = 0; 2719 } 2720 2721 if (v->spoofchk) { 2722 vfc.attr = IONIC_VF_ATTR_SPOOFCHK; 2723 vfc.spoofchk = v->spoofchk; 2724 ionic_set_vf_config(ionic, i, &vfc); 2725 vfc.spoofchk = 0; 2726 } 2727 2728 if (v->trusted) { 2729 vfc.attr = IONIC_VF_ATTR_TRUST; 2730 vfc.trust = v->trusted; 2731 ionic_set_vf_config(ionic, i, &vfc); 2732 vfc.trust = 0; 2733 } 2734 2735 if (v->linkstate) { 2736 vfc.attr = IONIC_VF_ATTR_LINKSTATE; 2737 vfc.linkstate = v->linkstate; 2738 ionic_set_vf_config(ionic, i, &vfc); 2739 vfc.linkstate = 0; 2740 } 2741 } 2742 2743 up_read(&ionic->vf_op_lock); 2744 2745 ionic_vf_start(ionic); 2746 } 2747 2748 static const struct net_device_ops ionic_netdev_ops = { 2749 .ndo_open = ionic_open, 2750 .ndo_stop = ionic_stop, 2751 .ndo_eth_ioctl = ionic_eth_ioctl, 2752 .ndo_start_xmit = ionic_start_xmit, 2753 .ndo_get_stats64 = ionic_get_stats64, 2754 .ndo_set_rx_mode = ionic_ndo_set_rx_mode, 2755 .ndo_set_features = ionic_set_features, 2756 .ndo_set_mac_address = ionic_set_mac_address, 2757 .ndo_validate_addr = eth_validate_addr, 2758 .ndo_tx_timeout = ionic_tx_timeout, 2759 .ndo_change_mtu = ionic_change_mtu, 2760 .ndo_vlan_rx_add_vid = ionic_vlan_rx_add_vid, 2761 .ndo_vlan_rx_kill_vid = ionic_vlan_rx_kill_vid, 2762 .ndo_set_vf_vlan = ionic_set_vf_vlan, 2763 .ndo_set_vf_trust = ionic_set_vf_trust, 2764 .ndo_set_vf_mac = ionic_set_vf_mac, 2765 .ndo_set_vf_rate = ionic_set_vf_rate, 2766 .ndo_set_vf_spoofchk = ionic_set_vf_spoofchk, 2767 .ndo_get_vf_config = ionic_get_vf_config, 2768 .ndo_set_vf_link_state = ionic_set_vf_link_state, 2769 .ndo_get_vf_stats = ionic_get_vf_stats, 2770 }; 2771 2772 static int ionic_cmb_reconfig(struct ionic_lif *lif, 2773 struct ionic_queue_params *qparam) 2774 { 2775 struct ionic_queue_params start_qparams; 2776 int err = 0; 2777 2778 /* When changing CMB queue parameters, we're using limited 2779 * on-device memory and don't have extra memory to use for 2780 * duplicate allocations, so we free it all first then 2781 * re-allocate with the new parameters. 2782 */ 2783 2784 /* Checkpoint for possible unwind */ 2785 ionic_init_queue_params(lif, &start_qparams); 2786 2787 /* Stop and free the queues */ 2788 ionic_stop_queues_reconfig(lif); 2789 ionic_txrx_free(lif); 2790 2791 /* Set up new qparams */ 2792 ionic_set_queue_params(lif, qparam); 2793 2794 if (netif_running(lif->netdev)) { 2795 /* Alloc and start the new configuration */ 2796 err = ionic_txrx_alloc(lif); 2797 if (err) { 2798 dev_warn(lif->ionic->dev, 2799 "CMB reconfig failed, restoring values: %d\n", err); 2800 2801 /* Back out the changes */ 2802 ionic_set_queue_params(lif, &start_qparams); 2803 err = ionic_txrx_alloc(lif); 2804 if (err) { 2805 dev_err(lif->ionic->dev, 2806 "CMB restore failed: %d\n", err); 2807 goto errout; 2808 } 2809 } 2810 2811 ionic_start_queues_reconfig(lif); 2812 } else { 2813 /* This was detached in ionic_stop_queues_reconfig() */ 2814 netif_device_attach(lif->netdev); 2815 } 2816 2817 errout: 2818 return err; 2819 } 2820 2821 static void ionic_swap_queues(struct ionic_qcq *a, struct ionic_qcq *b) 2822 { 2823 /* only swapping the queues, not the napi, flags, or other stuff */ 2824 swap(a->q.features, b->q.features); 2825 swap(a->q.num_descs, b->q.num_descs); 2826 swap(a->q.desc_size, b->q.desc_size); 2827 swap(a->q.base, b->q.base); 2828 swap(a->q.base_pa, b->q.base_pa); 2829 swap(a->q.info, b->q.info); 2830 swap(a->q_base, b->q_base); 2831 swap(a->q_base_pa, b->q_base_pa); 2832 swap(a->q_size, b->q_size); 2833 2834 swap(a->q.sg_desc_size, b->q.sg_desc_size); 2835 swap(a->q.sg_base, b->q.sg_base); 2836 swap(a->q.sg_base_pa, b->q.sg_base_pa); 2837 swap(a->sg_base, b->sg_base); 2838 swap(a->sg_base_pa, b->sg_base_pa); 2839 swap(a->sg_size, b->sg_size); 2840 2841 swap(a->cq.num_descs, b->cq.num_descs); 2842 swap(a->cq.desc_size, b->cq.desc_size); 2843 swap(a->cq.base, b->cq.base); 2844 swap(a->cq.base_pa, b->cq.base_pa); 2845 swap(a->cq.info, b->cq.info); 2846 swap(a->cq_base, b->cq_base); 2847 swap(a->cq_base_pa, b->cq_base_pa); 2848 swap(a->cq_size, b->cq_size); 2849 2850 ionic_debugfs_del_qcq(a); 2851 ionic_debugfs_add_qcq(a->q.lif, a); 2852 } 2853 2854 int ionic_reconfigure_queues(struct ionic_lif *lif, 2855 struct ionic_queue_params *qparam) 2856 { 2857 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz; 2858 struct ionic_qcq **tx_qcqs = NULL; 2859 struct ionic_qcq **rx_qcqs = NULL; 2860 unsigned int flags, i; 2861 int err = 0; 2862 2863 /* Are we changing q params while CMB is on */ 2864 if ((test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state) && qparam->cmb_tx) || 2865 (test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state) && qparam->cmb_rx)) 2866 return ionic_cmb_reconfig(lif, qparam); 2867 2868 /* allocate temporary qcq arrays to hold new queue structs */ 2869 if (qparam->nxqs != lif->nxqs || qparam->ntxq_descs != lif->ntxq_descs) { 2870 tx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->ntxqs_per_lif, 2871 sizeof(struct ionic_qcq *), GFP_KERNEL); 2872 if (!tx_qcqs) { 2873 err = -ENOMEM; 2874 goto err_out; 2875 } 2876 } 2877 if (qparam->nxqs != lif->nxqs || 2878 qparam->nrxq_descs != lif->nrxq_descs || 2879 qparam->rxq_features != lif->rxq_features) { 2880 rx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->nrxqs_per_lif, 2881 sizeof(struct ionic_qcq *), GFP_KERNEL); 2882 if (!rx_qcqs) { 2883 err = -ENOMEM; 2884 goto err_out; 2885 } 2886 } 2887 2888 /* allocate new desc_info and rings, but leave the interrupt setup 2889 * until later so as to not mess with the still-running queues 2890 */ 2891 if (tx_qcqs) { 2892 num_desc = qparam->ntxq_descs; 2893 desc_sz = sizeof(struct ionic_txq_desc); 2894 comp_sz = sizeof(struct ionic_txq_comp); 2895 2896 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 2897 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 2898 sizeof(struct ionic_txq_sg_desc_v1)) 2899 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 2900 else 2901 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 2902 2903 for (i = 0; i < qparam->nxqs; i++) { 2904 /* If missing, short placeholder qcq needed for swap */ 2905 if (!lif->txqcqs[i]) { 2906 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 2907 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 2908 4, desc_sz, comp_sz, sg_desc_sz, 2909 lif->kern_pid, &lif->txqcqs[i]); 2910 if (err) 2911 goto err_out; 2912 } 2913 2914 flags = lif->txqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2915 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 2916 num_desc, desc_sz, comp_sz, sg_desc_sz, 2917 lif->kern_pid, &tx_qcqs[i]); 2918 if (err) 2919 goto err_out; 2920 } 2921 } 2922 2923 if (rx_qcqs) { 2924 num_desc = qparam->nrxq_descs; 2925 desc_sz = sizeof(struct ionic_rxq_desc); 2926 comp_sz = sizeof(struct ionic_rxq_comp); 2927 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 2928 2929 if (qparam->rxq_features & IONIC_Q_F_2X_CQ_DESC) 2930 comp_sz *= 2; 2931 2932 for (i = 0; i < qparam->nxqs; i++) { 2933 /* If missing, short placeholder qcq needed for swap */ 2934 if (!lif->rxqcqs[i]) { 2935 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG; 2936 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 2937 4, desc_sz, comp_sz, sg_desc_sz, 2938 lif->kern_pid, &lif->rxqcqs[i]); 2939 if (err) 2940 goto err_out; 2941 } 2942 2943 flags = lif->rxqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2944 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 2945 num_desc, desc_sz, comp_sz, sg_desc_sz, 2946 lif->kern_pid, &rx_qcqs[i]); 2947 if (err) 2948 goto err_out; 2949 2950 rx_qcqs[i]->q.features = qparam->rxq_features; 2951 } 2952 } 2953 2954 /* stop and clean the queues */ 2955 ionic_stop_queues_reconfig(lif); 2956 2957 if (qparam->nxqs != lif->nxqs) { 2958 err = netif_set_real_num_tx_queues(lif->netdev, qparam->nxqs); 2959 if (err) 2960 goto err_out_reinit_unlock; 2961 err = netif_set_real_num_rx_queues(lif->netdev, qparam->nxqs); 2962 if (err) { 2963 netif_set_real_num_tx_queues(lif->netdev, lif->nxqs); 2964 goto err_out_reinit_unlock; 2965 } 2966 } 2967 2968 /* swap new desc_info and rings, keeping existing interrupt config */ 2969 if (tx_qcqs) { 2970 lif->ntxq_descs = qparam->ntxq_descs; 2971 for (i = 0; i < qparam->nxqs; i++) 2972 ionic_swap_queues(lif->txqcqs[i], tx_qcqs[i]); 2973 } 2974 2975 if (rx_qcqs) { 2976 lif->nrxq_descs = qparam->nrxq_descs; 2977 for (i = 0; i < qparam->nxqs; i++) 2978 ionic_swap_queues(lif->rxqcqs[i], rx_qcqs[i]); 2979 } 2980 2981 /* if we need to change the interrupt layout, this is the time */ 2982 if (qparam->intr_split != test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) || 2983 qparam->nxqs != lif->nxqs) { 2984 if (qparam->intr_split) { 2985 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 2986 } else { 2987 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 2988 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 2989 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 2990 } 2991 2992 /* Clear existing interrupt assignments. We check for NULL here 2993 * because we're checking the whole array for potential qcqs, not 2994 * just those qcqs that have just been set up. 2995 */ 2996 for (i = 0; i < lif->ionic->ntxqs_per_lif; i++) { 2997 if (lif->txqcqs[i]) 2998 ionic_qcq_intr_free(lif, lif->txqcqs[i]); 2999 if (lif->rxqcqs[i]) 3000 ionic_qcq_intr_free(lif, lif->rxqcqs[i]); 3001 } 3002 3003 /* re-assign the interrupts */ 3004 for (i = 0; i < qparam->nxqs; i++) { 3005 lif->rxqcqs[i]->flags |= IONIC_QCQ_F_INTR; 3006 err = ionic_alloc_qcq_interrupt(lif, lif->rxqcqs[i]); 3007 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 3008 lif->rxqcqs[i]->intr.index, 3009 lif->rx_coalesce_hw); 3010 3011 if (qparam->intr_split) { 3012 lif->txqcqs[i]->flags |= IONIC_QCQ_F_INTR; 3013 err = ionic_alloc_qcq_interrupt(lif, lif->txqcqs[i]); 3014 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 3015 lif->txqcqs[i]->intr.index, 3016 lif->tx_coalesce_hw); 3017 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 3018 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 3019 } else { 3020 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 3021 ionic_link_qcq_interrupts(lif->rxqcqs[i], lif->txqcqs[i]); 3022 } 3023 } 3024 } 3025 3026 /* now we can rework the debugfs mappings */ 3027 if (tx_qcqs) { 3028 for (i = 0; i < qparam->nxqs; i++) { 3029 ionic_debugfs_del_qcq(lif->txqcqs[i]); 3030 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 3031 } 3032 } 3033 3034 if (rx_qcqs) { 3035 for (i = 0; i < qparam->nxqs; i++) { 3036 ionic_debugfs_del_qcq(lif->rxqcqs[i]); 3037 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 3038 } 3039 } 3040 3041 swap(lif->nxqs, qparam->nxqs); 3042 swap(lif->rxq_features, qparam->rxq_features); 3043 3044 err_out_reinit_unlock: 3045 /* re-init the queues, but don't lose an error code */ 3046 if (err) 3047 ionic_start_queues_reconfig(lif); 3048 else 3049 err = ionic_start_queues_reconfig(lif); 3050 3051 err_out: 3052 /* free old allocs without cleaning intr */ 3053 for (i = 0; i < qparam->nxqs; i++) { 3054 if (tx_qcqs && tx_qcqs[i]) { 3055 tx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 3056 ionic_qcq_free(lif, tx_qcqs[i]); 3057 devm_kfree(lif->ionic->dev, tx_qcqs[i]); 3058 tx_qcqs[i] = NULL; 3059 } 3060 if (rx_qcqs && rx_qcqs[i]) { 3061 rx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 3062 ionic_qcq_free(lif, rx_qcqs[i]); 3063 devm_kfree(lif->ionic->dev, rx_qcqs[i]); 3064 rx_qcqs[i] = NULL; 3065 } 3066 } 3067 3068 /* free q array */ 3069 if (rx_qcqs) { 3070 devm_kfree(lif->ionic->dev, rx_qcqs); 3071 rx_qcqs = NULL; 3072 } 3073 if (tx_qcqs) { 3074 devm_kfree(lif->ionic->dev, tx_qcqs); 3075 tx_qcqs = NULL; 3076 } 3077 3078 /* clean the unused dma and info allocations when new set is smaller 3079 * than the full array, but leave the qcq shells in place 3080 */ 3081 for (i = lif->nxqs; i < lif->ionic->ntxqs_per_lif; i++) { 3082 if (lif->txqcqs && lif->txqcqs[i]) { 3083 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 3084 ionic_qcq_free(lif, lif->txqcqs[i]); 3085 } 3086 3087 if (lif->rxqcqs && lif->rxqcqs[i]) { 3088 lif->rxqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 3089 ionic_qcq_free(lif, lif->rxqcqs[i]); 3090 } 3091 } 3092 3093 if (err) 3094 netdev_info(lif->netdev, "%s: failed %d\n", __func__, err); 3095 3096 return err; 3097 } 3098 3099 int ionic_lif_alloc(struct ionic *ionic) 3100 { 3101 struct device *dev = ionic->dev; 3102 union ionic_lif_identity *lid; 3103 struct net_device *netdev; 3104 struct ionic_lif *lif; 3105 int tbl_sz; 3106 int err; 3107 3108 lid = kzalloc(sizeof(*lid), GFP_KERNEL); 3109 if (!lid) 3110 return -ENOMEM; 3111 3112 netdev = alloc_etherdev_mqs(sizeof(*lif), 3113 ionic->ntxqs_per_lif, ionic->ntxqs_per_lif); 3114 if (!netdev) { 3115 dev_err(dev, "Cannot allocate netdev, aborting\n"); 3116 err = -ENOMEM; 3117 goto err_out_free_lid; 3118 } 3119 3120 SET_NETDEV_DEV(netdev, dev); 3121 3122 lif = netdev_priv(netdev); 3123 lif->netdev = netdev; 3124 ionic->lif = lif; 3125 netdev->netdev_ops = &ionic_netdev_ops; 3126 ionic_ethtool_set_ops(netdev); 3127 3128 netdev->watchdog_timeo = 2 * HZ; 3129 netif_carrier_off(netdev); 3130 3131 lif->identity = lid; 3132 lif->lif_type = IONIC_LIF_TYPE_CLASSIC; 3133 err = ionic_lif_identify(ionic, lif->lif_type, lif->identity); 3134 if (err) { 3135 dev_err(ionic->dev, "Cannot identify type %d: %d\n", 3136 lif->lif_type, err); 3137 goto err_out_free_netdev; 3138 } 3139 lif->netdev->min_mtu = max_t(unsigned int, ETH_MIN_MTU, 3140 le32_to_cpu(lif->identity->eth.min_frame_size)); 3141 lif->netdev->max_mtu = 3142 le32_to_cpu(lif->identity->eth.max_frame_size) - ETH_HLEN - VLAN_HLEN; 3143 3144 lif->neqs = ionic->neqs_per_lif; 3145 lif->nxqs = ionic->ntxqs_per_lif; 3146 3147 lif->ionic = ionic; 3148 lif->index = 0; 3149 3150 if (is_kdump_kernel()) { 3151 lif->ntxq_descs = IONIC_MIN_TXRX_DESC; 3152 lif->nrxq_descs = IONIC_MIN_TXRX_DESC; 3153 } else { 3154 lif->ntxq_descs = IONIC_DEF_TXRX_DESC; 3155 lif->nrxq_descs = IONIC_DEF_TXRX_DESC; 3156 } 3157 3158 /* Convert the default coalesce value to actual hw resolution */ 3159 lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT; 3160 lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic, 3161 lif->rx_coalesce_usecs); 3162 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 3163 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 3164 set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 3165 set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 3166 3167 snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index); 3168 3169 mutex_init(&lif->queue_lock); 3170 mutex_init(&lif->config_lock); 3171 3172 spin_lock_init(&lif->adminq_lock); 3173 3174 spin_lock_init(&lif->deferred.lock); 3175 INIT_LIST_HEAD(&lif->deferred.list); 3176 INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work); 3177 3178 /* allocate lif info */ 3179 lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE); 3180 lif->info = dma_alloc_coherent(dev, lif->info_sz, 3181 &lif->info_pa, GFP_KERNEL); 3182 if (!lif->info) { 3183 dev_err(dev, "Failed to allocate lif info, aborting\n"); 3184 err = -ENOMEM; 3185 goto err_out_free_mutex; 3186 } 3187 3188 ionic_debugfs_add_lif(lif); 3189 3190 /* allocate control queues and txrx queue arrays */ 3191 ionic_lif_queue_identify(lif); 3192 err = ionic_qcqs_alloc(lif); 3193 if (err) 3194 goto err_out_free_lif_info; 3195 3196 /* allocate rss indirection table */ 3197 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 3198 lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz; 3199 lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz, 3200 &lif->rss_ind_tbl_pa, 3201 GFP_KERNEL); 3202 3203 if (!lif->rss_ind_tbl) { 3204 err = -ENOMEM; 3205 dev_err(dev, "Failed to allocate rss indirection table, aborting\n"); 3206 goto err_out_free_qcqs; 3207 } 3208 netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE); 3209 3210 ionic_lif_alloc_phc(lif); 3211 3212 return 0; 3213 3214 err_out_free_qcqs: 3215 ionic_qcqs_free(lif); 3216 err_out_free_lif_info: 3217 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 3218 lif->info = NULL; 3219 lif->info_pa = 0; 3220 err_out_free_mutex: 3221 mutex_destroy(&lif->config_lock); 3222 mutex_destroy(&lif->queue_lock); 3223 err_out_free_netdev: 3224 free_netdev(lif->netdev); 3225 lif = NULL; 3226 err_out_free_lid: 3227 kfree(lid); 3228 3229 return err; 3230 } 3231 3232 static void ionic_lif_reset(struct ionic_lif *lif) 3233 { 3234 struct ionic_dev *idev = &lif->ionic->idev; 3235 3236 mutex_lock(&lif->ionic->dev_cmd_lock); 3237 ionic_dev_cmd_lif_reset(idev, lif->index); 3238 ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 3239 mutex_unlock(&lif->ionic->dev_cmd_lock); 3240 } 3241 3242 static void ionic_lif_handle_fw_down(struct ionic_lif *lif) 3243 { 3244 struct ionic *ionic = lif->ionic; 3245 3246 if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state)) 3247 return; 3248 3249 dev_info(ionic->dev, "FW Down: Stopping LIFs\n"); 3250 3251 netif_device_detach(lif->netdev); 3252 3253 mutex_lock(&lif->queue_lock); 3254 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 3255 dev_info(ionic->dev, "Surprise FW stop, stopping queues\n"); 3256 ionic_stop_queues(lif); 3257 } 3258 3259 if (netif_running(lif->netdev)) { 3260 ionic_txrx_deinit(lif); 3261 ionic_txrx_free(lif); 3262 } 3263 ionic_lif_deinit(lif); 3264 ionic_reset(ionic); 3265 ionic_qcqs_free(lif); 3266 3267 mutex_unlock(&lif->queue_lock); 3268 3269 clear_bit(IONIC_LIF_F_FW_STOPPING, lif->state); 3270 dev_info(ionic->dev, "FW Down: LIFs stopped\n"); 3271 } 3272 3273 static void ionic_lif_handle_fw_up(struct ionic_lif *lif) 3274 { 3275 struct ionic *ionic = lif->ionic; 3276 int err; 3277 3278 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 3279 return; 3280 3281 dev_info(ionic->dev, "FW Up: restarting LIFs\n"); 3282 3283 ionic_init_devinfo(ionic); 3284 err = ionic_identify(ionic); 3285 if (err) 3286 goto err_out; 3287 err = ionic_port_identify(ionic); 3288 if (err) 3289 goto err_out; 3290 err = ionic_port_init(ionic); 3291 if (err) 3292 goto err_out; 3293 3294 mutex_lock(&lif->queue_lock); 3295 3296 if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state)) 3297 dev_info(ionic->dev, "FW Up: clearing broken state\n"); 3298 3299 err = ionic_qcqs_alloc(lif); 3300 if (err) 3301 goto err_unlock; 3302 3303 err = ionic_lif_init(lif); 3304 if (err) 3305 goto err_qcqs_free; 3306 3307 ionic_vf_attr_replay(lif); 3308 3309 if (lif->registered) 3310 ionic_lif_set_netdev_info(lif); 3311 3312 ionic_rx_filter_replay(lif); 3313 3314 if (netif_running(lif->netdev)) { 3315 err = ionic_txrx_alloc(lif); 3316 if (err) 3317 goto err_lifs_deinit; 3318 3319 err = ionic_txrx_init(lif); 3320 if (err) 3321 goto err_txrx_free; 3322 } 3323 3324 mutex_unlock(&lif->queue_lock); 3325 3326 clear_bit(IONIC_LIF_F_FW_RESET, lif->state); 3327 ionic_link_status_check_request(lif, CAN_SLEEP); 3328 netif_device_attach(lif->netdev); 3329 dev_info(ionic->dev, "FW Up: LIFs restarted\n"); 3330 3331 /* restore the hardware timestamping queues */ 3332 ionic_lif_hwstamp_replay(lif); 3333 3334 return; 3335 3336 err_txrx_free: 3337 ionic_txrx_free(lif); 3338 err_lifs_deinit: 3339 ionic_lif_deinit(lif); 3340 err_qcqs_free: 3341 ionic_qcqs_free(lif); 3342 err_unlock: 3343 mutex_unlock(&lif->queue_lock); 3344 err_out: 3345 dev_err(ionic->dev, "FW Up: LIFs restart failed - err %d\n", err); 3346 } 3347 3348 void ionic_lif_free(struct ionic_lif *lif) 3349 { 3350 struct device *dev = lif->ionic->dev; 3351 3352 ionic_lif_free_phc(lif); 3353 3354 /* free rss indirection table */ 3355 dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl, 3356 lif->rss_ind_tbl_pa); 3357 lif->rss_ind_tbl = NULL; 3358 lif->rss_ind_tbl_pa = 0; 3359 3360 /* free queues */ 3361 ionic_qcqs_free(lif); 3362 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 3363 ionic_lif_reset(lif); 3364 3365 /* free lif info */ 3366 kfree(lif->identity); 3367 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 3368 lif->info = NULL; 3369 lif->info_pa = 0; 3370 3371 /* unmap doorbell page */ 3372 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 3373 lif->kern_dbpage = NULL; 3374 3375 mutex_destroy(&lif->config_lock); 3376 mutex_destroy(&lif->queue_lock); 3377 3378 /* free netdev & lif */ 3379 ionic_debugfs_del_lif(lif); 3380 free_netdev(lif->netdev); 3381 } 3382 3383 void ionic_lif_deinit(struct ionic_lif *lif) 3384 { 3385 if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state)) 3386 return; 3387 3388 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 3389 cancel_work_sync(&lif->deferred.work); 3390 cancel_work_sync(&lif->tx_timeout_work); 3391 ionic_rx_filters_deinit(lif); 3392 if (lif->netdev->features & NETIF_F_RXHASH) 3393 ionic_lif_rss_deinit(lif); 3394 } 3395 3396 napi_disable(&lif->adminqcq->napi); 3397 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 3398 ionic_lif_qcq_deinit(lif, lif->adminqcq); 3399 3400 ionic_lif_reset(lif); 3401 } 3402 3403 static int ionic_lif_adminq_init(struct ionic_lif *lif) 3404 { 3405 struct device *dev = lif->ionic->dev; 3406 struct ionic_q_init_comp comp; 3407 struct ionic_dev *idev; 3408 struct ionic_qcq *qcq; 3409 struct ionic_queue *q; 3410 int err; 3411 3412 idev = &lif->ionic->idev; 3413 qcq = lif->adminqcq; 3414 q = &qcq->q; 3415 3416 mutex_lock(&lif->ionic->dev_cmd_lock); 3417 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index); 3418 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 3419 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 3420 mutex_unlock(&lif->ionic->dev_cmd_lock); 3421 if (err) { 3422 netdev_err(lif->netdev, "adminq init failed %d\n", err); 3423 return err; 3424 } 3425 3426 q->hw_type = comp.hw_type; 3427 q->hw_index = le32_to_cpu(comp.hw_index); 3428 q->dbval = IONIC_DBELL_QID(q->hw_index); 3429 3430 dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type); 3431 dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index); 3432 3433 q->dbell_deadline = IONIC_ADMIN_DOORBELL_DEADLINE; 3434 q->dbell_jiffies = jiffies; 3435 3436 netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi); 3437 3438 qcq->napi_qcq = qcq; 3439 timer_setup(&qcq->napi_deadline, ionic_napi_deadline, 0); 3440 3441 napi_enable(&qcq->napi); 3442 3443 if (qcq->flags & IONIC_QCQ_F_INTR) 3444 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 3445 IONIC_INTR_MASK_CLEAR); 3446 3447 qcq->flags |= IONIC_QCQ_F_INITED; 3448 3449 return 0; 3450 } 3451 3452 static int ionic_lif_notifyq_init(struct ionic_lif *lif) 3453 { 3454 struct ionic_qcq *qcq = lif->notifyqcq; 3455 struct device *dev = lif->ionic->dev; 3456 struct ionic_queue *q = &qcq->q; 3457 int err; 3458 3459 struct ionic_admin_ctx ctx = { 3460 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3461 .cmd.q_init = { 3462 .opcode = IONIC_CMD_Q_INIT, 3463 .lif_index = cpu_to_le16(lif->index), 3464 .type = q->type, 3465 .ver = lif->qtype_info[q->type].version, 3466 .index = cpu_to_le32(q->index), 3467 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 3468 IONIC_QINIT_F_ENA), 3469 .intr_index = cpu_to_le16(lif->adminqcq->intr.index), 3470 .pid = cpu_to_le16(q->pid), 3471 .ring_size = ilog2(q->num_descs), 3472 .ring_base = cpu_to_le64(q->base_pa), 3473 } 3474 }; 3475 3476 dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid); 3477 dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index); 3478 dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 3479 dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 3480 3481 err = ionic_adminq_post_wait(lif, &ctx); 3482 if (err) 3483 return err; 3484 3485 lif->last_eid = 0; 3486 q->hw_type = ctx.comp.q_init.hw_type; 3487 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 3488 q->dbval = IONIC_DBELL_QID(q->hw_index); 3489 3490 dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type); 3491 dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index); 3492 3493 /* preset the callback info */ 3494 q->info[0].cb_arg = lif; 3495 3496 qcq->flags |= IONIC_QCQ_F_INITED; 3497 3498 return 0; 3499 } 3500 3501 static int ionic_station_set(struct ionic_lif *lif) 3502 { 3503 struct net_device *netdev = lif->netdev; 3504 struct ionic_admin_ctx ctx = { 3505 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3506 .cmd.lif_getattr = { 3507 .opcode = IONIC_CMD_LIF_GETATTR, 3508 .index = cpu_to_le16(lif->index), 3509 .attr = IONIC_LIF_ATTR_MAC, 3510 }, 3511 }; 3512 u8 mac_address[ETH_ALEN]; 3513 struct sockaddr addr; 3514 int err; 3515 3516 err = ionic_adminq_post_wait(lif, &ctx); 3517 if (err) 3518 return err; 3519 netdev_dbg(lif->netdev, "found initial MAC addr %pM\n", 3520 ctx.comp.lif_getattr.mac); 3521 ether_addr_copy(mac_address, ctx.comp.lif_getattr.mac); 3522 3523 if (is_zero_ether_addr(mac_address)) { 3524 eth_hw_addr_random(netdev); 3525 netdev_dbg(netdev, "Random Mac generated: %pM\n", netdev->dev_addr); 3526 ether_addr_copy(mac_address, netdev->dev_addr); 3527 3528 err = ionic_program_mac(lif, mac_address); 3529 if (err < 0) 3530 return err; 3531 3532 if (err > 0) { 3533 netdev_dbg(netdev, "%s:SET/GET ATTR Mac are not same-due to old FW running\n", 3534 __func__); 3535 return 0; 3536 } 3537 } 3538 3539 if (!is_zero_ether_addr(netdev->dev_addr)) { 3540 /* If the netdev mac is non-zero and doesn't match the default 3541 * device address, it was set by something earlier and we're 3542 * likely here again after a fw-upgrade reset. We need to be 3543 * sure the netdev mac is in our filter list. 3544 */ 3545 if (!ether_addr_equal(mac_address, netdev->dev_addr)) 3546 ionic_lif_addr_add(lif, netdev->dev_addr); 3547 } else { 3548 /* Update the netdev mac with the device's mac */ 3549 ether_addr_copy(addr.sa_data, mac_address); 3550 addr.sa_family = AF_INET; 3551 err = eth_prepare_mac_addr_change(netdev, &addr); 3552 if (err) { 3553 netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n", 3554 addr.sa_data, err); 3555 return 0; 3556 } 3557 3558 eth_commit_mac_addr_change(netdev, &addr); 3559 } 3560 3561 netdev_dbg(lif->netdev, "adding station MAC addr %pM\n", 3562 netdev->dev_addr); 3563 ionic_lif_addr_add(lif, netdev->dev_addr); 3564 3565 return 0; 3566 } 3567 3568 int ionic_lif_init(struct ionic_lif *lif) 3569 { 3570 struct ionic_dev *idev = &lif->ionic->idev; 3571 struct device *dev = lif->ionic->dev; 3572 struct ionic_lif_init_comp comp; 3573 int dbpage_num; 3574 int err; 3575 3576 mutex_lock(&lif->ionic->dev_cmd_lock); 3577 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa); 3578 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 3579 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 3580 mutex_unlock(&lif->ionic->dev_cmd_lock); 3581 if (err) 3582 return err; 3583 3584 lif->hw_index = le16_to_cpu(comp.hw_index); 3585 3586 /* now that we have the hw_index we can figure out our doorbell page */ 3587 lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif); 3588 if (!lif->dbid_count) { 3589 dev_err(dev, "No doorbell pages, aborting\n"); 3590 return -EINVAL; 3591 } 3592 3593 lif->kern_pid = 0; 3594 dbpage_num = ionic_db_page_num(lif, lif->kern_pid); 3595 lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num); 3596 if (!lif->kern_dbpage) { 3597 dev_err(dev, "Cannot map dbpage, aborting\n"); 3598 return -ENOMEM; 3599 } 3600 3601 err = ionic_lif_adminq_init(lif); 3602 if (err) 3603 goto err_out_adminq_deinit; 3604 3605 if (lif->ionic->nnqs_per_lif) { 3606 err = ionic_lif_notifyq_init(lif); 3607 if (err) 3608 goto err_out_notifyq_deinit; 3609 } 3610 3611 err = ionic_init_nic_features(lif); 3612 if (err) 3613 goto err_out_notifyq_deinit; 3614 3615 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 3616 err = ionic_rx_filters_init(lif); 3617 if (err) 3618 goto err_out_notifyq_deinit; 3619 } 3620 3621 err = ionic_station_set(lif); 3622 if (err) 3623 goto err_out_notifyq_deinit; 3624 3625 lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT; 3626 3627 set_bit(IONIC_LIF_F_INITED, lif->state); 3628 3629 INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work); 3630 3631 return 0; 3632 3633 err_out_notifyq_deinit: 3634 napi_disable(&lif->adminqcq->napi); 3635 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 3636 err_out_adminq_deinit: 3637 ionic_lif_qcq_deinit(lif, lif->adminqcq); 3638 ionic_lif_reset(lif); 3639 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 3640 lif->kern_dbpage = NULL; 3641 3642 return err; 3643 } 3644 3645 static void ionic_lif_notify_work(struct work_struct *ws) 3646 { 3647 } 3648 3649 static void ionic_lif_set_netdev_info(struct ionic_lif *lif) 3650 { 3651 struct ionic_admin_ctx ctx = { 3652 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3653 .cmd.lif_setattr = { 3654 .opcode = IONIC_CMD_LIF_SETATTR, 3655 .index = cpu_to_le16(lif->index), 3656 .attr = IONIC_LIF_ATTR_NAME, 3657 }, 3658 }; 3659 3660 strscpy(ctx.cmd.lif_setattr.name, lif->netdev->name, 3661 sizeof(ctx.cmd.lif_setattr.name)); 3662 3663 ionic_adminq_post_wait(lif, &ctx); 3664 } 3665 3666 static struct ionic_lif *ionic_netdev_lif(struct net_device *netdev) 3667 { 3668 if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit) 3669 return NULL; 3670 3671 return netdev_priv(netdev); 3672 } 3673 3674 static int ionic_lif_notify(struct notifier_block *nb, 3675 unsigned long event, void *info) 3676 { 3677 struct net_device *ndev = netdev_notifier_info_to_dev(info); 3678 struct ionic *ionic = container_of(nb, struct ionic, nb); 3679 struct ionic_lif *lif = ionic_netdev_lif(ndev); 3680 3681 if (!lif || lif->ionic != ionic) 3682 return NOTIFY_DONE; 3683 3684 switch (event) { 3685 case NETDEV_CHANGENAME: 3686 ionic_lif_set_netdev_info(lif); 3687 break; 3688 } 3689 3690 return NOTIFY_DONE; 3691 } 3692 3693 int ionic_lif_register(struct ionic_lif *lif) 3694 { 3695 int err; 3696 3697 ionic_lif_register_phc(lif); 3698 3699 INIT_WORK(&lif->ionic->nb_work, ionic_lif_notify_work); 3700 3701 lif->ionic->nb.notifier_call = ionic_lif_notify; 3702 3703 err = register_netdevice_notifier(&lif->ionic->nb); 3704 if (err) 3705 lif->ionic->nb.notifier_call = NULL; 3706 3707 /* only register LIF0 for now */ 3708 err = register_netdev(lif->netdev); 3709 if (err) { 3710 dev_err(lif->ionic->dev, "Cannot register net device, aborting\n"); 3711 ionic_lif_unregister_phc(lif); 3712 return err; 3713 } 3714 3715 ionic_link_status_check_request(lif, CAN_SLEEP); 3716 lif->registered = true; 3717 ionic_lif_set_netdev_info(lif); 3718 3719 return 0; 3720 } 3721 3722 void ionic_lif_unregister(struct ionic_lif *lif) 3723 { 3724 if (lif->ionic->nb.notifier_call) { 3725 unregister_netdevice_notifier(&lif->ionic->nb); 3726 cancel_work_sync(&lif->ionic->nb_work); 3727 lif->ionic->nb.notifier_call = NULL; 3728 } 3729 3730 if (lif->netdev->reg_state == NETREG_REGISTERED) 3731 unregister_netdev(lif->netdev); 3732 3733 ionic_lif_unregister_phc(lif); 3734 3735 lif->registered = false; 3736 } 3737 3738 static void ionic_lif_queue_identify(struct ionic_lif *lif) 3739 { 3740 union ionic_q_identity __iomem *q_ident; 3741 struct ionic *ionic = lif->ionic; 3742 struct ionic_dev *idev; 3743 int qtype; 3744 int err; 3745 3746 idev = &lif->ionic->idev; 3747 q_ident = (union ionic_q_identity __iomem *)&idev->dev_cmd_regs->data; 3748 3749 for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) { 3750 struct ionic_qtype_info *qti = &lif->qtype_info[qtype]; 3751 3752 /* filter out the ones we know about */ 3753 switch (qtype) { 3754 case IONIC_QTYPE_ADMINQ: 3755 case IONIC_QTYPE_NOTIFYQ: 3756 case IONIC_QTYPE_RXQ: 3757 case IONIC_QTYPE_TXQ: 3758 break; 3759 default: 3760 continue; 3761 } 3762 3763 memset(qti, 0, sizeof(*qti)); 3764 3765 mutex_lock(&ionic->dev_cmd_lock); 3766 ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype, 3767 ionic_qtype_versions[qtype]); 3768 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3769 if (!err) { 3770 qti->version = readb(&q_ident->version); 3771 qti->supported = readb(&q_ident->supported); 3772 qti->features = readq(&q_ident->features); 3773 qti->desc_sz = readw(&q_ident->desc_sz); 3774 qti->comp_sz = readw(&q_ident->comp_sz); 3775 qti->sg_desc_sz = readw(&q_ident->sg_desc_sz); 3776 qti->max_sg_elems = readw(&q_ident->max_sg_elems); 3777 qti->sg_desc_stride = readw(&q_ident->sg_desc_stride); 3778 } 3779 mutex_unlock(&ionic->dev_cmd_lock); 3780 3781 if (err == -EINVAL) { 3782 dev_err(ionic->dev, "qtype %d not supported\n", qtype); 3783 continue; 3784 } else if (err == -EIO) { 3785 dev_err(ionic->dev, "q_ident failed, not supported on older FW\n"); 3786 return; 3787 } else if (err) { 3788 dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n", 3789 qtype, err); 3790 return; 3791 } 3792 3793 dev_dbg(ionic->dev, " qtype[%d].version = %d\n", 3794 qtype, qti->version); 3795 dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n", 3796 qtype, qti->supported); 3797 dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n", 3798 qtype, qti->features); 3799 dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n", 3800 qtype, qti->desc_sz); 3801 dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n", 3802 qtype, qti->comp_sz); 3803 dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n", 3804 qtype, qti->sg_desc_sz); 3805 dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n", 3806 qtype, qti->max_sg_elems); 3807 dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n", 3808 qtype, qti->sg_desc_stride); 3809 } 3810 } 3811 3812 int ionic_lif_identify(struct ionic *ionic, u8 lif_type, 3813 union ionic_lif_identity *lid) 3814 { 3815 struct ionic_dev *idev = &ionic->idev; 3816 size_t sz; 3817 int err; 3818 3819 sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data)); 3820 3821 mutex_lock(&ionic->dev_cmd_lock); 3822 ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1); 3823 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3824 memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz); 3825 mutex_unlock(&ionic->dev_cmd_lock); 3826 if (err) 3827 return (err); 3828 3829 dev_dbg(ionic->dev, "capabilities 0x%llx\n", 3830 le64_to_cpu(lid->capabilities)); 3831 3832 dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n", 3833 le32_to_cpu(lid->eth.max_ucast_filters)); 3834 dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n", 3835 le32_to_cpu(lid->eth.max_mcast_filters)); 3836 dev_dbg(ionic->dev, "eth.features 0x%llx\n", 3837 le64_to_cpu(lid->eth.config.features)); 3838 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n", 3839 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ])); 3840 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n", 3841 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ])); 3842 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n", 3843 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ])); 3844 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n", 3845 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ])); 3846 dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name); 3847 dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac); 3848 dev_dbg(ionic->dev, "eth.config.mtu %d\n", 3849 le32_to_cpu(lid->eth.config.mtu)); 3850 3851 return 0; 3852 } 3853 3854 int ionic_lif_size(struct ionic *ionic) 3855 { 3856 struct ionic_identity *ident = &ionic->ident; 3857 unsigned int nintrs, dev_nintrs; 3858 union ionic_lif_config *lc; 3859 unsigned int ntxqs_per_lif; 3860 unsigned int nrxqs_per_lif; 3861 unsigned int neqs_per_lif; 3862 unsigned int nnqs_per_lif; 3863 unsigned int nxqs, neqs; 3864 unsigned int min_intrs; 3865 int err; 3866 3867 /* retrieve basic values from FW */ 3868 lc = &ident->lif.eth.config; 3869 dev_nintrs = le32_to_cpu(ident->dev.nintrs); 3870 neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count); 3871 nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]); 3872 ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]); 3873 nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]); 3874 3875 /* limit values to play nice with kdump */ 3876 if (is_kdump_kernel()) { 3877 dev_nintrs = 2; 3878 neqs_per_lif = 0; 3879 nnqs_per_lif = 0; 3880 ntxqs_per_lif = 1; 3881 nrxqs_per_lif = 1; 3882 } 3883 3884 /* reserve last queue id for hardware timestamping */ 3885 if (lc->features & cpu_to_le64(IONIC_ETH_HW_TIMESTAMP)) { 3886 if (ntxqs_per_lif <= 1 || nrxqs_per_lif <= 1) { 3887 lc->features &= cpu_to_le64(~IONIC_ETH_HW_TIMESTAMP); 3888 } else { 3889 ntxqs_per_lif -= 1; 3890 nrxqs_per_lif -= 1; 3891 } 3892 } 3893 3894 nxqs = min(ntxqs_per_lif, nrxqs_per_lif); 3895 nxqs = min(nxqs, num_online_cpus()); 3896 neqs = min(neqs_per_lif, num_online_cpus()); 3897 3898 try_again: 3899 /* interrupt usage: 3900 * 1 for master lif adminq/notifyq 3901 * 1 for each CPU for master lif TxRx queue pairs 3902 * whatever's left is for RDMA queues 3903 */ 3904 nintrs = 1 + nxqs + neqs; 3905 min_intrs = 2; /* adminq + 1 TxRx queue pair */ 3906 3907 if (nintrs > dev_nintrs) 3908 goto try_fewer; 3909 3910 err = ionic_bus_alloc_irq_vectors(ionic, nintrs); 3911 if (err < 0 && err != -ENOSPC) { 3912 dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err); 3913 return err; 3914 } 3915 if (err == -ENOSPC) 3916 goto try_fewer; 3917 3918 if (err != nintrs) { 3919 ionic_bus_free_irq_vectors(ionic); 3920 goto try_fewer; 3921 } 3922 3923 ionic->nnqs_per_lif = nnqs_per_lif; 3924 ionic->neqs_per_lif = neqs; 3925 ionic->ntxqs_per_lif = nxqs; 3926 ionic->nrxqs_per_lif = nxqs; 3927 ionic->nintrs = nintrs; 3928 3929 ionic_debugfs_add_sizes(ionic); 3930 3931 return 0; 3932 3933 try_fewer: 3934 if (nnqs_per_lif > 1) { 3935 nnqs_per_lif >>= 1; 3936 goto try_again; 3937 } 3938 if (neqs > 1) { 3939 neqs >>= 1; 3940 goto try_again; 3941 } 3942 if (nxqs > 1) { 3943 nxqs >>= 1; 3944 goto try_again; 3945 } 3946 dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs); 3947 return -ENOSPC; 3948 } 3949