1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/printk.h> 5 #include <linux/dynamic_debug.h> 6 #include <linux/netdevice.h> 7 #include <linux/etherdevice.h> 8 #include <linux/if_vlan.h> 9 #include <linux/rtnetlink.h> 10 #include <linux/interrupt.h> 11 #include <linux/pci.h> 12 #include <linux/cpumask.h> 13 14 #include "ionic.h" 15 #include "ionic_bus.h" 16 #include "ionic_lif.h" 17 #include "ionic_txrx.h" 18 #include "ionic_ethtool.h" 19 #include "ionic_debugfs.h" 20 21 /* queuetype support level */ 22 static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = { 23 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */ 24 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */ 25 [IONIC_QTYPE_RXQ] = 0, /* 0 = Base version with CQ+SG support */ 26 [IONIC_QTYPE_TXQ] = 1, /* 0 = Base version with CQ+SG support 27 * 1 = ... with Tx SG version 1 28 */ 29 }; 30 31 static void ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode); 32 static int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr); 33 static int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr); 34 static void ionic_link_status_check(struct ionic_lif *lif); 35 static void ionic_lif_handle_fw_down(struct ionic_lif *lif); 36 static void ionic_lif_handle_fw_up(struct ionic_lif *lif); 37 static void ionic_lif_set_netdev_info(struct ionic_lif *lif); 38 39 static void ionic_txrx_deinit(struct ionic_lif *lif); 40 static int ionic_txrx_init(struct ionic_lif *lif); 41 static int ionic_start_queues(struct ionic_lif *lif); 42 static void ionic_stop_queues(struct ionic_lif *lif); 43 static void ionic_lif_queue_identify(struct ionic_lif *lif); 44 45 static void ionic_dim_work(struct work_struct *work) 46 { 47 struct dim *dim = container_of(work, struct dim, work); 48 struct dim_cq_moder cur_moder; 49 struct ionic_qcq *qcq; 50 u32 new_coal; 51 52 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 53 qcq = container_of(dim, struct ionic_qcq, dim); 54 new_coal = ionic_coal_usec_to_hw(qcq->q.lif->ionic, cur_moder.usec); 55 qcq->intr.dim_coal_hw = new_coal ? new_coal : 1; 56 dim->state = DIM_START_MEASURE; 57 } 58 59 static void ionic_lif_deferred_work(struct work_struct *work) 60 { 61 struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work); 62 struct ionic_deferred *def = &lif->deferred; 63 struct ionic_deferred_work *w = NULL; 64 65 do { 66 spin_lock_bh(&def->lock); 67 if (!list_empty(&def->list)) { 68 w = list_first_entry(&def->list, 69 struct ionic_deferred_work, list); 70 list_del(&w->list); 71 } 72 spin_unlock_bh(&def->lock); 73 74 if (!w) 75 break; 76 77 switch (w->type) { 78 case IONIC_DW_TYPE_RX_MODE: 79 ionic_lif_rx_mode(lif, w->rx_mode); 80 break; 81 case IONIC_DW_TYPE_RX_ADDR_ADD: 82 ionic_lif_addr_add(lif, w->addr); 83 break; 84 case IONIC_DW_TYPE_RX_ADDR_DEL: 85 ionic_lif_addr_del(lif, w->addr); 86 break; 87 case IONIC_DW_TYPE_LINK_STATUS: 88 ionic_link_status_check(lif); 89 break; 90 case IONIC_DW_TYPE_LIF_RESET: 91 if (w->fw_status) 92 ionic_lif_handle_fw_up(lif); 93 else 94 ionic_lif_handle_fw_down(lif); 95 break; 96 default: 97 break; 98 } 99 kfree(w); 100 w = NULL; 101 } while (true); 102 } 103 104 void ionic_lif_deferred_enqueue(struct ionic_deferred *def, 105 struct ionic_deferred_work *work) 106 { 107 spin_lock_bh(&def->lock); 108 list_add_tail(&work->list, &def->list); 109 spin_unlock_bh(&def->lock); 110 schedule_work(&def->work); 111 } 112 113 static void ionic_link_status_check(struct ionic_lif *lif) 114 { 115 struct net_device *netdev = lif->netdev; 116 u16 link_status; 117 bool link_up; 118 119 if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 120 return; 121 122 link_status = le16_to_cpu(lif->info->status.link_status); 123 link_up = link_status == IONIC_PORT_OPER_STATUS_UP; 124 125 if (link_up) { 126 if (lif->netdev->flags & IFF_UP && netif_running(lif->netdev)) { 127 mutex_lock(&lif->queue_lock); 128 ionic_start_queues(lif); 129 mutex_unlock(&lif->queue_lock); 130 } 131 132 if (!netif_carrier_ok(netdev)) { 133 u32 link_speed; 134 135 ionic_port_identify(lif->ionic); 136 link_speed = le32_to_cpu(lif->info->status.link_speed); 137 netdev_info(netdev, "Link up - %d Gbps\n", 138 link_speed / 1000); 139 netif_carrier_on(netdev); 140 } 141 } else { 142 if (netif_carrier_ok(netdev)) { 143 netdev_info(netdev, "Link down\n"); 144 netif_carrier_off(netdev); 145 } 146 147 if (lif->netdev->flags & IFF_UP && netif_running(lif->netdev)) { 148 mutex_lock(&lif->queue_lock); 149 ionic_stop_queues(lif); 150 mutex_unlock(&lif->queue_lock); 151 } 152 } 153 154 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 155 } 156 157 void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep) 158 { 159 struct ionic_deferred_work *work; 160 161 /* we only need one request outstanding at a time */ 162 if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 163 return; 164 165 if (!can_sleep) { 166 work = kzalloc(sizeof(*work), GFP_ATOMIC); 167 if (!work) { 168 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 169 return; 170 } 171 172 work->type = IONIC_DW_TYPE_LINK_STATUS; 173 ionic_lif_deferred_enqueue(&lif->deferred, work); 174 } else { 175 ionic_link_status_check(lif); 176 } 177 } 178 179 static irqreturn_t ionic_isr(int irq, void *data) 180 { 181 struct napi_struct *napi = data; 182 183 napi_schedule_irqoff(napi); 184 185 return IRQ_HANDLED; 186 } 187 188 static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq) 189 { 190 struct ionic_intr_info *intr = &qcq->intr; 191 struct device *dev = lif->ionic->dev; 192 struct ionic_queue *q = &qcq->q; 193 const char *name; 194 195 if (lif->registered) 196 name = lif->netdev->name; 197 else 198 name = dev_name(dev); 199 200 snprintf(intr->name, sizeof(intr->name), 201 "%s-%s-%s", IONIC_DRV_NAME, name, q->name); 202 203 return devm_request_irq(dev, intr->vector, ionic_isr, 204 0, intr->name, &qcq->napi); 205 } 206 207 static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) 208 { 209 struct ionic *ionic = lif->ionic; 210 int index; 211 212 index = find_first_zero_bit(ionic->intrs, ionic->nintrs); 213 if (index == ionic->nintrs) { 214 netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n", 215 __func__, index, ionic->nintrs); 216 return -ENOSPC; 217 } 218 219 set_bit(index, ionic->intrs); 220 ionic_intr_init(&ionic->idev, intr, index); 221 222 return 0; 223 } 224 225 static void ionic_intr_free(struct ionic *ionic, int index) 226 { 227 if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < ionic->nintrs) 228 clear_bit(index, ionic->intrs); 229 } 230 231 static int ionic_qcq_enable(struct ionic_qcq *qcq) 232 { 233 struct ionic_queue *q = &qcq->q; 234 struct ionic_lif *lif = q->lif; 235 struct ionic_dev *idev; 236 struct device *dev; 237 238 struct ionic_admin_ctx ctx = { 239 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 240 .cmd.q_control = { 241 .opcode = IONIC_CMD_Q_CONTROL, 242 .lif_index = cpu_to_le16(lif->index), 243 .type = q->type, 244 .index = cpu_to_le32(q->index), 245 .oper = IONIC_Q_ENABLE, 246 }, 247 }; 248 249 idev = &lif->ionic->idev; 250 dev = lif->ionic->dev; 251 252 dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n", 253 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 254 255 if (qcq->flags & IONIC_QCQ_F_INTR) { 256 irq_set_affinity_hint(qcq->intr.vector, 257 &qcq->intr.affinity_mask); 258 napi_enable(&qcq->napi); 259 ionic_intr_clean(idev->intr_ctrl, qcq->intr.index); 260 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 261 IONIC_INTR_MASK_CLEAR); 262 } 263 264 return ionic_adminq_post_wait(lif, &ctx); 265 } 266 267 static int ionic_qcq_disable(struct ionic_qcq *qcq, bool send_to_hw) 268 { 269 struct ionic_queue *q; 270 struct ionic_lif *lif; 271 int err = 0; 272 273 struct ionic_admin_ctx ctx = { 274 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 275 .cmd.q_control = { 276 .opcode = IONIC_CMD_Q_CONTROL, 277 .oper = IONIC_Q_DISABLE, 278 }, 279 }; 280 281 if (!qcq) 282 return -ENXIO; 283 284 q = &qcq->q; 285 lif = q->lif; 286 287 if (qcq->flags & IONIC_QCQ_F_INTR) { 288 struct ionic_dev *idev = &lif->ionic->idev; 289 290 cancel_work_sync(&qcq->dim.work); 291 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 292 IONIC_INTR_MASK_SET); 293 synchronize_irq(qcq->intr.vector); 294 irq_set_affinity_hint(qcq->intr.vector, NULL); 295 napi_disable(&qcq->napi); 296 } 297 298 if (send_to_hw) { 299 ctx.cmd.q_control.lif_index = cpu_to_le16(lif->index); 300 ctx.cmd.q_control.type = q->type; 301 ctx.cmd.q_control.index = cpu_to_le32(q->index); 302 dev_dbg(lif->ionic->dev, "q_disable.index %d q_disable.qtype %d\n", 303 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 304 305 err = ionic_adminq_post_wait(lif, &ctx); 306 } 307 308 return err; 309 } 310 311 static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq) 312 { 313 struct ionic_dev *idev = &lif->ionic->idev; 314 315 if (!qcq) 316 return; 317 318 if (!(qcq->flags & IONIC_QCQ_F_INITED)) 319 return; 320 321 if (qcq->flags & IONIC_QCQ_F_INTR) { 322 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 323 IONIC_INTR_MASK_SET); 324 netif_napi_del(&qcq->napi); 325 } 326 327 qcq->flags &= ~IONIC_QCQ_F_INITED; 328 } 329 330 static void ionic_qcq_intr_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 331 { 332 if (!(qcq->flags & IONIC_QCQ_F_INTR) || qcq->intr.vector == 0) 333 return; 334 335 irq_set_affinity_hint(qcq->intr.vector, NULL); 336 devm_free_irq(lif->ionic->dev, qcq->intr.vector, &qcq->napi); 337 qcq->intr.vector = 0; 338 ionic_intr_free(lif->ionic, qcq->intr.index); 339 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 340 } 341 342 static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 343 { 344 struct device *dev = lif->ionic->dev; 345 346 if (!qcq) 347 return; 348 349 ionic_debugfs_del_qcq(qcq); 350 351 if (qcq->q_base) { 352 dma_free_coherent(dev, qcq->q_size, qcq->q_base, qcq->q_base_pa); 353 qcq->q_base = NULL; 354 qcq->q_base_pa = 0; 355 } 356 357 if (qcq->cq_base) { 358 dma_free_coherent(dev, qcq->cq_size, qcq->cq_base, qcq->cq_base_pa); 359 qcq->cq_base = NULL; 360 qcq->cq_base_pa = 0; 361 } 362 363 if (qcq->sg_base) { 364 dma_free_coherent(dev, qcq->sg_size, qcq->sg_base, qcq->sg_base_pa); 365 qcq->sg_base = NULL; 366 qcq->sg_base_pa = 0; 367 } 368 369 ionic_qcq_intr_free(lif, qcq); 370 371 if (qcq->cq.info) { 372 devm_kfree(dev, qcq->cq.info); 373 qcq->cq.info = NULL; 374 } 375 if (qcq->q.info) { 376 devm_kfree(dev, qcq->q.info); 377 qcq->q.info = NULL; 378 } 379 } 380 381 static void ionic_qcqs_free(struct ionic_lif *lif) 382 { 383 struct device *dev = lif->ionic->dev; 384 385 if (lif->notifyqcq) { 386 ionic_qcq_free(lif, lif->notifyqcq); 387 devm_kfree(dev, lif->notifyqcq); 388 lif->notifyqcq = NULL; 389 } 390 391 if (lif->adminqcq) { 392 ionic_qcq_free(lif, lif->adminqcq); 393 devm_kfree(dev, lif->adminqcq); 394 lif->adminqcq = NULL; 395 } 396 397 if (lif->rxqcqs) { 398 devm_kfree(dev, lif->rxqstats); 399 lif->rxqstats = NULL; 400 devm_kfree(dev, lif->rxqcqs); 401 lif->rxqcqs = NULL; 402 } 403 404 if (lif->txqcqs) { 405 devm_kfree(dev, lif->txqstats); 406 lif->txqstats = NULL; 407 devm_kfree(dev, lif->txqcqs); 408 lif->txqcqs = NULL; 409 } 410 } 411 412 static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq, 413 struct ionic_qcq *n_qcq) 414 { 415 if (WARN_ON(n_qcq->flags & IONIC_QCQ_F_INTR)) { 416 ionic_intr_free(n_qcq->cq.lif->ionic, n_qcq->intr.index); 417 n_qcq->flags &= ~IONIC_QCQ_F_INTR; 418 } 419 420 n_qcq->intr.vector = src_qcq->intr.vector; 421 n_qcq->intr.index = src_qcq->intr.index; 422 } 423 424 static int ionic_alloc_qcq_interrupt(struct ionic_lif *lif, struct ionic_qcq *qcq) 425 { 426 int err; 427 428 if (!(qcq->flags & IONIC_QCQ_F_INTR)) { 429 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 430 return 0; 431 } 432 433 err = ionic_intr_alloc(lif, &qcq->intr); 434 if (err) { 435 netdev_warn(lif->netdev, "no intr for %s: %d\n", 436 qcq->q.name, err); 437 goto err_out; 438 } 439 440 err = ionic_bus_get_irq(lif->ionic, qcq->intr.index); 441 if (err < 0) { 442 netdev_warn(lif->netdev, "no vector for %s: %d\n", 443 qcq->q.name, err); 444 goto err_out_free_intr; 445 } 446 qcq->intr.vector = err; 447 ionic_intr_mask_assert(lif->ionic->idev.intr_ctrl, qcq->intr.index, 448 IONIC_INTR_MASK_SET); 449 450 err = ionic_request_irq(lif, qcq); 451 if (err) { 452 netdev_warn(lif->netdev, "irq request failed %d\n", err); 453 goto err_out_free_intr; 454 } 455 456 /* try to get the irq on the local numa node first */ 457 qcq->intr.cpu = cpumask_local_spread(qcq->intr.index, 458 dev_to_node(lif->ionic->dev)); 459 if (qcq->intr.cpu != -1) 460 cpumask_set_cpu(qcq->intr.cpu, &qcq->intr.affinity_mask); 461 462 netdev_dbg(lif->netdev, "%s: Interrupt index %d\n", qcq->q.name, qcq->intr.index); 463 return 0; 464 465 err_out_free_intr: 466 ionic_intr_free(lif->ionic, qcq->intr.index); 467 err_out: 468 return err; 469 } 470 471 static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type, 472 unsigned int index, 473 const char *name, unsigned int flags, 474 unsigned int num_descs, unsigned int desc_size, 475 unsigned int cq_desc_size, 476 unsigned int sg_desc_size, 477 unsigned int pid, struct ionic_qcq **qcq) 478 { 479 struct ionic_dev *idev = &lif->ionic->idev; 480 struct device *dev = lif->ionic->dev; 481 void *q_base, *cq_base, *sg_base; 482 dma_addr_t cq_base_pa = 0; 483 dma_addr_t sg_base_pa = 0; 484 dma_addr_t q_base_pa = 0; 485 struct ionic_qcq *new; 486 int err; 487 488 *qcq = NULL; 489 490 new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL); 491 if (!new) { 492 netdev_err(lif->netdev, "Cannot allocate queue structure\n"); 493 err = -ENOMEM; 494 goto err_out; 495 } 496 497 new->flags = flags; 498 499 new->q.info = devm_kcalloc(dev, num_descs, sizeof(*new->q.info), 500 GFP_KERNEL); 501 if (!new->q.info) { 502 netdev_err(lif->netdev, "Cannot allocate queue info\n"); 503 err = -ENOMEM; 504 goto err_out_free_qcq; 505 } 506 507 new->q.type = type; 508 509 err = ionic_q_init(lif, idev, &new->q, index, name, num_descs, 510 desc_size, sg_desc_size, pid); 511 if (err) { 512 netdev_err(lif->netdev, "Cannot initialize queue\n"); 513 goto err_out_free_q_info; 514 } 515 516 err = ionic_alloc_qcq_interrupt(lif, new); 517 if (err) 518 goto err_out; 519 520 new->cq.info = devm_kcalloc(dev, num_descs, sizeof(*new->cq.info), 521 GFP_KERNEL); 522 if (!new->cq.info) { 523 netdev_err(lif->netdev, "Cannot allocate completion queue info\n"); 524 err = -ENOMEM; 525 goto err_out_free_irq; 526 } 527 528 err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size); 529 if (err) { 530 netdev_err(lif->netdev, "Cannot initialize completion queue\n"); 531 goto err_out_free_cq_info; 532 } 533 534 if (flags & IONIC_QCQ_F_NOTIFYQ) { 535 int q_size, cq_size; 536 537 /* q & cq need to be contiguous in case of notifyq */ 538 q_size = ALIGN(num_descs * desc_size, PAGE_SIZE); 539 cq_size = ALIGN(num_descs * cq_desc_size, PAGE_SIZE); 540 541 new->q_size = PAGE_SIZE + q_size + cq_size; 542 new->q_base = dma_alloc_coherent(dev, new->q_size, 543 &new->q_base_pa, GFP_KERNEL); 544 if (!new->q_base) { 545 netdev_err(lif->netdev, "Cannot allocate qcq DMA memory\n"); 546 err = -ENOMEM; 547 goto err_out_free_cq_info; 548 } 549 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE); 550 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 551 ionic_q_map(&new->q, q_base, q_base_pa); 552 553 cq_base = PTR_ALIGN(q_base + q_size, PAGE_SIZE); 554 cq_base_pa = ALIGN(new->q_base_pa + q_size, PAGE_SIZE); 555 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 556 ionic_cq_bind(&new->cq, &new->q); 557 } else { 558 new->q_size = PAGE_SIZE + (num_descs * desc_size); 559 new->q_base = dma_alloc_coherent(dev, new->q_size, &new->q_base_pa, 560 GFP_KERNEL); 561 if (!new->q_base) { 562 netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n"); 563 err = -ENOMEM; 564 goto err_out_free_cq_info; 565 } 566 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE); 567 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 568 ionic_q_map(&new->q, q_base, q_base_pa); 569 570 new->cq_size = PAGE_SIZE + (num_descs * cq_desc_size); 571 new->cq_base = dma_alloc_coherent(dev, new->cq_size, &new->cq_base_pa, 572 GFP_KERNEL); 573 if (!new->cq_base) { 574 netdev_err(lif->netdev, "Cannot allocate cq DMA memory\n"); 575 err = -ENOMEM; 576 goto err_out_free_q; 577 } 578 cq_base = PTR_ALIGN(new->cq_base, PAGE_SIZE); 579 cq_base_pa = ALIGN(new->cq_base_pa, PAGE_SIZE); 580 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 581 ionic_cq_bind(&new->cq, &new->q); 582 } 583 584 if (flags & IONIC_QCQ_F_SG) { 585 new->sg_size = PAGE_SIZE + (num_descs * sg_desc_size); 586 new->sg_base = dma_alloc_coherent(dev, new->sg_size, &new->sg_base_pa, 587 GFP_KERNEL); 588 if (!new->sg_base) { 589 netdev_err(lif->netdev, "Cannot allocate sg DMA memory\n"); 590 err = -ENOMEM; 591 goto err_out_free_cq; 592 } 593 sg_base = PTR_ALIGN(new->sg_base, PAGE_SIZE); 594 sg_base_pa = ALIGN(new->sg_base_pa, PAGE_SIZE); 595 ionic_q_sg_map(&new->q, sg_base, sg_base_pa); 596 } 597 598 INIT_WORK(&new->dim.work, ionic_dim_work); 599 new->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 600 601 *qcq = new; 602 603 return 0; 604 605 err_out_free_cq: 606 dma_free_coherent(dev, new->cq_size, new->cq_base, new->cq_base_pa); 607 err_out_free_q: 608 dma_free_coherent(dev, new->q_size, new->q_base, new->q_base_pa); 609 err_out_free_cq_info: 610 devm_kfree(dev, new->cq.info); 611 err_out_free_irq: 612 if (flags & IONIC_QCQ_F_INTR) { 613 devm_free_irq(dev, new->intr.vector, &new->napi); 614 ionic_intr_free(lif->ionic, new->intr.index); 615 } 616 err_out_free_q_info: 617 devm_kfree(dev, new->q.info); 618 err_out_free_qcq: 619 devm_kfree(dev, new); 620 err_out: 621 dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err); 622 return err; 623 } 624 625 static int ionic_qcqs_alloc(struct ionic_lif *lif) 626 { 627 struct device *dev = lif->ionic->dev; 628 unsigned int flags; 629 int err; 630 631 flags = IONIC_QCQ_F_INTR; 632 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags, 633 IONIC_ADMINQ_LENGTH, 634 sizeof(struct ionic_admin_cmd), 635 sizeof(struct ionic_admin_comp), 636 0, lif->kern_pid, &lif->adminqcq); 637 if (err) 638 return err; 639 ionic_debugfs_add_qcq(lif, lif->adminqcq); 640 641 if (lif->ionic->nnqs_per_lif) { 642 flags = IONIC_QCQ_F_NOTIFYQ; 643 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq", 644 flags, IONIC_NOTIFYQ_LENGTH, 645 sizeof(struct ionic_notifyq_cmd), 646 sizeof(union ionic_notifyq_comp), 647 0, lif->kern_pid, &lif->notifyqcq); 648 if (err) 649 goto err_out; 650 ionic_debugfs_add_qcq(lif, lif->notifyqcq); 651 652 /* Let the notifyq ride on the adminq interrupt */ 653 ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq); 654 } 655 656 err = -ENOMEM; 657 lif->txqcqs = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif, 658 sizeof(struct ionic_qcq *), GFP_KERNEL); 659 if (!lif->txqcqs) 660 goto err_out; 661 lif->rxqcqs = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif, 662 sizeof(struct ionic_qcq *), GFP_KERNEL); 663 if (!lif->rxqcqs) 664 goto err_out; 665 666 lif->txqstats = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif, 667 sizeof(struct ionic_tx_stats), GFP_KERNEL); 668 if (!lif->txqstats) 669 goto err_out; 670 lif->rxqstats = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif, 671 sizeof(struct ionic_rx_stats), GFP_KERNEL); 672 if (!lif->rxqstats) 673 goto err_out; 674 675 return 0; 676 677 err_out: 678 ionic_qcqs_free(lif); 679 return err; 680 } 681 682 static void ionic_qcq_sanitize(struct ionic_qcq *qcq) 683 { 684 qcq->q.tail_idx = 0; 685 qcq->q.head_idx = 0; 686 qcq->cq.tail_idx = 0; 687 qcq->cq.done_color = 1; 688 memset(qcq->q_base, 0, qcq->q_size); 689 memset(qcq->cq_base, 0, qcq->cq_size); 690 memset(qcq->sg_base, 0, qcq->sg_size); 691 } 692 693 static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 694 { 695 struct device *dev = lif->ionic->dev; 696 struct ionic_queue *q = &qcq->q; 697 struct ionic_cq *cq = &qcq->cq; 698 struct ionic_admin_ctx ctx = { 699 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 700 .cmd.q_init = { 701 .opcode = IONIC_CMD_Q_INIT, 702 .lif_index = cpu_to_le16(lif->index), 703 .type = q->type, 704 .ver = lif->qtype_info[q->type].version, 705 .index = cpu_to_le32(q->index), 706 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 707 IONIC_QINIT_F_SG), 708 .pid = cpu_to_le16(q->pid), 709 .ring_size = ilog2(q->num_descs), 710 .ring_base = cpu_to_le64(q->base_pa), 711 .cq_ring_base = cpu_to_le64(cq->base_pa), 712 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 713 }, 714 }; 715 unsigned int intr_index; 716 int err; 717 718 if (qcq->flags & IONIC_QCQ_F_INTR) 719 intr_index = qcq->intr.index; 720 else 721 intr_index = lif->rxqcqs[q->index]->intr.index; 722 ctx.cmd.q_init.intr_index = cpu_to_le16(intr_index); 723 724 dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid); 725 dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index); 726 dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 727 dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 728 dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 729 dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver); 730 dev_dbg(dev, "txq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 731 732 ionic_qcq_sanitize(qcq); 733 734 err = ionic_adminq_post_wait(lif, &ctx); 735 if (err) 736 return err; 737 738 q->hw_type = ctx.comp.q_init.hw_type; 739 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 740 q->dbval = IONIC_DBELL_QID(q->hw_index); 741 742 dev_dbg(dev, "txq->hw_type %d\n", q->hw_type); 743 dev_dbg(dev, "txq->hw_index %d\n", q->hw_index); 744 745 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 746 netif_napi_add(lif->netdev, &qcq->napi, ionic_tx_napi, 747 NAPI_POLL_WEIGHT); 748 749 qcq->flags |= IONIC_QCQ_F_INITED; 750 751 return 0; 752 } 753 754 static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 755 { 756 struct device *dev = lif->ionic->dev; 757 struct ionic_queue *q = &qcq->q; 758 struct ionic_cq *cq = &qcq->cq; 759 struct ionic_admin_ctx ctx = { 760 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 761 .cmd.q_init = { 762 .opcode = IONIC_CMD_Q_INIT, 763 .lif_index = cpu_to_le16(lif->index), 764 .type = q->type, 765 .ver = lif->qtype_info[q->type].version, 766 .index = cpu_to_le32(q->index), 767 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 768 IONIC_QINIT_F_SG), 769 .intr_index = cpu_to_le16(cq->bound_intr->index), 770 .pid = cpu_to_le16(q->pid), 771 .ring_size = ilog2(q->num_descs), 772 .ring_base = cpu_to_le64(q->base_pa), 773 .cq_ring_base = cpu_to_le64(cq->base_pa), 774 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 775 }, 776 }; 777 int err; 778 779 dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid); 780 dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index); 781 dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 782 dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 783 dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 784 dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver); 785 dev_dbg(dev, "rxq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 786 787 ionic_qcq_sanitize(qcq); 788 789 err = ionic_adminq_post_wait(lif, &ctx); 790 if (err) 791 return err; 792 793 q->hw_type = ctx.comp.q_init.hw_type; 794 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 795 q->dbval = IONIC_DBELL_QID(q->hw_index); 796 797 dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type); 798 dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index); 799 800 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 801 netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi, 802 NAPI_POLL_WEIGHT); 803 else 804 netif_napi_add(lif->netdev, &qcq->napi, ionic_txrx_napi, 805 NAPI_POLL_WEIGHT); 806 807 qcq->flags |= IONIC_QCQ_F_INITED; 808 809 return 0; 810 } 811 812 static bool ionic_notifyq_service(struct ionic_cq *cq, 813 struct ionic_cq_info *cq_info) 814 { 815 union ionic_notifyq_comp *comp = cq_info->cq_desc; 816 struct ionic_deferred_work *work; 817 struct net_device *netdev; 818 struct ionic_queue *q; 819 struct ionic_lif *lif; 820 u64 eid; 821 822 q = cq->bound_q; 823 lif = q->info[0].cb_arg; 824 netdev = lif->netdev; 825 eid = le64_to_cpu(comp->event.eid); 826 827 /* Have we run out of new completions to process? */ 828 if ((s64)(eid - lif->last_eid) <= 0) 829 return false; 830 831 lif->last_eid = eid; 832 833 dev_dbg(lif->ionic->dev, "notifyq event:\n"); 834 dynamic_hex_dump("event ", DUMP_PREFIX_OFFSET, 16, 1, 835 comp, sizeof(*comp), true); 836 837 switch (le16_to_cpu(comp->event.ecode)) { 838 case IONIC_EVENT_LINK_CHANGE: 839 ionic_link_status_check_request(lif, false); 840 break; 841 case IONIC_EVENT_RESET: 842 work = kzalloc(sizeof(*work), GFP_ATOMIC); 843 if (!work) { 844 netdev_err(lif->netdev, "%s OOM\n", __func__); 845 } else { 846 work->type = IONIC_DW_TYPE_LIF_RESET; 847 ionic_lif_deferred_enqueue(&lif->deferred, work); 848 } 849 break; 850 default: 851 netdev_warn(netdev, "Notifyq event ecode=%d eid=%lld\n", 852 comp->event.ecode, eid); 853 break; 854 } 855 856 return true; 857 } 858 859 static bool ionic_adminq_service(struct ionic_cq *cq, 860 struct ionic_cq_info *cq_info) 861 { 862 struct ionic_admin_comp *comp = cq_info->cq_desc; 863 864 if (!color_match(comp->color, cq->done_color)) 865 return false; 866 867 ionic_q_service(cq->bound_q, cq_info, le16_to_cpu(comp->comp_index)); 868 869 return true; 870 } 871 872 static int ionic_adminq_napi(struct napi_struct *napi, int budget) 873 { 874 struct ionic_intr_info *intr = napi_to_cq(napi)->bound_intr; 875 struct ionic_lif *lif = napi_to_cq(napi)->lif; 876 struct ionic_dev *idev = &lif->ionic->idev; 877 unsigned int flags = 0; 878 int n_work = 0; 879 int a_work = 0; 880 int work_done; 881 882 if (lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED) 883 n_work = ionic_cq_service(&lif->notifyqcq->cq, budget, 884 ionic_notifyq_service, NULL, NULL); 885 886 if (lif->adminqcq && lif->adminqcq->flags & IONIC_QCQ_F_INITED) 887 a_work = ionic_cq_service(&lif->adminqcq->cq, budget, 888 ionic_adminq_service, NULL, NULL); 889 890 work_done = max(n_work, a_work); 891 if (work_done < budget && napi_complete_done(napi, work_done)) { 892 flags |= IONIC_INTR_CRED_UNMASK; 893 lif->adminqcq->cq.bound_intr->rearm_count++; 894 } 895 896 if (work_done || flags) { 897 flags |= IONIC_INTR_CRED_RESET_COALESCE; 898 ionic_intr_credits(idev->intr_ctrl, 899 intr->index, 900 n_work + a_work, flags); 901 } 902 903 return work_done; 904 } 905 906 void ionic_get_stats64(struct net_device *netdev, 907 struct rtnl_link_stats64 *ns) 908 { 909 struct ionic_lif *lif = netdev_priv(netdev); 910 struct ionic_lif_stats *ls; 911 912 memset(ns, 0, sizeof(*ns)); 913 ls = &lif->info->stats; 914 915 ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) + 916 le64_to_cpu(ls->rx_mcast_packets) + 917 le64_to_cpu(ls->rx_bcast_packets); 918 919 ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) + 920 le64_to_cpu(ls->tx_mcast_packets) + 921 le64_to_cpu(ls->tx_bcast_packets); 922 923 ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) + 924 le64_to_cpu(ls->rx_mcast_bytes) + 925 le64_to_cpu(ls->rx_bcast_bytes); 926 927 ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) + 928 le64_to_cpu(ls->tx_mcast_bytes) + 929 le64_to_cpu(ls->tx_bcast_bytes); 930 931 ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) + 932 le64_to_cpu(ls->rx_mcast_drop_packets) + 933 le64_to_cpu(ls->rx_bcast_drop_packets); 934 935 ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) + 936 le64_to_cpu(ls->tx_mcast_drop_packets) + 937 le64_to_cpu(ls->tx_bcast_drop_packets); 938 939 ns->multicast = le64_to_cpu(ls->rx_mcast_packets); 940 941 ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty); 942 943 ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) + 944 le64_to_cpu(ls->rx_queue_disabled) + 945 le64_to_cpu(ls->rx_desc_fetch_error) + 946 le64_to_cpu(ls->rx_desc_data_error); 947 948 ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) + 949 le64_to_cpu(ls->tx_queue_disabled) + 950 le64_to_cpu(ls->tx_desc_fetch_error) + 951 le64_to_cpu(ls->tx_desc_data_error); 952 953 ns->rx_errors = ns->rx_over_errors + 954 ns->rx_missed_errors; 955 956 ns->tx_errors = ns->tx_aborted_errors; 957 } 958 959 static int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr) 960 { 961 struct ionic_admin_ctx ctx = { 962 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 963 .cmd.rx_filter_add = { 964 .opcode = IONIC_CMD_RX_FILTER_ADD, 965 .lif_index = cpu_to_le16(lif->index), 966 .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_MAC), 967 }, 968 }; 969 struct ionic_rx_filter *f; 970 int err; 971 972 /* don't bother if we already have it */ 973 spin_lock_bh(&lif->rx_filters.lock); 974 f = ionic_rx_filter_by_addr(lif, addr); 975 spin_unlock_bh(&lif->rx_filters.lock); 976 if (f) 977 return 0; 978 979 netdev_dbg(lif->netdev, "rx_filter add ADDR %pM\n", addr); 980 981 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, ETH_ALEN); 982 err = ionic_adminq_post_wait(lif, &ctx); 983 if (err && err != -EEXIST) 984 return err; 985 986 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx); 987 } 988 989 static int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr) 990 { 991 struct ionic_admin_ctx ctx = { 992 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 993 .cmd.rx_filter_del = { 994 .opcode = IONIC_CMD_RX_FILTER_DEL, 995 .lif_index = cpu_to_le16(lif->index), 996 }, 997 }; 998 struct ionic_rx_filter *f; 999 int err; 1000 1001 spin_lock_bh(&lif->rx_filters.lock); 1002 f = ionic_rx_filter_by_addr(lif, addr); 1003 if (!f) { 1004 spin_unlock_bh(&lif->rx_filters.lock); 1005 return -ENOENT; 1006 } 1007 1008 netdev_dbg(lif->netdev, "rx_filter del ADDR %pM (id %d)\n", 1009 addr, f->filter_id); 1010 1011 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id); 1012 ionic_rx_filter_free(lif, f); 1013 spin_unlock_bh(&lif->rx_filters.lock); 1014 1015 err = ionic_adminq_post_wait(lif, &ctx); 1016 if (err && err != -EEXIST) 1017 return err; 1018 1019 return 0; 1020 } 1021 1022 static int ionic_lif_addr(struct ionic_lif *lif, const u8 *addr, bool add, 1023 bool can_sleep) 1024 { 1025 struct ionic_deferred_work *work; 1026 unsigned int nmfilters; 1027 unsigned int nufilters; 1028 1029 if (add) { 1030 /* Do we have space for this filter? We test the counters 1031 * here before checking the need for deferral so that we 1032 * can return an overflow error to the stack. 1033 */ 1034 nmfilters = le32_to_cpu(lif->identity->eth.max_mcast_filters); 1035 nufilters = le32_to_cpu(lif->identity->eth.max_ucast_filters); 1036 1037 if ((is_multicast_ether_addr(addr) && lif->nmcast < nmfilters)) 1038 lif->nmcast++; 1039 else if (!is_multicast_ether_addr(addr) && 1040 lif->nucast < nufilters) 1041 lif->nucast++; 1042 else 1043 return -ENOSPC; 1044 } else { 1045 if (is_multicast_ether_addr(addr) && lif->nmcast) 1046 lif->nmcast--; 1047 else if (!is_multicast_ether_addr(addr) && lif->nucast) 1048 lif->nucast--; 1049 } 1050 1051 if (!can_sleep) { 1052 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1053 if (!work) { 1054 netdev_err(lif->netdev, "%s OOM\n", __func__); 1055 return -ENOMEM; 1056 } 1057 work->type = add ? IONIC_DW_TYPE_RX_ADDR_ADD : 1058 IONIC_DW_TYPE_RX_ADDR_DEL; 1059 memcpy(work->addr, addr, ETH_ALEN); 1060 netdev_dbg(lif->netdev, "deferred: rx_filter %s %pM\n", 1061 add ? "add" : "del", addr); 1062 ionic_lif_deferred_enqueue(&lif->deferred, work); 1063 } else { 1064 netdev_dbg(lif->netdev, "rx_filter %s %pM\n", 1065 add ? "add" : "del", addr); 1066 if (add) 1067 return ionic_lif_addr_add(lif, addr); 1068 else 1069 return ionic_lif_addr_del(lif, addr); 1070 } 1071 1072 return 0; 1073 } 1074 1075 static int ionic_addr_add(struct net_device *netdev, const u8 *addr) 1076 { 1077 return ionic_lif_addr(netdev_priv(netdev), addr, ADD_ADDR, CAN_SLEEP); 1078 } 1079 1080 static int ionic_ndo_addr_add(struct net_device *netdev, const u8 *addr) 1081 { 1082 return ionic_lif_addr(netdev_priv(netdev), addr, ADD_ADDR, CAN_NOT_SLEEP); 1083 } 1084 1085 static int ionic_addr_del(struct net_device *netdev, const u8 *addr) 1086 { 1087 return ionic_lif_addr(netdev_priv(netdev), addr, DEL_ADDR, CAN_SLEEP); 1088 } 1089 1090 static int ionic_ndo_addr_del(struct net_device *netdev, const u8 *addr) 1091 { 1092 return ionic_lif_addr(netdev_priv(netdev), addr, DEL_ADDR, CAN_NOT_SLEEP); 1093 } 1094 1095 static void ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode) 1096 { 1097 struct ionic_admin_ctx ctx = { 1098 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1099 .cmd.rx_mode_set = { 1100 .opcode = IONIC_CMD_RX_MODE_SET, 1101 .lif_index = cpu_to_le16(lif->index), 1102 .rx_mode = cpu_to_le16(rx_mode), 1103 }, 1104 }; 1105 char buf[128]; 1106 int err; 1107 int i; 1108 #define REMAIN(__x) (sizeof(buf) - (__x)) 1109 1110 i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:", 1111 lif->rx_mode, rx_mode); 1112 if (rx_mode & IONIC_RX_MODE_F_UNICAST) 1113 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST"); 1114 if (rx_mode & IONIC_RX_MODE_F_MULTICAST) 1115 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST"); 1116 if (rx_mode & IONIC_RX_MODE_F_BROADCAST) 1117 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST"); 1118 if (rx_mode & IONIC_RX_MODE_F_PROMISC) 1119 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC"); 1120 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI) 1121 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI"); 1122 netdev_dbg(lif->netdev, "lif%d %s\n", lif->index, buf); 1123 1124 err = ionic_adminq_post_wait(lif, &ctx); 1125 if (err) 1126 netdev_warn(lif->netdev, "set rx_mode 0x%04x failed: %d\n", 1127 rx_mode, err); 1128 else 1129 lif->rx_mode = rx_mode; 1130 } 1131 1132 static void ionic_set_rx_mode(struct net_device *netdev, bool can_sleep) 1133 { 1134 struct ionic_lif *lif = netdev_priv(netdev); 1135 struct ionic_deferred_work *work; 1136 unsigned int nfilters; 1137 unsigned int rx_mode; 1138 1139 rx_mode = IONIC_RX_MODE_F_UNICAST; 1140 rx_mode |= (netdev->flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0; 1141 rx_mode |= (netdev->flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0; 1142 rx_mode |= (netdev->flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0; 1143 rx_mode |= (netdev->flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0; 1144 1145 /* sync unicast addresses 1146 * next check to see if we're in an overflow state 1147 * if so, we track that we overflowed and enable NIC PROMISC 1148 * else if the overflow is set and not needed 1149 * we remove our overflow flag and check the netdev flags 1150 * to see if we can disable NIC PROMISC 1151 */ 1152 if (can_sleep) 1153 __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del); 1154 else 1155 __dev_uc_sync(netdev, ionic_ndo_addr_add, ionic_ndo_addr_del); 1156 nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters); 1157 if (netdev_uc_count(netdev) + 1 > nfilters) { 1158 rx_mode |= IONIC_RX_MODE_F_PROMISC; 1159 lif->uc_overflow = true; 1160 } else if (lif->uc_overflow) { 1161 lif->uc_overflow = false; 1162 if (!(netdev->flags & IFF_PROMISC)) 1163 rx_mode &= ~IONIC_RX_MODE_F_PROMISC; 1164 } 1165 1166 /* same for multicast */ 1167 if (can_sleep) 1168 __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del); 1169 else 1170 __dev_mc_sync(netdev, ionic_ndo_addr_add, ionic_ndo_addr_del); 1171 nfilters = le32_to_cpu(lif->identity->eth.max_mcast_filters); 1172 if (netdev_mc_count(netdev) > nfilters) { 1173 rx_mode |= IONIC_RX_MODE_F_ALLMULTI; 1174 lif->mc_overflow = true; 1175 } else if (lif->mc_overflow) { 1176 lif->mc_overflow = false; 1177 if (!(netdev->flags & IFF_ALLMULTI)) 1178 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI; 1179 } 1180 1181 if (lif->rx_mode != rx_mode) { 1182 if (!can_sleep) { 1183 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1184 if (!work) { 1185 netdev_err(lif->netdev, "%s OOM\n", __func__); 1186 return; 1187 } 1188 work->type = IONIC_DW_TYPE_RX_MODE; 1189 work->rx_mode = rx_mode; 1190 netdev_dbg(lif->netdev, "deferred: rx_mode\n"); 1191 ionic_lif_deferred_enqueue(&lif->deferred, work); 1192 } else { 1193 ionic_lif_rx_mode(lif, rx_mode); 1194 } 1195 } 1196 } 1197 1198 static void ionic_ndo_set_rx_mode(struct net_device *netdev) 1199 { 1200 ionic_set_rx_mode(netdev, CAN_NOT_SLEEP); 1201 } 1202 1203 static __le64 ionic_netdev_features_to_nic(netdev_features_t features) 1204 { 1205 u64 wanted = 0; 1206 1207 if (features & NETIF_F_HW_VLAN_CTAG_TX) 1208 wanted |= IONIC_ETH_HW_VLAN_TX_TAG; 1209 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1210 wanted |= IONIC_ETH_HW_VLAN_RX_STRIP; 1211 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1212 wanted |= IONIC_ETH_HW_VLAN_RX_FILTER; 1213 if (features & NETIF_F_RXHASH) 1214 wanted |= IONIC_ETH_HW_RX_HASH; 1215 if (features & NETIF_F_RXCSUM) 1216 wanted |= IONIC_ETH_HW_RX_CSUM; 1217 if (features & NETIF_F_SG) 1218 wanted |= IONIC_ETH_HW_TX_SG; 1219 if (features & NETIF_F_HW_CSUM) 1220 wanted |= IONIC_ETH_HW_TX_CSUM; 1221 if (features & NETIF_F_TSO) 1222 wanted |= IONIC_ETH_HW_TSO; 1223 if (features & NETIF_F_TSO6) 1224 wanted |= IONIC_ETH_HW_TSO_IPV6; 1225 if (features & NETIF_F_TSO_ECN) 1226 wanted |= IONIC_ETH_HW_TSO_ECN; 1227 if (features & NETIF_F_GSO_GRE) 1228 wanted |= IONIC_ETH_HW_TSO_GRE; 1229 if (features & NETIF_F_GSO_GRE_CSUM) 1230 wanted |= IONIC_ETH_HW_TSO_GRE_CSUM; 1231 if (features & NETIF_F_GSO_IPXIP4) 1232 wanted |= IONIC_ETH_HW_TSO_IPXIP4; 1233 if (features & NETIF_F_GSO_IPXIP6) 1234 wanted |= IONIC_ETH_HW_TSO_IPXIP6; 1235 if (features & NETIF_F_GSO_UDP_TUNNEL) 1236 wanted |= IONIC_ETH_HW_TSO_UDP; 1237 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) 1238 wanted |= IONIC_ETH_HW_TSO_UDP_CSUM; 1239 1240 return cpu_to_le64(wanted); 1241 } 1242 1243 static int ionic_set_nic_features(struct ionic_lif *lif, 1244 netdev_features_t features) 1245 { 1246 struct device *dev = lif->ionic->dev; 1247 struct ionic_admin_ctx ctx = { 1248 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1249 .cmd.lif_setattr = { 1250 .opcode = IONIC_CMD_LIF_SETATTR, 1251 .index = cpu_to_le16(lif->index), 1252 .attr = IONIC_LIF_ATTR_FEATURES, 1253 }, 1254 }; 1255 u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG | 1256 IONIC_ETH_HW_VLAN_RX_STRIP | 1257 IONIC_ETH_HW_VLAN_RX_FILTER; 1258 u64 old_hw_features; 1259 int err; 1260 1261 ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features); 1262 err = ionic_adminq_post_wait(lif, &ctx); 1263 if (err) 1264 return err; 1265 1266 old_hw_features = lif->hw_features; 1267 lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features & 1268 ctx.comp.lif_setattr.features); 1269 1270 if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH) 1271 ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1272 1273 if ((vlan_flags & features) && 1274 !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features))) 1275 dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n"); 1276 1277 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1278 dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n"); 1279 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1280 dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n"); 1281 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1282 dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n"); 1283 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1284 dev_dbg(dev, "feature ETH_HW_RX_HASH\n"); 1285 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1286 dev_dbg(dev, "feature ETH_HW_TX_SG\n"); 1287 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1288 dev_dbg(dev, "feature ETH_HW_TX_CSUM\n"); 1289 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1290 dev_dbg(dev, "feature ETH_HW_RX_CSUM\n"); 1291 if (lif->hw_features & IONIC_ETH_HW_TSO) 1292 dev_dbg(dev, "feature ETH_HW_TSO\n"); 1293 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1294 dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n"); 1295 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1296 dev_dbg(dev, "feature ETH_HW_TSO_ECN\n"); 1297 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1298 dev_dbg(dev, "feature ETH_HW_TSO_GRE\n"); 1299 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1300 dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n"); 1301 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1302 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n"); 1303 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1304 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n"); 1305 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1306 dev_dbg(dev, "feature ETH_HW_TSO_UDP\n"); 1307 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1308 dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n"); 1309 1310 return 0; 1311 } 1312 1313 static int ionic_init_nic_features(struct ionic_lif *lif) 1314 { 1315 struct net_device *netdev = lif->netdev; 1316 netdev_features_t features; 1317 int err; 1318 1319 /* set up what we expect to support by default */ 1320 features = NETIF_F_HW_VLAN_CTAG_TX | 1321 NETIF_F_HW_VLAN_CTAG_RX | 1322 NETIF_F_HW_VLAN_CTAG_FILTER | 1323 NETIF_F_RXHASH | 1324 NETIF_F_SG | 1325 NETIF_F_HW_CSUM | 1326 NETIF_F_RXCSUM | 1327 NETIF_F_TSO | 1328 NETIF_F_TSO6 | 1329 NETIF_F_TSO_ECN; 1330 1331 err = ionic_set_nic_features(lif, features); 1332 if (err) 1333 return err; 1334 1335 /* tell the netdev what we actually can support */ 1336 netdev->features |= NETIF_F_HIGHDMA; 1337 1338 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1339 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 1340 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1341 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 1342 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1343 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1344 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1345 netdev->hw_features |= NETIF_F_RXHASH; 1346 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1347 netdev->hw_features |= NETIF_F_SG; 1348 1349 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1350 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 1351 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1352 netdev->hw_enc_features |= NETIF_F_RXCSUM; 1353 if (lif->hw_features & IONIC_ETH_HW_TSO) 1354 netdev->hw_enc_features |= NETIF_F_TSO; 1355 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1356 netdev->hw_enc_features |= NETIF_F_TSO6; 1357 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1358 netdev->hw_enc_features |= NETIF_F_TSO_ECN; 1359 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1360 netdev->hw_enc_features |= NETIF_F_GSO_GRE; 1361 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1362 netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM; 1363 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1364 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4; 1365 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1366 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6; 1367 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1368 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL; 1369 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1370 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 1371 1372 netdev->hw_features |= netdev->hw_enc_features; 1373 netdev->features |= netdev->hw_features; 1374 netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES; 1375 1376 netdev->priv_flags |= IFF_UNICAST_FLT | 1377 IFF_LIVE_ADDR_CHANGE; 1378 1379 return 0; 1380 } 1381 1382 static int ionic_set_features(struct net_device *netdev, 1383 netdev_features_t features) 1384 { 1385 struct ionic_lif *lif = netdev_priv(netdev); 1386 int err; 1387 1388 netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n", 1389 __func__, (u64)lif->netdev->features, (u64)features); 1390 1391 err = ionic_set_nic_features(lif, features); 1392 1393 return err; 1394 } 1395 1396 static int ionic_set_mac_address(struct net_device *netdev, void *sa) 1397 { 1398 struct sockaddr *addr = sa; 1399 u8 *mac; 1400 int err; 1401 1402 mac = (u8 *)addr->sa_data; 1403 if (ether_addr_equal(netdev->dev_addr, mac)) 1404 return 0; 1405 1406 err = eth_prepare_mac_addr_change(netdev, addr); 1407 if (err) 1408 return err; 1409 1410 if (!is_zero_ether_addr(netdev->dev_addr)) { 1411 netdev_info(netdev, "deleting mac addr %pM\n", 1412 netdev->dev_addr); 1413 ionic_addr_del(netdev, netdev->dev_addr); 1414 } 1415 1416 eth_commit_mac_addr_change(netdev, addr); 1417 netdev_info(netdev, "updating mac addr %pM\n", mac); 1418 1419 return ionic_addr_add(netdev, mac); 1420 } 1421 1422 static void ionic_stop_queues_reconfig(struct ionic_lif *lif) 1423 { 1424 /* Stop and clean the queues before reconfiguration */ 1425 mutex_lock(&lif->queue_lock); 1426 netif_device_detach(lif->netdev); 1427 ionic_stop_queues(lif); 1428 ionic_txrx_deinit(lif); 1429 } 1430 1431 static int ionic_start_queues_reconfig(struct ionic_lif *lif) 1432 { 1433 int err; 1434 1435 /* Re-init the queues after reconfiguration */ 1436 1437 /* The only way txrx_init can fail here is if communication 1438 * with FW is suddenly broken. There's not much we can do 1439 * at this point - error messages have already been printed, 1440 * so we can continue on and the user can eventually do a 1441 * DOWN and UP to try to reset and clear the issue. 1442 */ 1443 err = ionic_txrx_init(lif); 1444 mutex_unlock(&lif->queue_lock); 1445 ionic_link_status_check_request(lif, true); 1446 netif_device_attach(lif->netdev); 1447 1448 return err; 1449 } 1450 1451 static int ionic_change_mtu(struct net_device *netdev, int new_mtu) 1452 { 1453 struct ionic_lif *lif = netdev_priv(netdev); 1454 struct ionic_admin_ctx ctx = { 1455 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1456 .cmd.lif_setattr = { 1457 .opcode = IONIC_CMD_LIF_SETATTR, 1458 .index = cpu_to_le16(lif->index), 1459 .attr = IONIC_LIF_ATTR_MTU, 1460 .mtu = cpu_to_le32(new_mtu), 1461 }, 1462 }; 1463 int err; 1464 1465 err = ionic_adminq_post_wait(lif, &ctx); 1466 if (err) 1467 return err; 1468 1469 netdev->mtu = new_mtu; 1470 /* if we're not running, nothing more to do */ 1471 if (!netif_running(netdev)) 1472 return 0; 1473 1474 ionic_stop_queues_reconfig(lif); 1475 return ionic_start_queues_reconfig(lif); 1476 } 1477 1478 static void ionic_tx_timeout_work(struct work_struct *ws) 1479 { 1480 struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work); 1481 1482 netdev_info(lif->netdev, "Tx Timeout recovery\n"); 1483 1484 /* if we were stopped before this scheduled job was launched, 1485 * don't bother the queues as they are already stopped. 1486 */ 1487 if (!netif_running(lif->netdev)) 1488 return; 1489 1490 ionic_stop_queues_reconfig(lif); 1491 ionic_start_queues_reconfig(lif); 1492 } 1493 1494 static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1495 { 1496 struct ionic_lif *lif = netdev_priv(netdev); 1497 1498 schedule_work(&lif->tx_timeout_work); 1499 } 1500 1501 static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, 1502 u16 vid) 1503 { 1504 struct ionic_lif *lif = netdev_priv(netdev); 1505 struct ionic_admin_ctx ctx = { 1506 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1507 .cmd.rx_filter_add = { 1508 .opcode = IONIC_CMD_RX_FILTER_ADD, 1509 .lif_index = cpu_to_le16(lif->index), 1510 .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_VLAN), 1511 .vlan.vlan = cpu_to_le16(vid), 1512 }, 1513 }; 1514 int err; 1515 1516 netdev_dbg(netdev, "rx_filter add VLAN %d\n", vid); 1517 err = ionic_adminq_post_wait(lif, &ctx); 1518 if (err) 1519 return err; 1520 1521 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx); 1522 } 1523 1524 static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, 1525 u16 vid) 1526 { 1527 struct ionic_lif *lif = netdev_priv(netdev); 1528 struct ionic_admin_ctx ctx = { 1529 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1530 .cmd.rx_filter_del = { 1531 .opcode = IONIC_CMD_RX_FILTER_DEL, 1532 .lif_index = cpu_to_le16(lif->index), 1533 }, 1534 }; 1535 struct ionic_rx_filter *f; 1536 1537 spin_lock_bh(&lif->rx_filters.lock); 1538 1539 f = ionic_rx_filter_by_vlan(lif, vid); 1540 if (!f) { 1541 spin_unlock_bh(&lif->rx_filters.lock); 1542 return -ENOENT; 1543 } 1544 1545 netdev_dbg(netdev, "rx_filter del VLAN %d (id %d)\n", 1546 vid, f->filter_id); 1547 1548 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id); 1549 ionic_rx_filter_free(lif, f); 1550 spin_unlock_bh(&lif->rx_filters.lock); 1551 1552 return ionic_adminq_post_wait(lif, &ctx); 1553 } 1554 1555 int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types, 1556 const u8 *key, const u32 *indir) 1557 { 1558 struct ionic_admin_ctx ctx = { 1559 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1560 .cmd.lif_setattr = { 1561 .opcode = IONIC_CMD_LIF_SETATTR, 1562 .attr = IONIC_LIF_ATTR_RSS, 1563 .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa), 1564 }, 1565 }; 1566 unsigned int i, tbl_sz; 1567 1568 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) { 1569 lif->rss_types = types; 1570 ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types); 1571 } 1572 1573 if (key) 1574 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE); 1575 1576 if (indir) { 1577 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1578 for (i = 0; i < tbl_sz; i++) 1579 lif->rss_ind_tbl[i] = indir[i]; 1580 } 1581 1582 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key, 1583 IONIC_RSS_HASH_KEY_SIZE); 1584 1585 return ionic_adminq_post_wait(lif, &ctx); 1586 } 1587 1588 static int ionic_lif_rss_init(struct ionic_lif *lif) 1589 { 1590 unsigned int tbl_sz; 1591 unsigned int i; 1592 1593 lif->rss_types = IONIC_RSS_TYPE_IPV4 | 1594 IONIC_RSS_TYPE_IPV4_TCP | 1595 IONIC_RSS_TYPE_IPV4_UDP | 1596 IONIC_RSS_TYPE_IPV6 | 1597 IONIC_RSS_TYPE_IPV6_TCP | 1598 IONIC_RSS_TYPE_IPV6_UDP; 1599 1600 /* Fill indirection table with 'default' values */ 1601 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1602 for (i = 0; i < tbl_sz; i++) 1603 lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs); 1604 1605 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1606 } 1607 1608 static void ionic_lif_rss_deinit(struct ionic_lif *lif) 1609 { 1610 int tbl_sz; 1611 1612 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1613 memset(lif->rss_ind_tbl, 0, tbl_sz); 1614 memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE); 1615 1616 ionic_lif_rss_config(lif, 0x0, NULL, NULL); 1617 } 1618 1619 static void ionic_lif_quiesce(struct ionic_lif *lif) 1620 { 1621 struct ionic_admin_ctx ctx = { 1622 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1623 .cmd.lif_setattr = { 1624 .opcode = IONIC_CMD_LIF_SETATTR, 1625 .index = cpu_to_le16(lif->index), 1626 .attr = IONIC_LIF_ATTR_STATE, 1627 .state = IONIC_LIF_QUIESCE, 1628 }, 1629 }; 1630 int err; 1631 1632 err = ionic_adminq_post_wait(lif, &ctx); 1633 if (err) 1634 netdev_err(lif->netdev, "lif quiesce failed %d\n", err); 1635 } 1636 1637 static void ionic_txrx_disable(struct ionic_lif *lif) 1638 { 1639 unsigned int i; 1640 int err = 0; 1641 1642 if (lif->txqcqs) { 1643 for (i = 0; i < lif->nxqs; i++) 1644 err = ionic_qcq_disable(lif->txqcqs[i], (err != -ETIMEDOUT)); 1645 } 1646 1647 if (lif->rxqcqs) { 1648 for (i = 0; i < lif->nxqs; i++) 1649 err = ionic_qcq_disable(lif->rxqcqs[i], (err != -ETIMEDOUT)); 1650 } 1651 1652 ionic_lif_quiesce(lif); 1653 } 1654 1655 static void ionic_txrx_deinit(struct ionic_lif *lif) 1656 { 1657 unsigned int i; 1658 1659 if (lif->txqcqs) { 1660 for (i = 0; i < lif->nxqs && lif->txqcqs[i]; i++) { 1661 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 1662 ionic_tx_flush(&lif->txqcqs[i]->cq); 1663 ionic_tx_empty(&lif->txqcqs[i]->q); 1664 } 1665 } 1666 1667 if (lif->rxqcqs) { 1668 for (i = 0; i < lif->nxqs && lif->rxqcqs[i]; i++) { 1669 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 1670 ionic_rx_empty(&lif->rxqcqs[i]->q); 1671 } 1672 } 1673 lif->rx_mode = 0; 1674 } 1675 1676 static void ionic_txrx_free(struct ionic_lif *lif) 1677 { 1678 unsigned int i; 1679 1680 if (lif->txqcqs) { 1681 for (i = 0; i < lif->ionic->ntxqs_per_lif && lif->txqcqs[i]; i++) { 1682 ionic_qcq_free(lif, lif->txqcqs[i]); 1683 devm_kfree(lif->ionic->dev, lif->txqcqs[i]); 1684 lif->txqcqs[i] = NULL; 1685 } 1686 } 1687 1688 if (lif->rxqcqs) { 1689 for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) { 1690 ionic_qcq_free(lif, lif->rxqcqs[i]); 1691 devm_kfree(lif->ionic->dev, lif->rxqcqs[i]); 1692 lif->rxqcqs[i] = NULL; 1693 } 1694 } 1695 } 1696 1697 static int ionic_txrx_alloc(struct ionic_lif *lif) 1698 { 1699 unsigned int sg_desc_sz; 1700 unsigned int flags; 1701 unsigned int i; 1702 int err = 0; 1703 1704 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 1705 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 1706 sizeof(struct ionic_txq_sg_desc_v1)) 1707 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 1708 else 1709 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 1710 1711 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 1712 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 1713 flags |= IONIC_QCQ_F_INTR; 1714 for (i = 0; i < lif->nxqs; i++) { 1715 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 1716 lif->ntxq_descs, 1717 sizeof(struct ionic_txq_desc), 1718 sizeof(struct ionic_txq_comp), 1719 sg_desc_sz, 1720 lif->kern_pid, &lif->txqcqs[i]); 1721 if (err) 1722 goto err_out; 1723 1724 if (flags & IONIC_QCQ_F_INTR) { 1725 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 1726 lif->txqcqs[i]->intr.index, 1727 lif->tx_coalesce_hw); 1728 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 1729 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 1730 } 1731 1732 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 1733 } 1734 1735 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG | IONIC_QCQ_F_INTR; 1736 for (i = 0; i < lif->nxqs; i++) { 1737 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 1738 lif->nrxq_descs, 1739 sizeof(struct ionic_rxq_desc), 1740 sizeof(struct ionic_rxq_comp), 1741 sizeof(struct ionic_rxq_sg_desc), 1742 lif->kern_pid, &lif->rxqcqs[i]); 1743 if (err) 1744 goto err_out; 1745 1746 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 1747 lif->rxqcqs[i]->intr.index, 1748 lif->rx_coalesce_hw); 1749 if (test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state)) 1750 lif->rxqcqs[i]->intr.dim_coal_hw = lif->rx_coalesce_hw; 1751 1752 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 1753 ionic_link_qcq_interrupts(lif->rxqcqs[i], 1754 lif->txqcqs[i]); 1755 1756 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 1757 } 1758 1759 return 0; 1760 1761 err_out: 1762 ionic_txrx_free(lif); 1763 1764 return err; 1765 } 1766 1767 static int ionic_txrx_init(struct ionic_lif *lif) 1768 { 1769 unsigned int i; 1770 int err; 1771 1772 for (i = 0; i < lif->nxqs; i++) { 1773 err = ionic_lif_txq_init(lif, lif->txqcqs[i]); 1774 if (err) 1775 goto err_out; 1776 1777 err = ionic_lif_rxq_init(lif, lif->rxqcqs[i]); 1778 if (err) { 1779 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 1780 goto err_out; 1781 } 1782 } 1783 1784 if (lif->netdev->features & NETIF_F_RXHASH) 1785 ionic_lif_rss_init(lif); 1786 1787 ionic_set_rx_mode(lif->netdev, CAN_SLEEP); 1788 1789 return 0; 1790 1791 err_out: 1792 while (i--) { 1793 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 1794 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 1795 } 1796 1797 return err; 1798 } 1799 1800 static int ionic_txrx_enable(struct ionic_lif *lif) 1801 { 1802 int derr = 0; 1803 int i, err; 1804 1805 for (i = 0; i < lif->nxqs; i++) { 1806 if (!(lif->rxqcqs[i] && lif->txqcqs[i])) { 1807 dev_err(lif->ionic->dev, "%s: bad qcq %d\n", __func__, i); 1808 err = -ENXIO; 1809 goto err_out; 1810 } 1811 1812 ionic_rx_fill(&lif->rxqcqs[i]->q); 1813 err = ionic_qcq_enable(lif->rxqcqs[i]); 1814 if (err) 1815 goto err_out; 1816 1817 err = ionic_qcq_enable(lif->txqcqs[i]); 1818 if (err) { 1819 derr = ionic_qcq_disable(lif->rxqcqs[i], (err != -ETIMEDOUT)); 1820 goto err_out; 1821 } 1822 } 1823 1824 return 0; 1825 1826 err_out: 1827 while (i--) { 1828 derr = ionic_qcq_disable(lif->txqcqs[i], (derr != -ETIMEDOUT)); 1829 derr = ionic_qcq_disable(lif->rxqcqs[i], (derr != -ETIMEDOUT)); 1830 } 1831 1832 return err; 1833 } 1834 1835 static int ionic_start_queues(struct ionic_lif *lif) 1836 { 1837 int err; 1838 1839 if (test_and_set_bit(IONIC_LIF_F_UP, lif->state)) 1840 return 0; 1841 1842 err = ionic_txrx_enable(lif); 1843 if (err) { 1844 clear_bit(IONIC_LIF_F_UP, lif->state); 1845 return err; 1846 } 1847 netif_tx_wake_all_queues(lif->netdev); 1848 1849 return 0; 1850 } 1851 1852 static int ionic_open(struct net_device *netdev) 1853 { 1854 struct ionic_lif *lif = netdev_priv(netdev); 1855 int err; 1856 1857 err = ionic_txrx_alloc(lif); 1858 if (err) 1859 return err; 1860 1861 err = ionic_txrx_init(lif); 1862 if (err) 1863 goto err_out; 1864 1865 err = netif_set_real_num_tx_queues(netdev, lif->nxqs); 1866 if (err) 1867 goto err_txrx_deinit; 1868 1869 err = netif_set_real_num_rx_queues(netdev, lif->nxqs); 1870 if (err) 1871 goto err_txrx_deinit; 1872 1873 /* don't start the queues until we have link */ 1874 if (netif_carrier_ok(netdev)) { 1875 err = ionic_start_queues(lif); 1876 if (err) 1877 goto err_txrx_deinit; 1878 } 1879 1880 return 0; 1881 1882 err_txrx_deinit: 1883 ionic_txrx_deinit(lif); 1884 err_out: 1885 ionic_txrx_free(lif); 1886 return err; 1887 } 1888 1889 static void ionic_stop_queues(struct ionic_lif *lif) 1890 { 1891 if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state)) 1892 return; 1893 1894 netif_tx_disable(lif->netdev); 1895 ionic_txrx_disable(lif); 1896 } 1897 1898 static int ionic_stop(struct net_device *netdev) 1899 { 1900 struct ionic_lif *lif = netdev_priv(netdev); 1901 1902 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 1903 return 0; 1904 1905 ionic_stop_queues(lif); 1906 ionic_txrx_deinit(lif); 1907 ionic_txrx_free(lif); 1908 1909 return 0; 1910 } 1911 1912 static int ionic_get_vf_config(struct net_device *netdev, 1913 int vf, struct ifla_vf_info *ivf) 1914 { 1915 struct ionic_lif *lif = netdev_priv(netdev); 1916 struct ionic *ionic = lif->ionic; 1917 int ret = 0; 1918 1919 if (!netif_device_present(netdev)) 1920 return -EBUSY; 1921 1922 down_read(&ionic->vf_op_lock); 1923 1924 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1925 ret = -EINVAL; 1926 } else { 1927 ivf->vf = vf; 1928 ivf->vlan = le16_to_cpu(ionic->vfs[vf].vlanid); 1929 ivf->qos = 0; 1930 ivf->spoofchk = ionic->vfs[vf].spoofchk; 1931 ivf->linkstate = ionic->vfs[vf].linkstate; 1932 ivf->max_tx_rate = le32_to_cpu(ionic->vfs[vf].maxrate); 1933 ivf->trusted = ionic->vfs[vf].trusted; 1934 ether_addr_copy(ivf->mac, ionic->vfs[vf].macaddr); 1935 } 1936 1937 up_read(&ionic->vf_op_lock); 1938 return ret; 1939 } 1940 1941 static int ionic_get_vf_stats(struct net_device *netdev, int vf, 1942 struct ifla_vf_stats *vf_stats) 1943 { 1944 struct ionic_lif *lif = netdev_priv(netdev); 1945 struct ionic *ionic = lif->ionic; 1946 struct ionic_lif_stats *vs; 1947 int ret = 0; 1948 1949 if (!netif_device_present(netdev)) 1950 return -EBUSY; 1951 1952 down_read(&ionic->vf_op_lock); 1953 1954 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1955 ret = -EINVAL; 1956 } else { 1957 memset(vf_stats, 0, sizeof(*vf_stats)); 1958 vs = &ionic->vfs[vf].stats; 1959 1960 vf_stats->rx_packets = le64_to_cpu(vs->rx_ucast_packets); 1961 vf_stats->tx_packets = le64_to_cpu(vs->tx_ucast_packets); 1962 vf_stats->rx_bytes = le64_to_cpu(vs->rx_ucast_bytes); 1963 vf_stats->tx_bytes = le64_to_cpu(vs->tx_ucast_bytes); 1964 vf_stats->broadcast = le64_to_cpu(vs->rx_bcast_packets); 1965 vf_stats->multicast = le64_to_cpu(vs->rx_mcast_packets); 1966 vf_stats->rx_dropped = le64_to_cpu(vs->rx_ucast_drop_packets) + 1967 le64_to_cpu(vs->rx_mcast_drop_packets) + 1968 le64_to_cpu(vs->rx_bcast_drop_packets); 1969 vf_stats->tx_dropped = le64_to_cpu(vs->tx_ucast_drop_packets) + 1970 le64_to_cpu(vs->tx_mcast_drop_packets) + 1971 le64_to_cpu(vs->tx_bcast_drop_packets); 1972 } 1973 1974 up_read(&ionic->vf_op_lock); 1975 return ret; 1976 } 1977 1978 static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 1979 { 1980 struct ionic_lif *lif = netdev_priv(netdev); 1981 struct ionic *ionic = lif->ionic; 1982 int ret; 1983 1984 if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac))) 1985 return -EINVAL; 1986 1987 if (!netif_device_present(netdev)) 1988 return -EBUSY; 1989 1990 down_write(&ionic->vf_op_lock); 1991 1992 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1993 ret = -EINVAL; 1994 } else { 1995 ret = ionic_set_vf_config(ionic, vf, IONIC_VF_ATTR_MAC, mac); 1996 if (!ret) 1997 ether_addr_copy(ionic->vfs[vf].macaddr, mac); 1998 } 1999 2000 up_write(&ionic->vf_op_lock); 2001 return ret; 2002 } 2003 2004 static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 2005 u8 qos, __be16 proto) 2006 { 2007 struct ionic_lif *lif = netdev_priv(netdev); 2008 struct ionic *ionic = lif->ionic; 2009 int ret; 2010 2011 /* until someday when we support qos */ 2012 if (qos) 2013 return -EINVAL; 2014 2015 if (vlan > 4095) 2016 return -EINVAL; 2017 2018 if (proto != htons(ETH_P_8021Q)) 2019 return -EPROTONOSUPPORT; 2020 2021 if (!netif_device_present(netdev)) 2022 return -EBUSY; 2023 2024 down_write(&ionic->vf_op_lock); 2025 2026 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2027 ret = -EINVAL; 2028 } else { 2029 ret = ionic_set_vf_config(ionic, vf, 2030 IONIC_VF_ATTR_VLAN, (u8 *)&vlan); 2031 if (!ret) 2032 ionic->vfs[vf].vlanid = cpu_to_le16(vlan); 2033 } 2034 2035 up_write(&ionic->vf_op_lock); 2036 return ret; 2037 } 2038 2039 static int ionic_set_vf_rate(struct net_device *netdev, int vf, 2040 int tx_min, int tx_max) 2041 { 2042 struct ionic_lif *lif = netdev_priv(netdev); 2043 struct ionic *ionic = lif->ionic; 2044 int ret; 2045 2046 /* setting the min just seems silly */ 2047 if (tx_min) 2048 return -EINVAL; 2049 2050 if (!netif_device_present(netdev)) 2051 return -EBUSY; 2052 2053 down_write(&ionic->vf_op_lock); 2054 2055 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2056 ret = -EINVAL; 2057 } else { 2058 ret = ionic_set_vf_config(ionic, vf, 2059 IONIC_VF_ATTR_RATE, (u8 *)&tx_max); 2060 if (!ret) 2061 lif->ionic->vfs[vf].maxrate = cpu_to_le32(tx_max); 2062 } 2063 2064 up_write(&ionic->vf_op_lock); 2065 return ret; 2066 } 2067 2068 static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set) 2069 { 2070 struct ionic_lif *lif = netdev_priv(netdev); 2071 struct ionic *ionic = lif->ionic; 2072 u8 data = set; /* convert to u8 for config */ 2073 int ret; 2074 2075 if (!netif_device_present(netdev)) 2076 return -EBUSY; 2077 2078 down_write(&ionic->vf_op_lock); 2079 2080 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2081 ret = -EINVAL; 2082 } else { 2083 ret = ionic_set_vf_config(ionic, vf, 2084 IONIC_VF_ATTR_SPOOFCHK, &data); 2085 if (!ret) 2086 ionic->vfs[vf].spoofchk = data; 2087 } 2088 2089 up_write(&ionic->vf_op_lock); 2090 return ret; 2091 } 2092 2093 static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set) 2094 { 2095 struct ionic_lif *lif = netdev_priv(netdev); 2096 struct ionic *ionic = lif->ionic; 2097 u8 data = set; /* convert to u8 for config */ 2098 int ret; 2099 2100 if (!netif_device_present(netdev)) 2101 return -EBUSY; 2102 2103 down_write(&ionic->vf_op_lock); 2104 2105 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2106 ret = -EINVAL; 2107 } else { 2108 ret = ionic_set_vf_config(ionic, vf, 2109 IONIC_VF_ATTR_TRUST, &data); 2110 if (!ret) 2111 ionic->vfs[vf].trusted = data; 2112 } 2113 2114 up_write(&ionic->vf_op_lock); 2115 return ret; 2116 } 2117 2118 static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set) 2119 { 2120 struct ionic_lif *lif = netdev_priv(netdev); 2121 struct ionic *ionic = lif->ionic; 2122 u8 data; 2123 int ret; 2124 2125 switch (set) { 2126 case IFLA_VF_LINK_STATE_ENABLE: 2127 data = IONIC_VF_LINK_STATUS_UP; 2128 break; 2129 case IFLA_VF_LINK_STATE_DISABLE: 2130 data = IONIC_VF_LINK_STATUS_DOWN; 2131 break; 2132 case IFLA_VF_LINK_STATE_AUTO: 2133 data = IONIC_VF_LINK_STATUS_AUTO; 2134 break; 2135 default: 2136 return -EINVAL; 2137 } 2138 2139 if (!netif_device_present(netdev)) 2140 return -EBUSY; 2141 2142 down_write(&ionic->vf_op_lock); 2143 2144 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2145 ret = -EINVAL; 2146 } else { 2147 ret = ionic_set_vf_config(ionic, vf, 2148 IONIC_VF_ATTR_LINKSTATE, &data); 2149 if (!ret) 2150 ionic->vfs[vf].linkstate = set; 2151 } 2152 2153 up_write(&ionic->vf_op_lock); 2154 return ret; 2155 } 2156 2157 static const struct net_device_ops ionic_netdev_ops = { 2158 .ndo_open = ionic_open, 2159 .ndo_stop = ionic_stop, 2160 .ndo_start_xmit = ionic_start_xmit, 2161 .ndo_get_stats64 = ionic_get_stats64, 2162 .ndo_set_rx_mode = ionic_ndo_set_rx_mode, 2163 .ndo_set_features = ionic_set_features, 2164 .ndo_set_mac_address = ionic_set_mac_address, 2165 .ndo_validate_addr = eth_validate_addr, 2166 .ndo_tx_timeout = ionic_tx_timeout, 2167 .ndo_change_mtu = ionic_change_mtu, 2168 .ndo_vlan_rx_add_vid = ionic_vlan_rx_add_vid, 2169 .ndo_vlan_rx_kill_vid = ionic_vlan_rx_kill_vid, 2170 .ndo_set_vf_vlan = ionic_set_vf_vlan, 2171 .ndo_set_vf_trust = ionic_set_vf_trust, 2172 .ndo_set_vf_mac = ionic_set_vf_mac, 2173 .ndo_set_vf_rate = ionic_set_vf_rate, 2174 .ndo_set_vf_spoofchk = ionic_set_vf_spoofchk, 2175 .ndo_get_vf_config = ionic_get_vf_config, 2176 .ndo_set_vf_link_state = ionic_set_vf_link_state, 2177 .ndo_get_vf_stats = ionic_get_vf_stats, 2178 }; 2179 2180 static void ionic_swap_queues(struct ionic_qcq *a, struct ionic_qcq *b) 2181 { 2182 /* only swapping the queues, not the napi, flags, or other stuff */ 2183 swap(a->q.num_descs, b->q.num_descs); 2184 swap(a->q.base, b->q.base); 2185 swap(a->q.base_pa, b->q.base_pa); 2186 swap(a->q.info, b->q.info); 2187 swap(a->q_base, b->q_base); 2188 swap(a->q_base_pa, b->q_base_pa); 2189 swap(a->q_size, b->q_size); 2190 2191 swap(a->q.sg_base, b->q.sg_base); 2192 swap(a->q.sg_base_pa, b->q.sg_base_pa); 2193 swap(a->sg_base, b->sg_base); 2194 swap(a->sg_base_pa, b->sg_base_pa); 2195 swap(a->sg_size, b->sg_size); 2196 2197 swap(a->cq.num_descs, b->cq.num_descs); 2198 swap(a->cq.base, b->cq.base); 2199 swap(a->cq.base_pa, b->cq.base_pa); 2200 swap(a->cq.info, b->cq.info); 2201 swap(a->cq_base, b->cq_base); 2202 swap(a->cq_base_pa, b->cq_base_pa); 2203 swap(a->cq_size, b->cq_size); 2204 } 2205 2206 int ionic_reconfigure_queues(struct ionic_lif *lif, 2207 struct ionic_queue_params *qparam) 2208 { 2209 struct ionic_qcq **tx_qcqs = NULL; 2210 struct ionic_qcq **rx_qcqs = NULL; 2211 unsigned int sg_desc_sz; 2212 unsigned int flags; 2213 int err = -ENOMEM; 2214 unsigned int i; 2215 2216 /* allocate temporary qcq arrays to hold new queue structs */ 2217 if (qparam->nxqs != lif->nxqs || qparam->ntxq_descs != lif->ntxq_descs) { 2218 tx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->ntxqs_per_lif, 2219 sizeof(struct ionic_qcq *), GFP_KERNEL); 2220 if (!tx_qcqs) 2221 goto err_out; 2222 } 2223 if (qparam->nxqs != lif->nxqs || qparam->nrxq_descs != lif->nrxq_descs) { 2224 rx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->nrxqs_per_lif, 2225 sizeof(struct ionic_qcq *), GFP_KERNEL); 2226 if (!rx_qcqs) 2227 goto err_out; 2228 } 2229 2230 /* allocate new desc_info and rings, but leave the interrupt setup 2231 * until later so as to not mess with the still-running queues 2232 */ 2233 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 2234 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 2235 sizeof(struct ionic_txq_sg_desc_v1)) 2236 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 2237 else 2238 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 2239 2240 if (tx_qcqs) { 2241 for (i = 0; i < qparam->nxqs; i++) { 2242 flags = lif->txqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2243 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 2244 qparam->ntxq_descs, 2245 sizeof(struct ionic_txq_desc), 2246 sizeof(struct ionic_txq_comp), 2247 sg_desc_sz, 2248 lif->kern_pid, &tx_qcqs[i]); 2249 if (err) 2250 goto err_out; 2251 } 2252 } 2253 2254 if (rx_qcqs) { 2255 for (i = 0; i < qparam->nxqs; i++) { 2256 flags = lif->rxqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2257 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 2258 qparam->nrxq_descs, 2259 sizeof(struct ionic_rxq_desc), 2260 sizeof(struct ionic_rxq_comp), 2261 sizeof(struct ionic_rxq_sg_desc), 2262 lif->kern_pid, &rx_qcqs[i]); 2263 if (err) 2264 goto err_out; 2265 } 2266 } 2267 2268 /* stop and clean the queues */ 2269 ionic_stop_queues_reconfig(lif); 2270 2271 if (qparam->nxqs != lif->nxqs) { 2272 err = netif_set_real_num_tx_queues(lif->netdev, qparam->nxqs); 2273 if (err) 2274 goto err_out_reinit_unlock; 2275 err = netif_set_real_num_rx_queues(lif->netdev, qparam->nxqs); 2276 if (err) { 2277 netif_set_real_num_tx_queues(lif->netdev, lif->nxqs); 2278 goto err_out_reinit_unlock; 2279 } 2280 } 2281 2282 /* swap new desc_info and rings, keeping existing interrupt config */ 2283 if (tx_qcqs) { 2284 lif->ntxq_descs = qparam->ntxq_descs; 2285 for (i = 0; i < qparam->nxqs; i++) 2286 ionic_swap_queues(lif->txqcqs[i], tx_qcqs[i]); 2287 } 2288 2289 if (rx_qcqs) { 2290 lif->nrxq_descs = qparam->nrxq_descs; 2291 for (i = 0; i < qparam->nxqs; i++) 2292 ionic_swap_queues(lif->rxqcqs[i], rx_qcqs[i]); 2293 } 2294 2295 /* if we need to change the interrupt layout, this is the time */ 2296 if (qparam->intr_split != test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) || 2297 qparam->nxqs != lif->nxqs) { 2298 if (qparam->intr_split) { 2299 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 2300 } else { 2301 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 2302 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 2303 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 2304 } 2305 2306 /* clear existing interrupt assignments */ 2307 for (i = 0; i < lif->ionic->ntxqs_per_lif; i++) { 2308 ionic_qcq_intr_free(lif, lif->txqcqs[i]); 2309 ionic_qcq_intr_free(lif, lif->rxqcqs[i]); 2310 } 2311 2312 /* re-assign the interrupts */ 2313 for (i = 0; i < qparam->nxqs; i++) { 2314 lif->rxqcqs[i]->flags |= IONIC_QCQ_F_INTR; 2315 err = ionic_alloc_qcq_interrupt(lif, lif->rxqcqs[i]); 2316 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2317 lif->rxqcqs[i]->intr.index, 2318 lif->rx_coalesce_hw); 2319 2320 if (qparam->intr_split) { 2321 lif->txqcqs[i]->flags |= IONIC_QCQ_F_INTR; 2322 err = ionic_alloc_qcq_interrupt(lif, lif->txqcqs[i]); 2323 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2324 lif->txqcqs[i]->intr.index, 2325 lif->tx_coalesce_hw); 2326 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 2327 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 2328 } else { 2329 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2330 ionic_link_qcq_interrupts(lif->rxqcqs[i], lif->txqcqs[i]); 2331 } 2332 } 2333 } 2334 2335 /* now we can rework the debugfs mappings */ 2336 if (tx_qcqs) { 2337 for (i = 0; i < qparam->nxqs; i++) { 2338 ionic_debugfs_del_qcq(lif->txqcqs[i]); 2339 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 2340 } 2341 } 2342 2343 if (rx_qcqs) { 2344 for (i = 0; i < qparam->nxqs; i++) { 2345 ionic_debugfs_del_qcq(lif->rxqcqs[i]); 2346 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 2347 } 2348 } 2349 2350 swap(lif->nxqs, qparam->nxqs); 2351 2352 err_out_reinit_unlock: 2353 /* re-init the queues, but don't loose an error code */ 2354 if (err) 2355 ionic_start_queues_reconfig(lif); 2356 else 2357 err = ionic_start_queues_reconfig(lif); 2358 2359 err_out: 2360 /* free old allocs without cleaning intr */ 2361 for (i = 0; i < qparam->nxqs; i++) { 2362 if (tx_qcqs && tx_qcqs[i]) { 2363 tx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2364 ionic_qcq_free(lif, tx_qcqs[i]); 2365 devm_kfree(lif->ionic->dev, tx_qcqs[i]); 2366 tx_qcqs[i] = NULL; 2367 } 2368 if (rx_qcqs && rx_qcqs[i]) { 2369 rx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2370 ionic_qcq_free(lif, rx_qcqs[i]); 2371 devm_kfree(lif->ionic->dev, rx_qcqs[i]); 2372 rx_qcqs[i] = NULL; 2373 } 2374 } 2375 2376 /* free q array */ 2377 if (rx_qcqs) { 2378 devm_kfree(lif->ionic->dev, rx_qcqs); 2379 rx_qcqs = NULL; 2380 } 2381 if (tx_qcqs) { 2382 devm_kfree(lif->ionic->dev, tx_qcqs); 2383 tx_qcqs = NULL; 2384 } 2385 2386 /* clean the unused dma and info allocations when new set is smaller 2387 * than the full array, but leave the qcq shells in place 2388 */ 2389 for (i = lif->nxqs; i < lif->ionic->ntxqs_per_lif; i++) { 2390 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2391 ionic_qcq_free(lif, lif->txqcqs[i]); 2392 2393 lif->rxqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2394 ionic_qcq_free(lif, lif->rxqcqs[i]); 2395 } 2396 2397 return err; 2398 } 2399 2400 int ionic_lif_alloc(struct ionic *ionic) 2401 { 2402 struct device *dev = ionic->dev; 2403 union ionic_lif_identity *lid; 2404 struct net_device *netdev; 2405 struct ionic_lif *lif; 2406 int tbl_sz; 2407 int err; 2408 2409 lid = kzalloc(sizeof(*lid), GFP_KERNEL); 2410 if (!lid) 2411 return -ENOMEM; 2412 2413 netdev = alloc_etherdev_mqs(sizeof(*lif), 2414 ionic->ntxqs_per_lif, ionic->ntxqs_per_lif); 2415 if (!netdev) { 2416 dev_err(dev, "Cannot allocate netdev, aborting\n"); 2417 err = -ENOMEM; 2418 goto err_out_free_lid; 2419 } 2420 2421 SET_NETDEV_DEV(netdev, dev); 2422 2423 lif = netdev_priv(netdev); 2424 lif->netdev = netdev; 2425 ionic->lif = lif; 2426 netdev->netdev_ops = &ionic_netdev_ops; 2427 ionic_ethtool_set_ops(netdev); 2428 2429 netdev->watchdog_timeo = 2 * HZ; 2430 netif_carrier_off(netdev); 2431 2432 lif->identity = lid; 2433 lif->lif_type = IONIC_LIF_TYPE_CLASSIC; 2434 err = ionic_lif_identify(ionic, lif->lif_type, lif->identity); 2435 if (err) { 2436 dev_err(ionic->dev, "Cannot identify type %d: %d\n", 2437 lif->lif_type, err); 2438 goto err_out_free_netdev; 2439 } 2440 lif->netdev->min_mtu = max_t(unsigned int, ETH_MIN_MTU, 2441 le32_to_cpu(lif->identity->eth.min_frame_size)); 2442 lif->netdev->max_mtu = 2443 le32_to_cpu(lif->identity->eth.max_frame_size) - ETH_HLEN - VLAN_HLEN; 2444 2445 lif->neqs = ionic->neqs_per_lif; 2446 lif->nxqs = ionic->ntxqs_per_lif; 2447 2448 lif->ionic = ionic; 2449 lif->index = 0; 2450 lif->ntxq_descs = IONIC_DEF_TXRX_DESC; 2451 lif->nrxq_descs = IONIC_DEF_TXRX_DESC; 2452 lif->tx_budget = IONIC_TX_BUDGET_DEFAULT; 2453 2454 /* Convert the default coalesce value to actual hw resolution */ 2455 lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT; 2456 lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic, 2457 lif->rx_coalesce_usecs); 2458 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 2459 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 2460 set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 2461 set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 2462 2463 snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index); 2464 2465 spin_lock_init(&lif->adminq_lock); 2466 2467 spin_lock_init(&lif->deferred.lock); 2468 INIT_LIST_HEAD(&lif->deferred.list); 2469 INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work); 2470 2471 /* allocate lif info */ 2472 lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE); 2473 lif->info = dma_alloc_coherent(dev, lif->info_sz, 2474 &lif->info_pa, GFP_KERNEL); 2475 if (!lif->info) { 2476 dev_err(dev, "Failed to allocate lif info, aborting\n"); 2477 err = -ENOMEM; 2478 goto err_out_free_netdev; 2479 } 2480 2481 ionic_debugfs_add_lif(lif); 2482 2483 /* allocate control queues and txrx queue arrays */ 2484 ionic_lif_queue_identify(lif); 2485 err = ionic_qcqs_alloc(lif); 2486 if (err) 2487 goto err_out_free_lif_info; 2488 2489 /* allocate rss indirection table */ 2490 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 2491 lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz; 2492 lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz, 2493 &lif->rss_ind_tbl_pa, 2494 GFP_KERNEL); 2495 2496 if (!lif->rss_ind_tbl) { 2497 err = -ENOMEM; 2498 dev_err(dev, "Failed to allocate rss indirection table, aborting\n"); 2499 goto err_out_free_qcqs; 2500 } 2501 netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE); 2502 2503 return 0; 2504 2505 err_out_free_qcqs: 2506 ionic_qcqs_free(lif); 2507 err_out_free_lif_info: 2508 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 2509 lif->info = NULL; 2510 lif->info_pa = 0; 2511 err_out_free_netdev: 2512 free_netdev(lif->netdev); 2513 lif = NULL; 2514 err_out_free_lid: 2515 kfree(lid); 2516 2517 return err; 2518 } 2519 2520 static void ionic_lif_reset(struct ionic_lif *lif) 2521 { 2522 struct ionic_dev *idev = &lif->ionic->idev; 2523 2524 mutex_lock(&lif->ionic->dev_cmd_lock); 2525 ionic_dev_cmd_lif_reset(idev, lif->index); 2526 ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2527 mutex_unlock(&lif->ionic->dev_cmd_lock); 2528 } 2529 2530 static void ionic_lif_handle_fw_down(struct ionic_lif *lif) 2531 { 2532 struct ionic *ionic = lif->ionic; 2533 2534 if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2535 return; 2536 2537 dev_info(ionic->dev, "FW Down: Stopping LIFs\n"); 2538 2539 netif_device_detach(lif->netdev); 2540 2541 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 2542 dev_info(ionic->dev, "Surprise FW stop, stopping queues\n"); 2543 mutex_lock(&lif->queue_lock); 2544 ionic_stop_queues(lif); 2545 mutex_unlock(&lif->queue_lock); 2546 } 2547 2548 if (netif_running(lif->netdev)) { 2549 ionic_txrx_deinit(lif); 2550 ionic_txrx_free(lif); 2551 } 2552 ionic_lif_deinit(lif); 2553 ionic_reset(ionic); 2554 ionic_qcqs_free(lif); 2555 2556 dev_info(ionic->dev, "FW Down: LIFs stopped\n"); 2557 } 2558 2559 static void ionic_lif_handle_fw_up(struct ionic_lif *lif) 2560 { 2561 struct ionic *ionic = lif->ionic; 2562 int err; 2563 2564 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2565 return; 2566 2567 dev_info(ionic->dev, "FW Up: restarting LIFs\n"); 2568 2569 ionic_init_devinfo(ionic); 2570 err = ionic_identify(ionic); 2571 if (err) 2572 goto err_out; 2573 err = ionic_port_identify(ionic); 2574 if (err) 2575 goto err_out; 2576 err = ionic_port_init(ionic); 2577 if (err) 2578 goto err_out; 2579 err = ionic_qcqs_alloc(lif); 2580 if (err) 2581 goto err_out; 2582 2583 err = ionic_lif_init(lif); 2584 if (err) 2585 goto err_qcqs_free; 2586 2587 if (lif->registered) 2588 ionic_lif_set_netdev_info(lif); 2589 2590 ionic_rx_filter_replay(lif); 2591 2592 if (netif_running(lif->netdev)) { 2593 err = ionic_txrx_alloc(lif); 2594 if (err) 2595 goto err_lifs_deinit; 2596 2597 err = ionic_txrx_init(lif); 2598 if (err) 2599 goto err_txrx_free; 2600 } 2601 2602 clear_bit(IONIC_LIF_F_FW_RESET, lif->state); 2603 ionic_link_status_check_request(lif, true); 2604 netif_device_attach(lif->netdev); 2605 dev_info(ionic->dev, "FW Up: LIFs restarted\n"); 2606 2607 return; 2608 2609 err_txrx_free: 2610 ionic_txrx_free(lif); 2611 err_lifs_deinit: 2612 ionic_lif_deinit(lif); 2613 err_qcqs_free: 2614 ionic_qcqs_free(lif); 2615 err_out: 2616 dev_err(ionic->dev, "FW Up: LIFs restart failed - err %d\n", err); 2617 } 2618 2619 void ionic_lif_free(struct ionic_lif *lif) 2620 { 2621 struct device *dev = lif->ionic->dev; 2622 2623 /* free rss indirection table */ 2624 dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl, 2625 lif->rss_ind_tbl_pa); 2626 lif->rss_ind_tbl = NULL; 2627 lif->rss_ind_tbl_pa = 0; 2628 2629 /* free queues */ 2630 ionic_qcqs_free(lif); 2631 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2632 ionic_lif_reset(lif); 2633 2634 /* free lif info */ 2635 kfree(lif->identity); 2636 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 2637 lif->info = NULL; 2638 lif->info_pa = 0; 2639 2640 /* unmap doorbell page */ 2641 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 2642 lif->kern_dbpage = NULL; 2643 kfree(lif->dbid_inuse); 2644 lif->dbid_inuse = NULL; 2645 2646 /* free netdev & lif */ 2647 ionic_debugfs_del_lif(lif); 2648 free_netdev(lif->netdev); 2649 } 2650 2651 void ionic_lif_deinit(struct ionic_lif *lif) 2652 { 2653 if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state)) 2654 return; 2655 2656 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 2657 cancel_work_sync(&lif->deferred.work); 2658 cancel_work_sync(&lif->tx_timeout_work); 2659 ionic_rx_filters_deinit(lif); 2660 if (lif->netdev->features & NETIF_F_RXHASH) 2661 ionic_lif_rss_deinit(lif); 2662 } 2663 2664 napi_disable(&lif->adminqcq->napi); 2665 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 2666 ionic_lif_qcq_deinit(lif, lif->adminqcq); 2667 2668 mutex_destroy(&lif->queue_lock); 2669 ionic_lif_reset(lif); 2670 } 2671 2672 static int ionic_lif_adminq_init(struct ionic_lif *lif) 2673 { 2674 struct device *dev = lif->ionic->dev; 2675 struct ionic_q_init_comp comp; 2676 struct ionic_dev *idev; 2677 struct ionic_qcq *qcq; 2678 struct ionic_queue *q; 2679 int err; 2680 2681 idev = &lif->ionic->idev; 2682 qcq = lif->adminqcq; 2683 q = &qcq->q; 2684 2685 mutex_lock(&lif->ionic->dev_cmd_lock); 2686 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index); 2687 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2688 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 2689 mutex_unlock(&lif->ionic->dev_cmd_lock); 2690 if (err) { 2691 netdev_err(lif->netdev, "adminq init failed %d\n", err); 2692 return err; 2693 } 2694 2695 q->hw_type = comp.hw_type; 2696 q->hw_index = le32_to_cpu(comp.hw_index); 2697 q->dbval = IONIC_DBELL_QID(q->hw_index); 2698 2699 dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type); 2700 dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index); 2701 2702 netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi, 2703 NAPI_POLL_WEIGHT); 2704 2705 napi_enable(&qcq->napi); 2706 2707 if (qcq->flags & IONIC_QCQ_F_INTR) 2708 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 2709 IONIC_INTR_MASK_CLEAR); 2710 2711 qcq->flags |= IONIC_QCQ_F_INITED; 2712 2713 return 0; 2714 } 2715 2716 static int ionic_lif_notifyq_init(struct ionic_lif *lif) 2717 { 2718 struct ionic_qcq *qcq = lif->notifyqcq; 2719 struct device *dev = lif->ionic->dev; 2720 struct ionic_queue *q = &qcq->q; 2721 int err; 2722 2723 struct ionic_admin_ctx ctx = { 2724 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 2725 .cmd.q_init = { 2726 .opcode = IONIC_CMD_Q_INIT, 2727 .lif_index = cpu_to_le16(lif->index), 2728 .type = q->type, 2729 .ver = lif->qtype_info[q->type].version, 2730 .index = cpu_to_le32(q->index), 2731 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 2732 IONIC_QINIT_F_ENA), 2733 .intr_index = cpu_to_le16(lif->adminqcq->intr.index), 2734 .pid = cpu_to_le16(q->pid), 2735 .ring_size = ilog2(q->num_descs), 2736 .ring_base = cpu_to_le64(q->base_pa), 2737 } 2738 }; 2739 2740 dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid); 2741 dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index); 2742 dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 2743 dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 2744 2745 err = ionic_adminq_post_wait(lif, &ctx); 2746 if (err) 2747 return err; 2748 2749 lif->last_eid = 0; 2750 q->hw_type = ctx.comp.q_init.hw_type; 2751 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 2752 q->dbval = IONIC_DBELL_QID(q->hw_index); 2753 2754 dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type); 2755 dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index); 2756 2757 /* preset the callback info */ 2758 q->info[0].cb_arg = lif; 2759 2760 qcq->flags |= IONIC_QCQ_F_INITED; 2761 2762 return 0; 2763 } 2764 2765 static int ionic_station_set(struct ionic_lif *lif) 2766 { 2767 struct net_device *netdev = lif->netdev; 2768 struct ionic_admin_ctx ctx = { 2769 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 2770 .cmd.lif_getattr = { 2771 .opcode = IONIC_CMD_LIF_GETATTR, 2772 .index = cpu_to_le16(lif->index), 2773 .attr = IONIC_LIF_ATTR_MAC, 2774 }, 2775 }; 2776 struct sockaddr addr; 2777 int err; 2778 2779 err = ionic_adminq_post_wait(lif, &ctx); 2780 if (err) 2781 return err; 2782 netdev_dbg(lif->netdev, "found initial MAC addr %pM\n", 2783 ctx.comp.lif_getattr.mac); 2784 if (is_zero_ether_addr(ctx.comp.lif_getattr.mac)) 2785 return 0; 2786 2787 if (!is_zero_ether_addr(netdev->dev_addr)) { 2788 /* If the netdev mac is non-zero and doesn't match the default 2789 * device address, it was set by something earlier and we're 2790 * likely here again after a fw-upgrade reset. We need to be 2791 * sure the netdev mac is in our filter list. 2792 */ 2793 if (!ether_addr_equal(ctx.comp.lif_getattr.mac, 2794 netdev->dev_addr)) 2795 ionic_lif_addr(lif, netdev->dev_addr, ADD_ADDR, CAN_SLEEP); 2796 } else { 2797 /* Update the netdev mac with the device's mac */ 2798 memcpy(addr.sa_data, ctx.comp.lif_getattr.mac, netdev->addr_len); 2799 addr.sa_family = AF_INET; 2800 err = eth_prepare_mac_addr_change(netdev, &addr); 2801 if (err) { 2802 netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n", 2803 addr.sa_data, err); 2804 return 0; 2805 } 2806 2807 eth_commit_mac_addr_change(netdev, &addr); 2808 } 2809 2810 netdev_dbg(lif->netdev, "adding station MAC addr %pM\n", 2811 netdev->dev_addr); 2812 ionic_lif_addr(lif, netdev->dev_addr, ADD_ADDR, CAN_SLEEP); 2813 2814 return 0; 2815 } 2816 2817 int ionic_lif_init(struct ionic_lif *lif) 2818 { 2819 struct ionic_dev *idev = &lif->ionic->idev; 2820 struct device *dev = lif->ionic->dev; 2821 struct ionic_lif_init_comp comp; 2822 int dbpage_num; 2823 int err; 2824 2825 mutex_lock(&lif->ionic->dev_cmd_lock); 2826 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa); 2827 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2828 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 2829 mutex_unlock(&lif->ionic->dev_cmd_lock); 2830 if (err) 2831 return err; 2832 2833 lif->hw_index = le16_to_cpu(comp.hw_index); 2834 mutex_init(&lif->queue_lock); 2835 2836 /* now that we have the hw_index we can figure out our doorbell page */ 2837 lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif); 2838 if (!lif->dbid_count) { 2839 dev_err(dev, "No doorbell pages, aborting\n"); 2840 return -EINVAL; 2841 } 2842 2843 lif->dbid_inuse = bitmap_alloc(lif->dbid_count, GFP_KERNEL); 2844 if (!lif->dbid_inuse) { 2845 dev_err(dev, "Failed alloc doorbell id bitmap, aborting\n"); 2846 return -ENOMEM; 2847 } 2848 2849 /* first doorbell id reserved for kernel (dbid aka pid == zero) */ 2850 set_bit(0, lif->dbid_inuse); 2851 lif->kern_pid = 0; 2852 2853 dbpage_num = ionic_db_page_num(lif, lif->kern_pid); 2854 lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num); 2855 if (!lif->kern_dbpage) { 2856 dev_err(dev, "Cannot map dbpage, aborting\n"); 2857 err = -ENOMEM; 2858 goto err_out_free_dbid; 2859 } 2860 2861 err = ionic_lif_adminq_init(lif); 2862 if (err) 2863 goto err_out_adminq_deinit; 2864 2865 if (lif->ionic->nnqs_per_lif) { 2866 err = ionic_lif_notifyq_init(lif); 2867 if (err) 2868 goto err_out_notifyq_deinit; 2869 } 2870 2871 err = ionic_init_nic_features(lif); 2872 if (err) 2873 goto err_out_notifyq_deinit; 2874 2875 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 2876 err = ionic_rx_filters_init(lif); 2877 if (err) 2878 goto err_out_notifyq_deinit; 2879 } 2880 2881 err = ionic_station_set(lif); 2882 if (err) 2883 goto err_out_notifyq_deinit; 2884 2885 lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT; 2886 2887 set_bit(IONIC_LIF_F_INITED, lif->state); 2888 2889 INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work); 2890 2891 return 0; 2892 2893 err_out_notifyq_deinit: 2894 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 2895 err_out_adminq_deinit: 2896 ionic_lif_qcq_deinit(lif, lif->adminqcq); 2897 ionic_lif_reset(lif); 2898 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 2899 lif->kern_dbpage = NULL; 2900 err_out_free_dbid: 2901 kfree(lif->dbid_inuse); 2902 lif->dbid_inuse = NULL; 2903 2904 return err; 2905 } 2906 2907 static void ionic_lif_notify_work(struct work_struct *ws) 2908 { 2909 } 2910 2911 static void ionic_lif_set_netdev_info(struct ionic_lif *lif) 2912 { 2913 struct ionic_admin_ctx ctx = { 2914 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 2915 .cmd.lif_setattr = { 2916 .opcode = IONIC_CMD_LIF_SETATTR, 2917 .index = cpu_to_le16(lif->index), 2918 .attr = IONIC_LIF_ATTR_NAME, 2919 }, 2920 }; 2921 2922 strlcpy(ctx.cmd.lif_setattr.name, lif->netdev->name, 2923 sizeof(ctx.cmd.lif_setattr.name)); 2924 2925 ionic_adminq_post_wait(lif, &ctx); 2926 } 2927 2928 static struct ionic_lif *ionic_netdev_lif(struct net_device *netdev) 2929 { 2930 if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit) 2931 return NULL; 2932 2933 return netdev_priv(netdev); 2934 } 2935 2936 static int ionic_lif_notify(struct notifier_block *nb, 2937 unsigned long event, void *info) 2938 { 2939 struct net_device *ndev = netdev_notifier_info_to_dev(info); 2940 struct ionic *ionic = container_of(nb, struct ionic, nb); 2941 struct ionic_lif *lif = ionic_netdev_lif(ndev); 2942 2943 if (!lif || lif->ionic != ionic) 2944 return NOTIFY_DONE; 2945 2946 switch (event) { 2947 case NETDEV_CHANGENAME: 2948 ionic_lif_set_netdev_info(lif); 2949 break; 2950 } 2951 2952 return NOTIFY_DONE; 2953 } 2954 2955 int ionic_lif_register(struct ionic_lif *lif) 2956 { 2957 int err; 2958 2959 INIT_WORK(&lif->ionic->nb_work, ionic_lif_notify_work); 2960 2961 lif->ionic->nb.notifier_call = ionic_lif_notify; 2962 2963 err = register_netdevice_notifier(&lif->ionic->nb); 2964 if (err) 2965 lif->ionic->nb.notifier_call = NULL; 2966 2967 /* only register LIF0 for now */ 2968 err = register_netdev(lif->netdev); 2969 if (err) { 2970 dev_err(lif->ionic->dev, "Cannot register net device, aborting\n"); 2971 return err; 2972 } 2973 2974 ionic_link_status_check_request(lif, true); 2975 lif->registered = true; 2976 ionic_lif_set_netdev_info(lif); 2977 2978 return 0; 2979 } 2980 2981 void ionic_lif_unregister(struct ionic_lif *lif) 2982 { 2983 if (lif->ionic->nb.notifier_call) { 2984 unregister_netdevice_notifier(&lif->ionic->nb); 2985 cancel_work_sync(&lif->ionic->nb_work); 2986 lif->ionic->nb.notifier_call = NULL; 2987 } 2988 2989 if (lif->netdev->reg_state == NETREG_REGISTERED) 2990 unregister_netdev(lif->netdev); 2991 lif->registered = false; 2992 } 2993 2994 static void ionic_lif_queue_identify(struct ionic_lif *lif) 2995 { 2996 union ionic_q_identity __iomem *q_ident; 2997 struct ionic *ionic = lif->ionic; 2998 struct ionic_dev *idev; 2999 int qtype; 3000 int err; 3001 3002 idev = &lif->ionic->idev; 3003 q_ident = (union ionic_q_identity __iomem *)&idev->dev_cmd_regs->data; 3004 3005 for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) { 3006 struct ionic_qtype_info *qti = &lif->qtype_info[qtype]; 3007 3008 /* filter out the ones we know about */ 3009 switch (qtype) { 3010 case IONIC_QTYPE_ADMINQ: 3011 case IONIC_QTYPE_NOTIFYQ: 3012 case IONIC_QTYPE_RXQ: 3013 case IONIC_QTYPE_TXQ: 3014 break; 3015 default: 3016 continue; 3017 } 3018 3019 memset(qti, 0, sizeof(*qti)); 3020 3021 mutex_lock(&ionic->dev_cmd_lock); 3022 ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype, 3023 ionic_qtype_versions[qtype]); 3024 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3025 if (!err) { 3026 qti->version = readb(&q_ident->version); 3027 qti->supported = readb(&q_ident->supported); 3028 qti->features = readq(&q_ident->features); 3029 qti->desc_sz = readw(&q_ident->desc_sz); 3030 qti->comp_sz = readw(&q_ident->comp_sz); 3031 qti->sg_desc_sz = readw(&q_ident->sg_desc_sz); 3032 qti->max_sg_elems = readw(&q_ident->max_sg_elems); 3033 qti->sg_desc_stride = readw(&q_ident->sg_desc_stride); 3034 } 3035 mutex_unlock(&ionic->dev_cmd_lock); 3036 3037 if (err == -EINVAL) { 3038 dev_err(ionic->dev, "qtype %d not supported\n", qtype); 3039 continue; 3040 } else if (err == -EIO) { 3041 dev_err(ionic->dev, "q_ident failed, not supported on older FW\n"); 3042 return; 3043 } else if (err) { 3044 dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n", 3045 qtype, err); 3046 return; 3047 } 3048 3049 dev_dbg(ionic->dev, " qtype[%d].version = %d\n", 3050 qtype, qti->version); 3051 dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n", 3052 qtype, qti->supported); 3053 dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n", 3054 qtype, qti->features); 3055 dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n", 3056 qtype, qti->desc_sz); 3057 dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n", 3058 qtype, qti->comp_sz); 3059 dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n", 3060 qtype, qti->sg_desc_sz); 3061 dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n", 3062 qtype, qti->max_sg_elems); 3063 dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n", 3064 qtype, qti->sg_desc_stride); 3065 } 3066 } 3067 3068 int ionic_lif_identify(struct ionic *ionic, u8 lif_type, 3069 union ionic_lif_identity *lid) 3070 { 3071 struct ionic_dev *idev = &ionic->idev; 3072 size_t sz; 3073 int err; 3074 3075 sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data)); 3076 3077 mutex_lock(&ionic->dev_cmd_lock); 3078 ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1); 3079 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3080 memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz); 3081 mutex_unlock(&ionic->dev_cmd_lock); 3082 if (err) 3083 return (err); 3084 3085 dev_dbg(ionic->dev, "capabilities 0x%llx\n", 3086 le64_to_cpu(lid->capabilities)); 3087 3088 dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n", 3089 le32_to_cpu(lid->eth.max_ucast_filters)); 3090 dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n", 3091 le32_to_cpu(lid->eth.max_mcast_filters)); 3092 dev_dbg(ionic->dev, "eth.features 0x%llx\n", 3093 le64_to_cpu(lid->eth.config.features)); 3094 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n", 3095 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ])); 3096 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n", 3097 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ])); 3098 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n", 3099 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ])); 3100 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n", 3101 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ])); 3102 dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name); 3103 dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac); 3104 dev_dbg(ionic->dev, "eth.config.mtu %d\n", 3105 le32_to_cpu(lid->eth.config.mtu)); 3106 3107 return 0; 3108 } 3109 3110 int ionic_lif_size(struct ionic *ionic) 3111 { 3112 struct ionic_identity *ident = &ionic->ident; 3113 unsigned int nintrs, dev_nintrs; 3114 union ionic_lif_config *lc; 3115 unsigned int ntxqs_per_lif; 3116 unsigned int nrxqs_per_lif; 3117 unsigned int neqs_per_lif; 3118 unsigned int nnqs_per_lif; 3119 unsigned int nxqs, neqs; 3120 unsigned int min_intrs; 3121 int err; 3122 3123 lc = &ident->lif.eth.config; 3124 dev_nintrs = le32_to_cpu(ident->dev.nintrs); 3125 neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count); 3126 nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]); 3127 ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]); 3128 nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]); 3129 3130 nxqs = min(ntxqs_per_lif, nrxqs_per_lif); 3131 nxqs = min(nxqs, num_online_cpus()); 3132 neqs = min(neqs_per_lif, num_online_cpus()); 3133 3134 try_again: 3135 /* interrupt usage: 3136 * 1 for master lif adminq/notifyq 3137 * 1 for each CPU for master lif TxRx queue pairs 3138 * whatever's left is for RDMA queues 3139 */ 3140 nintrs = 1 + nxqs + neqs; 3141 min_intrs = 2; /* adminq + 1 TxRx queue pair */ 3142 3143 if (nintrs > dev_nintrs) 3144 goto try_fewer; 3145 3146 err = ionic_bus_alloc_irq_vectors(ionic, nintrs); 3147 if (err < 0 && err != -ENOSPC) { 3148 dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err); 3149 return err; 3150 } 3151 if (err == -ENOSPC) 3152 goto try_fewer; 3153 3154 if (err != nintrs) { 3155 ionic_bus_free_irq_vectors(ionic); 3156 goto try_fewer; 3157 } 3158 3159 ionic->nnqs_per_lif = nnqs_per_lif; 3160 ionic->neqs_per_lif = neqs; 3161 ionic->ntxqs_per_lif = nxqs; 3162 ionic->nrxqs_per_lif = nxqs; 3163 ionic->nintrs = nintrs; 3164 3165 ionic_debugfs_add_sizes(ionic); 3166 3167 return 0; 3168 3169 try_fewer: 3170 if (nnqs_per_lif > 1) { 3171 nnqs_per_lif >>= 1; 3172 goto try_again; 3173 } 3174 if (neqs > 1) { 3175 neqs >>= 1; 3176 goto try_again; 3177 } 3178 if (nxqs > 1) { 3179 nxqs >>= 1; 3180 goto try_again; 3181 } 3182 dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs); 3183 return -ENOSPC; 3184 } 3185