1 /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */ 2 /* Copyright (c) 2017-2020 Pensando Systems, Inc. All rights reserved. */ 3 4 #ifndef _IONIC_IF_H_ 5 #define _IONIC_IF_H_ 6 7 #define IONIC_DEV_INFO_SIGNATURE 0x44455649 /* 'DEVI' */ 8 #define IONIC_DEV_INFO_VERSION 1 9 #define IONIC_IFNAMSIZ 16 10 11 /* 12 * enum ionic_cmd_opcode - Device commands 13 */ 14 enum ionic_cmd_opcode { 15 IONIC_CMD_NOP = 0, 16 17 /* Device commands */ 18 IONIC_CMD_IDENTIFY = 1, 19 IONIC_CMD_INIT = 2, 20 IONIC_CMD_RESET = 3, 21 IONIC_CMD_GETATTR = 4, 22 IONIC_CMD_SETATTR = 5, 23 24 /* Port commands */ 25 IONIC_CMD_PORT_IDENTIFY = 10, 26 IONIC_CMD_PORT_INIT = 11, 27 IONIC_CMD_PORT_RESET = 12, 28 IONIC_CMD_PORT_GETATTR = 13, 29 IONIC_CMD_PORT_SETATTR = 14, 30 31 /* LIF commands */ 32 IONIC_CMD_LIF_IDENTIFY = 20, 33 IONIC_CMD_LIF_INIT = 21, 34 IONIC_CMD_LIF_RESET = 22, 35 IONIC_CMD_LIF_GETATTR = 23, 36 IONIC_CMD_LIF_SETATTR = 24, 37 IONIC_CMD_LIF_SETPHC = 25, 38 39 IONIC_CMD_RX_MODE_SET = 30, 40 IONIC_CMD_RX_FILTER_ADD = 31, 41 IONIC_CMD_RX_FILTER_DEL = 32, 42 43 /* Queue commands */ 44 IONIC_CMD_Q_IDENTIFY = 39, 45 IONIC_CMD_Q_INIT = 40, 46 IONIC_CMD_Q_CONTROL = 41, 47 48 /* RDMA commands */ 49 IONIC_CMD_RDMA_RESET_LIF = 50, 50 IONIC_CMD_RDMA_CREATE_EQ = 51, 51 IONIC_CMD_RDMA_CREATE_CQ = 52, 52 IONIC_CMD_RDMA_CREATE_ADMINQ = 53, 53 54 /* SR/IOV commands */ 55 IONIC_CMD_VF_GETATTR = 60, 56 IONIC_CMD_VF_SETATTR = 61, 57 IONIC_CMD_VF_CTRL = 62, 58 59 /* QoS commands */ 60 IONIC_CMD_QOS_CLASS_IDENTIFY = 240, 61 IONIC_CMD_QOS_CLASS_INIT = 241, 62 IONIC_CMD_QOS_CLASS_RESET = 242, 63 IONIC_CMD_QOS_CLASS_UPDATE = 243, 64 IONIC_CMD_QOS_CLEAR_STATS = 244, 65 IONIC_CMD_QOS_RESET = 245, 66 67 /* Firmware commands */ 68 IONIC_CMD_FW_DOWNLOAD = 252, 69 IONIC_CMD_FW_CONTROL = 253, 70 IONIC_CMD_FW_DOWNLOAD_V1 = 254, 71 IONIC_CMD_FW_CONTROL_V1 = 255, 72 }; 73 74 /* 75 * enum ionic_status_code - Device command return codes 76 */ 77 enum ionic_status_code { 78 IONIC_RC_SUCCESS = 0, /* Success */ 79 IONIC_RC_EVERSION = 1, /* Incorrect version for request */ 80 IONIC_RC_EOPCODE = 2, /* Invalid cmd opcode */ 81 IONIC_RC_EIO = 3, /* I/O error */ 82 IONIC_RC_EPERM = 4, /* Permission denied */ 83 IONIC_RC_EQID = 5, /* Bad qid */ 84 IONIC_RC_EQTYPE = 6, /* Bad qtype */ 85 IONIC_RC_ENOENT = 7, /* No such element */ 86 IONIC_RC_EINTR = 8, /* operation interrupted */ 87 IONIC_RC_EAGAIN = 9, /* Try again */ 88 IONIC_RC_ENOMEM = 10, /* Out of memory */ 89 IONIC_RC_EFAULT = 11, /* Bad address */ 90 IONIC_RC_EBUSY = 12, /* Device or resource busy */ 91 IONIC_RC_EEXIST = 13, /* object already exists */ 92 IONIC_RC_EINVAL = 14, /* Invalid argument */ 93 IONIC_RC_ENOSPC = 15, /* No space left or alloc failure */ 94 IONIC_RC_ERANGE = 16, /* Parameter out of range */ 95 IONIC_RC_BAD_ADDR = 17, /* Descriptor contains a bad ptr */ 96 IONIC_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */ 97 IONIC_RC_ENOSUPP = 19, /* Operation not supported */ 98 IONIC_RC_ERROR = 29, /* Generic error */ 99 IONIC_RC_ERDMA = 30, /* Generic RDMA error */ 100 IONIC_RC_EVFID = 31, /* VF ID does not exist */ 101 IONIC_RC_EBAD_FW = 32, /* FW file is invalid or corrupted */ 102 }; 103 104 enum ionic_notifyq_opcode { 105 IONIC_EVENT_LINK_CHANGE = 1, 106 IONIC_EVENT_RESET = 2, 107 IONIC_EVENT_HEARTBEAT = 3, 108 IONIC_EVENT_LOG = 4, 109 IONIC_EVENT_XCVR = 5, 110 }; 111 112 /** 113 * struct ionic_admin_cmd - General admin command format 114 * @opcode: Opcode for the command 115 * @rsvd: reserved byte(s) 116 * @lif_index: LIF index 117 * @cmd_data: Opcode-specific command bytes 118 */ 119 struct ionic_admin_cmd { 120 u8 opcode; 121 u8 rsvd; 122 __le16 lif_index; 123 u8 cmd_data[60]; 124 }; 125 126 /** 127 * struct ionic_admin_comp - General admin command completion format 128 * @status: Status of the command (enum ionic_status_code) 129 * @rsvd: reserved byte(s) 130 * @comp_index: Index in the descriptor ring for which this is the completion 131 * @cmd_data: Command-specific bytes 132 * @color: Color bit (Always 0 for commands issued to the 133 * Device Cmd Registers) 134 */ 135 struct ionic_admin_comp { 136 u8 status; 137 u8 rsvd; 138 __le16 comp_index; 139 u8 cmd_data[11]; 140 u8 color; 141 #define IONIC_COMP_COLOR_MASK 0x80 142 }; 143 144 static inline u8 color_match(u8 color, u8 done_color) 145 { 146 return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color; 147 } 148 149 /** 150 * struct ionic_nop_cmd - NOP command 151 * @opcode: opcode 152 * @rsvd: reserved byte(s) 153 */ 154 struct ionic_nop_cmd { 155 u8 opcode; 156 u8 rsvd[63]; 157 }; 158 159 /** 160 * struct ionic_nop_comp - NOP command completion 161 * @status: Status of the command (enum ionic_status_code) 162 * @rsvd: reserved byte(s) 163 */ 164 struct ionic_nop_comp { 165 u8 status; 166 u8 rsvd[15]; 167 }; 168 169 /** 170 * struct ionic_dev_init_cmd - Device init command 171 * @opcode: opcode 172 * @type: Device type 173 * @rsvd: reserved byte(s) 174 */ 175 struct ionic_dev_init_cmd { 176 u8 opcode; 177 u8 type; 178 u8 rsvd[62]; 179 }; 180 181 /** 182 * struct ionic_dev_init_comp - Device init command completion 183 * @status: Status of the command (enum ionic_status_code) 184 * @rsvd: reserved byte(s) 185 */ 186 struct ionic_dev_init_comp { 187 u8 status; 188 u8 rsvd[15]; 189 }; 190 191 /** 192 * struct ionic_dev_reset_cmd - Device reset command 193 * @opcode: opcode 194 * @rsvd: reserved byte(s) 195 */ 196 struct ionic_dev_reset_cmd { 197 u8 opcode; 198 u8 rsvd[63]; 199 }; 200 201 /** 202 * struct ionic_dev_reset_comp - Reset command completion 203 * @status: Status of the command (enum ionic_status_code) 204 * @rsvd: reserved byte(s) 205 */ 206 struct ionic_dev_reset_comp { 207 u8 status; 208 u8 rsvd[15]; 209 }; 210 211 #define IONIC_IDENTITY_VERSION_1 1 212 #define IONIC_DEV_IDENTITY_VERSION_2 2 213 214 /** 215 * struct ionic_dev_identify_cmd - Driver/device identify command 216 * @opcode: opcode 217 * @ver: Highest version of identify supported by driver 218 * @rsvd: reserved byte(s) 219 */ 220 struct ionic_dev_identify_cmd { 221 u8 opcode; 222 u8 ver; 223 u8 rsvd[62]; 224 }; 225 226 /** 227 * struct ionic_dev_identify_comp - Driver/device identify command completion 228 * @status: Status of the command (enum ionic_status_code) 229 * @ver: Version of identify returned by device 230 * @rsvd: reserved byte(s) 231 */ 232 struct ionic_dev_identify_comp { 233 u8 status; 234 u8 ver; 235 u8 rsvd[14]; 236 }; 237 238 enum ionic_os_type { 239 IONIC_OS_TYPE_LINUX = 1, 240 IONIC_OS_TYPE_WIN = 2, 241 IONIC_OS_TYPE_DPDK = 3, 242 IONIC_OS_TYPE_FREEBSD = 4, 243 IONIC_OS_TYPE_IPXE = 5, 244 IONIC_OS_TYPE_ESXI = 6, 245 }; 246 247 /** 248 * union ionic_drv_identity - driver identity information 249 * @os_type: OS type (see enum ionic_os_type) 250 * @os_dist: OS distribution, numeric format 251 * @os_dist_str: OS distribution, string format 252 * @kernel_ver: Kernel version, numeric format 253 * @kernel_ver_str: Kernel version, string format 254 * @driver_ver_str: Driver version, string format 255 * @words: word access to struct contents 256 */ 257 union ionic_drv_identity { 258 struct { 259 __le32 os_type; 260 __le32 os_dist; 261 char os_dist_str[128]; 262 __le32 kernel_ver; 263 char kernel_ver_str[32]; 264 char driver_ver_str[32]; 265 }; 266 __le32 words[478]; 267 }; 268 269 /** 270 * enum ionic_dev_capability - Device capabilities 271 * @IONIC_DEV_CAP_VF_CTRL: Device supports VF ctrl operations 272 */ 273 enum ionic_dev_capability { 274 IONIC_DEV_CAP_VF_CTRL = BIT(0), 275 }; 276 277 /** 278 * union ionic_dev_identity - device identity information 279 * @version: Version of device identify 280 * @type: Identify type (0 for now) 281 * @rsvd: reserved byte(s) 282 * @nports: Number of ports provisioned 283 * @rsvd2: reserved byte(s) 284 * @nlifs: Number of LIFs provisioned 285 * @nintrs: Number of interrupts provisioned 286 * @ndbpgs_per_lif: Number of doorbell pages per LIF 287 * @intr_coal_mult: Interrupt coalescing multiplication factor 288 * Scale user-supplied interrupt coalescing 289 * value in usecs to device units using: 290 * device units = usecs * mult / div 291 * @intr_coal_div: Interrupt coalescing division factor 292 * Scale user-supplied interrupt coalescing 293 * value in usecs to device units using: 294 * device units = usecs * mult / div 295 * @eq_count: Number of shared event queues 296 * @hwstamp_mask: Bitmask for subtraction of hardware tick values. 297 * @hwstamp_mult: Hardware tick to nanosecond multiplier. 298 * @hwstamp_shift: Hardware tick to nanosecond divisor (power of two). 299 * @capabilities: Device capabilities 300 * @words: word access to struct contents 301 */ 302 union ionic_dev_identity { 303 struct { 304 u8 version; 305 u8 type; 306 u8 rsvd[2]; 307 u8 nports; 308 u8 rsvd2[3]; 309 __le32 nlifs; 310 __le32 nintrs; 311 __le32 ndbpgs_per_lif; 312 __le32 intr_coal_mult; 313 __le32 intr_coal_div; 314 __le32 eq_count; 315 __le64 hwstamp_mask; 316 __le32 hwstamp_mult; 317 __le32 hwstamp_shift; 318 __le64 capabilities; 319 }; 320 __le32 words[478]; 321 }; 322 323 enum ionic_lif_type { 324 IONIC_LIF_TYPE_CLASSIC = 0, 325 IONIC_LIF_TYPE_MACVLAN = 1, 326 IONIC_LIF_TYPE_NETQUEUE = 2, 327 }; 328 329 /** 330 * struct ionic_lif_identify_cmd - LIF identify command 331 * @opcode: opcode 332 * @type: LIF type (enum ionic_lif_type) 333 * @ver: Version of identify returned by device 334 * @rsvd: reserved byte(s) 335 */ 336 struct ionic_lif_identify_cmd { 337 u8 opcode; 338 u8 type; 339 u8 ver; 340 u8 rsvd[61]; 341 }; 342 343 /** 344 * struct ionic_lif_identify_comp - LIF identify command completion 345 * @status: Status of the command (enum ionic_status_code) 346 * @ver: Version of identify returned by device 347 * @rsvd2: reserved byte(s) 348 */ 349 struct ionic_lif_identify_comp { 350 u8 status; 351 u8 ver; 352 u8 rsvd2[14]; 353 }; 354 355 /** 356 * enum ionic_lif_capability - LIF capabilities 357 * @IONIC_LIF_CAP_ETH: LIF supports Ethernet 358 * @IONIC_LIF_CAP_RDMA: LIF supports RDMA 359 */ 360 enum ionic_lif_capability { 361 IONIC_LIF_CAP_ETH = BIT(0), 362 IONIC_LIF_CAP_RDMA = BIT(1), 363 }; 364 365 /** 366 * enum ionic_logical_qtype - Logical Queue Types 367 * @IONIC_QTYPE_ADMINQ: Administrative Queue 368 * @IONIC_QTYPE_NOTIFYQ: Notify Queue 369 * @IONIC_QTYPE_RXQ: Receive Queue 370 * @IONIC_QTYPE_TXQ: Transmit Queue 371 * @IONIC_QTYPE_EQ: Event Queue 372 * @IONIC_QTYPE_MAX: Max queue type supported 373 */ 374 enum ionic_logical_qtype { 375 IONIC_QTYPE_ADMINQ = 0, 376 IONIC_QTYPE_NOTIFYQ = 1, 377 IONIC_QTYPE_RXQ = 2, 378 IONIC_QTYPE_TXQ = 3, 379 IONIC_QTYPE_EQ = 4, 380 IONIC_QTYPE_MAX = 16, 381 }; 382 383 /** 384 * enum ionic_q_feature - Common Features for most queue types 385 * 386 * Common features use bits 0-15. Per-queue-type features use higher bits. 387 * 388 * @IONIC_QIDENT_F_CQ: Queue has completion ring 389 * @IONIC_QIDENT_F_SG: Queue has scatter/gather ring 390 * @IONIC_QIDENT_F_EQ: Queue can use event queue 391 * @IONIC_QIDENT_F_CMB: Queue is in cmb bar 392 * @IONIC_Q_F_2X_DESC: Double main descriptor size 393 * @IONIC_Q_F_2X_CQ_DESC: Double cq descriptor size 394 * @IONIC_Q_F_2X_SG_DESC: Double sg descriptor size 395 * @IONIC_Q_F_4X_DESC: Quadruple main descriptor size 396 * @IONIC_Q_F_4X_CQ_DESC: Quadruple cq descriptor size 397 * @IONIC_Q_F_4X_SG_DESC: Quadruple sg descriptor size 398 */ 399 enum ionic_q_feature { 400 IONIC_QIDENT_F_CQ = BIT_ULL(0), 401 IONIC_QIDENT_F_SG = BIT_ULL(1), 402 IONIC_QIDENT_F_EQ = BIT_ULL(2), 403 IONIC_QIDENT_F_CMB = BIT_ULL(3), 404 IONIC_Q_F_2X_DESC = BIT_ULL(4), 405 IONIC_Q_F_2X_CQ_DESC = BIT_ULL(5), 406 IONIC_Q_F_2X_SG_DESC = BIT_ULL(6), 407 IONIC_Q_F_4X_DESC = BIT_ULL(7), 408 IONIC_Q_F_4X_CQ_DESC = BIT_ULL(8), 409 IONIC_Q_F_4X_SG_DESC = BIT_ULL(9), 410 }; 411 412 /** 413 * enum ionic_rxq_feature - RXQ-specific Features 414 * 415 * Per-queue-type features use bits 16 and higher. 416 * 417 * @IONIC_RXQ_F_HWSTAMP: Queue supports Hardware Timestamping 418 */ 419 enum ionic_rxq_feature { 420 IONIC_RXQ_F_HWSTAMP = BIT_ULL(16), 421 }; 422 423 /** 424 * enum ionic_txq_feature - TXQ-specific Features 425 * 426 * Per-queue-type features use bits 16 and higher. 427 * 428 * @IONIC_TXQ_F_HWSTAMP: Queue supports Hardware Timestamping 429 */ 430 enum ionic_txq_feature { 431 IONIC_TXQ_F_HWSTAMP = BIT(16), 432 }; 433 434 /** 435 * enum ionic_hwstamp_bits - Hardware timestamp decoding bits 436 * @IONIC_HWSTAMP_INVALID: Invalid hardware timestamp value 437 * @IONIC_HWSTAMP_CQ_NEGOFFSET: Timestamp field negative offset 438 * from the base cq descriptor. 439 */ 440 enum ionic_hwstamp_bits { 441 IONIC_HWSTAMP_INVALID = ~0ull, 442 IONIC_HWSTAMP_CQ_NEGOFFSET = 8, 443 }; 444 445 /** 446 * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type 447 * @qtype: Hardware Queue Type 448 * @rsvd: reserved byte(s) 449 * @qid_count: Number of Queue IDs of the logical type 450 * @qid_base: Minimum Queue ID of the logical type 451 */ 452 struct ionic_lif_logical_qtype { 453 u8 qtype; 454 u8 rsvd[3]; 455 __le32 qid_count; 456 __le32 qid_base; 457 }; 458 459 /** 460 * enum ionic_lif_state - LIF state 461 * @IONIC_LIF_DISABLE: LIF disabled 462 * @IONIC_LIF_ENABLE: LIF enabled 463 * @IONIC_LIF_QUIESCE: LIF Quiesced 464 */ 465 enum ionic_lif_state { 466 IONIC_LIF_QUIESCE = 0, 467 IONIC_LIF_ENABLE = 1, 468 IONIC_LIF_DISABLE = 2, 469 }; 470 471 /** 472 * union ionic_lif_config - LIF configuration 473 * @state: LIF state (enum ionic_lif_state) 474 * @rsvd: reserved byte(s) 475 * @name: LIF name 476 * @mtu: MTU 477 * @mac: Station MAC address 478 * @vlan: Default Vlan ID 479 * @features: Features (enum ionic_eth_hw_features) 480 * @queue_count: Queue counts per queue-type 481 * @words: word access to struct contents 482 */ 483 union ionic_lif_config { 484 struct { 485 u8 state; 486 u8 rsvd[3]; 487 char name[IONIC_IFNAMSIZ]; 488 __le32 mtu; 489 u8 mac[6]; 490 __le16 vlan; 491 __le64 features; 492 __le32 queue_count[IONIC_QTYPE_MAX]; 493 } __packed; 494 __le32 words[64]; 495 }; 496 497 /** 498 * struct ionic_lif_identity - LIF identity information (type-specific) 499 * 500 * @capabilities: LIF capabilities 501 * 502 * @eth: Ethernet identify structure 503 * @eth.version: Ethernet identify structure version 504 * @eth.rsvd: reserved byte(s) 505 * @eth.max_ucast_filters: Number of perfect unicast addresses supported 506 * @eth.max_mcast_filters: Number of perfect multicast addresses supported 507 * @eth.min_frame_size: Minimum size of frames to be sent 508 * @eth.max_frame_size: Maximum size of frames to be sent 509 * @eth.rsvd2: reserved byte(s) 510 * @eth.hwstamp_tx_modes: Bitmask of BIT_ULL(enum ionic_txstamp_mode) 511 * @eth.hwstamp_rx_filters: Bitmask of enum ionic_pkt_class 512 * @eth.rsvd3: reserved byte(s) 513 * @eth.config: LIF config struct with features, mtu, mac, q counts 514 * 515 * @rdma: RDMA identify structure 516 * @rdma.version: RDMA version of opcodes and queue descriptors 517 * @rdma.qp_opcodes: Number of RDMA queue pair opcodes supported 518 * @rdma.admin_opcodes: Number of RDMA admin opcodes supported 519 * @rdma.rsvd: reserved byte(s) 520 * @rdma.npts_per_lif: Page table size per LIF 521 * @rdma.nmrs_per_lif: Number of memory regions per LIF 522 * @rdma.nahs_per_lif: Number of address handles per LIF 523 * @rdma.max_stride: Max work request stride 524 * @rdma.cl_stride: Cache line stride 525 * @rdma.pte_stride: Page table entry stride 526 * @rdma.rrq_stride: Remote RQ work request stride 527 * @rdma.rsq_stride: Remote SQ work request stride 528 * @rdma.dcqcn_profiles: Number of DCQCN profiles 529 * @rdma.rsvd_dimensions: reserved byte(s) 530 * @rdma.aq_qtype: RDMA Admin Qtype 531 * @rdma.sq_qtype: RDMA Send Qtype 532 * @rdma.rq_qtype: RDMA Receive Qtype 533 * @rdma.cq_qtype: RDMA Completion Qtype 534 * @rdma.eq_qtype: RDMA Event Qtype 535 * @words: word access to struct contents 536 */ 537 union ionic_lif_identity { 538 struct { 539 __le64 capabilities; 540 541 struct { 542 u8 version; 543 u8 rsvd[3]; 544 __le32 max_ucast_filters; 545 __le32 max_mcast_filters; 546 __le16 rss_ind_tbl_sz; 547 __le32 min_frame_size; 548 __le32 max_frame_size; 549 u8 rsvd2[2]; 550 __le64 hwstamp_tx_modes; 551 __le64 hwstamp_rx_filters; 552 u8 rsvd3[88]; 553 union ionic_lif_config config; 554 } __packed eth; 555 556 struct { 557 u8 version; 558 u8 qp_opcodes; 559 u8 admin_opcodes; 560 u8 rsvd; 561 __le32 npts_per_lif; 562 __le32 nmrs_per_lif; 563 __le32 nahs_per_lif; 564 u8 max_stride; 565 u8 cl_stride; 566 u8 pte_stride; 567 u8 rrq_stride; 568 u8 rsq_stride; 569 u8 dcqcn_profiles; 570 u8 rsvd_dimensions[10]; 571 struct ionic_lif_logical_qtype aq_qtype; 572 struct ionic_lif_logical_qtype sq_qtype; 573 struct ionic_lif_logical_qtype rq_qtype; 574 struct ionic_lif_logical_qtype cq_qtype; 575 struct ionic_lif_logical_qtype eq_qtype; 576 } __packed rdma; 577 } __packed; 578 __le32 words[478]; 579 }; 580 581 /** 582 * struct ionic_lif_init_cmd - LIF init command 583 * @opcode: Opcode 584 * @type: LIF type (enum ionic_lif_type) 585 * @index: LIF index 586 * @rsvd: reserved byte(s) 587 * @info_pa: Destination address for LIF info (struct ionic_lif_info) 588 * @rsvd2: reserved byte(s) 589 */ 590 struct ionic_lif_init_cmd { 591 u8 opcode; 592 u8 type; 593 __le16 index; 594 __le32 rsvd; 595 __le64 info_pa; 596 u8 rsvd2[48]; 597 }; 598 599 /** 600 * struct ionic_lif_init_comp - LIF init command completion 601 * @status: Status of the command (enum ionic_status_code) 602 * @rsvd: reserved byte(s) 603 * @hw_index: Hardware index of the initialized LIF 604 * @rsvd2: reserved byte(s) 605 */ 606 struct ionic_lif_init_comp { 607 u8 status; 608 u8 rsvd; 609 __le16 hw_index; 610 u8 rsvd2[12]; 611 }; 612 613 /** 614 * struct ionic_q_identify_cmd - queue identify command 615 * @opcode: opcode 616 * @rsvd: reserved byte(s) 617 * @lif_type: LIF type (enum ionic_lif_type) 618 * @type: Logical queue type (enum ionic_logical_qtype) 619 * @ver: Highest queue type version that the driver supports 620 * @rsvd2: reserved byte(s) 621 */ 622 struct ionic_q_identify_cmd { 623 u8 opcode; 624 u8 rsvd; 625 __le16 lif_type; 626 u8 type; 627 u8 ver; 628 u8 rsvd2[58]; 629 }; 630 631 /** 632 * struct ionic_q_identify_comp - queue identify command completion 633 * @status: Status of the command (enum ionic_status_code) 634 * @rsvd: reserved byte(s) 635 * @comp_index: Index in the descriptor ring for which this is the completion 636 * @ver: Queue type version that can be used with FW 637 * @rsvd2: reserved byte(s) 638 */ 639 struct ionic_q_identify_comp { 640 u8 status; 641 u8 rsvd; 642 __le16 comp_index; 643 u8 ver; 644 u8 rsvd2[11]; 645 }; 646 647 /** 648 * union ionic_q_identity - queue identity information 649 * @version: Queue type version that can be used with FW 650 * @supported: Bitfield of queue versions, first bit = ver 0 651 * @rsvd: reserved byte(s) 652 * @features: Queue features (enum ionic_q_feature, etc) 653 * @desc_sz: Descriptor size 654 * @comp_sz: Completion descriptor size 655 * @sg_desc_sz: Scatter/Gather descriptor size 656 * @max_sg_elems: Maximum number of Scatter/Gather elements 657 * @sg_desc_stride: Number of Scatter/Gather elements per descriptor 658 * @words: word access to struct contents 659 */ 660 union ionic_q_identity { 661 struct { 662 u8 version; 663 u8 supported; 664 u8 rsvd[6]; 665 __le64 features; 666 __le16 desc_sz; 667 __le16 comp_sz; 668 __le16 sg_desc_sz; 669 __le16 max_sg_elems; 670 __le16 sg_desc_stride; 671 }; 672 __le32 words[478]; 673 }; 674 675 /** 676 * struct ionic_q_init_cmd - Queue init command 677 * @opcode: opcode 678 * @rsvd: reserved byte(s) 679 * @type: Logical queue type 680 * @ver: Queue type version 681 * @rsvd1: reserved byte(s) 682 * @lif_index: LIF index 683 * @index: (LIF, qtype) relative admin queue index 684 * @intr_index: Interrupt control register index, or Event queue index 685 * @pid: Process ID 686 * @flags: 687 * IRQ: Interrupt requested on completion 688 * ENA: Enable the queue. If ENA=0 the queue is initialized 689 * but remains disabled, to be later enabled with the 690 * Queue Enable command. If ENA=1, then queue is 691 * initialized and then enabled. 692 * SG: Enable Scatter-Gather on the queue. 693 * in number of descs. The actual ring size is 694 * (1 << ring_size). For example, to 695 * select a ring size of 64 descriptors write 696 * ring_size = 6. The minimum ring_size value is 2 697 * for a ring size of 4 descriptors. The maximum 698 * ring_size value is 16 for a ring size of 64k 699 * descriptors. Values of ring_size <2 and >16 are 700 * reserved. 701 * EQ: Enable the Event Queue 702 * @cos: Class of service for this queue 703 * @ring_size: Queue ring size, encoded as a log2(size) 704 * @ring_base: Queue ring base address 705 * @cq_ring_base: Completion queue ring base address 706 * @sg_ring_base: Scatter/Gather ring base address 707 * @rsvd2: reserved byte(s) 708 * @features: Mask of queue features to enable, if not in the flags above. 709 */ 710 struct ionic_q_init_cmd { 711 u8 opcode; 712 u8 rsvd; 713 __le16 lif_index; 714 u8 type; 715 u8 ver; 716 u8 rsvd1[2]; 717 __le32 index; 718 __le16 pid; 719 __le16 intr_index; 720 __le16 flags; 721 #define IONIC_QINIT_F_IRQ 0x01 /* Request interrupt on completion */ 722 #define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */ 723 #define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */ 724 #define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */ 725 #define IONIC_QINIT_F_CMB 0x10 /* Enable cmb-based queue */ 726 #define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */ 727 u8 cos; 728 u8 ring_size; 729 __le64 ring_base; 730 __le64 cq_ring_base; 731 __le64 sg_ring_base; 732 u8 rsvd2[12]; 733 __le64 features; 734 } __packed; 735 736 /** 737 * struct ionic_q_init_comp - Queue init command completion 738 * @status: Status of the command (enum ionic_status_code) 739 * @rsvd: reserved byte(s) 740 * @comp_index: Index in the descriptor ring for which this is the completion 741 * @hw_index: Hardware Queue ID 742 * @hw_type: Hardware Queue type 743 * @rsvd2: reserved byte(s) 744 * @color: Color 745 */ 746 struct ionic_q_init_comp { 747 u8 status; 748 u8 rsvd; 749 __le16 comp_index; 750 __le32 hw_index; 751 u8 hw_type; 752 u8 rsvd2[6]; 753 u8 color; 754 }; 755 756 /* the device's internal addressing uses up to 52 bits */ 757 #define IONIC_ADDR_LEN 52 758 #define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 759 760 enum ionic_txq_desc_opcode { 761 IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0, 762 IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1, 763 IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2, 764 IONIC_TXQ_DESC_OPCODE_TSO = 3, 765 }; 766 767 /** 768 * struct ionic_txq_desc - Ethernet Tx queue descriptor format 769 * @cmd: Tx operation, see IONIC_TXQ_DESC_OPCODE_*: 770 * 771 * IONIC_TXQ_DESC_OPCODE_CSUM_NONE: 772 * Non-offload send. No segmentation, 773 * fragmentation or checksum calc/insertion is 774 * performed by device; packet is prepared 775 * to send by software stack and requires 776 * no further manipulation from device. 777 * 778 * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL: 779 * Offload 16-bit L4 checksum 780 * calculation/insertion. The device will 781 * calculate the L4 checksum value and 782 * insert the result in the packet's L4 783 * header checksum field. The L4 checksum 784 * is calculated starting at @csum_start bytes 785 * into the packet to the end of the packet. 786 * The checksum insertion position is given 787 * in @csum_offset, which is the offset from 788 * @csum_start to the checksum field in the L4 789 * header. This feature is only applicable to 790 * protocols such as TCP, UDP and ICMP where a 791 * standard (i.e. the 'IP-style' checksum) 792 * one's complement 16-bit checksum is used, 793 * using an IP pseudo-header to seed the 794 * calculation. Software will preload the L4 795 * checksum field with the IP pseudo-header 796 * checksum. 797 * 798 * For tunnel encapsulation, @csum_start and 799 * @csum_offset refer to the inner L4 800 * header. Supported tunnels encapsulations 801 * are: IPIP, GRE, and UDP. If the @encap 802 * is clear, no further processing by the 803 * device is required; software will 804 * calculate the outer header checksums. If 805 * the @encap is set, the device will 806 * offload the outer header checksums using 807 * LCO (local checksum offload) (see 808 * Documentation/networking/checksum-offloads.rst 809 * for more info). 810 * 811 * IONIC_TXQ_DESC_OPCODE_CSUM_HW: 812 * Offload 16-bit checksum computation to hardware. 813 * If @csum_l3 is set then the packet's L3 checksum is 814 * updated. Similarly, if @csum_l4 is set the L4 815 * checksum is updated. If @encap is set then encap header 816 * checksums are also updated. 817 * 818 * IONIC_TXQ_DESC_OPCODE_TSO: 819 * Device performs TCP segmentation offload 820 * (TSO). @hdr_len is the number of bytes 821 * to the end of TCP header (the offset to 822 * the TCP payload). @mss is the desired 823 * MSS, the TCP payload length for each 824 * segment. The device will calculate/ 825 * insert IP (IPv4 only) and TCP checksums 826 * for each segment. In the first data 827 * buffer containing the header template, 828 * the driver will set IPv4 checksum to 0 829 * and preload TCP checksum with the IP 830 * pseudo header calculated with IP length = 0. 831 * 832 * Supported tunnel encapsulations are IPIP, 833 * layer-3 GRE, and UDP. @hdr_len includes 834 * both outer and inner headers. The driver 835 * will set IPv4 checksum to zero and 836 * preload TCP checksum with IP pseudo 837 * header on the inner header. 838 * 839 * TCP ECN offload is supported. The device 840 * will set CWR flag in the first segment if 841 * CWR is set in the template header, and 842 * clear CWR in remaining segments. 843 * flags: 844 * vlan: 845 * Insert an L2 VLAN header using @vlan_tci 846 * encap: 847 * Calculate encap header checksum 848 * csum_l3: 849 * Compute L3 header checksum 850 * csum_l4: 851 * Compute L4 header checksum 852 * tso_sot: 853 * TSO start 854 * tso_eot: 855 * TSO end 856 * num_sg_elems: Number of scatter-gather elements in SG 857 * descriptor 858 * addr: First data buffer's DMA address 859 * (Subsequent data buffers are on txq_sg_desc) 860 * @len: First data buffer's length, in bytes 861 * @vlan_tci: VLAN tag to insert in the packet (if requested 862 * by @V-bit). Includes .1p and .1q tags 863 * @hword0: half word padding 864 * @hdr_len: Length of packet headers, including 865 * encapsulating outer header, if applicable 866 * Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and 867 * IONIC_TXQ_DESC_OPCODE_TSO. Should be set to zero for 868 * all other modes. For 869 * IONIC_TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length 870 * of headers up to inner-most L4 header. For 871 * IONIC_TXQ_DESC_OPCODE_TSO, @hdr_len is up to 872 * inner-most L4 payload, so inclusive of 873 * inner-most L4 header. 874 * @hword1: half word padding 875 * @mss: Desired MSS value for TSO; only applicable for 876 * IONIC_TXQ_DESC_OPCODE_TSO 877 * @csum_start: Offset from packet to first byte checked in L4 checksum 878 * @csum_offset: Offset from csum_start to L4 checksum field 879 * @hword2: half word padding 880 */ 881 struct ionic_txq_desc { 882 __le64 cmd; 883 #define IONIC_TXQ_DESC_OPCODE_MASK 0xf 884 #define IONIC_TXQ_DESC_OPCODE_SHIFT 4 885 #define IONIC_TXQ_DESC_FLAGS_MASK 0xf 886 #define IONIC_TXQ_DESC_FLAGS_SHIFT 0 887 #define IONIC_TXQ_DESC_NSGE_MASK 0xf 888 #define IONIC_TXQ_DESC_NSGE_SHIFT 8 889 #define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 890 #define IONIC_TXQ_DESC_ADDR_SHIFT 12 891 892 /* common flags */ 893 #define IONIC_TXQ_DESC_FLAG_VLAN 0x1 894 #define IONIC_TXQ_DESC_FLAG_ENCAP 0x2 895 896 /* flags for csum_hw opcode */ 897 #define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4 898 #define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8 899 900 /* flags for tso opcode */ 901 #define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4 902 #define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8 903 904 __le16 len; 905 union { 906 __le16 vlan_tci; 907 __le16 hword0; 908 }; 909 union { 910 __le16 csum_start; 911 __le16 hdr_len; 912 __le16 hword1; 913 }; 914 union { 915 __le16 csum_offset; 916 __le16 mss; 917 __le16 hword2; 918 }; 919 }; 920 921 static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags, 922 u8 nsge, u64 addr) 923 { 924 u64 cmd; 925 926 cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << IONIC_TXQ_DESC_OPCODE_SHIFT; 927 cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << IONIC_TXQ_DESC_FLAGS_SHIFT; 928 cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT; 929 cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT; 930 931 return cmd; 932 }; 933 934 static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags, 935 u8 *nsge, u64 *addr) 936 { 937 *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & IONIC_TXQ_DESC_OPCODE_MASK; 938 *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & IONIC_TXQ_DESC_FLAGS_MASK; 939 *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK; 940 *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK; 941 }; 942 943 /** 944 * struct ionic_txq_sg_elem - Transmit scatter-gather (SG) descriptor element 945 * @addr: DMA address of SG element data buffer 946 * @len: Length of SG element data buffer, in bytes 947 * @rsvd: reserved byte(s) 948 */ 949 struct ionic_txq_sg_elem { 950 __le64 addr; 951 __le16 len; 952 __le16 rsvd[3]; 953 }; 954 955 /** 956 * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list 957 * @elems: Scatter-gather elements 958 */ 959 struct ionic_txq_sg_desc { 960 #define IONIC_TX_MAX_SG_ELEMS 8 961 #define IONIC_TX_SG_DESC_STRIDE 8 962 struct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS]; 963 }; 964 965 struct ionic_txq_sg_desc_v1 { 966 #define IONIC_TX_MAX_SG_ELEMS_V1 15 967 #define IONIC_TX_SG_DESC_STRIDE_V1 16 968 struct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1]; 969 }; 970 971 /** 972 * struct ionic_txq_comp - Ethernet transmit queue completion descriptor 973 * @status: Status of the command (enum ionic_status_code) 974 * @rsvd: reserved byte(s) 975 * @comp_index: Index in the descriptor ring for which this is the completion 976 * @rsvd2: reserved byte(s) 977 * @color: Color bit 978 */ 979 struct ionic_txq_comp { 980 u8 status; 981 u8 rsvd; 982 __le16 comp_index; 983 u8 rsvd2[11]; 984 u8 color; 985 }; 986 987 enum ionic_rxq_desc_opcode { 988 IONIC_RXQ_DESC_OPCODE_SIMPLE = 0, 989 IONIC_RXQ_DESC_OPCODE_SG = 1, 990 }; 991 992 /** 993 * struct ionic_rxq_desc - Ethernet Rx queue descriptor format 994 * @opcode: Rx operation, see IONIC_RXQ_DESC_OPCODE_*: 995 * 996 * IONIC_RXQ_DESC_OPCODE_SIMPLE: 997 * Receive full packet into data buffer 998 * starting at @addr. Results of 999 * receive, including actual bytes received, 1000 * are recorded in Rx completion descriptor. 1001 * 1002 * @rsvd: reserved byte(s) 1003 * @len: Data buffer's length, in bytes 1004 * @addr: Data buffer's DMA address 1005 */ 1006 struct ionic_rxq_desc { 1007 u8 opcode; 1008 u8 rsvd[5]; 1009 __le16 len; 1010 __le64 addr; 1011 }; 1012 1013 /** 1014 * struct ionic_rxq_sg_elem - Receive scatter-gather (SG) descriptor element 1015 * @addr: DMA address of SG element data buffer 1016 * @len: Length of SG element data buffer, in bytes 1017 * @rsvd: reserved byte(s) 1018 */ 1019 struct ionic_rxq_sg_elem { 1020 __le64 addr; 1021 __le16 len; 1022 __le16 rsvd[3]; 1023 }; 1024 1025 /** 1026 * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list 1027 * @elems: Scatter-gather elements 1028 */ 1029 struct ionic_rxq_sg_desc { 1030 #define IONIC_RX_MAX_SG_ELEMS 8 1031 #define IONIC_RX_SG_DESC_STRIDE 8 1032 struct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE]; 1033 }; 1034 1035 /** 1036 * struct ionic_rxq_comp - Ethernet receive queue completion descriptor 1037 * @status: Status of the command (enum ionic_status_code) 1038 * @num_sg_elems: Number of SG elements used by this descriptor 1039 * @comp_index: Index in the descriptor ring for which this is the completion 1040 * @rss_hash: 32-bit RSS hash 1041 * @csum: 16-bit sum of the packet's L2 payload 1042 * If the packet's L2 payload is odd length, an extra 1043 * zero-value byte is included in the @csum calculation but 1044 * not included in @len. 1045 * @vlan_tci: VLAN tag stripped from the packet. Valid if @VLAN is 1046 * set. Includes .1p and .1q tags. 1047 * @len: Received packet length, in bytes. Excludes FCS. 1048 * @csum_calc L2 payload checksum is computed or not 1049 * @csum_flags: See IONIC_RXQ_COMP_CSUM_F_*: 1050 * 1051 * IONIC_RXQ_COMP_CSUM_F_TCP_OK: 1052 * The TCP checksum calculated by the device 1053 * matched the checksum in the receive packet's 1054 * TCP header. 1055 * 1056 * IONIC_RXQ_COMP_CSUM_F_TCP_BAD: 1057 * The TCP checksum calculated by the device did 1058 * not match the checksum in the receive packet's 1059 * TCP header. 1060 * 1061 * IONIC_RXQ_COMP_CSUM_F_UDP_OK: 1062 * The UDP checksum calculated by the device 1063 * matched the checksum in the receive packet's 1064 * UDP header 1065 * 1066 * IONIC_RXQ_COMP_CSUM_F_UDP_BAD: 1067 * The UDP checksum calculated by the device did 1068 * not match the checksum in the receive packet's 1069 * UDP header. 1070 * 1071 * IONIC_RXQ_COMP_CSUM_F_IP_OK: 1072 * The IPv4 checksum calculated by the device 1073 * matched the checksum in the receive packet's 1074 * first IPv4 header. If the receive packet 1075 * contains both a tunnel IPv4 header and a 1076 * transport IPv4 header, the device validates the 1077 * checksum for the both IPv4 headers. 1078 * 1079 * IONIC_RXQ_COMP_CSUM_F_IP_BAD: 1080 * The IPv4 checksum calculated by the device did 1081 * not match the checksum in the receive packet's 1082 * first IPv4 header. If the receive packet 1083 * contains both a tunnel IPv4 header and a 1084 * transport IPv4 header, the device validates the 1085 * checksum for both IP headers. 1086 * 1087 * IONIC_RXQ_COMP_CSUM_F_VLAN: 1088 * The VLAN header was stripped and placed in @vlan_tci. 1089 * 1090 * IONIC_RXQ_COMP_CSUM_F_CALC: 1091 * The checksum was calculated by the device. 1092 * 1093 * @pkt_type_color: Packet type and color bit; see IONIC_RXQ_COMP_PKT_TYPE_MASK 1094 */ 1095 struct ionic_rxq_comp { 1096 u8 status; 1097 u8 num_sg_elems; 1098 __le16 comp_index; 1099 __le32 rss_hash; 1100 __le16 csum; 1101 __le16 vlan_tci; 1102 __le16 len; 1103 u8 csum_flags; 1104 #define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01 1105 #define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02 1106 #define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04 1107 #define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08 1108 #define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10 1109 #define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20 1110 #define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40 1111 #define IONIC_RXQ_COMP_CSUM_F_CALC 0x80 1112 u8 pkt_type_color; 1113 #define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x7f 1114 }; 1115 1116 enum ionic_pkt_type { 1117 IONIC_PKT_TYPE_NON_IP = 0x00, 1118 IONIC_PKT_TYPE_IPV4 = 0x01, 1119 IONIC_PKT_TYPE_IPV4_TCP = 0x03, 1120 IONIC_PKT_TYPE_IPV4_UDP = 0x05, 1121 IONIC_PKT_TYPE_IPV6 = 0x08, 1122 IONIC_PKT_TYPE_IPV6_TCP = 0x18, 1123 IONIC_PKT_TYPE_IPV6_UDP = 0x28, 1124 /* below types are only used if encap offloads are enabled on lif */ 1125 IONIC_PKT_TYPE_ENCAP_NON_IP = 0x40, 1126 IONIC_PKT_TYPE_ENCAP_IPV4 = 0x41, 1127 IONIC_PKT_TYPE_ENCAP_IPV4_TCP = 0x43, 1128 IONIC_PKT_TYPE_ENCAP_IPV4_UDP = 0x45, 1129 IONIC_PKT_TYPE_ENCAP_IPV6 = 0x48, 1130 IONIC_PKT_TYPE_ENCAP_IPV6_TCP = 0x58, 1131 IONIC_PKT_TYPE_ENCAP_IPV6_UDP = 0x68, 1132 }; 1133 1134 enum ionic_eth_hw_features { 1135 IONIC_ETH_HW_VLAN_TX_TAG = BIT(0), 1136 IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1), 1137 IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2), 1138 IONIC_ETH_HW_RX_HASH = BIT(3), 1139 IONIC_ETH_HW_RX_CSUM = BIT(4), 1140 IONIC_ETH_HW_TX_SG = BIT(5), 1141 IONIC_ETH_HW_RX_SG = BIT(6), 1142 IONIC_ETH_HW_TX_CSUM = BIT(7), 1143 IONIC_ETH_HW_TSO = BIT(8), 1144 IONIC_ETH_HW_TSO_IPV6 = BIT(9), 1145 IONIC_ETH_HW_TSO_ECN = BIT(10), 1146 IONIC_ETH_HW_TSO_GRE = BIT(11), 1147 IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12), 1148 IONIC_ETH_HW_TSO_IPXIP4 = BIT(13), 1149 IONIC_ETH_HW_TSO_IPXIP6 = BIT(14), 1150 IONIC_ETH_HW_TSO_UDP = BIT(15), 1151 IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16), 1152 IONIC_ETH_HW_RX_CSUM_GENEVE = BIT(17), 1153 IONIC_ETH_HW_TX_CSUM_GENEVE = BIT(18), 1154 IONIC_ETH_HW_TSO_GENEVE = BIT(19), 1155 IONIC_ETH_HW_TIMESTAMP = BIT(20), 1156 }; 1157 1158 /** 1159 * enum ionic_pkt_class - Packet classification mask. 1160 * 1161 * Used with rx steering filter, packets indicated by the mask can be steered 1162 * toward a specific receive queue. 1163 * 1164 * @IONIC_PKT_CLS_NTP_ALL: All NTP packets. 1165 * @IONIC_PKT_CLS_PTP1_SYNC: PTPv1 sync 1166 * @IONIC_PKT_CLS_PTP1_DREQ: PTPv1 delay-request 1167 * @IONIC_PKT_CLS_PTP1_ALL: PTPv1 all packets 1168 * @IONIC_PKT_CLS_PTP2_L4_SYNC: PTPv2-UDP sync 1169 * @IONIC_PKT_CLS_PTP2_L4_DREQ: PTPv2-UDP delay-request 1170 * @IONIC_PKT_CLS_PTP2_L4_ALL: PTPv2-UDP all packets 1171 * @IONIC_PKT_CLS_PTP2_L2_SYNC: PTPv2-ETH sync 1172 * @IONIC_PKT_CLS_PTP2_L2_DREQ: PTPv2-ETH delay-request 1173 * @IONIC_PKT_CLS_PTP2_L2_ALL: PTPv2-ETH all packets 1174 * @IONIC_PKT_CLS_PTP2_SYNC: PTPv2 sync 1175 * @IONIC_PKT_CLS_PTP2_DREQ: PTPv2 delay-request 1176 * @IONIC_PKT_CLS_PTP2_ALL: PTPv2 all packets 1177 * @IONIC_PKT_CLS_PTP_SYNC: PTP sync 1178 * @IONIC_PKT_CLS_PTP_DREQ: PTP delay-request 1179 * @IONIC_PKT_CLS_PTP_ALL: PTP all packets 1180 */ 1181 enum ionic_pkt_class { 1182 IONIC_PKT_CLS_NTP_ALL = BIT(0), 1183 1184 IONIC_PKT_CLS_PTP1_SYNC = BIT(1), 1185 IONIC_PKT_CLS_PTP1_DREQ = BIT(2), 1186 IONIC_PKT_CLS_PTP1_ALL = BIT(3) | 1187 IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP1_DREQ, 1188 1189 IONIC_PKT_CLS_PTP2_L4_SYNC = BIT(4), 1190 IONIC_PKT_CLS_PTP2_L4_DREQ = BIT(5), 1191 IONIC_PKT_CLS_PTP2_L4_ALL = BIT(6) | 1192 IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L4_DREQ, 1193 1194 IONIC_PKT_CLS_PTP2_L2_SYNC = BIT(7), 1195 IONIC_PKT_CLS_PTP2_L2_DREQ = BIT(8), 1196 IONIC_PKT_CLS_PTP2_L2_ALL = BIT(9) | 1197 IONIC_PKT_CLS_PTP2_L2_SYNC | IONIC_PKT_CLS_PTP2_L2_DREQ, 1198 1199 IONIC_PKT_CLS_PTP2_SYNC = 1200 IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L2_SYNC, 1201 IONIC_PKT_CLS_PTP2_DREQ = 1202 IONIC_PKT_CLS_PTP2_L4_DREQ | IONIC_PKT_CLS_PTP2_L2_DREQ, 1203 IONIC_PKT_CLS_PTP2_ALL = 1204 IONIC_PKT_CLS_PTP2_L4_ALL | IONIC_PKT_CLS_PTP2_L2_ALL, 1205 1206 IONIC_PKT_CLS_PTP_SYNC = 1207 IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP2_SYNC, 1208 IONIC_PKT_CLS_PTP_DREQ = 1209 IONIC_PKT_CLS_PTP1_DREQ | IONIC_PKT_CLS_PTP2_DREQ, 1210 IONIC_PKT_CLS_PTP_ALL = 1211 IONIC_PKT_CLS_PTP1_ALL | IONIC_PKT_CLS_PTP2_ALL, 1212 }; 1213 1214 /** 1215 * struct ionic_q_control_cmd - Queue control command 1216 * @opcode: opcode 1217 * @type: Queue type 1218 * @lif_index: LIF index 1219 * @index: Queue index 1220 * @oper: Operation (enum ionic_q_control_oper) 1221 * @rsvd: reserved byte(s) 1222 */ 1223 struct ionic_q_control_cmd { 1224 u8 opcode; 1225 u8 type; 1226 __le16 lif_index; 1227 __le32 index; 1228 u8 oper; 1229 u8 rsvd[55]; 1230 }; 1231 1232 typedef struct ionic_admin_comp ionic_q_control_comp; 1233 1234 enum ionic_q_control_oper { 1235 IONIC_Q_DISABLE = 0, 1236 IONIC_Q_ENABLE = 1, 1237 IONIC_Q_HANG_RESET = 2, 1238 }; 1239 1240 /** 1241 * enum ionic_phy_type - Physical connection type 1242 * @IONIC_PHY_TYPE_NONE: No PHY installed 1243 * @IONIC_PHY_TYPE_COPPER: Copper PHY 1244 * @IONIC_PHY_TYPE_FIBER: Fiber PHY 1245 */ 1246 enum ionic_phy_type { 1247 IONIC_PHY_TYPE_NONE = 0, 1248 IONIC_PHY_TYPE_COPPER = 1, 1249 IONIC_PHY_TYPE_FIBER = 2, 1250 }; 1251 1252 /** 1253 * enum ionic_xcvr_state - Transceiver status 1254 * @IONIC_XCVR_STATE_REMOVED: Transceiver removed 1255 * @IONIC_XCVR_STATE_INSERTED: Transceiver inserted 1256 * @IONIC_XCVR_STATE_PENDING: Transceiver pending 1257 * @IONIC_XCVR_STATE_SPROM_READ: Transceiver data read 1258 * @IONIC_XCVR_STATE_SPROM_READ_ERR: Transceiver data read error 1259 */ 1260 enum ionic_xcvr_state { 1261 IONIC_XCVR_STATE_REMOVED = 0, 1262 IONIC_XCVR_STATE_INSERTED = 1, 1263 IONIC_XCVR_STATE_PENDING = 2, 1264 IONIC_XCVR_STATE_SPROM_READ = 3, 1265 IONIC_XCVR_STATE_SPROM_READ_ERR = 4, 1266 }; 1267 1268 /* 1269 * enum ionic_xcvr_pid - Supported link modes 1270 */ 1271 enum ionic_xcvr_pid { 1272 IONIC_XCVR_PID_UNKNOWN = 0, 1273 1274 /* CU */ 1275 IONIC_XCVR_PID_QSFP_100G_CR4 = 1, 1276 IONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2, 1277 IONIC_XCVR_PID_SFP_25GBASE_CR_S = 3, 1278 IONIC_XCVR_PID_SFP_25GBASE_CR_L = 4, 1279 IONIC_XCVR_PID_SFP_25GBASE_CR_N = 5, 1280 IONIC_XCVR_PID_QSFP_50G_CR2_FC = 6, 1281 IONIC_XCVR_PID_QSFP_50G_CR2 = 7, 1282 IONIC_XCVR_PID_QSFP_200G_CR4 = 8, 1283 IONIC_XCVR_PID_QSFP_400G_CR4 = 9, 1284 /* Fiber */ 1285 IONIC_XCVR_PID_QSFP_100G_AOC = 50, 1286 IONIC_XCVR_PID_QSFP_100G_ACC = 51, 1287 IONIC_XCVR_PID_QSFP_100G_SR4 = 52, 1288 IONIC_XCVR_PID_QSFP_100G_LR4 = 53, 1289 IONIC_XCVR_PID_QSFP_100G_ER4 = 54, 1290 IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55, 1291 IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56, 1292 IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57, 1293 IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58, 1294 IONIC_XCVR_PID_SFP_25GBASE_SR = 59, 1295 IONIC_XCVR_PID_SFP_25GBASE_LR = 60, 1296 IONIC_XCVR_PID_SFP_25GBASE_ER = 61, 1297 IONIC_XCVR_PID_SFP_25GBASE_AOC = 62, 1298 IONIC_XCVR_PID_SFP_10GBASE_SR = 63, 1299 IONIC_XCVR_PID_SFP_10GBASE_LR = 64, 1300 IONIC_XCVR_PID_SFP_10GBASE_LRM = 65, 1301 IONIC_XCVR_PID_SFP_10GBASE_ER = 66, 1302 IONIC_XCVR_PID_SFP_10GBASE_AOC = 67, 1303 IONIC_XCVR_PID_SFP_10GBASE_CU = 68, 1304 IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69, 1305 IONIC_XCVR_PID_QSFP_100G_PSM4 = 70, 1306 IONIC_XCVR_PID_SFP_25GBASE_ACC = 71, 1307 IONIC_XCVR_PID_SFP_10GBASE_T = 72, 1308 IONIC_XCVR_PID_SFP_1000BASE_T = 73, 1309 IONIC_XCVR_PID_QSFP_200G_AOC = 74, 1310 IONIC_XCVR_PID_QSFP_200G_FR4 = 75, 1311 IONIC_XCVR_PID_QSFP_200G_DR4 = 76, 1312 IONIC_XCVR_PID_QSFP_200G_SR4 = 77, 1313 IONIC_XCVR_PID_QSFP_200G_ACC = 78, 1314 IONIC_XCVR_PID_QSFP_400G_FR4 = 79, 1315 IONIC_XCVR_PID_QSFP_400G_DR4 = 80, 1316 IONIC_XCVR_PID_QSFP_400G_SR4 = 81, 1317 IONIC_XCVR_PID_QSFP_400G_VR4 = 82, 1318 }; 1319 1320 /** 1321 * enum ionic_port_type - Port types 1322 * @IONIC_PORT_TYPE_NONE: Port type not configured 1323 * @IONIC_PORT_TYPE_ETH: Port carries ethernet traffic (inband) 1324 * @IONIC_PORT_TYPE_MGMT: Port carries mgmt traffic (out-of-band) 1325 */ 1326 enum ionic_port_type { 1327 IONIC_PORT_TYPE_NONE = 0, 1328 IONIC_PORT_TYPE_ETH = 1, 1329 IONIC_PORT_TYPE_MGMT = 2, 1330 }; 1331 1332 /** 1333 * enum ionic_port_admin_state - Port config state 1334 * @IONIC_PORT_ADMIN_STATE_NONE: Port admin state not configured 1335 * @IONIC_PORT_ADMIN_STATE_DOWN: Port admin disabled 1336 * @IONIC_PORT_ADMIN_STATE_UP: Port admin enabled 1337 */ 1338 enum ionic_port_admin_state { 1339 IONIC_PORT_ADMIN_STATE_NONE = 0, 1340 IONIC_PORT_ADMIN_STATE_DOWN = 1, 1341 IONIC_PORT_ADMIN_STATE_UP = 2, 1342 }; 1343 1344 /** 1345 * enum ionic_port_oper_status - Port operational status 1346 * @IONIC_PORT_OPER_STATUS_NONE: Port disabled 1347 * @IONIC_PORT_OPER_STATUS_UP: Port link status up 1348 * @IONIC_PORT_OPER_STATUS_DOWN: Port link status down 1349 */ 1350 enum ionic_port_oper_status { 1351 IONIC_PORT_OPER_STATUS_NONE = 0, 1352 IONIC_PORT_OPER_STATUS_UP = 1, 1353 IONIC_PORT_OPER_STATUS_DOWN = 2, 1354 }; 1355 1356 /** 1357 * enum ionic_port_fec_type - Ethernet Forward error correction (FEC) modes 1358 * @IONIC_PORT_FEC_TYPE_NONE: FEC Disabled 1359 * @IONIC_PORT_FEC_TYPE_FC: FireCode FEC 1360 * @IONIC_PORT_FEC_TYPE_RS: ReedSolomon FEC 1361 */ 1362 enum ionic_port_fec_type { 1363 IONIC_PORT_FEC_TYPE_NONE = 0, 1364 IONIC_PORT_FEC_TYPE_FC = 1, 1365 IONIC_PORT_FEC_TYPE_RS = 2, 1366 }; 1367 1368 /** 1369 * enum ionic_port_pause_type - Ethernet pause (flow control) modes 1370 * @IONIC_PORT_PAUSE_TYPE_NONE: Disable Pause 1371 * @IONIC_PORT_PAUSE_TYPE_LINK: Link level pause 1372 * @IONIC_PORT_PAUSE_TYPE_PFC: Priority-Flow Control 1373 */ 1374 enum ionic_port_pause_type { 1375 IONIC_PORT_PAUSE_TYPE_NONE = 0, 1376 IONIC_PORT_PAUSE_TYPE_LINK = 1, 1377 IONIC_PORT_PAUSE_TYPE_PFC = 2, 1378 }; 1379 1380 /** 1381 * enum ionic_port_loopback_mode - Loopback modes 1382 * @IONIC_PORT_LOOPBACK_MODE_NONE: Disable loopback 1383 * @IONIC_PORT_LOOPBACK_MODE_MAC: MAC loopback 1384 * @IONIC_PORT_LOOPBACK_MODE_PHY: PHY/SerDes loopback 1385 */ 1386 enum ionic_port_loopback_mode { 1387 IONIC_PORT_LOOPBACK_MODE_NONE = 0, 1388 IONIC_PORT_LOOPBACK_MODE_MAC = 1, 1389 IONIC_PORT_LOOPBACK_MODE_PHY = 2, 1390 }; 1391 1392 /** 1393 * struct ionic_xcvr_status - Transceiver Status information 1394 * @state: Transceiver status (enum ionic_xcvr_state) 1395 * @phy: Physical connection type (enum ionic_phy_type) 1396 * @pid: Transceiver link mode (enum ionic_xcvr_pid) 1397 * @sprom: Transceiver sprom contents 1398 */ 1399 struct ionic_xcvr_status { 1400 u8 state; 1401 u8 phy; 1402 __le16 pid; 1403 u8 sprom[256]; 1404 }; 1405 1406 /** 1407 * union ionic_port_config - Port configuration 1408 * @speed: port speed (in Mbps) 1409 * @mtu: mtu 1410 * @state: port admin state (enum ionic_port_admin_state) 1411 * @an_enable: autoneg enable 1412 * @fec_type: fec type (enum ionic_port_fec_type) 1413 * @pause_type: pause type (enum ionic_port_pause_type) 1414 * @loopback_mode: loopback mode (enum ionic_port_loopback_mode) 1415 * @words: word access to struct contents 1416 */ 1417 union ionic_port_config { 1418 struct { 1419 #define IONIC_SPEED_400G 400000 /* 400G in Mbps */ 1420 #define IONIC_SPEED_200G 200000 /* 200G in Mbps */ 1421 #define IONIC_SPEED_100G 100000 /* 100G in Mbps */ 1422 #define IONIC_SPEED_50G 50000 /* 50G in Mbps */ 1423 #define IONIC_SPEED_40G 40000 /* 40G in Mbps */ 1424 #define IONIC_SPEED_25G 25000 /* 25G in Mbps */ 1425 #define IONIC_SPEED_10G 10000 /* 10G in Mbps */ 1426 #define IONIC_SPEED_1G 1000 /* 1G in Mbps */ 1427 __le32 speed; 1428 __le32 mtu; 1429 u8 state; 1430 u8 an_enable; 1431 u8 fec_type; 1432 #define IONIC_PAUSE_TYPE_MASK 0x0f 1433 #define IONIC_PAUSE_FLAGS_MASK 0xf0 1434 #define IONIC_PAUSE_F_TX 0x10 1435 #define IONIC_PAUSE_F_RX 0x20 1436 u8 pause_type; 1437 u8 loopback_mode; 1438 }; 1439 __le32 words[64]; 1440 }; 1441 1442 /** 1443 * struct ionic_port_status - Port Status information 1444 * @status: link status (enum ionic_port_oper_status) 1445 * @id: port id 1446 * @speed: link speed (in Mbps) 1447 * @link_down_count: number of times link went from up to down 1448 * @fec_type: fec type (enum ionic_port_fec_type) 1449 * @rsvd: reserved byte(s) 1450 * @xcvr: transceiver status 1451 */ 1452 struct ionic_port_status { 1453 __le32 id; 1454 __le32 speed; 1455 u8 status; 1456 __le16 link_down_count; 1457 u8 fec_type; 1458 u8 rsvd[48]; 1459 struct ionic_xcvr_status xcvr; 1460 } __packed; 1461 1462 /** 1463 * struct ionic_port_identify_cmd - Port identify command 1464 * @opcode: opcode 1465 * @index: port index 1466 * @ver: Highest version of identify supported by driver 1467 * @rsvd: reserved byte(s) 1468 */ 1469 struct ionic_port_identify_cmd { 1470 u8 opcode; 1471 u8 index; 1472 u8 ver; 1473 u8 rsvd[61]; 1474 }; 1475 1476 /** 1477 * struct ionic_port_identify_comp - Port identify command completion 1478 * @status: Status of the command (enum ionic_status_code) 1479 * @ver: Version of identify returned by device 1480 * @rsvd: reserved byte(s) 1481 */ 1482 struct ionic_port_identify_comp { 1483 u8 status; 1484 u8 ver; 1485 u8 rsvd[14]; 1486 }; 1487 1488 /** 1489 * struct ionic_port_init_cmd - Port initialization command 1490 * @opcode: opcode 1491 * @index: port index 1492 * @rsvd: reserved byte(s) 1493 * @info_pa: destination address for port info (struct ionic_port_info) 1494 * @rsvd2: reserved byte(s) 1495 */ 1496 struct ionic_port_init_cmd { 1497 u8 opcode; 1498 u8 index; 1499 u8 rsvd[6]; 1500 __le64 info_pa; 1501 u8 rsvd2[48]; 1502 }; 1503 1504 /** 1505 * struct ionic_port_init_comp - Port initialization command completion 1506 * @status: Status of the command (enum ionic_status_code) 1507 * @rsvd: reserved byte(s) 1508 */ 1509 struct ionic_port_init_comp { 1510 u8 status; 1511 u8 rsvd[15]; 1512 }; 1513 1514 /** 1515 * struct ionic_port_reset_cmd - Port reset command 1516 * @opcode: opcode 1517 * @index: port index 1518 * @rsvd: reserved byte(s) 1519 */ 1520 struct ionic_port_reset_cmd { 1521 u8 opcode; 1522 u8 index; 1523 u8 rsvd[62]; 1524 }; 1525 1526 /** 1527 * struct ionic_port_reset_comp - Port reset command completion 1528 * @status: Status of the command (enum ionic_status_code) 1529 * @rsvd: reserved byte(s) 1530 */ 1531 struct ionic_port_reset_comp { 1532 u8 status; 1533 u8 rsvd[15]; 1534 }; 1535 1536 /** 1537 * enum ionic_stats_ctl_cmd - List of commands for stats control 1538 * @IONIC_STATS_CTL_RESET: Reset statistics 1539 */ 1540 enum ionic_stats_ctl_cmd { 1541 IONIC_STATS_CTL_RESET = 0, 1542 }; 1543 1544 /** 1545 * enum ionic_txstamp_mode - List of TX Timestamping Modes 1546 * @IONIC_TXSTAMP_OFF: Disable TX hardware timetamping. 1547 * @IONIC_TXSTAMP_ON: Enable local TX hardware timetamping. 1548 * @IONIC_TXSTAMP_ONESTEP_SYNC: Modify TX PTP Sync packets. 1549 * @IONIC_TXSTAMP_ONESTEP_P2P: Modify TX PTP Sync and PDelayResp. 1550 */ 1551 enum ionic_txstamp_mode { 1552 IONIC_TXSTAMP_OFF = 0, 1553 IONIC_TXSTAMP_ON = 1, 1554 IONIC_TXSTAMP_ONESTEP_SYNC = 2, 1555 IONIC_TXSTAMP_ONESTEP_P2P = 3, 1556 }; 1557 1558 /** 1559 * enum ionic_port_attr - List of device attributes 1560 * @IONIC_PORT_ATTR_STATE: Port state attribute 1561 * @IONIC_PORT_ATTR_SPEED: Port speed attribute 1562 * @IONIC_PORT_ATTR_MTU: Port MTU attribute 1563 * @IONIC_PORT_ATTR_AUTONEG: Port autonegotiation attribute 1564 * @IONIC_PORT_ATTR_FEC: Port FEC attribute 1565 * @IONIC_PORT_ATTR_PAUSE: Port pause attribute 1566 * @IONIC_PORT_ATTR_LOOPBACK: Port loopback attribute 1567 * @IONIC_PORT_ATTR_STATS_CTRL: Port statistics control attribute 1568 */ 1569 enum ionic_port_attr { 1570 IONIC_PORT_ATTR_STATE = 0, 1571 IONIC_PORT_ATTR_SPEED = 1, 1572 IONIC_PORT_ATTR_MTU = 2, 1573 IONIC_PORT_ATTR_AUTONEG = 3, 1574 IONIC_PORT_ATTR_FEC = 4, 1575 IONIC_PORT_ATTR_PAUSE = 5, 1576 IONIC_PORT_ATTR_LOOPBACK = 6, 1577 IONIC_PORT_ATTR_STATS_CTRL = 7, 1578 }; 1579 1580 /** 1581 * struct ionic_port_setattr_cmd - Set port attributes on the NIC 1582 * @opcode: Opcode 1583 * @index: Port index 1584 * @attr: Attribute type (enum ionic_port_attr) 1585 * @rsvd: reserved byte(s) 1586 * @state: Port state 1587 * @speed: Port speed 1588 * @mtu: Port MTU 1589 * @an_enable: Port autonegotiation setting 1590 * @fec_type: Port FEC type setting 1591 * @pause_type: Port pause type setting 1592 * @loopback_mode: Port loopback mode 1593 * @stats_ctl: Port stats setting 1594 * @rsvd2: reserved byte(s) 1595 */ 1596 struct ionic_port_setattr_cmd { 1597 u8 opcode; 1598 u8 index; 1599 u8 attr; 1600 u8 rsvd; 1601 union { 1602 u8 state; 1603 __le32 speed; 1604 __le32 mtu; 1605 u8 an_enable; 1606 u8 fec_type; 1607 u8 pause_type; 1608 u8 loopback_mode; 1609 u8 stats_ctl; 1610 u8 rsvd2[60]; 1611 }; 1612 }; 1613 1614 /** 1615 * struct ionic_port_setattr_comp - Port set attr command completion 1616 * @status: Status of the command (enum ionic_status_code) 1617 * @rsvd: reserved byte(s) 1618 * @color: Color bit 1619 */ 1620 struct ionic_port_setattr_comp { 1621 u8 status; 1622 u8 rsvd[14]; 1623 u8 color; 1624 }; 1625 1626 /** 1627 * struct ionic_port_getattr_cmd - Get port attributes from the NIC 1628 * @opcode: Opcode 1629 * @index: port index 1630 * @attr: Attribute type (enum ionic_port_attr) 1631 * @rsvd: reserved byte(s) 1632 */ 1633 struct ionic_port_getattr_cmd { 1634 u8 opcode; 1635 u8 index; 1636 u8 attr; 1637 u8 rsvd[61]; 1638 }; 1639 1640 /** 1641 * struct ionic_port_getattr_comp - Port get attr command completion 1642 * @status: Status of the command (enum ionic_status_code) 1643 * @rsvd: reserved byte(s) 1644 * @state: Port state 1645 * @speed: Port speed 1646 * @mtu: Port MTU 1647 * @an_enable: Port autonegotiation setting 1648 * @fec_type: Port FEC type setting 1649 * @pause_type: Port pause type setting 1650 * @loopback_mode: Port loopback mode 1651 * @rsvd2: reserved byte(s) 1652 * @color: Color bit 1653 */ 1654 struct ionic_port_getattr_comp { 1655 u8 status; 1656 u8 rsvd[3]; 1657 union { 1658 u8 state; 1659 __le32 speed; 1660 __le32 mtu; 1661 u8 an_enable; 1662 u8 fec_type; 1663 u8 pause_type; 1664 u8 loopback_mode; 1665 u8 rsvd2[11]; 1666 } __packed; 1667 u8 color; 1668 }; 1669 1670 /** 1671 * struct ionic_lif_status - LIF status register 1672 * @eid: most recent NotifyQ event id 1673 * @port_num: port the LIF is connected to 1674 * @rsvd: reserved byte(s) 1675 * @link_status: port status (enum ionic_port_oper_status) 1676 * @link_speed: speed of link in Mbps 1677 * @link_down_count: number of times link went from up to down 1678 * @rsvd2: reserved byte(s) 1679 */ 1680 struct ionic_lif_status { 1681 __le64 eid; 1682 u8 port_num; 1683 u8 rsvd; 1684 __le16 link_status; 1685 __le32 link_speed; /* units of 1Mbps: eg 10000 = 10Gbps */ 1686 __le16 link_down_count; 1687 u8 rsvd2[46]; 1688 }; 1689 1690 /** 1691 * struct ionic_lif_reset_cmd - LIF reset command 1692 * @opcode: opcode 1693 * @rsvd: reserved byte(s) 1694 * @index: LIF index 1695 * @rsvd2: reserved byte(s) 1696 */ 1697 struct ionic_lif_reset_cmd { 1698 u8 opcode; 1699 u8 rsvd; 1700 __le16 index; 1701 __le32 rsvd2[15]; 1702 }; 1703 1704 typedef struct ionic_admin_comp ionic_lif_reset_comp; 1705 1706 enum ionic_dev_state { 1707 IONIC_DEV_DISABLE = 0, 1708 IONIC_DEV_ENABLE = 1, 1709 IONIC_DEV_HANG_RESET = 2, 1710 }; 1711 1712 /** 1713 * enum ionic_dev_attr - List of device attributes 1714 * @IONIC_DEV_ATTR_STATE: Device state attribute 1715 * @IONIC_DEV_ATTR_NAME: Device name attribute 1716 * @IONIC_DEV_ATTR_FEATURES: Device feature attributes 1717 */ 1718 enum ionic_dev_attr { 1719 IONIC_DEV_ATTR_STATE = 0, 1720 IONIC_DEV_ATTR_NAME = 1, 1721 IONIC_DEV_ATTR_FEATURES = 2, 1722 }; 1723 1724 /** 1725 * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC 1726 * @opcode: Opcode 1727 * @attr: Attribute type (enum ionic_dev_attr) 1728 * @rsvd: reserved byte(s) 1729 * @state: Device state (enum ionic_dev_state) 1730 * @name: The bus info, e.g. PCI slot-device-function, 0 terminated 1731 * @features: Device features 1732 * @rsvd2: reserved byte(s) 1733 */ 1734 struct ionic_dev_setattr_cmd { 1735 u8 opcode; 1736 u8 attr; 1737 __le16 rsvd; 1738 union { 1739 u8 state; 1740 char name[IONIC_IFNAMSIZ]; 1741 __le64 features; 1742 u8 rsvd2[60]; 1743 } __packed; 1744 }; 1745 1746 /** 1747 * struct ionic_dev_setattr_comp - Device set attr command completion 1748 * @status: Status of the command (enum ionic_status_code) 1749 * @rsvd: reserved byte(s) 1750 * @features: Device features 1751 * @rsvd2: reserved byte(s) 1752 * @color: Color bit 1753 */ 1754 struct ionic_dev_setattr_comp { 1755 u8 status; 1756 u8 rsvd[3]; 1757 union { 1758 __le64 features; 1759 u8 rsvd2[11]; 1760 } __packed; 1761 u8 color; 1762 }; 1763 1764 /** 1765 * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC 1766 * @opcode: opcode 1767 * @attr: Attribute type (enum ionic_dev_attr) 1768 * @rsvd: reserved byte(s) 1769 */ 1770 struct ionic_dev_getattr_cmd { 1771 u8 opcode; 1772 u8 attr; 1773 u8 rsvd[62]; 1774 }; 1775 1776 /** 1777 * struct ionic_dev_getattr_comp - Device set attr command completion 1778 * @status: Status of the command (enum ionic_status_code) 1779 * @rsvd: reserved byte(s) 1780 * @features: Device features 1781 * @rsvd2: reserved byte(s) 1782 * @color: Color bit 1783 */ 1784 struct ionic_dev_getattr_comp { 1785 u8 status; 1786 u8 rsvd[3]; 1787 union { 1788 __le64 features; 1789 u8 rsvd2[11]; 1790 } __packed; 1791 u8 color; 1792 }; 1793 1794 /* 1795 * RSS parameters 1796 */ 1797 #define IONIC_RSS_HASH_KEY_SIZE 40 1798 1799 enum ionic_rss_hash_types { 1800 IONIC_RSS_TYPE_IPV4 = BIT(0), 1801 IONIC_RSS_TYPE_IPV4_TCP = BIT(1), 1802 IONIC_RSS_TYPE_IPV4_UDP = BIT(2), 1803 IONIC_RSS_TYPE_IPV6 = BIT(3), 1804 IONIC_RSS_TYPE_IPV6_TCP = BIT(4), 1805 IONIC_RSS_TYPE_IPV6_UDP = BIT(5), 1806 }; 1807 1808 /** 1809 * enum ionic_lif_attr - List of LIF attributes 1810 * @IONIC_LIF_ATTR_STATE: LIF state attribute 1811 * @IONIC_LIF_ATTR_NAME: LIF name attribute 1812 * @IONIC_LIF_ATTR_MTU: LIF MTU attribute 1813 * @IONIC_LIF_ATTR_MAC: LIF MAC attribute 1814 * @IONIC_LIF_ATTR_FEATURES: LIF features attribute 1815 * @IONIC_LIF_ATTR_RSS: LIF RSS attribute 1816 * @IONIC_LIF_ATTR_STATS_CTRL: LIF statistics control attribute 1817 * @IONIC_LIF_ATTR_TXSTAMP: LIF TX timestamping mode 1818 * @IONIC_LIF_ATTR_MAX: maximum attribute value 1819 */ 1820 enum ionic_lif_attr { 1821 IONIC_LIF_ATTR_STATE = 0, 1822 IONIC_LIF_ATTR_NAME = 1, 1823 IONIC_LIF_ATTR_MTU = 2, 1824 IONIC_LIF_ATTR_MAC = 3, 1825 IONIC_LIF_ATTR_FEATURES = 4, 1826 IONIC_LIF_ATTR_RSS = 5, 1827 IONIC_LIF_ATTR_STATS_CTRL = 6, 1828 IONIC_LIF_ATTR_TXSTAMP = 7, 1829 IONIC_LIF_ATTR_MAX = 255, 1830 }; 1831 1832 /** 1833 * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC 1834 * @opcode: Opcode 1835 * @attr: Attribute type (enum ionic_lif_attr) 1836 * @index: LIF index 1837 * @state: LIF state (enum ionic_lif_state) 1838 * @name: The netdev name string, 0 terminated 1839 * @mtu: Mtu 1840 * @mac: Station mac 1841 * @features: Features (enum ionic_eth_hw_features) 1842 * @rss: RSS properties 1843 * @rss.types: The hash types to enable (see rss_hash_types) 1844 * @rss.key: The hash secret key 1845 * @rss.rsvd: reserved byte(s) 1846 * @rss.addr: Address for the indirection table shared memory 1847 * @stats_ctl: stats control commands (enum ionic_stats_ctl_cmd) 1848 * @txstamp_mode: TX Timestamping Mode (enum ionic_txstamp_mode) 1849 * @rsvd: reserved byte(s) 1850 */ 1851 struct ionic_lif_setattr_cmd { 1852 u8 opcode; 1853 u8 attr; 1854 __le16 index; 1855 union { 1856 u8 state; 1857 char name[IONIC_IFNAMSIZ]; 1858 __le32 mtu; 1859 u8 mac[6]; 1860 __le64 features; 1861 struct { 1862 __le16 types; 1863 u8 key[IONIC_RSS_HASH_KEY_SIZE]; 1864 u8 rsvd[6]; 1865 __le64 addr; 1866 } rss; 1867 u8 stats_ctl; 1868 __le16 txstamp_mode; 1869 u8 rsvd[60]; 1870 } __packed; 1871 }; 1872 1873 /** 1874 * struct ionic_lif_setattr_comp - LIF set attr command completion 1875 * @status: Status of the command (enum ionic_status_code) 1876 * @rsvd: reserved byte(s) 1877 * @comp_index: Index in the descriptor ring for which this is the completion 1878 * @features: features (enum ionic_eth_hw_features) 1879 * @rsvd2: reserved byte(s) 1880 * @color: Color bit 1881 */ 1882 struct ionic_lif_setattr_comp { 1883 u8 status; 1884 u8 rsvd; 1885 __le16 comp_index; 1886 union { 1887 __le64 features; 1888 u8 rsvd2[11]; 1889 } __packed; 1890 u8 color; 1891 }; 1892 1893 /** 1894 * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC 1895 * @opcode: Opcode 1896 * @attr: Attribute type (enum ionic_lif_attr) 1897 * @index: LIF index 1898 * @rsvd: reserved byte(s) 1899 */ 1900 struct ionic_lif_getattr_cmd { 1901 u8 opcode; 1902 u8 attr; 1903 __le16 index; 1904 u8 rsvd[60]; 1905 }; 1906 1907 /** 1908 * struct ionic_lif_getattr_comp - LIF get attr command completion 1909 * @status: Status of the command (enum ionic_status_code) 1910 * @rsvd: reserved byte(s) 1911 * @comp_index: Index in the descriptor ring for which this is the completion 1912 * @state: LIF state (enum ionic_lif_state) 1913 * @mtu: Mtu 1914 * @mac: Station mac 1915 * @features: Features (enum ionic_eth_hw_features) 1916 * @txstamp_mode: TX Timestamping Mode (enum ionic_txstamp_mode) 1917 * @rsvd2: reserved byte(s) 1918 * @color: Color bit 1919 */ 1920 struct ionic_lif_getattr_comp { 1921 u8 status; 1922 u8 rsvd; 1923 __le16 comp_index; 1924 union { 1925 u8 state; 1926 __le32 mtu; 1927 u8 mac[6]; 1928 __le64 features; 1929 __le16 txstamp_mode; 1930 u8 rsvd2[11]; 1931 } __packed; 1932 u8 color; 1933 }; 1934 1935 /** 1936 * struct ionic_lif_setphc_cmd - Set LIF PTP Hardware Clock 1937 * @opcode: Opcode 1938 * @rsvd1: reserved byte(s) 1939 * @lif_index: LIF index 1940 * @rsvd2: reserved byte(s) 1941 * @tick: Hardware stamp tick of an instant in time. 1942 * @nsec: Nanosecond stamp of the same instant. 1943 * @frac: Fractional nanoseconds at the same instant. 1944 * @mult: Cycle to nanosecond multiplier. 1945 * @shift: Cycle to nanosecond divisor (power of two). 1946 * @rsvd3: reserved byte(s) 1947 */ 1948 struct ionic_lif_setphc_cmd { 1949 u8 opcode; 1950 u8 rsvd1; 1951 __le16 lif_index; 1952 u8 rsvd2[4]; 1953 __le64 tick; 1954 __le64 nsec; 1955 __le64 frac; 1956 __le32 mult; 1957 __le32 shift; 1958 u8 rsvd3[24]; 1959 }; 1960 1961 enum ionic_rx_mode { 1962 IONIC_RX_MODE_F_UNICAST = BIT(0), 1963 IONIC_RX_MODE_F_MULTICAST = BIT(1), 1964 IONIC_RX_MODE_F_BROADCAST = BIT(2), 1965 IONIC_RX_MODE_F_PROMISC = BIT(3), 1966 IONIC_RX_MODE_F_ALLMULTI = BIT(4), 1967 IONIC_RX_MODE_F_RDMA_SNIFFER = BIT(5), 1968 }; 1969 1970 /** 1971 * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command 1972 * @opcode: opcode 1973 * @rsvd: reserved byte(s) 1974 * @lif_index: LIF index 1975 * @rx_mode: Rx mode flags: 1976 * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets 1977 * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets 1978 * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets 1979 * IONIC_RX_MODE_F_PROMISC: Accept any packets 1980 * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets 1981 * IONIC_RX_MODE_F_RDMA_SNIFFER: Sniff RDMA packets 1982 * @rsvd2: reserved byte(s) 1983 */ 1984 struct ionic_rx_mode_set_cmd { 1985 u8 opcode; 1986 u8 rsvd; 1987 __le16 lif_index; 1988 __le16 rx_mode; 1989 __le16 rsvd2[29]; 1990 }; 1991 1992 typedef struct ionic_admin_comp ionic_rx_mode_set_comp; 1993 1994 enum ionic_rx_filter_match_type { 1995 IONIC_RX_FILTER_MATCH_VLAN = 0x0, 1996 IONIC_RX_FILTER_MATCH_MAC = 0x1, 1997 IONIC_RX_FILTER_MATCH_MAC_VLAN = 0x2, 1998 IONIC_RX_FILTER_STEER_PKTCLASS = 0x10, 1999 }; 2000 2001 /** 2002 * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command 2003 * @opcode: opcode 2004 * @qtype: Queue type 2005 * @lif_index: LIF index 2006 * @qid: Queue ID 2007 * @match: Rx filter match type (see IONIC_RX_FILTER_MATCH_xxx) 2008 * @vlan: VLAN filter 2009 * @vlan.vlan: VLAN ID 2010 * @mac: MAC filter 2011 * @mac.addr: MAC address (network-byte order) 2012 * @mac_vlan: MACVLAN filter 2013 * @mac_vlan.vlan: VLAN ID 2014 * @mac_vlan.addr: MAC address (network-byte order) 2015 * @pkt_class: Packet classification filter 2016 * @rsvd: reserved byte(s) 2017 */ 2018 struct ionic_rx_filter_add_cmd { 2019 u8 opcode; 2020 u8 qtype; 2021 __le16 lif_index; 2022 __le32 qid; 2023 __le16 match; 2024 union { 2025 struct { 2026 __le16 vlan; 2027 } vlan; 2028 struct { 2029 u8 addr[6]; 2030 } mac; 2031 struct { 2032 __le16 vlan; 2033 u8 addr[6]; 2034 } mac_vlan; 2035 __le64 pkt_class; 2036 u8 rsvd[54]; 2037 } __packed; 2038 }; 2039 2040 /** 2041 * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion 2042 * @status: Status of the command (enum ionic_status_code) 2043 * @rsvd: reserved byte(s) 2044 * @comp_index: Index in the descriptor ring for which this is the completion 2045 * @filter_id: Filter ID 2046 * @rsvd2: reserved byte(s) 2047 * @color: Color bit 2048 */ 2049 struct ionic_rx_filter_add_comp { 2050 u8 status; 2051 u8 rsvd; 2052 __le16 comp_index; 2053 __le32 filter_id; 2054 u8 rsvd2[7]; 2055 u8 color; 2056 }; 2057 2058 /** 2059 * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command 2060 * @opcode: opcode 2061 * @rsvd: reserved byte(s) 2062 * @lif_index: LIF index 2063 * @filter_id: Filter ID 2064 * @rsvd2: reserved byte(s) 2065 */ 2066 struct ionic_rx_filter_del_cmd { 2067 u8 opcode; 2068 u8 rsvd; 2069 __le16 lif_index; 2070 __le32 filter_id; 2071 u8 rsvd2[56]; 2072 }; 2073 2074 typedef struct ionic_admin_comp ionic_rx_filter_del_comp; 2075 2076 enum ionic_vf_attr { 2077 IONIC_VF_ATTR_SPOOFCHK = 1, 2078 IONIC_VF_ATTR_TRUST = 2, 2079 IONIC_VF_ATTR_MAC = 3, 2080 IONIC_VF_ATTR_LINKSTATE = 4, 2081 IONIC_VF_ATTR_VLAN = 5, 2082 IONIC_VF_ATTR_RATE = 6, 2083 IONIC_VF_ATTR_STATSADDR = 7, 2084 }; 2085 2086 /** 2087 * enum ionic_vf_link_status - Virtual Function link status 2088 * @IONIC_VF_LINK_STATUS_AUTO: Use link state of the uplink 2089 * @IONIC_VF_LINK_STATUS_UP: Link always up 2090 * @IONIC_VF_LINK_STATUS_DOWN: Link always down 2091 */ 2092 enum ionic_vf_link_status { 2093 IONIC_VF_LINK_STATUS_AUTO = 0, 2094 IONIC_VF_LINK_STATUS_UP = 1, 2095 IONIC_VF_LINK_STATUS_DOWN = 2, 2096 }; 2097 2098 /** 2099 * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC 2100 * @opcode: Opcode 2101 * @attr: Attribute type (enum ionic_vf_attr) 2102 * @vf_index: VF index 2103 * @macaddr: mac address 2104 * @vlanid: vlan ID 2105 * @maxrate: max Tx rate in Mbps 2106 * @spoofchk: enable address spoof checking 2107 * @trust: enable VF trust 2108 * @linkstate: set link up or down 2109 * @stats_pa: set DMA address for VF stats 2110 * @pad: reserved byte(s) 2111 */ 2112 struct ionic_vf_setattr_cmd { 2113 u8 opcode; 2114 u8 attr; 2115 __le16 vf_index; 2116 union { 2117 u8 macaddr[6]; 2118 __le16 vlanid; 2119 __le32 maxrate; 2120 u8 spoofchk; 2121 u8 trust; 2122 u8 linkstate; 2123 __le64 stats_pa; 2124 u8 pad[60]; 2125 } __packed; 2126 }; 2127 2128 struct ionic_vf_setattr_comp { 2129 u8 status; 2130 u8 attr; 2131 __le16 vf_index; 2132 __le16 comp_index; 2133 u8 rsvd[9]; 2134 u8 color; 2135 }; 2136 2137 /** 2138 * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC 2139 * @opcode: Opcode 2140 * @attr: Attribute type (enum ionic_vf_attr) 2141 * @vf_index: VF index 2142 * @rsvd: reserved byte(s) 2143 */ 2144 struct ionic_vf_getattr_cmd { 2145 u8 opcode; 2146 u8 attr; 2147 __le16 vf_index; 2148 u8 rsvd[60]; 2149 }; 2150 2151 struct ionic_vf_getattr_comp { 2152 u8 status; 2153 u8 attr; 2154 __le16 vf_index; 2155 union { 2156 u8 macaddr[6]; 2157 __le16 vlanid; 2158 __le32 maxrate; 2159 u8 spoofchk; 2160 u8 trust; 2161 u8 linkstate; 2162 __le64 stats_pa; 2163 u8 pad[11]; 2164 } __packed; 2165 u8 color; 2166 }; 2167 2168 enum ionic_vf_ctrl_opcode { 2169 IONIC_VF_CTRL_START_ALL = 0, 2170 IONIC_VF_CTRL_START = 1, 2171 }; 2172 2173 /** 2174 * struct ionic_vf_ctrl_cmd - VF control command 2175 * @opcode: Opcode for the command 2176 * @ctrl_opcode: VF control operation type 2177 * @vf_index: VF Index. It is unused if op START_ALL is used. 2178 */ 2179 struct ionic_vf_ctrl_cmd { 2180 u8 opcode; 2181 u8 ctrl_opcode; 2182 __le16 vf_index; 2183 /* private: */ 2184 u8 rsvd1[60]; 2185 }; 2186 2187 /** 2188 * struct ionic_vf_ctrl_comp - VF_CTRL command completion. 2189 * @status: Status of the command (enum ionic_status_code) 2190 */ 2191 struct ionic_vf_ctrl_comp { 2192 u8 status; 2193 /* private: */ 2194 u8 rsvd[15]; 2195 }; 2196 2197 /** 2198 * struct ionic_qos_identify_cmd - QoS identify command 2199 * @opcode: opcode 2200 * @ver: Highest version of identify supported by driver 2201 * @rsvd: reserved byte(s) 2202 */ 2203 struct ionic_qos_identify_cmd { 2204 u8 opcode; 2205 u8 ver; 2206 u8 rsvd[62]; 2207 }; 2208 2209 /** 2210 * struct ionic_qos_identify_comp - QoS identify command completion 2211 * @status: Status of the command (enum ionic_status_code) 2212 * @ver: Version of identify returned by device 2213 * @rsvd: reserved byte(s) 2214 */ 2215 struct ionic_qos_identify_comp { 2216 u8 status; 2217 u8 ver; 2218 u8 rsvd[14]; 2219 }; 2220 2221 #define IONIC_QOS_TC_MAX 8 2222 #define IONIC_QOS_ALL_TC 0xFF 2223 /* Capri max supported, should be renamed. */ 2224 #define IONIC_QOS_CLASS_MAX 7 2225 #define IONIC_QOS_PCP_MAX 8 2226 #define IONIC_QOS_CLASS_NAME_SZ 32 2227 #define IONIC_QOS_DSCP_MAX 64 2228 #define IONIC_QOS_ALL_PCP 0xFF 2229 #define IONIC_DSCP_BLOCK_SIZE 8 2230 2231 /* 2232 * enum ionic_qos_class 2233 */ 2234 enum ionic_qos_class { 2235 IONIC_QOS_CLASS_DEFAULT = 0, 2236 IONIC_QOS_CLASS_USER_DEFINED_1 = 1, 2237 IONIC_QOS_CLASS_USER_DEFINED_2 = 2, 2238 IONIC_QOS_CLASS_USER_DEFINED_3 = 3, 2239 IONIC_QOS_CLASS_USER_DEFINED_4 = 4, 2240 IONIC_QOS_CLASS_USER_DEFINED_5 = 5, 2241 IONIC_QOS_CLASS_USER_DEFINED_6 = 6, 2242 }; 2243 2244 /** 2245 * enum ionic_qos_class_type - Traffic classification criteria 2246 * @IONIC_QOS_CLASS_TYPE_NONE: No QoS 2247 * @IONIC_QOS_CLASS_TYPE_PCP: Dot1Q PCP 2248 * @IONIC_QOS_CLASS_TYPE_DSCP: IP DSCP 2249 */ 2250 enum ionic_qos_class_type { 2251 IONIC_QOS_CLASS_TYPE_NONE = 0, 2252 IONIC_QOS_CLASS_TYPE_PCP = 1, 2253 IONIC_QOS_CLASS_TYPE_DSCP = 2, 2254 }; 2255 2256 /** 2257 * enum ionic_qos_sched_type - QoS class scheduling type 2258 * @IONIC_QOS_SCHED_TYPE_STRICT: Strict priority 2259 * @IONIC_QOS_SCHED_TYPE_DWRR: Deficit weighted round-robin 2260 */ 2261 enum ionic_qos_sched_type { 2262 IONIC_QOS_SCHED_TYPE_STRICT = 0, 2263 IONIC_QOS_SCHED_TYPE_DWRR = 1, 2264 }; 2265 2266 /** 2267 * union ionic_qos_config - QoS configuration structure 2268 * @flags: Configuration flags 2269 * IONIC_QOS_CONFIG_F_ENABLE enable 2270 * IONIC_QOS_CONFIG_F_NO_DROP drop/nodrop 2271 * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite 2272 * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite 2273 * IONIC_QOS_CONFIG_F_NON_DISRUPTIVE Non-disruptive TC update 2274 * @sched_type: QoS class scheduling type (enum ionic_qos_sched_type) 2275 * @class_type: QoS class type (enum ionic_qos_class_type) 2276 * @pause_type: QoS pause type (enum ionic_qos_pause_type) 2277 * @name: QoS class name 2278 * @mtu: MTU of the class 2279 * @pfc_cos: Priority-Flow Control class of service 2280 * @dwrr_weight: QoS class scheduling weight 2281 * @strict_rlmt: Rate limit for strict priority scheduling 2282 * @rw_dot1q_pcp: Rewrite dot1q pcp to value (valid iff F_RW_DOT1Q_PCP) 2283 * @rw_ip_dscp: Rewrite ip dscp to value (valid iff F_RW_IP_DSCP) 2284 * @dot1q_pcp: Dot1q pcp value 2285 * @ndscp: Number of valid dscp values in the ip_dscp field 2286 * @ip_dscp: IP dscp values 2287 * @words: word access to struct contents 2288 */ 2289 union ionic_qos_config { 2290 struct { 2291 #define IONIC_QOS_CONFIG_F_ENABLE BIT(0) 2292 #define IONIC_QOS_CONFIG_F_NO_DROP BIT(1) 2293 /* Used to rewrite PCP or DSCP value. */ 2294 #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2) 2295 #define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3) 2296 /* Non-disruptive TC update */ 2297 #define IONIC_QOS_CONFIG_F_NON_DISRUPTIVE BIT(4) 2298 u8 flags; 2299 u8 sched_type; 2300 u8 class_type; 2301 u8 pause_type; 2302 char name[IONIC_QOS_CLASS_NAME_SZ]; 2303 __le32 mtu; 2304 /* flow control */ 2305 u8 pfc_cos; 2306 /* scheduler */ 2307 union { 2308 u8 dwrr_weight; 2309 __le64 strict_rlmt; 2310 }; 2311 /* marking */ 2312 /* Used to rewrite PCP or DSCP value. */ 2313 union { 2314 u8 rw_dot1q_pcp; 2315 u8 rw_ip_dscp; 2316 }; 2317 /* classification */ 2318 union { 2319 u8 dot1q_pcp; 2320 struct { 2321 u8 ndscp; 2322 u8 ip_dscp[IONIC_QOS_DSCP_MAX]; 2323 }; 2324 }; 2325 }; 2326 __le32 words[64]; 2327 }; 2328 2329 /** 2330 * union ionic_qos_identity - QoS identity structure 2331 * @version: Version of the identify structure 2332 * @type: QoS system type 2333 * @rsvd: reserved byte(s) 2334 * @config: Current configuration of classes 2335 * @words: word access to struct contents 2336 */ 2337 union ionic_qos_identity { 2338 struct { 2339 u8 version; 2340 u8 type; 2341 u8 rsvd[62]; 2342 union ionic_qos_config config[IONIC_QOS_CLASS_MAX]; 2343 }; 2344 __le32 words[478]; 2345 }; 2346 2347 /** 2348 * struct ionic_qos_init_cmd - QoS config init command 2349 * @opcode: Opcode 2350 * @group: QoS class id 2351 * @rsvd: reserved byte(s) 2352 * @info_pa: destination address for qos info 2353 * @rsvd1: reserved byte(s) 2354 */ 2355 struct ionic_qos_init_cmd { 2356 u8 opcode; 2357 u8 group; 2358 u8 rsvd[6]; 2359 __le64 info_pa; 2360 u8 rsvd1[48]; 2361 }; 2362 2363 typedef struct ionic_admin_comp ionic_qos_init_comp; 2364 2365 /** 2366 * struct ionic_qos_reset_cmd - QoS config reset command 2367 * @opcode: Opcode 2368 * @group: QoS class id 2369 * @rsvd: reserved byte(s) 2370 */ 2371 struct ionic_qos_reset_cmd { 2372 u8 opcode; 2373 u8 group; 2374 u8 rsvd[62]; 2375 }; 2376 2377 /** 2378 * struct ionic_qos_clear_stats_cmd - Qos config reset command 2379 * @opcode: Opcode 2380 * @group_bitmap: bitmap of groups to be cleared 2381 * @rsvd: reserved byte(s) 2382 */ 2383 struct ionic_qos_clear_stats_cmd { 2384 u8 opcode; 2385 u8 group_bitmap; 2386 u8 rsvd[62]; 2387 }; 2388 2389 typedef struct ionic_admin_comp ionic_qos_reset_comp; 2390 2391 /** 2392 * struct ionic_fw_download_cmd - Firmware download command 2393 * @opcode: opcode 2394 * @rsvd: reserved byte(s) 2395 * @addr: dma address of the firmware buffer 2396 * @offset: offset of the firmware buffer within the full image 2397 * @length: number of valid bytes in the firmware buffer 2398 */ 2399 struct ionic_fw_download_cmd { 2400 u8 opcode; 2401 u8 rsvd[3]; 2402 __le32 offset; 2403 __le64 addr; 2404 __le32 length; 2405 }; 2406 2407 typedef struct ionic_admin_comp ionic_fw_download_comp; 2408 2409 /** 2410 * enum ionic_fw_control_oper - FW control operations 2411 * @IONIC_FW_RESET: Reset firmware 2412 * @IONIC_FW_INSTALL: Install firmware 2413 * @IONIC_FW_ACTIVATE: Activate firmware 2414 * @IONIC_FW_INSTALL_ASYNC: Install firmware asynchronously 2415 * @IONIC_FW_INSTALL_STATUS: Firmware installation status 2416 * @IONIC_FW_ACTIVATE_ASYNC: Activate firmware asynchronously 2417 * @IONIC_FW_ACTIVATE_STATUS: Firmware activate status 2418 * @IONIC_FW_UPDATE_CLEANUP: Clean up after an interrupted fw update 2419 */ 2420 enum ionic_fw_control_oper { 2421 IONIC_FW_RESET = 0, 2422 IONIC_FW_INSTALL = 1, 2423 IONIC_FW_ACTIVATE = 2, 2424 IONIC_FW_INSTALL_ASYNC = 3, 2425 IONIC_FW_INSTALL_STATUS = 4, 2426 IONIC_FW_ACTIVATE_ASYNC = 5, 2427 IONIC_FW_ACTIVATE_STATUS = 6, 2428 IONIC_FW_UPDATE_CLEANUP = 7, 2429 }; 2430 2431 /** 2432 * struct ionic_fw_control_cmd - Firmware control command 2433 * @opcode: opcode 2434 * @rsvd: reserved byte(s) 2435 * @oper: firmware control operation (enum ionic_fw_control_oper) 2436 * @slot: slot to activate 2437 * @rsvd1: reserved byte(s) 2438 */ 2439 struct ionic_fw_control_cmd { 2440 u8 opcode; 2441 u8 rsvd[3]; 2442 u8 oper; 2443 u8 slot; 2444 u8 rsvd1[58]; 2445 }; 2446 2447 /** 2448 * struct ionic_fw_control_comp - Firmware control copletion 2449 * @status: Status of the command (enum ionic_status_code) 2450 * @rsvd: reserved byte(s) 2451 * @comp_index: Index in the descriptor ring for which this is the completion 2452 * @slot: Slot where the firmware was installed 2453 * @rsvd1: reserved byte(s) 2454 * @color: Color bit 2455 */ 2456 struct ionic_fw_control_comp { 2457 u8 status; 2458 u8 rsvd; 2459 __le16 comp_index; 2460 u8 slot; 2461 u8 rsvd1[10]; 2462 u8 color; 2463 }; 2464 2465 /****************************************************************** 2466 ******************* RDMA Commands ******************************** 2467 ******************************************************************/ 2468 2469 /** 2470 * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd 2471 * @opcode: opcode 2472 * @rsvd: reserved byte(s) 2473 * @lif_index: LIF index 2474 * @rsvd2: reserved byte(s) 2475 * 2476 * There is no RDMA specific dev command completion struct. Completion uses 2477 * the common struct ionic_admin_comp. Only the status is indicated. 2478 * Nonzero status means the LIF does not support RDMA. 2479 **/ 2480 struct ionic_rdma_reset_cmd { 2481 u8 opcode; 2482 u8 rsvd; 2483 __le16 lif_index; 2484 u8 rsvd2[60]; 2485 }; 2486 2487 /** 2488 * struct ionic_rdma_queue_cmd - Create RDMA Queue command 2489 * @opcode: opcode, 52, 53 2490 * @rsvd: reserved byte(s) 2491 * @lif_index: LIF index 2492 * @qid_ver: (qid | (RDMA version << 24)) 2493 * @cid: intr, eq_id, or cq_id 2494 * @dbid: doorbell page id 2495 * @depth_log2: log base two of queue depth 2496 * @stride_log2: log base two of queue stride 2497 * @dma_addr: address of the queue memory 2498 * @rsvd2: reserved byte(s) 2499 * 2500 * The same command struct is used to create an RDMA event queue, completion 2501 * queue, or RDMA admin queue. The cid is an interrupt number for an event 2502 * queue, an event queue id for a completion queue, or a completion queue id 2503 * for an RDMA admin queue. 2504 * 2505 * The queue created via a dev command must be contiguous in dma space. 2506 * 2507 * The dev commands are intended only to be used during driver initialization, 2508 * to create queues supporting the RDMA admin queue. Other queues, and other 2509 * types of RDMA resources like memory regions, will be created and registered 2510 * via the RDMA admin queue, and will support a more complete interface 2511 * providing scatter gather lists for larger, scattered queue buffers and 2512 * memory registration. 2513 * 2514 * There is no RDMA specific dev command completion struct. Completion uses 2515 * the common struct ionic_admin_comp. Only the status is indicated. 2516 **/ 2517 struct ionic_rdma_queue_cmd { 2518 u8 opcode; 2519 u8 rsvd; 2520 __le16 lif_index; 2521 __le32 qid_ver; 2522 __le32 cid; 2523 __le16 dbid; 2524 u8 depth_log2; 2525 u8 stride_log2; 2526 __le64 dma_addr; 2527 u8 rsvd2[40]; 2528 }; 2529 2530 /****************************************************************** 2531 ******************* Notify Events ******************************** 2532 ******************************************************************/ 2533 2534 /** 2535 * struct ionic_notifyq_event - Generic event reporting structure 2536 * @eid: event number 2537 * @ecode: event code 2538 * @data: unspecified data about the event 2539 * 2540 * This is the generic event report struct from which the other 2541 * actual events will be formed. 2542 */ 2543 struct ionic_notifyq_event { 2544 __le64 eid; 2545 __le16 ecode; 2546 u8 data[54]; 2547 }; 2548 2549 /** 2550 * struct ionic_link_change_event - Link change event notification 2551 * @eid: event number 2552 * @ecode: event code = IONIC_EVENT_LINK_CHANGE 2553 * @link_status: link up/down, with error bits (enum ionic_port_status) 2554 * @link_speed: speed of the network link 2555 * @rsvd: reserved byte(s) 2556 * 2557 * Sent when the network link state changes between UP and DOWN 2558 */ 2559 struct ionic_link_change_event { 2560 __le64 eid; 2561 __le16 ecode; 2562 __le16 link_status; 2563 __le32 link_speed; /* units of 1Mbps: e.g. 10000 = 10Gbps */ 2564 u8 rsvd[48]; 2565 }; 2566 2567 /** 2568 * struct ionic_reset_event - Reset event notification 2569 * @eid: event number 2570 * @ecode: event code = IONIC_EVENT_RESET 2571 * @reset_code: reset type 2572 * @state: 0=pending, 1=complete, 2=error 2573 * @rsvd: reserved byte(s) 2574 * 2575 * Sent when the NIC or some subsystem is going to be or 2576 * has been reset. 2577 */ 2578 struct ionic_reset_event { 2579 __le64 eid; 2580 __le16 ecode; 2581 u8 reset_code; 2582 u8 state; 2583 u8 rsvd[52]; 2584 }; 2585 2586 /** 2587 * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health 2588 * @eid: event number 2589 * @ecode: event code = IONIC_EVENT_HEARTBEAT 2590 * @rsvd: reserved byte(s) 2591 */ 2592 struct ionic_heartbeat_event { 2593 __le64 eid; 2594 __le16 ecode; 2595 u8 rsvd[54]; 2596 }; 2597 2598 /** 2599 * struct ionic_log_event - Sent to notify the driver of an internal error 2600 * @eid: event number 2601 * @ecode: event code = IONIC_EVENT_LOG 2602 * @data: log data 2603 */ 2604 struct ionic_log_event { 2605 __le64 eid; 2606 __le16 ecode; 2607 u8 data[54]; 2608 }; 2609 2610 /** 2611 * struct ionic_xcvr_event - Transceiver change event 2612 * @eid: event number 2613 * @ecode: event code = IONIC_EVENT_XCVR 2614 * @rsvd: reserved byte(s) 2615 */ 2616 struct ionic_xcvr_event { 2617 __le64 eid; 2618 __le16 ecode; 2619 u8 rsvd[54]; 2620 }; 2621 2622 /* 2623 * struct ionic_port_stats - Port statistics structure 2624 */ 2625 struct ionic_port_stats { 2626 __le64 frames_rx_ok; 2627 __le64 frames_rx_all; 2628 __le64 frames_rx_bad_fcs; 2629 __le64 frames_rx_bad_all; 2630 __le64 octets_rx_ok; 2631 __le64 octets_rx_all; 2632 __le64 frames_rx_unicast; 2633 __le64 frames_rx_multicast; 2634 __le64 frames_rx_broadcast; 2635 __le64 frames_rx_pause; 2636 __le64 frames_rx_bad_length; 2637 __le64 frames_rx_undersized; 2638 __le64 frames_rx_oversized; 2639 __le64 frames_rx_fragments; 2640 __le64 frames_rx_jabber; 2641 __le64 frames_rx_pripause; 2642 __le64 frames_rx_stomped_crc; 2643 __le64 frames_rx_too_long; 2644 __le64 frames_rx_vlan_good; 2645 __le64 frames_rx_dropped; 2646 __le64 frames_rx_less_than_64b; 2647 __le64 frames_rx_64b; 2648 __le64 frames_rx_65b_127b; 2649 __le64 frames_rx_128b_255b; 2650 __le64 frames_rx_256b_511b; 2651 __le64 frames_rx_512b_1023b; 2652 __le64 frames_rx_1024b_1518b; 2653 __le64 frames_rx_1519b_2047b; 2654 __le64 frames_rx_2048b_4095b; 2655 __le64 frames_rx_4096b_8191b; 2656 __le64 frames_rx_8192b_9215b; 2657 __le64 frames_rx_other; 2658 __le64 frames_tx_ok; 2659 __le64 frames_tx_all; 2660 __le64 frames_tx_bad; 2661 __le64 octets_tx_ok; 2662 __le64 octets_tx_total; 2663 __le64 frames_tx_unicast; 2664 __le64 frames_tx_multicast; 2665 __le64 frames_tx_broadcast; 2666 __le64 frames_tx_pause; 2667 __le64 frames_tx_pripause; 2668 __le64 frames_tx_vlan; 2669 __le64 frames_tx_less_than_64b; 2670 __le64 frames_tx_64b; 2671 __le64 frames_tx_65b_127b; 2672 __le64 frames_tx_128b_255b; 2673 __le64 frames_tx_256b_511b; 2674 __le64 frames_tx_512b_1023b; 2675 __le64 frames_tx_1024b_1518b; 2676 __le64 frames_tx_1519b_2047b; 2677 __le64 frames_tx_2048b_4095b; 2678 __le64 frames_tx_4096b_8191b; 2679 __le64 frames_tx_8192b_9215b; 2680 __le64 frames_tx_other; 2681 __le64 frames_tx_pri_0; 2682 __le64 frames_tx_pri_1; 2683 __le64 frames_tx_pri_2; 2684 __le64 frames_tx_pri_3; 2685 __le64 frames_tx_pri_4; 2686 __le64 frames_tx_pri_5; 2687 __le64 frames_tx_pri_6; 2688 __le64 frames_tx_pri_7; 2689 __le64 frames_rx_pri_0; 2690 __le64 frames_rx_pri_1; 2691 __le64 frames_rx_pri_2; 2692 __le64 frames_rx_pri_3; 2693 __le64 frames_rx_pri_4; 2694 __le64 frames_rx_pri_5; 2695 __le64 frames_rx_pri_6; 2696 __le64 frames_rx_pri_7; 2697 __le64 tx_pripause_0_1us_count; 2698 __le64 tx_pripause_1_1us_count; 2699 __le64 tx_pripause_2_1us_count; 2700 __le64 tx_pripause_3_1us_count; 2701 __le64 tx_pripause_4_1us_count; 2702 __le64 tx_pripause_5_1us_count; 2703 __le64 tx_pripause_6_1us_count; 2704 __le64 tx_pripause_7_1us_count; 2705 __le64 rx_pripause_0_1us_count; 2706 __le64 rx_pripause_1_1us_count; 2707 __le64 rx_pripause_2_1us_count; 2708 __le64 rx_pripause_3_1us_count; 2709 __le64 rx_pripause_4_1us_count; 2710 __le64 rx_pripause_5_1us_count; 2711 __le64 rx_pripause_6_1us_count; 2712 __le64 rx_pripause_7_1us_count; 2713 __le64 rx_pause_1us_count; 2714 __le64 frames_tx_truncated; 2715 }; 2716 2717 struct ionic_mgmt_port_stats { 2718 __le64 frames_rx_ok; 2719 __le64 frames_rx_all; 2720 __le64 frames_rx_bad_fcs; 2721 __le64 frames_rx_bad_all; 2722 __le64 octets_rx_ok; 2723 __le64 octets_rx_all; 2724 __le64 frames_rx_unicast; 2725 __le64 frames_rx_multicast; 2726 __le64 frames_rx_broadcast; 2727 __le64 frames_rx_pause; 2728 __le64 frames_rx_bad_length; 2729 __le64 frames_rx_undersized; 2730 __le64 frames_rx_oversized; 2731 __le64 frames_rx_fragments; 2732 __le64 frames_rx_jabber; 2733 __le64 frames_rx_64b; 2734 __le64 frames_rx_65b_127b; 2735 __le64 frames_rx_128b_255b; 2736 __le64 frames_rx_256b_511b; 2737 __le64 frames_rx_512b_1023b; 2738 __le64 frames_rx_1024b_1518b; 2739 __le64 frames_rx_gt_1518b; 2740 __le64 frames_rx_fifo_full; 2741 __le64 frames_tx_ok; 2742 __le64 frames_tx_all; 2743 __le64 frames_tx_bad; 2744 __le64 octets_tx_ok; 2745 __le64 octets_tx_total; 2746 __le64 frames_tx_unicast; 2747 __le64 frames_tx_multicast; 2748 __le64 frames_tx_broadcast; 2749 __le64 frames_tx_pause; 2750 }; 2751 2752 enum ionic_pb_buffer_drop_stats { 2753 IONIC_BUFFER_INTRINSIC_DROP = 0, 2754 IONIC_BUFFER_DISCARDED, 2755 IONIC_BUFFER_ADMITTED, 2756 IONIC_BUFFER_OUT_OF_CELLS_DROP, 2757 IONIC_BUFFER_OUT_OF_CELLS_DROP_2, 2758 IONIC_BUFFER_OUT_OF_CREDIT_DROP, 2759 IONIC_BUFFER_TRUNCATION_DROP, 2760 IONIC_BUFFER_PORT_DISABLED_DROP, 2761 IONIC_BUFFER_COPY_TO_CPU_TAIL_DROP, 2762 IONIC_BUFFER_SPAN_TAIL_DROP, 2763 IONIC_BUFFER_MIN_SIZE_VIOLATION_DROP, 2764 IONIC_BUFFER_ENQUEUE_ERROR_DROP, 2765 IONIC_BUFFER_INVALID_PORT_DROP, 2766 IONIC_BUFFER_INVALID_OUTPUT_QUEUE_DROP, 2767 IONIC_BUFFER_DROP_MAX, 2768 }; 2769 2770 enum ionic_oflow_drop_stats { 2771 IONIC_OFLOW_OCCUPANCY_DROP, 2772 IONIC_OFLOW_EMERGENCY_STOP_DROP, 2773 IONIC_OFLOW_WRITE_BUFFER_ACK_FILL_UP_DROP, 2774 IONIC_OFLOW_WRITE_BUFFER_ACK_FULL_DROP, 2775 IONIC_OFLOW_WRITE_BUFFER_FULL_DROP, 2776 IONIC_OFLOW_CONTROL_FIFO_FULL_DROP, 2777 IONIC_OFLOW_DROP_MAX, 2778 }; 2779 2780 /* struct ionic_port_pb_stats - packet buffers system stats 2781 * uses ionic_pb_buffer_drop_stats for drop_counts[] 2782 */ 2783 struct ionic_port_pb_stats { 2784 __le64 sop_count_in; 2785 __le64 eop_count_in; 2786 __le64 sop_count_out; 2787 __le64 eop_count_out; 2788 __le64 drop_counts[IONIC_BUFFER_DROP_MAX]; 2789 __le64 input_queue_buffer_occupancy[IONIC_QOS_TC_MAX]; 2790 __le64 input_queue_port_monitor[IONIC_QOS_TC_MAX]; 2791 __le64 output_queue_port_monitor[IONIC_QOS_TC_MAX]; 2792 __le64 oflow_drop_counts[IONIC_OFLOW_DROP_MAX]; 2793 __le64 input_queue_good_pkts_in[IONIC_QOS_TC_MAX]; 2794 __le64 input_queue_good_pkts_out[IONIC_QOS_TC_MAX]; 2795 __le64 input_queue_err_pkts_in[IONIC_QOS_TC_MAX]; 2796 __le64 input_queue_fifo_depth[IONIC_QOS_TC_MAX]; 2797 __le64 input_queue_max_fifo_depth[IONIC_QOS_TC_MAX]; 2798 __le64 input_queue_peak_occupancy[IONIC_QOS_TC_MAX]; 2799 __le64 output_queue_buffer_occupancy[IONIC_QOS_TC_MAX]; 2800 }; 2801 2802 /** 2803 * struct ionic_port_identity - port identity structure 2804 * @version: identity structure version 2805 * @type: type of port (enum ionic_port_type) 2806 * @num_lanes: number of lanes for the port 2807 * @autoneg: autoneg supported 2808 * @min_frame_size: minimum frame size supported 2809 * @max_frame_size: maximum frame size supported 2810 * @fec_type: supported fec types 2811 * @pause_type: supported pause types 2812 * @loopback_mode: supported loopback mode 2813 * @speeds: supported speeds 2814 * @rsvd2: reserved byte(s) 2815 * @config: current port configuration 2816 * @words: word access to struct contents 2817 */ 2818 union ionic_port_identity { 2819 struct { 2820 u8 version; 2821 u8 type; 2822 u8 num_lanes; 2823 u8 autoneg; 2824 __le32 min_frame_size; 2825 __le32 max_frame_size; 2826 u8 fec_type[4]; 2827 u8 pause_type[2]; 2828 u8 loopback_mode[2]; 2829 __le32 speeds[16]; 2830 u8 rsvd2[44]; 2831 union ionic_port_config config; 2832 }; 2833 __le32 words[478]; 2834 }; 2835 2836 /** 2837 * struct ionic_port_info - port info structure 2838 * @config: Port configuration data 2839 * @status: Port status data 2840 * @stats: Port statistics data 2841 * @mgmt_stats: Port management statistics data 2842 * @rsvd: reserved byte(s) 2843 * @pb_stats: uplink pb drop stats 2844 */ 2845 struct ionic_port_info { 2846 union ionic_port_config config; 2847 struct ionic_port_status status; 2848 union { 2849 struct ionic_port_stats stats; 2850 struct ionic_mgmt_port_stats mgmt_stats; 2851 }; 2852 /* room for pb_stats to start at 2k offset */ 2853 u8 rsvd[760]; 2854 struct ionic_port_pb_stats pb_stats; 2855 }; 2856 2857 /* 2858 * struct ionic_lif_stats - LIF statistics structure 2859 */ 2860 struct ionic_lif_stats { 2861 /* RX */ 2862 __le64 rx_ucast_bytes; 2863 __le64 rx_ucast_packets; 2864 __le64 rx_mcast_bytes; 2865 __le64 rx_mcast_packets; 2866 __le64 rx_bcast_bytes; 2867 __le64 rx_bcast_packets; 2868 __le64 rsvd0; 2869 __le64 rsvd1; 2870 /* RX drops */ 2871 __le64 rx_ucast_drop_bytes; 2872 __le64 rx_ucast_drop_packets; 2873 __le64 rx_mcast_drop_bytes; 2874 __le64 rx_mcast_drop_packets; 2875 __le64 rx_bcast_drop_bytes; 2876 __le64 rx_bcast_drop_packets; 2877 __le64 rx_dma_error; 2878 __le64 rsvd2; 2879 /* TX */ 2880 __le64 tx_ucast_bytes; 2881 __le64 tx_ucast_packets; 2882 __le64 tx_mcast_bytes; 2883 __le64 tx_mcast_packets; 2884 __le64 tx_bcast_bytes; 2885 __le64 tx_bcast_packets; 2886 __le64 rsvd3; 2887 __le64 rsvd4; 2888 /* TX drops */ 2889 __le64 tx_ucast_drop_bytes; 2890 __le64 tx_ucast_drop_packets; 2891 __le64 tx_mcast_drop_bytes; 2892 __le64 tx_mcast_drop_packets; 2893 __le64 tx_bcast_drop_bytes; 2894 __le64 tx_bcast_drop_packets; 2895 __le64 tx_dma_error; 2896 __le64 rsvd5; 2897 /* Rx Queue/Ring drops */ 2898 __le64 rx_queue_disabled; 2899 __le64 rx_queue_empty; 2900 __le64 rx_queue_error; 2901 __le64 rx_desc_fetch_error; 2902 __le64 rx_desc_data_error; 2903 __le64 rsvd6; 2904 __le64 rsvd7; 2905 __le64 rsvd8; 2906 /* Tx Queue/Ring drops */ 2907 __le64 tx_queue_disabled; 2908 __le64 tx_queue_error; 2909 __le64 tx_desc_fetch_error; 2910 __le64 tx_desc_data_error; 2911 __le64 tx_queue_empty; 2912 __le64 rsvd10; 2913 __le64 rsvd11; 2914 __le64 rsvd12; 2915 2916 /* RDMA/ROCE TX */ 2917 __le64 tx_rdma_ucast_bytes; 2918 __le64 tx_rdma_ucast_packets; 2919 __le64 tx_rdma_mcast_bytes; 2920 __le64 tx_rdma_mcast_packets; 2921 __le64 tx_rdma_cnp_packets; 2922 __le64 rsvd13; 2923 __le64 rsvd14; 2924 __le64 rsvd15; 2925 2926 /* RDMA/ROCE RX */ 2927 __le64 rx_rdma_ucast_bytes; 2928 __le64 rx_rdma_ucast_packets; 2929 __le64 rx_rdma_mcast_bytes; 2930 __le64 rx_rdma_mcast_packets; 2931 __le64 rx_rdma_cnp_packets; 2932 __le64 rx_rdma_ecn_packets; 2933 __le64 rsvd16; 2934 __le64 rsvd17; 2935 2936 __le64 rsvd18; 2937 __le64 rsvd19; 2938 __le64 rsvd20; 2939 __le64 rsvd21; 2940 __le64 rsvd22; 2941 __le64 rsvd23; 2942 __le64 rsvd24; 2943 __le64 rsvd25; 2944 2945 __le64 rsvd26; 2946 __le64 rsvd27; 2947 __le64 rsvd28; 2948 __le64 rsvd29; 2949 __le64 rsvd30; 2950 __le64 rsvd31; 2951 __le64 rsvd32; 2952 __le64 rsvd33; 2953 2954 __le64 rsvd34; 2955 __le64 rsvd35; 2956 __le64 rsvd36; 2957 __le64 rsvd37; 2958 __le64 rsvd38; 2959 __le64 rsvd39; 2960 __le64 rsvd40; 2961 __le64 rsvd41; 2962 2963 __le64 rsvd42; 2964 __le64 rsvd43; 2965 __le64 rsvd44; 2966 __le64 rsvd45; 2967 __le64 rsvd46; 2968 __le64 rsvd47; 2969 __le64 rsvd48; 2970 __le64 rsvd49; 2971 2972 /* RDMA/ROCE REQ Error/Debugs (768 - 895) */ 2973 __le64 rdma_req_rx_pkt_seq_err; 2974 __le64 rdma_req_rx_rnr_retry_err; 2975 __le64 rdma_req_rx_remote_access_err; 2976 __le64 rdma_req_rx_remote_inv_req_err; 2977 __le64 rdma_req_rx_remote_oper_err; 2978 __le64 rdma_req_rx_implied_nak_seq_err; 2979 __le64 rdma_req_rx_cqe_err; 2980 __le64 rdma_req_rx_cqe_flush_err; 2981 2982 __le64 rdma_req_rx_dup_responses; 2983 __le64 rdma_req_rx_invalid_packets; 2984 __le64 rdma_req_tx_local_access_err; 2985 __le64 rdma_req_tx_local_oper_err; 2986 __le64 rdma_req_tx_memory_mgmt_err; 2987 __le64 rsvd52; 2988 __le64 rsvd53; 2989 __le64 rsvd54; 2990 2991 /* RDMA/ROCE RESP Error/Debugs (896 - 1023) */ 2992 __le64 rdma_resp_rx_dup_requests; 2993 __le64 rdma_resp_rx_out_of_buffer; 2994 __le64 rdma_resp_rx_out_of_seq_pkts; 2995 __le64 rdma_resp_rx_cqe_err; 2996 __le64 rdma_resp_rx_cqe_flush_err; 2997 __le64 rdma_resp_rx_local_len_err; 2998 __le64 rdma_resp_rx_inv_request_err; 2999 __le64 rdma_resp_rx_local_qp_oper_err; 3000 3001 __le64 rdma_resp_rx_out_of_atomic_resource; 3002 __le64 rdma_resp_tx_pkt_seq_err; 3003 __le64 rdma_resp_tx_remote_inv_req_err; 3004 __le64 rdma_resp_tx_remote_access_err; 3005 __le64 rdma_resp_tx_remote_oper_err; 3006 __le64 rdma_resp_tx_rnr_retry_err; 3007 __le64 rsvd57; 3008 __le64 rsvd58; 3009 }; 3010 3011 /** 3012 * struct ionic_lif_info - LIF info structure 3013 * @config: LIF configuration structure 3014 * @status: LIF status structure 3015 * @stats: LIF statistics structure 3016 */ 3017 struct ionic_lif_info { 3018 union ionic_lif_config config; 3019 struct ionic_lif_status status; 3020 struct ionic_lif_stats stats; 3021 }; 3022 3023 union ionic_dev_cmd { 3024 u32 words[16]; 3025 struct ionic_admin_cmd cmd; 3026 struct ionic_nop_cmd nop; 3027 3028 struct ionic_dev_identify_cmd identify; 3029 struct ionic_dev_init_cmd init; 3030 struct ionic_dev_reset_cmd reset; 3031 struct ionic_dev_getattr_cmd getattr; 3032 struct ionic_dev_setattr_cmd setattr; 3033 3034 struct ionic_port_identify_cmd port_identify; 3035 struct ionic_port_init_cmd port_init; 3036 struct ionic_port_reset_cmd port_reset; 3037 struct ionic_port_getattr_cmd port_getattr; 3038 struct ionic_port_setattr_cmd port_setattr; 3039 3040 struct ionic_vf_setattr_cmd vf_setattr; 3041 struct ionic_vf_getattr_cmd vf_getattr; 3042 struct ionic_vf_ctrl_cmd vf_ctrl; 3043 3044 struct ionic_lif_identify_cmd lif_identify; 3045 struct ionic_lif_init_cmd lif_init; 3046 struct ionic_lif_reset_cmd lif_reset; 3047 3048 struct ionic_qos_identify_cmd qos_identify; 3049 struct ionic_qos_init_cmd qos_init; 3050 struct ionic_qos_reset_cmd qos_reset; 3051 struct ionic_qos_clear_stats_cmd qos_clear_stats; 3052 3053 struct ionic_q_identify_cmd q_identify; 3054 struct ionic_q_init_cmd q_init; 3055 struct ionic_q_control_cmd q_control; 3056 3057 struct ionic_fw_download_cmd fw_download; 3058 struct ionic_fw_control_cmd fw_control; 3059 }; 3060 3061 union ionic_dev_cmd_comp { 3062 u32 words[4]; 3063 u8 status; 3064 struct ionic_admin_comp comp; 3065 struct ionic_nop_comp nop; 3066 3067 struct ionic_dev_identify_comp identify; 3068 struct ionic_dev_init_comp init; 3069 struct ionic_dev_reset_comp reset; 3070 struct ionic_dev_getattr_comp getattr; 3071 struct ionic_dev_setattr_comp setattr; 3072 3073 struct ionic_port_identify_comp port_identify; 3074 struct ionic_port_init_comp port_init; 3075 struct ionic_port_reset_comp port_reset; 3076 struct ionic_port_getattr_comp port_getattr; 3077 struct ionic_port_setattr_comp port_setattr; 3078 3079 struct ionic_vf_setattr_comp vf_setattr; 3080 struct ionic_vf_getattr_comp vf_getattr; 3081 struct ionic_vf_ctrl_comp vf_ctrl; 3082 3083 struct ionic_lif_identify_comp lif_identify; 3084 struct ionic_lif_init_comp lif_init; 3085 ionic_lif_reset_comp lif_reset; 3086 3087 struct ionic_qos_identify_comp qos_identify; 3088 ionic_qos_init_comp qos_init; 3089 ionic_qos_reset_comp qos_reset; 3090 3091 struct ionic_q_identify_comp q_identify; 3092 struct ionic_q_init_comp q_init; 3093 3094 ionic_fw_download_comp fw_download; 3095 struct ionic_fw_control_comp fw_control; 3096 }; 3097 3098 /** 3099 * struct ionic_hwstamp_regs - Hardware current timestamp registers 3100 * @tick_low: Low 32 bits of hardware timestamp 3101 * @tick_high: High 32 bits of hardware timestamp 3102 */ 3103 struct ionic_hwstamp_regs { 3104 u32 tick_low; 3105 u32 tick_high; 3106 }; 3107 3108 /** 3109 * union ionic_dev_info_regs - Device info register format (read-only) 3110 * @signature: Signature value of 0x44455649 ('DEVI') 3111 * @version: Current version of info 3112 * @asic_type: Asic type 3113 * @asic_rev: Asic revision 3114 * @fw_status: Firmware status 3115 * bit 0 - 1 = fw running 3116 * bit 4-7 - 4 bit generation number, changes on fw restart 3117 * @fw_heartbeat: Firmware heartbeat counter 3118 * @serial_num: Serial number 3119 * @rsvd_pad1024: reserved byte(s) 3120 * @fw_version: Firmware version 3121 * @hwstamp: Hardware current timestamp registers 3122 * @words: word access to struct contents 3123 */ 3124 union ionic_dev_info_regs { 3125 #define IONIC_DEVINFO_FWVERS_BUFLEN 32 3126 #define IONIC_DEVINFO_SERIAL_BUFLEN 32 3127 struct { 3128 u32 signature; 3129 u8 version; 3130 u8 asic_type; 3131 u8 asic_rev; 3132 #define IONIC_FW_STS_F_RUNNING 0x01 3133 #define IONIC_FW_STS_F_GENERATION 0xF0 3134 u8 fw_status; 3135 u32 fw_heartbeat; 3136 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN]; 3137 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN]; 3138 u8 rsvd_pad1024[948]; 3139 struct ionic_hwstamp_regs hwstamp; 3140 }; 3141 u32 words[512]; 3142 }; 3143 3144 /** 3145 * union ionic_dev_cmd_regs - Device command register format (read-write) 3146 * @doorbell: Device Cmd Doorbell, write-only 3147 * Write a 1 to signal device to process cmd, 3148 * poll done for completion. 3149 * @done: Done indicator, bit 0 == 1 when command is complete 3150 * @cmd: Opcode-specific command bytes 3151 * @comp: Opcode-specific response bytes 3152 * @rsvd: reserved byte(s) 3153 * @data: Opcode-specific side-data 3154 * @words: word access to struct contents 3155 */ 3156 union ionic_dev_cmd_regs { 3157 struct { 3158 u32 doorbell; 3159 u32 done; 3160 union ionic_dev_cmd cmd; 3161 union ionic_dev_cmd_comp comp; 3162 u8 rsvd[48]; 3163 u32 data[478]; 3164 } __packed; 3165 u32 words[512]; 3166 }; 3167 3168 /** 3169 * union ionic_dev_regs - Device register format for bar 0 page 0 3170 * @info: Device info registers 3171 * @devcmd: Device command registers 3172 * @words: word access to struct contents 3173 */ 3174 union ionic_dev_regs { 3175 struct { 3176 union ionic_dev_info_regs info; 3177 union ionic_dev_cmd_regs devcmd; 3178 } __packed; 3179 __le32 words[1024]; 3180 }; 3181 3182 union ionic_adminq_cmd { 3183 struct ionic_admin_cmd cmd; 3184 struct ionic_nop_cmd nop; 3185 struct ionic_q_identify_cmd q_identify; 3186 struct ionic_q_init_cmd q_init; 3187 struct ionic_q_control_cmd q_control; 3188 struct ionic_lif_setattr_cmd lif_setattr; 3189 struct ionic_lif_getattr_cmd lif_getattr; 3190 struct ionic_lif_setphc_cmd lif_setphc; 3191 struct ionic_rx_mode_set_cmd rx_mode_set; 3192 struct ionic_rx_filter_add_cmd rx_filter_add; 3193 struct ionic_rx_filter_del_cmd rx_filter_del; 3194 struct ionic_rdma_reset_cmd rdma_reset; 3195 struct ionic_rdma_queue_cmd rdma_queue; 3196 struct ionic_fw_download_cmd fw_download; 3197 struct ionic_fw_control_cmd fw_control; 3198 }; 3199 3200 union ionic_adminq_comp { 3201 struct ionic_admin_comp comp; 3202 struct ionic_nop_comp nop; 3203 struct ionic_q_identify_comp q_identify; 3204 struct ionic_q_init_comp q_init; 3205 struct ionic_lif_setattr_comp lif_setattr; 3206 struct ionic_lif_getattr_comp lif_getattr; 3207 struct ionic_admin_comp lif_setphc; 3208 struct ionic_rx_filter_add_comp rx_filter_add; 3209 struct ionic_fw_control_comp fw_control; 3210 }; 3211 3212 #define IONIC_BARS_MAX 6 3213 #define IONIC_PCI_BAR_DBELL 1 3214 #define IONIC_PCI_BAR_CMB 2 3215 3216 #define IONIC_BAR0_SIZE 0x8000 3217 #define IONIC_BAR2_SIZE 0x800000 3218 3219 #define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000 3220 #define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800 3221 #define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00 3222 #define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000 3223 #define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000 3224 #define IONIC_DEV_CMD_DONE 0x00000001 3225 3226 #define IONIC_ASIC_TYPE_NONE 0 3227 #define IONIC_ASIC_TYPE_CAPRI 1 3228 #define IONIC_ASIC_TYPE_ELBA 2 3229 #define IONIC_ASIC_TYPE_GIGLIO 3 3230 #define IONIC_ASIC_TYPE_SALINA 4 3231 3232 /** 3233 * struct ionic_doorbell - Doorbell register layout 3234 * @p_index: Producer index 3235 * @ring: Selects the specific ring of the queue to update 3236 * Type-specific meaning: 3237 * ring=0: Default producer/consumer queue 3238 * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs 3239 * send events to EQs when armed. EQs send 3240 * interrupts when armed. 3241 * @qid_lo: Queue destination for the producer index and flags (low bits) 3242 * @qid_hi: Queue destination for the producer index and flags (high bits) 3243 * @rsvd2: reserved byte(s) 3244 */ 3245 struct ionic_doorbell { 3246 __le16 p_index; 3247 u8 ring; 3248 u8 qid_lo; 3249 __le16 qid_hi; 3250 u16 rsvd2; 3251 }; 3252 3253 struct ionic_intr_status { 3254 u32 status[2]; 3255 }; 3256 3257 struct ionic_notifyq_cmd { 3258 __le32 data; /* Not used but needed for qcq structure */ 3259 }; 3260 3261 union ionic_notifyq_comp { 3262 struct ionic_notifyq_event event; 3263 struct ionic_link_change_event link_change; 3264 struct ionic_reset_event reset; 3265 struct ionic_heartbeat_event heartbeat; 3266 struct ionic_log_event log; 3267 }; 3268 3269 /* Deprecate */ 3270 struct ionic_identity { 3271 union ionic_drv_identity drv; 3272 union ionic_dev_identity dev; 3273 union ionic_lif_identity lif; 3274 union ionic_port_identity port; 3275 union ionic_qos_identity qos; 3276 union ionic_q_identity txq; 3277 }; 3278 3279 #endif /* _IONIC_IF_H_ */ 3280