1 /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */ 2 /* Copyright (c) 2017-2020 Pensando Systems, Inc. All rights reserved. */ 3 4 #ifndef _IONIC_IF_H_ 5 #define _IONIC_IF_H_ 6 7 #define IONIC_DEV_INFO_SIGNATURE 0x44455649 /* 'DEVI' */ 8 #define IONIC_DEV_INFO_VERSION 1 9 #define IONIC_IFNAMSIZ 16 10 11 /* 12 * enum ionic_cmd_opcode - Device commands 13 */ 14 enum ionic_cmd_opcode { 15 IONIC_CMD_NOP = 0, 16 17 /* Device commands */ 18 IONIC_CMD_IDENTIFY = 1, 19 IONIC_CMD_INIT = 2, 20 IONIC_CMD_RESET = 3, 21 IONIC_CMD_GETATTR = 4, 22 IONIC_CMD_SETATTR = 5, 23 24 /* Port commands */ 25 IONIC_CMD_PORT_IDENTIFY = 10, 26 IONIC_CMD_PORT_INIT = 11, 27 IONIC_CMD_PORT_RESET = 12, 28 IONIC_CMD_PORT_GETATTR = 13, 29 IONIC_CMD_PORT_SETATTR = 14, 30 31 /* LIF commands */ 32 IONIC_CMD_LIF_IDENTIFY = 20, 33 IONIC_CMD_LIF_INIT = 21, 34 IONIC_CMD_LIF_RESET = 22, 35 IONIC_CMD_LIF_GETATTR = 23, 36 IONIC_CMD_LIF_SETATTR = 24, 37 IONIC_CMD_LIF_SETPHC = 25, 38 39 IONIC_CMD_RX_MODE_SET = 30, 40 IONIC_CMD_RX_FILTER_ADD = 31, 41 IONIC_CMD_RX_FILTER_DEL = 32, 42 43 /* Queue commands */ 44 IONIC_CMD_Q_IDENTIFY = 39, 45 IONIC_CMD_Q_INIT = 40, 46 IONIC_CMD_Q_CONTROL = 41, 47 48 /* RDMA commands */ 49 IONIC_CMD_RDMA_RESET_LIF = 50, 50 IONIC_CMD_RDMA_CREATE_EQ = 51, 51 IONIC_CMD_RDMA_CREATE_CQ = 52, 52 IONIC_CMD_RDMA_CREATE_ADMINQ = 53, 53 54 /* SR/IOV commands */ 55 IONIC_CMD_VF_GETATTR = 60, 56 IONIC_CMD_VF_SETATTR = 61, 57 IONIC_CMD_VF_CTRL = 62, 58 59 /* CMB command */ 60 IONIC_CMD_DISCOVER_CMB = 80, 61 62 /* QoS commands */ 63 IONIC_CMD_QOS_CLASS_IDENTIFY = 240, 64 IONIC_CMD_QOS_CLASS_INIT = 241, 65 IONIC_CMD_QOS_CLASS_RESET = 242, 66 IONIC_CMD_QOS_CLASS_UPDATE = 243, 67 IONIC_CMD_QOS_CLEAR_STATS = 244, 68 IONIC_CMD_QOS_RESET = 245, 69 70 /* Firmware commands */ 71 IONIC_CMD_FW_DOWNLOAD = 252, 72 IONIC_CMD_FW_CONTROL = 253, 73 IONIC_CMD_FW_DOWNLOAD_V1 = 254, 74 IONIC_CMD_FW_CONTROL_V1 = 255, 75 }; 76 77 /* 78 * enum ionic_status_code - Device command return codes 79 */ 80 enum ionic_status_code { 81 IONIC_RC_SUCCESS = 0, /* Success */ 82 IONIC_RC_EVERSION = 1, /* Incorrect version for request */ 83 IONIC_RC_EOPCODE = 2, /* Invalid cmd opcode */ 84 IONIC_RC_EIO = 3, /* I/O error */ 85 IONIC_RC_EPERM = 4, /* Permission denied */ 86 IONIC_RC_EQID = 5, /* Bad qid */ 87 IONIC_RC_EQTYPE = 6, /* Bad qtype */ 88 IONIC_RC_ENOENT = 7, /* No such element */ 89 IONIC_RC_EINTR = 8, /* operation interrupted */ 90 IONIC_RC_EAGAIN = 9, /* Try again */ 91 IONIC_RC_ENOMEM = 10, /* Out of memory */ 92 IONIC_RC_EFAULT = 11, /* Bad address */ 93 IONIC_RC_EBUSY = 12, /* Device or resource busy */ 94 IONIC_RC_EEXIST = 13, /* object already exists */ 95 IONIC_RC_EINVAL = 14, /* Invalid argument */ 96 IONIC_RC_ENOSPC = 15, /* No space left or alloc failure */ 97 IONIC_RC_ERANGE = 16, /* Parameter out of range */ 98 IONIC_RC_BAD_ADDR = 17, /* Descriptor contains a bad ptr */ 99 IONIC_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */ 100 IONIC_RC_ENOSUPP = 19, /* Operation not supported */ 101 IONIC_RC_ERROR = 29, /* Generic error */ 102 IONIC_RC_ERDMA = 30, /* Generic RDMA error */ 103 IONIC_RC_EVFID = 31, /* VF ID does not exist */ 104 IONIC_RC_EBAD_FW = 32, /* FW file is invalid or corrupted */ 105 }; 106 107 enum ionic_notifyq_opcode { 108 IONIC_EVENT_LINK_CHANGE = 1, 109 IONIC_EVENT_RESET = 2, 110 IONIC_EVENT_HEARTBEAT = 3, 111 IONIC_EVENT_LOG = 4, 112 IONIC_EVENT_XCVR = 5, 113 }; 114 115 /** 116 * struct ionic_admin_cmd - General admin command format 117 * @opcode: Opcode for the command 118 * @rsvd: reserved byte(s) 119 * @lif_index: LIF index 120 * @cmd_data: Opcode-specific command bytes 121 */ 122 struct ionic_admin_cmd { 123 u8 opcode; 124 u8 rsvd; 125 __le16 lif_index; 126 u8 cmd_data[60]; 127 }; 128 129 /** 130 * struct ionic_admin_comp - General admin command completion format 131 * @status: Status of the command (enum ionic_status_code) 132 * @rsvd: reserved byte(s) 133 * @comp_index: Index in the descriptor ring for which this is the completion 134 * @cmd_data: Command-specific bytes 135 * @color: Color bit (Always 0 for commands issued to the 136 * Device Cmd Registers) 137 */ 138 struct ionic_admin_comp { 139 u8 status; 140 u8 rsvd; 141 __le16 comp_index; 142 u8 cmd_data[11]; 143 u8 color; 144 #define IONIC_COMP_COLOR_MASK 0x80 145 }; 146 147 static inline u8 color_match(u8 color, u8 done_color) 148 { 149 return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color; 150 } 151 152 /** 153 * struct ionic_nop_cmd - NOP command 154 * @opcode: opcode 155 * @rsvd: reserved byte(s) 156 */ 157 struct ionic_nop_cmd { 158 u8 opcode; 159 u8 rsvd[63]; 160 }; 161 162 /** 163 * struct ionic_nop_comp - NOP command completion 164 * @status: Status of the command (enum ionic_status_code) 165 * @rsvd: reserved byte(s) 166 */ 167 struct ionic_nop_comp { 168 u8 status; 169 u8 rsvd[15]; 170 }; 171 172 /** 173 * struct ionic_dev_init_cmd - Device init command 174 * @opcode: opcode 175 * @type: Device type 176 * @rsvd: reserved byte(s) 177 */ 178 struct ionic_dev_init_cmd { 179 u8 opcode; 180 u8 type; 181 u8 rsvd[62]; 182 }; 183 184 /** 185 * struct ionic_dev_init_comp - Device init command completion 186 * @status: Status of the command (enum ionic_status_code) 187 * @rsvd: reserved byte(s) 188 */ 189 struct ionic_dev_init_comp { 190 u8 status; 191 u8 rsvd[15]; 192 }; 193 194 /** 195 * struct ionic_dev_reset_cmd - Device reset command 196 * @opcode: opcode 197 * @rsvd: reserved byte(s) 198 */ 199 struct ionic_dev_reset_cmd { 200 u8 opcode; 201 u8 rsvd[63]; 202 }; 203 204 /** 205 * struct ionic_dev_reset_comp - Reset command completion 206 * @status: Status of the command (enum ionic_status_code) 207 * @rsvd: reserved byte(s) 208 */ 209 struct ionic_dev_reset_comp { 210 u8 status; 211 u8 rsvd[15]; 212 }; 213 214 #define IONIC_IDENTITY_VERSION_1 1 215 #define IONIC_DEV_IDENTITY_VERSION_2 2 216 217 /** 218 * struct ionic_dev_identify_cmd - Driver/device identify command 219 * @opcode: opcode 220 * @ver: Highest version of identify supported by driver 221 * @rsvd: reserved byte(s) 222 */ 223 struct ionic_dev_identify_cmd { 224 u8 opcode; 225 u8 ver; 226 u8 rsvd[62]; 227 }; 228 229 /** 230 * struct ionic_dev_identify_comp - Driver/device identify command completion 231 * @status: Status of the command (enum ionic_status_code) 232 * @ver: Version of identify returned by device 233 * @rsvd: reserved byte(s) 234 */ 235 struct ionic_dev_identify_comp { 236 u8 status; 237 u8 ver; 238 u8 rsvd[14]; 239 }; 240 241 enum ionic_os_type { 242 IONIC_OS_TYPE_LINUX = 1, 243 IONIC_OS_TYPE_WIN = 2, 244 IONIC_OS_TYPE_DPDK = 3, 245 IONIC_OS_TYPE_FREEBSD = 4, 246 IONIC_OS_TYPE_IPXE = 5, 247 IONIC_OS_TYPE_ESXI = 6, 248 }; 249 250 /** 251 * union ionic_drv_identity - driver identity information 252 * @os_type: OS type (see enum ionic_os_type) 253 * @os_dist: OS distribution, numeric format 254 * @os_dist_str: OS distribution, string format 255 * @kernel_ver: Kernel version, numeric format 256 * @kernel_ver_str: Kernel version, string format 257 * @driver_ver_str: Driver version, string format 258 * @words: word access to struct contents 259 */ 260 union ionic_drv_identity { 261 struct { 262 __le32 os_type; 263 __le32 os_dist; 264 char os_dist_str[128]; 265 __le32 kernel_ver; 266 char kernel_ver_str[32]; 267 char driver_ver_str[32]; 268 }; 269 __le32 words[478]; 270 }; 271 272 /** 273 * enum ionic_dev_capability - Device capabilities 274 * @IONIC_DEV_CAP_VF_CTRL: Device supports VF ctrl operations 275 * @IONIC_DEV_CAP_DISC_CMB: Device supports CMB discovery operations 276 * @IONIC_DEV_CAP_EXTRA_STATS: Device supports extra stats schema 277 */ 278 enum ionic_dev_capability { 279 IONIC_DEV_CAP_VF_CTRL = BIT(0), 280 IONIC_DEV_CAP_DISC_CMB = BIT(1), 281 IONIC_DEV_CAP_EXTRA_STATS = BIT(4), 282 }; 283 284 /** 285 * union ionic_dev_identity - device identity information 286 * @version: Version of device identify 287 * @type: Identify type (0 for now) 288 * @rsvd: reserved byte(s) 289 * @nports: Number of ports provisioned 290 * @rsvd2: reserved byte(s) 291 * @nlifs: Number of LIFs provisioned 292 * @nintrs: Number of interrupts provisioned 293 * @ndbpgs_per_lif: Number of doorbell pages per LIF 294 * @intr_coal_mult: Interrupt coalescing multiplication factor 295 * Scale user-supplied interrupt coalescing 296 * value in usecs to device units using: 297 * device units = usecs * mult / div 298 * @intr_coal_div: Interrupt coalescing division factor 299 * Scale user-supplied interrupt coalescing 300 * value in usecs to device units using: 301 * device units = usecs * mult / div 302 * @eq_count: Number of shared event queues 303 * @hwstamp_mask: Bitmask for subtraction of hardware tick values. 304 * @hwstamp_mult: Hardware tick to nanosecond multiplier. 305 * @hwstamp_shift: Hardware tick to nanosecond divisor (power of two). 306 * @capabilities: Device capabilities 307 * @words: word access to struct contents 308 */ 309 union ionic_dev_identity { 310 struct { 311 u8 version; 312 u8 type; 313 u8 rsvd[2]; 314 u8 nports; 315 u8 rsvd2[3]; 316 __le32 nlifs; 317 __le32 nintrs; 318 __le32 ndbpgs_per_lif; 319 __le32 intr_coal_mult; 320 __le32 intr_coal_div; 321 __le32 eq_count; 322 __le64 hwstamp_mask; 323 __le32 hwstamp_mult; 324 __le32 hwstamp_shift; 325 __le64 capabilities; 326 }; 327 __le32 words[478]; 328 }; 329 330 enum ionic_lif_type { 331 IONIC_LIF_TYPE_CLASSIC = 0, 332 IONIC_LIF_TYPE_MACVLAN = 1, 333 IONIC_LIF_TYPE_NETQUEUE = 2, 334 }; 335 336 /** 337 * struct ionic_lif_identify_cmd - LIF identify command 338 * @opcode: opcode 339 * @type: LIF type (enum ionic_lif_type) 340 * @ver: Version of identify returned by device 341 * @rsvd: reserved byte(s) 342 */ 343 struct ionic_lif_identify_cmd { 344 u8 opcode; 345 u8 type; 346 u8 ver; 347 u8 rsvd[61]; 348 }; 349 350 /** 351 * struct ionic_lif_identify_comp - LIF identify command completion 352 * @status: Status of the command (enum ionic_status_code) 353 * @ver: Version of identify returned by device 354 * @rsvd2: reserved byte(s) 355 */ 356 struct ionic_lif_identify_comp { 357 u8 status; 358 u8 ver; 359 u8 rsvd2[14]; 360 }; 361 362 /** 363 * enum ionic_lif_capability - LIF capabilities 364 * @IONIC_LIF_CAP_ETH: LIF supports Ethernet 365 * @IONIC_LIF_CAP_RDMA: LIF supports RDMA 366 */ 367 enum ionic_lif_capability { 368 IONIC_LIF_CAP_ETH = BIT(0), 369 IONIC_LIF_CAP_RDMA = BIT(1), 370 }; 371 372 /** 373 * enum ionic_logical_qtype - Logical Queue Types 374 * @IONIC_QTYPE_ADMINQ: Administrative Queue 375 * @IONIC_QTYPE_NOTIFYQ: Notify Queue 376 * @IONIC_QTYPE_RXQ: Receive Queue 377 * @IONIC_QTYPE_TXQ: Transmit Queue 378 * @IONIC_QTYPE_EQ: Event Queue 379 * @IONIC_QTYPE_MAX: Max queue type supported 380 */ 381 enum ionic_logical_qtype { 382 IONIC_QTYPE_ADMINQ = 0, 383 IONIC_QTYPE_NOTIFYQ = 1, 384 IONIC_QTYPE_RXQ = 2, 385 IONIC_QTYPE_TXQ = 3, 386 IONIC_QTYPE_EQ = 4, 387 IONIC_QTYPE_MAX = 16, 388 }; 389 390 /** 391 * enum ionic_q_feature - Common Features for most queue types 392 * 393 * Common features use bits 0-15. Per-queue-type features use higher bits. 394 * 395 * @IONIC_QIDENT_F_CQ: Queue has completion ring 396 * @IONIC_QIDENT_F_SG: Queue has scatter/gather ring 397 * @IONIC_QIDENT_F_EQ: Queue can use event queue 398 * @IONIC_QIDENT_F_CMB: Queue is in cmb bar 399 * @IONIC_Q_F_2X_DESC: Double main descriptor size 400 * @IONIC_Q_F_2X_CQ_DESC: Double cq descriptor size 401 * @IONIC_Q_F_2X_SG_DESC: Double sg descriptor size 402 * @IONIC_Q_F_4X_DESC: Quadruple main descriptor size 403 * @IONIC_Q_F_4X_CQ_DESC: Quadruple cq descriptor size 404 * @IONIC_Q_F_4X_SG_DESC: Quadruple sg descriptor size 405 * @IONIC_QIDENT_F_EXPDB: Queue supports express doorbell 406 */ 407 enum ionic_q_feature { 408 IONIC_QIDENT_F_CQ = BIT_ULL(0), 409 IONIC_QIDENT_F_SG = BIT_ULL(1), 410 IONIC_QIDENT_F_EQ = BIT_ULL(2), 411 IONIC_QIDENT_F_CMB = BIT_ULL(3), 412 IONIC_Q_F_2X_DESC = BIT_ULL(4), 413 IONIC_Q_F_2X_CQ_DESC = BIT_ULL(5), 414 IONIC_Q_F_2X_SG_DESC = BIT_ULL(6), 415 IONIC_Q_F_4X_DESC = BIT_ULL(7), 416 IONIC_Q_F_4X_CQ_DESC = BIT_ULL(8), 417 IONIC_Q_F_4X_SG_DESC = BIT_ULL(9), 418 IONIC_QIDENT_F_EXPDB = BIT_ULL(10), 419 }; 420 421 /** 422 * enum ionic_rxq_feature - RXQ-specific Features 423 * 424 * Per-queue-type features use bits 16 and higher. 425 * 426 * @IONIC_RXQ_F_HWSTAMP: Queue supports Hardware Timestamping 427 */ 428 enum ionic_rxq_feature { 429 IONIC_RXQ_F_HWSTAMP = BIT_ULL(16), 430 }; 431 432 /** 433 * enum ionic_txq_feature - TXQ-specific Features 434 * 435 * Per-queue-type features use bits 16 and higher. 436 * 437 * @IONIC_TXQ_F_HWSTAMP: Queue supports Hardware Timestamping 438 */ 439 enum ionic_txq_feature { 440 IONIC_TXQ_F_HWSTAMP = BIT(16), 441 }; 442 443 /** 444 * enum ionic_hwstamp_bits - Hardware timestamp decoding bits 445 * @IONIC_HWSTAMP_INVALID: Invalid hardware timestamp value 446 * @IONIC_HWSTAMP_CQ_NEGOFFSET: Timestamp field negative offset 447 * from the base cq descriptor. 448 */ 449 enum ionic_hwstamp_bits { 450 IONIC_HWSTAMP_INVALID = ~0ull, 451 IONIC_HWSTAMP_CQ_NEGOFFSET = 8, 452 }; 453 454 /** 455 * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type 456 * @qtype: Hardware Queue Type 457 * @rsvd: reserved byte(s) 458 * @qid_count: Number of Queue IDs of the logical type 459 * @qid_base: Minimum Queue ID of the logical type 460 */ 461 struct ionic_lif_logical_qtype { 462 u8 qtype; 463 u8 rsvd[3]; 464 __le32 qid_count; 465 __le32 qid_base; 466 }; 467 468 /** 469 * enum ionic_lif_state - LIF state 470 * @IONIC_LIF_DISABLE: LIF disabled 471 * @IONIC_LIF_ENABLE: LIF enabled 472 * @IONIC_LIF_QUIESCE: LIF Quiesced 473 */ 474 enum ionic_lif_state { 475 IONIC_LIF_QUIESCE = 0, 476 IONIC_LIF_ENABLE = 1, 477 IONIC_LIF_DISABLE = 2, 478 }; 479 480 /** 481 * union ionic_lif_config - LIF configuration 482 * @state: LIF state (enum ionic_lif_state) 483 * @rsvd: reserved byte(s) 484 * @name: LIF name 485 * @mtu: MTU 486 * @mac: Station MAC address 487 * @vlan: Default Vlan ID 488 * @features: Features (enum ionic_eth_hw_features) 489 * @queue_count: Queue counts per queue-type 490 * @words: word access to struct contents 491 */ 492 union ionic_lif_config { 493 struct { 494 u8 state; 495 u8 rsvd[3]; 496 char name[IONIC_IFNAMSIZ]; 497 __le32 mtu; 498 u8 mac[6]; 499 __le16 vlan; 500 __le64 features; 501 __le32 queue_count[IONIC_QTYPE_MAX]; 502 } __packed; 503 __le32 words[64]; 504 }; 505 506 /** 507 * enum ionic_lif_rdma_cap_stats - LIF stat type 508 * @IONIC_LIF_RDMA_STAT_GLOBAL: Global stats 509 * @IONIC_LIF_RDMA_STAT_QP: Queue pair stats 510 */ 511 enum ionic_lif_rdma_cap_stats { 512 IONIC_LIF_RDMA_STAT_GLOBAL = BIT(0), 513 IONIC_LIF_RDMA_STAT_QP = BIT(1), 514 }; 515 516 /** 517 * struct ionic_lif_identity - LIF identity information (type-specific) 518 * 519 * @capabilities: LIF capabilities 520 * 521 * @eth: Ethernet identify structure 522 * @eth.version: Ethernet identify structure version 523 * @eth.rsvd: reserved byte(s) 524 * @eth.max_ucast_filters: Number of perfect unicast addresses supported 525 * @eth.max_mcast_filters: Number of perfect multicast addresses supported 526 * @eth.min_frame_size: Minimum size of frames to be sent 527 * @eth.max_frame_size: Maximum size of frames to be sent 528 * @eth.rsvd2: reserved byte(s) 529 * @eth.hwstamp_tx_modes: Bitmask of BIT_ULL(enum ionic_txstamp_mode) 530 * @eth.hwstamp_rx_filters: Bitmask of enum ionic_pkt_class 531 * @eth.rsvd3: reserved byte(s) 532 * @eth.config: LIF config struct with features, mtu, mac, q counts 533 * 534 * @rdma: RDMA identify structure 535 * @rdma.version: RDMA capability version 536 * @rdma.qp_opcodes: Number of RDMA queue pair opcodes supported 537 * @rdma.admin_opcodes: Number of RDMA admin opcodes supported 538 * @rdma.minor_version: RDMA capability minor version 539 * @rdma.npts_per_lif: Page table size per LIF 540 * @rdma.nmrs_per_lif: Number of memory regions per LIF 541 * @rdma.nahs_per_lif: Number of address handles per LIF 542 * @rdma.max_stride: Max work request stride 543 * @rdma.cl_stride: Cache line stride 544 * @rdma.pte_stride: Page table entry stride 545 * @rdma.rrq_stride: Remote RQ work request stride 546 * @rdma.rsq_stride: Remote SQ work request stride 547 * @rdma.dcqcn_profiles: Number of DCQCN profiles 548 * @rdma.udma_shift: Log2 number of queues per queue group 549 * @rdma.rsvd_dimensions: Reserved byte 550 * @rdma.page_size_cap: Supported page sizes 551 * @rdma.aq_qtype: RDMA Admin Qtype 552 * @rdma.sq_qtype: RDMA Send Qtype 553 * @rdma.rq_qtype: RDMA Receive Qtype 554 * @rdma.cq_qtype: RDMA Completion Qtype 555 * @rdma.eq_qtype: RDMA Event Qtype 556 * @rdma.stats_type: Supported statistics type 557 * (enum ionic_lif_rdma_cap_stats) 558 * @rdma.rsvd1: Reserved byte(s) 559 * @words: word access to struct contents 560 */ 561 union ionic_lif_identity { 562 struct { 563 __le64 capabilities; 564 565 struct { 566 u8 version; 567 u8 rsvd[3]; 568 __le32 max_ucast_filters; 569 __le32 max_mcast_filters; 570 __le16 rss_ind_tbl_sz; 571 __le32 min_frame_size; 572 __le32 max_frame_size; 573 u8 rsvd2[2]; 574 __le64 hwstamp_tx_modes; 575 __le64 hwstamp_rx_filters; 576 u8 rsvd3[88]; 577 union ionic_lif_config config; 578 } __packed eth; 579 580 struct { 581 u8 version; 582 u8 qp_opcodes; 583 u8 admin_opcodes; 584 u8 minor_version; 585 __le32 npts_per_lif; 586 __le32 nmrs_per_lif; 587 __le32 nahs_per_lif; 588 u8 max_stride; 589 u8 cl_stride; 590 u8 pte_stride; 591 u8 rrq_stride; 592 u8 rsq_stride; 593 u8 dcqcn_profiles; 594 u8 udma_shift; 595 u8 rsvd_dimensions; 596 __le64 page_size_cap; 597 struct ionic_lif_logical_qtype aq_qtype; 598 struct ionic_lif_logical_qtype sq_qtype; 599 struct ionic_lif_logical_qtype rq_qtype; 600 struct ionic_lif_logical_qtype cq_qtype; 601 struct ionic_lif_logical_qtype eq_qtype; 602 __le16 stats_type; 603 u8 rsvd1[162]; 604 } __packed rdma; 605 } __packed; 606 __le32 words[478]; 607 }; 608 609 /** 610 * struct ionic_lif_init_cmd - LIF init command 611 * @opcode: Opcode 612 * @type: LIF type (enum ionic_lif_type) 613 * @index: LIF index 614 * @rsvd: reserved byte(s) 615 * @info_pa: Destination address for LIF info (struct ionic_lif_info) 616 * @rsvd2: reserved byte(s) 617 */ 618 struct ionic_lif_init_cmd { 619 u8 opcode; 620 u8 type; 621 __le16 index; 622 __le32 rsvd; 623 __le64 info_pa; 624 u8 rsvd2[48]; 625 }; 626 627 /** 628 * struct ionic_lif_init_comp - LIF init command completion 629 * @status: Status of the command (enum ionic_status_code) 630 * @rsvd: reserved byte(s) 631 * @hw_index: Hardware index of the initialized LIF 632 * @rsvd2: reserved byte(s) 633 */ 634 struct ionic_lif_init_comp { 635 u8 status; 636 u8 rsvd; 637 __le16 hw_index; 638 u8 rsvd2[12]; 639 }; 640 641 /** 642 * struct ionic_q_identify_cmd - queue identify command 643 * @opcode: opcode 644 * @rsvd: reserved byte(s) 645 * @lif_type: LIF type (enum ionic_lif_type) 646 * @type: Logical queue type (enum ionic_logical_qtype) 647 * @ver: Highest queue type version that the driver supports 648 * @rsvd2: reserved byte(s) 649 */ 650 struct ionic_q_identify_cmd { 651 u8 opcode; 652 u8 rsvd; 653 __le16 lif_type; 654 u8 type; 655 u8 ver; 656 u8 rsvd2[58]; 657 }; 658 659 /** 660 * struct ionic_q_identify_comp - queue identify command completion 661 * @status: Status of the command (enum ionic_status_code) 662 * @rsvd: reserved byte(s) 663 * @comp_index: Index in the descriptor ring for which this is the completion 664 * @ver: Queue type version that can be used with FW 665 * @rsvd2: reserved byte(s) 666 */ 667 struct ionic_q_identify_comp { 668 u8 status; 669 u8 rsvd; 670 __le16 comp_index; 671 u8 ver; 672 u8 rsvd2[11]; 673 }; 674 675 /** 676 * union ionic_q_identity - queue identity information 677 * @version: Queue type version that can be used with FW 678 * @supported: Bitfield of queue versions, first bit = ver 0 679 * @rsvd: reserved byte(s) 680 * @features: Queue features (enum ionic_q_feature, etc) 681 * @desc_sz: Descriptor size 682 * @comp_sz: Completion descriptor size 683 * @sg_desc_sz: Scatter/Gather descriptor size 684 * @max_sg_elems: Maximum number of Scatter/Gather elements 685 * @sg_desc_stride: Number of Scatter/Gather elements per descriptor 686 * @words: word access to struct contents 687 */ 688 union ionic_q_identity { 689 struct { 690 u8 version; 691 u8 supported; 692 u8 rsvd[6]; 693 __le64 features; 694 __le16 desc_sz; 695 __le16 comp_sz; 696 __le16 sg_desc_sz; 697 __le16 max_sg_elems; 698 __le16 sg_desc_stride; 699 }; 700 __le32 words[478]; 701 }; 702 703 /** 704 * struct ionic_q_init_cmd - Queue init command 705 * @opcode: opcode 706 * @rsvd: reserved byte(s) 707 * @type: Logical queue type 708 * @ver: Queue type version 709 * @rsvd1: reserved byte(s) 710 * @lif_index: LIF index 711 * @index: (LIF, qtype) relative admin queue index 712 * @intr_index: Interrupt control register index, or Event queue index 713 * @pid: Process ID 714 * @flags: 715 * IRQ: Interrupt requested on completion 716 * ENA: Enable the queue. If ENA=0 the queue is initialized 717 * but remains disabled, to be later enabled with the 718 * Queue Enable command. If ENA=1, then queue is 719 * initialized and then enabled. 720 * SG: Enable Scatter-Gather on the queue. 721 * in number of descs. The actual ring size is 722 * (1 << ring_size). For example, to 723 * select a ring size of 64 descriptors write 724 * ring_size = 6. The minimum ring_size value is 2 725 * for a ring size of 4 descriptors. The maximum 726 * ring_size value is 16 for a ring size of 64k 727 * descriptors. Values of ring_size <2 and >16 are 728 * reserved. 729 * EQ: Enable the Event Queue 730 * @cos: Class of service for this queue 731 * @ring_size: Queue ring size, encoded as a log2(size) 732 * @ring_base: Queue ring base address 733 * @cq_ring_base: Completion queue ring base address 734 * @sg_ring_base: Scatter/Gather ring base address 735 * @rsvd2: reserved byte(s) 736 * @features: Mask of queue features to enable, if not in the flags above. 737 */ 738 struct ionic_q_init_cmd { 739 u8 opcode; 740 u8 rsvd; 741 __le16 lif_index; 742 u8 type; 743 u8 ver; 744 u8 rsvd1[2]; 745 __le32 index; 746 __le16 pid; 747 __le16 intr_index; 748 __le16 flags; 749 #define IONIC_QINIT_F_IRQ 0x01 /* Request interrupt on completion */ 750 #define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */ 751 #define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */ 752 #define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */ 753 #define IONIC_QINIT_F_CMB 0x10 /* Enable cmb-based queue */ 754 #define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */ 755 u8 cos; 756 u8 ring_size; 757 __le64 ring_base; 758 __le64 cq_ring_base; 759 __le64 sg_ring_base; 760 u8 rsvd2[12]; 761 __le64 features; 762 } __packed; 763 764 /** 765 * struct ionic_q_init_comp - Queue init command completion 766 * @status: Status of the command (enum ionic_status_code) 767 * @rsvd: reserved byte(s) 768 * @comp_index: Index in the descriptor ring for which this is the completion 769 * @hw_index: Hardware Queue ID 770 * @hw_type: Hardware Queue type 771 * @rsvd2: reserved byte(s) 772 * @color: Color 773 */ 774 struct ionic_q_init_comp { 775 u8 status; 776 u8 rsvd; 777 __le16 comp_index; 778 __le32 hw_index; 779 u8 hw_type; 780 u8 rsvd2[6]; 781 u8 color; 782 }; 783 784 /* the device's internal addressing uses up to 52 bits */ 785 #define IONIC_ADDR_LEN 52 786 #define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 787 788 enum ionic_txq_desc_opcode { 789 IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0, 790 IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1, 791 IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2, 792 IONIC_TXQ_DESC_OPCODE_TSO = 3, 793 }; 794 795 /** 796 * struct ionic_txq_desc - Ethernet Tx queue descriptor format 797 * @cmd: Tx operation, see IONIC_TXQ_DESC_OPCODE_*: 798 * 799 * IONIC_TXQ_DESC_OPCODE_CSUM_NONE: 800 * Non-offload send. No segmentation, 801 * fragmentation or checksum calc/insertion is 802 * performed by device; packet is prepared 803 * to send by software stack and requires 804 * no further manipulation from device. 805 * 806 * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL: 807 * Offload 16-bit L4 checksum 808 * calculation/insertion. The device will 809 * calculate the L4 checksum value and 810 * insert the result in the packet's L4 811 * header checksum field. The L4 checksum 812 * is calculated starting at @csum_start bytes 813 * into the packet to the end of the packet. 814 * The checksum insertion position is given 815 * in @csum_offset, which is the offset from 816 * @csum_start to the checksum field in the L4 817 * header. This feature is only applicable to 818 * protocols such as TCP, UDP and ICMP where a 819 * standard (i.e. the 'IP-style' checksum) 820 * one's complement 16-bit checksum is used, 821 * using an IP pseudo-header to seed the 822 * calculation. Software will preload the L4 823 * checksum field with the IP pseudo-header 824 * checksum. 825 * 826 * For tunnel encapsulation, @csum_start and 827 * @csum_offset refer to the inner L4 828 * header. Supported tunnels encapsulations 829 * are: IPIP, GRE, and UDP. If the @encap 830 * is clear, no further processing by the 831 * device is required; software will 832 * calculate the outer header checksums. If 833 * the @encap is set, the device will 834 * offload the outer header checksums using 835 * LCO (local checksum offload) (see 836 * Documentation/networking/checksum-offloads.rst 837 * for more info). 838 * 839 * IONIC_TXQ_DESC_OPCODE_CSUM_HW: 840 * Offload 16-bit checksum computation to hardware. 841 * If @csum_l3 is set then the packet's L3 checksum is 842 * updated. Similarly, if @csum_l4 is set the L4 843 * checksum is updated. If @encap is set then encap header 844 * checksums are also updated. 845 * 846 * IONIC_TXQ_DESC_OPCODE_TSO: 847 * Device performs TCP segmentation offload 848 * (TSO). @hdr_len is the number of bytes 849 * to the end of TCP header (the offset to 850 * the TCP payload). @mss is the desired 851 * MSS, the TCP payload length for each 852 * segment. The device will calculate/ 853 * insert IP (IPv4 only) and TCP checksums 854 * for each segment. In the first data 855 * buffer containing the header template, 856 * the driver will set IPv4 checksum to 0 857 * and preload TCP checksum with the IP 858 * pseudo header calculated with IP length = 0. 859 * 860 * Supported tunnel encapsulations are IPIP, 861 * layer-3 GRE, and UDP. @hdr_len includes 862 * both outer and inner headers. The driver 863 * will set IPv4 checksum to zero and 864 * preload TCP checksum with IP pseudo 865 * header on the inner header. 866 * 867 * TCP ECN offload is supported. The device 868 * will set CWR flag in the first segment if 869 * CWR is set in the template header, and 870 * clear CWR in remaining segments. 871 * flags: 872 * vlan: 873 * Insert an L2 VLAN header using @vlan_tci 874 * encap: 875 * Calculate encap header checksum 876 * csum_l3: 877 * Compute L3 header checksum 878 * csum_l4: 879 * Compute L4 header checksum 880 * tso_sot: 881 * TSO start 882 * tso_eot: 883 * TSO end 884 * num_sg_elems: Number of scatter-gather elements in SG 885 * descriptor 886 * addr: First data buffer's DMA address 887 * (Subsequent data buffers are on txq_sg_desc) 888 * @len: First data buffer's length, in bytes 889 * @vlan_tci: VLAN tag to insert in the packet (if requested 890 * by @V-bit). Includes .1p and .1q tags 891 * @hword0: half word padding 892 * @hdr_len: Length of packet headers, including 893 * encapsulating outer header, if applicable 894 * Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and 895 * IONIC_TXQ_DESC_OPCODE_TSO. Should be set to zero for 896 * all other modes. For 897 * IONIC_TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length 898 * of headers up to inner-most L4 header. For 899 * IONIC_TXQ_DESC_OPCODE_TSO, @hdr_len is up to 900 * inner-most L4 payload, so inclusive of 901 * inner-most L4 header. 902 * @hword1: half word padding 903 * @mss: Desired MSS value for TSO; only applicable for 904 * IONIC_TXQ_DESC_OPCODE_TSO 905 * @csum_start: Offset from packet to first byte checked in L4 checksum 906 * @csum_offset: Offset from csum_start to L4 checksum field 907 * @hword2: half word padding 908 */ 909 struct ionic_txq_desc { 910 __le64 cmd; 911 #define IONIC_TXQ_DESC_OPCODE_MASK 0xf 912 #define IONIC_TXQ_DESC_OPCODE_SHIFT 4 913 #define IONIC_TXQ_DESC_FLAGS_MASK 0xf 914 #define IONIC_TXQ_DESC_FLAGS_SHIFT 0 915 #define IONIC_TXQ_DESC_NSGE_MASK 0xf 916 #define IONIC_TXQ_DESC_NSGE_SHIFT 8 917 #define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 918 #define IONIC_TXQ_DESC_ADDR_SHIFT 12 919 920 /* common flags */ 921 #define IONIC_TXQ_DESC_FLAG_VLAN 0x1 922 #define IONIC_TXQ_DESC_FLAG_ENCAP 0x2 923 924 /* flags for csum_hw opcode */ 925 #define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4 926 #define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8 927 928 /* flags for tso opcode */ 929 #define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4 930 #define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8 931 932 __le16 len; 933 union { 934 __le16 vlan_tci; 935 __le16 hword0; 936 }; 937 union { 938 __le16 csum_start; 939 __le16 hdr_len; 940 __le16 hword1; 941 }; 942 union { 943 __le16 csum_offset; 944 __le16 mss; 945 __le16 hword2; 946 }; 947 }; 948 949 static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags, 950 u8 nsge, u64 addr) 951 { 952 u64 cmd; 953 954 cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << IONIC_TXQ_DESC_OPCODE_SHIFT; 955 cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << IONIC_TXQ_DESC_FLAGS_SHIFT; 956 cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT; 957 cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT; 958 959 return cmd; 960 }; 961 962 static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags, 963 u8 *nsge, u64 *addr) 964 { 965 *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & IONIC_TXQ_DESC_OPCODE_MASK; 966 *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & IONIC_TXQ_DESC_FLAGS_MASK; 967 *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK; 968 *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK; 969 }; 970 971 /** 972 * struct ionic_txq_sg_elem - Transmit scatter-gather (SG) descriptor element 973 * @addr: DMA address of SG element data buffer 974 * @len: Length of SG element data buffer, in bytes 975 * @rsvd: reserved byte(s) 976 */ 977 struct ionic_txq_sg_elem { 978 __le64 addr; 979 __le16 len; 980 __le16 rsvd[3]; 981 }; 982 983 /** 984 * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list 985 * @elems: Scatter-gather elements 986 */ 987 struct ionic_txq_sg_desc { 988 #define IONIC_TX_MAX_SG_ELEMS 8 989 #define IONIC_TX_SG_DESC_STRIDE 8 990 struct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS]; 991 }; 992 993 struct ionic_txq_sg_desc_v1 { 994 #define IONIC_TX_MAX_SG_ELEMS_V1 15 995 #define IONIC_TX_SG_DESC_STRIDE_V1 16 996 struct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1]; 997 }; 998 999 /** 1000 * struct ionic_txq_comp - Ethernet transmit queue completion descriptor 1001 * @status: Status of the command (enum ionic_status_code) 1002 * @rsvd: reserved byte(s) 1003 * @comp_index: Index in the descriptor ring for which this is the completion 1004 * @rsvd2: reserved byte(s) 1005 * @color: Color bit 1006 */ 1007 struct ionic_txq_comp { 1008 u8 status; 1009 u8 rsvd; 1010 __le16 comp_index; 1011 u8 rsvd2[11]; 1012 u8 color; 1013 }; 1014 1015 enum ionic_rxq_desc_opcode { 1016 IONIC_RXQ_DESC_OPCODE_SIMPLE = 0, 1017 IONIC_RXQ_DESC_OPCODE_SG = 1, 1018 }; 1019 1020 /** 1021 * struct ionic_rxq_desc - Ethernet Rx queue descriptor format 1022 * @opcode: Rx operation, see IONIC_RXQ_DESC_OPCODE_*: 1023 * 1024 * IONIC_RXQ_DESC_OPCODE_SIMPLE: 1025 * Receive full packet into data buffer 1026 * starting at @addr. Results of 1027 * receive, including actual bytes received, 1028 * are recorded in Rx completion descriptor. 1029 * 1030 * @rsvd: reserved byte(s) 1031 * @len: Data buffer's length, in bytes 1032 * @addr: Data buffer's DMA address 1033 */ 1034 struct ionic_rxq_desc { 1035 u8 opcode; 1036 u8 rsvd[5]; 1037 __le16 len; 1038 __le64 addr; 1039 }; 1040 1041 /** 1042 * struct ionic_rxq_sg_elem - Receive scatter-gather (SG) descriptor element 1043 * @addr: DMA address of SG element data buffer 1044 * @len: Length of SG element data buffer, in bytes 1045 * @rsvd: reserved byte(s) 1046 */ 1047 struct ionic_rxq_sg_elem { 1048 __le64 addr; 1049 __le16 len; 1050 __le16 rsvd[3]; 1051 }; 1052 1053 /** 1054 * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list 1055 * @elems: Scatter-gather elements 1056 */ 1057 struct ionic_rxq_sg_desc { 1058 #define IONIC_RX_MAX_SG_ELEMS 8 1059 #define IONIC_RX_SG_DESC_STRIDE 8 1060 struct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE]; 1061 }; 1062 1063 /** 1064 * struct ionic_rxq_comp - Ethernet receive queue completion descriptor 1065 * @status: Status of the command (enum ionic_status_code) 1066 * @num_sg_elems: Number of SG elements used by this descriptor 1067 * @comp_index: Index in the descriptor ring for which this is the completion 1068 * @rss_hash: 32-bit RSS hash 1069 * @csum: 16-bit sum of the packet's L2 payload 1070 * If the packet's L2 payload is odd length, an extra 1071 * zero-value byte is included in the @csum calculation but 1072 * not included in @len. 1073 * @vlan_tci: VLAN tag stripped from the packet. Valid if @VLAN is 1074 * set. Includes .1p and .1q tags. 1075 * @len: Received packet length, in bytes. Excludes FCS. 1076 * @csum_calc L2 payload checksum is computed or not 1077 * @csum_flags: See IONIC_RXQ_COMP_CSUM_F_*: 1078 * 1079 * IONIC_RXQ_COMP_CSUM_F_TCP_OK: 1080 * The TCP checksum calculated by the device 1081 * matched the checksum in the receive packet's 1082 * TCP header. 1083 * 1084 * IONIC_RXQ_COMP_CSUM_F_TCP_BAD: 1085 * The TCP checksum calculated by the device did 1086 * not match the checksum in the receive packet's 1087 * TCP header. 1088 * 1089 * IONIC_RXQ_COMP_CSUM_F_UDP_OK: 1090 * The UDP checksum calculated by the device 1091 * matched the checksum in the receive packet's 1092 * UDP header 1093 * 1094 * IONIC_RXQ_COMP_CSUM_F_UDP_BAD: 1095 * The UDP checksum calculated by the device did 1096 * not match the checksum in the receive packet's 1097 * UDP header. 1098 * 1099 * IONIC_RXQ_COMP_CSUM_F_IP_OK: 1100 * The IPv4 checksum calculated by the device 1101 * matched the checksum in the receive packet's 1102 * first IPv4 header. If the receive packet 1103 * contains both a tunnel IPv4 header and a 1104 * transport IPv4 header, the device validates the 1105 * checksum for both IPv4 headers. 1106 * 1107 * IONIC_RXQ_COMP_CSUM_F_IP_BAD: 1108 * The IPv4 checksum calculated by the device did 1109 * not match the checksum in the receive packet's 1110 * first IPv4 header. If the receive packet 1111 * contains both a tunnel IPv4 header and a 1112 * transport IPv4 header, the device validates the 1113 * checksum for both IP headers. 1114 * 1115 * IONIC_RXQ_COMP_CSUM_F_VLAN: 1116 * The VLAN header was stripped and placed in @vlan_tci. 1117 * 1118 * IONIC_RXQ_COMP_CSUM_F_CALC: 1119 * The checksum was calculated by the device. 1120 * 1121 * @pkt_type_color: Packet type and color bit; see IONIC_RXQ_COMP_PKT_TYPE_MASK 1122 */ 1123 struct ionic_rxq_comp { 1124 u8 status; 1125 u8 num_sg_elems; 1126 __le16 comp_index; 1127 __le32 rss_hash; 1128 __le16 csum; 1129 __le16 vlan_tci; 1130 __le16 len; 1131 u8 csum_flags; 1132 #define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01 1133 #define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02 1134 #define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04 1135 #define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08 1136 #define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10 1137 #define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20 1138 #define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40 1139 #define IONIC_RXQ_COMP_CSUM_F_CALC 0x80 1140 u8 pkt_type_color; 1141 #define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x7f 1142 }; 1143 1144 enum ionic_pkt_type { 1145 IONIC_PKT_TYPE_NON_IP = 0x00, 1146 IONIC_PKT_TYPE_IPV4 = 0x01, 1147 IONIC_PKT_TYPE_IPV4_TCP = 0x03, 1148 IONIC_PKT_TYPE_IPV4_UDP = 0x05, 1149 IONIC_PKT_TYPE_IPV6 = 0x08, 1150 IONIC_PKT_TYPE_IPV6_TCP = 0x18, 1151 IONIC_PKT_TYPE_IPV6_UDP = 0x28, 1152 /* below types are only used if encap offloads are enabled on lif */ 1153 IONIC_PKT_TYPE_ENCAP_NON_IP = 0x40, 1154 IONIC_PKT_TYPE_ENCAP_IPV4 = 0x41, 1155 IONIC_PKT_TYPE_ENCAP_IPV4_TCP = 0x43, 1156 IONIC_PKT_TYPE_ENCAP_IPV4_UDP = 0x45, 1157 IONIC_PKT_TYPE_ENCAP_IPV6 = 0x48, 1158 IONIC_PKT_TYPE_ENCAP_IPV6_TCP = 0x58, 1159 IONIC_PKT_TYPE_ENCAP_IPV6_UDP = 0x68, 1160 }; 1161 1162 enum ionic_eth_hw_features { 1163 IONIC_ETH_HW_VLAN_TX_TAG = BIT(0), 1164 IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1), 1165 IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2), 1166 IONIC_ETH_HW_RX_HASH = BIT(3), 1167 IONIC_ETH_HW_RX_CSUM = BIT(4), 1168 IONIC_ETH_HW_TX_SG = BIT(5), 1169 IONIC_ETH_HW_RX_SG = BIT(6), 1170 IONIC_ETH_HW_TX_CSUM = BIT(7), 1171 IONIC_ETH_HW_TSO = BIT(8), 1172 IONIC_ETH_HW_TSO_IPV6 = BIT(9), 1173 IONIC_ETH_HW_TSO_ECN = BIT(10), 1174 IONIC_ETH_HW_TSO_GRE = BIT(11), 1175 IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12), 1176 IONIC_ETH_HW_TSO_IPXIP4 = BIT(13), 1177 IONIC_ETH_HW_TSO_IPXIP6 = BIT(14), 1178 IONIC_ETH_HW_TSO_UDP = BIT(15), 1179 IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16), 1180 IONIC_ETH_HW_RX_CSUM_GENEVE = BIT(17), 1181 IONIC_ETH_HW_TX_CSUM_GENEVE = BIT(18), 1182 IONIC_ETH_HW_TSO_GENEVE = BIT(19), 1183 IONIC_ETH_HW_TIMESTAMP = BIT(20), 1184 IONIC_ETH_HW_RDMA_TIMESTAMP = BIT(21), 1185 }; 1186 1187 /** 1188 * enum ionic_pkt_class - Packet classification mask. 1189 * 1190 * Used with rx steering filter, packets indicated by the mask can be steered 1191 * toward a specific receive queue. 1192 * 1193 * @IONIC_PKT_CLS_NTP_ALL: All NTP packets. 1194 * @IONIC_PKT_CLS_PTP1_SYNC: PTPv1 sync 1195 * @IONIC_PKT_CLS_PTP1_DREQ: PTPv1 delay-request 1196 * @IONIC_PKT_CLS_PTP1_ALL: PTPv1 all packets 1197 * @IONIC_PKT_CLS_PTP2_L4_SYNC: PTPv2-UDP sync 1198 * @IONIC_PKT_CLS_PTP2_L4_DREQ: PTPv2-UDP delay-request 1199 * @IONIC_PKT_CLS_PTP2_L4_ALL: PTPv2-UDP all packets 1200 * @IONIC_PKT_CLS_PTP2_L2_SYNC: PTPv2-ETH sync 1201 * @IONIC_PKT_CLS_PTP2_L2_DREQ: PTPv2-ETH delay-request 1202 * @IONIC_PKT_CLS_PTP2_L2_ALL: PTPv2-ETH all packets 1203 * @IONIC_PKT_CLS_PTP2_SYNC: PTPv2 sync 1204 * @IONIC_PKT_CLS_PTP2_DREQ: PTPv2 delay-request 1205 * @IONIC_PKT_CLS_PTP2_ALL: PTPv2 all packets 1206 * @IONIC_PKT_CLS_PTP_SYNC: PTP sync 1207 * @IONIC_PKT_CLS_PTP_DREQ: PTP delay-request 1208 * @IONIC_PKT_CLS_PTP_ALL: PTP all packets 1209 */ 1210 enum ionic_pkt_class { 1211 IONIC_PKT_CLS_NTP_ALL = BIT(0), 1212 1213 IONIC_PKT_CLS_PTP1_SYNC = BIT(1), 1214 IONIC_PKT_CLS_PTP1_DREQ = BIT(2), 1215 IONIC_PKT_CLS_PTP1_ALL = BIT(3) | 1216 IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP1_DREQ, 1217 1218 IONIC_PKT_CLS_PTP2_L4_SYNC = BIT(4), 1219 IONIC_PKT_CLS_PTP2_L4_DREQ = BIT(5), 1220 IONIC_PKT_CLS_PTP2_L4_ALL = BIT(6) | 1221 IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L4_DREQ, 1222 1223 IONIC_PKT_CLS_PTP2_L2_SYNC = BIT(7), 1224 IONIC_PKT_CLS_PTP2_L2_DREQ = BIT(8), 1225 IONIC_PKT_CLS_PTP2_L2_ALL = BIT(9) | 1226 IONIC_PKT_CLS_PTP2_L2_SYNC | IONIC_PKT_CLS_PTP2_L2_DREQ, 1227 1228 IONIC_PKT_CLS_PTP2_SYNC = 1229 IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L2_SYNC, 1230 IONIC_PKT_CLS_PTP2_DREQ = 1231 IONIC_PKT_CLS_PTP2_L4_DREQ | IONIC_PKT_CLS_PTP2_L2_DREQ, 1232 IONIC_PKT_CLS_PTP2_ALL = 1233 IONIC_PKT_CLS_PTP2_L4_ALL | IONIC_PKT_CLS_PTP2_L2_ALL, 1234 1235 IONIC_PKT_CLS_PTP_SYNC = 1236 IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP2_SYNC, 1237 IONIC_PKT_CLS_PTP_DREQ = 1238 IONIC_PKT_CLS_PTP1_DREQ | IONIC_PKT_CLS_PTP2_DREQ, 1239 IONIC_PKT_CLS_PTP_ALL = 1240 IONIC_PKT_CLS_PTP1_ALL | IONIC_PKT_CLS_PTP2_ALL, 1241 }; 1242 1243 /** 1244 * struct ionic_q_control_cmd - Queue control command 1245 * @opcode: opcode 1246 * @type: Queue type 1247 * @lif_index: LIF index 1248 * @index: Queue index 1249 * @oper: Operation (enum ionic_q_control_oper) 1250 * @rsvd: reserved byte(s) 1251 */ 1252 struct ionic_q_control_cmd { 1253 u8 opcode; 1254 u8 type; 1255 __le16 lif_index; 1256 __le32 index; 1257 u8 oper; 1258 u8 rsvd[55]; 1259 }; 1260 1261 typedef struct ionic_admin_comp ionic_q_control_comp; 1262 1263 enum ionic_q_control_oper { 1264 IONIC_Q_DISABLE = 0, 1265 IONIC_Q_ENABLE = 1, 1266 IONIC_Q_HANG_RESET = 2, 1267 }; 1268 1269 /** 1270 * enum ionic_phy_type - Physical connection type 1271 * @IONIC_PHY_TYPE_NONE: No PHY installed 1272 * @IONIC_PHY_TYPE_COPPER: Copper PHY 1273 * @IONIC_PHY_TYPE_FIBER: Fiber PHY 1274 */ 1275 enum ionic_phy_type { 1276 IONIC_PHY_TYPE_NONE = 0, 1277 IONIC_PHY_TYPE_COPPER = 1, 1278 IONIC_PHY_TYPE_FIBER = 2, 1279 }; 1280 1281 /** 1282 * enum ionic_xcvr_state - Transceiver status 1283 * @IONIC_XCVR_STATE_REMOVED: Transceiver removed 1284 * @IONIC_XCVR_STATE_INSERTED: Transceiver inserted 1285 * @IONIC_XCVR_STATE_PENDING: Transceiver pending 1286 * @IONIC_XCVR_STATE_SPROM_READ: Transceiver data read 1287 * @IONIC_XCVR_STATE_SPROM_READ_ERR: Transceiver data read error 1288 */ 1289 enum ionic_xcvr_state { 1290 IONIC_XCVR_STATE_REMOVED = 0, 1291 IONIC_XCVR_STATE_INSERTED = 1, 1292 IONIC_XCVR_STATE_PENDING = 2, 1293 IONIC_XCVR_STATE_SPROM_READ = 3, 1294 IONIC_XCVR_STATE_SPROM_READ_ERR = 4, 1295 }; 1296 1297 /* 1298 * enum ionic_xcvr_pid - Supported link modes 1299 */ 1300 enum ionic_xcvr_pid { 1301 IONIC_XCVR_PID_UNKNOWN = 0, 1302 1303 /* CU */ 1304 IONIC_XCVR_PID_QSFP_100G_CR4 = 1, 1305 IONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2, 1306 IONIC_XCVR_PID_SFP_25GBASE_CR_S = 3, 1307 IONIC_XCVR_PID_SFP_25GBASE_CR_L = 4, 1308 IONIC_XCVR_PID_SFP_25GBASE_CR_N = 5, 1309 IONIC_XCVR_PID_QSFP_50G_CR2_FC = 6, 1310 IONIC_XCVR_PID_QSFP_50G_CR2 = 7, 1311 IONIC_XCVR_PID_QSFP_200G_CR4 = 8, 1312 IONIC_XCVR_PID_QSFP_400G_CR4 = 9, 1313 /* Fiber */ 1314 IONIC_XCVR_PID_QSFP_100G_AOC = 50, 1315 IONIC_XCVR_PID_QSFP_100G_ACC = 51, 1316 IONIC_XCVR_PID_QSFP_100G_SR4 = 52, 1317 IONIC_XCVR_PID_QSFP_100G_LR4 = 53, 1318 IONIC_XCVR_PID_QSFP_100G_ER4 = 54, 1319 IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55, 1320 IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56, 1321 IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57, 1322 IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58, 1323 IONIC_XCVR_PID_SFP_25GBASE_SR = 59, 1324 IONIC_XCVR_PID_SFP_25GBASE_LR = 60, 1325 IONIC_XCVR_PID_SFP_25GBASE_ER = 61, 1326 IONIC_XCVR_PID_SFP_25GBASE_AOC = 62, 1327 IONIC_XCVR_PID_SFP_10GBASE_SR = 63, 1328 IONIC_XCVR_PID_SFP_10GBASE_LR = 64, 1329 IONIC_XCVR_PID_SFP_10GBASE_LRM = 65, 1330 IONIC_XCVR_PID_SFP_10GBASE_ER = 66, 1331 IONIC_XCVR_PID_SFP_10GBASE_AOC = 67, 1332 IONIC_XCVR_PID_SFP_10GBASE_CU = 68, 1333 IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69, 1334 IONIC_XCVR_PID_QSFP_100G_PSM4 = 70, 1335 IONIC_XCVR_PID_SFP_25GBASE_ACC = 71, 1336 IONIC_XCVR_PID_SFP_10GBASE_T = 72, 1337 IONIC_XCVR_PID_SFP_1000BASE_T = 73, 1338 IONIC_XCVR_PID_QSFP_200G_AOC = 74, 1339 IONIC_XCVR_PID_QSFP_200G_FR4 = 75, 1340 IONIC_XCVR_PID_QSFP_200G_DR4 = 76, 1341 IONIC_XCVR_PID_QSFP_200G_SR4 = 77, 1342 IONIC_XCVR_PID_QSFP_200G_ACC = 78, 1343 IONIC_XCVR_PID_QSFP_400G_FR4 = 79, 1344 IONIC_XCVR_PID_QSFP_400G_DR4 = 80, 1345 IONIC_XCVR_PID_QSFP_400G_SR4 = 81, 1346 IONIC_XCVR_PID_QSFP_400G_VR4 = 82, 1347 IONIC_XCVR_PID_QSFP_400G_AOC = 83, 1348 IONIC_XCVR_PID_QSFP_400G_AEC = 84, 1349 IONIC_XCVR_PID_QSFP_200G_AEC = 85, 1350 IONIC_XCVR_PID_QSFP_400G_LPO = 86, 1351 IONIC_XCVR_PID_QSFP_100G_FR4 = 87, 1352 IONIC_XCVR_PID_QSFP_100G_DR4 = 88, 1353 }; 1354 1355 /** 1356 * enum ionic_port_type - Port types 1357 * @IONIC_PORT_TYPE_NONE: Port type not configured 1358 * @IONIC_PORT_TYPE_ETH: Port carries ethernet traffic (inband) 1359 * @IONIC_PORT_TYPE_MGMT: Port carries mgmt traffic (out-of-band) 1360 */ 1361 enum ionic_port_type { 1362 IONIC_PORT_TYPE_NONE = 0, 1363 IONIC_PORT_TYPE_ETH = 1, 1364 IONIC_PORT_TYPE_MGMT = 2, 1365 }; 1366 1367 /** 1368 * enum ionic_port_admin_state - Port config state 1369 * @IONIC_PORT_ADMIN_STATE_NONE: Port admin state not configured 1370 * @IONIC_PORT_ADMIN_STATE_DOWN: Port admin disabled 1371 * @IONIC_PORT_ADMIN_STATE_UP: Port admin enabled 1372 */ 1373 enum ionic_port_admin_state { 1374 IONIC_PORT_ADMIN_STATE_NONE = 0, 1375 IONIC_PORT_ADMIN_STATE_DOWN = 1, 1376 IONIC_PORT_ADMIN_STATE_UP = 2, 1377 }; 1378 1379 /** 1380 * enum ionic_port_oper_status - Port operational status 1381 * @IONIC_PORT_OPER_STATUS_NONE: Port disabled 1382 * @IONIC_PORT_OPER_STATUS_UP: Port link status up 1383 * @IONIC_PORT_OPER_STATUS_DOWN: Port link status down 1384 */ 1385 enum ionic_port_oper_status { 1386 IONIC_PORT_OPER_STATUS_NONE = 0, 1387 IONIC_PORT_OPER_STATUS_UP = 1, 1388 IONIC_PORT_OPER_STATUS_DOWN = 2, 1389 }; 1390 1391 /** 1392 * enum ionic_port_fec_type - Ethernet Forward error correction (FEC) modes 1393 * @IONIC_PORT_FEC_TYPE_NONE: FEC Disabled 1394 * @IONIC_PORT_FEC_TYPE_FC: FireCode FEC 1395 * @IONIC_PORT_FEC_TYPE_RS: ReedSolomon FEC 1396 */ 1397 enum ionic_port_fec_type { 1398 IONIC_PORT_FEC_TYPE_NONE = 0, 1399 IONIC_PORT_FEC_TYPE_FC = 1, 1400 IONIC_PORT_FEC_TYPE_RS = 2, 1401 }; 1402 1403 /** 1404 * enum ionic_port_pause_type - Ethernet pause (flow control) modes 1405 * @IONIC_PORT_PAUSE_TYPE_NONE: Disable Pause 1406 * @IONIC_PORT_PAUSE_TYPE_LINK: Link level pause 1407 * @IONIC_PORT_PAUSE_TYPE_PFC: Priority-Flow Control 1408 */ 1409 enum ionic_port_pause_type { 1410 IONIC_PORT_PAUSE_TYPE_NONE = 0, 1411 IONIC_PORT_PAUSE_TYPE_LINK = 1, 1412 IONIC_PORT_PAUSE_TYPE_PFC = 2, 1413 }; 1414 1415 /** 1416 * enum ionic_port_loopback_mode - Loopback modes 1417 * @IONIC_PORT_LOOPBACK_MODE_NONE: Disable loopback 1418 * @IONIC_PORT_LOOPBACK_MODE_MAC: MAC loopback 1419 * @IONIC_PORT_LOOPBACK_MODE_PHY: PHY/SerDes loopback 1420 */ 1421 enum ionic_port_loopback_mode { 1422 IONIC_PORT_LOOPBACK_MODE_NONE = 0, 1423 IONIC_PORT_LOOPBACK_MODE_MAC = 1, 1424 IONIC_PORT_LOOPBACK_MODE_PHY = 2, 1425 }; 1426 1427 /** 1428 * struct ionic_xcvr_status - Transceiver Status information 1429 * @state: Transceiver status (enum ionic_xcvr_state) 1430 * @phy: Physical connection type (enum ionic_phy_type) 1431 * @pid: Transceiver link mode (enum ionic_xcvr_pid) 1432 * @sprom: Transceiver sprom contents 1433 */ 1434 struct ionic_xcvr_status { 1435 u8 state; 1436 u8 phy; 1437 __le16 pid; 1438 u8 sprom[256]; 1439 }; 1440 1441 /** 1442 * union ionic_port_config - Port configuration 1443 * @speed: port speed (in Mbps) 1444 * @mtu: mtu 1445 * @state: port admin state (enum ionic_port_admin_state) 1446 * @an_enable: autoneg enable 1447 * @fec_type: fec type (enum ionic_port_fec_type) 1448 * @pause_type: pause type (enum ionic_port_pause_type) 1449 * @loopback_mode: loopback mode (enum ionic_port_loopback_mode) 1450 * @words: word access to struct contents 1451 */ 1452 union ionic_port_config { 1453 struct { 1454 #define IONIC_SPEED_400G 400000 /* 400G in Mbps */ 1455 #define IONIC_SPEED_200G 200000 /* 200G in Mbps */ 1456 #define IONIC_SPEED_100G 100000 /* 100G in Mbps */ 1457 #define IONIC_SPEED_50G 50000 /* 50G in Mbps */ 1458 #define IONIC_SPEED_40G 40000 /* 40G in Mbps */ 1459 #define IONIC_SPEED_25G 25000 /* 25G in Mbps */ 1460 #define IONIC_SPEED_10G 10000 /* 10G in Mbps */ 1461 #define IONIC_SPEED_1G 1000 /* 1G in Mbps */ 1462 __le32 speed; 1463 __le32 mtu; 1464 u8 state; 1465 u8 an_enable; 1466 u8 fec_type; 1467 #define IONIC_PAUSE_TYPE_MASK 0x0f 1468 #define IONIC_PAUSE_FLAGS_MASK 0xf0 1469 #define IONIC_PAUSE_F_TX 0x10 1470 #define IONIC_PAUSE_F_RX 0x20 1471 u8 pause_type; 1472 u8 loopback_mode; 1473 }; 1474 __le32 words[64]; 1475 }; 1476 1477 /** 1478 * struct ionic_port_status - Port Status information 1479 * @status: link status (enum ionic_port_oper_status) 1480 * @id: port id 1481 * @speed: link speed (in Mbps) 1482 * @link_down_count: number of times link went from up to down 1483 * @fec_type: fec type (enum ionic_port_fec_type) 1484 * @rsvd: reserved byte(s) 1485 * @xcvr: transceiver status 1486 */ 1487 struct ionic_port_status { 1488 __le32 id; 1489 __le32 speed; 1490 u8 status; 1491 __le16 link_down_count; 1492 u8 fec_type; 1493 u8 rsvd[48]; 1494 struct ionic_xcvr_status xcvr; 1495 } __packed; 1496 1497 /** 1498 * struct ionic_port_identify_cmd - Port identify command 1499 * @opcode: opcode 1500 * @index: port index 1501 * @ver: Highest version of identify supported by driver 1502 * @rsvd: reserved byte(s) 1503 */ 1504 struct ionic_port_identify_cmd { 1505 u8 opcode; 1506 u8 index; 1507 u8 ver; 1508 u8 rsvd[61]; 1509 }; 1510 1511 /** 1512 * struct ionic_port_identify_comp - Port identify command completion 1513 * @status: Status of the command (enum ionic_status_code) 1514 * @ver: Version of identify returned by device 1515 * @rsvd: reserved byte(s) 1516 */ 1517 struct ionic_port_identify_comp { 1518 u8 status; 1519 u8 ver; 1520 u8 rsvd[14]; 1521 }; 1522 1523 /** 1524 * struct ionic_port_init_cmd - Port initialization command 1525 * @opcode: opcode 1526 * @index: port index 1527 * @rsvd: reserved byte(s) 1528 * @info_pa: destination address for port info (struct ionic_port_info) 1529 * @rsvd2: reserved byte(s) 1530 */ 1531 struct ionic_port_init_cmd { 1532 u8 opcode; 1533 u8 index; 1534 u8 rsvd[6]; 1535 __le64 info_pa; 1536 u8 rsvd2[48]; 1537 }; 1538 1539 /** 1540 * struct ionic_port_init_comp - Port initialization command completion 1541 * @status: Status of the command (enum ionic_status_code) 1542 * @rsvd: reserved byte(s) 1543 */ 1544 struct ionic_port_init_comp { 1545 u8 status; 1546 u8 rsvd[15]; 1547 }; 1548 1549 /** 1550 * struct ionic_port_reset_cmd - Port reset command 1551 * @opcode: opcode 1552 * @index: port index 1553 * @rsvd: reserved byte(s) 1554 */ 1555 struct ionic_port_reset_cmd { 1556 u8 opcode; 1557 u8 index; 1558 u8 rsvd[62]; 1559 }; 1560 1561 /** 1562 * struct ionic_port_reset_comp - Port reset command completion 1563 * @status: Status of the command (enum ionic_status_code) 1564 * @rsvd: reserved byte(s) 1565 */ 1566 struct ionic_port_reset_comp { 1567 u8 status; 1568 u8 rsvd[15]; 1569 }; 1570 1571 /** 1572 * enum ionic_stats_ctl_cmd - List of commands for stats control 1573 * @IONIC_STATS_CTL_RESET: Reset statistics 1574 */ 1575 enum ionic_stats_ctl_cmd { 1576 IONIC_STATS_CTL_RESET = 0, 1577 }; 1578 1579 /** 1580 * enum ionic_txstamp_mode - List of TX Timestamping Modes 1581 * @IONIC_TXSTAMP_OFF: Disable TX hardware timetamping. 1582 * @IONIC_TXSTAMP_ON: Enable local TX hardware timetamping. 1583 * @IONIC_TXSTAMP_ONESTEP_SYNC: Modify TX PTP Sync packets. 1584 * @IONIC_TXSTAMP_ONESTEP_P2P: Modify TX PTP Sync and PDelayResp. 1585 */ 1586 enum ionic_txstamp_mode { 1587 IONIC_TXSTAMP_OFF = 0, 1588 IONIC_TXSTAMP_ON = 1, 1589 IONIC_TXSTAMP_ONESTEP_SYNC = 2, 1590 IONIC_TXSTAMP_ONESTEP_P2P = 3, 1591 }; 1592 1593 /** 1594 * enum ionic_port_attr - List of device attributes 1595 * @IONIC_PORT_ATTR_STATE: Port state attribute 1596 * @IONIC_PORT_ATTR_SPEED: Port speed attribute 1597 * @IONIC_PORT_ATTR_MTU: Port MTU attribute 1598 * @IONIC_PORT_ATTR_AUTONEG: Port autonegotiation attribute 1599 * @IONIC_PORT_ATTR_FEC: Port FEC attribute 1600 * @IONIC_PORT_ATTR_PAUSE: Port pause attribute 1601 * @IONIC_PORT_ATTR_LOOPBACK: Port loopback attribute 1602 * @IONIC_PORT_ATTR_STATS_CTRL: Port statistics control attribute 1603 */ 1604 enum ionic_port_attr { 1605 IONIC_PORT_ATTR_STATE = 0, 1606 IONIC_PORT_ATTR_SPEED = 1, 1607 IONIC_PORT_ATTR_MTU = 2, 1608 IONIC_PORT_ATTR_AUTONEG = 3, 1609 IONIC_PORT_ATTR_FEC = 4, 1610 IONIC_PORT_ATTR_PAUSE = 5, 1611 IONIC_PORT_ATTR_LOOPBACK = 6, 1612 IONIC_PORT_ATTR_STATS_CTRL = 7, 1613 }; 1614 1615 /** 1616 * struct ionic_port_setattr_cmd - Set port attributes on the NIC 1617 * @opcode: Opcode 1618 * @index: Port index 1619 * @attr: Attribute type (enum ionic_port_attr) 1620 * @rsvd: reserved byte(s) 1621 * @state: Port state 1622 * @speed: Port speed 1623 * @mtu: Port MTU 1624 * @an_enable: Port autonegotiation setting 1625 * @fec_type: Port FEC type setting 1626 * @pause_type: Port pause type setting 1627 * @loopback_mode: Port loopback mode 1628 * @stats_ctl: Port stats setting 1629 * @rsvd2: reserved byte(s) 1630 */ 1631 struct ionic_port_setattr_cmd { 1632 u8 opcode; 1633 u8 index; 1634 u8 attr; 1635 u8 rsvd; 1636 union { 1637 u8 state; 1638 __le32 speed; 1639 __le32 mtu; 1640 u8 an_enable; 1641 u8 fec_type; 1642 u8 pause_type; 1643 u8 loopback_mode; 1644 u8 stats_ctl; 1645 u8 rsvd2[60]; 1646 }; 1647 }; 1648 1649 /** 1650 * struct ionic_port_setattr_comp - Port set attr command completion 1651 * @status: Status of the command (enum ionic_status_code) 1652 * @rsvd: reserved byte(s) 1653 * @color: Color bit 1654 */ 1655 struct ionic_port_setattr_comp { 1656 u8 status; 1657 u8 rsvd[14]; 1658 u8 color; 1659 }; 1660 1661 /** 1662 * struct ionic_port_getattr_cmd - Get port attributes from the NIC 1663 * @opcode: Opcode 1664 * @index: port index 1665 * @attr: Attribute type (enum ionic_port_attr) 1666 * @rsvd: reserved byte(s) 1667 */ 1668 struct ionic_port_getattr_cmd { 1669 u8 opcode; 1670 u8 index; 1671 u8 attr; 1672 u8 rsvd[61]; 1673 }; 1674 1675 /** 1676 * struct ionic_port_getattr_comp - Port get attr command completion 1677 * @status: Status of the command (enum ionic_status_code) 1678 * @rsvd: reserved byte(s) 1679 * @state: Port state 1680 * @speed: Port speed 1681 * @mtu: Port MTU 1682 * @an_enable: Port autonegotiation setting 1683 * @fec_type: Port FEC type setting 1684 * @pause_type: Port pause type setting 1685 * @loopback_mode: Port loopback mode 1686 * @rsvd2: reserved byte(s) 1687 * @color: Color bit 1688 */ 1689 struct ionic_port_getattr_comp { 1690 u8 status; 1691 u8 rsvd[3]; 1692 union { 1693 u8 state; 1694 __le32 speed; 1695 __le32 mtu; 1696 u8 an_enable; 1697 u8 fec_type; 1698 u8 pause_type; 1699 u8 loopback_mode; 1700 u8 rsvd2[11]; 1701 } __packed; 1702 u8 color; 1703 }; 1704 1705 /** 1706 * struct ionic_lif_status - LIF status register 1707 * @eid: most recent NotifyQ event id 1708 * @port_num: port the LIF is connected to 1709 * @rsvd: reserved byte(s) 1710 * @link_status: port status (enum ionic_port_oper_status) 1711 * @link_speed: speed of link in Mbps 1712 * @link_down_count: number of times link went from up to down 1713 * @rsvd2: reserved byte(s) 1714 */ 1715 struct ionic_lif_status { 1716 __le64 eid; 1717 u8 port_num; 1718 u8 rsvd; 1719 __le16 link_status; 1720 __le32 link_speed; /* units of 1Mbps: eg 10000 = 10Gbps */ 1721 __le16 link_down_count; 1722 u8 rsvd2[46]; 1723 }; 1724 1725 /** 1726 * struct ionic_lif_reset_cmd - LIF reset command 1727 * @opcode: opcode 1728 * @rsvd: reserved byte(s) 1729 * @index: LIF index 1730 * @rsvd2: reserved byte(s) 1731 */ 1732 struct ionic_lif_reset_cmd { 1733 u8 opcode; 1734 u8 rsvd; 1735 __le16 index; 1736 __le32 rsvd2[15]; 1737 }; 1738 1739 typedef struct ionic_admin_comp ionic_lif_reset_comp; 1740 1741 enum ionic_dev_state { 1742 IONIC_DEV_DISABLE = 0, 1743 IONIC_DEV_ENABLE = 1, 1744 IONIC_DEV_HANG_RESET = 2, 1745 }; 1746 1747 /** 1748 * enum ionic_dev_attr - List of device attributes 1749 * @IONIC_DEV_ATTR_STATE: Device state attribute 1750 * @IONIC_DEV_ATTR_NAME: Device name attribute 1751 * @IONIC_DEV_ATTR_FEATURES: Device feature attributes 1752 */ 1753 enum ionic_dev_attr { 1754 IONIC_DEV_ATTR_STATE = 0, 1755 IONIC_DEV_ATTR_NAME = 1, 1756 IONIC_DEV_ATTR_FEATURES = 2, 1757 }; 1758 1759 /** 1760 * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC 1761 * @opcode: Opcode 1762 * @attr: Attribute type (enum ionic_dev_attr) 1763 * @rsvd: reserved byte(s) 1764 * @state: Device state (enum ionic_dev_state) 1765 * @name: The bus info, e.g. PCI slot-device-function, 0 terminated 1766 * @features: Device features 1767 * @rsvd2: reserved byte(s) 1768 */ 1769 struct ionic_dev_setattr_cmd { 1770 u8 opcode; 1771 u8 attr; 1772 __le16 rsvd; 1773 union { 1774 u8 state; 1775 char name[IONIC_IFNAMSIZ]; 1776 __le64 features; 1777 u8 rsvd2[60]; 1778 } __packed; 1779 }; 1780 1781 /** 1782 * struct ionic_dev_setattr_comp - Device set attr command completion 1783 * @status: Status of the command (enum ionic_status_code) 1784 * @rsvd: reserved byte(s) 1785 * @features: Device features 1786 * @rsvd2: reserved byte(s) 1787 * @color: Color bit 1788 */ 1789 struct ionic_dev_setattr_comp { 1790 u8 status; 1791 u8 rsvd[3]; 1792 union { 1793 __le64 features; 1794 u8 rsvd2[11]; 1795 } __packed; 1796 u8 color; 1797 }; 1798 1799 /** 1800 * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC 1801 * @opcode: opcode 1802 * @attr: Attribute type (enum ionic_dev_attr) 1803 * @rsvd: reserved byte(s) 1804 */ 1805 struct ionic_dev_getattr_cmd { 1806 u8 opcode; 1807 u8 attr; 1808 u8 rsvd[62]; 1809 }; 1810 1811 /** 1812 * struct ionic_dev_getattr_comp - Device set attr command completion 1813 * @status: Status of the command (enum ionic_status_code) 1814 * @rsvd: reserved byte(s) 1815 * @features: Device features 1816 * @rsvd2: reserved byte(s) 1817 * @color: Color bit 1818 */ 1819 struct ionic_dev_getattr_comp { 1820 u8 status; 1821 u8 rsvd[3]; 1822 union { 1823 __le64 features; 1824 u8 rsvd2[11]; 1825 } __packed; 1826 u8 color; 1827 }; 1828 1829 /* 1830 * RSS parameters 1831 */ 1832 #define IONIC_RSS_HASH_KEY_SIZE 40 1833 1834 enum ionic_rss_hash_types { 1835 IONIC_RSS_TYPE_IPV4 = BIT(0), 1836 IONIC_RSS_TYPE_IPV4_TCP = BIT(1), 1837 IONIC_RSS_TYPE_IPV4_UDP = BIT(2), 1838 IONIC_RSS_TYPE_IPV6 = BIT(3), 1839 IONIC_RSS_TYPE_IPV6_TCP = BIT(4), 1840 IONIC_RSS_TYPE_IPV6_UDP = BIT(5), 1841 }; 1842 1843 /** 1844 * enum ionic_lif_attr - List of LIF attributes 1845 * @IONIC_LIF_ATTR_STATE: LIF state attribute 1846 * @IONIC_LIF_ATTR_NAME: LIF name attribute 1847 * @IONIC_LIF_ATTR_MTU: LIF MTU attribute 1848 * @IONIC_LIF_ATTR_MAC: LIF MAC attribute 1849 * @IONIC_LIF_ATTR_FEATURES: LIF features attribute 1850 * @IONIC_LIF_ATTR_RSS: LIF RSS attribute 1851 * @IONIC_LIF_ATTR_STATS_CTRL: LIF statistics control attribute 1852 * @IONIC_LIF_ATTR_TXSTAMP: LIF TX timestamping mode 1853 * @IONIC_LIF_ATTR_MAX: maximum attribute value 1854 */ 1855 enum ionic_lif_attr { 1856 IONIC_LIF_ATTR_STATE = 0, 1857 IONIC_LIF_ATTR_NAME = 1, 1858 IONIC_LIF_ATTR_MTU = 2, 1859 IONIC_LIF_ATTR_MAC = 3, 1860 IONIC_LIF_ATTR_FEATURES = 4, 1861 IONIC_LIF_ATTR_RSS = 5, 1862 IONIC_LIF_ATTR_STATS_CTRL = 6, 1863 IONIC_LIF_ATTR_TXSTAMP = 7, 1864 IONIC_LIF_ATTR_MAX = 255, 1865 }; 1866 1867 /** 1868 * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC 1869 * @opcode: Opcode 1870 * @attr: Attribute type (enum ionic_lif_attr) 1871 * @index: LIF index 1872 * @state: LIF state (enum ionic_lif_state) 1873 * @name: The netdev name string, 0 terminated 1874 * @mtu: Mtu 1875 * @mac: Station mac 1876 * @features: Features (enum ionic_eth_hw_features) 1877 * @rss: RSS properties 1878 * @rss.types: The hash types to enable (see rss_hash_types) 1879 * @rss.key: The hash secret key 1880 * @rss.rsvd: reserved byte(s) 1881 * @rss.addr: Address for the indirection table shared memory 1882 * @stats_ctl: stats control commands (enum ionic_stats_ctl_cmd) 1883 * @txstamp_mode: TX Timestamping Mode (enum ionic_txstamp_mode) 1884 * @rsvd: reserved byte(s) 1885 */ 1886 struct ionic_lif_setattr_cmd { 1887 u8 opcode; 1888 u8 attr; 1889 __le16 index; 1890 union { 1891 u8 state; 1892 char name[IONIC_IFNAMSIZ]; 1893 __le32 mtu; 1894 u8 mac[6]; 1895 __le64 features; 1896 struct { 1897 __le16 types; 1898 u8 key[IONIC_RSS_HASH_KEY_SIZE]; 1899 u8 rsvd[6]; 1900 __le64 addr; 1901 } rss; 1902 u8 stats_ctl; 1903 __le16 txstamp_mode; 1904 u8 rsvd[60]; 1905 } __packed; 1906 }; 1907 1908 /** 1909 * struct ionic_lif_setattr_comp - LIF set attr command completion 1910 * @status: Status of the command (enum ionic_status_code) 1911 * @rsvd: reserved byte(s) 1912 * @comp_index: Index in the descriptor ring for which this is the completion 1913 * @features: features (enum ionic_eth_hw_features) 1914 * @rsvd2: reserved byte(s) 1915 * @color: Color bit 1916 */ 1917 struct ionic_lif_setattr_comp { 1918 u8 status; 1919 u8 rsvd; 1920 __le16 comp_index; 1921 union { 1922 __le64 features; 1923 u8 rsvd2[11]; 1924 } __packed; 1925 u8 color; 1926 }; 1927 1928 /** 1929 * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC 1930 * @opcode: Opcode 1931 * @attr: Attribute type (enum ionic_lif_attr) 1932 * @index: LIF index 1933 * @rsvd: reserved byte(s) 1934 */ 1935 struct ionic_lif_getattr_cmd { 1936 u8 opcode; 1937 u8 attr; 1938 __le16 index; 1939 u8 rsvd[60]; 1940 }; 1941 1942 /** 1943 * struct ionic_lif_getattr_comp - LIF get attr command completion 1944 * @status: Status of the command (enum ionic_status_code) 1945 * @rsvd: reserved byte(s) 1946 * @comp_index: Index in the descriptor ring for which this is the completion 1947 * @state: LIF state (enum ionic_lif_state) 1948 * @mtu: Mtu 1949 * @mac: Station mac 1950 * @features: Features (enum ionic_eth_hw_features) 1951 * @txstamp_mode: TX Timestamping Mode (enum ionic_txstamp_mode) 1952 * @rsvd2: reserved byte(s) 1953 * @color: Color bit 1954 */ 1955 struct ionic_lif_getattr_comp { 1956 u8 status; 1957 u8 rsvd; 1958 __le16 comp_index; 1959 union { 1960 u8 state; 1961 __le32 mtu; 1962 u8 mac[6]; 1963 __le64 features; 1964 __le16 txstamp_mode; 1965 u8 rsvd2[11]; 1966 } __packed; 1967 u8 color; 1968 }; 1969 1970 /** 1971 * struct ionic_lif_setphc_cmd - Set LIF PTP Hardware Clock 1972 * @opcode: Opcode 1973 * @rsvd1: reserved byte(s) 1974 * @lif_index: LIF index 1975 * @rsvd2: reserved byte(s) 1976 * @tick: Hardware stamp tick of an instant in time. 1977 * @nsec: Nanosecond stamp of the same instant. 1978 * @frac: Fractional nanoseconds at the same instant. 1979 * @mult: Cycle to nanosecond multiplier. 1980 * @shift: Cycle to nanosecond divisor (power of two). 1981 * @rsvd3: reserved byte(s) 1982 */ 1983 struct ionic_lif_setphc_cmd { 1984 u8 opcode; 1985 u8 rsvd1; 1986 __le16 lif_index; 1987 u8 rsvd2[4]; 1988 __le64 tick; 1989 __le64 nsec; 1990 __le64 frac; 1991 __le32 mult; 1992 __le32 shift; 1993 u8 rsvd3[24]; 1994 }; 1995 1996 enum ionic_rx_mode { 1997 IONIC_RX_MODE_F_UNICAST = BIT(0), 1998 IONIC_RX_MODE_F_MULTICAST = BIT(1), 1999 IONIC_RX_MODE_F_BROADCAST = BIT(2), 2000 IONIC_RX_MODE_F_PROMISC = BIT(3), 2001 IONIC_RX_MODE_F_ALLMULTI = BIT(4), 2002 IONIC_RX_MODE_F_RDMA_SNIFFER = BIT(5), 2003 }; 2004 2005 /** 2006 * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command 2007 * @opcode: opcode 2008 * @rsvd: reserved byte(s) 2009 * @lif_index: LIF index 2010 * @rx_mode: Rx mode flags: 2011 * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets 2012 * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets 2013 * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets 2014 * IONIC_RX_MODE_F_PROMISC: Accept any packets 2015 * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets 2016 * IONIC_RX_MODE_F_RDMA_SNIFFER: Sniff RDMA packets 2017 * @rsvd2: reserved byte(s) 2018 */ 2019 struct ionic_rx_mode_set_cmd { 2020 u8 opcode; 2021 u8 rsvd; 2022 __le16 lif_index; 2023 __le16 rx_mode; 2024 __le16 rsvd2[29]; 2025 }; 2026 2027 typedef struct ionic_admin_comp ionic_rx_mode_set_comp; 2028 2029 enum ionic_rx_filter_match_type { 2030 IONIC_RX_FILTER_MATCH_VLAN = 0x0, 2031 IONIC_RX_FILTER_MATCH_MAC = 0x1, 2032 IONIC_RX_FILTER_MATCH_MAC_VLAN = 0x2, 2033 IONIC_RX_FILTER_STEER_PKTCLASS = 0x10, 2034 }; 2035 2036 /** 2037 * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command 2038 * @opcode: opcode 2039 * @qtype: Queue type 2040 * @lif_index: LIF index 2041 * @qid: Queue ID 2042 * @match: Rx filter match type (see IONIC_RX_FILTER_MATCH_xxx) 2043 * @vlan: VLAN filter 2044 * @vlan.vlan: VLAN ID 2045 * @mac: MAC filter 2046 * @mac.addr: MAC address (network-byte order) 2047 * @mac_vlan: MACVLAN filter 2048 * @mac_vlan.vlan: VLAN ID 2049 * @mac_vlan.addr: MAC address (network-byte order) 2050 * @pkt_class: Packet classification filter 2051 * @rsvd: reserved byte(s) 2052 */ 2053 struct ionic_rx_filter_add_cmd { 2054 u8 opcode; 2055 u8 qtype; 2056 __le16 lif_index; 2057 __le32 qid; 2058 __le16 match; 2059 union { 2060 struct { 2061 __le16 vlan; 2062 } vlan; 2063 struct { 2064 u8 addr[6]; 2065 } mac; 2066 struct { 2067 __le16 vlan; 2068 u8 addr[6]; 2069 } mac_vlan; 2070 __le64 pkt_class; 2071 u8 rsvd[54]; 2072 } __packed; 2073 }; 2074 2075 /** 2076 * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion 2077 * @status: Status of the command (enum ionic_status_code) 2078 * @rsvd: reserved byte(s) 2079 * @comp_index: Index in the descriptor ring for which this is the completion 2080 * @filter_id: Filter ID 2081 * @rsvd2: reserved byte(s) 2082 * @color: Color bit 2083 */ 2084 struct ionic_rx_filter_add_comp { 2085 u8 status; 2086 u8 rsvd; 2087 __le16 comp_index; 2088 __le32 filter_id; 2089 u8 rsvd2[7]; 2090 u8 color; 2091 }; 2092 2093 /** 2094 * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command 2095 * @opcode: opcode 2096 * @rsvd: reserved byte(s) 2097 * @lif_index: LIF index 2098 * @filter_id: Filter ID 2099 * @rsvd2: reserved byte(s) 2100 */ 2101 struct ionic_rx_filter_del_cmd { 2102 u8 opcode; 2103 u8 rsvd; 2104 __le16 lif_index; 2105 __le32 filter_id; 2106 u8 rsvd2[56]; 2107 }; 2108 2109 typedef struct ionic_admin_comp ionic_rx_filter_del_comp; 2110 2111 enum ionic_vf_attr { 2112 IONIC_VF_ATTR_SPOOFCHK = 1, 2113 IONIC_VF_ATTR_TRUST = 2, 2114 IONIC_VF_ATTR_MAC = 3, 2115 IONIC_VF_ATTR_LINKSTATE = 4, 2116 IONIC_VF_ATTR_VLAN = 5, 2117 IONIC_VF_ATTR_RATE = 6, 2118 IONIC_VF_ATTR_STATSADDR = 7, 2119 }; 2120 2121 /** 2122 * enum ionic_vf_link_status - Virtual Function link status 2123 * @IONIC_VF_LINK_STATUS_AUTO: Use link state of the uplink 2124 * @IONIC_VF_LINK_STATUS_UP: Link always up 2125 * @IONIC_VF_LINK_STATUS_DOWN: Link always down 2126 */ 2127 enum ionic_vf_link_status { 2128 IONIC_VF_LINK_STATUS_AUTO = 0, 2129 IONIC_VF_LINK_STATUS_UP = 1, 2130 IONIC_VF_LINK_STATUS_DOWN = 2, 2131 }; 2132 2133 /** 2134 * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC 2135 * @opcode: Opcode 2136 * @attr: Attribute type (enum ionic_vf_attr) 2137 * @vf_index: VF index 2138 * @macaddr: mac address 2139 * @vlanid: vlan ID 2140 * @maxrate: max Tx rate in Mbps 2141 * @spoofchk: enable address spoof checking 2142 * @trust: enable VF trust 2143 * @linkstate: set link up or down 2144 * @stats_pa: set DMA address for VF stats 2145 * @pad: reserved byte(s) 2146 */ 2147 struct ionic_vf_setattr_cmd { 2148 u8 opcode; 2149 u8 attr; 2150 __le16 vf_index; 2151 union { 2152 u8 macaddr[6]; 2153 __le16 vlanid; 2154 __le32 maxrate; 2155 u8 spoofchk; 2156 u8 trust; 2157 u8 linkstate; 2158 __le64 stats_pa; 2159 u8 pad[60]; 2160 } __packed; 2161 }; 2162 2163 struct ionic_vf_setattr_comp { 2164 u8 status; 2165 u8 attr; 2166 __le16 vf_index; 2167 __le16 comp_index; 2168 u8 rsvd[9]; 2169 u8 color; 2170 }; 2171 2172 /** 2173 * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC 2174 * @opcode: Opcode 2175 * @attr: Attribute type (enum ionic_vf_attr) 2176 * @vf_index: VF index 2177 * @rsvd: reserved byte(s) 2178 */ 2179 struct ionic_vf_getattr_cmd { 2180 u8 opcode; 2181 u8 attr; 2182 __le16 vf_index; 2183 u8 rsvd[60]; 2184 }; 2185 2186 struct ionic_vf_getattr_comp { 2187 u8 status; 2188 u8 attr; 2189 __le16 vf_index; 2190 union { 2191 u8 macaddr[6]; 2192 __le16 vlanid; 2193 __le32 maxrate; 2194 u8 spoofchk; 2195 u8 trust; 2196 u8 linkstate; 2197 __le64 stats_pa; 2198 u8 pad[11]; 2199 } __packed; 2200 u8 color; 2201 }; 2202 2203 enum ionic_vf_ctrl_opcode { 2204 IONIC_VF_CTRL_START_ALL = 0, 2205 IONIC_VF_CTRL_START = 1, 2206 }; 2207 2208 /** 2209 * struct ionic_vf_ctrl_cmd - VF control command 2210 * @opcode: Opcode for the command 2211 * @ctrl_opcode: VF control operation type 2212 * @vf_index: VF Index. It is unused if op START_ALL is used. 2213 */ 2214 struct ionic_vf_ctrl_cmd { 2215 u8 opcode; 2216 u8 ctrl_opcode; 2217 __le16 vf_index; 2218 /* private: */ 2219 u8 rsvd1[60]; 2220 }; 2221 2222 /** 2223 * struct ionic_vf_ctrl_comp - VF_CTRL command completion. 2224 * @status: Status of the command (enum ionic_status_code) 2225 */ 2226 struct ionic_vf_ctrl_comp { 2227 u8 status; 2228 /* private: */ 2229 u8 rsvd[15]; 2230 }; 2231 2232 /** 2233 * struct ionic_discover_cmb_cmd - CMB discovery command 2234 * @opcode: Opcode for the command 2235 * @rsvd: Reserved bytes 2236 */ 2237 struct ionic_discover_cmb_cmd { 2238 u8 opcode; 2239 u8 rsvd[63]; 2240 }; 2241 2242 /** 2243 * struct ionic_discover_cmb_comp - CMB discover command completion. 2244 * @status: Status of the command (enum ionic_status_code) 2245 * @rsvd: Reserved bytes 2246 */ 2247 struct ionic_discover_cmb_comp { 2248 u8 status; 2249 u8 rsvd[15]; 2250 }; 2251 2252 #define IONIC_MAX_CMB_REGIONS 16 2253 #define IONIC_CMB_SHIFT_64K 16 2254 2255 enum ionic_cmb_type { 2256 IONIC_CMB_TYPE_DEVMEM = 0, 2257 IONIC_CMB_TYPE_EXPDB64 = 1, 2258 IONIC_CMB_TYPE_EXPDB128 = 2, 2259 IONIC_CMB_TYPE_EXPDB256 = 3, 2260 IONIC_CMB_TYPE_EXPDB512 = 4, 2261 }; 2262 2263 /** 2264 * union ionic_cmb_region - Configuration for CMB region 2265 * @bar_num: CMB mapping number from FW 2266 * @cmb_type: Type of CMB this region describes (enum ionic_cmb_type) 2267 * @rsvd: Reserved 2268 * @offset: Offset within BAR in 64KB pages 2269 * @length: Length of the CMB region 2270 * @words: 32-bit words for direct access to the entire region 2271 */ 2272 union ionic_cmb_region { 2273 struct { 2274 u8 bar_num; 2275 u8 cmb_type; 2276 u8 rsvd[6]; 2277 __le32 offset; 2278 __le32 length; 2279 } __packed; 2280 __le32 words[4]; 2281 }; 2282 2283 /** 2284 * union ionic_discover_cmb_identity - CMB layout identity structure 2285 * @num_regions: Number of CMB regions, up to 16 2286 * @flags: Feature and capability bits (0 for express 2287 * doorbell, 1 for 4K alignment indicator, 2288 * 31-24 for version information) 2289 * @region: CMB mappings region, entry 0 for regular 2290 * mapping, entries 1-7 for WQE sizes 64, 2291 * 128, 256, 512, 1024, 2048 and 4096 bytes 2292 * @words: Full union buffer size 2293 */ 2294 union ionic_discover_cmb_identity { 2295 struct { 2296 __le32 num_regions; 2297 #define IONIC_CMB_FLAG_EXPDB BIT(0) 2298 #define IONIC_CMB_FLAG_4KALIGN BIT(1) 2299 #define IONIC_CMB_FLAG_VERSION 0xff000000 2300 __le32 flags; 2301 union ionic_cmb_region region[IONIC_MAX_CMB_REGIONS]; 2302 }; 2303 __le32 words[478]; 2304 }; 2305 2306 /** 2307 * struct ionic_qos_identify_cmd - QoS identify command 2308 * @opcode: opcode 2309 * @ver: Highest version of identify supported by driver 2310 * @rsvd: reserved byte(s) 2311 */ 2312 struct ionic_qos_identify_cmd { 2313 u8 opcode; 2314 u8 ver; 2315 u8 rsvd[62]; 2316 }; 2317 2318 /** 2319 * struct ionic_qos_identify_comp - QoS identify command completion 2320 * @status: Status of the command (enum ionic_status_code) 2321 * @ver: Version of identify returned by device 2322 * @rsvd: reserved byte(s) 2323 */ 2324 struct ionic_qos_identify_comp { 2325 u8 status; 2326 u8 ver; 2327 u8 rsvd[14]; 2328 }; 2329 2330 #define IONIC_QOS_TC_MAX 8 2331 #define IONIC_QOS_ALL_TC 0xFF 2332 /* Capri max supported, should be renamed. */ 2333 #define IONIC_QOS_CLASS_MAX 7 2334 #define IONIC_QOS_PCP_MAX 8 2335 #define IONIC_QOS_CLASS_NAME_SZ 32 2336 #define IONIC_QOS_DSCP_MAX 64 2337 #define IONIC_QOS_ALL_PCP 0xFF 2338 #define IONIC_DSCP_BLOCK_SIZE 8 2339 2340 /* 2341 * enum ionic_qos_class 2342 */ 2343 enum ionic_qos_class { 2344 IONIC_QOS_CLASS_DEFAULT = 0, 2345 IONIC_QOS_CLASS_USER_DEFINED_1 = 1, 2346 IONIC_QOS_CLASS_USER_DEFINED_2 = 2, 2347 IONIC_QOS_CLASS_USER_DEFINED_3 = 3, 2348 IONIC_QOS_CLASS_USER_DEFINED_4 = 4, 2349 IONIC_QOS_CLASS_USER_DEFINED_5 = 5, 2350 IONIC_QOS_CLASS_USER_DEFINED_6 = 6, 2351 }; 2352 2353 /** 2354 * enum ionic_qos_class_type - Traffic classification criteria 2355 * @IONIC_QOS_CLASS_TYPE_NONE: No QoS 2356 * @IONIC_QOS_CLASS_TYPE_PCP: Dot1Q PCP 2357 * @IONIC_QOS_CLASS_TYPE_DSCP: IP DSCP 2358 */ 2359 enum ionic_qos_class_type { 2360 IONIC_QOS_CLASS_TYPE_NONE = 0, 2361 IONIC_QOS_CLASS_TYPE_PCP = 1, 2362 IONIC_QOS_CLASS_TYPE_DSCP = 2, 2363 }; 2364 2365 /** 2366 * enum ionic_qos_sched_type - QoS class scheduling type 2367 * @IONIC_QOS_SCHED_TYPE_STRICT: Strict priority 2368 * @IONIC_QOS_SCHED_TYPE_DWRR: Deficit weighted round-robin 2369 */ 2370 enum ionic_qos_sched_type { 2371 IONIC_QOS_SCHED_TYPE_STRICT = 0, 2372 IONIC_QOS_SCHED_TYPE_DWRR = 1, 2373 }; 2374 2375 /** 2376 * union ionic_qos_config - QoS configuration structure 2377 * @flags: Configuration flags 2378 * IONIC_QOS_CONFIG_F_ENABLE enable 2379 * IONIC_QOS_CONFIG_F_NO_DROP drop/nodrop 2380 * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite 2381 * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite 2382 * IONIC_QOS_CONFIG_F_NON_DISRUPTIVE Non-disruptive TC update 2383 * @sched_type: QoS class scheduling type (enum ionic_qos_sched_type) 2384 * @class_type: QoS class type (enum ionic_qos_class_type) 2385 * @pause_type: QoS pause type (enum ionic_qos_pause_type) 2386 * @name: QoS class name 2387 * @mtu: MTU of the class 2388 * @pfc_cos: Priority-Flow Control class of service 2389 * @dwrr_weight: QoS class scheduling weight 2390 * @strict_rlmt: Rate limit for strict priority scheduling 2391 * @rw_dot1q_pcp: Rewrite dot1q pcp to value (valid iff F_RW_DOT1Q_PCP) 2392 * @rw_ip_dscp: Rewrite ip dscp to value (valid iff F_RW_IP_DSCP) 2393 * @dot1q_pcp: Dot1q pcp value 2394 * @ndscp: Number of valid dscp values in the ip_dscp field 2395 * @ip_dscp: IP dscp values 2396 * @words: word access to struct contents 2397 */ 2398 union ionic_qos_config { 2399 struct { 2400 #define IONIC_QOS_CONFIG_F_ENABLE BIT(0) 2401 #define IONIC_QOS_CONFIG_F_NO_DROP BIT(1) 2402 /* Used to rewrite PCP or DSCP value. */ 2403 #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2) 2404 #define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3) 2405 /* Non-disruptive TC update */ 2406 #define IONIC_QOS_CONFIG_F_NON_DISRUPTIVE BIT(4) 2407 u8 flags; 2408 u8 sched_type; 2409 u8 class_type; 2410 u8 pause_type; 2411 char name[IONIC_QOS_CLASS_NAME_SZ]; 2412 __le32 mtu; 2413 /* flow control */ 2414 u8 pfc_cos; 2415 /* scheduler */ 2416 union { 2417 u8 dwrr_weight; 2418 __le64 strict_rlmt; 2419 }; 2420 /* marking */ 2421 /* Used to rewrite PCP or DSCP value. */ 2422 union { 2423 u8 rw_dot1q_pcp; 2424 u8 rw_ip_dscp; 2425 }; 2426 /* classification */ 2427 union { 2428 u8 dot1q_pcp; 2429 struct { 2430 u8 ndscp; 2431 u8 ip_dscp[IONIC_QOS_DSCP_MAX]; 2432 }; 2433 }; 2434 }; 2435 __le32 words[64]; 2436 }; 2437 2438 /** 2439 * union ionic_qos_identity - QoS identity structure 2440 * @version: Version of the identify structure 2441 * @type: QoS system type 2442 * @rsvd: reserved byte(s) 2443 * @config: Current configuration of classes 2444 * @words: word access to struct contents 2445 */ 2446 union ionic_qos_identity { 2447 struct { 2448 u8 version; 2449 u8 type; 2450 u8 rsvd[62]; 2451 union ionic_qos_config config[IONIC_QOS_CLASS_MAX]; 2452 }; 2453 __le32 words[478]; 2454 }; 2455 2456 /** 2457 * struct ionic_qos_init_cmd - QoS config init command 2458 * @opcode: Opcode 2459 * @group: QoS class id 2460 * @rsvd: reserved byte(s) 2461 * @info_pa: destination address for qos info 2462 * @rsvd1: reserved byte(s) 2463 */ 2464 struct ionic_qos_init_cmd { 2465 u8 opcode; 2466 u8 group; 2467 u8 rsvd[6]; 2468 __le64 info_pa; 2469 u8 rsvd1[48]; 2470 }; 2471 2472 typedef struct ionic_admin_comp ionic_qos_init_comp; 2473 2474 /** 2475 * struct ionic_qos_reset_cmd - QoS config reset command 2476 * @opcode: Opcode 2477 * @group: QoS class id 2478 * @rsvd: reserved byte(s) 2479 */ 2480 struct ionic_qos_reset_cmd { 2481 u8 opcode; 2482 u8 group; 2483 u8 rsvd[62]; 2484 }; 2485 2486 /** 2487 * struct ionic_qos_clear_stats_cmd - Qos config reset command 2488 * @opcode: Opcode 2489 * @group_bitmap: bitmap of groups to be cleared 2490 * @rsvd: reserved byte(s) 2491 */ 2492 struct ionic_qos_clear_stats_cmd { 2493 u8 opcode; 2494 u8 group_bitmap; 2495 u8 rsvd[62]; 2496 }; 2497 2498 typedef struct ionic_admin_comp ionic_qos_reset_comp; 2499 2500 /** 2501 * struct ionic_fw_download_cmd - Firmware download command 2502 * @opcode: opcode 2503 * @rsvd: reserved byte(s) 2504 * @addr: dma address of the firmware buffer 2505 * @offset: offset of the firmware buffer within the full image 2506 * @length: number of valid bytes in the firmware buffer 2507 */ 2508 struct ionic_fw_download_cmd { 2509 u8 opcode; 2510 u8 rsvd[3]; 2511 __le32 offset; 2512 __le64 addr; 2513 __le32 length; 2514 }; 2515 2516 typedef struct ionic_admin_comp ionic_fw_download_comp; 2517 2518 /** 2519 * enum ionic_fw_control_oper - FW control operations 2520 * @IONIC_FW_RESET: Reset firmware 2521 * @IONIC_FW_INSTALL: Install firmware 2522 * @IONIC_FW_ACTIVATE: Activate firmware 2523 * @IONIC_FW_INSTALL_ASYNC: Install firmware asynchronously 2524 * @IONIC_FW_INSTALL_STATUS: Firmware installation status 2525 * @IONIC_FW_ACTIVATE_ASYNC: Activate firmware asynchronously 2526 * @IONIC_FW_ACTIVATE_STATUS: Firmware activate status 2527 * @IONIC_FW_UPDATE_CLEANUP: Clean up after an interrupted fw update 2528 */ 2529 enum ionic_fw_control_oper { 2530 IONIC_FW_RESET = 0, 2531 IONIC_FW_INSTALL = 1, 2532 IONIC_FW_ACTIVATE = 2, 2533 IONIC_FW_INSTALL_ASYNC = 3, 2534 IONIC_FW_INSTALL_STATUS = 4, 2535 IONIC_FW_ACTIVATE_ASYNC = 5, 2536 IONIC_FW_ACTIVATE_STATUS = 6, 2537 IONIC_FW_UPDATE_CLEANUP = 7, 2538 }; 2539 2540 /** 2541 * struct ionic_fw_control_cmd - Firmware control command 2542 * @opcode: opcode 2543 * @rsvd: reserved byte(s) 2544 * @oper: firmware control operation (enum ionic_fw_control_oper) 2545 * @slot: slot to activate 2546 * @rsvd1: reserved byte(s) 2547 */ 2548 struct ionic_fw_control_cmd { 2549 u8 opcode; 2550 u8 rsvd[3]; 2551 u8 oper; 2552 u8 slot; 2553 u8 rsvd1[58]; 2554 }; 2555 2556 /** 2557 * struct ionic_fw_control_comp - Firmware control copletion 2558 * @status: Status of the command (enum ionic_status_code) 2559 * @rsvd: reserved byte(s) 2560 * @comp_index: Index in the descriptor ring for which this is the completion 2561 * @slot: Slot where the firmware was installed 2562 * @rsvd1: reserved byte(s) 2563 * @color: Color bit 2564 */ 2565 struct ionic_fw_control_comp { 2566 u8 status; 2567 u8 rsvd; 2568 __le16 comp_index; 2569 u8 slot; 2570 u8 rsvd1[10]; 2571 u8 color; 2572 }; 2573 2574 /****************************************************************** 2575 ******************* RDMA Commands ******************************** 2576 ******************************************************************/ 2577 2578 /** 2579 * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd 2580 * @opcode: opcode 2581 * @rsvd: reserved byte(s) 2582 * @lif_index: LIF index 2583 * @rsvd2: reserved byte(s) 2584 * 2585 * There is no RDMA specific dev command completion struct. Completion uses 2586 * the common struct ionic_admin_comp. Only the status is indicated. 2587 * Nonzero status means the LIF does not support RDMA. 2588 **/ 2589 struct ionic_rdma_reset_cmd { 2590 u8 opcode; 2591 u8 rsvd; 2592 __le16 lif_index; 2593 u8 rsvd2[60]; 2594 }; 2595 2596 /** 2597 * struct ionic_rdma_queue_cmd - Create RDMA Queue command 2598 * @opcode: opcode, 52, 53 2599 * @rsvd: reserved byte(s) 2600 * @lif_index: LIF index 2601 * @qid_ver: (qid | (RDMA version << 24)) 2602 * @cid: intr, eq_id, or cq_id 2603 * @dbid: doorbell page id 2604 * @depth_log2: log base two of queue depth 2605 * @stride_log2: log base two of queue stride 2606 * @dma_addr: address of the queue memory 2607 * @rsvd2: reserved byte(s) 2608 * 2609 * The same command struct is used to create an RDMA event queue, completion 2610 * queue, or RDMA admin queue. The cid is an interrupt number for an event 2611 * queue, an event queue id for a completion queue, or a completion queue id 2612 * for an RDMA admin queue. 2613 * 2614 * The queue created via a dev command must be contiguous in dma space. 2615 * 2616 * The dev commands are intended only to be used during driver initialization, 2617 * to create queues supporting the RDMA admin queue. Other queues, and other 2618 * types of RDMA resources like memory regions, will be created and registered 2619 * via the RDMA admin queue, and will support a more complete interface 2620 * providing scatter gather lists for larger, scattered queue buffers and 2621 * memory registration. 2622 * 2623 * There is no RDMA specific dev command completion struct. Completion uses 2624 * the common struct ionic_admin_comp. Only the status is indicated. 2625 **/ 2626 struct ionic_rdma_queue_cmd { 2627 u8 opcode; 2628 u8 rsvd; 2629 __le16 lif_index; 2630 __le32 qid_ver; 2631 __le32 cid; 2632 __le16 dbid; 2633 u8 depth_log2; 2634 u8 stride_log2; 2635 __le64 dma_addr; 2636 u8 rsvd2[40]; 2637 }; 2638 2639 /****************************************************************** 2640 ******************* Notify Events ******************************** 2641 ******************************************************************/ 2642 2643 /** 2644 * struct ionic_notifyq_event - Generic event reporting structure 2645 * @eid: event number 2646 * @ecode: event code 2647 * @data: unspecified data about the event 2648 * 2649 * This is the generic event report struct from which the other 2650 * actual events will be formed. 2651 */ 2652 struct ionic_notifyq_event { 2653 __le64 eid; 2654 __le16 ecode; 2655 u8 data[54]; 2656 }; 2657 2658 /** 2659 * struct ionic_link_change_event - Link change event notification 2660 * @eid: event number 2661 * @ecode: event code = IONIC_EVENT_LINK_CHANGE 2662 * @link_status: link up/down, with error bits (enum ionic_port_status) 2663 * @link_speed: speed of the network link 2664 * @rsvd: reserved byte(s) 2665 * 2666 * Sent when the network link state changes between UP and DOWN 2667 */ 2668 struct ionic_link_change_event { 2669 __le64 eid; 2670 __le16 ecode; 2671 __le16 link_status; 2672 __le32 link_speed; /* units of 1Mbps: e.g. 10000 = 10Gbps */ 2673 u8 rsvd[48]; 2674 }; 2675 2676 /** 2677 * struct ionic_reset_event - Reset event notification 2678 * @eid: event number 2679 * @ecode: event code = IONIC_EVENT_RESET 2680 * @reset_code: reset type 2681 * @state: 0=pending, 1=complete, 2=error 2682 * @rsvd: reserved byte(s) 2683 * 2684 * Sent when the NIC or some subsystem is going to be or 2685 * has been reset. 2686 */ 2687 struct ionic_reset_event { 2688 __le64 eid; 2689 __le16 ecode; 2690 u8 reset_code; 2691 u8 state; 2692 u8 rsvd[52]; 2693 }; 2694 2695 /** 2696 * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health 2697 * @eid: event number 2698 * @ecode: event code = IONIC_EVENT_HEARTBEAT 2699 * @rsvd: reserved byte(s) 2700 */ 2701 struct ionic_heartbeat_event { 2702 __le64 eid; 2703 __le16 ecode; 2704 u8 rsvd[54]; 2705 }; 2706 2707 /** 2708 * struct ionic_log_event - Sent to notify the driver of an internal error 2709 * @eid: event number 2710 * @ecode: event code = IONIC_EVENT_LOG 2711 * @data: log data 2712 */ 2713 struct ionic_log_event { 2714 __le64 eid; 2715 __le16 ecode; 2716 u8 data[54]; 2717 }; 2718 2719 /** 2720 * struct ionic_xcvr_event - Transceiver change event 2721 * @eid: event number 2722 * @ecode: event code = IONIC_EVENT_XCVR 2723 * @rsvd: reserved byte(s) 2724 */ 2725 struct ionic_xcvr_event { 2726 __le64 eid; 2727 __le16 ecode; 2728 u8 rsvd[54]; 2729 }; 2730 2731 /* 2732 * struct ionic_port_stats - Port statistics structure 2733 */ 2734 struct ionic_port_stats { 2735 __le64 frames_rx_ok; 2736 __le64 frames_rx_all; 2737 __le64 frames_rx_bad_fcs; 2738 __le64 frames_rx_bad_all; 2739 __le64 octets_rx_ok; 2740 __le64 octets_rx_all; 2741 __le64 frames_rx_unicast; 2742 __le64 frames_rx_multicast; 2743 __le64 frames_rx_broadcast; 2744 __le64 frames_rx_pause; 2745 __le64 frames_rx_bad_length; 2746 __le64 frames_rx_undersized; 2747 __le64 frames_rx_oversized; 2748 __le64 frames_rx_fragments; 2749 __le64 frames_rx_jabber; 2750 __le64 frames_rx_pripause; 2751 __le64 frames_rx_stomped_crc; 2752 __le64 frames_rx_too_long; 2753 __le64 frames_rx_vlan_good; 2754 __le64 frames_rx_dropped; 2755 __le64 frames_rx_less_than_64b; 2756 __le64 frames_rx_64b; 2757 __le64 frames_rx_65b_127b; 2758 __le64 frames_rx_128b_255b; 2759 __le64 frames_rx_256b_511b; 2760 __le64 frames_rx_512b_1023b; 2761 __le64 frames_rx_1024b_1518b; 2762 __le64 frames_rx_1519b_2047b; 2763 __le64 frames_rx_2048b_4095b; 2764 __le64 frames_rx_4096b_8191b; 2765 __le64 frames_rx_8192b_9215b; 2766 __le64 frames_rx_other; 2767 __le64 frames_tx_ok; 2768 __le64 frames_tx_all; 2769 __le64 frames_tx_bad; 2770 __le64 octets_tx_ok; 2771 __le64 octets_tx_total; 2772 __le64 frames_tx_unicast; 2773 __le64 frames_tx_multicast; 2774 __le64 frames_tx_broadcast; 2775 __le64 frames_tx_pause; 2776 __le64 frames_tx_pripause; 2777 __le64 frames_tx_vlan; 2778 __le64 frames_tx_less_than_64b; 2779 __le64 frames_tx_64b; 2780 __le64 frames_tx_65b_127b; 2781 __le64 frames_tx_128b_255b; 2782 __le64 frames_tx_256b_511b; 2783 __le64 frames_tx_512b_1023b; 2784 __le64 frames_tx_1024b_1518b; 2785 __le64 frames_tx_1519b_2047b; 2786 __le64 frames_tx_2048b_4095b; 2787 __le64 frames_tx_4096b_8191b; 2788 __le64 frames_tx_8192b_9215b; 2789 __le64 frames_tx_other; 2790 __le64 frames_tx_pri_0; 2791 __le64 frames_tx_pri_1; 2792 __le64 frames_tx_pri_2; 2793 __le64 frames_tx_pri_3; 2794 __le64 frames_tx_pri_4; 2795 __le64 frames_tx_pri_5; 2796 __le64 frames_tx_pri_6; 2797 __le64 frames_tx_pri_7; 2798 __le64 frames_rx_pri_0; 2799 __le64 frames_rx_pri_1; 2800 __le64 frames_rx_pri_2; 2801 __le64 frames_rx_pri_3; 2802 __le64 frames_rx_pri_4; 2803 __le64 frames_rx_pri_5; 2804 __le64 frames_rx_pri_6; 2805 __le64 frames_rx_pri_7; 2806 __le64 tx_pripause_0_1us_count; 2807 __le64 tx_pripause_1_1us_count; 2808 __le64 tx_pripause_2_1us_count; 2809 __le64 tx_pripause_3_1us_count; 2810 __le64 tx_pripause_4_1us_count; 2811 __le64 tx_pripause_5_1us_count; 2812 __le64 tx_pripause_6_1us_count; 2813 __le64 tx_pripause_7_1us_count; 2814 __le64 rx_pripause_0_1us_count; 2815 __le64 rx_pripause_1_1us_count; 2816 __le64 rx_pripause_2_1us_count; 2817 __le64 rx_pripause_3_1us_count; 2818 __le64 rx_pripause_4_1us_count; 2819 __le64 rx_pripause_5_1us_count; 2820 __le64 rx_pripause_6_1us_count; 2821 __le64 rx_pripause_7_1us_count; 2822 __le64 rx_pause_1us_count; 2823 __le64 frames_tx_truncated; 2824 }; 2825 2826 struct ionic_mgmt_port_stats { 2827 __le64 frames_rx_ok; 2828 __le64 frames_rx_all; 2829 __le64 frames_rx_bad_fcs; 2830 __le64 frames_rx_bad_all; 2831 __le64 octets_rx_ok; 2832 __le64 octets_rx_all; 2833 __le64 frames_rx_unicast; 2834 __le64 frames_rx_multicast; 2835 __le64 frames_rx_broadcast; 2836 __le64 frames_rx_pause; 2837 __le64 frames_rx_bad_length; 2838 __le64 frames_rx_undersized; 2839 __le64 frames_rx_oversized; 2840 __le64 frames_rx_fragments; 2841 __le64 frames_rx_jabber; 2842 __le64 frames_rx_64b; 2843 __le64 frames_rx_65b_127b; 2844 __le64 frames_rx_128b_255b; 2845 __le64 frames_rx_256b_511b; 2846 __le64 frames_rx_512b_1023b; 2847 __le64 frames_rx_1024b_1518b; 2848 __le64 frames_rx_gt_1518b; 2849 __le64 frames_rx_fifo_full; 2850 __le64 frames_tx_ok; 2851 __le64 frames_tx_all; 2852 __le64 frames_tx_bad; 2853 __le64 octets_tx_ok; 2854 __le64 octets_tx_total; 2855 __le64 frames_tx_unicast; 2856 __le64 frames_tx_multicast; 2857 __le64 frames_tx_broadcast; 2858 __le64 frames_tx_pause; 2859 }; 2860 2861 struct ionic_port_extra_stats { 2862 __le64 rsfec_correctable_blocks; 2863 __le64 rsfec_uncorrectable_blocks; 2864 __le64 fec_corrected_bits_total; 2865 __le64 rx_bits_phy; 2866 __le64 fec_codeword_error_bin[16]; 2867 }; 2868 2869 /** 2870 * struct ionic_port_identity - port identity structure 2871 * @version: identity structure version 2872 * @type: type of port (enum ionic_port_type) 2873 * @num_lanes: number of lanes for the port 2874 * @autoneg: autoneg supported 2875 * @min_frame_size: minimum frame size supported 2876 * @max_frame_size: maximum frame size supported 2877 * @fec_type: supported fec types 2878 * @pause_type: supported pause types 2879 * @loopback_mode: supported loopback mode 2880 * @speeds: supported speeds 2881 * @rsvd2: reserved byte(s) 2882 * @config: current port configuration 2883 * @words: word access to struct contents 2884 */ 2885 union ionic_port_identity { 2886 struct { 2887 u8 version; 2888 u8 type; 2889 u8 num_lanes; 2890 u8 autoneg; 2891 __le32 min_frame_size; 2892 __le32 max_frame_size; 2893 u8 fec_type[4]; 2894 u8 pause_type[2]; 2895 u8 loopback_mode[2]; 2896 __le32 speeds[16]; 2897 u8 rsvd2[44]; 2898 union ionic_port_config config; 2899 }; 2900 __le32 words[478]; 2901 }; 2902 2903 /** 2904 * struct ionic_port_info - port info structure 2905 * @config: Port configuration data 2906 * @status: Port status data 2907 * @stats: Port statistics data 2908 * @mgmt_stats: Port management statistics data 2909 * @sprom_epage: Extended Transceiver sprom 2910 * @sprom_page1: Extended Transceiver sprom, page 1 2911 * @sprom_page2: Extended Transceiver sprom, page 2 2912 * @sprom_page17: Extended Transceiver sprom, page 17 2913 * @rsvd: reserved byte(s) 2914 * @extra_stats: Extra port statistics data 2915 */ 2916 struct ionic_port_info { 2917 union ionic_port_config config; 2918 struct ionic_port_status status; 2919 union { 2920 struct ionic_port_stats stats; 2921 struct ionic_mgmt_port_stats mgmt_stats; 2922 }; 2923 union { 2924 u8 sprom_epage[384]; 2925 struct { 2926 u8 sprom_page1[128]; 2927 u8 sprom_page2[128]; 2928 u8 sprom_page17[128]; 2929 }; 2930 }; 2931 u8 rsvd[376]; 2932 struct ionic_port_extra_stats extra_stats; 2933 }; 2934 2935 /* 2936 * struct ionic_lif_stats - LIF statistics structure 2937 */ 2938 struct ionic_lif_stats { 2939 /* RX */ 2940 __le64 rx_ucast_bytes; 2941 __le64 rx_ucast_packets; 2942 __le64 rx_mcast_bytes; 2943 __le64 rx_mcast_packets; 2944 __le64 rx_bcast_bytes; 2945 __le64 rx_bcast_packets; 2946 __le64 rsvd0; 2947 __le64 rsvd1; 2948 /* RX drops */ 2949 __le64 rx_ucast_drop_bytes; 2950 __le64 rx_ucast_drop_packets; 2951 __le64 rx_mcast_drop_bytes; 2952 __le64 rx_mcast_drop_packets; 2953 __le64 rx_bcast_drop_bytes; 2954 __le64 rx_bcast_drop_packets; 2955 __le64 rx_dma_error; 2956 __le64 rsvd2; 2957 /* TX */ 2958 __le64 tx_ucast_bytes; 2959 __le64 tx_ucast_packets; 2960 __le64 tx_mcast_bytes; 2961 __le64 tx_mcast_packets; 2962 __le64 tx_bcast_bytes; 2963 __le64 tx_bcast_packets; 2964 __le64 rsvd3; 2965 __le64 rsvd4; 2966 /* TX drops */ 2967 __le64 tx_ucast_drop_bytes; 2968 __le64 tx_ucast_drop_packets; 2969 __le64 tx_mcast_drop_bytes; 2970 __le64 tx_mcast_drop_packets; 2971 __le64 tx_bcast_drop_bytes; 2972 __le64 tx_bcast_drop_packets; 2973 __le64 tx_dma_error; 2974 __le64 rsvd5; 2975 /* Rx Queue/Ring drops */ 2976 __le64 rx_queue_disabled; 2977 __le64 rx_queue_empty; 2978 __le64 rx_queue_error; 2979 __le64 rx_desc_fetch_error; 2980 __le64 rx_desc_data_error; 2981 __le64 rsvd6; 2982 __le64 rsvd7; 2983 __le64 rsvd8; 2984 /* Tx Queue/Ring drops */ 2985 __le64 tx_queue_disabled; 2986 __le64 tx_queue_error; 2987 __le64 tx_desc_fetch_error; 2988 __le64 tx_desc_data_error; 2989 __le64 tx_queue_empty; 2990 __le64 rsvd10; 2991 __le64 rsvd11; 2992 __le64 rsvd12; 2993 2994 /* RDMA/ROCE TX */ 2995 __le64 tx_rdma_ucast_bytes; 2996 __le64 tx_rdma_ucast_packets; 2997 __le64 tx_rdma_mcast_bytes; 2998 __le64 tx_rdma_mcast_packets; 2999 __le64 tx_rdma_cnp_packets; 3000 __le64 rsvd13; 3001 __le64 rsvd14; 3002 __le64 rsvd15; 3003 3004 /* RDMA/ROCE RX */ 3005 __le64 rx_rdma_ucast_bytes; 3006 __le64 rx_rdma_ucast_packets; 3007 __le64 rx_rdma_mcast_bytes; 3008 __le64 rx_rdma_mcast_packets; 3009 __le64 rx_rdma_cnp_packets; 3010 __le64 rx_rdma_ecn_packets; 3011 __le64 rsvd16; 3012 __le64 rsvd17; 3013 3014 __le64 rsvd18; 3015 __le64 rsvd19; 3016 __le64 rsvd20; 3017 __le64 rsvd21; 3018 __le64 rsvd22; 3019 __le64 rsvd23; 3020 __le64 rsvd24; 3021 __le64 rsvd25; 3022 3023 __le64 rsvd26; 3024 __le64 rsvd27; 3025 __le64 rsvd28; 3026 __le64 rsvd29; 3027 __le64 rsvd30; 3028 __le64 rsvd31; 3029 __le64 rsvd32; 3030 __le64 rsvd33; 3031 3032 __le64 rsvd34; 3033 __le64 rsvd35; 3034 __le64 rsvd36; 3035 __le64 rsvd37; 3036 __le64 rsvd38; 3037 __le64 rsvd39; 3038 __le64 rsvd40; 3039 __le64 rsvd41; 3040 3041 __le64 rsvd42; 3042 __le64 rsvd43; 3043 __le64 rsvd44; 3044 __le64 rsvd45; 3045 __le64 rsvd46; 3046 __le64 rsvd47; 3047 __le64 rsvd48; 3048 __le64 rsvd49; 3049 3050 /* RDMA/ROCE REQ Error/Debugs (768 - 895) */ 3051 __le64 rdma_req_rx_pkt_seq_err; 3052 __le64 rdma_req_rx_rnr_retry_err; 3053 __le64 rdma_req_rx_remote_access_err; 3054 __le64 rdma_req_rx_remote_inv_req_err; 3055 __le64 rdma_req_rx_remote_oper_err; 3056 __le64 rdma_req_rx_implied_nak_seq_err; 3057 __le64 rdma_req_rx_cqe_err; 3058 __le64 rdma_req_rx_cqe_flush_err; 3059 3060 __le64 rdma_req_rx_dup_responses; 3061 __le64 rdma_req_rx_invalid_packets; 3062 __le64 rdma_req_tx_local_access_err; 3063 __le64 rdma_req_tx_local_oper_err; 3064 __le64 rdma_req_tx_memory_mgmt_err; 3065 __le64 rsvd52; 3066 __le64 rsvd53; 3067 __le64 rsvd54; 3068 3069 /* RDMA/ROCE RESP Error/Debugs (896 - 1023) */ 3070 __le64 rdma_resp_rx_dup_requests; 3071 __le64 rdma_resp_rx_out_of_buffer; 3072 __le64 rdma_resp_rx_out_of_seq_pkts; 3073 __le64 rdma_resp_rx_cqe_err; 3074 __le64 rdma_resp_rx_cqe_flush_err; 3075 __le64 rdma_resp_rx_local_len_err; 3076 __le64 rdma_resp_rx_inv_request_err; 3077 __le64 rdma_resp_rx_local_qp_oper_err; 3078 3079 __le64 rdma_resp_rx_out_of_atomic_resource; 3080 __le64 rdma_resp_tx_pkt_seq_err; 3081 __le64 rdma_resp_tx_remote_inv_req_err; 3082 __le64 rdma_resp_tx_remote_access_err; 3083 __le64 rdma_resp_tx_remote_oper_err; 3084 __le64 rdma_resp_tx_rnr_retry_err; 3085 __le64 rsvd57; 3086 __le64 rsvd58; 3087 }; 3088 3089 /** 3090 * struct ionic_lif_info - LIF info structure 3091 * @config: LIF configuration structure 3092 * @status: LIF status structure 3093 * @stats: LIF statistics structure 3094 */ 3095 struct ionic_lif_info { 3096 union ionic_lif_config config; 3097 struct ionic_lif_status status; 3098 struct ionic_lif_stats stats; 3099 }; 3100 3101 union ionic_dev_cmd { 3102 u32 words[16]; 3103 struct ionic_admin_cmd cmd; 3104 struct ionic_nop_cmd nop; 3105 3106 struct ionic_dev_identify_cmd identify; 3107 struct ionic_dev_init_cmd init; 3108 struct ionic_dev_reset_cmd reset; 3109 struct ionic_dev_getattr_cmd getattr; 3110 struct ionic_dev_setattr_cmd setattr; 3111 3112 struct ionic_port_identify_cmd port_identify; 3113 struct ionic_port_init_cmd port_init; 3114 struct ionic_port_reset_cmd port_reset; 3115 struct ionic_port_getattr_cmd port_getattr; 3116 struct ionic_port_setattr_cmd port_setattr; 3117 3118 struct ionic_vf_setattr_cmd vf_setattr; 3119 struct ionic_vf_getattr_cmd vf_getattr; 3120 struct ionic_vf_ctrl_cmd vf_ctrl; 3121 3122 struct ionic_discover_cmb_cmd discover_cmb; 3123 3124 struct ionic_lif_identify_cmd lif_identify; 3125 struct ionic_lif_init_cmd lif_init; 3126 struct ionic_lif_reset_cmd lif_reset; 3127 3128 struct ionic_qos_identify_cmd qos_identify; 3129 struct ionic_qos_init_cmd qos_init; 3130 struct ionic_qos_reset_cmd qos_reset; 3131 struct ionic_qos_clear_stats_cmd qos_clear_stats; 3132 3133 struct ionic_q_identify_cmd q_identify; 3134 struct ionic_q_init_cmd q_init; 3135 struct ionic_q_control_cmd q_control; 3136 3137 struct ionic_fw_download_cmd fw_download; 3138 struct ionic_fw_control_cmd fw_control; 3139 }; 3140 3141 union ionic_dev_cmd_comp { 3142 u32 words[4]; 3143 u8 status; 3144 struct ionic_admin_comp comp; 3145 struct ionic_nop_comp nop; 3146 3147 struct ionic_dev_identify_comp identify; 3148 struct ionic_dev_init_comp init; 3149 struct ionic_dev_reset_comp reset; 3150 struct ionic_dev_getattr_comp getattr; 3151 struct ionic_dev_setattr_comp setattr; 3152 3153 struct ionic_port_identify_comp port_identify; 3154 struct ionic_port_init_comp port_init; 3155 struct ionic_port_reset_comp port_reset; 3156 struct ionic_port_getattr_comp port_getattr; 3157 struct ionic_port_setattr_comp port_setattr; 3158 3159 struct ionic_vf_setattr_comp vf_setattr; 3160 struct ionic_vf_getattr_comp vf_getattr; 3161 struct ionic_vf_ctrl_comp vf_ctrl; 3162 3163 struct ionic_discover_cmb_comp discover_cmb; 3164 3165 struct ionic_lif_identify_comp lif_identify; 3166 struct ionic_lif_init_comp lif_init; 3167 ionic_lif_reset_comp lif_reset; 3168 3169 struct ionic_qos_identify_comp qos_identify; 3170 ionic_qos_init_comp qos_init; 3171 ionic_qos_reset_comp qos_reset; 3172 3173 struct ionic_q_identify_comp q_identify; 3174 struct ionic_q_init_comp q_init; 3175 3176 ionic_fw_download_comp fw_download; 3177 struct ionic_fw_control_comp fw_control; 3178 }; 3179 3180 /** 3181 * struct ionic_hwstamp_regs - Hardware current timestamp registers 3182 * @tick_low: Low 32 bits of hardware timestamp 3183 * @tick_high: High 32 bits of hardware timestamp 3184 */ 3185 struct ionic_hwstamp_regs { 3186 u32 tick_low; 3187 u32 tick_high; 3188 }; 3189 3190 /** 3191 * union ionic_dev_info_regs - Device info register format (read-only) 3192 * @signature: Signature value of 0x44455649 ('DEVI') 3193 * @version: Current version of info 3194 * @asic_type: Asic type 3195 * @asic_rev: Asic revision 3196 * @fw_status: Firmware status 3197 * bit 0 - 1 = fw running 3198 * bit 4-7 - 4 bit generation number, changes on fw restart 3199 * @fw_heartbeat: Firmware heartbeat counter 3200 * @serial_num: Serial number 3201 * @rsvd_pad1024: reserved byte(s) 3202 * @fw_version: Firmware version 3203 * @hwstamp: Hardware current timestamp registers 3204 * @words: word access to struct contents 3205 */ 3206 union ionic_dev_info_regs { 3207 #define IONIC_DEVINFO_FWVERS_BUFLEN 32 3208 #define IONIC_DEVINFO_SERIAL_BUFLEN 32 3209 struct { 3210 u32 signature; 3211 u8 version; 3212 u8 asic_type; 3213 u8 asic_rev; 3214 #define IONIC_FW_STS_F_RUNNING 0x01 3215 #define IONIC_FW_STS_F_GENERATION 0xF0 3216 u8 fw_status; 3217 u32 fw_heartbeat; 3218 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN]; 3219 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN]; 3220 u8 rsvd_pad1024[948]; 3221 struct ionic_hwstamp_regs hwstamp; 3222 }; 3223 u32 words[512]; 3224 }; 3225 3226 /** 3227 * union ionic_dev_cmd_regs - Device command register format (read-write) 3228 * @doorbell: Device Cmd Doorbell, write-only 3229 * Write a 1 to signal device to process cmd, 3230 * poll done for completion. 3231 * @done: Done indicator, bit 0 == 1 when command is complete 3232 * @cmd: Opcode-specific command bytes 3233 * @comp: Opcode-specific response bytes 3234 * @rsvd: reserved byte(s) 3235 * @data: Opcode-specific side-data 3236 * @words: word access to struct contents 3237 */ 3238 union ionic_dev_cmd_regs { 3239 struct { 3240 u32 doorbell; 3241 u32 done; 3242 union ionic_dev_cmd cmd; 3243 union ionic_dev_cmd_comp comp; 3244 u8 rsvd[48]; 3245 u32 data[478]; 3246 } __packed; 3247 u32 words[512]; 3248 }; 3249 3250 /** 3251 * union ionic_dev_regs - Device register format for bar 0 page 0 3252 * @info: Device info registers 3253 * @devcmd: Device command registers 3254 * @words: word access to struct contents 3255 */ 3256 union ionic_dev_regs { 3257 struct { 3258 union ionic_dev_info_regs info; 3259 union ionic_dev_cmd_regs devcmd; 3260 } __packed; 3261 __le32 words[1024]; 3262 }; 3263 3264 union ionic_adminq_cmd { 3265 struct ionic_admin_cmd cmd; 3266 struct ionic_nop_cmd nop; 3267 struct ionic_q_identify_cmd q_identify; 3268 struct ionic_q_init_cmd q_init; 3269 struct ionic_q_control_cmd q_control; 3270 struct ionic_lif_setattr_cmd lif_setattr; 3271 struct ionic_lif_getattr_cmd lif_getattr; 3272 struct ionic_lif_setphc_cmd lif_setphc; 3273 struct ionic_rx_mode_set_cmd rx_mode_set; 3274 struct ionic_rx_filter_add_cmd rx_filter_add; 3275 struct ionic_rx_filter_del_cmd rx_filter_del; 3276 struct ionic_rdma_reset_cmd rdma_reset; 3277 struct ionic_rdma_queue_cmd rdma_queue; 3278 struct ionic_fw_download_cmd fw_download; 3279 struct ionic_fw_control_cmd fw_control; 3280 }; 3281 3282 union ionic_adminq_comp { 3283 struct ionic_admin_comp comp; 3284 struct ionic_nop_comp nop; 3285 struct ionic_q_identify_comp q_identify; 3286 struct ionic_q_init_comp q_init; 3287 struct ionic_lif_setattr_comp lif_setattr; 3288 struct ionic_lif_getattr_comp lif_getattr; 3289 struct ionic_admin_comp lif_setphc; 3290 struct ionic_rx_filter_add_comp rx_filter_add; 3291 struct ionic_fw_control_comp fw_control; 3292 }; 3293 3294 #define IONIC_BARS_MAX 6 3295 #define IONIC_PCI_BAR_DBELL 1 3296 #define IONIC_PCI_BAR_CMB 2 3297 3298 #define IONIC_BAR0_SIZE 0x8000 3299 #define IONIC_BAR2_SIZE 0x800000 3300 3301 #define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000 3302 #define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800 3303 #define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00 3304 #define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000 3305 #define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000 3306 3307 /* BAR2 */ 3308 #define IONIC_BAR2_CMB_ENTRY_SIZE 0x800000 3309 #define IONIC_DEV_CMD_DONE 0x00000001 3310 3311 #define IONIC_ASIC_TYPE_NONE 0 3312 #define IONIC_ASIC_TYPE_CAPRI 1 3313 #define IONIC_ASIC_TYPE_ELBA 2 3314 #define IONIC_ASIC_TYPE_GIGLIO 3 3315 #define IONIC_ASIC_TYPE_SALINA 4 3316 3317 /** 3318 * struct ionic_doorbell - Doorbell register layout 3319 * @p_index: Producer index 3320 * @ring: Selects the specific ring of the queue to update 3321 * Type-specific meaning: 3322 * ring=0: Default producer/consumer queue 3323 * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs 3324 * send events to EQs when armed. EQs send 3325 * interrupts when armed. 3326 * @qid_lo: Queue destination for the producer index and flags (low bits) 3327 * @qid_hi: Queue destination for the producer index and flags (high bits) 3328 * @rsvd2: reserved byte(s) 3329 */ 3330 struct ionic_doorbell { 3331 __le16 p_index; 3332 u8 ring; 3333 u8 qid_lo; 3334 __le16 qid_hi; 3335 u16 rsvd2; 3336 }; 3337 3338 struct ionic_intr_status { 3339 u32 status[2]; 3340 }; 3341 3342 struct ionic_notifyq_cmd { 3343 __le32 data; /* Not used but needed for qcq structure */ 3344 }; 3345 3346 union ionic_notifyq_comp { 3347 struct ionic_notifyq_event event; 3348 struct ionic_link_change_event link_change; 3349 struct ionic_reset_event reset; 3350 struct ionic_heartbeat_event heartbeat; 3351 struct ionic_log_event log; 3352 }; 3353 3354 /* Deprecate */ 3355 struct ionic_identity { 3356 union ionic_drv_identity drv; 3357 union ionic_dev_identity dev; 3358 union ionic_lif_identity lif; 3359 union ionic_port_identity port; 3360 union ionic_qos_identity qos; 3361 union ionic_q_identity txq; 3362 union ionic_discover_cmb_identity cmb_layout; 3363 }; 3364 3365 #endif /* _IONIC_IF_H_ */ 3366