1 /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */ 2 /* Copyright (c) 2017-2020 Pensando Systems, Inc. All rights reserved. */ 3 4 #ifndef _IONIC_IF_H_ 5 #define _IONIC_IF_H_ 6 7 #define IONIC_DEV_INFO_SIGNATURE 0x44455649 /* 'DEVI' */ 8 #define IONIC_DEV_INFO_VERSION 1 9 #define IONIC_IFNAMSIZ 16 10 #define IONIC_CREATE_CQ_CMD_V2_MAGIC -1 11 12 /* 13 * enum ionic_cmd_opcode - Device commands 14 */ 15 enum ionic_cmd_opcode { 16 IONIC_CMD_NOP = 0, 17 18 /* Device commands */ 19 IONIC_CMD_IDENTIFY = 1, 20 IONIC_CMD_INIT = 2, 21 IONIC_CMD_RESET = 3, 22 IONIC_CMD_GETATTR = 4, 23 IONIC_CMD_SETATTR = 5, 24 25 /* Port commands */ 26 IONIC_CMD_PORT_IDENTIFY = 10, 27 IONIC_CMD_PORT_INIT = 11, 28 IONIC_CMD_PORT_RESET = 12, 29 IONIC_CMD_PORT_GETATTR = 13, 30 IONIC_CMD_PORT_SETATTR = 14, 31 32 /* LIF commands */ 33 IONIC_CMD_LIF_IDENTIFY = 20, 34 IONIC_CMD_LIF_INIT = 21, 35 IONIC_CMD_LIF_RESET = 22, 36 IONIC_CMD_LIF_GETATTR = 23, 37 IONIC_CMD_LIF_SETATTR = 24, 38 IONIC_CMD_LIF_SETPHC = 25, 39 40 IONIC_CMD_RX_MODE_SET = 30, 41 IONIC_CMD_RX_FILTER_ADD = 31, 42 IONIC_CMD_RX_FILTER_DEL = 32, 43 44 /* Queue commands */ 45 IONIC_CMD_Q_IDENTIFY = 39, 46 IONIC_CMD_Q_INIT = 40, 47 IONIC_CMD_Q_CONTROL = 41, 48 49 /* RDMA commands */ 50 IONIC_CMD_RDMA_RESET_LIF = 50, 51 IONIC_CMD_RDMA_CREATE_EQ = 51, 52 IONIC_CMD_RDMA_CREATE_CQ = 52, 53 IONIC_CMD_RDMA_CREATE_ADMINQ = 53, 54 55 /* SR/IOV commands */ 56 IONIC_CMD_VF_GETATTR = 60, 57 IONIC_CMD_VF_SETATTR = 61, 58 IONIC_CMD_VF_CTRL = 62, 59 60 /* CMB command */ 61 IONIC_CMD_DISCOVER_CMB = 80, 62 63 /* QoS commands */ 64 IONIC_CMD_QOS_CLASS_IDENTIFY = 240, 65 IONIC_CMD_QOS_CLASS_INIT = 241, 66 IONIC_CMD_QOS_CLASS_RESET = 242, 67 IONIC_CMD_QOS_CLASS_UPDATE = 243, 68 IONIC_CMD_QOS_CLEAR_STATS = 244, 69 IONIC_CMD_QOS_RESET = 245, 70 71 /* Firmware commands */ 72 IONIC_CMD_FW_DOWNLOAD = 252, 73 IONIC_CMD_FW_CONTROL = 253, 74 IONIC_CMD_FW_DOWNLOAD_V1 = 254, 75 IONIC_CMD_FW_CONTROL_V1 = 255, 76 }; 77 78 /* 79 * enum ionic_status_code - Device command return codes 80 */ 81 enum ionic_status_code { 82 IONIC_RC_SUCCESS = 0, /* Success */ 83 IONIC_RC_EVERSION = 1, /* Incorrect version for request */ 84 IONIC_RC_EOPCODE = 2, /* Invalid cmd opcode */ 85 IONIC_RC_EIO = 3, /* I/O error */ 86 IONIC_RC_EPERM = 4, /* Permission denied */ 87 IONIC_RC_EQID = 5, /* Bad qid */ 88 IONIC_RC_EQTYPE = 6, /* Bad qtype */ 89 IONIC_RC_ENOENT = 7, /* No such element */ 90 IONIC_RC_EINTR = 8, /* operation interrupted */ 91 IONIC_RC_EAGAIN = 9, /* Try again */ 92 IONIC_RC_ENOMEM = 10, /* Out of memory */ 93 IONIC_RC_EFAULT = 11, /* Bad address */ 94 IONIC_RC_EBUSY = 12, /* Device or resource busy */ 95 IONIC_RC_EEXIST = 13, /* object already exists */ 96 IONIC_RC_EINVAL = 14, /* Invalid argument */ 97 IONIC_RC_ENOSPC = 15, /* No space left or alloc failure */ 98 IONIC_RC_ERANGE = 16, /* Parameter out of range */ 99 IONIC_RC_BAD_ADDR = 17, /* Descriptor contains a bad ptr */ 100 IONIC_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */ 101 IONIC_RC_ENOSUPP = 19, /* Operation not supported */ 102 IONIC_RC_ERROR = 29, /* Generic error */ 103 IONIC_RC_ERDMA = 30, /* Generic RDMA error */ 104 IONIC_RC_EVFID = 31, /* VF ID does not exist */ 105 IONIC_RC_EBAD_FW = 32, /* FW file is invalid or corrupted */ 106 }; 107 108 enum ionic_notifyq_opcode { 109 IONIC_EVENT_LINK_CHANGE = 1, 110 IONIC_EVENT_RESET = 2, 111 IONIC_EVENT_HEARTBEAT = 3, 112 IONIC_EVENT_LOG = 4, 113 IONIC_EVENT_XCVR = 5, 114 }; 115 116 /** 117 * struct ionic_admin_cmd - General admin command format 118 * @opcode: Opcode for the command 119 * @rsvd: reserved byte(s) 120 * @lif_index: LIF index 121 * @cmd_data: Opcode-specific command bytes 122 */ 123 struct ionic_admin_cmd { 124 u8 opcode; 125 u8 rsvd; 126 __le16 lif_index; 127 u8 cmd_data[60]; 128 }; 129 130 /** 131 * struct ionic_admin_comp - General admin command completion format 132 * @status: Status of the command (enum ionic_status_code) 133 * @rsvd: reserved byte(s) 134 * @comp_index: Index in the descriptor ring for which this is the completion 135 * @cmd_data: Command-specific bytes 136 * @color: Color bit (Always 0 for commands issued to the 137 * Device Cmd Registers) 138 */ 139 struct ionic_admin_comp { 140 u8 status; 141 u8 rsvd; 142 __le16 comp_index; 143 u8 cmd_data[11]; 144 u8 color; 145 #define IONIC_COMP_COLOR_MASK 0x80 146 }; 147 148 static inline u8 color_match(u8 color, u8 done_color) 149 { 150 return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color; 151 } 152 153 /** 154 * struct ionic_nop_cmd - NOP command 155 * @opcode: opcode 156 * @rsvd: reserved byte(s) 157 */ 158 struct ionic_nop_cmd { 159 u8 opcode; 160 u8 rsvd[63]; 161 }; 162 163 /** 164 * struct ionic_nop_comp - NOP command completion 165 * @status: Status of the command (enum ionic_status_code) 166 * @rsvd: reserved byte(s) 167 */ 168 struct ionic_nop_comp { 169 u8 status; 170 u8 rsvd[15]; 171 }; 172 173 /** 174 * struct ionic_dev_init_cmd - Device init command 175 * @opcode: opcode 176 * @type: Device type 177 * @rsvd: reserved byte(s) 178 */ 179 struct ionic_dev_init_cmd { 180 u8 opcode; 181 u8 type; 182 u8 rsvd[62]; 183 }; 184 185 /** 186 * struct ionic_dev_init_comp - Device init command completion 187 * @status: Status of the command (enum ionic_status_code) 188 * @rsvd: reserved byte(s) 189 */ 190 struct ionic_dev_init_comp { 191 u8 status; 192 u8 rsvd[15]; 193 }; 194 195 /** 196 * struct ionic_dev_reset_cmd - Device reset command 197 * @opcode: opcode 198 * @rsvd: reserved byte(s) 199 */ 200 struct ionic_dev_reset_cmd { 201 u8 opcode; 202 u8 rsvd[63]; 203 }; 204 205 /** 206 * struct ionic_dev_reset_comp - Reset command completion 207 * @status: Status of the command (enum ionic_status_code) 208 * @rsvd: reserved byte(s) 209 */ 210 struct ionic_dev_reset_comp { 211 u8 status; 212 u8 rsvd[15]; 213 }; 214 215 #define IONIC_IDENTITY_VERSION_1 1 216 #define IONIC_DEV_IDENTITY_VERSION_2 2 217 218 /** 219 * struct ionic_dev_identify_cmd - Driver/device identify command 220 * @opcode: opcode 221 * @ver: Highest version of identify supported by driver 222 * @rsvd: reserved byte(s) 223 */ 224 struct ionic_dev_identify_cmd { 225 u8 opcode; 226 u8 ver; 227 u8 rsvd[62]; 228 }; 229 230 /** 231 * struct ionic_dev_identify_comp - Driver/device identify command completion 232 * @status: Status of the command (enum ionic_status_code) 233 * @ver: Version of identify returned by device 234 * @rsvd: reserved byte(s) 235 */ 236 struct ionic_dev_identify_comp { 237 u8 status; 238 u8 ver; 239 u8 rsvd[14]; 240 }; 241 242 enum ionic_os_type { 243 IONIC_OS_TYPE_LINUX = 1, 244 IONIC_OS_TYPE_WIN = 2, 245 IONIC_OS_TYPE_DPDK = 3, 246 IONIC_OS_TYPE_FREEBSD = 4, 247 IONIC_OS_TYPE_IPXE = 5, 248 IONIC_OS_TYPE_ESXI = 6, 249 }; 250 251 /** 252 * union ionic_drv_identity - driver identity information 253 * @os_type: OS type (see enum ionic_os_type) 254 * @os_dist: OS distribution, numeric format 255 * @os_dist_str: OS distribution, string format 256 * @kernel_ver: Kernel version, numeric format 257 * @kernel_ver_str: Kernel version, string format 258 * @driver_ver_str: Driver version, string format 259 * @words: word access to struct contents 260 */ 261 union ionic_drv_identity { 262 struct { 263 __le32 os_type; 264 __le32 os_dist; 265 char os_dist_str[128]; 266 __le32 kernel_ver; 267 char kernel_ver_str[32]; 268 char driver_ver_str[32]; 269 }; 270 __le32 words[478]; 271 }; 272 273 /** 274 * enum ionic_dev_capability - Device capabilities 275 * @IONIC_DEV_CAP_VF_CTRL: Device supports VF ctrl operations 276 * @IONIC_DEV_CAP_DISC_CMB: Device supports CMB discovery operations 277 * @IONIC_DEV_CAP_EXTRA_STATS: Device supports extra stats schema 278 */ 279 enum ionic_dev_capability { 280 IONIC_DEV_CAP_VF_CTRL = BIT(0), 281 IONIC_DEV_CAP_DISC_CMB = BIT(1), 282 IONIC_DEV_CAP_EXTRA_STATS = BIT(4), 283 }; 284 285 /** 286 * union ionic_dev_identity - device identity information 287 * @version: Version of device identify 288 * @type: Identify type (0 for now) 289 * @rsvd: reserved byte(s) 290 * @nports: Number of ports provisioned 291 * @rsvd2: reserved byte(s) 292 * @nlifs: Number of LIFs provisioned 293 * @nintrs: Number of interrupts provisioned 294 * @ndbpgs_per_lif: Number of doorbell pages per LIF 295 * @intr_coal_mult: Interrupt coalescing multiplication factor 296 * Scale user-supplied interrupt coalescing 297 * value in usecs to device units using: 298 * device units = usecs * mult / div 299 * @intr_coal_div: Interrupt coalescing division factor 300 * Scale user-supplied interrupt coalescing 301 * value in usecs to device units using: 302 * device units = usecs * mult / div 303 * @eq_count: Number of shared event queues 304 * @hwstamp_mask: Bitmask for subtraction of hardware tick values. 305 * @hwstamp_mult: Hardware tick to nanosecond multiplier. 306 * @hwstamp_shift: Hardware tick to nanosecond divisor (power of two). 307 * @capabilities: Device capabilities 308 * @words: word access to struct contents 309 */ 310 union ionic_dev_identity { 311 struct { 312 u8 version; 313 u8 type; 314 u8 rsvd[2]; 315 u8 nports; 316 u8 rsvd2[3]; 317 __le32 nlifs; 318 __le32 nintrs; 319 __le32 ndbpgs_per_lif; 320 __le32 intr_coal_mult; 321 __le32 intr_coal_div; 322 __le32 eq_count; 323 __le64 hwstamp_mask; 324 __le32 hwstamp_mult; 325 __le32 hwstamp_shift; 326 __le64 capabilities; 327 }; 328 __le32 words[478]; 329 }; 330 331 enum ionic_lif_type { 332 IONIC_LIF_TYPE_CLASSIC = 0, 333 IONIC_LIF_TYPE_MACVLAN = 1, 334 IONIC_LIF_TYPE_NETQUEUE = 2, 335 }; 336 337 /** 338 * struct ionic_lif_identify_cmd - LIF identify command 339 * @opcode: opcode 340 * @type: LIF type (enum ionic_lif_type) 341 * @ver: Version of identify returned by device 342 * @rsvd: reserved byte(s) 343 */ 344 struct ionic_lif_identify_cmd { 345 u8 opcode; 346 u8 type; 347 u8 ver; 348 u8 rsvd[61]; 349 }; 350 351 /** 352 * struct ionic_lif_identify_comp - LIF identify command completion 353 * @status: Status of the command (enum ionic_status_code) 354 * @ver: Version of identify returned by device 355 * @rsvd2: reserved byte(s) 356 */ 357 struct ionic_lif_identify_comp { 358 u8 status; 359 u8 ver; 360 u8 rsvd2[14]; 361 }; 362 363 /** 364 * enum ionic_lif_capability - LIF capabilities 365 * @IONIC_LIF_CAP_ETH: LIF supports Ethernet 366 * @IONIC_LIF_CAP_RDMA: LIF supports RDMA 367 */ 368 enum ionic_lif_capability { 369 IONIC_LIF_CAP_ETH = BIT(0), 370 IONIC_LIF_CAP_RDMA = BIT(1), 371 }; 372 373 /** 374 * enum ionic_logical_qtype - Logical Queue Types 375 * @IONIC_QTYPE_ADMINQ: Administrative Queue 376 * @IONIC_QTYPE_NOTIFYQ: Notify Queue 377 * @IONIC_QTYPE_RXQ: Receive Queue 378 * @IONIC_QTYPE_TXQ: Transmit Queue 379 * @IONIC_QTYPE_EQ: Event Queue 380 * @IONIC_QTYPE_MAX: Max queue type supported 381 */ 382 enum ionic_logical_qtype { 383 IONIC_QTYPE_ADMINQ = 0, 384 IONIC_QTYPE_NOTIFYQ = 1, 385 IONIC_QTYPE_RXQ = 2, 386 IONIC_QTYPE_TXQ = 3, 387 IONIC_QTYPE_EQ = 4, 388 IONIC_QTYPE_MAX = 16, 389 }; 390 391 /** 392 * enum ionic_q_feature - Common Features for most queue types 393 * 394 * Common features use bits 0-15. Per-queue-type features use higher bits. 395 * 396 * @IONIC_QIDENT_F_CQ: Queue has completion ring 397 * @IONIC_QIDENT_F_SG: Queue has scatter/gather ring 398 * @IONIC_QIDENT_F_EQ: Queue can use event queue 399 * @IONIC_QIDENT_F_CMB: Queue is in cmb bar 400 * @IONIC_Q_F_2X_DESC: Double main descriptor size 401 * @IONIC_Q_F_2X_CQ_DESC: Double cq descriptor size 402 * @IONIC_Q_F_2X_SG_DESC: Double sg descriptor size 403 * @IONIC_Q_F_4X_DESC: Quadruple main descriptor size 404 * @IONIC_Q_F_4X_CQ_DESC: Quadruple cq descriptor size 405 * @IONIC_Q_F_4X_SG_DESC: Quadruple sg descriptor size 406 * @IONIC_QIDENT_F_EXPDB: Queue supports express doorbell 407 */ 408 enum ionic_q_feature { 409 IONIC_QIDENT_F_CQ = BIT_ULL(0), 410 IONIC_QIDENT_F_SG = BIT_ULL(1), 411 IONIC_QIDENT_F_EQ = BIT_ULL(2), 412 IONIC_QIDENT_F_CMB = BIT_ULL(3), 413 IONIC_Q_F_2X_DESC = BIT_ULL(4), 414 IONIC_Q_F_2X_CQ_DESC = BIT_ULL(5), 415 IONIC_Q_F_2X_SG_DESC = BIT_ULL(6), 416 IONIC_Q_F_4X_DESC = BIT_ULL(7), 417 IONIC_Q_F_4X_CQ_DESC = BIT_ULL(8), 418 IONIC_Q_F_4X_SG_DESC = BIT_ULL(9), 419 IONIC_QIDENT_F_EXPDB = BIT_ULL(10), 420 }; 421 422 /** 423 * enum ionic_rxq_feature - RXQ-specific Features 424 * 425 * Per-queue-type features use bits 16 and higher. 426 * 427 * @IONIC_RXQ_F_HWSTAMP: Queue supports Hardware Timestamping 428 */ 429 enum ionic_rxq_feature { 430 IONIC_RXQ_F_HWSTAMP = BIT_ULL(16), 431 }; 432 433 /** 434 * enum ionic_txq_feature - TXQ-specific Features 435 * 436 * Per-queue-type features use bits 16 and higher. 437 * 438 * @IONIC_TXQ_F_HWSTAMP: Queue supports Hardware Timestamping 439 */ 440 enum ionic_txq_feature { 441 IONIC_TXQ_F_HWSTAMP = BIT(16), 442 }; 443 444 /** 445 * enum ionic_hwstamp_bits - Hardware timestamp decoding bits 446 * @IONIC_HWSTAMP_INVALID: Invalid hardware timestamp value 447 * @IONIC_HWSTAMP_CQ_NEGOFFSET: Timestamp field negative offset 448 * from the base cq descriptor. 449 */ 450 enum ionic_hwstamp_bits { 451 IONIC_HWSTAMP_INVALID = ~0ull, 452 IONIC_HWSTAMP_CQ_NEGOFFSET = 8, 453 }; 454 455 /** 456 * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type 457 * @qtype: Hardware Queue Type 458 * @rsvd: reserved byte(s) 459 * @qid_count: Number of Queue IDs of the logical type 460 * @qid_base: Minimum Queue ID of the logical type 461 */ 462 struct ionic_lif_logical_qtype { 463 u8 qtype; 464 u8 rsvd[3]; 465 __le32 qid_count; 466 __le32 qid_base; 467 }; 468 469 /** 470 * enum ionic_lif_state - LIF state 471 * @IONIC_LIF_DISABLE: LIF disabled 472 * @IONIC_LIF_ENABLE: LIF enabled 473 * @IONIC_LIF_QUIESCE: LIF Quiesced 474 */ 475 enum ionic_lif_state { 476 IONIC_LIF_QUIESCE = 0, 477 IONIC_LIF_ENABLE = 1, 478 IONIC_LIF_DISABLE = 2, 479 }; 480 481 /** 482 * union ionic_lif_config - LIF configuration 483 * @state: LIF state (enum ionic_lif_state) 484 * @rsvd: reserved byte(s) 485 * @name: LIF name 486 * @mtu: MTU 487 * @mac: Station MAC address 488 * @vlan: Default Vlan ID 489 * @features: Features (enum ionic_eth_hw_features) 490 * @queue_count: Queue counts per queue-type 491 * @words: word access to struct contents 492 */ 493 union ionic_lif_config { 494 struct { 495 u8 state; 496 u8 rsvd[3]; 497 char name[IONIC_IFNAMSIZ]; 498 __le32 mtu; 499 u8 mac[6]; 500 __le16 vlan; 501 __le64 features; 502 __le32 queue_count[IONIC_QTYPE_MAX]; 503 } __packed; 504 __le32 words[64]; 505 }; 506 507 /** 508 * enum ionic_lif_rdma_cap_stats - LIF stat type 509 * @IONIC_LIF_RDMA_STAT_GLOBAL: Global stats 510 * @IONIC_LIF_RDMA_STAT_QP: Queue pair stats 511 */ 512 enum ionic_lif_rdma_cap_stats { 513 IONIC_LIF_RDMA_STAT_GLOBAL = BIT(0), 514 IONIC_LIF_RDMA_STAT_QP = BIT(1), 515 }; 516 517 /** 518 * enum ionic_lif_rdma_alloc_qid - RDMA QID allocation capability 519 * 520 * Bitmask of RDMA queue types for which firmware can automatically 521 * allocate queue IDs. When a bit is set, the driver can request the 522 * firmware to allocate QIDs for that queue type during creation. 523 * 524 * @IONIC_LIF_RDMA_ALLOC_QID_CQ: Firmware can allocate QIDs for 525 * Completion Queues 526 * @IONIC_LIF_RDMA_ALLOC_QID_SRQ: Firmware can allocate QIDs for 527 * Shared Receive Queues 528 */ 529 enum ionic_lif_rdma_alloc_qid { 530 IONIC_LIF_RDMA_ALLOC_QID_CQ = BIT(0), 531 IONIC_LIF_RDMA_ALLOC_QID_SRQ = BIT(1), 532 }; 533 534 /** 535 * struct ionic_lif_identity - LIF identity information (type-specific) 536 * 537 * @capabilities: LIF capabilities 538 * 539 * @eth: Ethernet identify structure 540 * @eth.version: Ethernet identify structure version 541 * @eth.rsvd: reserved byte(s) 542 * @eth.max_ucast_filters: Number of perfect unicast addresses supported 543 * @eth.max_mcast_filters: Number of perfect multicast addresses supported 544 * @eth.min_frame_size: Minimum size of frames to be sent 545 * @eth.max_frame_size: Maximum size of frames to be sent 546 * @eth.rsvd2: reserved byte(s) 547 * @eth.hwstamp_tx_modes: Bitmask of BIT_ULL(enum ionic_txstamp_mode) 548 * @eth.hwstamp_rx_filters: Bitmask of enum ionic_pkt_class 549 * @eth.rsvd3: reserved byte(s) 550 * @eth.config: LIF config struct with features, mtu, mac, q counts 551 * 552 * @rdma: RDMA identify structure 553 * @rdma.version: RDMA capability version 554 * @rdma.qp_opcodes: Number of RDMA queue pair opcodes supported 555 * @rdma.admin_opcodes: Number of RDMA admin opcodes supported 556 * @rdma.minor_version: RDMA capability minor version 557 * @rdma.npts_per_lif: Page table size per LIF 558 * @rdma.nmrs_per_lif: Number of memory regions per LIF 559 * @rdma.nahs_per_lif: Number of address handles per LIF 560 * @rdma.max_stride: Max work request stride 561 * @rdma.cl_stride: Cache line stride 562 * @rdma.pte_stride: Page table entry stride 563 * @rdma.rrq_stride: Remote RQ work request stride 564 * @rdma.rsq_stride: Remote SQ work request stride 565 * @rdma.dcqcn_profiles: Number of DCQCN profiles 566 * @rdma.udma_shift: Log2 number of queues per queue group 567 * @rdma.rsvd_dimensions: Reserved byte 568 * @rdma.page_size_cap: Supported page sizes 569 * @rdma.aq_qtype: RDMA Admin Qtype 570 * @rdma.sq_qtype: RDMA Send Qtype 571 * @rdma.rq_qtype: RDMA Receive Qtype 572 * @rdma.cq_qtype: RDMA Completion Qtype 573 * @rdma.eq_qtype: RDMA Event Qtype 574 * @rdma.stats_type: Supported statistics type 575 * (enum ionic_lif_rdma_cap_stats) 576 * @rdma.rsvd: Reserved byte 577 * @rdma.rcq_sign_bit: RCQ sign bit 578 * @rdma.srq_qtype: RDMA Shared Receive Qtype 579 * @rdma.rsvd2: Reserved byte(s) 580 * @rdma.alloc_qid_cap: RDMA queue type QID allocation capability 581 * (bitmask of enum ionic_lif_rdma_alloc_qid) 582 * @rdma.rsvd1: Reserved byte(s) 583 * @words: word access to struct contents 584 */ 585 union ionic_lif_identity { 586 struct { 587 __le64 capabilities; 588 589 struct { 590 u8 version; 591 u8 rsvd[3]; 592 __le32 max_ucast_filters; 593 __le32 max_mcast_filters; 594 __le16 rss_ind_tbl_sz; 595 __le32 min_frame_size; 596 __le32 max_frame_size; 597 u8 rsvd2[2]; 598 __le64 hwstamp_tx_modes; 599 __le64 hwstamp_rx_filters; 600 u8 rsvd3[88]; 601 union ionic_lif_config config; 602 } __packed eth; 603 604 struct { 605 u8 version; 606 u8 qp_opcodes; 607 u8 admin_opcodes; 608 u8 minor_version; 609 __le32 npts_per_lif; 610 __le32 nmrs_per_lif; 611 __le32 nahs_per_lif; 612 u8 max_stride; 613 u8 cl_stride; 614 u8 pte_stride; 615 u8 rrq_stride; 616 u8 rsq_stride; 617 u8 dcqcn_profiles; 618 u8 udma_shift; 619 u8 rsvd_dimensions; 620 __le64 page_size_cap; 621 struct ionic_lif_logical_qtype aq_qtype; 622 struct ionic_lif_logical_qtype sq_qtype; 623 struct ionic_lif_logical_qtype rq_qtype; 624 struct ionic_lif_logical_qtype cq_qtype; 625 struct ionic_lif_logical_qtype eq_qtype; 626 __le16 stats_type; 627 u8 rsvd; 628 u8 rcq_sign_bit; 629 struct ionic_lif_logical_qtype srq_qtype; 630 u8 rsvd2[5]; 631 u8 alloc_qid_cap; 632 u8 rsvd1[142]; 633 } __packed rdma; 634 } __packed; 635 __le32 words[478]; 636 }; 637 638 /** 639 * struct ionic_lif_init_cmd - LIF init command 640 * @opcode: Opcode 641 * @type: LIF type (enum ionic_lif_type) 642 * @index: LIF index 643 * @rsvd: reserved byte(s) 644 * @info_pa: Destination address for LIF info (struct ionic_lif_info) 645 * @rsvd2: reserved byte(s) 646 */ 647 struct ionic_lif_init_cmd { 648 u8 opcode; 649 u8 type; 650 __le16 index; 651 __le32 rsvd; 652 __le64 info_pa; 653 u8 rsvd2[48]; 654 }; 655 656 /** 657 * struct ionic_lif_init_comp - LIF init command completion 658 * @status: Status of the command (enum ionic_status_code) 659 * @rsvd: reserved byte(s) 660 * @hw_index: Hardware index of the initialized LIF 661 * @rsvd2: reserved byte(s) 662 */ 663 struct ionic_lif_init_comp { 664 u8 status; 665 u8 rsvd; 666 __le16 hw_index; 667 u8 rsvd2[12]; 668 }; 669 670 /** 671 * struct ionic_q_identify_cmd - queue identify command 672 * @opcode: opcode 673 * @rsvd: reserved byte(s) 674 * @lif_type: LIF type (enum ionic_lif_type) 675 * @type: Logical queue type (enum ionic_logical_qtype) 676 * @ver: Highest queue type version that the driver supports 677 * @rsvd2: reserved byte(s) 678 */ 679 struct ionic_q_identify_cmd { 680 u8 opcode; 681 u8 rsvd; 682 __le16 lif_type; 683 u8 type; 684 u8 ver; 685 u8 rsvd2[58]; 686 }; 687 688 /** 689 * struct ionic_q_identify_comp - queue identify command completion 690 * @status: Status of the command (enum ionic_status_code) 691 * @rsvd: reserved byte(s) 692 * @comp_index: Index in the descriptor ring for which this is the completion 693 * @ver: Queue type version that can be used with FW 694 * @rsvd2: reserved byte(s) 695 */ 696 struct ionic_q_identify_comp { 697 u8 status; 698 u8 rsvd; 699 __le16 comp_index; 700 u8 ver; 701 u8 rsvd2[11]; 702 }; 703 704 /** 705 * union ionic_q_identity - queue identity information 706 * @version: Queue type version that can be used with FW 707 * @supported: Bitfield of queue versions, first bit = ver 0 708 * @rsvd: reserved byte(s) 709 * @features: Queue features (enum ionic_q_feature, etc) 710 * @desc_sz: Descriptor size 711 * @comp_sz: Completion descriptor size 712 * @sg_desc_sz: Scatter/Gather descriptor size 713 * @max_sg_elems: Maximum number of Scatter/Gather elements 714 * @sg_desc_stride: Number of Scatter/Gather elements per descriptor 715 * @words: word access to struct contents 716 */ 717 union ionic_q_identity { 718 struct { 719 u8 version; 720 u8 supported; 721 u8 rsvd[6]; 722 __le64 features; 723 __le16 desc_sz; 724 __le16 comp_sz; 725 __le16 sg_desc_sz; 726 __le16 max_sg_elems; 727 __le16 sg_desc_stride; 728 }; 729 __le32 words[478]; 730 }; 731 732 /** 733 * struct ionic_q_init_cmd - Queue init command 734 * @opcode: opcode 735 * @rsvd: reserved byte(s) 736 * @type: Logical queue type 737 * @ver: Queue type version 738 * @rsvd1: reserved byte(s) 739 * @lif_index: LIF index 740 * @index: (LIF, qtype) relative admin queue index 741 * @intr_index: Interrupt control register index, or Event queue index 742 * @pid: Process ID 743 * @flags: 744 * IRQ: Interrupt requested on completion 745 * ENA: Enable the queue. If ENA=0 the queue is initialized 746 * but remains disabled, to be later enabled with the 747 * Queue Enable command. If ENA=1, then queue is 748 * initialized and then enabled. 749 * SG: Enable Scatter-Gather on the queue. 750 * in number of descs. The actual ring size is 751 * (1 << ring_size). For example, to 752 * select a ring size of 64 descriptors write 753 * ring_size = 6. The minimum ring_size value is 2 754 * for a ring size of 4 descriptors. The maximum 755 * ring_size value is 16 for a ring size of 64k 756 * descriptors. Values of ring_size <2 and >16 are 757 * reserved. 758 * EQ: Enable the Event Queue 759 * @cos: Class of service for this queue 760 * @ring_size: Queue ring size, encoded as a log2(size) 761 * @ring_base: Queue ring base address 762 * @cq_ring_base: Completion queue ring base address 763 * @sg_ring_base: Scatter/Gather ring base address 764 * @rsvd2: reserved byte(s) 765 * @features: Mask of queue features to enable, if not in the flags above. 766 */ 767 struct ionic_q_init_cmd { 768 u8 opcode; 769 u8 rsvd; 770 __le16 lif_index; 771 u8 type; 772 u8 ver; 773 u8 rsvd1[2]; 774 __le32 index; 775 __le16 pid; 776 __le16 intr_index; 777 __le16 flags; 778 #define IONIC_QINIT_F_IRQ 0x01 /* Request interrupt on completion */ 779 #define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */ 780 #define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */ 781 #define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */ 782 #define IONIC_QINIT_F_CMB 0x10 /* Enable cmb-based queue */ 783 #define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */ 784 u8 cos; 785 u8 ring_size; 786 __le64 ring_base; 787 __le64 cq_ring_base; 788 __le64 sg_ring_base; 789 u8 rsvd2[12]; 790 __le64 features; 791 } __packed; 792 793 /** 794 * struct ionic_q_init_comp - Queue init command completion 795 * @status: Status of the command (enum ionic_status_code) 796 * @rsvd: reserved byte(s) 797 * @comp_index: Index in the descriptor ring for which this is the completion 798 * @hw_index: Hardware Queue ID 799 * @hw_type: Hardware Queue type 800 * @rsvd2: reserved byte(s) 801 * @color: Color 802 */ 803 struct ionic_q_init_comp { 804 u8 status; 805 u8 rsvd; 806 __le16 comp_index; 807 __le32 hw_index; 808 u8 hw_type; 809 u8 rsvd2[6]; 810 u8 color; 811 }; 812 813 /* the device's internal addressing uses up to 52 bits */ 814 #define IONIC_ADDR_LEN 52 815 #define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 816 817 enum ionic_txq_desc_opcode { 818 IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0, 819 IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1, 820 IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2, 821 IONIC_TXQ_DESC_OPCODE_TSO = 3, 822 }; 823 824 /** 825 * struct ionic_txq_desc - Ethernet Tx queue descriptor format 826 * @cmd: Tx operation, see IONIC_TXQ_DESC_OPCODE_*: 827 * 828 * IONIC_TXQ_DESC_OPCODE_CSUM_NONE: 829 * Non-offload send. No segmentation, 830 * fragmentation or checksum calc/insertion is 831 * performed by device; packet is prepared 832 * to send by software stack and requires 833 * no further manipulation from device. 834 * 835 * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL: 836 * Offload 16-bit L4 checksum 837 * calculation/insertion. The device will 838 * calculate the L4 checksum value and 839 * insert the result in the packet's L4 840 * header checksum field. The L4 checksum 841 * is calculated starting at @csum_start bytes 842 * into the packet to the end of the packet. 843 * The checksum insertion position is given 844 * in @csum_offset, which is the offset from 845 * @csum_start to the checksum field in the L4 846 * header. This feature is only applicable to 847 * protocols such as TCP, UDP and ICMP where a 848 * standard (i.e. the 'IP-style' checksum) 849 * one's complement 16-bit checksum is used, 850 * using an IP pseudo-header to seed the 851 * calculation. Software will preload the L4 852 * checksum field with the IP pseudo-header 853 * checksum. 854 * 855 * For tunnel encapsulation, @csum_start and 856 * @csum_offset refer to the inner L4 857 * header. Supported tunnels encapsulations 858 * are: IPIP, GRE, and UDP. If the @encap 859 * is clear, no further processing by the 860 * device is required; software will 861 * calculate the outer header checksums. If 862 * the @encap is set, the device will 863 * offload the outer header checksums using 864 * LCO (local checksum offload) (see 865 * Documentation/networking/checksum-offloads.rst 866 * for more info). 867 * 868 * IONIC_TXQ_DESC_OPCODE_CSUM_HW: 869 * Offload 16-bit checksum computation to hardware. 870 * If @csum_l3 is set then the packet's L3 checksum is 871 * updated. Similarly, if @csum_l4 is set the L4 872 * checksum is updated. If @encap is set then encap header 873 * checksums are also updated. 874 * 875 * IONIC_TXQ_DESC_OPCODE_TSO: 876 * Device performs TCP segmentation offload 877 * (TSO). @hdr_len is the number of bytes 878 * to the end of TCP header (the offset to 879 * the TCP payload). @mss is the desired 880 * MSS, the TCP payload length for each 881 * segment. The device will calculate/ 882 * insert IP (IPv4 only) and TCP checksums 883 * for each segment. In the first data 884 * buffer containing the header template, 885 * the driver will set IPv4 checksum to 0 886 * and preload TCP checksum with the IP 887 * pseudo header calculated with IP length = 0. 888 * 889 * Supported tunnel encapsulations are IPIP, 890 * layer-3 GRE, and UDP. @hdr_len includes 891 * both outer and inner headers. The driver 892 * will set IPv4 checksum to zero and 893 * preload TCP checksum with IP pseudo 894 * header on the inner header. 895 * 896 * TCP ECN offload is supported. The device 897 * will set CWR flag in the first segment if 898 * CWR is set in the template header, and 899 * clear CWR in remaining segments. 900 * flags: 901 * vlan: 902 * Insert an L2 VLAN header using @vlan_tci 903 * encap: 904 * Calculate encap header checksum 905 * csum_l3: 906 * Compute L3 header checksum 907 * csum_l4: 908 * Compute L4 header checksum 909 * tso_sot: 910 * TSO start 911 * tso_eot: 912 * TSO end 913 * num_sg_elems: Number of scatter-gather elements in SG 914 * descriptor 915 * addr: First data buffer's DMA address 916 * (Subsequent data buffers are on txq_sg_desc) 917 * @len: First data buffer's length, in bytes 918 * @vlan_tci: VLAN tag to insert in the packet (if requested 919 * by @V-bit). Includes .1p and .1q tags 920 * @hword0: half word padding 921 * @hdr_len: Length of packet headers, including 922 * encapsulating outer header, if applicable 923 * Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and 924 * IONIC_TXQ_DESC_OPCODE_TSO. Should be set to zero for 925 * all other modes. For 926 * IONIC_TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length 927 * of headers up to inner-most L4 header. For 928 * IONIC_TXQ_DESC_OPCODE_TSO, @hdr_len is up to 929 * inner-most L4 payload, so inclusive of 930 * inner-most L4 header. 931 * @hword1: half word padding 932 * @mss: Desired MSS value for TSO; only applicable for 933 * IONIC_TXQ_DESC_OPCODE_TSO 934 * @csum_start: Offset from packet to first byte checked in L4 checksum 935 * @csum_offset: Offset from csum_start to L4 checksum field 936 * @hword2: half word padding 937 */ 938 struct ionic_txq_desc { 939 __le64 cmd; 940 #define IONIC_TXQ_DESC_OPCODE_MASK 0xf 941 #define IONIC_TXQ_DESC_OPCODE_SHIFT 4 942 #define IONIC_TXQ_DESC_FLAGS_MASK 0xf 943 #define IONIC_TXQ_DESC_FLAGS_SHIFT 0 944 #define IONIC_TXQ_DESC_NSGE_MASK 0xf 945 #define IONIC_TXQ_DESC_NSGE_SHIFT 8 946 #define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 947 #define IONIC_TXQ_DESC_ADDR_SHIFT 12 948 949 /* common flags */ 950 #define IONIC_TXQ_DESC_FLAG_VLAN 0x1 951 #define IONIC_TXQ_DESC_FLAG_ENCAP 0x2 952 953 /* flags for csum_hw opcode */ 954 #define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4 955 #define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8 956 957 /* flags for tso opcode */ 958 #define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4 959 #define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8 960 961 __le16 len; 962 union { 963 __le16 vlan_tci; 964 __le16 hword0; 965 }; 966 union { 967 __le16 csum_start; 968 __le16 hdr_len; 969 __le16 hword1; 970 }; 971 union { 972 __le16 csum_offset; 973 __le16 mss; 974 __le16 hword2; 975 }; 976 }; 977 978 static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags, 979 u8 nsge, u64 addr) 980 { 981 u64 cmd; 982 983 cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << IONIC_TXQ_DESC_OPCODE_SHIFT; 984 cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << IONIC_TXQ_DESC_FLAGS_SHIFT; 985 cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT; 986 cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT; 987 988 return cmd; 989 }; 990 991 static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags, 992 u8 *nsge, u64 *addr) 993 { 994 *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & IONIC_TXQ_DESC_OPCODE_MASK; 995 *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & IONIC_TXQ_DESC_FLAGS_MASK; 996 *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK; 997 *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK; 998 }; 999 1000 /** 1001 * struct ionic_txq_sg_elem - Transmit scatter-gather (SG) descriptor element 1002 * @addr: DMA address of SG element data buffer 1003 * @len: Length of SG element data buffer, in bytes 1004 * @rsvd: reserved byte(s) 1005 */ 1006 struct ionic_txq_sg_elem { 1007 __le64 addr; 1008 __le16 len; 1009 __le16 rsvd[3]; 1010 }; 1011 1012 /** 1013 * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list 1014 * @elems: Scatter-gather elements 1015 */ 1016 struct ionic_txq_sg_desc { 1017 #define IONIC_TX_MAX_SG_ELEMS 8 1018 #define IONIC_TX_SG_DESC_STRIDE 8 1019 struct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS]; 1020 }; 1021 1022 struct ionic_txq_sg_desc_v1 { 1023 #define IONIC_TX_MAX_SG_ELEMS_V1 15 1024 #define IONIC_TX_SG_DESC_STRIDE_V1 16 1025 struct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1]; 1026 }; 1027 1028 /** 1029 * struct ionic_txq_comp - Ethernet transmit queue completion descriptor 1030 * @status: Status of the command (enum ionic_status_code) 1031 * @rsvd: reserved byte(s) 1032 * @comp_index: Index in the descriptor ring for which this is the completion 1033 * @rsvd2: reserved byte(s) 1034 * @color: Color bit 1035 */ 1036 struct ionic_txq_comp { 1037 u8 status; 1038 u8 rsvd; 1039 __le16 comp_index; 1040 u8 rsvd2[11]; 1041 u8 color; 1042 }; 1043 1044 enum ionic_rxq_desc_opcode { 1045 IONIC_RXQ_DESC_OPCODE_SIMPLE = 0, 1046 IONIC_RXQ_DESC_OPCODE_SG = 1, 1047 }; 1048 1049 /** 1050 * struct ionic_rxq_desc - Ethernet Rx queue descriptor format 1051 * @opcode: Rx operation, see IONIC_RXQ_DESC_OPCODE_*: 1052 * 1053 * IONIC_RXQ_DESC_OPCODE_SIMPLE: 1054 * Receive full packet into data buffer 1055 * starting at @addr. Results of 1056 * receive, including actual bytes received, 1057 * are recorded in Rx completion descriptor. 1058 * 1059 * @rsvd: reserved byte(s) 1060 * @len: Data buffer's length, in bytes 1061 * @addr: Data buffer's DMA address 1062 */ 1063 struct ionic_rxq_desc { 1064 u8 opcode; 1065 u8 rsvd[5]; 1066 __le16 len; 1067 __le64 addr; 1068 }; 1069 1070 /** 1071 * struct ionic_rxq_sg_elem - Receive scatter-gather (SG) descriptor element 1072 * @addr: DMA address of SG element data buffer 1073 * @len: Length of SG element data buffer, in bytes 1074 * @rsvd: reserved byte(s) 1075 */ 1076 struct ionic_rxq_sg_elem { 1077 __le64 addr; 1078 __le16 len; 1079 __le16 rsvd[3]; 1080 }; 1081 1082 /** 1083 * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list 1084 * @elems: Scatter-gather elements 1085 */ 1086 struct ionic_rxq_sg_desc { 1087 #define IONIC_RX_MAX_SG_ELEMS 8 1088 #define IONIC_RX_SG_DESC_STRIDE 8 1089 struct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE]; 1090 }; 1091 1092 /** 1093 * struct ionic_rxq_comp - Ethernet receive queue completion descriptor 1094 * @status: Status of the command (enum ionic_status_code) 1095 * @num_sg_elems: Number of SG elements used by this descriptor 1096 * @comp_index: Index in the descriptor ring for which this is the completion 1097 * @rss_hash: 32-bit RSS hash 1098 * @csum: 16-bit sum of the packet's L2 payload 1099 * If the packet's L2 payload is odd length, an extra 1100 * zero-value byte is included in the @csum calculation but 1101 * not included in @len. 1102 * @vlan_tci: VLAN tag stripped from the packet. Valid if @VLAN is 1103 * set. Includes .1p and .1q tags. 1104 * @len: Received packet length, in bytes. Excludes FCS. 1105 * @csum_calc L2 payload checksum is computed or not 1106 * @csum_flags: See IONIC_RXQ_COMP_CSUM_F_*: 1107 * 1108 * IONIC_RXQ_COMP_CSUM_F_TCP_OK: 1109 * The TCP checksum calculated by the device 1110 * matched the checksum in the receive packet's 1111 * TCP header. 1112 * 1113 * IONIC_RXQ_COMP_CSUM_F_TCP_BAD: 1114 * The TCP checksum calculated by the device did 1115 * not match the checksum in the receive packet's 1116 * TCP header. 1117 * 1118 * IONIC_RXQ_COMP_CSUM_F_UDP_OK: 1119 * The UDP checksum calculated by the device 1120 * matched the checksum in the receive packet's 1121 * UDP header 1122 * 1123 * IONIC_RXQ_COMP_CSUM_F_UDP_BAD: 1124 * The UDP checksum calculated by the device did 1125 * not match the checksum in the receive packet's 1126 * UDP header. 1127 * 1128 * IONIC_RXQ_COMP_CSUM_F_IP_OK: 1129 * The IPv4 checksum calculated by the device 1130 * matched the checksum in the receive packet's 1131 * first IPv4 header. If the receive packet 1132 * contains both a tunnel IPv4 header and a 1133 * transport IPv4 header, the device validates the 1134 * checksum for both IPv4 headers. 1135 * 1136 * IONIC_RXQ_COMP_CSUM_F_IP_BAD: 1137 * The IPv4 checksum calculated by the device did 1138 * not match the checksum in the receive packet's 1139 * first IPv4 header. If the receive packet 1140 * contains both a tunnel IPv4 header and a 1141 * transport IPv4 header, the device validates the 1142 * checksum for both IP headers. 1143 * 1144 * IONIC_RXQ_COMP_CSUM_F_VLAN: 1145 * The VLAN header was stripped and placed in @vlan_tci. 1146 * 1147 * IONIC_RXQ_COMP_CSUM_F_CALC: 1148 * The checksum was calculated by the device. 1149 * 1150 * @pkt_type_color: Packet type and color bit; see IONIC_RXQ_COMP_PKT_TYPE_MASK 1151 */ 1152 struct ionic_rxq_comp { 1153 u8 status; 1154 u8 num_sg_elems; 1155 __le16 comp_index; 1156 __le32 rss_hash; 1157 __le16 csum; 1158 __le16 vlan_tci; 1159 __le16 len; 1160 u8 csum_flags; 1161 #define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01 1162 #define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02 1163 #define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04 1164 #define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08 1165 #define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10 1166 #define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20 1167 #define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40 1168 #define IONIC_RXQ_COMP_CSUM_F_CALC 0x80 1169 u8 pkt_type_color; 1170 #define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x7f 1171 }; 1172 1173 enum ionic_pkt_type { 1174 IONIC_PKT_TYPE_NON_IP = 0x00, 1175 IONIC_PKT_TYPE_IPV4 = 0x01, 1176 IONIC_PKT_TYPE_IPV4_TCP = 0x03, 1177 IONIC_PKT_TYPE_IPV4_UDP = 0x05, 1178 IONIC_PKT_TYPE_IPV6 = 0x08, 1179 IONIC_PKT_TYPE_IPV6_TCP = 0x18, 1180 IONIC_PKT_TYPE_IPV6_UDP = 0x28, 1181 /* below types are only used if encap offloads are enabled on lif */ 1182 IONIC_PKT_TYPE_ENCAP_NON_IP = 0x40, 1183 IONIC_PKT_TYPE_ENCAP_IPV4 = 0x41, 1184 IONIC_PKT_TYPE_ENCAP_IPV4_TCP = 0x43, 1185 IONIC_PKT_TYPE_ENCAP_IPV4_UDP = 0x45, 1186 IONIC_PKT_TYPE_ENCAP_IPV6 = 0x48, 1187 IONIC_PKT_TYPE_ENCAP_IPV6_TCP = 0x58, 1188 IONIC_PKT_TYPE_ENCAP_IPV6_UDP = 0x68, 1189 }; 1190 1191 enum ionic_eth_hw_features { 1192 IONIC_ETH_HW_VLAN_TX_TAG = BIT(0), 1193 IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1), 1194 IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2), 1195 IONIC_ETH_HW_RX_HASH = BIT(3), 1196 IONIC_ETH_HW_RX_CSUM = BIT(4), 1197 IONIC_ETH_HW_TX_SG = BIT(5), 1198 IONIC_ETH_HW_RX_SG = BIT(6), 1199 IONIC_ETH_HW_TX_CSUM = BIT(7), 1200 IONIC_ETH_HW_TSO = BIT(8), 1201 IONIC_ETH_HW_TSO_IPV6 = BIT(9), 1202 IONIC_ETH_HW_TSO_ECN = BIT(10), 1203 IONIC_ETH_HW_TSO_GRE = BIT(11), 1204 IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12), 1205 IONIC_ETH_HW_TSO_IPXIP4 = BIT(13), 1206 IONIC_ETH_HW_TSO_IPXIP6 = BIT(14), 1207 IONIC_ETH_HW_TSO_UDP = BIT(15), 1208 IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16), 1209 IONIC_ETH_HW_RX_CSUM_GENEVE = BIT(17), 1210 IONIC_ETH_HW_TX_CSUM_GENEVE = BIT(18), 1211 IONIC_ETH_HW_TSO_GENEVE = BIT(19), 1212 IONIC_ETH_HW_TIMESTAMP = BIT(20), 1213 IONIC_ETH_HW_RDMA_TIMESTAMP = BIT(21), 1214 }; 1215 1216 /** 1217 * enum ionic_pkt_class - Packet classification mask. 1218 * 1219 * Used with rx steering filter, packets indicated by the mask can be steered 1220 * toward a specific receive queue. 1221 * 1222 * @IONIC_PKT_CLS_NTP_ALL: All NTP packets. 1223 * @IONIC_PKT_CLS_PTP1_SYNC: PTPv1 sync 1224 * @IONIC_PKT_CLS_PTP1_DREQ: PTPv1 delay-request 1225 * @IONIC_PKT_CLS_PTP1_ALL: PTPv1 all packets 1226 * @IONIC_PKT_CLS_PTP2_L4_SYNC: PTPv2-UDP sync 1227 * @IONIC_PKT_CLS_PTP2_L4_DREQ: PTPv2-UDP delay-request 1228 * @IONIC_PKT_CLS_PTP2_L4_ALL: PTPv2-UDP all packets 1229 * @IONIC_PKT_CLS_PTP2_L2_SYNC: PTPv2-ETH sync 1230 * @IONIC_PKT_CLS_PTP2_L2_DREQ: PTPv2-ETH delay-request 1231 * @IONIC_PKT_CLS_PTP2_L2_ALL: PTPv2-ETH all packets 1232 * @IONIC_PKT_CLS_PTP2_SYNC: PTPv2 sync 1233 * @IONIC_PKT_CLS_PTP2_DREQ: PTPv2 delay-request 1234 * @IONIC_PKT_CLS_PTP2_ALL: PTPv2 all packets 1235 * @IONIC_PKT_CLS_PTP_SYNC: PTP sync 1236 * @IONIC_PKT_CLS_PTP_DREQ: PTP delay-request 1237 * @IONIC_PKT_CLS_PTP_ALL: PTP all packets 1238 */ 1239 enum ionic_pkt_class { 1240 IONIC_PKT_CLS_NTP_ALL = BIT(0), 1241 1242 IONIC_PKT_CLS_PTP1_SYNC = BIT(1), 1243 IONIC_PKT_CLS_PTP1_DREQ = BIT(2), 1244 IONIC_PKT_CLS_PTP1_ALL = BIT(3) | 1245 IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP1_DREQ, 1246 1247 IONIC_PKT_CLS_PTP2_L4_SYNC = BIT(4), 1248 IONIC_PKT_CLS_PTP2_L4_DREQ = BIT(5), 1249 IONIC_PKT_CLS_PTP2_L4_ALL = BIT(6) | 1250 IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L4_DREQ, 1251 1252 IONIC_PKT_CLS_PTP2_L2_SYNC = BIT(7), 1253 IONIC_PKT_CLS_PTP2_L2_DREQ = BIT(8), 1254 IONIC_PKT_CLS_PTP2_L2_ALL = BIT(9) | 1255 IONIC_PKT_CLS_PTP2_L2_SYNC | IONIC_PKT_CLS_PTP2_L2_DREQ, 1256 1257 IONIC_PKT_CLS_PTP2_SYNC = 1258 IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L2_SYNC, 1259 IONIC_PKT_CLS_PTP2_DREQ = 1260 IONIC_PKT_CLS_PTP2_L4_DREQ | IONIC_PKT_CLS_PTP2_L2_DREQ, 1261 IONIC_PKT_CLS_PTP2_ALL = 1262 IONIC_PKT_CLS_PTP2_L4_ALL | IONIC_PKT_CLS_PTP2_L2_ALL, 1263 1264 IONIC_PKT_CLS_PTP_SYNC = 1265 IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP2_SYNC, 1266 IONIC_PKT_CLS_PTP_DREQ = 1267 IONIC_PKT_CLS_PTP1_DREQ | IONIC_PKT_CLS_PTP2_DREQ, 1268 IONIC_PKT_CLS_PTP_ALL = 1269 IONIC_PKT_CLS_PTP1_ALL | IONIC_PKT_CLS_PTP2_ALL, 1270 }; 1271 1272 /** 1273 * struct ionic_q_control_cmd - Queue control command 1274 * @opcode: opcode 1275 * @type: Queue type 1276 * @lif_index: LIF index 1277 * @index: Queue index 1278 * @oper: Operation (enum ionic_q_control_oper) 1279 * @rsvd: reserved byte(s) 1280 */ 1281 struct ionic_q_control_cmd { 1282 u8 opcode; 1283 u8 type; 1284 __le16 lif_index; 1285 __le32 index; 1286 u8 oper; 1287 u8 rsvd[55]; 1288 }; 1289 1290 typedef struct ionic_admin_comp ionic_q_control_comp; 1291 1292 enum ionic_q_control_oper { 1293 IONIC_Q_DISABLE = 0, 1294 IONIC_Q_ENABLE = 1, 1295 IONIC_Q_HANG_RESET = 2, 1296 }; 1297 1298 /** 1299 * enum ionic_phy_type - Physical connection type 1300 * @IONIC_PHY_TYPE_NONE: No PHY installed 1301 * @IONIC_PHY_TYPE_COPPER: Copper PHY 1302 * @IONIC_PHY_TYPE_FIBER: Fiber PHY 1303 */ 1304 enum ionic_phy_type { 1305 IONIC_PHY_TYPE_NONE = 0, 1306 IONIC_PHY_TYPE_COPPER = 1, 1307 IONIC_PHY_TYPE_FIBER = 2, 1308 }; 1309 1310 /** 1311 * enum ionic_xcvr_state - Transceiver status 1312 * @IONIC_XCVR_STATE_REMOVED: Transceiver removed 1313 * @IONIC_XCVR_STATE_INSERTED: Transceiver inserted 1314 * @IONIC_XCVR_STATE_PENDING: Transceiver pending 1315 * @IONIC_XCVR_STATE_SPROM_READ: Transceiver data read 1316 * @IONIC_XCVR_STATE_SPROM_READ_ERR: Transceiver data read error 1317 */ 1318 enum ionic_xcvr_state { 1319 IONIC_XCVR_STATE_REMOVED = 0, 1320 IONIC_XCVR_STATE_INSERTED = 1, 1321 IONIC_XCVR_STATE_PENDING = 2, 1322 IONIC_XCVR_STATE_SPROM_READ = 3, 1323 IONIC_XCVR_STATE_SPROM_READ_ERR = 4, 1324 }; 1325 1326 /* 1327 * enum ionic_xcvr_pid - Supported link modes 1328 */ 1329 enum ionic_xcvr_pid { 1330 IONIC_XCVR_PID_UNKNOWN = 0, 1331 1332 /* CU */ 1333 IONIC_XCVR_PID_QSFP_100G_CR4 = 1, 1334 IONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2, 1335 IONIC_XCVR_PID_SFP_25GBASE_CR_S = 3, 1336 IONIC_XCVR_PID_SFP_25GBASE_CR_L = 4, 1337 IONIC_XCVR_PID_SFP_25GBASE_CR_N = 5, 1338 IONIC_XCVR_PID_QSFP_50G_CR2_FC = 6, 1339 IONIC_XCVR_PID_QSFP_50G_CR2 = 7, 1340 IONIC_XCVR_PID_QSFP_200G_CR4 = 8, 1341 IONIC_XCVR_PID_QSFP_400G_CR4 = 9, 1342 /* Fiber */ 1343 IONIC_XCVR_PID_QSFP_100G_AOC = 50, 1344 IONIC_XCVR_PID_QSFP_100G_ACC = 51, 1345 IONIC_XCVR_PID_QSFP_100G_SR4 = 52, 1346 IONIC_XCVR_PID_QSFP_100G_LR4 = 53, 1347 IONIC_XCVR_PID_QSFP_100G_ER4 = 54, 1348 IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55, 1349 IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56, 1350 IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57, 1351 IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58, 1352 IONIC_XCVR_PID_SFP_25GBASE_SR = 59, 1353 IONIC_XCVR_PID_SFP_25GBASE_LR = 60, 1354 IONIC_XCVR_PID_SFP_25GBASE_ER = 61, 1355 IONIC_XCVR_PID_SFP_25GBASE_AOC = 62, 1356 IONIC_XCVR_PID_SFP_10GBASE_SR = 63, 1357 IONIC_XCVR_PID_SFP_10GBASE_LR = 64, 1358 IONIC_XCVR_PID_SFP_10GBASE_LRM = 65, 1359 IONIC_XCVR_PID_SFP_10GBASE_ER = 66, 1360 IONIC_XCVR_PID_SFP_10GBASE_AOC = 67, 1361 IONIC_XCVR_PID_SFP_10GBASE_CU = 68, 1362 IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69, 1363 IONIC_XCVR_PID_QSFP_100G_PSM4 = 70, 1364 IONIC_XCVR_PID_SFP_25GBASE_ACC = 71, 1365 IONIC_XCVR_PID_SFP_10GBASE_T = 72, 1366 IONIC_XCVR_PID_SFP_1000BASE_T = 73, 1367 IONIC_XCVR_PID_QSFP_200G_AOC = 74, 1368 IONIC_XCVR_PID_QSFP_200G_FR4 = 75, 1369 IONIC_XCVR_PID_QSFP_200G_DR4 = 76, 1370 IONIC_XCVR_PID_QSFP_200G_SR4 = 77, 1371 IONIC_XCVR_PID_QSFP_200G_ACC = 78, 1372 IONIC_XCVR_PID_QSFP_400G_FR4 = 79, 1373 IONIC_XCVR_PID_QSFP_400G_DR4 = 80, 1374 IONIC_XCVR_PID_QSFP_400G_SR4 = 81, 1375 IONIC_XCVR_PID_QSFP_400G_VR4 = 82, 1376 IONIC_XCVR_PID_QSFP_400G_AOC = 83, 1377 IONIC_XCVR_PID_QSFP_400G_AEC = 84, 1378 IONIC_XCVR_PID_QSFP_200G_AEC = 85, 1379 IONIC_XCVR_PID_QSFP_400G_LPO = 86, 1380 IONIC_XCVR_PID_QSFP_100G_FR4 = 87, 1381 IONIC_XCVR_PID_QSFP_100G_DR4 = 88, 1382 }; 1383 1384 /** 1385 * enum ionic_port_type - Port types 1386 * @IONIC_PORT_TYPE_NONE: Port type not configured 1387 * @IONIC_PORT_TYPE_ETH: Port carries ethernet traffic (inband) 1388 * @IONIC_PORT_TYPE_MGMT: Port carries mgmt traffic (out-of-band) 1389 */ 1390 enum ionic_port_type { 1391 IONIC_PORT_TYPE_NONE = 0, 1392 IONIC_PORT_TYPE_ETH = 1, 1393 IONIC_PORT_TYPE_MGMT = 2, 1394 }; 1395 1396 /** 1397 * enum ionic_port_admin_state - Port config state 1398 * @IONIC_PORT_ADMIN_STATE_NONE: Port admin state not configured 1399 * @IONIC_PORT_ADMIN_STATE_DOWN: Port admin disabled 1400 * @IONIC_PORT_ADMIN_STATE_UP: Port admin enabled 1401 */ 1402 enum ionic_port_admin_state { 1403 IONIC_PORT_ADMIN_STATE_NONE = 0, 1404 IONIC_PORT_ADMIN_STATE_DOWN = 1, 1405 IONIC_PORT_ADMIN_STATE_UP = 2, 1406 }; 1407 1408 /** 1409 * enum ionic_port_oper_status - Port operational status 1410 * @IONIC_PORT_OPER_STATUS_NONE: Port disabled 1411 * @IONIC_PORT_OPER_STATUS_UP: Port link status up 1412 * @IONIC_PORT_OPER_STATUS_DOWN: Port link status down 1413 */ 1414 enum ionic_port_oper_status { 1415 IONIC_PORT_OPER_STATUS_NONE = 0, 1416 IONIC_PORT_OPER_STATUS_UP = 1, 1417 IONIC_PORT_OPER_STATUS_DOWN = 2, 1418 }; 1419 1420 /** 1421 * enum ionic_port_fec_type - Ethernet Forward error correction (FEC) modes 1422 * @IONIC_PORT_FEC_TYPE_NONE: FEC Disabled 1423 * @IONIC_PORT_FEC_TYPE_FC: FireCode FEC 1424 * @IONIC_PORT_FEC_TYPE_RS: ReedSolomon FEC 1425 */ 1426 enum ionic_port_fec_type { 1427 IONIC_PORT_FEC_TYPE_NONE = 0, 1428 IONIC_PORT_FEC_TYPE_FC = 1, 1429 IONIC_PORT_FEC_TYPE_RS = 2, 1430 }; 1431 1432 /** 1433 * enum ionic_port_pause_type - Ethernet pause (flow control) modes 1434 * @IONIC_PORT_PAUSE_TYPE_NONE: Disable Pause 1435 * @IONIC_PORT_PAUSE_TYPE_LINK: Link level pause 1436 * @IONIC_PORT_PAUSE_TYPE_PFC: Priority-Flow Control 1437 */ 1438 enum ionic_port_pause_type { 1439 IONIC_PORT_PAUSE_TYPE_NONE = 0, 1440 IONIC_PORT_PAUSE_TYPE_LINK = 1, 1441 IONIC_PORT_PAUSE_TYPE_PFC = 2, 1442 }; 1443 1444 /** 1445 * enum ionic_port_loopback_mode - Loopback modes 1446 * @IONIC_PORT_LOOPBACK_MODE_NONE: Disable loopback 1447 * @IONIC_PORT_LOOPBACK_MODE_MAC: MAC loopback 1448 * @IONIC_PORT_LOOPBACK_MODE_PHY: PHY/SerDes loopback 1449 */ 1450 enum ionic_port_loopback_mode { 1451 IONIC_PORT_LOOPBACK_MODE_NONE = 0, 1452 IONIC_PORT_LOOPBACK_MODE_MAC = 1, 1453 IONIC_PORT_LOOPBACK_MODE_PHY = 2, 1454 }; 1455 1456 /** 1457 * struct ionic_xcvr_status - Transceiver Status information 1458 * @state: Transceiver status (enum ionic_xcvr_state) 1459 * @phy: Physical connection type (enum ionic_phy_type) 1460 * @pid: Transceiver link mode (enum ionic_xcvr_pid) 1461 * @sprom: Transceiver sprom contents 1462 */ 1463 struct ionic_xcvr_status { 1464 u8 state; 1465 u8 phy; 1466 __le16 pid; 1467 u8 sprom[256]; 1468 }; 1469 1470 /** 1471 * union ionic_port_config - Port configuration 1472 * @speed: port speed (in Mbps) 1473 * @mtu: mtu 1474 * @state: port admin state (enum ionic_port_admin_state) 1475 * @an_enable: autoneg enable 1476 * @fec_type: fec type (enum ionic_port_fec_type) 1477 * @pause_type: pause type (enum ionic_port_pause_type) 1478 * @loopback_mode: loopback mode (enum ionic_port_loopback_mode) 1479 * @words: word access to struct contents 1480 */ 1481 union ionic_port_config { 1482 struct { 1483 #define IONIC_SPEED_400G 400000 /* 400G in Mbps */ 1484 #define IONIC_SPEED_200G 200000 /* 200G in Mbps */ 1485 #define IONIC_SPEED_100G 100000 /* 100G in Mbps */ 1486 #define IONIC_SPEED_50G 50000 /* 50G in Mbps */ 1487 #define IONIC_SPEED_40G 40000 /* 40G in Mbps */ 1488 #define IONIC_SPEED_25G 25000 /* 25G in Mbps */ 1489 #define IONIC_SPEED_10G 10000 /* 10G in Mbps */ 1490 #define IONIC_SPEED_1G 1000 /* 1G in Mbps */ 1491 __le32 speed; 1492 __le32 mtu; 1493 u8 state; 1494 u8 an_enable; 1495 u8 fec_type; 1496 #define IONIC_PAUSE_TYPE_MASK 0x0f 1497 #define IONIC_PAUSE_FLAGS_MASK 0xf0 1498 #define IONIC_PAUSE_F_TX 0x10 1499 #define IONIC_PAUSE_F_RX 0x20 1500 u8 pause_type; 1501 u8 loopback_mode; 1502 }; 1503 __le32 words[64]; 1504 }; 1505 1506 /** 1507 * struct ionic_port_status - Port Status information 1508 * @status: link status (enum ionic_port_oper_status) 1509 * @id: port id 1510 * @speed: link speed (in Mbps) 1511 * @link_down_count: number of times link went from up to down 1512 * @fec_type: fec type (enum ionic_port_fec_type) 1513 * @rsvd: reserved byte(s) 1514 * @xcvr: transceiver status 1515 */ 1516 struct ionic_port_status { 1517 __le32 id; 1518 __le32 speed; 1519 u8 status; 1520 __le16 link_down_count; 1521 u8 fec_type; 1522 u8 rsvd[48]; 1523 struct ionic_xcvr_status xcvr; 1524 } __packed; 1525 1526 /** 1527 * struct ionic_port_identify_cmd - Port identify command 1528 * @opcode: opcode 1529 * @index: port index 1530 * @ver: Highest version of identify supported by driver 1531 * @rsvd: reserved byte(s) 1532 */ 1533 struct ionic_port_identify_cmd { 1534 u8 opcode; 1535 u8 index; 1536 u8 ver; 1537 u8 rsvd[61]; 1538 }; 1539 1540 /** 1541 * struct ionic_port_identify_comp - Port identify command completion 1542 * @status: Status of the command (enum ionic_status_code) 1543 * @ver: Version of identify returned by device 1544 * @rsvd: reserved byte(s) 1545 */ 1546 struct ionic_port_identify_comp { 1547 u8 status; 1548 u8 ver; 1549 u8 rsvd[14]; 1550 }; 1551 1552 /** 1553 * struct ionic_port_init_cmd - Port initialization command 1554 * @opcode: opcode 1555 * @index: port index 1556 * @rsvd: reserved byte(s) 1557 * @info_pa: destination address for port info (struct ionic_port_info) 1558 * @rsvd2: reserved byte(s) 1559 */ 1560 struct ionic_port_init_cmd { 1561 u8 opcode; 1562 u8 index; 1563 u8 rsvd[6]; 1564 __le64 info_pa; 1565 u8 rsvd2[48]; 1566 }; 1567 1568 /** 1569 * struct ionic_port_init_comp - Port initialization command completion 1570 * @status: Status of the command (enum ionic_status_code) 1571 * @rsvd: reserved byte(s) 1572 */ 1573 struct ionic_port_init_comp { 1574 u8 status; 1575 u8 rsvd[15]; 1576 }; 1577 1578 /** 1579 * struct ionic_port_reset_cmd - Port reset command 1580 * @opcode: opcode 1581 * @index: port index 1582 * @rsvd: reserved byte(s) 1583 */ 1584 struct ionic_port_reset_cmd { 1585 u8 opcode; 1586 u8 index; 1587 u8 rsvd[62]; 1588 }; 1589 1590 /** 1591 * struct ionic_port_reset_comp - Port reset command completion 1592 * @status: Status of the command (enum ionic_status_code) 1593 * @rsvd: reserved byte(s) 1594 */ 1595 struct ionic_port_reset_comp { 1596 u8 status; 1597 u8 rsvd[15]; 1598 }; 1599 1600 /** 1601 * enum ionic_stats_ctl_cmd - List of commands for stats control 1602 * @IONIC_STATS_CTL_RESET: Reset statistics 1603 */ 1604 enum ionic_stats_ctl_cmd { 1605 IONIC_STATS_CTL_RESET = 0, 1606 }; 1607 1608 /** 1609 * enum ionic_txstamp_mode - List of TX Timestamping Modes 1610 * @IONIC_TXSTAMP_OFF: Disable TX hardware timetamping. 1611 * @IONIC_TXSTAMP_ON: Enable local TX hardware timetamping. 1612 * @IONIC_TXSTAMP_ONESTEP_SYNC: Modify TX PTP Sync packets. 1613 * @IONIC_TXSTAMP_ONESTEP_P2P: Modify TX PTP Sync and PDelayResp. 1614 */ 1615 enum ionic_txstamp_mode { 1616 IONIC_TXSTAMP_OFF = 0, 1617 IONIC_TXSTAMP_ON = 1, 1618 IONIC_TXSTAMP_ONESTEP_SYNC = 2, 1619 IONIC_TXSTAMP_ONESTEP_P2P = 3, 1620 }; 1621 1622 /** 1623 * enum ionic_port_attr - List of device attributes 1624 * @IONIC_PORT_ATTR_STATE: Port state attribute 1625 * @IONIC_PORT_ATTR_SPEED: Port speed attribute 1626 * @IONIC_PORT_ATTR_MTU: Port MTU attribute 1627 * @IONIC_PORT_ATTR_AUTONEG: Port autonegotiation attribute 1628 * @IONIC_PORT_ATTR_FEC: Port FEC attribute 1629 * @IONIC_PORT_ATTR_PAUSE: Port pause attribute 1630 * @IONIC_PORT_ATTR_LOOPBACK: Port loopback attribute 1631 * @IONIC_PORT_ATTR_STATS_CTRL: Port statistics control attribute 1632 */ 1633 enum ionic_port_attr { 1634 IONIC_PORT_ATTR_STATE = 0, 1635 IONIC_PORT_ATTR_SPEED = 1, 1636 IONIC_PORT_ATTR_MTU = 2, 1637 IONIC_PORT_ATTR_AUTONEG = 3, 1638 IONIC_PORT_ATTR_FEC = 4, 1639 IONIC_PORT_ATTR_PAUSE = 5, 1640 IONIC_PORT_ATTR_LOOPBACK = 6, 1641 IONIC_PORT_ATTR_STATS_CTRL = 7, 1642 }; 1643 1644 /** 1645 * struct ionic_port_setattr_cmd - Set port attributes on the NIC 1646 * @opcode: Opcode 1647 * @index: Port index 1648 * @attr: Attribute type (enum ionic_port_attr) 1649 * @rsvd: reserved byte(s) 1650 * @state: Port state 1651 * @speed: Port speed 1652 * @mtu: Port MTU 1653 * @an_enable: Port autonegotiation setting 1654 * @fec_type: Port FEC type setting 1655 * @pause_type: Port pause type setting 1656 * @loopback_mode: Port loopback mode 1657 * @stats_ctl: Port stats setting 1658 * @rsvd2: reserved byte(s) 1659 */ 1660 struct ionic_port_setattr_cmd { 1661 u8 opcode; 1662 u8 index; 1663 u8 attr; 1664 u8 rsvd; 1665 union { 1666 u8 state; 1667 __le32 speed; 1668 __le32 mtu; 1669 u8 an_enable; 1670 u8 fec_type; 1671 u8 pause_type; 1672 u8 loopback_mode; 1673 u8 stats_ctl; 1674 u8 rsvd2[60]; 1675 }; 1676 }; 1677 1678 /** 1679 * struct ionic_port_setattr_comp - Port set attr command completion 1680 * @status: Status of the command (enum ionic_status_code) 1681 * @rsvd: reserved byte(s) 1682 * @color: Color bit 1683 */ 1684 struct ionic_port_setattr_comp { 1685 u8 status; 1686 u8 rsvd[14]; 1687 u8 color; 1688 }; 1689 1690 /** 1691 * struct ionic_port_getattr_cmd - Get port attributes from the NIC 1692 * @opcode: Opcode 1693 * @index: port index 1694 * @attr: Attribute type (enum ionic_port_attr) 1695 * @rsvd: reserved byte(s) 1696 */ 1697 struct ionic_port_getattr_cmd { 1698 u8 opcode; 1699 u8 index; 1700 u8 attr; 1701 u8 rsvd[61]; 1702 }; 1703 1704 /** 1705 * struct ionic_port_getattr_comp - Port get attr command completion 1706 * @status: Status of the command (enum ionic_status_code) 1707 * @rsvd: reserved byte(s) 1708 * @state: Port state 1709 * @speed: Port speed 1710 * @mtu: Port MTU 1711 * @an_enable: Port autonegotiation setting 1712 * @fec_type: Port FEC type setting 1713 * @pause_type: Port pause type setting 1714 * @loopback_mode: Port loopback mode 1715 * @rsvd2: reserved byte(s) 1716 * @color: Color bit 1717 */ 1718 struct ionic_port_getattr_comp { 1719 u8 status; 1720 u8 rsvd[3]; 1721 union { 1722 u8 state; 1723 __le32 speed; 1724 __le32 mtu; 1725 u8 an_enable; 1726 u8 fec_type; 1727 u8 pause_type; 1728 u8 loopback_mode; 1729 u8 rsvd2[11]; 1730 } __packed; 1731 u8 color; 1732 }; 1733 1734 /** 1735 * struct ionic_lif_status - LIF status register 1736 * @eid: most recent NotifyQ event id 1737 * @port_num: port the LIF is connected to 1738 * @rsvd: reserved byte(s) 1739 * @link_status: port status (enum ionic_port_oper_status) 1740 * @link_speed: speed of link in Mbps 1741 * @link_down_count: number of times link went from up to down 1742 * @rsvd2: reserved byte(s) 1743 */ 1744 struct ionic_lif_status { 1745 __le64 eid; 1746 u8 port_num; 1747 u8 rsvd; 1748 __le16 link_status; 1749 __le32 link_speed; /* units of 1Mbps: eg 10000 = 10Gbps */ 1750 __le16 link_down_count; 1751 u8 rsvd2[46]; 1752 }; 1753 1754 /** 1755 * struct ionic_lif_reset_cmd - LIF reset command 1756 * @opcode: opcode 1757 * @rsvd: reserved byte(s) 1758 * @index: LIF index 1759 * @rsvd2: reserved byte(s) 1760 */ 1761 struct ionic_lif_reset_cmd { 1762 u8 opcode; 1763 u8 rsvd; 1764 __le16 index; 1765 __le32 rsvd2[15]; 1766 }; 1767 1768 typedef struct ionic_admin_comp ionic_lif_reset_comp; 1769 1770 enum ionic_dev_state { 1771 IONIC_DEV_DISABLE = 0, 1772 IONIC_DEV_ENABLE = 1, 1773 IONIC_DEV_HANG_RESET = 2, 1774 }; 1775 1776 /** 1777 * enum ionic_dev_attr - List of device attributes 1778 * @IONIC_DEV_ATTR_STATE: Device state attribute 1779 * @IONIC_DEV_ATTR_NAME: Device name attribute 1780 * @IONIC_DEV_ATTR_FEATURES: Device feature attributes 1781 */ 1782 enum ionic_dev_attr { 1783 IONIC_DEV_ATTR_STATE = 0, 1784 IONIC_DEV_ATTR_NAME = 1, 1785 IONIC_DEV_ATTR_FEATURES = 2, 1786 }; 1787 1788 /** 1789 * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC 1790 * @opcode: Opcode 1791 * @attr: Attribute type (enum ionic_dev_attr) 1792 * @rsvd: reserved byte(s) 1793 * @state: Device state (enum ionic_dev_state) 1794 * @name: The bus info, e.g. PCI slot-device-function, 0 terminated 1795 * @features: Device features 1796 * @rsvd2: reserved byte(s) 1797 */ 1798 struct ionic_dev_setattr_cmd { 1799 u8 opcode; 1800 u8 attr; 1801 __le16 rsvd; 1802 union { 1803 u8 state; 1804 char name[IONIC_IFNAMSIZ]; 1805 __le64 features; 1806 u8 rsvd2[60]; 1807 } __packed; 1808 }; 1809 1810 /** 1811 * struct ionic_dev_setattr_comp - Device set attr command completion 1812 * @status: Status of the command (enum ionic_status_code) 1813 * @rsvd: reserved byte(s) 1814 * @features: Device features 1815 * @rsvd2: reserved byte(s) 1816 * @color: Color bit 1817 */ 1818 struct ionic_dev_setattr_comp { 1819 u8 status; 1820 u8 rsvd[3]; 1821 union { 1822 __le64 features; 1823 u8 rsvd2[11]; 1824 } __packed; 1825 u8 color; 1826 }; 1827 1828 /** 1829 * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC 1830 * @opcode: opcode 1831 * @attr: Attribute type (enum ionic_dev_attr) 1832 * @rsvd: reserved byte(s) 1833 */ 1834 struct ionic_dev_getattr_cmd { 1835 u8 opcode; 1836 u8 attr; 1837 u8 rsvd[62]; 1838 }; 1839 1840 /** 1841 * struct ionic_dev_getattr_comp - Device set attr command completion 1842 * @status: Status of the command (enum ionic_status_code) 1843 * @rsvd: reserved byte(s) 1844 * @features: Device features 1845 * @rsvd2: reserved byte(s) 1846 * @color: Color bit 1847 */ 1848 struct ionic_dev_getattr_comp { 1849 u8 status; 1850 u8 rsvd[3]; 1851 union { 1852 __le64 features; 1853 u8 rsvd2[11]; 1854 } __packed; 1855 u8 color; 1856 }; 1857 1858 /* 1859 * RSS parameters 1860 */ 1861 #define IONIC_RSS_HASH_KEY_SIZE 40 1862 1863 enum ionic_rss_hash_types { 1864 IONIC_RSS_TYPE_IPV4 = BIT(0), 1865 IONIC_RSS_TYPE_IPV4_TCP = BIT(1), 1866 IONIC_RSS_TYPE_IPV4_UDP = BIT(2), 1867 IONIC_RSS_TYPE_IPV6 = BIT(3), 1868 IONIC_RSS_TYPE_IPV6_TCP = BIT(4), 1869 IONIC_RSS_TYPE_IPV6_UDP = BIT(5), 1870 }; 1871 1872 /** 1873 * enum ionic_lif_attr - List of LIF attributes 1874 * @IONIC_LIF_ATTR_STATE: LIF state attribute 1875 * @IONIC_LIF_ATTR_NAME: LIF name attribute 1876 * @IONIC_LIF_ATTR_MTU: LIF MTU attribute 1877 * @IONIC_LIF_ATTR_MAC: LIF MAC attribute 1878 * @IONIC_LIF_ATTR_FEATURES: LIF features attribute 1879 * @IONIC_LIF_ATTR_RSS: LIF RSS attribute 1880 * @IONIC_LIF_ATTR_STATS_CTRL: LIF statistics control attribute 1881 * @IONIC_LIF_ATTR_TXSTAMP: LIF TX timestamping mode 1882 * @IONIC_LIF_ATTR_MAX: maximum attribute value 1883 */ 1884 enum ionic_lif_attr { 1885 IONIC_LIF_ATTR_STATE = 0, 1886 IONIC_LIF_ATTR_NAME = 1, 1887 IONIC_LIF_ATTR_MTU = 2, 1888 IONIC_LIF_ATTR_MAC = 3, 1889 IONIC_LIF_ATTR_FEATURES = 4, 1890 IONIC_LIF_ATTR_RSS = 5, 1891 IONIC_LIF_ATTR_STATS_CTRL = 6, 1892 IONIC_LIF_ATTR_TXSTAMP = 7, 1893 IONIC_LIF_ATTR_MAX = 255, 1894 }; 1895 1896 /** 1897 * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC 1898 * @opcode: Opcode 1899 * @attr: Attribute type (enum ionic_lif_attr) 1900 * @index: LIF index 1901 * @state: LIF state (enum ionic_lif_state) 1902 * @name: The netdev name string, 0 terminated 1903 * @mtu: Mtu 1904 * @mac: Station mac 1905 * @features: Features (enum ionic_eth_hw_features) 1906 * @rss: RSS properties 1907 * @rss.types: The hash types to enable (see rss_hash_types) 1908 * @rss.key: The hash secret key 1909 * @rss.rsvd: reserved byte(s) 1910 * @rss.addr: Address for the indirection table shared memory 1911 * @stats_ctl: stats control commands (enum ionic_stats_ctl_cmd) 1912 * @txstamp_mode: TX Timestamping Mode (enum ionic_txstamp_mode) 1913 * @rsvd: reserved byte(s) 1914 */ 1915 struct ionic_lif_setattr_cmd { 1916 u8 opcode; 1917 u8 attr; 1918 __le16 index; 1919 union { 1920 u8 state; 1921 char name[IONIC_IFNAMSIZ]; 1922 __le32 mtu; 1923 u8 mac[6]; 1924 __le64 features; 1925 struct { 1926 __le16 types; 1927 u8 key[IONIC_RSS_HASH_KEY_SIZE]; 1928 u8 rsvd[6]; 1929 __le64 addr; 1930 } rss; 1931 u8 stats_ctl; 1932 __le16 txstamp_mode; 1933 u8 rsvd[60]; 1934 } __packed; 1935 }; 1936 1937 /** 1938 * struct ionic_lif_setattr_comp - LIF set attr command completion 1939 * @status: Status of the command (enum ionic_status_code) 1940 * @rsvd: reserved byte(s) 1941 * @comp_index: Index in the descriptor ring for which this is the completion 1942 * @features: features (enum ionic_eth_hw_features) 1943 * @rsvd2: reserved byte(s) 1944 * @color: Color bit 1945 */ 1946 struct ionic_lif_setattr_comp { 1947 u8 status; 1948 u8 rsvd; 1949 __le16 comp_index; 1950 union { 1951 __le64 features; 1952 u8 rsvd2[11]; 1953 } __packed; 1954 u8 color; 1955 }; 1956 1957 /** 1958 * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC 1959 * @opcode: Opcode 1960 * @attr: Attribute type (enum ionic_lif_attr) 1961 * @index: LIF index 1962 * @rsvd: reserved byte(s) 1963 */ 1964 struct ionic_lif_getattr_cmd { 1965 u8 opcode; 1966 u8 attr; 1967 __le16 index; 1968 u8 rsvd[60]; 1969 }; 1970 1971 /** 1972 * struct ionic_lif_getattr_comp - LIF get attr command completion 1973 * @status: Status of the command (enum ionic_status_code) 1974 * @rsvd: reserved byte(s) 1975 * @comp_index: Index in the descriptor ring for which this is the completion 1976 * @state: LIF state (enum ionic_lif_state) 1977 * @mtu: Mtu 1978 * @mac: Station mac 1979 * @features: Features (enum ionic_eth_hw_features) 1980 * @txstamp_mode: TX Timestamping Mode (enum ionic_txstamp_mode) 1981 * @rsvd2: reserved byte(s) 1982 * @color: Color bit 1983 */ 1984 struct ionic_lif_getattr_comp { 1985 u8 status; 1986 u8 rsvd; 1987 __le16 comp_index; 1988 union { 1989 u8 state; 1990 __le32 mtu; 1991 u8 mac[6]; 1992 __le64 features; 1993 __le16 txstamp_mode; 1994 u8 rsvd2[11]; 1995 } __packed; 1996 u8 color; 1997 }; 1998 1999 /** 2000 * struct ionic_lif_setphc_cmd - Set LIF PTP Hardware Clock 2001 * @opcode: Opcode 2002 * @rsvd1: reserved byte(s) 2003 * @lif_index: LIF index 2004 * @rsvd2: reserved byte(s) 2005 * @tick: Hardware stamp tick of an instant in time. 2006 * @nsec: Nanosecond stamp of the same instant. 2007 * @frac: Fractional nanoseconds at the same instant. 2008 * @mult: Cycle to nanosecond multiplier. 2009 * @shift: Cycle to nanosecond divisor (power of two). 2010 * @rsvd3: reserved byte(s) 2011 */ 2012 struct ionic_lif_setphc_cmd { 2013 u8 opcode; 2014 u8 rsvd1; 2015 __le16 lif_index; 2016 u8 rsvd2[4]; 2017 __le64 tick; 2018 __le64 nsec; 2019 __le64 frac; 2020 __le32 mult; 2021 __le32 shift; 2022 u8 rsvd3[24]; 2023 }; 2024 2025 enum ionic_rx_mode { 2026 IONIC_RX_MODE_F_UNICAST = BIT(0), 2027 IONIC_RX_MODE_F_MULTICAST = BIT(1), 2028 IONIC_RX_MODE_F_BROADCAST = BIT(2), 2029 IONIC_RX_MODE_F_PROMISC = BIT(3), 2030 IONIC_RX_MODE_F_ALLMULTI = BIT(4), 2031 IONIC_RX_MODE_F_RDMA_SNIFFER = BIT(5), 2032 }; 2033 2034 /** 2035 * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command 2036 * @opcode: opcode 2037 * @rsvd: reserved byte(s) 2038 * @lif_index: LIF index 2039 * @rx_mode: Rx mode flags: 2040 * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets 2041 * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets 2042 * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets 2043 * IONIC_RX_MODE_F_PROMISC: Accept any packets 2044 * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets 2045 * IONIC_RX_MODE_F_RDMA_SNIFFER: Sniff RDMA packets 2046 * @rsvd2: reserved byte(s) 2047 */ 2048 struct ionic_rx_mode_set_cmd { 2049 u8 opcode; 2050 u8 rsvd; 2051 __le16 lif_index; 2052 __le16 rx_mode; 2053 __le16 rsvd2[29]; 2054 }; 2055 2056 typedef struct ionic_admin_comp ionic_rx_mode_set_comp; 2057 2058 enum ionic_rx_filter_match_type { 2059 IONIC_RX_FILTER_MATCH_VLAN = 0x0, 2060 IONIC_RX_FILTER_MATCH_MAC = 0x1, 2061 IONIC_RX_FILTER_MATCH_MAC_VLAN = 0x2, 2062 IONIC_RX_FILTER_STEER_PKTCLASS = 0x10, 2063 }; 2064 2065 /** 2066 * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command 2067 * @opcode: opcode 2068 * @qtype: Queue type 2069 * @lif_index: LIF index 2070 * @qid: Queue ID 2071 * @match: Rx filter match type (see IONIC_RX_FILTER_MATCH_xxx) 2072 * @vlan: VLAN filter 2073 * @vlan.vlan: VLAN ID 2074 * @mac: MAC filter 2075 * @mac.addr: MAC address (network-byte order) 2076 * @mac_vlan: MACVLAN filter 2077 * @mac_vlan.vlan: VLAN ID 2078 * @mac_vlan.addr: MAC address (network-byte order) 2079 * @pkt_class: Packet classification filter 2080 * @rsvd: reserved byte(s) 2081 */ 2082 struct ionic_rx_filter_add_cmd { 2083 u8 opcode; 2084 u8 qtype; 2085 __le16 lif_index; 2086 __le32 qid; 2087 __le16 match; 2088 union { 2089 struct { 2090 __le16 vlan; 2091 } vlan; 2092 struct { 2093 u8 addr[6]; 2094 } mac; 2095 struct { 2096 __le16 vlan; 2097 u8 addr[6]; 2098 } mac_vlan; 2099 __le64 pkt_class; 2100 u8 rsvd[54]; 2101 } __packed; 2102 }; 2103 2104 /** 2105 * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion 2106 * @status: Status of the command (enum ionic_status_code) 2107 * @rsvd: reserved byte(s) 2108 * @comp_index: Index in the descriptor ring for which this is the completion 2109 * @filter_id: Filter ID 2110 * @rsvd2: reserved byte(s) 2111 * @color: Color bit 2112 */ 2113 struct ionic_rx_filter_add_comp { 2114 u8 status; 2115 u8 rsvd; 2116 __le16 comp_index; 2117 __le32 filter_id; 2118 u8 rsvd2[7]; 2119 u8 color; 2120 }; 2121 2122 /** 2123 * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command 2124 * @opcode: opcode 2125 * @rsvd: reserved byte(s) 2126 * @lif_index: LIF index 2127 * @filter_id: Filter ID 2128 * @rsvd2: reserved byte(s) 2129 */ 2130 struct ionic_rx_filter_del_cmd { 2131 u8 opcode; 2132 u8 rsvd; 2133 __le16 lif_index; 2134 __le32 filter_id; 2135 u8 rsvd2[56]; 2136 }; 2137 2138 typedef struct ionic_admin_comp ionic_rx_filter_del_comp; 2139 2140 enum ionic_vf_attr { 2141 IONIC_VF_ATTR_SPOOFCHK = 1, 2142 IONIC_VF_ATTR_TRUST = 2, 2143 IONIC_VF_ATTR_MAC = 3, 2144 IONIC_VF_ATTR_LINKSTATE = 4, 2145 IONIC_VF_ATTR_VLAN = 5, 2146 IONIC_VF_ATTR_RATE = 6, 2147 IONIC_VF_ATTR_STATSADDR = 7, 2148 }; 2149 2150 /** 2151 * enum ionic_vf_link_status - Virtual Function link status 2152 * @IONIC_VF_LINK_STATUS_AUTO: Use link state of the uplink 2153 * @IONIC_VF_LINK_STATUS_UP: Link always up 2154 * @IONIC_VF_LINK_STATUS_DOWN: Link always down 2155 */ 2156 enum ionic_vf_link_status { 2157 IONIC_VF_LINK_STATUS_AUTO = 0, 2158 IONIC_VF_LINK_STATUS_UP = 1, 2159 IONIC_VF_LINK_STATUS_DOWN = 2, 2160 }; 2161 2162 /** 2163 * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC 2164 * @opcode: Opcode 2165 * @attr: Attribute type (enum ionic_vf_attr) 2166 * @vf_index: VF index 2167 * @macaddr: mac address 2168 * @vlanid: vlan ID 2169 * @maxrate: max Tx rate in Mbps 2170 * @spoofchk: enable address spoof checking 2171 * @trust: enable VF trust 2172 * @linkstate: set link up or down 2173 * @stats_pa: set DMA address for VF stats 2174 * @pad: reserved byte(s) 2175 */ 2176 struct ionic_vf_setattr_cmd { 2177 u8 opcode; 2178 u8 attr; 2179 __le16 vf_index; 2180 union { 2181 u8 macaddr[6]; 2182 __le16 vlanid; 2183 __le32 maxrate; 2184 u8 spoofchk; 2185 u8 trust; 2186 u8 linkstate; 2187 __le64 stats_pa; 2188 u8 pad[60]; 2189 } __packed; 2190 }; 2191 2192 struct ionic_vf_setattr_comp { 2193 u8 status; 2194 u8 attr; 2195 __le16 vf_index; 2196 __le16 comp_index; 2197 u8 rsvd[9]; 2198 u8 color; 2199 }; 2200 2201 /** 2202 * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC 2203 * @opcode: Opcode 2204 * @attr: Attribute type (enum ionic_vf_attr) 2205 * @vf_index: VF index 2206 * @rsvd: reserved byte(s) 2207 */ 2208 struct ionic_vf_getattr_cmd { 2209 u8 opcode; 2210 u8 attr; 2211 __le16 vf_index; 2212 u8 rsvd[60]; 2213 }; 2214 2215 struct ionic_vf_getattr_comp { 2216 u8 status; 2217 u8 attr; 2218 __le16 vf_index; 2219 union { 2220 u8 macaddr[6]; 2221 __le16 vlanid; 2222 __le32 maxrate; 2223 u8 spoofchk; 2224 u8 trust; 2225 u8 linkstate; 2226 __le64 stats_pa; 2227 u8 pad[11]; 2228 } __packed; 2229 u8 color; 2230 }; 2231 2232 enum ionic_vf_ctrl_opcode { 2233 IONIC_VF_CTRL_START_ALL = 0, 2234 IONIC_VF_CTRL_START = 1, 2235 }; 2236 2237 /** 2238 * struct ionic_vf_ctrl_cmd - VF control command 2239 * @opcode: Opcode for the command 2240 * @ctrl_opcode: VF control operation type 2241 * @vf_index: VF Index. It is unused if op START_ALL is used. 2242 */ 2243 struct ionic_vf_ctrl_cmd { 2244 u8 opcode; 2245 u8 ctrl_opcode; 2246 __le16 vf_index; 2247 /* private: */ 2248 u8 rsvd1[60]; 2249 }; 2250 2251 /** 2252 * struct ionic_vf_ctrl_comp - VF_CTRL command completion. 2253 * @status: Status of the command (enum ionic_status_code) 2254 */ 2255 struct ionic_vf_ctrl_comp { 2256 u8 status; 2257 /* private: */ 2258 u8 rsvd[15]; 2259 }; 2260 2261 /** 2262 * struct ionic_discover_cmb_cmd - CMB discovery command 2263 * @opcode: Opcode for the command 2264 * @rsvd: Reserved bytes 2265 */ 2266 struct ionic_discover_cmb_cmd { 2267 u8 opcode; 2268 u8 rsvd[63]; 2269 }; 2270 2271 /** 2272 * struct ionic_discover_cmb_comp - CMB discover command completion. 2273 * @status: Status of the command (enum ionic_status_code) 2274 * @rsvd: Reserved bytes 2275 */ 2276 struct ionic_discover_cmb_comp { 2277 u8 status; 2278 u8 rsvd[15]; 2279 }; 2280 2281 #define IONIC_MAX_CMB_REGIONS 16 2282 #define IONIC_CMB_SHIFT_64K 16 2283 2284 enum ionic_cmb_type { 2285 IONIC_CMB_TYPE_DEVMEM = 0, 2286 IONIC_CMB_TYPE_EXPDB64 = 1, 2287 IONIC_CMB_TYPE_EXPDB128 = 2, 2288 IONIC_CMB_TYPE_EXPDB256 = 3, 2289 IONIC_CMB_TYPE_EXPDB512 = 4, 2290 }; 2291 2292 /** 2293 * union ionic_cmb_region - Configuration for CMB region 2294 * @bar_num: CMB mapping number from FW 2295 * @cmb_type: Type of CMB this region describes (enum ionic_cmb_type) 2296 * @rsvd: Reserved 2297 * @offset: Offset within BAR in 64KB pages 2298 * @length: Length of the CMB region 2299 * @words: 32-bit words for direct access to the entire region 2300 */ 2301 union ionic_cmb_region { 2302 struct { 2303 u8 bar_num; 2304 u8 cmb_type; 2305 u8 rsvd[6]; 2306 __le32 offset; 2307 __le32 length; 2308 } __packed; 2309 __le32 words[4]; 2310 }; 2311 2312 /** 2313 * union ionic_discover_cmb_identity - CMB layout identity structure 2314 * @num_regions: Number of CMB regions, up to 16 2315 * @flags: Feature and capability bits (0 for express 2316 * doorbell, 1 for 4K alignment indicator, 2317 * 31-24 for version information) 2318 * @region: CMB mappings region, entry 0 for regular 2319 * mapping, entries 1-7 for WQE sizes 64, 2320 * 128, 256, 512, 1024, 2048 and 4096 bytes 2321 * @words: Full union buffer size 2322 */ 2323 union ionic_discover_cmb_identity { 2324 struct { 2325 __le32 num_regions; 2326 #define IONIC_CMB_FLAG_EXPDB BIT(0) 2327 #define IONIC_CMB_FLAG_4KALIGN BIT(1) 2328 #define IONIC_CMB_FLAG_VERSION 0xff000000 2329 __le32 flags; 2330 union ionic_cmb_region region[IONIC_MAX_CMB_REGIONS]; 2331 }; 2332 __le32 words[478]; 2333 }; 2334 2335 /** 2336 * struct ionic_qos_identify_cmd - QoS identify command 2337 * @opcode: opcode 2338 * @ver: Highest version of identify supported by driver 2339 * @rsvd: reserved byte(s) 2340 */ 2341 struct ionic_qos_identify_cmd { 2342 u8 opcode; 2343 u8 ver; 2344 u8 rsvd[62]; 2345 }; 2346 2347 /** 2348 * struct ionic_qos_identify_comp - QoS identify command completion 2349 * @status: Status of the command (enum ionic_status_code) 2350 * @ver: Version of identify returned by device 2351 * @rsvd: reserved byte(s) 2352 */ 2353 struct ionic_qos_identify_comp { 2354 u8 status; 2355 u8 ver; 2356 u8 rsvd[14]; 2357 }; 2358 2359 #define IONIC_QOS_TC_MAX 8 2360 #define IONIC_QOS_ALL_TC 0xFF 2361 /* Capri max supported, should be renamed. */ 2362 #define IONIC_QOS_CLASS_MAX 7 2363 #define IONIC_QOS_PCP_MAX 8 2364 #define IONIC_QOS_CLASS_NAME_SZ 32 2365 #define IONIC_QOS_DSCP_MAX 64 2366 #define IONIC_QOS_ALL_PCP 0xFF 2367 #define IONIC_DSCP_BLOCK_SIZE 8 2368 2369 /* 2370 * enum ionic_qos_class 2371 */ 2372 enum ionic_qos_class { 2373 IONIC_QOS_CLASS_DEFAULT = 0, 2374 IONIC_QOS_CLASS_USER_DEFINED_1 = 1, 2375 IONIC_QOS_CLASS_USER_DEFINED_2 = 2, 2376 IONIC_QOS_CLASS_USER_DEFINED_3 = 3, 2377 IONIC_QOS_CLASS_USER_DEFINED_4 = 4, 2378 IONIC_QOS_CLASS_USER_DEFINED_5 = 5, 2379 IONIC_QOS_CLASS_USER_DEFINED_6 = 6, 2380 }; 2381 2382 /** 2383 * enum ionic_qos_class_type - Traffic classification criteria 2384 * @IONIC_QOS_CLASS_TYPE_NONE: No QoS 2385 * @IONIC_QOS_CLASS_TYPE_PCP: Dot1Q PCP 2386 * @IONIC_QOS_CLASS_TYPE_DSCP: IP DSCP 2387 */ 2388 enum ionic_qos_class_type { 2389 IONIC_QOS_CLASS_TYPE_NONE = 0, 2390 IONIC_QOS_CLASS_TYPE_PCP = 1, 2391 IONIC_QOS_CLASS_TYPE_DSCP = 2, 2392 }; 2393 2394 /** 2395 * enum ionic_qos_sched_type - QoS class scheduling type 2396 * @IONIC_QOS_SCHED_TYPE_STRICT: Strict priority 2397 * @IONIC_QOS_SCHED_TYPE_DWRR: Deficit weighted round-robin 2398 */ 2399 enum ionic_qos_sched_type { 2400 IONIC_QOS_SCHED_TYPE_STRICT = 0, 2401 IONIC_QOS_SCHED_TYPE_DWRR = 1, 2402 }; 2403 2404 /** 2405 * union ionic_qos_config - QoS configuration structure 2406 * @flags: Configuration flags 2407 * IONIC_QOS_CONFIG_F_ENABLE enable 2408 * IONIC_QOS_CONFIG_F_NO_DROP drop/nodrop 2409 * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite 2410 * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite 2411 * IONIC_QOS_CONFIG_F_NON_DISRUPTIVE Non-disruptive TC update 2412 * @sched_type: QoS class scheduling type (enum ionic_qos_sched_type) 2413 * @class_type: QoS class type (enum ionic_qos_class_type) 2414 * @pause_type: QoS pause type (enum ionic_qos_pause_type) 2415 * @name: QoS class name 2416 * @mtu: MTU of the class 2417 * @pfc_cos: Priority-Flow Control class of service 2418 * @dwrr_weight: QoS class scheduling weight 2419 * @strict_rlmt: Rate limit for strict priority scheduling 2420 * @rw_dot1q_pcp: Rewrite dot1q pcp to value (valid iff F_RW_DOT1Q_PCP) 2421 * @rw_ip_dscp: Rewrite ip dscp to value (valid iff F_RW_IP_DSCP) 2422 * @dot1q_pcp: Dot1q pcp value 2423 * @ndscp: Number of valid dscp values in the ip_dscp field 2424 * @ip_dscp: IP dscp values 2425 * @words: word access to struct contents 2426 */ 2427 union ionic_qos_config { 2428 struct { 2429 #define IONIC_QOS_CONFIG_F_ENABLE BIT(0) 2430 #define IONIC_QOS_CONFIG_F_NO_DROP BIT(1) 2431 /* Used to rewrite PCP or DSCP value. */ 2432 #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2) 2433 #define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3) 2434 /* Non-disruptive TC update */ 2435 #define IONIC_QOS_CONFIG_F_NON_DISRUPTIVE BIT(4) 2436 u8 flags; 2437 u8 sched_type; 2438 u8 class_type; 2439 u8 pause_type; 2440 char name[IONIC_QOS_CLASS_NAME_SZ]; 2441 __le32 mtu; 2442 /* flow control */ 2443 u8 pfc_cos; 2444 /* scheduler */ 2445 union { 2446 u8 dwrr_weight; 2447 __le64 strict_rlmt; 2448 }; 2449 /* marking */ 2450 /* Used to rewrite PCP or DSCP value. */ 2451 union { 2452 u8 rw_dot1q_pcp; 2453 u8 rw_ip_dscp; 2454 }; 2455 /* classification */ 2456 union { 2457 u8 dot1q_pcp; 2458 struct { 2459 u8 ndscp; 2460 u8 ip_dscp[IONIC_QOS_DSCP_MAX]; 2461 }; 2462 }; 2463 }; 2464 __le32 words[64]; 2465 }; 2466 2467 /** 2468 * union ionic_qos_identity - QoS identity structure 2469 * @version: Version of the identify structure 2470 * @type: QoS system type 2471 * @rsvd: reserved byte(s) 2472 * @config: Current configuration of classes 2473 * @words: word access to struct contents 2474 */ 2475 union ionic_qos_identity { 2476 struct { 2477 u8 version; 2478 u8 type; 2479 u8 rsvd[62]; 2480 union ionic_qos_config config[IONIC_QOS_CLASS_MAX]; 2481 }; 2482 __le32 words[478]; 2483 }; 2484 2485 /** 2486 * struct ionic_qos_init_cmd - QoS config init command 2487 * @opcode: Opcode 2488 * @group: QoS class id 2489 * @rsvd: reserved byte(s) 2490 * @info_pa: destination address for qos info 2491 * @rsvd1: reserved byte(s) 2492 */ 2493 struct ionic_qos_init_cmd { 2494 u8 opcode; 2495 u8 group; 2496 u8 rsvd[6]; 2497 __le64 info_pa; 2498 u8 rsvd1[48]; 2499 }; 2500 2501 typedef struct ionic_admin_comp ionic_qos_init_comp; 2502 2503 /** 2504 * struct ionic_qos_reset_cmd - QoS config reset command 2505 * @opcode: Opcode 2506 * @group: QoS class id 2507 * @rsvd: reserved byte(s) 2508 */ 2509 struct ionic_qos_reset_cmd { 2510 u8 opcode; 2511 u8 group; 2512 u8 rsvd[62]; 2513 }; 2514 2515 /** 2516 * struct ionic_qos_clear_stats_cmd - Qos config reset command 2517 * @opcode: Opcode 2518 * @group_bitmap: bitmap of groups to be cleared 2519 * @rsvd: reserved byte(s) 2520 */ 2521 struct ionic_qos_clear_stats_cmd { 2522 u8 opcode; 2523 u8 group_bitmap; 2524 u8 rsvd[62]; 2525 }; 2526 2527 typedef struct ionic_admin_comp ionic_qos_reset_comp; 2528 2529 /** 2530 * struct ionic_fw_download_cmd - Firmware download command 2531 * @opcode: opcode 2532 * @rsvd: reserved byte(s) 2533 * @addr: dma address of the firmware buffer 2534 * @offset: offset of the firmware buffer within the full image 2535 * @length: number of valid bytes in the firmware buffer 2536 */ 2537 struct ionic_fw_download_cmd { 2538 u8 opcode; 2539 u8 rsvd[3]; 2540 __le32 offset; 2541 __le64 addr; 2542 __le32 length; 2543 }; 2544 2545 typedef struct ionic_admin_comp ionic_fw_download_comp; 2546 2547 /** 2548 * enum ionic_fw_control_oper - FW control operations 2549 * @IONIC_FW_RESET: Reset firmware 2550 * @IONIC_FW_INSTALL: Install firmware 2551 * @IONIC_FW_ACTIVATE: Activate firmware 2552 * @IONIC_FW_INSTALL_ASYNC: Install firmware asynchronously 2553 * @IONIC_FW_INSTALL_STATUS: Firmware installation status 2554 * @IONIC_FW_ACTIVATE_ASYNC: Activate firmware asynchronously 2555 * @IONIC_FW_ACTIVATE_STATUS: Firmware activate status 2556 * @IONIC_FW_UPDATE_CLEANUP: Clean up after an interrupted fw update 2557 */ 2558 enum ionic_fw_control_oper { 2559 IONIC_FW_RESET = 0, 2560 IONIC_FW_INSTALL = 1, 2561 IONIC_FW_ACTIVATE = 2, 2562 IONIC_FW_INSTALL_ASYNC = 3, 2563 IONIC_FW_INSTALL_STATUS = 4, 2564 IONIC_FW_ACTIVATE_ASYNC = 5, 2565 IONIC_FW_ACTIVATE_STATUS = 6, 2566 IONIC_FW_UPDATE_CLEANUP = 7, 2567 }; 2568 2569 /** 2570 * struct ionic_fw_control_cmd - Firmware control command 2571 * @opcode: opcode 2572 * @rsvd: reserved byte(s) 2573 * @oper: firmware control operation (enum ionic_fw_control_oper) 2574 * @slot: slot to activate 2575 * @rsvd1: reserved byte(s) 2576 */ 2577 struct ionic_fw_control_cmd { 2578 u8 opcode; 2579 u8 rsvd[3]; 2580 u8 oper; 2581 u8 slot; 2582 u8 rsvd1[58]; 2583 }; 2584 2585 /** 2586 * struct ionic_fw_control_comp - Firmware control copletion 2587 * @status: Status of the command (enum ionic_status_code) 2588 * @rsvd: reserved byte(s) 2589 * @comp_index: Index in the descriptor ring for which this is the completion 2590 * @slot: Slot where the firmware was installed 2591 * @rsvd1: reserved byte(s) 2592 * @color: Color bit 2593 */ 2594 struct ionic_fw_control_comp { 2595 u8 status; 2596 u8 rsvd; 2597 __le16 comp_index; 2598 u8 slot; 2599 u8 rsvd1[10]; 2600 u8 color; 2601 }; 2602 2603 /****************************************************************** 2604 ******************* RDMA Commands ******************************** 2605 ******************************************************************/ 2606 2607 /** 2608 * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd 2609 * @opcode: opcode 2610 * @rsvd: reserved byte(s) 2611 * @lif_index: LIF index 2612 * @rsvd2: reserved byte(s) 2613 * 2614 * There is no RDMA specific dev command completion struct. Completion uses 2615 * the common struct ionic_admin_comp. Only the status is indicated. 2616 * Nonzero status means the LIF does not support RDMA. 2617 **/ 2618 struct ionic_rdma_reset_cmd { 2619 u8 opcode; 2620 u8 rsvd; 2621 __le16 lif_index; 2622 u8 rsvd2[60]; 2623 }; 2624 2625 /** 2626 * struct ionic_rdma_queue_cmd - Create RDMA Queue command 2627 * @opcode: opcode, 52, 53 2628 * @rsvd: reserved byte(s) 2629 * @lif_index: LIF index 2630 * @qid_ver: (qid | (RDMA version << 24)) 2631 * @cid: intr, eq_id, or cq_id 2632 * @dbid: doorbell page id 2633 * @depth_log2: log base two of queue depth 2634 * @stride_log2: log base two of queue stride 2635 * @dma_addr: address of the queue memory 2636 * @udma_idx: udma index 2637 * @rsvd2: reserved byte(s) 2638 * 2639 * The same command struct is used to create an RDMA event queue, completion 2640 * queue, or RDMA admin queue. The cid is an interrupt number for an event 2641 * queue, an event queue id for a completion queue, or a completion queue id 2642 * for an RDMA admin queue. 2643 * 2644 * The queue created via a dev command must be contiguous in dma space. 2645 * 2646 * The dev commands are intended only to be used during driver initialization, 2647 * to create queues supporting the RDMA admin queue. Other queues, and other 2648 * types of RDMA resources like memory regions, will be created and registered 2649 * via the RDMA admin queue, and will support a more complete interface 2650 * providing scatter gather lists for larger, scattered queue buffers and 2651 * memory registration. 2652 * 2653 * There is no RDMA specific dev command completion struct. Completion uses 2654 * the common struct ionic_admin_comp. Only the status is indicated. 2655 **/ 2656 struct ionic_rdma_queue_cmd { 2657 u8 opcode; 2658 u8 rsvd; 2659 __le16 lif_index; 2660 __le32 qid_ver; 2661 __le32 cid; 2662 __le16 dbid; 2663 u8 depth_log2; 2664 u8 stride_log2; 2665 __le64 dma_addr; 2666 u8 udma_idx; 2667 u8 rsvd2[39]; 2668 }; 2669 2670 /****************************************************************** 2671 ******************* Notify Events ******************************** 2672 ******************************************************************/ 2673 2674 /** 2675 * struct ionic_notifyq_event - Generic event reporting structure 2676 * @eid: event number 2677 * @ecode: event code 2678 * @data: unspecified data about the event 2679 * 2680 * This is the generic event report struct from which the other 2681 * actual events will be formed. 2682 */ 2683 struct ionic_notifyq_event { 2684 __le64 eid; 2685 __le16 ecode; 2686 u8 data[54]; 2687 }; 2688 2689 /** 2690 * struct ionic_link_change_event - Link change event notification 2691 * @eid: event number 2692 * @ecode: event code = IONIC_EVENT_LINK_CHANGE 2693 * @link_status: link up/down, with error bits (enum ionic_port_status) 2694 * @link_speed: speed of the network link 2695 * @rsvd: reserved byte(s) 2696 * 2697 * Sent when the network link state changes between UP and DOWN 2698 */ 2699 struct ionic_link_change_event { 2700 __le64 eid; 2701 __le16 ecode; 2702 __le16 link_status; 2703 __le32 link_speed; /* units of 1Mbps: e.g. 10000 = 10Gbps */ 2704 u8 rsvd[48]; 2705 }; 2706 2707 /** 2708 * struct ionic_reset_event - Reset event notification 2709 * @eid: event number 2710 * @ecode: event code = IONIC_EVENT_RESET 2711 * @reset_code: reset type 2712 * @state: 0=pending, 1=complete, 2=error 2713 * @rsvd: reserved byte(s) 2714 * 2715 * Sent when the NIC or some subsystem is going to be or 2716 * has been reset. 2717 */ 2718 struct ionic_reset_event { 2719 __le64 eid; 2720 __le16 ecode; 2721 u8 reset_code; 2722 u8 state; 2723 u8 rsvd[52]; 2724 }; 2725 2726 /** 2727 * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health 2728 * @eid: event number 2729 * @ecode: event code = IONIC_EVENT_HEARTBEAT 2730 * @rsvd: reserved byte(s) 2731 */ 2732 struct ionic_heartbeat_event { 2733 __le64 eid; 2734 __le16 ecode; 2735 u8 rsvd[54]; 2736 }; 2737 2738 /** 2739 * struct ionic_log_event - Sent to notify the driver of an internal error 2740 * @eid: event number 2741 * @ecode: event code = IONIC_EVENT_LOG 2742 * @data: log data 2743 */ 2744 struct ionic_log_event { 2745 __le64 eid; 2746 __le16 ecode; 2747 u8 data[54]; 2748 }; 2749 2750 /** 2751 * struct ionic_xcvr_event - Transceiver change event 2752 * @eid: event number 2753 * @ecode: event code = IONIC_EVENT_XCVR 2754 * @rsvd: reserved byte(s) 2755 */ 2756 struct ionic_xcvr_event { 2757 __le64 eid; 2758 __le16 ecode; 2759 u8 rsvd[54]; 2760 }; 2761 2762 /* 2763 * struct ionic_port_stats - Port statistics structure 2764 */ 2765 struct ionic_port_stats { 2766 __le64 frames_rx_ok; 2767 __le64 frames_rx_all; 2768 __le64 frames_rx_bad_fcs; 2769 __le64 frames_rx_bad_all; 2770 __le64 octets_rx_ok; 2771 __le64 octets_rx_all; 2772 __le64 frames_rx_unicast; 2773 __le64 frames_rx_multicast; 2774 __le64 frames_rx_broadcast; 2775 __le64 frames_rx_pause; 2776 __le64 frames_rx_bad_length; 2777 __le64 frames_rx_undersized; 2778 __le64 frames_rx_oversized; 2779 __le64 frames_rx_fragments; 2780 __le64 frames_rx_jabber; 2781 __le64 frames_rx_pripause; 2782 __le64 frames_rx_stomped_crc; 2783 __le64 frames_rx_too_long; 2784 __le64 frames_rx_vlan_good; 2785 __le64 frames_rx_dropped; 2786 __le64 frames_rx_less_than_64b; 2787 __le64 frames_rx_64b; 2788 __le64 frames_rx_65b_127b; 2789 __le64 frames_rx_128b_255b; 2790 __le64 frames_rx_256b_511b; 2791 __le64 frames_rx_512b_1023b; 2792 __le64 frames_rx_1024b_1518b; 2793 __le64 frames_rx_1519b_2047b; 2794 __le64 frames_rx_2048b_4095b; 2795 __le64 frames_rx_4096b_8191b; 2796 __le64 frames_rx_8192b_9215b; 2797 __le64 frames_rx_other; 2798 __le64 frames_tx_ok; 2799 __le64 frames_tx_all; 2800 __le64 frames_tx_bad; 2801 __le64 octets_tx_ok; 2802 __le64 octets_tx_total; 2803 __le64 frames_tx_unicast; 2804 __le64 frames_tx_multicast; 2805 __le64 frames_tx_broadcast; 2806 __le64 frames_tx_pause; 2807 __le64 frames_tx_pripause; 2808 __le64 frames_tx_vlan; 2809 __le64 frames_tx_less_than_64b; 2810 __le64 frames_tx_64b; 2811 __le64 frames_tx_65b_127b; 2812 __le64 frames_tx_128b_255b; 2813 __le64 frames_tx_256b_511b; 2814 __le64 frames_tx_512b_1023b; 2815 __le64 frames_tx_1024b_1518b; 2816 __le64 frames_tx_1519b_2047b; 2817 __le64 frames_tx_2048b_4095b; 2818 __le64 frames_tx_4096b_8191b; 2819 __le64 frames_tx_8192b_9215b; 2820 __le64 frames_tx_other; 2821 __le64 frames_tx_pri_0; 2822 __le64 frames_tx_pri_1; 2823 __le64 frames_tx_pri_2; 2824 __le64 frames_tx_pri_3; 2825 __le64 frames_tx_pri_4; 2826 __le64 frames_tx_pri_5; 2827 __le64 frames_tx_pri_6; 2828 __le64 frames_tx_pri_7; 2829 __le64 frames_rx_pri_0; 2830 __le64 frames_rx_pri_1; 2831 __le64 frames_rx_pri_2; 2832 __le64 frames_rx_pri_3; 2833 __le64 frames_rx_pri_4; 2834 __le64 frames_rx_pri_5; 2835 __le64 frames_rx_pri_6; 2836 __le64 frames_rx_pri_7; 2837 __le64 tx_pripause_0_1us_count; 2838 __le64 tx_pripause_1_1us_count; 2839 __le64 tx_pripause_2_1us_count; 2840 __le64 tx_pripause_3_1us_count; 2841 __le64 tx_pripause_4_1us_count; 2842 __le64 tx_pripause_5_1us_count; 2843 __le64 tx_pripause_6_1us_count; 2844 __le64 tx_pripause_7_1us_count; 2845 __le64 rx_pripause_0_1us_count; 2846 __le64 rx_pripause_1_1us_count; 2847 __le64 rx_pripause_2_1us_count; 2848 __le64 rx_pripause_3_1us_count; 2849 __le64 rx_pripause_4_1us_count; 2850 __le64 rx_pripause_5_1us_count; 2851 __le64 rx_pripause_6_1us_count; 2852 __le64 rx_pripause_7_1us_count; 2853 __le64 rx_pause_1us_count; 2854 __le64 frames_tx_truncated; 2855 }; 2856 2857 struct ionic_mgmt_port_stats { 2858 __le64 frames_rx_ok; 2859 __le64 frames_rx_all; 2860 __le64 frames_rx_bad_fcs; 2861 __le64 frames_rx_bad_all; 2862 __le64 octets_rx_ok; 2863 __le64 octets_rx_all; 2864 __le64 frames_rx_unicast; 2865 __le64 frames_rx_multicast; 2866 __le64 frames_rx_broadcast; 2867 __le64 frames_rx_pause; 2868 __le64 frames_rx_bad_length; 2869 __le64 frames_rx_undersized; 2870 __le64 frames_rx_oversized; 2871 __le64 frames_rx_fragments; 2872 __le64 frames_rx_jabber; 2873 __le64 frames_rx_64b; 2874 __le64 frames_rx_65b_127b; 2875 __le64 frames_rx_128b_255b; 2876 __le64 frames_rx_256b_511b; 2877 __le64 frames_rx_512b_1023b; 2878 __le64 frames_rx_1024b_1518b; 2879 __le64 frames_rx_gt_1518b; 2880 __le64 frames_rx_fifo_full; 2881 __le64 frames_tx_ok; 2882 __le64 frames_tx_all; 2883 __le64 frames_tx_bad; 2884 __le64 octets_tx_ok; 2885 __le64 octets_tx_total; 2886 __le64 frames_tx_unicast; 2887 __le64 frames_tx_multicast; 2888 __le64 frames_tx_broadcast; 2889 __le64 frames_tx_pause; 2890 }; 2891 2892 struct ionic_port_extra_stats { 2893 __le64 rsfec_correctable_blocks; 2894 __le64 rsfec_uncorrectable_blocks; 2895 __le64 fec_corrected_bits_total; 2896 __le64 rx_bits_phy; 2897 __le64 fec_codeword_error_bin[16]; 2898 }; 2899 2900 /** 2901 * struct ionic_port_identity - port identity structure 2902 * @version: identity structure version 2903 * @type: type of port (enum ionic_port_type) 2904 * @num_lanes: number of lanes for the port 2905 * @autoneg: autoneg supported 2906 * @min_frame_size: minimum frame size supported 2907 * @max_frame_size: maximum frame size supported 2908 * @fec_type: supported fec types 2909 * @pause_type: supported pause types 2910 * @loopback_mode: supported loopback mode 2911 * @speeds: supported speeds 2912 * @rsvd2: reserved byte(s) 2913 * @config: current port configuration 2914 * @words: word access to struct contents 2915 */ 2916 union ionic_port_identity { 2917 struct { 2918 u8 version; 2919 u8 type; 2920 u8 num_lanes; 2921 u8 autoneg; 2922 __le32 min_frame_size; 2923 __le32 max_frame_size; 2924 u8 fec_type[4]; 2925 u8 pause_type[2]; 2926 u8 loopback_mode[2]; 2927 __le32 speeds[16]; 2928 u8 rsvd2[44]; 2929 union ionic_port_config config; 2930 }; 2931 __le32 words[478]; 2932 }; 2933 2934 /** 2935 * struct ionic_port_info - port info structure 2936 * @config: Port configuration data 2937 * @status: Port status data 2938 * @stats: Port statistics data 2939 * @mgmt_stats: Port management statistics data 2940 * @sprom_epage: Extended Transceiver sprom 2941 * @sprom_page1: Extended Transceiver sprom, page 1 2942 * @sprom_page2: Extended Transceiver sprom, page 2 2943 * @sprom_page17: Extended Transceiver sprom, page 17 2944 * @rsvd: reserved byte(s) 2945 * @extra_stats: Extra port statistics data 2946 */ 2947 struct ionic_port_info { 2948 union ionic_port_config config; 2949 struct ionic_port_status status; 2950 union { 2951 struct ionic_port_stats stats; 2952 struct ionic_mgmt_port_stats mgmt_stats; 2953 }; 2954 union { 2955 u8 sprom_epage[384]; 2956 struct { 2957 u8 sprom_page1[128]; 2958 u8 sprom_page2[128]; 2959 u8 sprom_page17[128]; 2960 }; 2961 }; 2962 u8 rsvd[376]; 2963 struct ionic_port_extra_stats extra_stats; 2964 }; 2965 2966 /* 2967 * struct ionic_lif_stats - LIF statistics structure 2968 */ 2969 struct ionic_lif_stats { 2970 /* RX */ 2971 __le64 rx_ucast_bytes; 2972 __le64 rx_ucast_packets; 2973 __le64 rx_mcast_bytes; 2974 __le64 rx_mcast_packets; 2975 __le64 rx_bcast_bytes; 2976 __le64 rx_bcast_packets; 2977 __le64 rsvd0; 2978 __le64 rsvd1; 2979 /* RX drops */ 2980 __le64 rx_ucast_drop_bytes; 2981 __le64 rx_ucast_drop_packets; 2982 __le64 rx_mcast_drop_bytes; 2983 __le64 rx_mcast_drop_packets; 2984 __le64 rx_bcast_drop_bytes; 2985 __le64 rx_bcast_drop_packets; 2986 __le64 rx_dma_error; 2987 __le64 rsvd2; 2988 /* TX */ 2989 __le64 tx_ucast_bytes; 2990 __le64 tx_ucast_packets; 2991 __le64 tx_mcast_bytes; 2992 __le64 tx_mcast_packets; 2993 __le64 tx_bcast_bytes; 2994 __le64 tx_bcast_packets; 2995 __le64 rsvd3; 2996 __le64 rsvd4; 2997 /* TX drops */ 2998 __le64 tx_ucast_drop_bytes; 2999 __le64 tx_ucast_drop_packets; 3000 __le64 tx_mcast_drop_bytes; 3001 __le64 tx_mcast_drop_packets; 3002 __le64 tx_bcast_drop_bytes; 3003 __le64 tx_bcast_drop_packets; 3004 __le64 tx_dma_error; 3005 __le64 rsvd5; 3006 /* Rx Queue/Ring drops */ 3007 __le64 rx_queue_disabled; 3008 __le64 rx_queue_empty; 3009 __le64 rx_queue_error; 3010 __le64 rx_desc_fetch_error; 3011 __le64 rx_desc_data_error; 3012 __le64 rsvd6; 3013 __le64 rsvd7; 3014 __le64 rsvd8; 3015 /* Tx Queue/Ring drops */ 3016 __le64 tx_queue_disabled; 3017 __le64 tx_queue_error; 3018 __le64 tx_desc_fetch_error; 3019 __le64 tx_desc_data_error; 3020 __le64 tx_queue_empty; 3021 __le64 rsvd10; 3022 __le64 rsvd11; 3023 __le64 rsvd12; 3024 3025 /* RDMA/ROCE TX */ 3026 __le64 tx_rdma_ucast_bytes; 3027 __le64 tx_rdma_ucast_packets; 3028 __le64 tx_rdma_mcast_bytes; 3029 __le64 tx_rdma_mcast_packets; 3030 __le64 tx_rdma_cnp_packets; 3031 __le64 rsvd13; 3032 __le64 rsvd14; 3033 __le64 rsvd15; 3034 3035 /* RDMA/ROCE RX */ 3036 __le64 rx_rdma_ucast_bytes; 3037 __le64 rx_rdma_ucast_packets; 3038 __le64 rx_rdma_mcast_bytes; 3039 __le64 rx_rdma_mcast_packets; 3040 __le64 rx_rdma_cnp_packets; 3041 __le64 rx_rdma_ecn_packets; 3042 __le64 rsvd16; 3043 __le64 rsvd17; 3044 3045 __le64 rsvd18; 3046 __le64 rsvd19; 3047 __le64 rsvd20; 3048 __le64 rsvd21; 3049 __le64 rsvd22; 3050 __le64 rsvd23; 3051 __le64 rsvd24; 3052 __le64 rsvd25; 3053 3054 __le64 rsvd26; 3055 __le64 rsvd27; 3056 __le64 rsvd28; 3057 __le64 rsvd29; 3058 __le64 rsvd30; 3059 __le64 rsvd31; 3060 __le64 rsvd32; 3061 __le64 rsvd33; 3062 3063 __le64 rsvd34; 3064 __le64 rsvd35; 3065 __le64 rsvd36; 3066 __le64 rsvd37; 3067 __le64 rsvd38; 3068 __le64 rsvd39; 3069 __le64 rsvd40; 3070 __le64 rsvd41; 3071 3072 __le64 rsvd42; 3073 __le64 rsvd43; 3074 __le64 rsvd44; 3075 __le64 rsvd45; 3076 __le64 rsvd46; 3077 __le64 rsvd47; 3078 __le64 rsvd48; 3079 __le64 rsvd49; 3080 3081 /* RDMA/ROCE REQ Error/Debugs (768 - 895) */ 3082 __le64 rdma_req_rx_pkt_seq_err; 3083 __le64 rdma_req_rx_rnr_retry_err; 3084 __le64 rdma_req_rx_remote_access_err; 3085 __le64 rdma_req_rx_remote_inv_req_err; 3086 __le64 rdma_req_rx_remote_oper_err; 3087 __le64 rdma_req_rx_implied_nak_seq_err; 3088 __le64 rdma_req_rx_cqe_err; 3089 __le64 rdma_req_rx_cqe_flush_err; 3090 3091 __le64 rdma_req_rx_dup_responses; 3092 __le64 rdma_req_rx_invalid_packets; 3093 __le64 rdma_req_tx_local_access_err; 3094 __le64 rdma_req_tx_local_oper_err; 3095 __le64 rdma_req_tx_memory_mgmt_err; 3096 __le64 rsvd52; 3097 __le64 rsvd53; 3098 __le64 rsvd54; 3099 3100 /* RDMA/ROCE RESP Error/Debugs (896 - 1023) */ 3101 __le64 rdma_resp_rx_dup_requests; 3102 __le64 rdma_resp_rx_out_of_buffer; 3103 __le64 rdma_resp_rx_out_of_seq_pkts; 3104 __le64 rdma_resp_rx_cqe_err; 3105 __le64 rdma_resp_rx_cqe_flush_err; 3106 __le64 rdma_resp_rx_local_len_err; 3107 __le64 rdma_resp_rx_inv_request_err; 3108 __le64 rdma_resp_rx_local_qp_oper_err; 3109 3110 __le64 rdma_resp_rx_out_of_atomic_resource; 3111 __le64 rdma_resp_tx_pkt_seq_err; 3112 __le64 rdma_resp_tx_remote_inv_req_err; 3113 __le64 rdma_resp_tx_remote_access_err; 3114 __le64 rdma_resp_tx_remote_oper_err; 3115 __le64 rdma_resp_tx_rnr_retry_err; 3116 __le64 rsvd57; 3117 __le64 rsvd58; 3118 }; 3119 3120 /** 3121 * struct ionic_lif_info - LIF info structure 3122 * @config: LIF configuration structure 3123 * @status: LIF status structure 3124 * @stats: LIF statistics structure 3125 */ 3126 struct ionic_lif_info { 3127 union ionic_lif_config config; 3128 struct ionic_lif_status status; 3129 struct ionic_lif_stats stats; 3130 }; 3131 3132 union ionic_dev_cmd { 3133 u32 words[16]; 3134 struct ionic_admin_cmd cmd; 3135 struct ionic_nop_cmd nop; 3136 3137 struct ionic_dev_identify_cmd identify; 3138 struct ionic_dev_init_cmd init; 3139 struct ionic_dev_reset_cmd reset; 3140 struct ionic_dev_getattr_cmd getattr; 3141 struct ionic_dev_setattr_cmd setattr; 3142 3143 struct ionic_port_identify_cmd port_identify; 3144 struct ionic_port_init_cmd port_init; 3145 struct ionic_port_reset_cmd port_reset; 3146 struct ionic_port_getattr_cmd port_getattr; 3147 struct ionic_port_setattr_cmd port_setattr; 3148 3149 struct ionic_vf_setattr_cmd vf_setattr; 3150 struct ionic_vf_getattr_cmd vf_getattr; 3151 struct ionic_vf_ctrl_cmd vf_ctrl; 3152 3153 struct ionic_discover_cmb_cmd discover_cmb; 3154 3155 struct ionic_lif_identify_cmd lif_identify; 3156 struct ionic_lif_init_cmd lif_init; 3157 struct ionic_lif_reset_cmd lif_reset; 3158 3159 struct ionic_qos_identify_cmd qos_identify; 3160 struct ionic_qos_init_cmd qos_init; 3161 struct ionic_qos_reset_cmd qos_reset; 3162 struct ionic_qos_clear_stats_cmd qos_clear_stats; 3163 3164 struct ionic_q_identify_cmd q_identify; 3165 struct ionic_q_init_cmd q_init; 3166 struct ionic_q_control_cmd q_control; 3167 3168 struct ionic_fw_download_cmd fw_download; 3169 struct ionic_fw_control_cmd fw_control; 3170 }; 3171 3172 union ionic_dev_cmd_comp { 3173 u32 words[4]; 3174 u8 status; 3175 struct ionic_admin_comp comp; 3176 struct ionic_nop_comp nop; 3177 3178 struct ionic_dev_identify_comp identify; 3179 struct ionic_dev_init_comp init; 3180 struct ionic_dev_reset_comp reset; 3181 struct ionic_dev_getattr_comp getattr; 3182 struct ionic_dev_setattr_comp setattr; 3183 3184 struct ionic_port_identify_comp port_identify; 3185 struct ionic_port_init_comp port_init; 3186 struct ionic_port_reset_comp port_reset; 3187 struct ionic_port_getattr_comp port_getattr; 3188 struct ionic_port_setattr_comp port_setattr; 3189 3190 struct ionic_vf_setattr_comp vf_setattr; 3191 struct ionic_vf_getattr_comp vf_getattr; 3192 struct ionic_vf_ctrl_comp vf_ctrl; 3193 3194 struct ionic_discover_cmb_comp discover_cmb; 3195 3196 struct ionic_lif_identify_comp lif_identify; 3197 struct ionic_lif_init_comp lif_init; 3198 ionic_lif_reset_comp lif_reset; 3199 3200 struct ionic_qos_identify_comp qos_identify; 3201 ionic_qos_init_comp qos_init; 3202 ionic_qos_reset_comp qos_reset; 3203 3204 struct ionic_q_identify_comp q_identify; 3205 struct ionic_q_init_comp q_init; 3206 3207 ionic_fw_download_comp fw_download; 3208 struct ionic_fw_control_comp fw_control; 3209 }; 3210 3211 /** 3212 * struct ionic_hwstamp_regs - Hardware current timestamp registers 3213 * @tick_low: Low 32 bits of hardware timestamp 3214 * @tick_high: High 32 bits of hardware timestamp 3215 */ 3216 struct ionic_hwstamp_regs { 3217 u32 tick_low; 3218 u32 tick_high; 3219 }; 3220 3221 /** 3222 * union ionic_dev_info_regs - Device info register format (read-only) 3223 * @signature: Signature value of 0x44455649 ('DEVI') 3224 * @version: Current version of info 3225 * @asic_type: Asic type 3226 * @asic_rev: Asic revision 3227 * @fw_status: Firmware status 3228 * bit 0 - 1 = fw running 3229 * bit 4-7 - 4 bit generation number, changes on fw restart 3230 * @fw_heartbeat: Firmware heartbeat counter 3231 * @serial_num: Serial number 3232 * @rsvd_pad1024: reserved byte(s) 3233 * @fw_version: Firmware version 3234 * @hwstamp: Hardware current timestamp registers 3235 * @words: word access to struct contents 3236 */ 3237 union ionic_dev_info_regs { 3238 #define IONIC_DEVINFO_FWVERS_BUFLEN 32 3239 #define IONIC_DEVINFO_SERIAL_BUFLEN 32 3240 struct { 3241 u32 signature; 3242 u8 version; 3243 u8 asic_type; 3244 u8 asic_rev; 3245 #define IONIC_FW_STS_F_RUNNING 0x01 3246 #define IONIC_FW_STS_F_GENERATION 0xF0 3247 u8 fw_status; 3248 u32 fw_heartbeat; 3249 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN]; 3250 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN]; 3251 u8 rsvd_pad1024[948]; 3252 struct ionic_hwstamp_regs hwstamp; 3253 }; 3254 u32 words[512]; 3255 }; 3256 3257 /** 3258 * union ionic_dev_cmd_regs - Device command register format (read-write) 3259 * @doorbell: Device Cmd Doorbell, write-only 3260 * Write a 1 to signal device to process cmd, 3261 * poll done for completion. 3262 * @done: Done indicator, bit 0 == 1 when command is complete 3263 * @cmd: Opcode-specific command bytes 3264 * @comp: Opcode-specific response bytes 3265 * @rsvd: reserved byte(s) 3266 * @data: Opcode-specific side-data 3267 * @words: word access to struct contents 3268 */ 3269 union ionic_dev_cmd_regs { 3270 struct { 3271 u32 doorbell; 3272 u32 done; 3273 union ionic_dev_cmd cmd; 3274 union ionic_dev_cmd_comp comp; 3275 u8 rsvd[48]; 3276 u32 data[478]; 3277 } __packed; 3278 u32 words[512]; 3279 }; 3280 3281 /** 3282 * union ionic_dev_regs - Device register format for bar 0 page 0 3283 * @info: Device info registers 3284 * @devcmd: Device command registers 3285 * @words: word access to struct contents 3286 */ 3287 union ionic_dev_regs { 3288 struct { 3289 union ionic_dev_info_regs info; 3290 union ionic_dev_cmd_regs devcmd; 3291 } __packed; 3292 __le32 words[1024]; 3293 }; 3294 3295 union ionic_adminq_cmd { 3296 struct ionic_admin_cmd cmd; 3297 struct ionic_nop_cmd nop; 3298 struct ionic_q_identify_cmd q_identify; 3299 struct ionic_q_init_cmd q_init; 3300 struct ionic_q_control_cmd q_control; 3301 struct ionic_lif_setattr_cmd lif_setattr; 3302 struct ionic_lif_getattr_cmd lif_getattr; 3303 struct ionic_lif_setphc_cmd lif_setphc; 3304 struct ionic_rx_mode_set_cmd rx_mode_set; 3305 struct ionic_rx_filter_add_cmd rx_filter_add; 3306 struct ionic_rx_filter_del_cmd rx_filter_del; 3307 struct ionic_rdma_reset_cmd rdma_reset; 3308 struct ionic_rdma_queue_cmd rdma_queue; 3309 struct ionic_fw_download_cmd fw_download; 3310 struct ionic_fw_control_cmd fw_control; 3311 }; 3312 3313 union ionic_adminq_comp { 3314 struct ionic_admin_comp comp; 3315 struct ionic_nop_comp nop; 3316 struct ionic_q_identify_comp q_identify; 3317 struct ionic_q_init_comp q_init; 3318 struct ionic_lif_setattr_comp lif_setattr; 3319 struct ionic_lif_getattr_comp lif_getattr; 3320 struct ionic_admin_comp lif_setphc; 3321 struct ionic_rx_filter_add_comp rx_filter_add; 3322 struct ionic_fw_control_comp fw_control; 3323 }; 3324 3325 #define IONIC_BARS_MAX 6 3326 #define IONIC_PCI_BAR_DBELL 1 3327 #define IONIC_PCI_BAR_CMB 2 3328 3329 #define IONIC_BAR0_SIZE 0x8000 3330 #define IONIC_BAR2_SIZE 0x800000 3331 3332 #define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000 3333 #define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800 3334 #define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00 3335 #define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000 3336 #define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000 3337 3338 /* BAR2 */ 3339 #define IONIC_BAR2_CMB_ENTRY_SIZE 0x800000 3340 #define IONIC_DEV_CMD_DONE 0x00000001 3341 3342 #define IONIC_ASIC_TYPE_NONE 0 3343 #define IONIC_ASIC_TYPE_CAPRI 1 3344 #define IONIC_ASIC_TYPE_ELBA 2 3345 #define IONIC_ASIC_TYPE_GIGLIO 3 3346 #define IONIC_ASIC_TYPE_SALINA 4 3347 3348 /** 3349 * struct ionic_doorbell - Doorbell register layout 3350 * @p_index: Producer index 3351 * @ring: Selects the specific ring of the queue to update 3352 * Type-specific meaning: 3353 * ring=0: Default producer/consumer queue 3354 * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs 3355 * send events to EQs when armed. EQs send 3356 * interrupts when armed. 3357 * @qid_lo: Queue destination for the producer index and flags (low bits) 3358 * @qid_hi: Queue destination for the producer index and flags (high bits) 3359 * @rsvd2: reserved byte(s) 3360 */ 3361 struct ionic_doorbell { 3362 __le16 p_index; 3363 u8 ring; 3364 u8 qid_lo; 3365 __le16 qid_hi; 3366 u16 rsvd2; 3367 }; 3368 3369 struct ionic_intr_status { 3370 u32 status[2]; 3371 }; 3372 3373 struct ionic_notifyq_cmd { 3374 __le32 data; /* Not used but needed for qcq structure */ 3375 }; 3376 3377 union ionic_notifyq_comp { 3378 struct ionic_notifyq_event event; 3379 struct ionic_link_change_event link_change; 3380 struct ionic_reset_event reset; 3381 struct ionic_heartbeat_event heartbeat; 3382 struct ionic_log_event log; 3383 }; 3384 3385 /* Deprecate */ 3386 struct ionic_identity { 3387 union ionic_drv_identity drv; 3388 union ionic_dev_identity dev; 3389 union ionic_lif_identity lif; 3390 union ionic_port_identity port; 3391 union ionic_qos_identity qos; 3392 union ionic_q_identity txq; 3393 union ionic_discover_cmb_identity cmb_layout; 3394 }; 3395 3396 #endif /* _IONIC_IF_H_ */ 3397