1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/module.h> 5 #include <linux/netdevice.h> 6 #include <linux/sfp.h> 7 8 #include "ionic.h" 9 #include "ionic_bus.h" 10 #include "ionic_lif.h" 11 #include "ionic_ethtool.h" 12 #include "ionic_stats.h" 13 14 #define IONIC_MAX_RX_COPYBREAK min(U16_MAX, IONIC_MAX_BUF_LEN) 15 16 static void ionic_get_stats_strings(struct ionic_lif *lif, u8 *buf) 17 { 18 u32 i; 19 20 for (i = 0; i < ionic_num_stats_grps; i++) 21 ionic_stats_groups[i].get_strings(lif, &buf); 22 } 23 24 static void ionic_get_stats(struct net_device *netdev, 25 struct ethtool_stats *stats, u64 *buf) 26 { 27 struct ionic_lif *lif = netdev_priv(netdev); 28 u32 i; 29 30 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 31 return; 32 33 memset(buf, 0, stats->n_stats * sizeof(*buf)); 34 for (i = 0; i < ionic_num_stats_grps; i++) 35 ionic_stats_groups[i].get_values(lif, &buf); 36 } 37 38 static int ionic_get_stats_count(struct ionic_lif *lif) 39 { 40 int i, num_stats = 0; 41 42 for (i = 0; i < ionic_num_stats_grps; i++) 43 num_stats += ionic_stats_groups[i].get_count(lif); 44 45 return num_stats; 46 } 47 48 static int ionic_get_sset_count(struct net_device *netdev, int sset) 49 { 50 struct ionic_lif *lif = netdev_priv(netdev); 51 int count = 0; 52 53 switch (sset) { 54 case ETH_SS_STATS: 55 count = ionic_get_stats_count(lif); 56 break; 57 } 58 return count; 59 } 60 61 static void ionic_get_strings(struct net_device *netdev, 62 u32 sset, u8 *buf) 63 { 64 struct ionic_lif *lif = netdev_priv(netdev); 65 66 switch (sset) { 67 case ETH_SS_STATS: 68 ionic_get_stats_strings(lif, buf); 69 break; 70 } 71 } 72 73 static void ionic_get_drvinfo(struct net_device *netdev, 74 struct ethtool_drvinfo *drvinfo) 75 { 76 struct ionic_lif *lif = netdev_priv(netdev); 77 struct ionic *ionic = lif->ionic; 78 79 strscpy(drvinfo->driver, IONIC_DRV_NAME, sizeof(drvinfo->driver)); 80 strscpy(drvinfo->fw_version, ionic->idev.dev_info.fw_version, 81 sizeof(drvinfo->fw_version)); 82 strscpy(drvinfo->bus_info, ionic_bus_info(ionic), 83 sizeof(drvinfo->bus_info)); 84 } 85 86 static int ionic_get_regs_len(struct net_device *netdev) 87 { 88 return (IONIC_DEV_INFO_REG_COUNT + IONIC_DEV_CMD_REG_COUNT) * sizeof(u32); 89 } 90 91 static void ionic_get_regs(struct net_device *netdev, struct ethtool_regs *regs, 92 void *p) 93 { 94 struct ionic_lif *lif = netdev_priv(netdev); 95 struct ionic_dev *idev; 96 unsigned int offset; 97 unsigned int size; 98 99 regs->version = IONIC_DEV_CMD_REG_VERSION; 100 101 idev = &lif->ionic->idev; 102 if (!idev->dev_info_regs) 103 return; 104 105 offset = 0; 106 size = IONIC_DEV_INFO_REG_COUNT * sizeof(u32); 107 memcpy_fromio(p + offset, lif->ionic->idev.dev_info_regs->words, size); 108 109 offset += size; 110 size = IONIC_DEV_CMD_REG_COUNT * sizeof(u32); 111 memcpy_fromio(p + offset, idev->dev_cmd_regs->words, size); 112 } 113 114 static void ionic_get_link_ext_stats(struct net_device *netdev, 115 struct ethtool_link_ext_stats *stats) 116 { 117 struct ionic_lif *lif = netdev_priv(netdev); 118 119 if (lif->ionic->pdev->is_physfn) 120 stats->link_down_events = lif->link_down_count; 121 } 122 123 static int ionic_get_link_ksettings(struct net_device *netdev, 124 struct ethtool_link_ksettings *ks) 125 { 126 struct ionic_lif *lif = netdev_priv(netdev); 127 struct ionic_dev *idev = &lif->ionic->idev; 128 int copper_seen = 0; 129 130 ethtool_link_ksettings_zero_link_mode(ks, supported); 131 132 if (!idev->port_info) { 133 netdev_err(netdev, "port_info not initialized\n"); 134 return -EOPNOTSUPP; 135 } 136 137 /* The port_info data is found in a DMA space that the NIC keeps 138 * up-to-date, so there's no need to request the data from the 139 * NIC, we already have it in our memory space. 140 */ 141 142 switch (le16_to_cpu(idev->port_info->status.xcvr.pid)) { 143 /* Copper */ 144 case IONIC_XCVR_PID_QSFP_100G_CR4: 145 ethtool_link_ksettings_add_link_mode(ks, supported, 146 100000baseCR4_Full); 147 copper_seen++; 148 break; 149 case IONIC_XCVR_PID_QSFP_40GBASE_CR4: 150 ethtool_link_ksettings_add_link_mode(ks, supported, 151 40000baseCR4_Full); 152 copper_seen++; 153 break; 154 case IONIC_XCVR_PID_SFP_25GBASE_CR_S: 155 case IONIC_XCVR_PID_SFP_25GBASE_CR_L: 156 case IONIC_XCVR_PID_SFP_25GBASE_CR_N: 157 ethtool_link_ksettings_add_link_mode(ks, supported, 158 25000baseCR_Full); 159 copper_seen++; 160 break; 161 case IONIC_XCVR_PID_QSFP_50G_CR2_FC: 162 case IONIC_XCVR_PID_QSFP_50G_CR2: 163 ethtool_link_ksettings_add_link_mode(ks, supported, 164 50000baseCR2_Full); 165 copper_seen++; 166 break; 167 case IONIC_XCVR_PID_QSFP_200G_CR4: 168 ethtool_link_ksettings_add_link_mode(ks, supported, 200000baseCR4_Full); 169 copper_seen++; 170 break; 171 case IONIC_XCVR_PID_QSFP_400G_CR4: 172 ethtool_link_ksettings_add_link_mode(ks, supported, 400000baseCR4_Full); 173 copper_seen++; 174 break; 175 case IONIC_XCVR_PID_SFP_10GBASE_AOC: 176 case IONIC_XCVR_PID_SFP_10GBASE_CU: 177 ethtool_link_ksettings_add_link_mode(ks, supported, 178 10000baseCR_Full); 179 copper_seen++; 180 break; 181 182 /* Fibre */ 183 case IONIC_XCVR_PID_QSFP_100G_SR4: 184 case IONIC_XCVR_PID_QSFP_100G_AOC: 185 ethtool_link_ksettings_add_link_mode(ks, supported, 186 100000baseSR4_Full); 187 break; 188 case IONIC_XCVR_PID_QSFP_100G_CWDM4: 189 case IONIC_XCVR_PID_QSFP_100G_PSM4: 190 case IONIC_XCVR_PID_QSFP_100G_LR4: 191 case IONIC_XCVR_PID_QSFP_100G_ER4: 192 case IONIC_XCVR_PID_QSFP_100G_FR4: 193 case IONIC_XCVR_PID_QSFP_100G_DR4: 194 ethtool_link_ksettings_add_link_mode(ks, supported, 195 100000baseLR4_ER4_Full); 196 break; 197 case IONIC_XCVR_PID_QSFP_40GBASE_SR4: 198 case IONIC_XCVR_PID_QSFP_40GBASE_AOC: 199 ethtool_link_ksettings_add_link_mode(ks, supported, 200 40000baseSR4_Full); 201 break; 202 case IONIC_XCVR_PID_QSFP_40GBASE_LR4: 203 ethtool_link_ksettings_add_link_mode(ks, supported, 204 40000baseLR4_Full); 205 break; 206 case IONIC_XCVR_PID_SFP_25GBASE_SR: 207 case IONIC_XCVR_PID_SFP_25GBASE_AOC: 208 case IONIC_XCVR_PID_SFP_25GBASE_ACC: 209 ethtool_link_ksettings_add_link_mode(ks, supported, 210 25000baseSR_Full); 211 break; 212 case IONIC_XCVR_PID_QSFP_200G_AOC: 213 case IONIC_XCVR_PID_QSFP_200G_SR4: 214 case IONIC_XCVR_PID_QSFP_200G_AEC: 215 ethtool_link_ksettings_add_link_mode(ks, supported, 216 200000baseSR4_Full); 217 break; 218 case IONIC_XCVR_PID_QSFP_200G_FR4: 219 ethtool_link_ksettings_add_link_mode(ks, supported, 220 200000baseLR4_ER4_FR4_Full); 221 break; 222 case IONIC_XCVR_PID_QSFP_200G_DR4: 223 ethtool_link_ksettings_add_link_mode(ks, supported, 224 200000baseDR4_Full); 225 break; 226 case IONIC_XCVR_PID_QSFP_400G_FR4: 227 ethtool_link_ksettings_add_link_mode(ks, supported, 228 400000baseLR4_ER4_FR4_Full); 229 break; 230 case IONIC_XCVR_PID_QSFP_400G_DR4: 231 ethtool_link_ksettings_add_link_mode(ks, supported, 232 400000baseDR4_Full); 233 break; 234 case IONIC_XCVR_PID_QSFP_400G_SR4: 235 case IONIC_XCVR_PID_QSFP_400G_AOC: 236 case IONIC_XCVR_PID_QSFP_400G_AEC: 237 case IONIC_XCVR_PID_QSFP_400G_LPO: 238 ethtool_link_ksettings_add_link_mode(ks, supported, 239 400000baseSR4_Full); 240 break; 241 case IONIC_XCVR_PID_SFP_10GBASE_SR: 242 ethtool_link_ksettings_add_link_mode(ks, supported, 243 10000baseSR_Full); 244 break; 245 case IONIC_XCVR_PID_SFP_10GBASE_LR: 246 ethtool_link_ksettings_add_link_mode(ks, supported, 247 10000baseLR_Full); 248 break; 249 case IONIC_XCVR_PID_SFP_10GBASE_LRM: 250 ethtool_link_ksettings_add_link_mode(ks, supported, 251 10000baseLRM_Full); 252 break; 253 case IONIC_XCVR_PID_SFP_10GBASE_ER: 254 ethtool_link_ksettings_add_link_mode(ks, supported, 255 10000baseER_Full); 256 break; 257 case IONIC_XCVR_PID_SFP_10GBASE_T: 258 ethtool_link_ksettings_add_link_mode(ks, supported, 259 10000baseT_Full); 260 break; 261 case IONIC_XCVR_PID_SFP_1000BASE_T: 262 ethtool_link_ksettings_add_link_mode(ks, supported, 263 1000baseT_Full); 264 break; 265 case IONIC_XCVR_PID_UNKNOWN: 266 /* This means there's no module plugged in */ 267 break; 268 default: 269 dev_dbg_ratelimited(lif->ionic->dev, 270 "unknown xcvr type pid=%d / 0x%x\n", 271 idev->port_info->status.xcvr.pid, 272 idev->port_info->status.xcvr.pid); 273 break; 274 } 275 276 linkmode_copy(ks->link_modes.advertising, ks->link_modes.supported); 277 278 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_BASER); 279 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_RS); 280 if (idev->port_info->config.fec_type == IONIC_PORT_FEC_TYPE_FC) 281 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_BASER); 282 else if (idev->port_info->config.fec_type == IONIC_PORT_FEC_TYPE_RS) 283 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_RS); 284 285 ethtool_link_ksettings_add_link_mode(ks, supported, FIBRE); 286 ethtool_link_ksettings_add_link_mode(ks, supported, Pause); 287 288 if (idev->port_info->status.xcvr.phy == IONIC_PHY_TYPE_COPPER || 289 copper_seen) 290 ks->base.port = PORT_DA; 291 else if (idev->port_info->status.xcvr.phy == IONIC_PHY_TYPE_FIBER) 292 ks->base.port = PORT_FIBRE; 293 else 294 ks->base.port = PORT_NONE; 295 296 if (ks->base.port != PORT_NONE) { 297 ks->base.speed = le32_to_cpu(lif->info->status.link_speed); 298 299 if (le16_to_cpu(lif->info->status.link_status)) 300 ks->base.duplex = DUPLEX_FULL; 301 else 302 ks->base.duplex = DUPLEX_UNKNOWN; 303 304 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg); 305 306 if (idev->port_info->config.an_enable) { 307 ethtool_link_ksettings_add_link_mode(ks, advertising, 308 Autoneg); 309 ks->base.autoneg = AUTONEG_ENABLE; 310 } 311 } 312 313 return 0; 314 } 315 316 static int ionic_set_link_ksettings(struct net_device *netdev, 317 const struct ethtool_link_ksettings *ks) 318 { 319 struct ionic_lif *lif = netdev_priv(netdev); 320 struct ionic_dev *idev = &lif->ionic->idev; 321 struct ionic *ionic = lif->ionic; 322 int err = 0; 323 324 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 325 return -EBUSY; 326 327 /* set autoneg */ 328 if (ks->base.autoneg != idev->port_info->config.an_enable) { 329 mutex_lock(&ionic->dev_cmd_lock); 330 ionic_dev_cmd_port_autoneg(idev, ks->base.autoneg); 331 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 332 mutex_unlock(&ionic->dev_cmd_lock); 333 if (err) 334 return err; 335 } 336 337 /* set speed */ 338 if (ks->base.speed != le32_to_cpu(idev->port_info->config.speed)) { 339 mutex_lock(&ionic->dev_cmd_lock); 340 ionic_dev_cmd_port_speed(idev, ks->base.speed); 341 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 342 mutex_unlock(&ionic->dev_cmd_lock); 343 if (err) 344 return err; 345 } 346 347 return 0; 348 } 349 350 static void ionic_get_pauseparam(struct net_device *netdev, 351 struct ethtool_pauseparam *pause) 352 { 353 struct ionic_lif *lif = netdev_priv(netdev); 354 u8 pause_type; 355 356 pause->autoneg = 0; 357 358 pause_type = lif->ionic->idev.port_info->config.pause_type; 359 if (pause_type) { 360 pause->rx_pause = (pause_type & IONIC_PAUSE_F_RX) ? 1 : 0; 361 pause->tx_pause = (pause_type & IONIC_PAUSE_F_TX) ? 1 : 0; 362 } 363 } 364 365 static int ionic_set_pauseparam(struct net_device *netdev, 366 struct ethtool_pauseparam *pause) 367 { 368 struct ionic_lif *lif = netdev_priv(netdev); 369 struct ionic *ionic = lif->ionic; 370 u32 requested_pause; 371 int err; 372 373 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 374 return -EBUSY; 375 376 if (pause->autoneg) 377 return -EOPNOTSUPP; 378 379 /* change both at the same time */ 380 requested_pause = IONIC_PORT_PAUSE_TYPE_LINK; 381 if (pause->rx_pause) 382 requested_pause |= IONIC_PAUSE_F_RX; 383 if (pause->tx_pause) 384 requested_pause |= IONIC_PAUSE_F_TX; 385 386 if (requested_pause == lif->ionic->idev.port_info->config.pause_type) 387 return 0; 388 389 mutex_lock(&ionic->dev_cmd_lock); 390 ionic_dev_cmd_port_pause(&lif->ionic->idev, requested_pause); 391 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 392 mutex_unlock(&ionic->dev_cmd_lock); 393 if (err) 394 return err; 395 396 return 0; 397 } 398 399 static int ionic_get_fecparam(struct net_device *netdev, 400 struct ethtool_fecparam *fec) 401 { 402 struct ionic_lif *lif = netdev_priv(netdev); 403 404 switch (lif->ionic->idev.port_info->config.fec_type) { 405 case IONIC_PORT_FEC_TYPE_NONE: 406 fec->active_fec = ETHTOOL_FEC_OFF; 407 break; 408 case IONIC_PORT_FEC_TYPE_RS: 409 fec->active_fec = ETHTOOL_FEC_RS; 410 break; 411 case IONIC_PORT_FEC_TYPE_FC: 412 fec->active_fec = ETHTOOL_FEC_BASER; 413 break; 414 } 415 416 fec->fec = ETHTOOL_FEC_OFF | ETHTOOL_FEC_RS | ETHTOOL_FEC_BASER; 417 418 return 0; 419 } 420 421 static int ionic_set_fecparam(struct net_device *netdev, 422 struct ethtool_fecparam *fec) 423 { 424 struct ionic_lif *lif = netdev_priv(netdev); 425 u8 fec_type; 426 int ret = 0; 427 428 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 429 return -EBUSY; 430 431 if (lif->ionic->idev.port_info->config.an_enable) { 432 netdev_err(netdev, "FEC request not allowed while autoneg is enabled\n"); 433 return -EINVAL; 434 } 435 436 switch (fec->fec) { 437 case ETHTOOL_FEC_NONE: 438 fec_type = IONIC_PORT_FEC_TYPE_NONE; 439 break; 440 case ETHTOOL_FEC_OFF: 441 fec_type = IONIC_PORT_FEC_TYPE_NONE; 442 break; 443 case ETHTOOL_FEC_RS: 444 fec_type = IONIC_PORT_FEC_TYPE_RS; 445 break; 446 case ETHTOOL_FEC_BASER: 447 fec_type = IONIC_PORT_FEC_TYPE_FC; 448 break; 449 case ETHTOOL_FEC_AUTO: 450 default: 451 netdev_err(netdev, "FEC request 0x%04x not supported\n", 452 fec->fec); 453 return -EINVAL; 454 } 455 456 if (fec_type != lif->ionic->idev.port_info->config.fec_type) { 457 mutex_lock(&lif->ionic->dev_cmd_lock); 458 ionic_dev_cmd_port_fec(&lif->ionic->idev, fec_type); 459 ret = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 460 mutex_unlock(&lif->ionic->dev_cmd_lock); 461 } 462 463 return ret; 464 } 465 466 static int ionic_get_coalesce(struct net_device *netdev, 467 struct ethtool_coalesce *coalesce, 468 struct kernel_ethtool_coalesce *kernel_coal, 469 struct netlink_ext_ack *extack) 470 { 471 struct ionic_lif *lif = netdev_priv(netdev); 472 473 coalesce->tx_coalesce_usecs = lif->tx_coalesce_usecs; 474 coalesce->rx_coalesce_usecs = lif->rx_coalesce_usecs; 475 476 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 477 coalesce->use_adaptive_tx_coalesce = test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 478 else 479 coalesce->use_adaptive_tx_coalesce = 0; 480 481 coalesce->use_adaptive_rx_coalesce = test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 482 483 return 0; 484 } 485 486 static int ionic_set_coalesce(struct net_device *netdev, 487 struct ethtool_coalesce *coalesce, 488 struct kernel_ethtool_coalesce *kernel_coal, 489 struct netlink_ext_ack *extack) 490 { 491 struct ionic_lif *lif = netdev_priv(netdev); 492 struct ionic_identity *ident; 493 u32 rx_coal, rx_dim; 494 u32 tx_coal, tx_dim; 495 unsigned int i; 496 497 ident = &lif->ionic->ident; 498 if (ident->dev.intr_coal_div == 0) { 499 netdev_warn(netdev, "bad HW value in dev.intr_coal_div = %d\n", 500 ident->dev.intr_coal_div); 501 return -EIO; 502 } 503 504 /* Tx normally shares Rx interrupt, so only change Rx if not split */ 505 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) && 506 (coalesce->tx_coalesce_usecs != lif->rx_coalesce_usecs || 507 coalesce->use_adaptive_tx_coalesce)) { 508 netdev_warn(netdev, "only rx parameters can be changed\n"); 509 return -EINVAL; 510 } 511 512 /* Convert the usec request to a HW usable value. If they asked 513 * for non-zero and it resolved to zero, bump it up 514 */ 515 rx_coal = ionic_coal_usec_to_hw(lif->ionic, coalesce->rx_coalesce_usecs); 516 if (!rx_coal && coalesce->rx_coalesce_usecs) 517 rx_coal = 1; 518 tx_coal = ionic_coal_usec_to_hw(lif->ionic, coalesce->tx_coalesce_usecs); 519 if (!tx_coal && coalesce->tx_coalesce_usecs) 520 tx_coal = 1; 521 522 if (rx_coal > IONIC_INTR_CTRL_COAL_MAX || 523 tx_coal > IONIC_INTR_CTRL_COAL_MAX) 524 return -ERANGE; 525 526 /* Save the new values */ 527 lif->rx_coalesce_usecs = coalesce->rx_coalesce_usecs; 528 lif->rx_coalesce_hw = rx_coal; 529 530 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 531 lif->tx_coalesce_usecs = coalesce->tx_coalesce_usecs; 532 else 533 lif->tx_coalesce_usecs = coalesce->rx_coalesce_usecs; 534 lif->tx_coalesce_hw = tx_coal; 535 536 if (coalesce->use_adaptive_rx_coalesce) { 537 set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 538 rx_dim = rx_coal; 539 } else { 540 clear_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 541 rx_dim = 0; 542 } 543 544 if (coalesce->use_adaptive_tx_coalesce) { 545 set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 546 tx_dim = tx_coal; 547 } else { 548 clear_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 549 tx_dim = 0; 550 } 551 552 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 553 for (i = 0; i < lif->nxqs; i++) { 554 if (lif->rxqcqs[i]->flags & IONIC_QCQ_F_INTR) { 555 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 556 lif->rxqcqs[i]->intr.index, 557 lif->rx_coalesce_hw); 558 lif->rxqcqs[i]->intr.dim_coal_hw = rx_dim; 559 } 560 561 if (lif->txqcqs[i]->flags & IONIC_QCQ_F_INTR) { 562 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 563 lif->txqcqs[i]->intr.index, 564 lif->tx_coalesce_hw); 565 lif->txqcqs[i]->intr.dim_coal_hw = tx_dim; 566 } 567 } 568 } 569 570 return 0; 571 } 572 573 static int ionic_validate_cmb_config(struct ionic_lif *lif, 574 struct ionic_queue_params *qparam) 575 { 576 int pages_have, pages_required = 0; 577 unsigned long sz; 578 579 if (!lif->ionic->idev.cmb_inuse && 580 (qparam->cmb_tx || qparam->cmb_rx)) { 581 netdev_info(lif->netdev, "CMB rings are not supported on this device\n"); 582 return -EOPNOTSUPP; 583 } 584 585 if (qparam->cmb_tx) { 586 if (!(lif->qtype_info[IONIC_QTYPE_TXQ].features & IONIC_QIDENT_F_CMB)) { 587 netdev_info(lif->netdev, 588 "CMB rings for tx-push are not supported on this device\n"); 589 return -EOPNOTSUPP; 590 } 591 592 sz = sizeof(struct ionic_txq_desc) * qparam->ntxq_descs * qparam->nxqs; 593 pages_required += ALIGN(sz, PAGE_SIZE) / PAGE_SIZE; 594 } 595 596 if (qparam->cmb_rx) { 597 if (!(lif->qtype_info[IONIC_QTYPE_RXQ].features & IONIC_QIDENT_F_CMB)) { 598 netdev_info(lif->netdev, 599 "CMB rings for rx-push are not supported on this device\n"); 600 return -EOPNOTSUPP; 601 } 602 603 sz = sizeof(struct ionic_rxq_desc) * qparam->nrxq_descs * qparam->nxqs; 604 pages_required += ALIGN(sz, PAGE_SIZE) / PAGE_SIZE; 605 } 606 607 pages_have = lif->ionic->bars[IONIC_PCI_BAR_CMB].len / PAGE_SIZE; 608 if (pages_required > pages_have) { 609 netdev_info(lif->netdev, 610 "Not enough CMB pages for number of queues and size of descriptor rings, need %d have %d", 611 pages_required, pages_have); 612 return -ENOMEM; 613 } 614 615 return pages_required; 616 } 617 618 static int ionic_cmb_rings_toggle(struct ionic_lif *lif, bool cmb_tx, bool cmb_rx) 619 { 620 struct ionic_queue_params qparam; 621 int pages_used; 622 623 if (netif_running(lif->netdev)) { 624 netdev_info(lif->netdev, "Please stop device to toggle CMB for tx/rx-push\n"); 625 return -EBUSY; 626 } 627 628 ionic_init_queue_params(lif, &qparam); 629 qparam.cmb_tx = cmb_tx; 630 qparam.cmb_rx = cmb_rx; 631 pages_used = ionic_validate_cmb_config(lif, &qparam); 632 if (pages_used < 0) 633 return pages_used; 634 635 if (cmb_tx) 636 set_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state); 637 else 638 clear_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state); 639 640 if (cmb_rx) 641 set_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state); 642 else 643 clear_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state); 644 645 if (cmb_tx || cmb_rx) 646 netdev_info(lif->netdev, "Enabling CMB %s %s rings - %d pages\n", 647 cmb_tx ? "TX" : "", cmb_rx ? "RX" : "", pages_used); 648 else 649 netdev_info(lif->netdev, "Disabling CMB rings\n"); 650 651 return 0; 652 } 653 654 static void ionic_get_ringparam(struct net_device *netdev, 655 struct ethtool_ringparam *ring, 656 struct kernel_ethtool_ringparam *kernel_ring, 657 struct netlink_ext_ack *extack) 658 { 659 struct ionic_lif *lif = netdev_priv(netdev); 660 661 ring->tx_max_pending = IONIC_MAX_TX_DESC; 662 ring->tx_pending = lif->ntxq_descs; 663 ring->rx_max_pending = IONIC_MAX_RX_DESC; 664 ring->rx_pending = lif->nrxq_descs; 665 kernel_ring->tx_push = test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state); 666 kernel_ring->rx_push = test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state); 667 } 668 669 static int ionic_set_ringparam(struct net_device *netdev, 670 struct ethtool_ringparam *ring, 671 struct kernel_ethtool_ringparam *kernel_ring, 672 struct netlink_ext_ack *extack) 673 { 674 struct ionic_lif *lif = netdev_priv(netdev); 675 struct ionic_queue_params qparam; 676 int err; 677 678 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 679 return -EBUSY; 680 681 ionic_init_queue_params(lif, &qparam); 682 683 if (ring->rx_mini_pending || ring->rx_jumbo_pending) { 684 netdev_info(netdev, "Changing jumbo or mini descriptors not supported\n"); 685 return -EINVAL; 686 } 687 688 if (!is_power_of_2(ring->tx_pending) || 689 !is_power_of_2(ring->rx_pending)) { 690 netdev_info(netdev, "Descriptor count must be a power of 2\n"); 691 return -EINVAL; 692 } 693 694 /* if nothing to do return success */ 695 if (ring->tx_pending == lif->ntxq_descs && 696 ring->rx_pending == lif->nrxq_descs && 697 kernel_ring->tx_push == test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state) && 698 kernel_ring->rx_push == test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state)) 699 return 0; 700 701 qparam.ntxq_descs = ring->tx_pending; 702 qparam.nrxq_descs = ring->rx_pending; 703 qparam.cmb_tx = kernel_ring->tx_push; 704 qparam.cmb_rx = kernel_ring->rx_push; 705 706 err = ionic_validate_cmb_config(lif, &qparam); 707 if (err < 0) 708 return err; 709 710 if (kernel_ring->tx_push != test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state) || 711 kernel_ring->rx_push != test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state)) { 712 err = ionic_cmb_rings_toggle(lif, kernel_ring->tx_push, 713 kernel_ring->rx_push); 714 if (err < 0) 715 return err; 716 } 717 718 if (ring->tx_pending != lif->ntxq_descs) 719 netdev_info(netdev, "Changing Tx ring size from %d to %d\n", 720 lif->ntxq_descs, ring->tx_pending); 721 722 if (ring->rx_pending != lif->nrxq_descs) 723 netdev_info(netdev, "Changing Rx ring size from %d to %d\n", 724 lif->nrxq_descs, ring->rx_pending); 725 726 /* if we're not running, just set the values and return */ 727 if (!netif_running(lif->netdev)) { 728 lif->ntxq_descs = ring->tx_pending; 729 lif->nrxq_descs = ring->rx_pending; 730 return 0; 731 } 732 733 mutex_lock(&lif->queue_lock); 734 err = ionic_reconfigure_queues(lif, &qparam); 735 mutex_unlock(&lif->queue_lock); 736 if (err) 737 netdev_info(netdev, "Ring reconfiguration failed, changes canceled: %d\n", err); 738 739 return err; 740 } 741 742 static void ionic_get_channels(struct net_device *netdev, 743 struct ethtool_channels *ch) 744 { 745 struct ionic_lif *lif = netdev_priv(netdev); 746 747 /* report maximum channels */ 748 ch->max_combined = lif->ionic->ntxqs_per_lif; 749 ch->max_rx = lif->ionic->ntxqs_per_lif / 2; 750 ch->max_tx = lif->ionic->ntxqs_per_lif / 2; 751 752 /* report current channels */ 753 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) { 754 ch->rx_count = lif->nxqs; 755 ch->tx_count = lif->nxqs; 756 } else { 757 ch->combined_count = lif->nxqs; 758 } 759 } 760 761 static int ionic_set_channels(struct net_device *netdev, 762 struct ethtool_channels *ch) 763 { 764 struct ionic_lif *lif = netdev_priv(netdev); 765 struct ionic_queue_params qparam; 766 int max_cnt; 767 int err; 768 769 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 770 return -EBUSY; 771 772 ionic_init_queue_params(lif, &qparam); 773 774 if ((ch->rx_count || ch->tx_count) && lif->xdp_prog) { 775 netdev_info(lif->netdev, "Split Tx/Rx interrupts not available when using XDP\n"); 776 return -EOPNOTSUPP; 777 } 778 779 if (ch->rx_count != ch->tx_count) { 780 netdev_info(netdev, "The rx and tx count must be equal\n"); 781 return -EINVAL; 782 } 783 784 if (ch->combined_count && ch->rx_count) { 785 netdev_info(netdev, "Use either combined or rx and tx, not both\n"); 786 return -EINVAL; 787 } 788 789 max_cnt = lif->ionic->ntxqs_per_lif; 790 if (ch->combined_count) { 791 if (ch->combined_count > max_cnt) 792 return -EINVAL; 793 794 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 795 netdev_info(lif->netdev, "Sharing queue interrupts\n"); 796 else if (ch->combined_count == lif->nxqs) 797 return 0; 798 799 if (lif->nxqs != ch->combined_count) 800 netdev_info(netdev, "Changing queue count from %d to %d\n", 801 lif->nxqs, ch->combined_count); 802 803 qparam.nxqs = ch->combined_count; 804 qparam.intr_split = false; 805 } else { 806 max_cnt /= 2; 807 if (ch->rx_count > max_cnt) 808 return -EINVAL; 809 810 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 811 netdev_info(lif->netdev, "Splitting queue interrupts\n"); 812 else if (ch->rx_count == lif->nxqs) 813 return 0; 814 815 if (lif->nxqs != ch->rx_count) 816 netdev_info(netdev, "Changing queue count from %d to %d\n", 817 lif->nxqs, ch->rx_count); 818 819 qparam.nxqs = ch->rx_count; 820 qparam.intr_split = true; 821 } 822 823 err = ionic_validate_cmb_config(lif, &qparam); 824 if (err < 0) 825 return err; 826 827 /* if we're not running, just set the values and return */ 828 if (!netif_running(lif->netdev)) { 829 lif->nxqs = qparam.nxqs; 830 831 if (qparam.intr_split) { 832 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 833 } else { 834 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 835 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 836 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 837 } 838 return 0; 839 } 840 841 mutex_lock(&lif->queue_lock); 842 err = ionic_reconfigure_queues(lif, &qparam); 843 mutex_unlock(&lif->queue_lock); 844 if (err) 845 netdev_info(netdev, "Queue reconfiguration failed, changes canceled: %d\n", err); 846 847 return err; 848 } 849 850 static u32 ionic_get_rx_ring_count(struct net_device *netdev) 851 { 852 struct ionic_lif *lif = netdev_priv(netdev); 853 854 return lif->nxqs; 855 } 856 857 static u32 ionic_get_rxfh_indir_size(struct net_device *netdev) 858 { 859 struct ionic_lif *lif = netdev_priv(netdev); 860 861 return le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 862 } 863 864 static u32 ionic_get_rxfh_key_size(struct net_device *netdev) 865 { 866 return IONIC_RSS_HASH_KEY_SIZE; 867 } 868 869 static int ionic_get_rxfh(struct net_device *netdev, 870 struct ethtool_rxfh_param *rxfh) 871 { 872 struct ionic_lif *lif = netdev_priv(netdev); 873 unsigned int i, tbl_sz; 874 875 if (rxfh->indir) { 876 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 877 for (i = 0; i < tbl_sz; i++) 878 rxfh->indir[i] = lif->rss_ind_tbl[i]; 879 } 880 881 if (rxfh->key) 882 memcpy(rxfh->key, lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE); 883 884 rxfh->hfunc = ETH_RSS_HASH_TOP; 885 886 return 0; 887 } 888 889 static int ionic_set_rxfh(struct net_device *netdev, 890 struct ethtool_rxfh_param *rxfh, 891 struct netlink_ext_ack *extack) 892 { 893 struct ionic_lif *lif = netdev_priv(netdev); 894 895 if (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE && 896 rxfh->hfunc != ETH_RSS_HASH_TOP) 897 return -EOPNOTSUPP; 898 899 return ionic_lif_rss_config(lif, lif->rss_types, 900 rxfh->key, rxfh->indir); 901 } 902 903 static int ionic_set_tunable(struct net_device *dev, 904 const struct ethtool_tunable *tuna, 905 const void *data) 906 { 907 struct ionic_lif *lif = netdev_priv(dev); 908 u32 rx_copybreak; 909 910 switch (tuna->id) { 911 case ETHTOOL_RX_COPYBREAK: 912 rx_copybreak = *(u32 *)data; 913 if (rx_copybreak > IONIC_MAX_RX_COPYBREAK) { 914 netdev_err(dev, "Max supported rx_copybreak size: %u\n", 915 IONIC_MAX_RX_COPYBREAK); 916 return -EINVAL; 917 } 918 lif->rx_copybreak = (u16)rx_copybreak; 919 break; 920 default: 921 return -EOPNOTSUPP; 922 } 923 924 return 0; 925 } 926 927 static int ionic_get_tunable(struct net_device *netdev, 928 const struct ethtool_tunable *tuna, void *data) 929 { 930 struct ionic_lif *lif = netdev_priv(netdev); 931 932 switch (tuna->id) { 933 case ETHTOOL_RX_COPYBREAK: 934 *(u32 *)data = lif->rx_copybreak; 935 break; 936 default: 937 return -EOPNOTSUPP; 938 } 939 940 return 0; 941 } 942 943 static int ionic_do_module_copy(u8 *dst, u8 *src, u32 len) 944 { 945 char tbuf[sizeof_field(struct ionic_xcvr_status, sprom)]; 946 int count = 10; 947 948 /* The NIC keeps the module prom up-to-date in the DMA space 949 * so we can simply copy the module bytes into the data buffer. 950 */ 951 do { 952 memcpy(dst, src, len); 953 memcpy(tbuf, src, len); 954 955 /* Let's make sure we got a consistent copy */ 956 if (!memcmp(dst, tbuf, len)) 957 break; 958 959 } while (--count); 960 961 if (!count) 962 return -ETIMEDOUT; 963 964 return 0; 965 } 966 967 static int ionic_get_module_eeprom_by_page(struct net_device *netdev, 968 const struct ethtool_module_eeprom *page_data, 969 struct netlink_ext_ack *extack) 970 { 971 struct ionic_lif *lif = netdev_priv(netdev); 972 struct ionic_dev *idev = &lif->ionic->idev; 973 int err; 974 u8 *src; 975 976 if (!page_data->length) 977 return -EINVAL; 978 979 if (page_data->bank != 0) { 980 NL_SET_ERR_MSG_MOD(extack, "Only bank 0 is supported"); 981 return -EINVAL; 982 } 983 984 switch (page_data->page) { 985 case 0: 986 src = &idev->port_info->status.xcvr.sprom[page_data->offset]; 987 break; 988 case 1: 989 src = &idev->port_info->sprom_page1[page_data->offset - 128]; 990 break; 991 case 2: 992 src = &idev->port_info->sprom_page2[page_data->offset - 128]; 993 break; 994 case 17: 995 src = &idev->port_info->sprom_page17[page_data->offset - 128]; 996 break; 997 default: 998 return -EOPNOTSUPP; 999 } 1000 1001 memset(page_data->data, 0, page_data->length); 1002 err = ionic_do_module_copy(page_data->data, src, page_data->length); 1003 if (err) 1004 return err; 1005 1006 return page_data->length; 1007 } 1008 1009 static int ionic_get_ts_info(struct net_device *netdev, 1010 struct kernel_ethtool_ts_info *info) 1011 { 1012 struct ionic_lif *lif = netdev_priv(netdev); 1013 struct ionic *ionic = lif->ionic; 1014 __le64 mask; 1015 1016 if (!lif->phc || !lif->phc->ptp) 1017 return ethtool_op_get_ts_info(netdev, info); 1018 1019 info->phc_index = ptp_clock_index(lif->phc->ptp); 1020 1021 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1022 SOF_TIMESTAMPING_TX_HARDWARE | 1023 SOF_TIMESTAMPING_RX_HARDWARE | 1024 SOF_TIMESTAMPING_RAW_HARDWARE; 1025 1026 /* tx modes */ 1027 1028 info->tx_types = BIT(HWTSTAMP_TX_OFF) | 1029 BIT(HWTSTAMP_TX_ON); 1030 1031 mask = cpu_to_le64(BIT_ULL(IONIC_TXSTAMP_ONESTEP_SYNC)); 1032 if (ionic->ident.lif.eth.hwstamp_tx_modes & mask) 1033 info->tx_types |= BIT(HWTSTAMP_TX_ONESTEP_SYNC); 1034 1035 mask = cpu_to_le64(BIT_ULL(IONIC_TXSTAMP_ONESTEP_P2P)); 1036 if (ionic->ident.lif.eth.hwstamp_tx_modes & mask) 1037 info->tx_types |= BIT(HWTSTAMP_TX_ONESTEP_P2P); 1038 1039 /* rx filters */ 1040 1041 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 1042 BIT(HWTSTAMP_FILTER_ALL); 1043 1044 mask = cpu_to_le64(IONIC_PKT_CLS_NTP_ALL); 1045 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1046 info->rx_filters |= BIT(HWTSTAMP_FILTER_NTP_ALL); 1047 1048 mask = cpu_to_le64(IONIC_PKT_CLS_PTP1_SYNC); 1049 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1050 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC); 1051 1052 mask = cpu_to_le64(IONIC_PKT_CLS_PTP1_DREQ); 1053 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1054 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ); 1055 1056 mask = cpu_to_le64(IONIC_PKT_CLS_PTP1_ALL); 1057 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1058 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_EVENT); 1059 1060 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L4_SYNC); 1061 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1062 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC); 1063 1064 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L4_DREQ); 1065 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1066 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ); 1067 1068 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L4_ALL); 1069 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1070 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 1071 1072 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L2_SYNC); 1073 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1074 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC); 1075 1076 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L2_DREQ); 1077 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1078 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ); 1079 1080 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L2_ALL); 1081 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1082 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT); 1083 1084 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_SYNC); 1085 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1086 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_SYNC); 1087 1088 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_DREQ); 1089 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1090 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ); 1091 1092 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_ALL); 1093 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1094 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_EVENT); 1095 1096 return 0; 1097 } 1098 1099 static int ionic_nway_reset(struct net_device *netdev) 1100 { 1101 struct ionic_lif *lif = netdev_priv(netdev); 1102 struct ionic *ionic = lif->ionic; 1103 int err = 0; 1104 1105 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 1106 return -EBUSY; 1107 1108 /* flap the link to force auto-negotiation */ 1109 1110 mutex_lock(&ionic->dev_cmd_lock); 1111 1112 ionic_dev_cmd_port_state(&ionic->idev, IONIC_PORT_ADMIN_STATE_DOWN); 1113 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 1114 1115 if (!err) { 1116 ionic_dev_cmd_port_state(&ionic->idev, IONIC_PORT_ADMIN_STATE_UP); 1117 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 1118 } 1119 1120 mutex_unlock(&ionic->dev_cmd_lock); 1121 1122 return err; 1123 } 1124 1125 static const struct ethtool_ops ionic_ethtool_ops = { 1126 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1127 ETHTOOL_COALESCE_USE_ADAPTIVE_RX | 1128 ETHTOOL_COALESCE_USE_ADAPTIVE_TX, 1129 .supported_ring_params = ETHTOOL_RING_USE_TX_PUSH | 1130 ETHTOOL_RING_USE_RX_PUSH, 1131 .get_drvinfo = ionic_get_drvinfo, 1132 .get_regs_len = ionic_get_regs_len, 1133 .get_regs = ionic_get_regs, 1134 .get_link = ethtool_op_get_link, 1135 .get_link_ext_stats = ionic_get_link_ext_stats, 1136 .get_link_ksettings = ionic_get_link_ksettings, 1137 .set_link_ksettings = ionic_set_link_ksettings, 1138 .get_coalesce = ionic_get_coalesce, 1139 .set_coalesce = ionic_set_coalesce, 1140 .get_ringparam = ionic_get_ringparam, 1141 .set_ringparam = ionic_set_ringparam, 1142 .get_channels = ionic_get_channels, 1143 .set_channels = ionic_set_channels, 1144 .get_strings = ionic_get_strings, 1145 .get_ethtool_stats = ionic_get_stats, 1146 .get_sset_count = ionic_get_sset_count, 1147 .get_rx_ring_count = ionic_get_rx_ring_count, 1148 .get_rxfh_indir_size = ionic_get_rxfh_indir_size, 1149 .get_rxfh_key_size = ionic_get_rxfh_key_size, 1150 .get_rxfh = ionic_get_rxfh, 1151 .set_rxfh = ionic_set_rxfh, 1152 .get_tunable = ionic_get_tunable, 1153 .set_tunable = ionic_set_tunable, 1154 .get_module_eeprom_by_page = ionic_get_module_eeprom_by_page, 1155 .get_pauseparam = ionic_get_pauseparam, 1156 .set_pauseparam = ionic_set_pauseparam, 1157 .get_fecparam = ionic_get_fecparam, 1158 .set_fecparam = ionic_set_fecparam, 1159 .get_ts_info = ionic_get_ts_info, 1160 .nway_reset = ionic_nway_reset, 1161 }; 1162 1163 void ionic_ethtool_set_ops(struct net_device *netdev) 1164 { 1165 netdev->ethtool_ops = &ionic_ethtool_ops; 1166 } 1167