1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/module.h> 5 #include <linux/netdevice.h> 6 #include <linux/sfp.h> 7 8 #include "ionic.h" 9 #include "ionic_bus.h" 10 #include "ionic_lif.h" 11 #include "ionic_ethtool.h" 12 #include "ionic_stats.h" 13 14 static void ionic_get_stats_strings(struct ionic_lif *lif, u8 *buf) 15 { 16 u32 i; 17 18 for (i = 0; i < ionic_num_stats_grps; i++) 19 ionic_stats_groups[i].get_strings(lif, &buf); 20 } 21 22 static void ionic_get_stats(struct net_device *netdev, 23 struct ethtool_stats *stats, u64 *buf) 24 { 25 struct ionic_lif *lif = netdev_priv(netdev); 26 u32 i; 27 28 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 29 return; 30 31 memset(buf, 0, stats->n_stats * sizeof(*buf)); 32 for (i = 0; i < ionic_num_stats_grps; i++) 33 ionic_stats_groups[i].get_values(lif, &buf); 34 } 35 36 static int ionic_get_stats_count(struct ionic_lif *lif) 37 { 38 int i, num_stats = 0; 39 40 for (i = 0; i < ionic_num_stats_grps; i++) 41 num_stats += ionic_stats_groups[i].get_count(lif); 42 43 return num_stats; 44 } 45 46 static int ionic_get_sset_count(struct net_device *netdev, int sset) 47 { 48 struct ionic_lif *lif = netdev_priv(netdev); 49 int count = 0; 50 51 switch (sset) { 52 case ETH_SS_STATS: 53 count = ionic_get_stats_count(lif); 54 break; 55 } 56 return count; 57 } 58 59 static void ionic_get_strings(struct net_device *netdev, 60 u32 sset, u8 *buf) 61 { 62 struct ionic_lif *lif = netdev_priv(netdev); 63 64 switch (sset) { 65 case ETH_SS_STATS: 66 ionic_get_stats_strings(lif, buf); 67 break; 68 } 69 } 70 71 static void ionic_get_drvinfo(struct net_device *netdev, 72 struct ethtool_drvinfo *drvinfo) 73 { 74 struct ionic_lif *lif = netdev_priv(netdev); 75 struct ionic *ionic = lif->ionic; 76 77 strscpy(drvinfo->driver, IONIC_DRV_NAME, sizeof(drvinfo->driver)); 78 strscpy(drvinfo->fw_version, ionic->idev.dev_info.fw_version, 79 sizeof(drvinfo->fw_version)); 80 strscpy(drvinfo->bus_info, ionic_bus_info(ionic), 81 sizeof(drvinfo->bus_info)); 82 } 83 84 static int ionic_get_regs_len(struct net_device *netdev) 85 { 86 return (IONIC_DEV_INFO_REG_COUNT + IONIC_DEV_CMD_REG_COUNT) * sizeof(u32); 87 } 88 89 static void ionic_get_regs(struct net_device *netdev, struct ethtool_regs *regs, 90 void *p) 91 { 92 struct ionic_lif *lif = netdev_priv(netdev); 93 unsigned int offset; 94 unsigned int size; 95 96 regs->version = IONIC_DEV_CMD_REG_VERSION; 97 98 offset = 0; 99 size = IONIC_DEV_INFO_REG_COUNT * sizeof(u32); 100 memcpy_fromio(p + offset, lif->ionic->idev.dev_info_regs->words, size); 101 102 offset += size; 103 size = IONIC_DEV_CMD_REG_COUNT * sizeof(u32); 104 memcpy_fromio(p + offset, lif->ionic->idev.dev_cmd_regs->words, size); 105 } 106 107 static void ionic_get_link_ext_stats(struct net_device *netdev, 108 struct ethtool_link_ext_stats *stats) 109 { 110 struct ionic_lif *lif = netdev_priv(netdev); 111 112 if (lif->ionic->pdev->is_physfn) 113 stats->link_down_events = lif->link_down_count; 114 } 115 116 static int ionic_get_link_ksettings(struct net_device *netdev, 117 struct ethtool_link_ksettings *ks) 118 { 119 struct ionic_lif *lif = netdev_priv(netdev); 120 struct ionic_dev *idev = &lif->ionic->idev; 121 int copper_seen = 0; 122 123 ethtool_link_ksettings_zero_link_mode(ks, supported); 124 125 if (!idev->port_info) { 126 netdev_err(netdev, "port_info not initialized\n"); 127 return -EOPNOTSUPP; 128 } 129 130 /* The port_info data is found in a DMA space that the NIC keeps 131 * up-to-date, so there's no need to request the data from the 132 * NIC, we already have it in our memory space. 133 */ 134 135 switch (le16_to_cpu(idev->port_info->status.xcvr.pid)) { 136 /* Copper */ 137 case IONIC_XCVR_PID_QSFP_100G_CR4: 138 ethtool_link_ksettings_add_link_mode(ks, supported, 139 100000baseCR4_Full); 140 copper_seen++; 141 break; 142 case IONIC_XCVR_PID_QSFP_40GBASE_CR4: 143 ethtool_link_ksettings_add_link_mode(ks, supported, 144 40000baseCR4_Full); 145 copper_seen++; 146 break; 147 case IONIC_XCVR_PID_SFP_25GBASE_CR_S: 148 case IONIC_XCVR_PID_SFP_25GBASE_CR_L: 149 case IONIC_XCVR_PID_SFP_25GBASE_CR_N: 150 ethtool_link_ksettings_add_link_mode(ks, supported, 151 25000baseCR_Full); 152 copper_seen++; 153 break; 154 case IONIC_XCVR_PID_SFP_10GBASE_AOC: 155 case IONIC_XCVR_PID_SFP_10GBASE_CU: 156 ethtool_link_ksettings_add_link_mode(ks, supported, 157 10000baseCR_Full); 158 copper_seen++; 159 break; 160 161 /* Fibre */ 162 case IONIC_XCVR_PID_QSFP_100G_SR4: 163 case IONIC_XCVR_PID_QSFP_100G_AOC: 164 ethtool_link_ksettings_add_link_mode(ks, supported, 165 100000baseSR4_Full); 166 break; 167 case IONIC_XCVR_PID_QSFP_100G_CWDM4: 168 case IONIC_XCVR_PID_QSFP_100G_PSM4: 169 case IONIC_XCVR_PID_QSFP_100G_LR4: 170 ethtool_link_ksettings_add_link_mode(ks, supported, 171 100000baseLR4_ER4_Full); 172 break; 173 case IONIC_XCVR_PID_QSFP_100G_ER4: 174 ethtool_link_ksettings_add_link_mode(ks, supported, 175 100000baseLR4_ER4_Full); 176 break; 177 case IONIC_XCVR_PID_QSFP_40GBASE_SR4: 178 case IONIC_XCVR_PID_QSFP_40GBASE_AOC: 179 ethtool_link_ksettings_add_link_mode(ks, supported, 180 40000baseSR4_Full); 181 break; 182 case IONIC_XCVR_PID_QSFP_40GBASE_LR4: 183 ethtool_link_ksettings_add_link_mode(ks, supported, 184 40000baseLR4_Full); 185 break; 186 case IONIC_XCVR_PID_SFP_25GBASE_SR: 187 case IONIC_XCVR_PID_SFP_25GBASE_AOC: 188 case IONIC_XCVR_PID_SFP_25GBASE_ACC: 189 ethtool_link_ksettings_add_link_mode(ks, supported, 190 25000baseSR_Full); 191 break; 192 case IONIC_XCVR_PID_SFP_10GBASE_SR: 193 ethtool_link_ksettings_add_link_mode(ks, supported, 194 10000baseSR_Full); 195 break; 196 case IONIC_XCVR_PID_SFP_10GBASE_LR: 197 ethtool_link_ksettings_add_link_mode(ks, supported, 198 10000baseLR_Full); 199 break; 200 case IONIC_XCVR_PID_SFP_10GBASE_LRM: 201 ethtool_link_ksettings_add_link_mode(ks, supported, 202 10000baseLRM_Full); 203 break; 204 case IONIC_XCVR_PID_SFP_10GBASE_ER: 205 ethtool_link_ksettings_add_link_mode(ks, supported, 206 10000baseER_Full); 207 break; 208 case IONIC_XCVR_PID_SFP_10GBASE_T: 209 ethtool_link_ksettings_add_link_mode(ks, supported, 210 10000baseT_Full); 211 break; 212 case IONIC_XCVR_PID_SFP_1000BASE_T: 213 ethtool_link_ksettings_add_link_mode(ks, supported, 214 1000baseT_Full); 215 break; 216 case IONIC_XCVR_PID_UNKNOWN: 217 /* This means there's no module plugged in */ 218 break; 219 default: 220 dev_info(lif->ionic->dev, "unknown xcvr type pid=%d / 0x%x\n", 221 idev->port_info->status.xcvr.pid, 222 idev->port_info->status.xcvr.pid); 223 break; 224 } 225 226 linkmode_copy(ks->link_modes.advertising, ks->link_modes.supported); 227 228 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_BASER); 229 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_RS); 230 if (idev->port_info->config.fec_type == IONIC_PORT_FEC_TYPE_FC) 231 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_BASER); 232 else if (idev->port_info->config.fec_type == IONIC_PORT_FEC_TYPE_RS) 233 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_RS); 234 235 ethtool_link_ksettings_add_link_mode(ks, supported, FIBRE); 236 ethtool_link_ksettings_add_link_mode(ks, supported, Pause); 237 238 if (idev->port_info->status.xcvr.phy == IONIC_PHY_TYPE_COPPER || 239 copper_seen) 240 ks->base.port = PORT_DA; 241 else if (idev->port_info->status.xcvr.phy == IONIC_PHY_TYPE_FIBER) 242 ks->base.port = PORT_FIBRE; 243 else 244 ks->base.port = PORT_NONE; 245 246 if (ks->base.port != PORT_NONE) { 247 ks->base.speed = le32_to_cpu(lif->info->status.link_speed); 248 249 if (le16_to_cpu(lif->info->status.link_status)) 250 ks->base.duplex = DUPLEX_FULL; 251 else 252 ks->base.duplex = DUPLEX_UNKNOWN; 253 254 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg); 255 256 if (idev->port_info->config.an_enable) { 257 ethtool_link_ksettings_add_link_mode(ks, advertising, 258 Autoneg); 259 ks->base.autoneg = AUTONEG_ENABLE; 260 } 261 } 262 263 return 0; 264 } 265 266 static int ionic_set_link_ksettings(struct net_device *netdev, 267 const struct ethtool_link_ksettings *ks) 268 { 269 struct ionic_lif *lif = netdev_priv(netdev); 270 struct ionic_dev *idev = &lif->ionic->idev; 271 struct ionic *ionic = lif->ionic; 272 int err = 0; 273 274 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 275 return -EBUSY; 276 277 /* set autoneg */ 278 if (ks->base.autoneg != idev->port_info->config.an_enable) { 279 mutex_lock(&ionic->dev_cmd_lock); 280 ionic_dev_cmd_port_autoneg(idev, ks->base.autoneg); 281 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 282 mutex_unlock(&ionic->dev_cmd_lock); 283 if (err) 284 return err; 285 } 286 287 /* set speed */ 288 if (ks->base.speed != le32_to_cpu(idev->port_info->config.speed)) { 289 mutex_lock(&ionic->dev_cmd_lock); 290 ionic_dev_cmd_port_speed(idev, ks->base.speed); 291 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 292 mutex_unlock(&ionic->dev_cmd_lock); 293 if (err) 294 return err; 295 } 296 297 return 0; 298 } 299 300 static void ionic_get_pauseparam(struct net_device *netdev, 301 struct ethtool_pauseparam *pause) 302 { 303 struct ionic_lif *lif = netdev_priv(netdev); 304 u8 pause_type; 305 306 pause->autoneg = 0; 307 308 pause_type = lif->ionic->idev.port_info->config.pause_type; 309 if (pause_type) { 310 pause->rx_pause = (pause_type & IONIC_PAUSE_F_RX) ? 1 : 0; 311 pause->tx_pause = (pause_type & IONIC_PAUSE_F_TX) ? 1 : 0; 312 } 313 } 314 315 static int ionic_set_pauseparam(struct net_device *netdev, 316 struct ethtool_pauseparam *pause) 317 { 318 struct ionic_lif *lif = netdev_priv(netdev); 319 struct ionic *ionic = lif->ionic; 320 u32 requested_pause; 321 int err; 322 323 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 324 return -EBUSY; 325 326 if (pause->autoneg) 327 return -EOPNOTSUPP; 328 329 /* change both at the same time */ 330 requested_pause = IONIC_PORT_PAUSE_TYPE_LINK; 331 if (pause->rx_pause) 332 requested_pause |= IONIC_PAUSE_F_RX; 333 if (pause->tx_pause) 334 requested_pause |= IONIC_PAUSE_F_TX; 335 336 if (requested_pause == lif->ionic->idev.port_info->config.pause_type) 337 return 0; 338 339 mutex_lock(&ionic->dev_cmd_lock); 340 ionic_dev_cmd_port_pause(&lif->ionic->idev, requested_pause); 341 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 342 mutex_unlock(&ionic->dev_cmd_lock); 343 if (err) 344 return err; 345 346 return 0; 347 } 348 349 static int ionic_get_fecparam(struct net_device *netdev, 350 struct ethtool_fecparam *fec) 351 { 352 struct ionic_lif *lif = netdev_priv(netdev); 353 354 switch (lif->ionic->idev.port_info->config.fec_type) { 355 case IONIC_PORT_FEC_TYPE_NONE: 356 fec->active_fec = ETHTOOL_FEC_OFF; 357 break; 358 case IONIC_PORT_FEC_TYPE_RS: 359 fec->active_fec = ETHTOOL_FEC_RS; 360 break; 361 case IONIC_PORT_FEC_TYPE_FC: 362 fec->active_fec = ETHTOOL_FEC_BASER; 363 break; 364 } 365 366 fec->fec = ETHTOOL_FEC_OFF | ETHTOOL_FEC_RS | ETHTOOL_FEC_BASER; 367 368 return 0; 369 } 370 371 static int ionic_set_fecparam(struct net_device *netdev, 372 struct ethtool_fecparam *fec) 373 { 374 struct ionic_lif *lif = netdev_priv(netdev); 375 u8 fec_type; 376 int ret = 0; 377 378 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 379 return -EBUSY; 380 381 if (lif->ionic->idev.port_info->config.an_enable) { 382 netdev_err(netdev, "FEC request not allowed while autoneg is enabled\n"); 383 return -EINVAL; 384 } 385 386 switch (fec->fec) { 387 case ETHTOOL_FEC_NONE: 388 fec_type = IONIC_PORT_FEC_TYPE_NONE; 389 break; 390 case ETHTOOL_FEC_OFF: 391 fec_type = IONIC_PORT_FEC_TYPE_NONE; 392 break; 393 case ETHTOOL_FEC_RS: 394 fec_type = IONIC_PORT_FEC_TYPE_RS; 395 break; 396 case ETHTOOL_FEC_BASER: 397 fec_type = IONIC_PORT_FEC_TYPE_FC; 398 break; 399 case ETHTOOL_FEC_AUTO: 400 default: 401 netdev_err(netdev, "FEC request 0x%04x not supported\n", 402 fec->fec); 403 return -EINVAL; 404 } 405 406 if (fec_type != lif->ionic->idev.port_info->config.fec_type) { 407 mutex_lock(&lif->ionic->dev_cmd_lock); 408 ionic_dev_cmd_port_fec(&lif->ionic->idev, fec_type); 409 ret = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 410 mutex_unlock(&lif->ionic->dev_cmd_lock); 411 } 412 413 return ret; 414 } 415 416 static int ionic_get_coalesce(struct net_device *netdev, 417 struct ethtool_coalesce *coalesce, 418 struct kernel_ethtool_coalesce *kernel_coal, 419 struct netlink_ext_ack *extack) 420 { 421 struct ionic_lif *lif = netdev_priv(netdev); 422 423 coalesce->tx_coalesce_usecs = lif->tx_coalesce_usecs; 424 coalesce->rx_coalesce_usecs = lif->rx_coalesce_usecs; 425 426 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 427 coalesce->use_adaptive_tx_coalesce = test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 428 else 429 coalesce->use_adaptive_tx_coalesce = 0; 430 431 coalesce->use_adaptive_rx_coalesce = test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 432 433 return 0; 434 } 435 436 static int ionic_set_coalesce(struct net_device *netdev, 437 struct ethtool_coalesce *coalesce, 438 struct kernel_ethtool_coalesce *kernel_coal, 439 struct netlink_ext_ack *extack) 440 { 441 struct ionic_lif *lif = netdev_priv(netdev); 442 struct ionic_identity *ident; 443 u32 rx_coal, rx_dim; 444 u32 tx_coal, tx_dim; 445 unsigned int i; 446 447 ident = &lif->ionic->ident; 448 if (ident->dev.intr_coal_div == 0) { 449 netdev_warn(netdev, "bad HW value in dev.intr_coal_div = %d\n", 450 ident->dev.intr_coal_div); 451 return -EIO; 452 } 453 454 /* Tx normally shares Rx interrupt, so only change Rx if not split */ 455 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) && 456 (coalesce->tx_coalesce_usecs != lif->rx_coalesce_usecs || 457 coalesce->use_adaptive_tx_coalesce)) { 458 netdev_warn(netdev, "only rx parameters can be changed\n"); 459 return -EINVAL; 460 } 461 462 /* Convert the usec request to a HW usable value. If they asked 463 * for non-zero and it resolved to zero, bump it up 464 */ 465 rx_coal = ionic_coal_usec_to_hw(lif->ionic, coalesce->rx_coalesce_usecs); 466 if (!rx_coal && coalesce->rx_coalesce_usecs) 467 rx_coal = 1; 468 tx_coal = ionic_coal_usec_to_hw(lif->ionic, coalesce->tx_coalesce_usecs); 469 if (!tx_coal && coalesce->tx_coalesce_usecs) 470 tx_coal = 1; 471 472 if (rx_coal > IONIC_INTR_CTRL_COAL_MAX || 473 tx_coal > IONIC_INTR_CTRL_COAL_MAX) 474 return -ERANGE; 475 476 /* Save the new values */ 477 lif->rx_coalesce_usecs = coalesce->rx_coalesce_usecs; 478 lif->rx_coalesce_hw = rx_coal; 479 480 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 481 lif->tx_coalesce_usecs = coalesce->tx_coalesce_usecs; 482 else 483 lif->tx_coalesce_usecs = coalesce->rx_coalesce_usecs; 484 lif->tx_coalesce_hw = tx_coal; 485 486 if (coalesce->use_adaptive_rx_coalesce) { 487 set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 488 rx_dim = rx_coal; 489 } else { 490 clear_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 491 rx_dim = 0; 492 } 493 494 if (coalesce->use_adaptive_tx_coalesce) { 495 set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 496 tx_dim = tx_coal; 497 } else { 498 clear_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 499 tx_dim = 0; 500 } 501 502 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 503 for (i = 0; i < lif->nxqs; i++) { 504 if (lif->rxqcqs[i]->flags & IONIC_QCQ_F_INTR) { 505 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 506 lif->rxqcqs[i]->intr.index, 507 lif->rx_coalesce_hw); 508 lif->rxqcqs[i]->intr.dim_coal_hw = rx_dim; 509 } 510 511 if (lif->txqcqs[i]->flags & IONIC_QCQ_F_INTR) { 512 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 513 lif->txqcqs[i]->intr.index, 514 lif->tx_coalesce_hw); 515 lif->txqcqs[i]->intr.dim_coal_hw = tx_dim; 516 } 517 } 518 } 519 520 return 0; 521 } 522 523 static int ionic_validate_cmb_config(struct ionic_lif *lif, 524 struct ionic_queue_params *qparam) 525 { 526 int pages_have, pages_required = 0; 527 unsigned long sz; 528 529 if (!lif->ionic->idev.cmb_inuse && 530 (qparam->cmb_tx || qparam->cmb_rx)) { 531 netdev_info(lif->netdev, "CMB rings are not supported on this device\n"); 532 return -EOPNOTSUPP; 533 } 534 535 if (qparam->cmb_tx) { 536 if (!(lif->qtype_info[IONIC_QTYPE_TXQ].features & IONIC_QIDENT_F_CMB)) { 537 netdev_info(lif->netdev, 538 "CMB rings for tx-push are not supported on this device\n"); 539 return -EOPNOTSUPP; 540 } 541 542 sz = sizeof(struct ionic_txq_desc) * qparam->ntxq_descs * qparam->nxqs; 543 pages_required += ALIGN(sz, PAGE_SIZE) / PAGE_SIZE; 544 } 545 546 if (qparam->cmb_rx) { 547 if (!(lif->qtype_info[IONIC_QTYPE_RXQ].features & IONIC_QIDENT_F_CMB)) { 548 netdev_info(lif->netdev, 549 "CMB rings for rx-push are not supported on this device\n"); 550 return -EOPNOTSUPP; 551 } 552 553 sz = sizeof(struct ionic_rxq_desc) * qparam->nrxq_descs * qparam->nxqs; 554 pages_required += ALIGN(sz, PAGE_SIZE) / PAGE_SIZE; 555 } 556 557 pages_have = lif->ionic->bars[IONIC_PCI_BAR_CMB].len / PAGE_SIZE; 558 if (pages_required > pages_have) { 559 netdev_info(lif->netdev, 560 "Not enough CMB pages for number of queues and size of descriptor rings, need %d have %d", 561 pages_required, pages_have); 562 return -ENOMEM; 563 } 564 565 return pages_required; 566 } 567 568 static int ionic_cmb_rings_toggle(struct ionic_lif *lif, bool cmb_tx, bool cmb_rx) 569 { 570 struct ionic_queue_params qparam; 571 int pages_used; 572 573 if (netif_running(lif->netdev)) { 574 netdev_info(lif->netdev, "Please stop device to toggle CMB for tx/rx-push\n"); 575 return -EBUSY; 576 } 577 578 ionic_init_queue_params(lif, &qparam); 579 qparam.cmb_tx = cmb_tx; 580 qparam.cmb_rx = cmb_rx; 581 pages_used = ionic_validate_cmb_config(lif, &qparam); 582 if (pages_used < 0) 583 return pages_used; 584 585 if (cmb_tx) 586 set_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state); 587 else 588 clear_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state); 589 590 if (cmb_rx) 591 set_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state); 592 else 593 clear_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state); 594 595 if (cmb_tx || cmb_rx) 596 netdev_info(lif->netdev, "Enabling CMB %s %s rings - %d pages\n", 597 cmb_tx ? "TX" : "", cmb_rx ? "RX" : "", pages_used); 598 else 599 netdev_info(lif->netdev, "Disabling CMB rings\n"); 600 601 return 0; 602 } 603 604 static void ionic_get_ringparam(struct net_device *netdev, 605 struct ethtool_ringparam *ring, 606 struct kernel_ethtool_ringparam *kernel_ring, 607 struct netlink_ext_ack *extack) 608 { 609 struct ionic_lif *lif = netdev_priv(netdev); 610 611 ring->tx_max_pending = IONIC_MAX_TX_DESC; 612 ring->tx_pending = lif->ntxq_descs; 613 ring->rx_max_pending = IONIC_MAX_RX_DESC; 614 ring->rx_pending = lif->nrxq_descs; 615 kernel_ring->tx_push = test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state); 616 kernel_ring->rx_push = test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state); 617 } 618 619 static int ionic_set_ringparam(struct net_device *netdev, 620 struct ethtool_ringparam *ring, 621 struct kernel_ethtool_ringparam *kernel_ring, 622 struct netlink_ext_ack *extack) 623 { 624 struct ionic_lif *lif = netdev_priv(netdev); 625 struct ionic_queue_params qparam; 626 int err; 627 628 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 629 return -EBUSY; 630 631 ionic_init_queue_params(lif, &qparam); 632 633 if (ring->rx_mini_pending || ring->rx_jumbo_pending) { 634 netdev_info(netdev, "Changing jumbo or mini descriptors not supported\n"); 635 return -EINVAL; 636 } 637 638 if (!is_power_of_2(ring->tx_pending) || 639 !is_power_of_2(ring->rx_pending)) { 640 netdev_info(netdev, "Descriptor count must be a power of 2\n"); 641 return -EINVAL; 642 } 643 644 /* if nothing to do return success */ 645 if (ring->tx_pending == lif->ntxq_descs && 646 ring->rx_pending == lif->nrxq_descs && 647 kernel_ring->tx_push == test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state) && 648 kernel_ring->rx_push == test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state)) 649 return 0; 650 651 qparam.ntxq_descs = ring->tx_pending; 652 qparam.nrxq_descs = ring->rx_pending; 653 qparam.cmb_tx = kernel_ring->tx_push; 654 qparam.cmb_rx = kernel_ring->rx_push; 655 656 err = ionic_validate_cmb_config(lif, &qparam); 657 if (err < 0) 658 return err; 659 660 if (kernel_ring->tx_push != test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state) || 661 kernel_ring->rx_push != test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state)) { 662 err = ionic_cmb_rings_toggle(lif, kernel_ring->tx_push, 663 kernel_ring->rx_push); 664 if (err < 0) 665 return err; 666 } 667 668 if (ring->tx_pending != lif->ntxq_descs) 669 netdev_info(netdev, "Changing Tx ring size from %d to %d\n", 670 lif->ntxq_descs, ring->tx_pending); 671 672 if (ring->rx_pending != lif->nrxq_descs) 673 netdev_info(netdev, "Changing Rx ring size from %d to %d\n", 674 lif->nrxq_descs, ring->rx_pending); 675 676 /* if we're not running, just set the values and return */ 677 if (!netif_running(lif->netdev)) { 678 lif->ntxq_descs = ring->tx_pending; 679 lif->nrxq_descs = ring->rx_pending; 680 return 0; 681 } 682 683 mutex_lock(&lif->queue_lock); 684 err = ionic_reconfigure_queues(lif, &qparam); 685 mutex_unlock(&lif->queue_lock); 686 if (err) 687 netdev_info(netdev, "Ring reconfiguration failed, changes canceled: %d\n", err); 688 689 return err; 690 } 691 692 static void ionic_get_channels(struct net_device *netdev, 693 struct ethtool_channels *ch) 694 { 695 struct ionic_lif *lif = netdev_priv(netdev); 696 697 /* report maximum channels */ 698 ch->max_combined = lif->ionic->ntxqs_per_lif; 699 ch->max_rx = lif->ionic->ntxqs_per_lif / 2; 700 ch->max_tx = lif->ionic->ntxqs_per_lif / 2; 701 702 /* report current channels */ 703 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) { 704 ch->rx_count = lif->nxqs; 705 ch->tx_count = lif->nxqs; 706 } else { 707 ch->combined_count = lif->nxqs; 708 } 709 } 710 711 static int ionic_set_channels(struct net_device *netdev, 712 struct ethtool_channels *ch) 713 { 714 struct ionic_lif *lif = netdev_priv(netdev); 715 struct ionic_queue_params qparam; 716 int max_cnt; 717 int err; 718 719 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 720 return -EBUSY; 721 722 ionic_init_queue_params(lif, &qparam); 723 724 if ((ch->rx_count || ch->tx_count) && lif->xdp_prog) { 725 netdev_info(lif->netdev, "Split Tx/Rx interrupts not available when using XDP\n"); 726 return -EOPNOTSUPP; 727 } 728 729 if (ch->rx_count != ch->tx_count) { 730 netdev_info(netdev, "The rx and tx count must be equal\n"); 731 return -EINVAL; 732 } 733 734 if (ch->combined_count && ch->rx_count) { 735 netdev_info(netdev, "Use either combined or rx and tx, not both\n"); 736 return -EINVAL; 737 } 738 739 max_cnt = lif->ionic->ntxqs_per_lif; 740 if (ch->combined_count) { 741 if (ch->combined_count > max_cnt) 742 return -EINVAL; 743 744 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 745 netdev_info(lif->netdev, "Sharing queue interrupts\n"); 746 else if (ch->combined_count == lif->nxqs) 747 return 0; 748 749 if (lif->nxqs != ch->combined_count) 750 netdev_info(netdev, "Changing queue count from %d to %d\n", 751 lif->nxqs, ch->combined_count); 752 753 qparam.nxqs = ch->combined_count; 754 qparam.intr_split = false; 755 } else { 756 max_cnt /= 2; 757 if (ch->rx_count > max_cnt) 758 return -EINVAL; 759 760 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 761 netdev_info(lif->netdev, "Splitting queue interrupts\n"); 762 else if (ch->rx_count == lif->nxqs) 763 return 0; 764 765 if (lif->nxqs != ch->rx_count) 766 netdev_info(netdev, "Changing queue count from %d to %d\n", 767 lif->nxqs, ch->rx_count); 768 769 qparam.nxqs = ch->rx_count; 770 qparam.intr_split = true; 771 } 772 773 err = ionic_validate_cmb_config(lif, &qparam); 774 if (err < 0) 775 return err; 776 777 /* if we're not running, just set the values and return */ 778 if (!netif_running(lif->netdev)) { 779 lif->nxqs = qparam.nxqs; 780 781 if (qparam.intr_split) { 782 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 783 } else { 784 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 785 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 786 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 787 } 788 return 0; 789 } 790 791 mutex_lock(&lif->queue_lock); 792 err = ionic_reconfigure_queues(lif, &qparam); 793 mutex_unlock(&lif->queue_lock); 794 if (err) 795 netdev_info(netdev, "Queue reconfiguration failed, changes canceled: %d\n", err); 796 797 return err; 798 } 799 800 static int ionic_get_rxnfc(struct net_device *netdev, 801 struct ethtool_rxnfc *info, u32 *rules) 802 { 803 struct ionic_lif *lif = netdev_priv(netdev); 804 int err = 0; 805 806 switch (info->cmd) { 807 case ETHTOOL_GRXRINGS: 808 info->data = lif->nxqs; 809 break; 810 default: 811 netdev_dbg(netdev, "Command parameter %d is not supported\n", 812 info->cmd); 813 err = -EOPNOTSUPP; 814 } 815 816 return err; 817 } 818 819 static u32 ionic_get_rxfh_indir_size(struct net_device *netdev) 820 { 821 struct ionic_lif *lif = netdev_priv(netdev); 822 823 return le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 824 } 825 826 static u32 ionic_get_rxfh_key_size(struct net_device *netdev) 827 { 828 return IONIC_RSS_HASH_KEY_SIZE; 829 } 830 831 static int ionic_get_rxfh(struct net_device *netdev, 832 struct ethtool_rxfh_param *rxfh) 833 { 834 struct ionic_lif *lif = netdev_priv(netdev); 835 unsigned int i, tbl_sz; 836 837 if (rxfh->indir) { 838 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 839 for (i = 0; i < tbl_sz; i++) 840 rxfh->indir[i] = lif->rss_ind_tbl[i]; 841 } 842 843 if (rxfh->key) 844 memcpy(rxfh->key, lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE); 845 846 rxfh->hfunc = ETH_RSS_HASH_TOP; 847 848 return 0; 849 } 850 851 static int ionic_set_rxfh(struct net_device *netdev, 852 struct ethtool_rxfh_param *rxfh, 853 struct netlink_ext_ack *extack) 854 { 855 struct ionic_lif *lif = netdev_priv(netdev); 856 857 if (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE && 858 rxfh->hfunc != ETH_RSS_HASH_TOP) 859 return -EOPNOTSUPP; 860 861 return ionic_lif_rss_config(lif, lif->rss_types, 862 rxfh->key, rxfh->indir); 863 } 864 865 static int ionic_set_tunable(struct net_device *dev, 866 const struct ethtool_tunable *tuna, 867 const void *data) 868 { 869 struct ionic_lif *lif = netdev_priv(dev); 870 871 switch (tuna->id) { 872 case ETHTOOL_RX_COPYBREAK: 873 lif->rx_copybreak = *(u32 *)data; 874 break; 875 default: 876 return -EOPNOTSUPP; 877 } 878 879 return 0; 880 } 881 882 static int ionic_get_tunable(struct net_device *netdev, 883 const struct ethtool_tunable *tuna, void *data) 884 { 885 struct ionic_lif *lif = netdev_priv(netdev); 886 887 switch (tuna->id) { 888 case ETHTOOL_RX_COPYBREAK: 889 *(u32 *)data = lif->rx_copybreak; 890 break; 891 default: 892 return -EOPNOTSUPP; 893 } 894 895 return 0; 896 } 897 898 static int ionic_get_module_info(struct net_device *netdev, 899 struct ethtool_modinfo *modinfo) 900 901 { 902 struct ionic_lif *lif = netdev_priv(netdev); 903 struct ionic_dev *idev = &lif->ionic->idev; 904 struct ionic_xcvr_status *xcvr; 905 struct sfp_eeprom_base *sfp; 906 907 xcvr = &idev->port_info->status.xcvr; 908 sfp = (struct sfp_eeprom_base *) xcvr->sprom; 909 910 /* report the module data type and length */ 911 switch (sfp->phys_id) { 912 case SFF8024_ID_SFP: 913 modinfo->type = ETH_MODULE_SFF_8079; 914 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 915 break; 916 case SFF8024_ID_QSFP_8436_8636: 917 case SFF8024_ID_QSFP28_8636: 918 modinfo->type = ETH_MODULE_SFF_8436; 919 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 920 break; 921 default: 922 netdev_info(netdev, "unknown xcvr type 0x%02x\n", 923 xcvr->sprom[0]); 924 modinfo->type = 0; 925 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 926 break; 927 } 928 929 return 0; 930 } 931 932 static int ionic_get_module_eeprom(struct net_device *netdev, 933 struct ethtool_eeprom *ee, 934 u8 *data) 935 { 936 struct ionic_lif *lif = netdev_priv(netdev); 937 struct ionic_dev *idev = &lif->ionic->idev; 938 struct ionic_xcvr_status *xcvr; 939 char tbuf[sizeof(xcvr->sprom)]; 940 int count = 10; 941 u32 len; 942 943 /* The NIC keeps the module prom up-to-date in the DMA space 944 * so we can simply copy the module bytes into the data buffer. 945 */ 946 xcvr = &idev->port_info->status.xcvr; 947 len = min_t(u32, sizeof(xcvr->sprom), ee->len); 948 949 do { 950 memcpy(data, xcvr->sprom, len); 951 memcpy(tbuf, xcvr->sprom, len); 952 953 /* Let's make sure we got a consistent copy */ 954 if (!memcmp(data, tbuf, len)) 955 break; 956 957 } while (--count); 958 959 if (!count) 960 return -ETIMEDOUT; 961 962 return 0; 963 } 964 965 static int ionic_get_ts_info(struct net_device *netdev, 966 struct ethtool_ts_info *info) 967 { 968 struct ionic_lif *lif = netdev_priv(netdev); 969 struct ionic *ionic = lif->ionic; 970 __le64 mask; 971 972 if (!lif->phc || !lif->phc->ptp) 973 return ethtool_op_get_ts_info(netdev, info); 974 975 info->phc_index = ptp_clock_index(lif->phc->ptp); 976 977 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 978 SOF_TIMESTAMPING_RX_SOFTWARE | 979 SOF_TIMESTAMPING_SOFTWARE | 980 SOF_TIMESTAMPING_TX_HARDWARE | 981 SOF_TIMESTAMPING_RX_HARDWARE | 982 SOF_TIMESTAMPING_RAW_HARDWARE; 983 984 /* tx modes */ 985 986 info->tx_types = BIT(HWTSTAMP_TX_OFF) | 987 BIT(HWTSTAMP_TX_ON); 988 989 mask = cpu_to_le64(BIT_ULL(IONIC_TXSTAMP_ONESTEP_SYNC)); 990 if (ionic->ident.lif.eth.hwstamp_tx_modes & mask) 991 info->tx_types |= BIT(HWTSTAMP_TX_ONESTEP_SYNC); 992 993 mask = cpu_to_le64(BIT_ULL(IONIC_TXSTAMP_ONESTEP_P2P)); 994 if (ionic->ident.lif.eth.hwstamp_tx_modes & mask) 995 info->tx_types |= BIT(HWTSTAMP_TX_ONESTEP_P2P); 996 997 /* rx filters */ 998 999 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 1000 BIT(HWTSTAMP_FILTER_ALL); 1001 1002 mask = cpu_to_le64(IONIC_PKT_CLS_NTP_ALL); 1003 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1004 info->rx_filters |= BIT(HWTSTAMP_FILTER_NTP_ALL); 1005 1006 mask = cpu_to_le64(IONIC_PKT_CLS_PTP1_SYNC); 1007 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1008 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC); 1009 1010 mask = cpu_to_le64(IONIC_PKT_CLS_PTP1_DREQ); 1011 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1012 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ); 1013 1014 mask = cpu_to_le64(IONIC_PKT_CLS_PTP1_ALL); 1015 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1016 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_EVENT); 1017 1018 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L4_SYNC); 1019 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1020 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC); 1021 1022 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L4_DREQ); 1023 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1024 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ); 1025 1026 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L4_ALL); 1027 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1028 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 1029 1030 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L2_SYNC); 1031 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1032 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC); 1033 1034 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L2_DREQ); 1035 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1036 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ); 1037 1038 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L2_ALL); 1039 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1040 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT); 1041 1042 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_SYNC); 1043 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1044 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_SYNC); 1045 1046 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_DREQ); 1047 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1048 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ); 1049 1050 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_ALL); 1051 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1052 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_EVENT); 1053 1054 return 0; 1055 } 1056 1057 static int ionic_nway_reset(struct net_device *netdev) 1058 { 1059 struct ionic_lif *lif = netdev_priv(netdev); 1060 struct ionic *ionic = lif->ionic; 1061 int err = 0; 1062 1063 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 1064 return -EBUSY; 1065 1066 /* flap the link to force auto-negotiation */ 1067 1068 mutex_lock(&ionic->dev_cmd_lock); 1069 1070 ionic_dev_cmd_port_state(&ionic->idev, IONIC_PORT_ADMIN_STATE_DOWN); 1071 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 1072 1073 if (!err) { 1074 ionic_dev_cmd_port_state(&ionic->idev, IONIC_PORT_ADMIN_STATE_UP); 1075 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 1076 } 1077 1078 mutex_unlock(&ionic->dev_cmd_lock); 1079 1080 return err; 1081 } 1082 1083 static const struct ethtool_ops ionic_ethtool_ops = { 1084 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1085 ETHTOOL_COALESCE_USE_ADAPTIVE_RX | 1086 ETHTOOL_COALESCE_USE_ADAPTIVE_TX, 1087 .supported_ring_params = ETHTOOL_RING_USE_TX_PUSH | 1088 ETHTOOL_RING_USE_RX_PUSH, 1089 .get_drvinfo = ionic_get_drvinfo, 1090 .get_regs_len = ionic_get_regs_len, 1091 .get_regs = ionic_get_regs, 1092 .get_link = ethtool_op_get_link, 1093 .get_link_ext_stats = ionic_get_link_ext_stats, 1094 .get_link_ksettings = ionic_get_link_ksettings, 1095 .set_link_ksettings = ionic_set_link_ksettings, 1096 .get_coalesce = ionic_get_coalesce, 1097 .set_coalesce = ionic_set_coalesce, 1098 .get_ringparam = ionic_get_ringparam, 1099 .set_ringparam = ionic_set_ringparam, 1100 .get_channels = ionic_get_channels, 1101 .set_channels = ionic_set_channels, 1102 .get_strings = ionic_get_strings, 1103 .get_ethtool_stats = ionic_get_stats, 1104 .get_sset_count = ionic_get_sset_count, 1105 .get_rxnfc = ionic_get_rxnfc, 1106 .get_rxfh_indir_size = ionic_get_rxfh_indir_size, 1107 .get_rxfh_key_size = ionic_get_rxfh_key_size, 1108 .get_rxfh = ionic_get_rxfh, 1109 .set_rxfh = ionic_set_rxfh, 1110 .get_tunable = ionic_get_tunable, 1111 .set_tunable = ionic_set_tunable, 1112 .get_module_info = ionic_get_module_info, 1113 .get_module_eeprom = ionic_get_module_eeprom, 1114 .get_pauseparam = ionic_get_pauseparam, 1115 .set_pauseparam = ionic_set_pauseparam, 1116 .get_fecparam = ionic_get_fecparam, 1117 .set_fecparam = ionic_set_fecparam, 1118 .get_ts_info = ionic_get_ts_info, 1119 .nway_reset = ionic_nway_reset, 1120 }; 1121 1122 void ionic_ethtool_set_ops(struct net_device *netdev) 1123 { 1124 netdev->ethtool_ops = &ionic_ethtool_ops; 1125 } 1126