1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/module.h> 5 #include <linux/netdevice.h> 6 #include <linux/sfp.h> 7 8 #include "ionic.h" 9 #include "ionic_bus.h" 10 #include "ionic_lif.h" 11 #include "ionic_ethtool.h" 12 #include "ionic_stats.h" 13 14 #define IONIC_MAX_RX_COPYBREAK min(U16_MAX, IONIC_MAX_BUF_LEN) 15 16 static void ionic_get_stats_strings(struct ionic_lif *lif, u8 *buf) 17 { 18 u32 i; 19 20 for (i = 0; i < ionic_num_stats_grps; i++) 21 ionic_stats_groups[i].get_strings(lif, &buf); 22 } 23 24 static void ionic_get_stats(struct net_device *netdev, 25 struct ethtool_stats *stats, u64 *buf) 26 { 27 struct ionic_lif *lif = netdev_priv(netdev); 28 u32 i; 29 30 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 31 return; 32 33 memset(buf, 0, stats->n_stats * sizeof(*buf)); 34 for (i = 0; i < ionic_num_stats_grps; i++) 35 ionic_stats_groups[i].get_values(lif, &buf); 36 } 37 38 static int ionic_get_stats_count(struct ionic_lif *lif) 39 { 40 int i, num_stats = 0; 41 42 for (i = 0; i < ionic_num_stats_grps; i++) 43 num_stats += ionic_stats_groups[i].get_count(lif); 44 45 return num_stats; 46 } 47 48 static int ionic_get_sset_count(struct net_device *netdev, int sset) 49 { 50 struct ionic_lif *lif = netdev_priv(netdev); 51 int count = 0; 52 53 switch (sset) { 54 case ETH_SS_STATS: 55 count = ionic_get_stats_count(lif); 56 break; 57 } 58 return count; 59 } 60 61 static void ionic_get_strings(struct net_device *netdev, 62 u32 sset, u8 *buf) 63 { 64 struct ionic_lif *lif = netdev_priv(netdev); 65 66 switch (sset) { 67 case ETH_SS_STATS: 68 ionic_get_stats_strings(lif, buf); 69 break; 70 } 71 } 72 73 static void ionic_get_drvinfo(struct net_device *netdev, 74 struct ethtool_drvinfo *drvinfo) 75 { 76 struct ionic_lif *lif = netdev_priv(netdev); 77 struct ionic *ionic = lif->ionic; 78 79 strscpy(drvinfo->driver, IONIC_DRV_NAME, sizeof(drvinfo->driver)); 80 strscpy(drvinfo->fw_version, ionic->idev.dev_info.fw_version, 81 sizeof(drvinfo->fw_version)); 82 strscpy(drvinfo->bus_info, ionic_bus_info(ionic), 83 sizeof(drvinfo->bus_info)); 84 } 85 86 static int ionic_get_regs_len(struct net_device *netdev) 87 { 88 return (IONIC_DEV_INFO_REG_COUNT + IONIC_DEV_CMD_REG_COUNT) * sizeof(u32); 89 } 90 91 static void ionic_get_regs(struct net_device *netdev, struct ethtool_regs *regs, 92 void *p) 93 { 94 struct ionic_lif *lif = netdev_priv(netdev); 95 struct ionic_dev *idev; 96 unsigned int offset; 97 unsigned int size; 98 99 regs->version = IONIC_DEV_CMD_REG_VERSION; 100 101 idev = &lif->ionic->idev; 102 if (!idev->dev_info_regs) 103 return; 104 105 offset = 0; 106 size = IONIC_DEV_INFO_REG_COUNT * sizeof(u32); 107 memcpy_fromio(p + offset, lif->ionic->idev.dev_info_regs->words, size); 108 109 offset += size; 110 size = IONIC_DEV_CMD_REG_COUNT * sizeof(u32); 111 memcpy_fromio(p + offset, idev->dev_cmd_regs->words, size); 112 } 113 114 static void ionic_get_link_ext_stats(struct net_device *netdev, 115 struct ethtool_link_ext_stats *stats) 116 { 117 struct ionic_lif *lif = netdev_priv(netdev); 118 struct ionic *ionic = lif->ionic; 119 u64 link_down_count_total; 120 u16 link_down_count_fw; 121 122 if (ionic->pdev->is_virtfn) 123 return; 124 125 if (!ionic->idev.port_info) { 126 netdev_err_once(netdev, "port_info not initialized\n"); 127 return; 128 } 129 130 link_down_count_fw = 131 le16_to_cpu(ionic->idev.port_info->status.link_down_count); 132 link_down_count_total = ionic->idev.link_down_count_total + 133 link_down_count_fw - 134 ionic->idev.link_down_count_last; 135 136 /* The firmware counter is only 16 bits and can wraparound */ 137 if (link_down_count_fw < ionic->idev.link_down_count_last) 138 link_down_count_total += BIT(16); 139 140 ionic->idev.link_down_count_last = link_down_count_fw; 141 ionic->idev.link_down_count_total = link_down_count_total; 142 143 stats->link_down_events = link_down_count_total; 144 } 145 146 static int ionic_get_link_ksettings(struct net_device *netdev, 147 struct ethtool_link_ksettings *ks) 148 { 149 struct ionic_lif *lif = netdev_priv(netdev); 150 struct ionic_dev *idev = &lif->ionic->idev; 151 int copper_seen = 0; 152 153 ethtool_link_ksettings_zero_link_mode(ks, supported); 154 155 if (!idev->port_info) { 156 netdev_err(netdev, "port_info not initialized\n"); 157 return -EOPNOTSUPP; 158 } 159 160 /* The port_info data is found in a DMA space that the NIC keeps 161 * up-to-date, so there's no need to request the data from the 162 * NIC, we already have it in our memory space. 163 */ 164 165 switch (le16_to_cpu(idev->port_info->status.xcvr.pid)) { 166 /* Copper */ 167 case IONIC_XCVR_PID_QSFP_100G_CR4: 168 ethtool_link_ksettings_add_link_mode(ks, supported, 169 100000baseCR4_Full); 170 copper_seen++; 171 break; 172 case IONIC_XCVR_PID_QSFP_40GBASE_CR4: 173 ethtool_link_ksettings_add_link_mode(ks, supported, 174 40000baseCR4_Full); 175 copper_seen++; 176 break; 177 case IONIC_XCVR_PID_SFP_25GBASE_CR_S: 178 case IONIC_XCVR_PID_SFP_25GBASE_CR_L: 179 case IONIC_XCVR_PID_SFP_25GBASE_CR_N: 180 ethtool_link_ksettings_add_link_mode(ks, supported, 181 25000baseCR_Full); 182 copper_seen++; 183 break; 184 case IONIC_XCVR_PID_QSFP_50G_CR2_FC: 185 case IONIC_XCVR_PID_QSFP_50G_CR2: 186 ethtool_link_ksettings_add_link_mode(ks, supported, 187 50000baseCR2_Full); 188 copper_seen++; 189 break; 190 case IONIC_XCVR_PID_QSFP_200G_CR4: 191 ethtool_link_ksettings_add_link_mode(ks, supported, 200000baseCR4_Full); 192 copper_seen++; 193 break; 194 case IONIC_XCVR_PID_QSFP_400G_CR4: 195 ethtool_link_ksettings_add_link_mode(ks, supported, 400000baseCR4_Full); 196 copper_seen++; 197 break; 198 case IONIC_XCVR_PID_SFP_10GBASE_AOC: 199 case IONIC_XCVR_PID_SFP_10GBASE_CU: 200 ethtool_link_ksettings_add_link_mode(ks, supported, 201 10000baseCR_Full); 202 copper_seen++; 203 break; 204 205 /* Fibre */ 206 case IONIC_XCVR_PID_QSFP_100G_SR4: 207 case IONIC_XCVR_PID_QSFP_100G_AOC: 208 ethtool_link_ksettings_add_link_mode(ks, supported, 209 100000baseSR4_Full); 210 break; 211 case IONIC_XCVR_PID_QSFP_100G_CWDM4: 212 case IONIC_XCVR_PID_QSFP_100G_PSM4: 213 case IONIC_XCVR_PID_QSFP_100G_LR4: 214 case IONIC_XCVR_PID_QSFP_100G_ER4: 215 case IONIC_XCVR_PID_QSFP_100G_FR4: 216 case IONIC_XCVR_PID_QSFP_100G_DR4: 217 ethtool_link_ksettings_add_link_mode(ks, supported, 218 100000baseLR4_ER4_Full); 219 break; 220 case IONIC_XCVR_PID_QSFP_40GBASE_SR4: 221 case IONIC_XCVR_PID_QSFP_40GBASE_AOC: 222 ethtool_link_ksettings_add_link_mode(ks, supported, 223 40000baseSR4_Full); 224 break; 225 case IONIC_XCVR_PID_QSFP_40GBASE_LR4: 226 ethtool_link_ksettings_add_link_mode(ks, supported, 227 40000baseLR4_Full); 228 break; 229 case IONIC_XCVR_PID_SFP_25GBASE_SR: 230 case IONIC_XCVR_PID_SFP_25GBASE_AOC: 231 case IONIC_XCVR_PID_SFP_25GBASE_ACC: 232 ethtool_link_ksettings_add_link_mode(ks, supported, 233 25000baseSR_Full); 234 break; 235 case IONIC_XCVR_PID_QSFP_200G_AOC: 236 case IONIC_XCVR_PID_QSFP_200G_SR4: 237 case IONIC_XCVR_PID_QSFP_200G_AEC: 238 ethtool_link_ksettings_add_link_mode(ks, supported, 239 200000baseSR4_Full); 240 break; 241 case IONIC_XCVR_PID_QSFP_200G_FR4: 242 ethtool_link_ksettings_add_link_mode(ks, supported, 243 200000baseLR4_ER4_FR4_Full); 244 break; 245 case IONIC_XCVR_PID_QSFP_200G_DR4: 246 ethtool_link_ksettings_add_link_mode(ks, supported, 247 200000baseDR4_Full); 248 break; 249 case IONIC_XCVR_PID_QSFP_400G_FR4: 250 ethtool_link_ksettings_add_link_mode(ks, supported, 251 400000baseLR4_ER4_FR4_Full); 252 break; 253 case IONIC_XCVR_PID_QSFP_400G_DR4: 254 ethtool_link_ksettings_add_link_mode(ks, supported, 255 400000baseDR4_Full); 256 break; 257 case IONIC_XCVR_PID_QSFP_400G_SR4: 258 case IONIC_XCVR_PID_QSFP_400G_AOC: 259 case IONIC_XCVR_PID_QSFP_400G_AEC: 260 case IONIC_XCVR_PID_QSFP_400G_LPO: 261 ethtool_link_ksettings_add_link_mode(ks, supported, 262 400000baseSR4_Full); 263 break; 264 case IONIC_XCVR_PID_SFP_10GBASE_SR: 265 ethtool_link_ksettings_add_link_mode(ks, supported, 266 10000baseSR_Full); 267 break; 268 case IONIC_XCVR_PID_SFP_10GBASE_LR: 269 ethtool_link_ksettings_add_link_mode(ks, supported, 270 10000baseLR_Full); 271 break; 272 case IONIC_XCVR_PID_SFP_10GBASE_LRM: 273 ethtool_link_ksettings_add_link_mode(ks, supported, 274 10000baseLRM_Full); 275 break; 276 case IONIC_XCVR_PID_SFP_10GBASE_ER: 277 ethtool_link_ksettings_add_link_mode(ks, supported, 278 10000baseER_Full); 279 break; 280 case IONIC_XCVR_PID_SFP_10GBASE_T: 281 ethtool_link_ksettings_add_link_mode(ks, supported, 282 10000baseT_Full); 283 break; 284 case IONIC_XCVR_PID_SFP_1000BASE_T: 285 ethtool_link_ksettings_add_link_mode(ks, supported, 286 1000baseT_Full); 287 break; 288 case IONIC_XCVR_PID_UNKNOWN: 289 /* This means there's no module plugged in */ 290 break; 291 default: 292 dev_dbg_ratelimited(lif->ionic->dev, 293 "unknown xcvr type pid=%d / 0x%x\n", 294 idev->port_info->status.xcvr.pid, 295 idev->port_info->status.xcvr.pid); 296 break; 297 } 298 299 linkmode_copy(ks->link_modes.advertising, ks->link_modes.supported); 300 301 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_BASER); 302 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_RS); 303 if (idev->port_info->config.fec_type == IONIC_PORT_FEC_TYPE_FC) 304 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_BASER); 305 else if (idev->port_info->config.fec_type == IONIC_PORT_FEC_TYPE_RS) 306 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_RS); 307 308 ethtool_link_ksettings_add_link_mode(ks, supported, FIBRE); 309 ethtool_link_ksettings_add_link_mode(ks, supported, Pause); 310 311 if (idev->port_info->status.xcvr.phy == IONIC_PHY_TYPE_COPPER || 312 copper_seen) 313 ks->base.port = PORT_DA; 314 else if (idev->port_info->status.xcvr.phy == IONIC_PHY_TYPE_FIBER) 315 ks->base.port = PORT_FIBRE; 316 else 317 ks->base.port = PORT_NONE; 318 319 if (ks->base.port != PORT_NONE) { 320 ks->base.speed = le32_to_cpu(lif->info->status.link_speed); 321 322 if (le16_to_cpu(lif->info->status.link_status)) 323 ks->base.duplex = DUPLEX_FULL; 324 else 325 ks->base.duplex = DUPLEX_UNKNOWN; 326 327 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg); 328 329 if (idev->port_info->config.an_enable) { 330 ethtool_link_ksettings_add_link_mode(ks, advertising, 331 Autoneg); 332 ks->base.autoneg = AUTONEG_ENABLE; 333 } 334 } 335 336 return 0; 337 } 338 339 static int ionic_set_link_ksettings(struct net_device *netdev, 340 const struct ethtool_link_ksettings *ks) 341 { 342 struct ionic_lif *lif = netdev_priv(netdev); 343 struct ionic_dev *idev = &lif->ionic->idev; 344 struct ionic *ionic = lif->ionic; 345 int err = 0; 346 347 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 348 return -EBUSY; 349 350 /* set autoneg */ 351 if (ks->base.autoneg != idev->port_info->config.an_enable) { 352 mutex_lock(&ionic->dev_cmd_lock); 353 ionic_dev_cmd_port_autoneg(idev, ks->base.autoneg); 354 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 355 mutex_unlock(&ionic->dev_cmd_lock); 356 if (err) 357 return err; 358 } 359 360 /* set speed */ 361 if (ks->base.speed != le32_to_cpu(idev->port_info->config.speed)) { 362 mutex_lock(&ionic->dev_cmd_lock); 363 ionic_dev_cmd_port_speed(idev, ks->base.speed); 364 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 365 mutex_unlock(&ionic->dev_cmd_lock); 366 if (err) 367 return err; 368 } 369 370 return 0; 371 } 372 373 static void ionic_get_pauseparam(struct net_device *netdev, 374 struct ethtool_pauseparam *pause) 375 { 376 struct ionic_lif *lif = netdev_priv(netdev); 377 u8 pause_type; 378 379 pause->autoneg = 0; 380 381 pause_type = lif->ionic->idev.port_info->config.pause_type; 382 if (pause_type) { 383 pause->rx_pause = (pause_type & IONIC_PAUSE_F_RX) ? 1 : 0; 384 pause->tx_pause = (pause_type & IONIC_PAUSE_F_TX) ? 1 : 0; 385 } 386 } 387 388 static int ionic_set_pauseparam(struct net_device *netdev, 389 struct ethtool_pauseparam *pause) 390 { 391 struct ionic_lif *lif = netdev_priv(netdev); 392 struct ionic *ionic = lif->ionic; 393 u32 requested_pause; 394 int err; 395 396 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 397 return -EBUSY; 398 399 if (pause->autoneg) 400 return -EOPNOTSUPP; 401 402 /* change both at the same time */ 403 requested_pause = IONIC_PORT_PAUSE_TYPE_LINK; 404 if (pause->rx_pause) 405 requested_pause |= IONIC_PAUSE_F_RX; 406 if (pause->tx_pause) 407 requested_pause |= IONIC_PAUSE_F_TX; 408 409 if (requested_pause == lif->ionic->idev.port_info->config.pause_type) 410 return 0; 411 412 mutex_lock(&ionic->dev_cmd_lock); 413 ionic_dev_cmd_port_pause(&lif->ionic->idev, requested_pause); 414 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 415 mutex_unlock(&ionic->dev_cmd_lock); 416 if (err) 417 return err; 418 419 return 0; 420 } 421 422 static int ionic_get_fecparam(struct net_device *netdev, 423 struct ethtool_fecparam *fec) 424 { 425 struct ionic_lif *lif = netdev_priv(netdev); 426 427 switch (lif->ionic->idev.port_info->config.fec_type) { 428 case IONIC_PORT_FEC_TYPE_NONE: 429 fec->active_fec = ETHTOOL_FEC_OFF; 430 break; 431 case IONIC_PORT_FEC_TYPE_RS: 432 fec->active_fec = ETHTOOL_FEC_RS; 433 break; 434 case IONIC_PORT_FEC_TYPE_FC: 435 fec->active_fec = ETHTOOL_FEC_BASER; 436 break; 437 } 438 439 fec->fec = ETHTOOL_FEC_OFF | ETHTOOL_FEC_RS | ETHTOOL_FEC_BASER; 440 441 return 0; 442 } 443 444 static int ionic_set_fecparam(struct net_device *netdev, 445 struct ethtool_fecparam *fec) 446 { 447 struct ionic_lif *lif = netdev_priv(netdev); 448 u8 fec_type; 449 int ret = 0; 450 451 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 452 return -EBUSY; 453 454 if (lif->ionic->idev.port_info->config.an_enable) { 455 netdev_err(netdev, "FEC request not allowed while autoneg is enabled\n"); 456 return -EINVAL; 457 } 458 459 switch (fec->fec) { 460 case ETHTOOL_FEC_NONE: 461 fec_type = IONIC_PORT_FEC_TYPE_NONE; 462 break; 463 case ETHTOOL_FEC_OFF: 464 fec_type = IONIC_PORT_FEC_TYPE_NONE; 465 break; 466 case ETHTOOL_FEC_RS: 467 fec_type = IONIC_PORT_FEC_TYPE_RS; 468 break; 469 case ETHTOOL_FEC_BASER: 470 fec_type = IONIC_PORT_FEC_TYPE_FC; 471 break; 472 case ETHTOOL_FEC_AUTO: 473 default: 474 netdev_err(netdev, "FEC request 0x%04x not supported\n", 475 fec->fec); 476 return -EINVAL; 477 } 478 479 if (fec_type != lif->ionic->idev.port_info->config.fec_type) { 480 mutex_lock(&lif->ionic->dev_cmd_lock); 481 ionic_dev_cmd_port_fec(&lif->ionic->idev, fec_type); 482 ret = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 483 mutex_unlock(&lif->ionic->dev_cmd_lock); 484 } 485 486 return ret; 487 } 488 489 static int ionic_get_coalesce(struct net_device *netdev, 490 struct ethtool_coalesce *coalesce, 491 struct kernel_ethtool_coalesce *kernel_coal, 492 struct netlink_ext_ack *extack) 493 { 494 struct ionic_lif *lif = netdev_priv(netdev); 495 496 coalesce->tx_coalesce_usecs = lif->tx_coalesce_usecs; 497 coalesce->rx_coalesce_usecs = lif->rx_coalesce_usecs; 498 499 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 500 coalesce->use_adaptive_tx_coalesce = test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 501 else 502 coalesce->use_adaptive_tx_coalesce = 0; 503 504 coalesce->use_adaptive_rx_coalesce = test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 505 506 return 0; 507 } 508 509 static int ionic_set_coalesce(struct net_device *netdev, 510 struct ethtool_coalesce *coalesce, 511 struct kernel_ethtool_coalesce *kernel_coal, 512 struct netlink_ext_ack *extack) 513 { 514 struct ionic_lif *lif = netdev_priv(netdev); 515 struct ionic_identity *ident; 516 u32 rx_coal, rx_dim; 517 u32 tx_coal, tx_dim; 518 unsigned int i; 519 520 ident = &lif->ionic->ident; 521 if (ident->dev.intr_coal_div == 0) { 522 netdev_warn(netdev, "bad HW value in dev.intr_coal_div = %d\n", 523 ident->dev.intr_coal_div); 524 return -EIO; 525 } 526 527 /* Tx normally shares Rx interrupt, so only change Rx if not split */ 528 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) && 529 (coalesce->tx_coalesce_usecs != lif->rx_coalesce_usecs || 530 coalesce->use_adaptive_tx_coalesce)) { 531 netdev_warn(netdev, "only rx parameters can be changed\n"); 532 return -EINVAL; 533 } 534 535 /* Convert the usec request to a HW usable value. If they asked 536 * for non-zero and it resolved to zero, bump it up 537 */ 538 rx_coal = ionic_coal_usec_to_hw(lif->ionic, coalesce->rx_coalesce_usecs); 539 if (!rx_coal && coalesce->rx_coalesce_usecs) 540 rx_coal = 1; 541 tx_coal = ionic_coal_usec_to_hw(lif->ionic, coalesce->tx_coalesce_usecs); 542 if (!tx_coal && coalesce->tx_coalesce_usecs) 543 tx_coal = 1; 544 545 if (rx_coal > IONIC_INTR_CTRL_COAL_MAX || 546 tx_coal > IONIC_INTR_CTRL_COAL_MAX) 547 return -ERANGE; 548 549 /* Save the new values */ 550 lif->rx_coalesce_usecs = coalesce->rx_coalesce_usecs; 551 lif->rx_coalesce_hw = rx_coal; 552 553 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 554 lif->tx_coalesce_usecs = coalesce->tx_coalesce_usecs; 555 else 556 lif->tx_coalesce_usecs = coalesce->rx_coalesce_usecs; 557 lif->tx_coalesce_hw = tx_coal; 558 559 if (coalesce->use_adaptive_rx_coalesce) { 560 set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 561 rx_dim = rx_coal; 562 } else { 563 clear_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 564 rx_dim = 0; 565 } 566 567 if (coalesce->use_adaptive_tx_coalesce) { 568 set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 569 tx_dim = tx_coal; 570 } else { 571 clear_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 572 tx_dim = 0; 573 } 574 575 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 576 for (i = 0; i < lif->nxqs; i++) { 577 if (lif->rxqcqs[i]->flags & IONIC_QCQ_F_INTR) { 578 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 579 lif->rxqcqs[i]->intr.index, 580 lif->rx_coalesce_hw); 581 lif->rxqcqs[i]->intr.dim_coal_hw = rx_dim; 582 } 583 584 if (lif->txqcqs[i]->flags & IONIC_QCQ_F_INTR) { 585 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 586 lif->txqcqs[i]->intr.index, 587 lif->tx_coalesce_hw); 588 lif->txqcqs[i]->intr.dim_coal_hw = tx_dim; 589 } 590 } 591 } 592 593 return 0; 594 } 595 596 static int ionic_validate_cmb_config(struct ionic_lif *lif, 597 struct ionic_queue_params *qparam) 598 { 599 int pages_have, pages_required = 0; 600 unsigned long sz; 601 602 if (!lif->ionic->idev.cmb_inuse && 603 (qparam->cmb_tx || qparam->cmb_rx)) { 604 netdev_info(lif->netdev, "CMB rings are not supported on this device\n"); 605 return -EOPNOTSUPP; 606 } 607 608 if (qparam->cmb_tx) { 609 if (!(lif->qtype_info[IONIC_QTYPE_TXQ].features & IONIC_QIDENT_F_CMB)) { 610 netdev_info(lif->netdev, 611 "CMB rings for tx-push are not supported on this device\n"); 612 return -EOPNOTSUPP; 613 } 614 615 sz = sizeof(struct ionic_txq_desc) * qparam->ntxq_descs * qparam->nxqs; 616 pages_required += ALIGN(sz, PAGE_SIZE) / PAGE_SIZE; 617 } 618 619 if (qparam->cmb_rx) { 620 if (!(lif->qtype_info[IONIC_QTYPE_RXQ].features & IONIC_QIDENT_F_CMB)) { 621 netdev_info(lif->netdev, 622 "CMB rings for rx-push are not supported on this device\n"); 623 return -EOPNOTSUPP; 624 } 625 626 sz = sizeof(struct ionic_rxq_desc) * qparam->nrxq_descs * qparam->nxqs; 627 pages_required += ALIGN(sz, PAGE_SIZE) / PAGE_SIZE; 628 } 629 630 pages_have = lif->ionic->bars[IONIC_PCI_BAR_CMB].len / PAGE_SIZE; 631 if (pages_required > pages_have) { 632 netdev_info(lif->netdev, 633 "Not enough CMB pages for number of queues and size of descriptor rings, need %d have %d", 634 pages_required, pages_have); 635 return -ENOMEM; 636 } 637 638 return pages_required; 639 } 640 641 static int ionic_cmb_rings_toggle(struct ionic_lif *lif, bool cmb_tx, bool cmb_rx) 642 { 643 struct ionic_queue_params qparam; 644 int pages_used; 645 646 if (netif_running(lif->netdev)) { 647 netdev_info(lif->netdev, "Please stop device to toggle CMB for tx/rx-push\n"); 648 return -EBUSY; 649 } 650 651 ionic_init_queue_params(lif, &qparam); 652 qparam.cmb_tx = cmb_tx; 653 qparam.cmb_rx = cmb_rx; 654 pages_used = ionic_validate_cmb_config(lif, &qparam); 655 if (pages_used < 0) 656 return pages_used; 657 658 assign_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state, cmb_tx); 659 660 assign_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state, cmb_rx); 661 662 if (cmb_tx || cmb_rx) 663 netdev_info(lif->netdev, "Enabling CMB %s %s rings - %d pages\n", 664 cmb_tx ? "TX" : "", cmb_rx ? "RX" : "", pages_used); 665 else 666 netdev_info(lif->netdev, "Disabling CMB rings\n"); 667 668 return 0; 669 } 670 671 static void ionic_get_ringparam(struct net_device *netdev, 672 struct ethtool_ringparam *ring, 673 struct kernel_ethtool_ringparam *kernel_ring, 674 struct netlink_ext_ack *extack) 675 { 676 struct ionic_lif *lif = netdev_priv(netdev); 677 678 ring->tx_max_pending = IONIC_MAX_TX_DESC; 679 ring->tx_pending = lif->ntxq_descs; 680 ring->rx_max_pending = IONIC_MAX_RX_DESC; 681 ring->rx_pending = lif->nrxq_descs; 682 kernel_ring->tx_push = test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state); 683 kernel_ring->rx_push = test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state); 684 } 685 686 static int ionic_set_ringparam(struct net_device *netdev, 687 struct ethtool_ringparam *ring, 688 struct kernel_ethtool_ringparam *kernel_ring, 689 struct netlink_ext_ack *extack) 690 { 691 struct ionic_lif *lif = netdev_priv(netdev); 692 struct ionic_queue_params qparam; 693 int err; 694 695 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 696 return -EBUSY; 697 698 ionic_init_queue_params(lif, &qparam); 699 700 if (ring->rx_mini_pending || ring->rx_jumbo_pending) { 701 netdev_info(netdev, "Changing jumbo or mini descriptors not supported\n"); 702 return -EINVAL; 703 } 704 705 if (!is_power_of_2(ring->tx_pending) || 706 !is_power_of_2(ring->rx_pending)) { 707 netdev_info(netdev, "Descriptor count must be a power of 2\n"); 708 return -EINVAL; 709 } 710 711 /* if nothing to do return success */ 712 if (ring->tx_pending == lif->ntxq_descs && 713 ring->rx_pending == lif->nrxq_descs && 714 kernel_ring->tx_push == test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state) && 715 kernel_ring->rx_push == test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state)) 716 return 0; 717 718 qparam.ntxq_descs = ring->tx_pending; 719 qparam.nrxq_descs = ring->rx_pending; 720 qparam.cmb_tx = kernel_ring->tx_push; 721 qparam.cmb_rx = kernel_ring->rx_push; 722 723 err = ionic_validate_cmb_config(lif, &qparam); 724 if (err < 0) 725 return err; 726 727 if (kernel_ring->tx_push != test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state) || 728 kernel_ring->rx_push != test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state)) { 729 err = ionic_cmb_rings_toggle(lif, kernel_ring->tx_push, 730 kernel_ring->rx_push); 731 if (err < 0) 732 return err; 733 } 734 735 if (ring->tx_pending != lif->ntxq_descs) 736 netdev_info(netdev, "Changing Tx ring size from %d to %d\n", 737 lif->ntxq_descs, ring->tx_pending); 738 739 if (ring->rx_pending != lif->nrxq_descs) 740 netdev_info(netdev, "Changing Rx ring size from %d to %d\n", 741 lif->nrxq_descs, ring->rx_pending); 742 743 /* if we're not running, just set the values and return */ 744 if (!netif_running(lif->netdev)) { 745 lif->ntxq_descs = ring->tx_pending; 746 lif->nrxq_descs = ring->rx_pending; 747 return 0; 748 } 749 750 mutex_lock(&lif->queue_lock); 751 err = ionic_reconfigure_queues(lif, &qparam); 752 mutex_unlock(&lif->queue_lock); 753 if (err) 754 netdev_info(netdev, "Ring reconfiguration failed, changes canceled: %d\n", err); 755 756 return err; 757 } 758 759 static void ionic_get_channels(struct net_device *netdev, 760 struct ethtool_channels *ch) 761 { 762 struct ionic_lif *lif = netdev_priv(netdev); 763 764 /* report maximum channels */ 765 ch->max_combined = lif->ionic->ntxqs_per_lif; 766 ch->max_rx = lif->ionic->ntxqs_per_lif / 2; 767 ch->max_tx = lif->ionic->ntxqs_per_lif / 2; 768 769 /* report current channels */ 770 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) { 771 ch->rx_count = lif->nxqs; 772 ch->tx_count = lif->nxqs; 773 } else { 774 ch->combined_count = lif->nxqs; 775 } 776 } 777 778 static int ionic_set_channels(struct net_device *netdev, 779 struct ethtool_channels *ch) 780 { 781 struct ionic_lif *lif = netdev_priv(netdev); 782 struct ionic_queue_params qparam; 783 int max_cnt; 784 int err; 785 786 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 787 return -EBUSY; 788 789 ionic_init_queue_params(lif, &qparam); 790 791 if ((ch->rx_count || ch->tx_count) && lif->xdp_prog) { 792 netdev_info(lif->netdev, "Split Tx/Rx interrupts not available when using XDP\n"); 793 return -EOPNOTSUPP; 794 } 795 796 if (ch->rx_count != ch->tx_count) { 797 netdev_info(netdev, "The rx and tx count must be equal\n"); 798 return -EINVAL; 799 } 800 801 if (ch->combined_count && ch->rx_count) { 802 netdev_info(netdev, "Use either combined or rx and tx, not both\n"); 803 return -EINVAL; 804 } 805 806 max_cnt = lif->ionic->ntxqs_per_lif; 807 if (ch->combined_count) { 808 if (ch->combined_count > max_cnt) 809 return -EINVAL; 810 811 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 812 netdev_info(lif->netdev, "Sharing queue interrupts\n"); 813 else if (ch->combined_count == lif->nxqs) 814 return 0; 815 816 if (lif->nxqs != ch->combined_count) 817 netdev_info(netdev, "Changing queue count from %d to %d\n", 818 lif->nxqs, ch->combined_count); 819 820 qparam.nxqs = ch->combined_count; 821 qparam.intr_split = false; 822 } else { 823 max_cnt /= 2; 824 if (ch->rx_count > max_cnt) 825 return -EINVAL; 826 827 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 828 netdev_info(lif->netdev, "Splitting queue interrupts\n"); 829 else if (ch->rx_count == lif->nxqs) 830 return 0; 831 832 if (lif->nxqs != ch->rx_count) 833 netdev_info(netdev, "Changing queue count from %d to %d\n", 834 lif->nxqs, ch->rx_count); 835 836 qparam.nxqs = ch->rx_count; 837 qparam.intr_split = true; 838 } 839 840 err = ionic_validate_cmb_config(lif, &qparam); 841 if (err < 0) 842 return err; 843 844 /* if we're not running, just set the values and return */ 845 if (!netif_running(lif->netdev)) { 846 lif->nxqs = qparam.nxqs; 847 848 if (qparam.intr_split) { 849 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 850 } else { 851 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 852 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 853 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 854 } 855 return 0; 856 } 857 858 mutex_lock(&lif->queue_lock); 859 err = ionic_reconfigure_queues(lif, &qparam); 860 mutex_unlock(&lif->queue_lock); 861 if (err) 862 netdev_info(netdev, "Queue reconfiguration failed, changes canceled: %d\n", err); 863 864 return err; 865 } 866 867 static u32 ionic_get_rx_ring_count(struct net_device *netdev) 868 { 869 struct ionic_lif *lif = netdev_priv(netdev); 870 871 return lif->nxqs; 872 } 873 874 static u32 ionic_get_rxfh_indir_size(struct net_device *netdev) 875 { 876 struct ionic_lif *lif = netdev_priv(netdev); 877 878 return le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 879 } 880 881 static u32 ionic_get_rxfh_key_size(struct net_device *netdev) 882 { 883 return IONIC_RSS_HASH_KEY_SIZE; 884 } 885 886 static int ionic_get_rxfh(struct net_device *netdev, 887 struct ethtool_rxfh_param *rxfh) 888 { 889 struct ionic_lif *lif = netdev_priv(netdev); 890 unsigned int i, tbl_sz; 891 892 if (rxfh->indir) { 893 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 894 for (i = 0; i < tbl_sz; i++) 895 rxfh->indir[i] = lif->rss_ind_tbl[i]; 896 } 897 898 if (rxfh->key) 899 memcpy(rxfh->key, lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE); 900 901 rxfh->hfunc = ETH_RSS_HASH_TOP; 902 903 return 0; 904 } 905 906 static int ionic_set_rxfh(struct net_device *netdev, 907 struct ethtool_rxfh_param *rxfh, 908 struct netlink_ext_ack *extack) 909 { 910 struct ionic_lif *lif = netdev_priv(netdev); 911 912 if (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE && 913 rxfh->hfunc != ETH_RSS_HASH_TOP) 914 return -EOPNOTSUPP; 915 916 return ionic_lif_rss_config(lif, lif->rss_types, 917 rxfh->key, rxfh->indir); 918 } 919 920 static int ionic_set_tunable(struct net_device *dev, 921 const struct ethtool_tunable *tuna, 922 const void *data) 923 { 924 struct ionic_lif *lif = netdev_priv(dev); 925 u32 rx_copybreak; 926 927 switch (tuna->id) { 928 case ETHTOOL_RX_COPYBREAK: 929 rx_copybreak = *(u32 *)data; 930 if (rx_copybreak > IONIC_MAX_RX_COPYBREAK) { 931 netdev_err(dev, "Max supported rx_copybreak size: %u\n", 932 IONIC_MAX_RX_COPYBREAK); 933 return -EINVAL; 934 } 935 lif->rx_copybreak = (u16)rx_copybreak; 936 break; 937 default: 938 return -EOPNOTSUPP; 939 } 940 941 return 0; 942 } 943 944 static int ionic_get_tunable(struct net_device *netdev, 945 const struct ethtool_tunable *tuna, void *data) 946 { 947 struct ionic_lif *lif = netdev_priv(netdev); 948 949 switch (tuna->id) { 950 case ETHTOOL_RX_COPYBREAK: 951 *(u32 *)data = lif->rx_copybreak; 952 break; 953 default: 954 return -EOPNOTSUPP; 955 } 956 957 return 0; 958 } 959 960 static int ionic_do_module_copy(u8 *dst, u8 *src, u32 len) 961 { 962 char tbuf[sizeof_field(struct ionic_xcvr_status, sprom)]; 963 int count = 10; 964 965 /* The NIC keeps the module prom up-to-date in the DMA space 966 * so we can simply copy the module bytes into the data buffer. 967 */ 968 do { 969 memcpy(dst, src, len); 970 memcpy(tbuf, src, len); 971 972 /* Let's make sure we got a consistent copy */ 973 if (!memcmp(dst, tbuf, len)) 974 break; 975 976 } while (--count); 977 978 if (!count) 979 return -ETIMEDOUT; 980 981 return 0; 982 } 983 984 static int ionic_get_module_eeprom_by_page(struct net_device *netdev, 985 const struct ethtool_module_eeprom *page_data, 986 struct netlink_ext_ack *extack) 987 { 988 struct ionic_lif *lif = netdev_priv(netdev); 989 struct ionic_dev *idev = &lif->ionic->idev; 990 int err; 991 u8 *src; 992 993 if (!page_data->length) 994 return -EINVAL; 995 996 if (page_data->bank != 0) { 997 NL_SET_ERR_MSG_MOD(extack, "Only bank 0 is supported"); 998 return -EINVAL; 999 } 1000 1001 switch (page_data->page) { 1002 case 0: 1003 src = &idev->port_info->status.xcvr.sprom[page_data->offset]; 1004 break; 1005 case 1: 1006 src = &idev->port_info->sprom_page1[page_data->offset - 128]; 1007 break; 1008 case 2: 1009 src = &idev->port_info->sprom_page2[page_data->offset - 128]; 1010 break; 1011 case 17: 1012 src = &idev->port_info->sprom_page17[page_data->offset - 128]; 1013 break; 1014 default: 1015 return -EOPNOTSUPP; 1016 } 1017 1018 memset(page_data->data, 0, page_data->length); 1019 err = ionic_do_module_copy(page_data->data, src, page_data->length); 1020 if (err) 1021 return err; 1022 1023 return page_data->length; 1024 } 1025 1026 static int ionic_get_ts_info(struct net_device *netdev, 1027 struct kernel_ethtool_ts_info *info) 1028 { 1029 struct ionic_lif *lif = netdev_priv(netdev); 1030 struct ionic *ionic = lif->ionic; 1031 __le64 mask; 1032 1033 if (!lif->phc || !lif->phc->ptp) 1034 return ethtool_op_get_ts_info(netdev, info); 1035 1036 info->phc_index = ptp_clock_index(lif->phc->ptp); 1037 1038 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE; 1039 1040 if (!(lif->hw_features & IONIC_ETH_HW_TIMESTAMP)) 1041 return 0; 1042 1043 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | 1044 SOF_TIMESTAMPING_RX_HARDWARE | 1045 SOF_TIMESTAMPING_RAW_HARDWARE; 1046 1047 /* tx modes */ 1048 1049 info->tx_types = BIT(HWTSTAMP_TX_OFF) | 1050 BIT(HWTSTAMP_TX_ON); 1051 1052 mask = cpu_to_le64(BIT_ULL(IONIC_TXSTAMP_ONESTEP_SYNC)); 1053 if (ionic->ident.lif.eth.hwstamp_tx_modes & mask) 1054 info->tx_types |= BIT(HWTSTAMP_TX_ONESTEP_SYNC); 1055 1056 mask = cpu_to_le64(BIT_ULL(IONIC_TXSTAMP_ONESTEP_P2P)); 1057 if (ionic->ident.lif.eth.hwstamp_tx_modes & mask) 1058 info->tx_types |= BIT(HWTSTAMP_TX_ONESTEP_P2P); 1059 1060 /* rx filters */ 1061 1062 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 1063 BIT(HWTSTAMP_FILTER_ALL); 1064 1065 mask = cpu_to_le64(IONIC_PKT_CLS_NTP_ALL); 1066 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1067 info->rx_filters |= BIT(HWTSTAMP_FILTER_NTP_ALL); 1068 1069 mask = cpu_to_le64(IONIC_PKT_CLS_PTP1_SYNC); 1070 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1071 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC); 1072 1073 mask = cpu_to_le64(IONIC_PKT_CLS_PTP1_DREQ); 1074 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1075 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ); 1076 1077 mask = cpu_to_le64(IONIC_PKT_CLS_PTP1_ALL); 1078 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1079 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_EVENT); 1080 1081 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L4_SYNC); 1082 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1083 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC); 1084 1085 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L4_DREQ); 1086 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1087 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ); 1088 1089 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L4_ALL); 1090 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1091 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 1092 1093 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L2_SYNC); 1094 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1095 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC); 1096 1097 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L2_DREQ); 1098 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1099 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ); 1100 1101 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L2_ALL); 1102 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1103 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT); 1104 1105 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_SYNC); 1106 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1107 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_SYNC); 1108 1109 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_DREQ); 1110 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1111 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ); 1112 1113 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_ALL); 1114 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1115 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_EVENT); 1116 1117 return 0; 1118 } 1119 1120 static int ionic_nway_reset(struct net_device *netdev) 1121 { 1122 struct ionic_lif *lif = netdev_priv(netdev); 1123 struct ionic *ionic = lif->ionic; 1124 int err = 0; 1125 1126 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 1127 return -EBUSY; 1128 1129 /* flap the link to force auto-negotiation */ 1130 1131 mutex_lock(&ionic->dev_cmd_lock); 1132 1133 ionic_dev_cmd_port_state(&ionic->idev, IONIC_PORT_ADMIN_STATE_DOWN); 1134 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 1135 1136 if (!err) { 1137 ionic_dev_cmd_port_state(&ionic->idev, IONIC_PORT_ADMIN_STATE_UP); 1138 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 1139 } 1140 1141 mutex_unlock(&ionic->dev_cmd_lock); 1142 1143 return err; 1144 } 1145 1146 static const struct ethtool_ops ionic_ethtool_ops = { 1147 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1148 ETHTOOL_COALESCE_USE_ADAPTIVE_RX | 1149 ETHTOOL_COALESCE_USE_ADAPTIVE_TX, 1150 .supported_ring_params = ETHTOOL_RING_USE_TX_PUSH | 1151 ETHTOOL_RING_USE_RX_PUSH, 1152 .get_drvinfo = ionic_get_drvinfo, 1153 .get_regs_len = ionic_get_regs_len, 1154 .get_regs = ionic_get_regs, 1155 .get_link = ethtool_op_get_link, 1156 .get_link_ext_stats = ionic_get_link_ext_stats, 1157 .get_link_ksettings = ionic_get_link_ksettings, 1158 .set_link_ksettings = ionic_set_link_ksettings, 1159 .get_coalesce = ionic_get_coalesce, 1160 .set_coalesce = ionic_set_coalesce, 1161 .get_ringparam = ionic_get_ringparam, 1162 .set_ringparam = ionic_set_ringparam, 1163 .get_channels = ionic_get_channels, 1164 .set_channels = ionic_set_channels, 1165 .get_strings = ionic_get_strings, 1166 .get_ethtool_stats = ionic_get_stats, 1167 .get_sset_count = ionic_get_sset_count, 1168 .get_rx_ring_count = ionic_get_rx_ring_count, 1169 .get_rxfh_indir_size = ionic_get_rxfh_indir_size, 1170 .get_rxfh_key_size = ionic_get_rxfh_key_size, 1171 .get_rxfh = ionic_get_rxfh, 1172 .set_rxfh = ionic_set_rxfh, 1173 .get_tunable = ionic_get_tunable, 1174 .set_tunable = ionic_set_tunable, 1175 .get_module_eeprom_by_page = ionic_get_module_eeprom_by_page, 1176 .get_pauseparam = ionic_get_pauseparam, 1177 .set_pauseparam = ionic_set_pauseparam, 1178 .get_fecparam = ionic_get_fecparam, 1179 .set_fecparam = ionic_set_fecparam, 1180 .get_ts_info = ionic_get_ts_info, 1181 .nway_reset = ionic_nway_reset, 1182 }; 1183 1184 void ionic_ethtool_set_ops(struct net_device *netdev) 1185 { 1186 netdev->ethtool_ops = &ionic_ethtool_ops; 1187 } 1188