1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/module.h> 5 #include <linux/netdevice.h> 6 #include <linux/sfp.h> 7 8 #include "ionic.h" 9 #include "ionic_bus.h" 10 #include "ionic_lif.h" 11 #include "ionic_ethtool.h" 12 #include "ionic_stats.h" 13 14 #define IONIC_MAX_RX_COPYBREAK min(U16_MAX, IONIC_MAX_BUF_LEN) 15 16 static void ionic_get_stats_strings(struct ionic_lif *lif, u8 *buf) 17 { 18 u32 i; 19 20 for (i = 0; i < ionic_num_stats_grps; i++) 21 ionic_stats_groups[i].get_strings(lif, &buf); 22 } 23 24 static void ionic_get_stats(struct net_device *netdev, 25 struct ethtool_stats *stats, u64 *buf) 26 { 27 struct ionic_lif *lif = netdev_priv(netdev); 28 u32 i; 29 30 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 31 return; 32 33 memset(buf, 0, stats->n_stats * sizeof(*buf)); 34 for (i = 0; i < ionic_num_stats_grps; i++) 35 ionic_stats_groups[i].get_values(lif, &buf); 36 } 37 38 static int ionic_get_stats_count(struct ionic_lif *lif) 39 { 40 int i, num_stats = 0; 41 42 for (i = 0; i < ionic_num_stats_grps; i++) 43 num_stats += ionic_stats_groups[i].get_count(lif); 44 45 return num_stats; 46 } 47 48 static int ionic_get_sset_count(struct net_device *netdev, int sset) 49 { 50 struct ionic_lif *lif = netdev_priv(netdev); 51 int count = 0; 52 53 switch (sset) { 54 case ETH_SS_STATS: 55 count = ionic_get_stats_count(lif); 56 break; 57 } 58 return count; 59 } 60 61 static void ionic_get_strings(struct net_device *netdev, 62 u32 sset, u8 *buf) 63 { 64 struct ionic_lif *lif = netdev_priv(netdev); 65 66 switch (sset) { 67 case ETH_SS_STATS: 68 ionic_get_stats_strings(lif, buf); 69 break; 70 } 71 } 72 73 static void ionic_get_drvinfo(struct net_device *netdev, 74 struct ethtool_drvinfo *drvinfo) 75 { 76 struct ionic_lif *lif = netdev_priv(netdev); 77 struct ionic *ionic = lif->ionic; 78 79 strscpy(drvinfo->driver, IONIC_DRV_NAME, sizeof(drvinfo->driver)); 80 strscpy(drvinfo->fw_version, ionic->idev.dev_info.fw_version, 81 sizeof(drvinfo->fw_version)); 82 strscpy(drvinfo->bus_info, ionic_bus_info(ionic), 83 sizeof(drvinfo->bus_info)); 84 } 85 86 static int ionic_get_regs_len(struct net_device *netdev) 87 { 88 return (IONIC_DEV_INFO_REG_COUNT + IONIC_DEV_CMD_REG_COUNT) * sizeof(u32); 89 } 90 91 static void ionic_get_regs(struct net_device *netdev, struct ethtool_regs *regs, 92 void *p) 93 { 94 struct ionic_lif *lif = netdev_priv(netdev); 95 struct ionic_dev *idev; 96 unsigned int offset; 97 unsigned int size; 98 99 regs->version = IONIC_DEV_CMD_REG_VERSION; 100 101 idev = &lif->ionic->idev; 102 if (!idev->dev_info_regs) 103 return; 104 105 offset = 0; 106 size = IONIC_DEV_INFO_REG_COUNT * sizeof(u32); 107 memcpy_fromio(p + offset, lif->ionic->idev.dev_info_regs->words, size); 108 109 offset += size; 110 size = IONIC_DEV_CMD_REG_COUNT * sizeof(u32); 111 memcpy_fromio(p + offset, idev->dev_cmd_regs->words, size); 112 } 113 114 static void ionic_get_link_ext_stats(struct net_device *netdev, 115 struct ethtool_link_ext_stats *stats) 116 { 117 struct ionic_lif *lif = netdev_priv(netdev); 118 119 if (lif->ionic->pdev->is_physfn) 120 stats->link_down_events = lif->link_down_count; 121 } 122 123 static int ionic_get_link_ksettings(struct net_device *netdev, 124 struct ethtool_link_ksettings *ks) 125 { 126 struct ionic_lif *lif = netdev_priv(netdev); 127 struct ionic_dev *idev = &lif->ionic->idev; 128 int copper_seen = 0; 129 130 ethtool_link_ksettings_zero_link_mode(ks, supported); 131 132 if (!idev->port_info) { 133 netdev_err(netdev, "port_info not initialized\n"); 134 return -EOPNOTSUPP; 135 } 136 137 /* The port_info data is found in a DMA space that the NIC keeps 138 * up-to-date, so there's no need to request the data from the 139 * NIC, we already have it in our memory space. 140 */ 141 142 switch (le16_to_cpu(idev->port_info->status.xcvr.pid)) { 143 /* Copper */ 144 case IONIC_XCVR_PID_QSFP_100G_CR4: 145 ethtool_link_ksettings_add_link_mode(ks, supported, 146 100000baseCR4_Full); 147 copper_seen++; 148 break; 149 case IONIC_XCVR_PID_QSFP_40GBASE_CR4: 150 ethtool_link_ksettings_add_link_mode(ks, supported, 151 40000baseCR4_Full); 152 copper_seen++; 153 break; 154 case IONIC_XCVR_PID_SFP_25GBASE_CR_S: 155 case IONIC_XCVR_PID_SFP_25GBASE_CR_L: 156 case IONIC_XCVR_PID_SFP_25GBASE_CR_N: 157 ethtool_link_ksettings_add_link_mode(ks, supported, 158 25000baseCR_Full); 159 copper_seen++; 160 break; 161 case IONIC_XCVR_PID_QSFP_50G_CR2_FC: 162 case IONIC_XCVR_PID_QSFP_50G_CR2: 163 ethtool_link_ksettings_add_link_mode(ks, supported, 164 50000baseCR2_Full); 165 copper_seen++; 166 break; 167 case IONIC_XCVR_PID_QSFP_200G_CR4: 168 ethtool_link_ksettings_add_link_mode(ks, supported, 200000baseCR4_Full); 169 copper_seen++; 170 break; 171 case IONIC_XCVR_PID_QSFP_400G_CR4: 172 ethtool_link_ksettings_add_link_mode(ks, supported, 400000baseCR4_Full); 173 copper_seen++; 174 break; 175 case IONIC_XCVR_PID_SFP_10GBASE_AOC: 176 case IONIC_XCVR_PID_SFP_10GBASE_CU: 177 ethtool_link_ksettings_add_link_mode(ks, supported, 178 10000baseCR_Full); 179 copper_seen++; 180 break; 181 182 /* Fibre */ 183 case IONIC_XCVR_PID_QSFP_100G_SR4: 184 case IONIC_XCVR_PID_QSFP_100G_AOC: 185 ethtool_link_ksettings_add_link_mode(ks, supported, 186 100000baseSR4_Full); 187 break; 188 case IONIC_XCVR_PID_QSFP_100G_CWDM4: 189 case IONIC_XCVR_PID_QSFP_100G_PSM4: 190 case IONIC_XCVR_PID_QSFP_100G_LR4: 191 ethtool_link_ksettings_add_link_mode(ks, supported, 192 100000baseLR4_ER4_Full); 193 break; 194 case IONIC_XCVR_PID_QSFP_100G_ER4: 195 ethtool_link_ksettings_add_link_mode(ks, supported, 196 100000baseLR4_ER4_Full); 197 break; 198 case IONIC_XCVR_PID_QSFP_40GBASE_SR4: 199 case IONIC_XCVR_PID_QSFP_40GBASE_AOC: 200 ethtool_link_ksettings_add_link_mode(ks, supported, 201 40000baseSR4_Full); 202 break; 203 case IONIC_XCVR_PID_QSFP_40GBASE_LR4: 204 ethtool_link_ksettings_add_link_mode(ks, supported, 205 40000baseLR4_Full); 206 break; 207 case IONIC_XCVR_PID_SFP_25GBASE_SR: 208 case IONIC_XCVR_PID_SFP_25GBASE_AOC: 209 case IONIC_XCVR_PID_SFP_25GBASE_ACC: 210 ethtool_link_ksettings_add_link_mode(ks, supported, 211 25000baseSR_Full); 212 break; 213 case IONIC_XCVR_PID_QSFP_200G_AOC: 214 case IONIC_XCVR_PID_QSFP_200G_SR4: 215 ethtool_link_ksettings_add_link_mode(ks, supported, 216 200000baseSR4_Full); 217 break; 218 case IONIC_XCVR_PID_QSFP_200G_FR4: 219 ethtool_link_ksettings_add_link_mode(ks, supported, 220 200000baseLR4_ER4_FR4_Full); 221 break; 222 case IONIC_XCVR_PID_QSFP_200G_DR4: 223 ethtool_link_ksettings_add_link_mode(ks, supported, 224 200000baseDR4_Full); 225 break; 226 case IONIC_XCVR_PID_QSFP_400G_FR4: 227 ethtool_link_ksettings_add_link_mode(ks, supported, 228 400000baseLR4_ER4_FR4_Full); 229 break; 230 case IONIC_XCVR_PID_QSFP_400G_DR4: 231 ethtool_link_ksettings_add_link_mode(ks, supported, 232 400000baseDR4_Full); 233 break; 234 case IONIC_XCVR_PID_QSFP_400G_SR4: 235 ethtool_link_ksettings_add_link_mode(ks, supported, 236 400000baseSR4_Full); 237 break; 238 case IONIC_XCVR_PID_SFP_10GBASE_SR: 239 ethtool_link_ksettings_add_link_mode(ks, supported, 240 10000baseSR_Full); 241 break; 242 case IONIC_XCVR_PID_SFP_10GBASE_LR: 243 ethtool_link_ksettings_add_link_mode(ks, supported, 244 10000baseLR_Full); 245 break; 246 case IONIC_XCVR_PID_SFP_10GBASE_LRM: 247 ethtool_link_ksettings_add_link_mode(ks, supported, 248 10000baseLRM_Full); 249 break; 250 case IONIC_XCVR_PID_SFP_10GBASE_ER: 251 ethtool_link_ksettings_add_link_mode(ks, supported, 252 10000baseER_Full); 253 break; 254 case IONIC_XCVR_PID_SFP_10GBASE_T: 255 ethtool_link_ksettings_add_link_mode(ks, supported, 256 10000baseT_Full); 257 break; 258 case IONIC_XCVR_PID_SFP_1000BASE_T: 259 ethtool_link_ksettings_add_link_mode(ks, supported, 260 1000baseT_Full); 261 break; 262 case IONIC_XCVR_PID_UNKNOWN: 263 /* This means there's no module plugged in */ 264 break; 265 default: 266 dev_dbg_ratelimited(lif->ionic->dev, 267 "unknown xcvr type pid=%d / 0x%x\n", 268 idev->port_info->status.xcvr.pid, 269 idev->port_info->status.xcvr.pid); 270 break; 271 } 272 273 linkmode_copy(ks->link_modes.advertising, ks->link_modes.supported); 274 275 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_BASER); 276 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_RS); 277 if (idev->port_info->config.fec_type == IONIC_PORT_FEC_TYPE_FC) 278 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_BASER); 279 else if (idev->port_info->config.fec_type == IONIC_PORT_FEC_TYPE_RS) 280 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_RS); 281 282 ethtool_link_ksettings_add_link_mode(ks, supported, FIBRE); 283 ethtool_link_ksettings_add_link_mode(ks, supported, Pause); 284 285 if (idev->port_info->status.xcvr.phy == IONIC_PHY_TYPE_COPPER || 286 copper_seen) 287 ks->base.port = PORT_DA; 288 else if (idev->port_info->status.xcvr.phy == IONIC_PHY_TYPE_FIBER) 289 ks->base.port = PORT_FIBRE; 290 else 291 ks->base.port = PORT_NONE; 292 293 if (ks->base.port != PORT_NONE) { 294 ks->base.speed = le32_to_cpu(lif->info->status.link_speed); 295 296 if (le16_to_cpu(lif->info->status.link_status)) 297 ks->base.duplex = DUPLEX_FULL; 298 else 299 ks->base.duplex = DUPLEX_UNKNOWN; 300 301 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg); 302 303 if (idev->port_info->config.an_enable) { 304 ethtool_link_ksettings_add_link_mode(ks, advertising, 305 Autoneg); 306 ks->base.autoneg = AUTONEG_ENABLE; 307 } 308 } 309 310 return 0; 311 } 312 313 static int ionic_set_link_ksettings(struct net_device *netdev, 314 const struct ethtool_link_ksettings *ks) 315 { 316 struct ionic_lif *lif = netdev_priv(netdev); 317 struct ionic_dev *idev = &lif->ionic->idev; 318 struct ionic *ionic = lif->ionic; 319 int err = 0; 320 321 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 322 return -EBUSY; 323 324 /* set autoneg */ 325 if (ks->base.autoneg != idev->port_info->config.an_enable) { 326 mutex_lock(&ionic->dev_cmd_lock); 327 ionic_dev_cmd_port_autoneg(idev, ks->base.autoneg); 328 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 329 mutex_unlock(&ionic->dev_cmd_lock); 330 if (err) 331 return err; 332 } 333 334 /* set speed */ 335 if (ks->base.speed != le32_to_cpu(idev->port_info->config.speed)) { 336 mutex_lock(&ionic->dev_cmd_lock); 337 ionic_dev_cmd_port_speed(idev, ks->base.speed); 338 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 339 mutex_unlock(&ionic->dev_cmd_lock); 340 if (err) 341 return err; 342 } 343 344 return 0; 345 } 346 347 static void ionic_get_pauseparam(struct net_device *netdev, 348 struct ethtool_pauseparam *pause) 349 { 350 struct ionic_lif *lif = netdev_priv(netdev); 351 u8 pause_type; 352 353 pause->autoneg = 0; 354 355 pause_type = lif->ionic->idev.port_info->config.pause_type; 356 if (pause_type) { 357 pause->rx_pause = (pause_type & IONIC_PAUSE_F_RX) ? 1 : 0; 358 pause->tx_pause = (pause_type & IONIC_PAUSE_F_TX) ? 1 : 0; 359 } 360 } 361 362 static int ionic_set_pauseparam(struct net_device *netdev, 363 struct ethtool_pauseparam *pause) 364 { 365 struct ionic_lif *lif = netdev_priv(netdev); 366 struct ionic *ionic = lif->ionic; 367 u32 requested_pause; 368 int err; 369 370 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 371 return -EBUSY; 372 373 if (pause->autoneg) 374 return -EOPNOTSUPP; 375 376 /* change both at the same time */ 377 requested_pause = IONIC_PORT_PAUSE_TYPE_LINK; 378 if (pause->rx_pause) 379 requested_pause |= IONIC_PAUSE_F_RX; 380 if (pause->tx_pause) 381 requested_pause |= IONIC_PAUSE_F_TX; 382 383 if (requested_pause == lif->ionic->idev.port_info->config.pause_type) 384 return 0; 385 386 mutex_lock(&ionic->dev_cmd_lock); 387 ionic_dev_cmd_port_pause(&lif->ionic->idev, requested_pause); 388 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 389 mutex_unlock(&ionic->dev_cmd_lock); 390 if (err) 391 return err; 392 393 return 0; 394 } 395 396 static int ionic_get_fecparam(struct net_device *netdev, 397 struct ethtool_fecparam *fec) 398 { 399 struct ionic_lif *lif = netdev_priv(netdev); 400 401 switch (lif->ionic->idev.port_info->config.fec_type) { 402 case IONIC_PORT_FEC_TYPE_NONE: 403 fec->active_fec = ETHTOOL_FEC_OFF; 404 break; 405 case IONIC_PORT_FEC_TYPE_RS: 406 fec->active_fec = ETHTOOL_FEC_RS; 407 break; 408 case IONIC_PORT_FEC_TYPE_FC: 409 fec->active_fec = ETHTOOL_FEC_BASER; 410 break; 411 } 412 413 fec->fec = ETHTOOL_FEC_OFF | ETHTOOL_FEC_RS | ETHTOOL_FEC_BASER; 414 415 return 0; 416 } 417 418 static int ionic_set_fecparam(struct net_device *netdev, 419 struct ethtool_fecparam *fec) 420 { 421 struct ionic_lif *lif = netdev_priv(netdev); 422 u8 fec_type; 423 int ret = 0; 424 425 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 426 return -EBUSY; 427 428 if (lif->ionic->idev.port_info->config.an_enable) { 429 netdev_err(netdev, "FEC request not allowed while autoneg is enabled\n"); 430 return -EINVAL; 431 } 432 433 switch (fec->fec) { 434 case ETHTOOL_FEC_NONE: 435 fec_type = IONIC_PORT_FEC_TYPE_NONE; 436 break; 437 case ETHTOOL_FEC_OFF: 438 fec_type = IONIC_PORT_FEC_TYPE_NONE; 439 break; 440 case ETHTOOL_FEC_RS: 441 fec_type = IONIC_PORT_FEC_TYPE_RS; 442 break; 443 case ETHTOOL_FEC_BASER: 444 fec_type = IONIC_PORT_FEC_TYPE_FC; 445 break; 446 case ETHTOOL_FEC_AUTO: 447 default: 448 netdev_err(netdev, "FEC request 0x%04x not supported\n", 449 fec->fec); 450 return -EINVAL; 451 } 452 453 if (fec_type != lif->ionic->idev.port_info->config.fec_type) { 454 mutex_lock(&lif->ionic->dev_cmd_lock); 455 ionic_dev_cmd_port_fec(&lif->ionic->idev, fec_type); 456 ret = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 457 mutex_unlock(&lif->ionic->dev_cmd_lock); 458 } 459 460 return ret; 461 } 462 463 static int ionic_get_coalesce(struct net_device *netdev, 464 struct ethtool_coalesce *coalesce, 465 struct kernel_ethtool_coalesce *kernel_coal, 466 struct netlink_ext_ack *extack) 467 { 468 struct ionic_lif *lif = netdev_priv(netdev); 469 470 coalesce->tx_coalesce_usecs = lif->tx_coalesce_usecs; 471 coalesce->rx_coalesce_usecs = lif->rx_coalesce_usecs; 472 473 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 474 coalesce->use_adaptive_tx_coalesce = test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 475 else 476 coalesce->use_adaptive_tx_coalesce = 0; 477 478 coalesce->use_adaptive_rx_coalesce = test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 479 480 return 0; 481 } 482 483 static int ionic_set_coalesce(struct net_device *netdev, 484 struct ethtool_coalesce *coalesce, 485 struct kernel_ethtool_coalesce *kernel_coal, 486 struct netlink_ext_ack *extack) 487 { 488 struct ionic_lif *lif = netdev_priv(netdev); 489 struct ionic_identity *ident; 490 u32 rx_coal, rx_dim; 491 u32 tx_coal, tx_dim; 492 unsigned int i; 493 494 ident = &lif->ionic->ident; 495 if (ident->dev.intr_coal_div == 0) { 496 netdev_warn(netdev, "bad HW value in dev.intr_coal_div = %d\n", 497 ident->dev.intr_coal_div); 498 return -EIO; 499 } 500 501 /* Tx normally shares Rx interrupt, so only change Rx if not split */ 502 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) && 503 (coalesce->tx_coalesce_usecs != lif->rx_coalesce_usecs || 504 coalesce->use_adaptive_tx_coalesce)) { 505 netdev_warn(netdev, "only rx parameters can be changed\n"); 506 return -EINVAL; 507 } 508 509 /* Convert the usec request to a HW usable value. If they asked 510 * for non-zero and it resolved to zero, bump it up 511 */ 512 rx_coal = ionic_coal_usec_to_hw(lif->ionic, coalesce->rx_coalesce_usecs); 513 if (!rx_coal && coalesce->rx_coalesce_usecs) 514 rx_coal = 1; 515 tx_coal = ionic_coal_usec_to_hw(lif->ionic, coalesce->tx_coalesce_usecs); 516 if (!tx_coal && coalesce->tx_coalesce_usecs) 517 tx_coal = 1; 518 519 if (rx_coal > IONIC_INTR_CTRL_COAL_MAX || 520 tx_coal > IONIC_INTR_CTRL_COAL_MAX) 521 return -ERANGE; 522 523 /* Save the new values */ 524 lif->rx_coalesce_usecs = coalesce->rx_coalesce_usecs; 525 lif->rx_coalesce_hw = rx_coal; 526 527 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 528 lif->tx_coalesce_usecs = coalesce->tx_coalesce_usecs; 529 else 530 lif->tx_coalesce_usecs = coalesce->rx_coalesce_usecs; 531 lif->tx_coalesce_hw = tx_coal; 532 533 if (coalesce->use_adaptive_rx_coalesce) { 534 set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 535 rx_dim = rx_coal; 536 } else { 537 clear_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 538 rx_dim = 0; 539 } 540 541 if (coalesce->use_adaptive_tx_coalesce) { 542 set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 543 tx_dim = tx_coal; 544 } else { 545 clear_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 546 tx_dim = 0; 547 } 548 549 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 550 for (i = 0; i < lif->nxqs; i++) { 551 if (lif->rxqcqs[i]->flags & IONIC_QCQ_F_INTR) { 552 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 553 lif->rxqcqs[i]->intr.index, 554 lif->rx_coalesce_hw); 555 lif->rxqcqs[i]->intr.dim_coal_hw = rx_dim; 556 } 557 558 if (lif->txqcqs[i]->flags & IONIC_QCQ_F_INTR) { 559 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 560 lif->txqcqs[i]->intr.index, 561 lif->tx_coalesce_hw); 562 lif->txqcqs[i]->intr.dim_coal_hw = tx_dim; 563 } 564 } 565 } 566 567 return 0; 568 } 569 570 static int ionic_validate_cmb_config(struct ionic_lif *lif, 571 struct ionic_queue_params *qparam) 572 { 573 int pages_have, pages_required = 0; 574 unsigned long sz; 575 576 if (!lif->ionic->idev.cmb_inuse && 577 (qparam->cmb_tx || qparam->cmb_rx)) { 578 netdev_info(lif->netdev, "CMB rings are not supported on this device\n"); 579 return -EOPNOTSUPP; 580 } 581 582 if (qparam->cmb_tx) { 583 if (!(lif->qtype_info[IONIC_QTYPE_TXQ].features & IONIC_QIDENT_F_CMB)) { 584 netdev_info(lif->netdev, 585 "CMB rings for tx-push are not supported on this device\n"); 586 return -EOPNOTSUPP; 587 } 588 589 sz = sizeof(struct ionic_txq_desc) * qparam->ntxq_descs * qparam->nxqs; 590 pages_required += ALIGN(sz, PAGE_SIZE) / PAGE_SIZE; 591 } 592 593 if (qparam->cmb_rx) { 594 if (!(lif->qtype_info[IONIC_QTYPE_RXQ].features & IONIC_QIDENT_F_CMB)) { 595 netdev_info(lif->netdev, 596 "CMB rings for rx-push are not supported on this device\n"); 597 return -EOPNOTSUPP; 598 } 599 600 sz = sizeof(struct ionic_rxq_desc) * qparam->nrxq_descs * qparam->nxqs; 601 pages_required += ALIGN(sz, PAGE_SIZE) / PAGE_SIZE; 602 } 603 604 pages_have = lif->ionic->bars[IONIC_PCI_BAR_CMB].len / PAGE_SIZE; 605 if (pages_required > pages_have) { 606 netdev_info(lif->netdev, 607 "Not enough CMB pages for number of queues and size of descriptor rings, need %d have %d", 608 pages_required, pages_have); 609 return -ENOMEM; 610 } 611 612 return pages_required; 613 } 614 615 static int ionic_cmb_rings_toggle(struct ionic_lif *lif, bool cmb_tx, bool cmb_rx) 616 { 617 struct ionic_queue_params qparam; 618 int pages_used; 619 620 if (netif_running(lif->netdev)) { 621 netdev_info(lif->netdev, "Please stop device to toggle CMB for tx/rx-push\n"); 622 return -EBUSY; 623 } 624 625 ionic_init_queue_params(lif, &qparam); 626 qparam.cmb_tx = cmb_tx; 627 qparam.cmb_rx = cmb_rx; 628 pages_used = ionic_validate_cmb_config(lif, &qparam); 629 if (pages_used < 0) 630 return pages_used; 631 632 if (cmb_tx) 633 set_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state); 634 else 635 clear_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state); 636 637 if (cmb_rx) 638 set_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state); 639 else 640 clear_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state); 641 642 if (cmb_tx || cmb_rx) 643 netdev_info(lif->netdev, "Enabling CMB %s %s rings - %d pages\n", 644 cmb_tx ? "TX" : "", cmb_rx ? "RX" : "", pages_used); 645 else 646 netdev_info(lif->netdev, "Disabling CMB rings\n"); 647 648 return 0; 649 } 650 651 static void ionic_get_ringparam(struct net_device *netdev, 652 struct ethtool_ringparam *ring, 653 struct kernel_ethtool_ringparam *kernel_ring, 654 struct netlink_ext_ack *extack) 655 { 656 struct ionic_lif *lif = netdev_priv(netdev); 657 658 ring->tx_max_pending = IONIC_MAX_TX_DESC; 659 ring->tx_pending = lif->ntxq_descs; 660 ring->rx_max_pending = IONIC_MAX_RX_DESC; 661 ring->rx_pending = lif->nrxq_descs; 662 kernel_ring->tx_push = test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state); 663 kernel_ring->rx_push = test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state); 664 } 665 666 static int ionic_set_ringparam(struct net_device *netdev, 667 struct ethtool_ringparam *ring, 668 struct kernel_ethtool_ringparam *kernel_ring, 669 struct netlink_ext_ack *extack) 670 { 671 struct ionic_lif *lif = netdev_priv(netdev); 672 struct ionic_queue_params qparam; 673 int err; 674 675 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 676 return -EBUSY; 677 678 ionic_init_queue_params(lif, &qparam); 679 680 if (ring->rx_mini_pending || ring->rx_jumbo_pending) { 681 netdev_info(netdev, "Changing jumbo or mini descriptors not supported\n"); 682 return -EINVAL; 683 } 684 685 if (!is_power_of_2(ring->tx_pending) || 686 !is_power_of_2(ring->rx_pending)) { 687 netdev_info(netdev, "Descriptor count must be a power of 2\n"); 688 return -EINVAL; 689 } 690 691 /* if nothing to do return success */ 692 if (ring->tx_pending == lif->ntxq_descs && 693 ring->rx_pending == lif->nrxq_descs && 694 kernel_ring->tx_push == test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state) && 695 kernel_ring->rx_push == test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state)) 696 return 0; 697 698 qparam.ntxq_descs = ring->tx_pending; 699 qparam.nrxq_descs = ring->rx_pending; 700 qparam.cmb_tx = kernel_ring->tx_push; 701 qparam.cmb_rx = kernel_ring->rx_push; 702 703 err = ionic_validate_cmb_config(lif, &qparam); 704 if (err < 0) 705 return err; 706 707 if (kernel_ring->tx_push != test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state) || 708 kernel_ring->rx_push != test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state)) { 709 err = ionic_cmb_rings_toggle(lif, kernel_ring->tx_push, 710 kernel_ring->rx_push); 711 if (err < 0) 712 return err; 713 } 714 715 if (ring->tx_pending != lif->ntxq_descs) 716 netdev_info(netdev, "Changing Tx ring size from %d to %d\n", 717 lif->ntxq_descs, ring->tx_pending); 718 719 if (ring->rx_pending != lif->nrxq_descs) 720 netdev_info(netdev, "Changing Rx ring size from %d to %d\n", 721 lif->nrxq_descs, ring->rx_pending); 722 723 /* if we're not running, just set the values and return */ 724 if (!netif_running(lif->netdev)) { 725 lif->ntxq_descs = ring->tx_pending; 726 lif->nrxq_descs = ring->rx_pending; 727 return 0; 728 } 729 730 mutex_lock(&lif->queue_lock); 731 err = ionic_reconfigure_queues(lif, &qparam); 732 mutex_unlock(&lif->queue_lock); 733 if (err) 734 netdev_info(netdev, "Ring reconfiguration failed, changes canceled: %d\n", err); 735 736 return err; 737 } 738 739 static void ionic_get_channels(struct net_device *netdev, 740 struct ethtool_channels *ch) 741 { 742 struct ionic_lif *lif = netdev_priv(netdev); 743 744 /* report maximum channels */ 745 ch->max_combined = lif->ionic->ntxqs_per_lif; 746 ch->max_rx = lif->ionic->ntxqs_per_lif / 2; 747 ch->max_tx = lif->ionic->ntxqs_per_lif / 2; 748 749 /* report current channels */ 750 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) { 751 ch->rx_count = lif->nxqs; 752 ch->tx_count = lif->nxqs; 753 } else { 754 ch->combined_count = lif->nxqs; 755 } 756 } 757 758 static int ionic_set_channels(struct net_device *netdev, 759 struct ethtool_channels *ch) 760 { 761 struct ionic_lif *lif = netdev_priv(netdev); 762 struct ionic_queue_params qparam; 763 int max_cnt; 764 int err; 765 766 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 767 return -EBUSY; 768 769 ionic_init_queue_params(lif, &qparam); 770 771 if ((ch->rx_count || ch->tx_count) && lif->xdp_prog) { 772 netdev_info(lif->netdev, "Split Tx/Rx interrupts not available when using XDP\n"); 773 return -EOPNOTSUPP; 774 } 775 776 if (ch->rx_count != ch->tx_count) { 777 netdev_info(netdev, "The rx and tx count must be equal\n"); 778 return -EINVAL; 779 } 780 781 if (ch->combined_count && ch->rx_count) { 782 netdev_info(netdev, "Use either combined or rx and tx, not both\n"); 783 return -EINVAL; 784 } 785 786 max_cnt = lif->ionic->ntxqs_per_lif; 787 if (ch->combined_count) { 788 if (ch->combined_count > max_cnt) 789 return -EINVAL; 790 791 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 792 netdev_info(lif->netdev, "Sharing queue interrupts\n"); 793 else if (ch->combined_count == lif->nxqs) 794 return 0; 795 796 if (lif->nxqs != ch->combined_count) 797 netdev_info(netdev, "Changing queue count from %d to %d\n", 798 lif->nxqs, ch->combined_count); 799 800 qparam.nxqs = ch->combined_count; 801 qparam.intr_split = false; 802 } else { 803 max_cnt /= 2; 804 if (ch->rx_count > max_cnt) 805 return -EINVAL; 806 807 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 808 netdev_info(lif->netdev, "Splitting queue interrupts\n"); 809 else if (ch->rx_count == lif->nxqs) 810 return 0; 811 812 if (lif->nxqs != ch->rx_count) 813 netdev_info(netdev, "Changing queue count from %d to %d\n", 814 lif->nxqs, ch->rx_count); 815 816 qparam.nxqs = ch->rx_count; 817 qparam.intr_split = true; 818 } 819 820 err = ionic_validate_cmb_config(lif, &qparam); 821 if (err < 0) 822 return err; 823 824 /* if we're not running, just set the values and return */ 825 if (!netif_running(lif->netdev)) { 826 lif->nxqs = qparam.nxqs; 827 828 if (qparam.intr_split) { 829 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 830 } else { 831 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 832 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 833 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 834 } 835 return 0; 836 } 837 838 mutex_lock(&lif->queue_lock); 839 err = ionic_reconfigure_queues(lif, &qparam); 840 mutex_unlock(&lif->queue_lock); 841 if (err) 842 netdev_info(netdev, "Queue reconfiguration failed, changes canceled: %d\n", err); 843 844 return err; 845 } 846 847 static u32 ionic_get_rx_ring_count(struct net_device *netdev) 848 { 849 struct ionic_lif *lif = netdev_priv(netdev); 850 851 return lif->nxqs; 852 } 853 854 static u32 ionic_get_rxfh_indir_size(struct net_device *netdev) 855 { 856 struct ionic_lif *lif = netdev_priv(netdev); 857 858 return le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 859 } 860 861 static u32 ionic_get_rxfh_key_size(struct net_device *netdev) 862 { 863 return IONIC_RSS_HASH_KEY_SIZE; 864 } 865 866 static int ionic_get_rxfh(struct net_device *netdev, 867 struct ethtool_rxfh_param *rxfh) 868 { 869 struct ionic_lif *lif = netdev_priv(netdev); 870 unsigned int i, tbl_sz; 871 872 if (rxfh->indir) { 873 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 874 for (i = 0; i < tbl_sz; i++) 875 rxfh->indir[i] = lif->rss_ind_tbl[i]; 876 } 877 878 if (rxfh->key) 879 memcpy(rxfh->key, lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE); 880 881 rxfh->hfunc = ETH_RSS_HASH_TOP; 882 883 return 0; 884 } 885 886 static int ionic_set_rxfh(struct net_device *netdev, 887 struct ethtool_rxfh_param *rxfh, 888 struct netlink_ext_ack *extack) 889 { 890 struct ionic_lif *lif = netdev_priv(netdev); 891 892 if (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE && 893 rxfh->hfunc != ETH_RSS_HASH_TOP) 894 return -EOPNOTSUPP; 895 896 return ionic_lif_rss_config(lif, lif->rss_types, 897 rxfh->key, rxfh->indir); 898 } 899 900 static int ionic_set_tunable(struct net_device *dev, 901 const struct ethtool_tunable *tuna, 902 const void *data) 903 { 904 struct ionic_lif *lif = netdev_priv(dev); 905 u32 rx_copybreak; 906 907 switch (tuna->id) { 908 case ETHTOOL_RX_COPYBREAK: 909 rx_copybreak = *(u32 *)data; 910 if (rx_copybreak > IONIC_MAX_RX_COPYBREAK) { 911 netdev_err(dev, "Max supported rx_copybreak size: %u\n", 912 IONIC_MAX_RX_COPYBREAK); 913 return -EINVAL; 914 } 915 lif->rx_copybreak = (u16)rx_copybreak; 916 break; 917 default: 918 return -EOPNOTSUPP; 919 } 920 921 return 0; 922 } 923 924 static int ionic_get_tunable(struct net_device *netdev, 925 const struct ethtool_tunable *tuna, void *data) 926 { 927 struct ionic_lif *lif = netdev_priv(netdev); 928 929 switch (tuna->id) { 930 case ETHTOOL_RX_COPYBREAK: 931 *(u32 *)data = lif->rx_copybreak; 932 break; 933 default: 934 return -EOPNOTSUPP; 935 } 936 937 return 0; 938 } 939 940 static int ionic_do_module_copy(u8 *dst, u8 *src, u32 len) 941 { 942 char tbuf[sizeof_field(struct ionic_xcvr_status, sprom)]; 943 int count = 10; 944 945 /* The NIC keeps the module prom up-to-date in the DMA space 946 * so we can simply copy the module bytes into the data buffer. 947 */ 948 do { 949 memcpy(dst, src, len); 950 memcpy(tbuf, src, len); 951 952 /* Let's make sure we got a consistent copy */ 953 if (!memcmp(dst, tbuf, len)) 954 break; 955 956 } while (--count); 957 958 if (!count) 959 return -ETIMEDOUT; 960 961 return 0; 962 } 963 964 static int ionic_get_module_eeprom_by_page(struct net_device *netdev, 965 const struct ethtool_module_eeprom *page_data, 966 struct netlink_ext_ack *extack) 967 { 968 struct ionic_lif *lif = netdev_priv(netdev); 969 struct ionic_dev *idev = &lif->ionic->idev; 970 int err; 971 u8 *src; 972 973 if (!page_data->length) 974 return -EINVAL; 975 976 if (page_data->bank != 0) { 977 NL_SET_ERR_MSG_MOD(extack, "Only bank 0 is supported"); 978 return -EINVAL; 979 } 980 981 switch (page_data->page) { 982 case 0: 983 src = &idev->port_info->status.xcvr.sprom[page_data->offset]; 984 break; 985 case 1: 986 src = &idev->port_info->sprom_page1[page_data->offset - 128]; 987 break; 988 case 2: 989 src = &idev->port_info->sprom_page2[page_data->offset - 128]; 990 break; 991 case 17: 992 src = &idev->port_info->sprom_page17[page_data->offset - 128]; 993 break; 994 default: 995 return -EOPNOTSUPP; 996 } 997 998 memset(page_data->data, 0, page_data->length); 999 err = ionic_do_module_copy(page_data->data, src, page_data->length); 1000 if (err) 1001 return err; 1002 1003 return page_data->length; 1004 } 1005 1006 static int ionic_get_ts_info(struct net_device *netdev, 1007 struct kernel_ethtool_ts_info *info) 1008 { 1009 struct ionic_lif *lif = netdev_priv(netdev); 1010 struct ionic *ionic = lif->ionic; 1011 __le64 mask; 1012 1013 if (!lif->phc || !lif->phc->ptp) 1014 return ethtool_op_get_ts_info(netdev, info); 1015 1016 info->phc_index = ptp_clock_index(lif->phc->ptp); 1017 1018 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1019 SOF_TIMESTAMPING_TX_HARDWARE | 1020 SOF_TIMESTAMPING_RX_HARDWARE | 1021 SOF_TIMESTAMPING_RAW_HARDWARE; 1022 1023 /* tx modes */ 1024 1025 info->tx_types = BIT(HWTSTAMP_TX_OFF) | 1026 BIT(HWTSTAMP_TX_ON); 1027 1028 mask = cpu_to_le64(BIT_ULL(IONIC_TXSTAMP_ONESTEP_SYNC)); 1029 if (ionic->ident.lif.eth.hwstamp_tx_modes & mask) 1030 info->tx_types |= BIT(HWTSTAMP_TX_ONESTEP_SYNC); 1031 1032 mask = cpu_to_le64(BIT_ULL(IONIC_TXSTAMP_ONESTEP_P2P)); 1033 if (ionic->ident.lif.eth.hwstamp_tx_modes & mask) 1034 info->tx_types |= BIT(HWTSTAMP_TX_ONESTEP_P2P); 1035 1036 /* rx filters */ 1037 1038 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 1039 BIT(HWTSTAMP_FILTER_ALL); 1040 1041 mask = cpu_to_le64(IONIC_PKT_CLS_NTP_ALL); 1042 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1043 info->rx_filters |= BIT(HWTSTAMP_FILTER_NTP_ALL); 1044 1045 mask = cpu_to_le64(IONIC_PKT_CLS_PTP1_SYNC); 1046 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1047 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC); 1048 1049 mask = cpu_to_le64(IONIC_PKT_CLS_PTP1_DREQ); 1050 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1051 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ); 1052 1053 mask = cpu_to_le64(IONIC_PKT_CLS_PTP1_ALL); 1054 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1055 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_EVENT); 1056 1057 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L4_SYNC); 1058 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1059 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC); 1060 1061 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L4_DREQ); 1062 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1063 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ); 1064 1065 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L4_ALL); 1066 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1067 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 1068 1069 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L2_SYNC); 1070 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1071 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC); 1072 1073 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L2_DREQ); 1074 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1075 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ); 1076 1077 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L2_ALL); 1078 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1079 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT); 1080 1081 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_SYNC); 1082 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1083 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_SYNC); 1084 1085 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_DREQ); 1086 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1087 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ); 1088 1089 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_ALL); 1090 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1091 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_EVENT); 1092 1093 return 0; 1094 } 1095 1096 static int ionic_nway_reset(struct net_device *netdev) 1097 { 1098 struct ionic_lif *lif = netdev_priv(netdev); 1099 struct ionic *ionic = lif->ionic; 1100 int err = 0; 1101 1102 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 1103 return -EBUSY; 1104 1105 /* flap the link to force auto-negotiation */ 1106 1107 mutex_lock(&ionic->dev_cmd_lock); 1108 1109 ionic_dev_cmd_port_state(&ionic->idev, IONIC_PORT_ADMIN_STATE_DOWN); 1110 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 1111 1112 if (!err) { 1113 ionic_dev_cmd_port_state(&ionic->idev, IONIC_PORT_ADMIN_STATE_UP); 1114 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 1115 } 1116 1117 mutex_unlock(&ionic->dev_cmd_lock); 1118 1119 return err; 1120 } 1121 1122 static const struct ethtool_ops ionic_ethtool_ops = { 1123 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1124 ETHTOOL_COALESCE_USE_ADAPTIVE_RX | 1125 ETHTOOL_COALESCE_USE_ADAPTIVE_TX, 1126 .supported_ring_params = ETHTOOL_RING_USE_TX_PUSH | 1127 ETHTOOL_RING_USE_RX_PUSH, 1128 .get_drvinfo = ionic_get_drvinfo, 1129 .get_regs_len = ionic_get_regs_len, 1130 .get_regs = ionic_get_regs, 1131 .get_link = ethtool_op_get_link, 1132 .get_link_ext_stats = ionic_get_link_ext_stats, 1133 .get_link_ksettings = ionic_get_link_ksettings, 1134 .set_link_ksettings = ionic_set_link_ksettings, 1135 .get_coalesce = ionic_get_coalesce, 1136 .set_coalesce = ionic_set_coalesce, 1137 .get_ringparam = ionic_get_ringparam, 1138 .set_ringparam = ionic_set_ringparam, 1139 .get_channels = ionic_get_channels, 1140 .set_channels = ionic_set_channels, 1141 .get_strings = ionic_get_strings, 1142 .get_ethtool_stats = ionic_get_stats, 1143 .get_sset_count = ionic_get_sset_count, 1144 .get_rx_ring_count = ionic_get_rx_ring_count, 1145 .get_rxfh_indir_size = ionic_get_rxfh_indir_size, 1146 .get_rxfh_key_size = ionic_get_rxfh_key_size, 1147 .get_rxfh = ionic_get_rxfh, 1148 .set_rxfh = ionic_set_rxfh, 1149 .get_tunable = ionic_get_tunable, 1150 .set_tunable = ionic_set_tunable, 1151 .get_module_eeprom_by_page = ionic_get_module_eeprom_by_page, 1152 .get_pauseparam = ionic_get_pauseparam, 1153 .set_pauseparam = ionic_set_pauseparam, 1154 .get_fecparam = ionic_get_fecparam, 1155 .set_fecparam = ionic_set_fecparam, 1156 .get_ts_info = ionic_get_ts_info, 1157 .nway_reset = ionic_nway_reset, 1158 }; 1159 1160 void ionic_ethtool_set_ops(struct net_device *netdev) 1161 { 1162 netdev->ethtool_ops = &ionic_ethtool_ops; 1163 } 1164