1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #ifndef _IONIC_DEV_H_ 5 #define _IONIC_DEV_H_ 6 7 #include <linux/atomic.h> 8 #include <linux/mutex.h> 9 #include <linux/workqueue.h> 10 #include <linux/skbuff.h> 11 #include <linux/bpf_trace.h> 12 13 #include "ionic_if.h" 14 #include "ionic_regs.h" 15 16 #define IONIC_MAX_TX_DESC 8192 17 #define IONIC_MAX_RX_DESC 16384 18 #define IONIC_MIN_TXRX_DESC 64 19 #define IONIC_DEF_TXRX_DESC 1024 20 #define IONIC_RX_FILL_THRESHOLD 16 21 #define IONIC_RX_FILL_DIV 8 22 #define IONIC_TSO_DESCS_NEEDED 44 /* 64K TSO @1500B */ 23 #define IONIC_LIFS_MAX 1024 24 #define IONIC_WATCHDOG_SECS 5 25 #define IONIC_ITR_COAL_USEC_DEFAULT 64 26 27 #define IONIC_DEV_CMD_REG_VERSION 1 28 #define IONIC_DEV_INFO_REG_COUNT 32 29 #define IONIC_DEV_CMD_REG_COUNT 32 30 31 #define IONIC_NAPI_DEADLINE (HZ / 200) /* 5ms */ 32 #define IONIC_ADMIN_DOORBELL_DEADLINE (HZ / 2) /* 500ms */ 33 #define IONIC_TX_DOORBELL_DEADLINE (HZ / 100) /* 10ms */ 34 #define IONIC_RX_MIN_DOORBELL_DEADLINE (HZ / 100) /* 10ms */ 35 #define IONIC_RX_MAX_DOORBELL_DEADLINE (HZ * 5) /* 5s */ 36 37 struct ionic_dev_bar { 38 void __iomem *vaddr; 39 phys_addr_t bus_addr; 40 unsigned long len; 41 int res_index; 42 }; 43 44 #ifndef __CHECKER__ 45 /* Registers */ 46 static_assert(sizeof(struct ionic_intr) == 32); 47 48 static_assert(sizeof(struct ionic_doorbell) == 8); 49 static_assert(sizeof(struct ionic_intr_status) == 8); 50 static_assert(sizeof(union ionic_dev_regs) == 4096); 51 static_assert(sizeof(union ionic_dev_info_regs) == 2048); 52 static_assert(sizeof(union ionic_dev_cmd_regs) == 2048); 53 static_assert(sizeof(struct ionic_lif_stats) == 1024); 54 55 static_assert(sizeof(struct ionic_admin_cmd) == 64); 56 static_assert(sizeof(struct ionic_admin_comp) == 16); 57 static_assert(sizeof(struct ionic_nop_cmd) == 64); 58 static_assert(sizeof(struct ionic_nop_comp) == 16); 59 60 /* Device commands */ 61 static_assert(sizeof(struct ionic_dev_identify_cmd) == 64); 62 static_assert(sizeof(struct ionic_dev_identify_comp) == 16); 63 static_assert(sizeof(struct ionic_dev_init_cmd) == 64); 64 static_assert(sizeof(struct ionic_dev_init_comp) == 16); 65 static_assert(sizeof(struct ionic_dev_reset_cmd) == 64); 66 static_assert(sizeof(struct ionic_dev_reset_comp) == 16); 67 static_assert(sizeof(struct ionic_dev_getattr_cmd) == 64); 68 static_assert(sizeof(struct ionic_dev_getattr_comp) == 16); 69 static_assert(sizeof(struct ionic_dev_setattr_cmd) == 64); 70 static_assert(sizeof(struct ionic_dev_setattr_comp) == 16); 71 static_assert(sizeof(struct ionic_lif_setphc_cmd) == 64); 72 73 /* Port commands */ 74 static_assert(sizeof(struct ionic_port_identify_cmd) == 64); 75 static_assert(sizeof(struct ionic_port_identify_comp) == 16); 76 static_assert(sizeof(struct ionic_port_init_cmd) == 64); 77 static_assert(sizeof(struct ionic_port_init_comp) == 16); 78 static_assert(sizeof(struct ionic_port_reset_cmd) == 64); 79 static_assert(sizeof(struct ionic_port_reset_comp) == 16); 80 static_assert(sizeof(struct ionic_port_getattr_cmd) == 64); 81 static_assert(sizeof(struct ionic_port_getattr_comp) == 16); 82 static_assert(sizeof(struct ionic_port_setattr_cmd) == 64); 83 static_assert(sizeof(struct ionic_port_setattr_comp) == 16); 84 85 /* LIF commands */ 86 static_assert(sizeof(struct ionic_lif_init_cmd) == 64); 87 static_assert(sizeof(struct ionic_lif_init_comp) == 16); 88 static_assert(sizeof(struct ionic_lif_reset_cmd) == 64); 89 static_assert(sizeof(ionic_lif_reset_comp) == 16); 90 static_assert(sizeof(struct ionic_lif_getattr_cmd) == 64); 91 static_assert(sizeof(struct ionic_lif_getattr_comp) == 16); 92 static_assert(sizeof(struct ionic_lif_setattr_cmd) == 64); 93 static_assert(sizeof(struct ionic_lif_setattr_comp) == 16); 94 95 static_assert(sizeof(struct ionic_q_init_cmd) == 64); 96 static_assert(sizeof(struct ionic_q_init_comp) == 16); 97 static_assert(sizeof(struct ionic_q_control_cmd) == 64); 98 static_assert(sizeof(ionic_q_control_comp) == 16); 99 static_assert(sizeof(struct ionic_q_identify_cmd) == 64); 100 static_assert(sizeof(struct ionic_q_identify_comp) == 16); 101 102 static_assert(sizeof(struct ionic_rx_mode_set_cmd) == 64); 103 static_assert(sizeof(ionic_rx_mode_set_comp) == 16); 104 static_assert(sizeof(struct ionic_rx_filter_add_cmd) == 64); 105 static_assert(sizeof(struct ionic_rx_filter_add_comp) == 16); 106 static_assert(sizeof(struct ionic_rx_filter_del_cmd) == 64); 107 static_assert(sizeof(ionic_rx_filter_del_comp) == 16); 108 109 /* RDMA commands */ 110 static_assert(sizeof(struct ionic_rdma_reset_cmd) == 64); 111 static_assert(sizeof(struct ionic_rdma_queue_cmd) == 64); 112 113 /* Events */ 114 static_assert(sizeof(struct ionic_notifyq_cmd) == 4); 115 static_assert(sizeof(union ionic_notifyq_comp) == 64); 116 static_assert(sizeof(struct ionic_notifyq_event) == 64); 117 static_assert(sizeof(struct ionic_link_change_event) == 64); 118 static_assert(sizeof(struct ionic_reset_event) == 64); 119 static_assert(sizeof(struct ionic_heartbeat_event) == 64); 120 static_assert(sizeof(struct ionic_log_event) == 64); 121 122 /* I/O */ 123 static_assert(sizeof(struct ionic_txq_desc) == 16); 124 static_assert(sizeof(struct ionic_txq_sg_desc) == 128); 125 static_assert(sizeof(struct ionic_txq_comp) == 16); 126 127 static_assert(sizeof(struct ionic_rxq_desc) == 16); 128 static_assert(sizeof(struct ionic_rxq_sg_desc) == 128); 129 static_assert(sizeof(struct ionic_rxq_comp) == 16); 130 131 /* SR/IOV */ 132 static_assert(sizeof(struct ionic_vf_setattr_cmd) == 64); 133 static_assert(sizeof(struct ionic_vf_setattr_comp) == 16); 134 static_assert(sizeof(struct ionic_vf_getattr_cmd) == 64); 135 static_assert(sizeof(struct ionic_vf_getattr_comp) == 16); 136 static_assert(sizeof(struct ionic_vf_ctrl_cmd) == 64); 137 static_assert(sizeof(struct ionic_vf_ctrl_comp) == 16); 138 #endif /* __CHECKER__ */ 139 140 struct ionic_devinfo { 141 u8 asic_type; 142 u8 asic_rev; 143 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN + 1]; 144 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN + 1]; 145 }; 146 147 struct ionic_dev { 148 union ionic_dev_info_regs __iomem *dev_info_regs; 149 union ionic_dev_cmd_regs __iomem *dev_cmd_regs; 150 struct ionic_hwstamp_regs __iomem *hwstamp_regs; 151 152 atomic_long_t last_check_time; 153 unsigned long last_hb_time; 154 u32 last_fw_hb; 155 bool fw_hb_ready; 156 bool fw_status_ready; 157 u8 fw_generation; 158 u8 opcode; 159 160 u64 __iomem *db_pages; 161 dma_addr_t phy_db_pages; 162 163 struct ionic_intr __iomem *intr_ctrl; 164 u64 __iomem *intr_status; 165 166 struct mutex cmb_inuse_lock; /* for cmb_inuse */ 167 unsigned long *cmb_inuse; 168 dma_addr_t phy_cmb_pages; 169 u32 cmb_npages; 170 171 u32 port_info_sz; 172 struct ionic_port_info *port_info; 173 dma_addr_t port_info_pa; 174 175 struct ionic_devinfo dev_info; 176 }; 177 178 struct ionic_cq_info { 179 union { 180 void *cq_desc; 181 struct ionic_admin_comp *admincq; 182 struct ionic_notifyq_event *notifyq; 183 }; 184 }; 185 186 struct ionic_queue; 187 struct ionic_qcq; 188 struct ionic_desc_info; 189 190 typedef void (*ionic_desc_cb)(struct ionic_queue *q, 191 struct ionic_desc_info *desc_info, 192 struct ionic_cq_info *cq_info, void *cb_arg); 193 194 #define IONIC_MAX_BUF_LEN ((u16)-1) 195 #define IONIC_PAGE_SIZE PAGE_SIZE 196 #define IONIC_PAGE_SPLIT_SZ (PAGE_SIZE / 2) 197 #define IONIC_PAGE_GFP_MASK (GFP_ATOMIC | __GFP_NOWARN |\ 198 __GFP_COMP | __GFP_MEMALLOC) 199 200 #define IONIC_XDP_MAX_LINEAR_MTU (IONIC_PAGE_SIZE - \ 201 (VLAN_ETH_HLEN + \ 202 XDP_PACKET_HEADROOM + \ 203 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))) 204 205 struct ionic_buf_info { 206 struct page *page; 207 dma_addr_t dma_addr; 208 u32 page_offset; 209 u32 len; 210 }; 211 212 #define IONIC_MAX_FRAGS (1 + IONIC_TX_MAX_SG_ELEMS_V1) 213 214 struct ionic_desc_info { 215 union { 216 void *desc; 217 struct ionic_txq_desc *txq_desc; 218 struct ionic_rxq_desc *rxq_desc; 219 struct ionic_admin_cmd *adminq_desc; 220 }; 221 void __iomem *cmb_desc; 222 union { 223 void *sg_desc; 224 struct ionic_txq_sg_desc *txq_sg_desc; 225 struct ionic_rxq_sg_desc *rxq_sgl_desc; 226 }; 227 unsigned int bytes; 228 unsigned int nbufs; 229 struct ionic_buf_info bufs[MAX_SKB_FRAGS + 1]; 230 ionic_desc_cb cb; 231 void *cb_arg; 232 struct xdp_frame *xdpf; 233 enum xdp_action act; 234 }; 235 236 #define IONIC_QUEUE_NAME_MAX_SZ 16 237 238 struct ionic_queue { 239 struct device *dev; 240 struct ionic_lif *lif; 241 struct ionic_desc_info *info; 242 u64 dbval; 243 unsigned long dbell_deadline; 244 unsigned long dbell_jiffies; 245 u16 head_idx; 246 u16 tail_idx; 247 unsigned int index; 248 unsigned int num_descs; 249 unsigned int max_sg_elems; 250 u64 features; 251 u64 drop; 252 struct ionic_dev *idev; 253 unsigned int type; 254 unsigned int hw_index; 255 unsigned int hw_type; 256 union { 257 void *base; 258 struct ionic_txq_desc *txq; 259 struct ionic_rxq_desc *rxq; 260 struct ionic_admin_cmd *adminq; 261 }; 262 void __iomem *cmb_base; 263 union { 264 void *sg_base; 265 struct ionic_txq_sg_desc *txq_sgl; 266 struct ionic_rxq_sg_desc *rxq_sgl; 267 }; 268 struct xdp_rxq_info *xdp_rxq_info; 269 struct ionic_queue *partner; 270 bool xdp_flush; 271 dma_addr_t base_pa; 272 dma_addr_t cmb_base_pa; 273 dma_addr_t sg_base_pa; 274 unsigned int desc_size; 275 unsigned int sg_desc_size; 276 unsigned int pid; 277 char name[IONIC_QUEUE_NAME_MAX_SZ]; 278 } ____cacheline_aligned_in_smp; 279 280 #define IONIC_INTR_INDEX_NOT_ASSIGNED -1 281 #define IONIC_INTR_NAME_MAX_SZ 32 282 283 struct ionic_intr_info { 284 char name[IONIC_INTR_NAME_MAX_SZ]; 285 u64 rearm_count; 286 unsigned int index; 287 unsigned int vector; 288 unsigned int cpu; 289 u32 dim_coal_hw; 290 cpumask_t affinity_mask; 291 }; 292 293 struct ionic_cq { 294 struct ionic_lif *lif; 295 struct ionic_cq_info *info; 296 struct ionic_queue *bound_q; 297 struct ionic_intr_info *bound_intr; 298 u16 tail_idx; 299 bool done_color; 300 unsigned int num_descs; 301 unsigned int desc_size; 302 void *base; 303 dma_addr_t base_pa; 304 } ____cacheline_aligned_in_smp; 305 306 struct ionic; 307 308 static inline void ionic_intr_init(struct ionic_dev *idev, 309 struct ionic_intr_info *intr, 310 unsigned long index) 311 { 312 ionic_intr_clean(idev->intr_ctrl, index); 313 intr->index = index; 314 } 315 316 static inline unsigned int ionic_q_space_avail(struct ionic_queue *q) 317 { 318 unsigned int avail = q->tail_idx; 319 320 if (q->head_idx >= avail) 321 avail += q->num_descs - q->head_idx - 1; 322 else 323 avail -= q->head_idx + 1; 324 325 return avail; 326 } 327 328 static inline bool ionic_q_has_space(struct ionic_queue *q, unsigned int want) 329 { 330 return ionic_q_space_avail(q) >= want; 331 } 332 333 void ionic_init_devinfo(struct ionic *ionic); 334 int ionic_dev_setup(struct ionic *ionic); 335 void ionic_dev_teardown(struct ionic *ionic); 336 337 void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd); 338 u8 ionic_dev_cmd_status(struct ionic_dev *idev); 339 bool ionic_dev_cmd_done(struct ionic_dev *idev); 340 void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp); 341 342 void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver); 343 void ionic_dev_cmd_init(struct ionic_dev *idev); 344 void ionic_dev_cmd_reset(struct ionic_dev *idev); 345 346 void ionic_dev_cmd_port_identify(struct ionic_dev *idev); 347 void ionic_dev_cmd_port_init(struct ionic_dev *idev); 348 void ionic_dev_cmd_port_reset(struct ionic_dev *idev); 349 void ionic_dev_cmd_port_state(struct ionic_dev *idev, u8 state); 350 void ionic_dev_cmd_port_speed(struct ionic_dev *idev, u32 speed); 351 void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, u8 an_enable); 352 void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type); 353 void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type); 354 355 int ionic_set_vf_config(struct ionic *ionic, int vf, 356 struct ionic_vf_setattr_cmd *vfc); 357 358 void ionic_dev_cmd_queue_identify(struct ionic_dev *idev, 359 u16 lif_type, u8 qtype, u8 qver); 360 void ionic_vf_start(struct ionic *ionic); 361 void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver); 362 void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index, 363 dma_addr_t addr); 364 void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index); 365 void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq, 366 u16 lif_index, u16 intr_index); 367 368 int ionic_db_page_num(struct ionic_lif *lif, int pid); 369 370 int ionic_get_cmb(struct ionic_lif *lif, u32 *pgid, phys_addr_t *pgaddr, int order); 371 void ionic_put_cmb(struct ionic_lif *lif, u32 pgid, int order); 372 373 int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq, 374 struct ionic_intr_info *intr, 375 unsigned int num_descs, size_t desc_size); 376 void ionic_cq_map(struct ionic_cq *cq, void *base, dma_addr_t base_pa); 377 void ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q); 378 typedef bool (*ionic_cq_cb)(struct ionic_cq *cq, struct ionic_cq_info *cq_info); 379 typedef void (*ionic_cq_done_cb)(void *done_arg); 380 unsigned int ionic_cq_service(struct ionic_cq *cq, unsigned int work_to_do, 381 ionic_cq_cb cb, ionic_cq_done_cb done_cb, 382 void *done_arg); 383 unsigned int ionic_tx_cq_service(struct ionic_cq *cq, unsigned int work_to_do); 384 385 int ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev, 386 struct ionic_queue *q, unsigned int index, const char *name, 387 unsigned int num_descs, size_t desc_size, 388 size_t sg_desc_size, unsigned int pid); 389 void ionic_q_map(struct ionic_queue *q, void *base, dma_addr_t base_pa); 390 void ionic_q_cmb_map(struct ionic_queue *q, void __iomem *base, dma_addr_t base_pa); 391 void ionic_q_sg_map(struct ionic_queue *q, void *base, dma_addr_t base_pa); 392 void ionic_q_post(struct ionic_queue *q, bool ring_doorbell, ionic_desc_cb cb, 393 void *cb_arg); 394 void ionic_q_service(struct ionic_queue *q, struct ionic_cq_info *cq_info, 395 unsigned int stop_index); 396 int ionic_heartbeat_check(struct ionic *ionic); 397 bool ionic_is_fw_running(struct ionic_dev *idev); 398 399 bool ionic_adminq_poke_doorbell(struct ionic_queue *q); 400 bool ionic_txq_poke_doorbell(struct ionic_queue *q); 401 bool ionic_rxq_poke_doorbell(struct ionic_queue *q); 402 403 #endif /* _IONIC_DEV_H_ */ 404