1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/kernel.h> 5 #include <linux/types.h> 6 #include <linux/errno.h> 7 #include <linux/io.h> 8 #include <linux/slab.h> 9 #include <linux/etherdevice.h> 10 #include "ionic.h" 11 #include "ionic_dev.h" 12 #include "ionic_lif.h" 13 14 static void ionic_watchdog_cb(struct timer_list *t) 15 { 16 struct ionic *ionic = from_timer(ionic, t, watchdog_timer); 17 struct ionic_lif *lif = ionic->lif; 18 struct ionic_deferred_work *work; 19 int hb; 20 21 mod_timer(&ionic->watchdog_timer, 22 round_jiffies(jiffies + ionic->watchdog_period)); 23 24 if (!lif) 25 return; 26 27 hb = ionic_heartbeat_check(ionic); 28 dev_dbg(ionic->dev, "%s: hb %d running %d UP %d\n", 29 __func__, hb, netif_running(lif->netdev), 30 test_bit(IONIC_LIF_F_UP, lif->state)); 31 32 if (hb >= 0 && 33 !test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 34 ionic_link_status_check_request(lif, CAN_NOT_SLEEP); 35 36 if (test_bit(IONIC_LIF_F_FILTER_SYNC_NEEDED, lif->state) && 37 !test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 38 work = kzalloc(sizeof(*work), GFP_ATOMIC); 39 if (!work) { 40 netdev_err(lif->netdev, "rxmode change dropped\n"); 41 return; 42 } 43 44 work->type = IONIC_DW_TYPE_RX_MODE; 45 netdev_dbg(lif->netdev, "deferred: rx_mode\n"); 46 ionic_lif_deferred_enqueue(lif, work); 47 } 48 } 49 50 static void ionic_napi_schedule_do_softirq(struct napi_struct *napi) 51 { 52 local_bh_disable(); 53 napi_schedule(napi); 54 local_bh_enable(); 55 } 56 57 void ionic_doorbell_napi_work(struct work_struct *work) 58 { 59 struct ionic_qcq *qcq = container_of(work, struct ionic_qcq, 60 doorbell_napi_work); 61 unsigned long now, then, dif; 62 63 now = READ_ONCE(jiffies); 64 then = qcq->q.dbell_jiffies; 65 dif = now - then; 66 67 if (dif > qcq->q.dbell_deadline) 68 ionic_napi_schedule_do_softirq(&qcq->napi); 69 } 70 71 static int ionic_get_preferred_cpu(struct ionic *ionic, 72 struct ionic_intr_info *intr) 73 { 74 int cpu; 75 76 cpu = cpumask_first_and(*intr->affinity_mask, cpu_online_mask); 77 if (cpu >= nr_cpu_ids) 78 cpu = cpumask_local_spread(0, dev_to_node(ionic->dev)); 79 80 return cpu; 81 } 82 83 static void ionic_queue_dbell_napi_work(struct ionic *ionic, 84 struct ionic_qcq *qcq) 85 { 86 int cpu; 87 88 if (!(qcq->flags & IONIC_QCQ_F_INTR)) 89 return; 90 91 cpu = ionic_get_preferred_cpu(ionic, &qcq->intr); 92 queue_work_on(cpu, ionic->wq, &qcq->doorbell_napi_work); 93 } 94 95 static void ionic_doorbell_check_dwork(struct work_struct *work) 96 { 97 struct ionic *ionic = container_of(work, struct ionic, 98 doorbell_check_dwork.work); 99 struct ionic_lif *lif = ionic->lif; 100 101 mutex_lock(&lif->queue_lock); 102 103 if (test_bit(IONIC_LIF_F_FW_STOPPING, lif->state) || 104 test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 105 mutex_unlock(&lif->queue_lock); 106 return; 107 } 108 109 ionic_napi_schedule_do_softirq(&lif->adminqcq->napi); 110 111 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 112 int i; 113 114 for (i = 0; i < lif->nxqs; i++) { 115 ionic_queue_dbell_napi_work(ionic, lif->txqcqs[i]); 116 ionic_queue_dbell_napi_work(ionic, lif->rxqcqs[i]); 117 } 118 119 if (lif->hwstamp_txq && 120 lif->hwstamp_txq->flags & IONIC_QCQ_F_INTR) 121 ionic_napi_schedule_do_softirq(&lif->hwstamp_txq->napi); 122 if (lif->hwstamp_rxq && 123 lif->hwstamp_rxq->flags & IONIC_QCQ_F_INTR) 124 ionic_napi_schedule_do_softirq(&lif->hwstamp_rxq->napi); 125 } 126 mutex_unlock(&lif->queue_lock); 127 128 ionic_queue_doorbell_check(ionic, IONIC_NAPI_DEADLINE); 129 } 130 131 bool ionic_doorbell_wa(struct ionic *ionic) 132 { 133 u8 asic_type = ionic->idev.dev_info.asic_type; 134 135 return !asic_type || asic_type == IONIC_ASIC_TYPE_ELBA; 136 } 137 138 static int ionic_watchdog_init(struct ionic *ionic) 139 { 140 struct ionic_dev *idev = &ionic->idev; 141 142 timer_setup(&ionic->watchdog_timer, ionic_watchdog_cb, 0); 143 ionic->watchdog_period = IONIC_WATCHDOG_SECS * HZ; 144 145 /* set times to ensure the first check will proceed */ 146 atomic_long_set(&idev->last_check_time, jiffies - 2 * HZ); 147 idev->last_hb_time = jiffies - 2 * ionic->watchdog_period; 148 /* init as ready, so no transition if the first check succeeds */ 149 idev->last_fw_hb = 0; 150 idev->fw_hb_ready = true; 151 idev->fw_status_ready = true; 152 idev->fw_generation = IONIC_FW_STS_F_GENERATION & 153 ioread8(&idev->dev_info_regs->fw_status); 154 155 ionic->wq = alloc_workqueue("%s-wq", WQ_UNBOUND, 0, 156 dev_name(ionic->dev)); 157 if (!ionic->wq) { 158 dev_err(ionic->dev, "alloc_workqueue failed"); 159 return -ENOMEM; 160 } 161 162 if (ionic_doorbell_wa(ionic)) 163 INIT_DELAYED_WORK(&ionic->doorbell_check_dwork, 164 ionic_doorbell_check_dwork); 165 166 return 0; 167 } 168 169 void ionic_queue_doorbell_check(struct ionic *ionic, int delay) 170 { 171 int cpu; 172 173 if (!ionic->lif->doorbell_wa) 174 return; 175 176 cpu = ionic_get_preferred_cpu(ionic, &ionic->lif->adminqcq->intr); 177 queue_delayed_work_on(cpu, ionic->wq, &ionic->doorbell_check_dwork, 178 delay); 179 } 180 181 void ionic_init_devinfo(struct ionic *ionic) 182 { 183 struct ionic_dev *idev = &ionic->idev; 184 185 idev->dev_info.asic_type = ioread8(&idev->dev_info_regs->asic_type); 186 idev->dev_info.asic_rev = ioread8(&idev->dev_info_regs->asic_rev); 187 188 memcpy_fromio(idev->dev_info.fw_version, 189 idev->dev_info_regs->fw_version, 190 IONIC_DEVINFO_FWVERS_BUFLEN); 191 192 memcpy_fromio(idev->dev_info.serial_num, 193 idev->dev_info_regs->serial_num, 194 IONIC_DEVINFO_SERIAL_BUFLEN); 195 196 idev->dev_info.fw_version[IONIC_DEVINFO_FWVERS_BUFLEN] = 0; 197 idev->dev_info.serial_num[IONIC_DEVINFO_SERIAL_BUFLEN] = 0; 198 199 dev_dbg(ionic->dev, "fw_version %s\n", idev->dev_info.fw_version); 200 } 201 202 int ionic_dev_setup(struct ionic *ionic) 203 { 204 struct ionic_dev_bar *bar = ionic->bars; 205 unsigned int num_bars = ionic->num_bars; 206 struct ionic_dev *idev = &ionic->idev; 207 struct device *dev = ionic->dev; 208 int size; 209 u32 sig; 210 int err; 211 212 /* BAR0: dev_cmd and interrupts */ 213 if (num_bars < 1) { 214 dev_err(dev, "No bars found, aborting\n"); 215 return -EFAULT; 216 } 217 218 if (bar->len < IONIC_BAR0_SIZE) { 219 dev_err(dev, "Resource bar size %lu too small, aborting\n", 220 bar->len); 221 return -EFAULT; 222 } 223 224 idev->dev_info_regs = bar->vaddr + IONIC_BAR0_DEV_INFO_REGS_OFFSET; 225 idev->dev_cmd_regs = bar->vaddr + IONIC_BAR0_DEV_CMD_REGS_OFFSET; 226 idev->intr_status = bar->vaddr + IONIC_BAR0_INTR_STATUS_OFFSET; 227 idev->intr_ctrl = bar->vaddr + IONIC_BAR0_INTR_CTRL_OFFSET; 228 229 idev->hwstamp_regs = &idev->dev_info_regs->hwstamp; 230 231 sig = ioread32(&idev->dev_info_regs->signature); 232 if (sig != IONIC_DEV_INFO_SIGNATURE) { 233 dev_err(dev, "Incompatible firmware signature %x", sig); 234 return -EFAULT; 235 } 236 237 ionic_init_devinfo(ionic); 238 239 /* BAR1: doorbells */ 240 bar++; 241 if (num_bars < 2) { 242 dev_err(dev, "Doorbell bar missing, aborting\n"); 243 return -EFAULT; 244 } 245 246 err = ionic_watchdog_init(ionic); 247 if (err) 248 return err; 249 250 idev->db_pages = bar->vaddr; 251 idev->phy_db_pages = bar->bus_addr; 252 253 /* BAR2: optional controller memory mapping */ 254 bar++; 255 mutex_init(&idev->cmb_inuse_lock); 256 if (num_bars < 3 || !ionic->bars[IONIC_PCI_BAR_CMB].len) { 257 idev->cmb_inuse = NULL; 258 return 0; 259 } 260 261 idev->phy_cmb_pages = bar->bus_addr; 262 idev->cmb_npages = bar->len / PAGE_SIZE; 263 size = BITS_TO_LONGS(idev->cmb_npages) * sizeof(long); 264 idev->cmb_inuse = kzalloc(size, GFP_KERNEL); 265 if (!idev->cmb_inuse) 266 dev_warn(dev, "No memory for CMB, disabling\n"); 267 268 return 0; 269 } 270 271 void ionic_dev_teardown(struct ionic *ionic) 272 { 273 struct ionic_dev *idev = &ionic->idev; 274 275 kfree(idev->cmb_inuse); 276 idev->cmb_inuse = NULL; 277 idev->phy_cmb_pages = 0; 278 idev->cmb_npages = 0; 279 280 if (ionic->wq) { 281 destroy_workqueue(ionic->wq); 282 ionic->wq = NULL; 283 } 284 mutex_destroy(&idev->cmb_inuse_lock); 285 } 286 287 /* Devcmd Interface */ 288 static bool __ionic_is_fw_running(struct ionic_dev *idev, u8 *status_ptr) 289 { 290 u8 fw_status; 291 292 if (!idev->dev_info_regs) { 293 if (status_ptr) 294 *status_ptr = 0xff; 295 return false; 296 } 297 298 fw_status = ioread8(&idev->dev_info_regs->fw_status); 299 if (status_ptr) 300 *status_ptr = fw_status; 301 302 /* firmware is useful only if the running bit is set and 303 * fw_status != 0xff (bad PCI read) 304 */ 305 return (fw_status != 0xff) && (fw_status & IONIC_FW_STS_F_RUNNING); 306 } 307 308 bool ionic_is_fw_running(struct ionic_dev *idev) 309 { 310 return __ionic_is_fw_running(idev, NULL); 311 } 312 313 int ionic_heartbeat_check(struct ionic *ionic) 314 { 315 unsigned long check_time, last_check_time; 316 struct ionic_dev *idev = &ionic->idev; 317 struct ionic_lif *lif = ionic->lif; 318 bool fw_status_ready = true; 319 bool fw_hb_ready; 320 u8 fw_generation; 321 u8 fw_status; 322 u32 fw_hb; 323 324 /* wait a least one second before testing again */ 325 check_time = jiffies; 326 last_check_time = atomic_long_read(&idev->last_check_time); 327 do_check_time: 328 if (time_before(check_time, last_check_time + HZ)) 329 return 0; 330 if (!atomic_long_try_cmpxchg_relaxed(&idev->last_check_time, 331 &last_check_time, check_time)) { 332 /* if called concurrently, only the first should proceed. */ 333 dev_dbg(ionic->dev, "%s: do_check_time again\n", __func__); 334 goto do_check_time; 335 } 336 337 /* If fw_status is not ready don't bother with the generation */ 338 if (!__ionic_is_fw_running(idev, &fw_status)) { 339 fw_status_ready = false; 340 } else { 341 fw_generation = fw_status & IONIC_FW_STS_F_GENERATION; 342 if (idev->fw_generation != fw_generation) { 343 dev_info(ionic->dev, "FW generation 0x%02x -> 0x%02x\n", 344 idev->fw_generation, fw_generation); 345 346 idev->fw_generation = fw_generation; 347 348 /* If the generation changed, the fw status is not 349 * ready so we need to trigger a fw-down cycle. After 350 * the down, the next watchdog will see the fw is up 351 * and the generation value stable, so will trigger 352 * the fw-up activity. 353 * 354 * If we had already moved to FW_RESET from a RESET event, 355 * it is possible that we never saw the fw_status go to 0, 356 * so we fake the current idev->fw_status_ready here to 357 * force the transition and get FW up again. 358 */ 359 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 360 idev->fw_status_ready = false; /* go to running */ 361 else 362 fw_status_ready = false; /* go to down */ 363 } 364 } 365 366 dev_dbg(ionic->dev, "fw_status 0x%02x ready %d idev->ready %d last_hb 0x%x state 0x%02lx\n", 367 fw_status, fw_status_ready, idev->fw_status_ready, 368 idev->last_fw_hb, lif->state[0]); 369 370 /* is this a transition? */ 371 if (fw_status_ready != idev->fw_status_ready && 372 !test_bit(IONIC_LIF_F_FW_STOPPING, lif->state)) { 373 bool trigger = false; 374 375 idev->fw_status_ready = fw_status_ready; 376 377 if (!fw_status_ready && 378 !test_bit(IONIC_LIF_F_FW_RESET, lif->state) && 379 !test_and_set_bit(IONIC_LIF_F_FW_STOPPING, lif->state)) { 380 dev_info(ionic->dev, "FW stopped 0x%02x\n", fw_status); 381 trigger = true; 382 383 } else if (fw_status_ready && 384 test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 385 dev_info(ionic->dev, "FW running 0x%02x\n", fw_status); 386 trigger = true; 387 } 388 389 if (trigger) { 390 struct ionic_deferred_work *work; 391 392 work = kzalloc(sizeof(*work), GFP_ATOMIC); 393 if (work) { 394 work->type = IONIC_DW_TYPE_LIF_RESET; 395 work->fw_status = fw_status_ready; 396 ionic_lif_deferred_enqueue(lif, work); 397 } 398 } 399 } 400 401 if (!idev->fw_status_ready) 402 return -ENXIO; 403 404 /* Because of some variability in the actual FW heartbeat, we 405 * wait longer than the DEVCMD_TIMEOUT before checking again. 406 */ 407 last_check_time = idev->last_hb_time; 408 if (time_before(check_time, last_check_time + DEVCMD_TIMEOUT * 2 * HZ)) 409 return 0; 410 411 fw_hb = ioread32(&idev->dev_info_regs->fw_heartbeat); 412 fw_hb_ready = fw_hb != idev->last_fw_hb; 413 414 /* early FW version had no heartbeat, so fake it */ 415 if (!fw_hb_ready && !fw_hb) 416 fw_hb_ready = true; 417 418 dev_dbg(ionic->dev, "%s: fw_hb %u last_fw_hb %u ready %u\n", 419 __func__, fw_hb, idev->last_fw_hb, fw_hb_ready); 420 421 idev->last_fw_hb = fw_hb; 422 423 /* log a transition */ 424 if (fw_hb_ready != idev->fw_hb_ready) { 425 idev->fw_hb_ready = fw_hb_ready; 426 if (!fw_hb_ready) 427 dev_info(ionic->dev, "FW heartbeat stalled at %d\n", fw_hb); 428 else 429 dev_info(ionic->dev, "FW heartbeat restored at %d\n", fw_hb); 430 } 431 432 if (!fw_hb_ready) 433 return -ENXIO; 434 435 idev->last_hb_time = check_time; 436 437 return 0; 438 } 439 440 u8 ionic_dev_cmd_status(struct ionic_dev *idev) 441 { 442 if (!idev->dev_cmd_regs) 443 return (u8)PCI_ERROR_RESPONSE; 444 return ioread8(&idev->dev_cmd_regs->comp.comp.status); 445 } 446 447 bool ionic_dev_cmd_done(struct ionic_dev *idev) 448 { 449 if (!idev->dev_cmd_regs) 450 return false; 451 return ioread32(&idev->dev_cmd_regs->done) & IONIC_DEV_CMD_DONE; 452 } 453 454 void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp) 455 { 456 if (!idev->dev_cmd_regs) 457 return; 458 memcpy_fromio(comp, &idev->dev_cmd_regs->comp, sizeof(*comp)); 459 } 460 461 void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd) 462 { 463 idev->opcode = cmd->cmd.opcode; 464 465 if (!idev->dev_cmd_regs) 466 return; 467 468 memcpy_toio(&idev->dev_cmd_regs->cmd, cmd, sizeof(*cmd)); 469 iowrite32(0, &idev->dev_cmd_regs->done); 470 iowrite32(1, &idev->dev_cmd_regs->doorbell); 471 } 472 473 /* Device commands */ 474 void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver) 475 { 476 union ionic_dev_cmd cmd = { 477 .identify.opcode = IONIC_CMD_IDENTIFY, 478 .identify.ver = ver, 479 }; 480 481 ionic_dev_cmd_go(idev, &cmd); 482 } 483 484 void ionic_dev_cmd_init(struct ionic_dev *idev) 485 { 486 union ionic_dev_cmd cmd = { 487 .init.opcode = IONIC_CMD_INIT, 488 .init.type = 0, 489 }; 490 491 ionic_dev_cmd_go(idev, &cmd); 492 } 493 494 void ionic_dev_cmd_reset(struct ionic_dev *idev) 495 { 496 union ionic_dev_cmd cmd = { 497 .reset.opcode = IONIC_CMD_RESET, 498 }; 499 500 ionic_dev_cmd_go(idev, &cmd); 501 } 502 503 /* Port commands */ 504 void ionic_dev_cmd_port_identify(struct ionic_dev *idev) 505 { 506 union ionic_dev_cmd cmd = { 507 .port_init.opcode = IONIC_CMD_PORT_IDENTIFY, 508 .port_init.index = 0, 509 }; 510 511 ionic_dev_cmd_go(idev, &cmd); 512 } 513 514 void ionic_dev_cmd_port_init(struct ionic_dev *idev) 515 { 516 union ionic_dev_cmd cmd = { 517 .port_init.opcode = IONIC_CMD_PORT_INIT, 518 .port_init.index = 0, 519 .port_init.info_pa = cpu_to_le64(idev->port_info_pa), 520 }; 521 522 ionic_dev_cmd_go(idev, &cmd); 523 } 524 525 void ionic_dev_cmd_port_reset(struct ionic_dev *idev) 526 { 527 union ionic_dev_cmd cmd = { 528 .port_reset.opcode = IONIC_CMD_PORT_RESET, 529 .port_reset.index = 0, 530 }; 531 532 ionic_dev_cmd_go(idev, &cmd); 533 } 534 535 void ionic_dev_cmd_port_state(struct ionic_dev *idev, u8 state) 536 { 537 union ionic_dev_cmd cmd = { 538 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 539 .port_setattr.index = 0, 540 .port_setattr.attr = IONIC_PORT_ATTR_STATE, 541 .port_setattr.state = state, 542 }; 543 544 ionic_dev_cmd_go(idev, &cmd); 545 } 546 547 void ionic_dev_cmd_port_speed(struct ionic_dev *idev, u32 speed) 548 { 549 union ionic_dev_cmd cmd = { 550 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 551 .port_setattr.index = 0, 552 .port_setattr.attr = IONIC_PORT_ATTR_SPEED, 553 .port_setattr.speed = cpu_to_le32(speed), 554 }; 555 556 ionic_dev_cmd_go(idev, &cmd); 557 } 558 559 void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, u8 an_enable) 560 { 561 union ionic_dev_cmd cmd = { 562 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 563 .port_setattr.index = 0, 564 .port_setattr.attr = IONIC_PORT_ATTR_AUTONEG, 565 .port_setattr.an_enable = an_enable, 566 }; 567 568 ionic_dev_cmd_go(idev, &cmd); 569 } 570 571 void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type) 572 { 573 union ionic_dev_cmd cmd = { 574 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 575 .port_setattr.index = 0, 576 .port_setattr.attr = IONIC_PORT_ATTR_FEC, 577 .port_setattr.fec_type = fec_type, 578 }; 579 580 ionic_dev_cmd_go(idev, &cmd); 581 } 582 583 void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type) 584 { 585 union ionic_dev_cmd cmd = { 586 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 587 .port_setattr.index = 0, 588 .port_setattr.attr = IONIC_PORT_ATTR_PAUSE, 589 .port_setattr.pause_type = pause_type, 590 }; 591 592 ionic_dev_cmd_go(idev, &cmd); 593 } 594 595 /* VF commands */ 596 int ionic_set_vf_config(struct ionic *ionic, int vf, 597 struct ionic_vf_setattr_cmd *vfc) 598 { 599 union ionic_dev_cmd cmd = { 600 .vf_setattr.opcode = IONIC_CMD_VF_SETATTR, 601 .vf_setattr.attr = vfc->attr, 602 .vf_setattr.vf_index = cpu_to_le16(vf), 603 }; 604 int err; 605 606 memcpy(cmd.vf_setattr.pad, vfc->pad, sizeof(vfc->pad)); 607 608 mutex_lock(&ionic->dev_cmd_lock); 609 ionic_dev_cmd_go(&ionic->idev, &cmd); 610 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 611 mutex_unlock(&ionic->dev_cmd_lock); 612 613 return err; 614 } 615 616 void ionic_vf_start(struct ionic *ionic) 617 { 618 union ionic_dev_cmd cmd = { 619 .vf_ctrl.opcode = IONIC_CMD_VF_CTRL, 620 .vf_ctrl.ctrl_opcode = IONIC_VF_CTRL_START_ALL, 621 }; 622 623 if (!(ionic->ident.dev.capabilities & cpu_to_le64(IONIC_DEV_CAP_VF_CTRL))) 624 return; 625 626 ionic_dev_cmd_go(&ionic->idev, &cmd); 627 ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 628 } 629 630 /* LIF commands */ 631 void ionic_dev_cmd_queue_identify(struct ionic_dev *idev, 632 u16 lif_type, u8 qtype, u8 qver) 633 { 634 union ionic_dev_cmd cmd = { 635 .q_identify.opcode = IONIC_CMD_Q_IDENTIFY, 636 .q_identify.lif_type = cpu_to_le16(lif_type), 637 .q_identify.type = qtype, 638 .q_identify.ver = qver, 639 }; 640 641 ionic_dev_cmd_go(idev, &cmd); 642 } 643 644 void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver) 645 { 646 union ionic_dev_cmd cmd = { 647 .lif_identify.opcode = IONIC_CMD_LIF_IDENTIFY, 648 .lif_identify.type = type, 649 .lif_identify.ver = ver, 650 }; 651 652 ionic_dev_cmd_go(idev, &cmd); 653 } 654 655 void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index, 656 dma_addr_t info_pa) 657 { 658 union ionic_dev_cmd cmd = { 659 .lif_init.opcode = IONIC_CMD_LIF_INIT, 660 .lif_init.index = cpu_to_le16(lif_index), 661 .lif_init.info_pa = cpu_to_le64(info_pa), 662 }; 663 664 ionic_dev_cmd_go(idev, &cmd); 665 } 666 667 void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index) 668 { 669 union ionic_dev_cmd cmd = { 670 .lif_init.opcode = IONIC_CMD_LIF_RESET, 671 .lif_init.index = cpu_to_le16(lif_index), 672 }; 673 674 ionic_dev_cmd_go(idev, &cmd); 675 } 676 677 void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq, 678 u16 lif_index, u16 intr_index) 679 { 680 struct ionic_queue *q = &qcq->q; 681 struct ionic_cq *cq = &qcq->cq; 682 683 union ionic_dev_cmd cmd = { 684 .q_init.opcode = IONIC_CMD_Q_INIT, 685 .q_init.lif_index = cpu_to_le16(lif_index), 686 .q_init.type = q->type, 687 .q_init.ver = qcq->q.lif->qtype_info[q->type].version, 688 .q_init.index = cpu_to_le32(q->index), 689 .q_init.flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 690 IONIC_QINIT_F_ENA), 691 .q_init.pid = cpu_to_le16(q->pid), 692 .q_init.intr_index = cpu_to_le16(intr_index), 693 .q_init.ring_size = ilog2(q->num_descs), 694 .q_init.ring_base = cpu_to_le64(q->base_pa), 695 .q_init.cq_ring_base = cpu_to_le64(cq->base_pa), 696 }; 697 698 ionic_dev_cmd_go(idev, &cmd); 699 } 700 701 int ionic_db_page_num(struct ionic_lif *lif, int pid) 702 { 703 return (lif->hw_index * lif->dbid_count) + pid; 704 } 705 706 int ionic_get_cmb(struct ionic_lif *lif, u32 *pgid, phys_addr_t *pgaddr, int order) 707 { 708 struct ionic_dev *idev = &lif->ionic->idev; 709 int ret; 710 711 mutex_lock(&idev->cmb_inuse_lock); 712 ret = bitmap_find_free_region(idev->cmb_inuse, idev->cmb_npages, order); 713 mutex_unlock(&idev->cmb_inuse_lock); 714 715 if (ret < 0) 716 return ret; 717 718 *pgid = ret; 719 *pgaddr = idev->phy_cmb_pages + ret * PAGE_SIZE; 720 721 return 0; 722 } 723 724 void ionic_put_cmb(struct ionic_lif *lif, u32 pgid, int order) 725 { 726 struct ionic_dev *idev = &lif->ionic->idev; 727 728 mutex_lock(&idev->cmb_inuse_lock); 729 bitmap_release_region(idev->cmb_inuse, pgid, order); 730 mutex_unlock(&idev->cmb_inuse_lock); 731 } 732 733 int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq, 734 struct ionic_intr_info *intr, 735 unsigned int num_descs, size_t desc_size) 736 { 737 unsigned int ring_size; 738 739 if (desc_size == 0 || !is_power_of_2(num_descs)) 740 return -EINVAL; 741 742 ring_size = ilog2(num_descs); 743 if (ring_size < 2 || ring_size > 16) 744 return -EINVAL; 745 746 cq->lif = lif; 747 cq->bound_intr = intr; 748 cq->num_descs = num_descs; 749 cq->desc_size = desc_size; 750 cq->tail_idx = 0; 751 cq->done_color = 1; 752 cq->idev = &lif->ionic->idev; 753 754 return 0; 755 } 756 757 unsigned int ionic_cq_service(struct ionic_cq *cq, unsigned int work_to_do, 758 ionic_cq_cb cb, ionic_cq_done_cb done_cb, 759 void *done_arg) 760 { 761 unsigned int work_done = 0; 762 763 if (work_to_do == 0) 764 return 0; 765 766 while (cb(cq)) { 767 if (cq->tail_idx == cq->num_descs - 1) 768 cq->done_color = !cq->done_color; 769 770 cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1); 771 772 if (++work_done >= work_to_do) 773 break; 774 } 775 776 if (work_done && done_cb) 777 done_cb(done_arg); 778 779 return work_done; 780 } 781 782 int ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev, 783 struct ionic_queue *q, unsigned int index, const char *name, 784 unsigned int num_descs, size_t desc_size, 785 size_t sg_desc_size, unsigned int pid) 786 { 787 unsigned int ring_size; 788 789 if (desc_size == 0 || !is_power_of_2(num_descs)) 790 return -EINVAL; 791 792 ring_size = ilog2(num_descs); 793 if (ring_size < 2 || ring_size > 16) 794 return -EINVAL; 795 796 q->lif = lif; 797 q->index = index; 798 q->num_descs = num_descs; 799 q->desc_size = desc_size; 800 q->sg_desc_size = sg_desc_size; 801 q->tail_idx = 0; 802 q->head_idx = 0; 803 q->pid = pid; 804 805 snprintf(q->name, sizeof(q->name), "L%d-%s%u", lif->index, name, index); 806 807 return 0; 808 } 809 810 void ionic_q_post(struct ionic_queue *q, bool ring_doorbell) 811 { 812 struct ionic_lif *lif = q->lif; 813 struct device *dev = q->dev; 814 815 q->head_idx = (q->head_idx + 1) & (q->num_descs - 1); 816 817 dev_dbg(dev, "lif=%d qname=%s qid=%d qtype=%d p_index=%d ringdb=%d\n", 818 q->lif->index, q->name, q->hw_type, q->hw_index, 819 q->head_idx, ring_doorbell); 820 821 if (ring_doorbell) { 822 ionic_dbell_ring(lif->kern_dbpage, q->hw_type, 823 q->dbval | q->head_idx); 824 825 q->dbell_jiffies = jiffies; 826 } 827 } 828 829 bool ionic_q_is_posted(struct ionic_queue *q, unsigned int pos) 830 { 831 unsigned int mask, tail, head; 832 833 mask = q->num_descs - 1; 834 tail = q->tail_idx; 835 head = q->head_idx; 836 837 return ((pos - tail) & mask) < ((head - tail) & mask); 838 } 839