1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/kernel.h> 5 #include <linux/types.h> 6 #include <linux/errno.h> 7 #include <linux/io.h> 8 #include <linux/slab.h> 9 #include <linux/etherdevice.h> 10 #include "ionic.h" 11 #include "ionic_dev.h" 12 #include "ionic_lif.h" 13 14 static void ionic_watchdog_cb(struct timer_list *t) 15 { 16 struct ionic *ionic = from_timer(ionic, t, watchdog_timer); 17 18 mod_timer(&ionic->watchdog_timer, 19 round_jiffies(jiffies + ionic->watchdog_period)); 20 21 ionic_heartbeat_check(ionic); 22 } 23 24 void ionic_init_devinfo(struct ionic *ionic) 25 { 26 struct ionic_dev *idev = &ionic->idev; 27 28 idev->dev_info.asic_type = ioread8(&idev->dev_info_regs->asic_type); 29 idev->dev_info.asic_rev = ioread8(&idev->dev_info_regs->asic_rev); 30 31 memcpy_fromio(idev->dev_info.fw_version, 32 idev->dev_info_regs->fw_version, 33 IONIC_DEVINFO_FWVERS_BUFLEN); 34 35 memcpy_fromio(idev->dev_info.serial_num, 36 idev->dev_info_regs->serial_num, 37 IONIC_DEVINFO_SERIAL_BUFLEN); 38 39 idev->dev_info.fw_version[IONIC_DEVINFO_FWVERS_BUFLEN] = 0; 40 idev->dev_info.serial_num[IONIC_DEVINFO_SERIAL_BUFLEN] = 0; 41 42 dev_dbg(ionic->dev, "fw_version %s\n", idev->dev_info.fw_version); 43 } 44 45 int ionic_dev_setup(struct ionic *ionic) 46 { 47 struct ionic_dev_bar *bar = ionic->bars; 48 unsigned int num_bars = ionic->num_bars; 49 struct ionic_dev *idev = &ionic->idev; 50 struct device *dev = ionic->dev; 51 u32 sig; 52 53 /* BAR0: dev_cmd and interrupts */ 54 if (num_bars < 1) { 55 dev_err(dev, "No bars found, aborting\n"); 56 return -EFAULT; 57 } 58 59 if (bar->len < IONIC_BAR0_SIZE) { 60 dev_err(dev, "Resource bar size %lu too small, aborting\n", 61 bar->len); 62 return -EFAULT; 63 } 64 65 idev->dev_info_regs = bar->vaddr + IONIC_BAR0_DEV_INFO_REGS_OFFSET; 66 idev->dev_cmd_regs = bar->vaddr + IONIC_BAR0_DEV_CMD_REGS_OFFSET; 67 idev->intr_status = bar->vaddr + IONIC_BAR0_INTR_STATUS_OFFSET; 68 idev->intr_ctrl = bar->vaddr + IONIC_BAR0_INTR_CTRL_OFFSET; 69 70 sig = ioread32(&idev->dev_info_regs->signature); 71 if (sig != IONIC_DEV_INFO_SIGNATURE) { 72 dev_err(dev, "Incompatible firmware signature %x", sig); 73 return -EFAULT; 74 } 75 76 ionic_init_devinfo(ionic); 77 78 /* BAR1: doorbells */ 79 bar++; 80 if (num_bars < 2) { 81 dev_err(dev, "Doorbell bar missing, aborting\n"); 82 return -EFAULT; 83 } 84 85 timer_setup(&ionic->watchdog_timer, ionic_watchdog_cb, 0); 86 ionic->watchdog_period = IONIC_WATCHDOG_SECS * HZ; 87 mod_timer(&ionic->watchdog_timer, 88 round_jiffies(jiffies + ionic->watchdog_period)); 89 90 idev->db_pages = bar->vaddr; 91 idev->phy_db_pages = bar->bus_addr; 92 93 return 0; 94 } 95 96 void ionic_dev_teardown(struct ionic *ionic) 97 { 98 del_timer_sync(&ionic->watchdog_timer); 99 } 100 101 /* Devcmd Interface */ 102 int ionic_heartbeat_check(struct ionic *ionic) 103 { 104 struct ionic_dev *idev = &ionic->idev; 105 unsigned long hb_time; 106 u8 fw_status; 107 u32 hb; 108 109 /* wait a little more than one second before testing again */ 110 hb_time = jiffies; 111 if (time_before(hb_time, (idev->last_hb_time + ionic->watchdog_period))) 112 return 0; 113 114 /* firmware is useful only if the running bit is set and 115 * fw_status != 0xff (bad PCI read) 116 */ 117 fw_status = ioread8(&idev->dev_info_regs->fw_status); 118 if (fw_status == 0xff || 119 !(fw_status & IONIC_FW_STS_F_RUNNING)) 120 return -ENXIO; 121 122 /* early FW has no heartbeat, else FW will return non-zero */ 123 hb = ioread32(&idev->dev_info_regs->fw_heartbeat); 124 if (!hb) 125 return 0; 126 127 /* are we stalled? */ 128 if (hb == idev->last_hb) { 129 /* only complain once for each stall seen */ 130 if (idev->last_hb_time != 1) { 131 dev_info(ionic->dev, "FW heartbeat stalled at %d\n", 132 idev->last_hb); 133 idev->last_hb_time = 1; 134 } 135 136 return -ENXIO; 137 } 138 139 if (idev->last_hb_time == 1) 140 dev_info(ionic->dev, "FW heartbeat restored at %d\n", hb); 141 142 idev->last_hb = hb; 143 idev->last_hb_time = hb_time; 144 145 return 0; 146 } 147 148 u8 ionic_dev_cmd_status(struct ionic_dev *idev) 149 { 150 return ioread8(&idev->dev_cmd_regs->comp.comp.status); 151 } 152 153 bool ionic_dev_cmd_done(struct ionic_dev *idev) 154 { 155 return ioread32(&idev->dev_cmd_regs->done) & IONIC_DEV_CMD_DONE; 156 } 157 158 void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp) 159 { 160 memcpy_fromio(comp, &idev->dev_cmd_regs->comp, sizeof(*comp)); 161 } 162 163 void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd) 164 { 165 memcpy_toio(&idev->dev_cmd_regs->cmd, cmd, sizeof(*cmd)); 166 iowrite32(0, &idev->dev_cmd_regs->done); 167 iowrite32(1, &idev->dev_cmd_regs->doorbell); 168 } 169 170 /* Device commands */ 171 void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver) 172 { 173 union ionic_dev_cmd cmd = { 174 .identify.opcode = IONIC_CMD_IDENTIFY, 175 .identify.ver = ver, 176 }; 177 178 ionic_dev_cmd_go(idev, &cmd); 179 } 180 181 void ionic_dev_cmd_init(struct ionic_dev *idev) 182 { 183 union ionic_dev_cmd cmd = { 184 .init.opcode = IONIC_CMD_INIT, 185 .init.type = 0, 186 }; 187 188 ionic_dev_cmd_go(idev, &cmd); 189 } 190 191 void ionic_dev_cmd_reset(struct ionic_dev *idev) 192 { 193 union ionic_dev_cmd cmd = { 194 .reset.opcode = IONIC_CMD_RESET, 195 }; 196 197 ionic_dev_cmd_go(idev, &cmd); 198 } 199 200 /* Port commands */ 201 void ionic_dev_cmd_port_identify(struct ionic_dev *idev) 202 { 203 union ionic_dev_cmd cmd = { 204 .port_init.opcode = IONIC_CMD_PORT_IDENTIFY, 205 .port_init.index = 0, 206 }; 207 208 ionic_dev_cmd_go(idev, &cmd); 209 } 210 211 void ionic_dev_cmd_port_init(struct ionic_dev *idev) 212 { 213 union ionic_dev_cmd cmd = { 214 .port_init.opcode = IONIC_CMD_PORT_INIT, 215 .port_init.index = 0, 216 .port_init.info_pa = cpu_to_le64(idev->port_info_pa), 217 }; 218 219 ionic_dev_cmd_go(idev, &cmd); 220 } 221 222 void ionic_dev_cmd_port_reset(struct ionic_dev *idev) 223 { 224 union ionic_dev_cmd cmd = { 225 .port_reset.opcode = IONIC_CMD_PORT_RESET, 226 .port_reset.index = 0, 227 }; 228 229 ionic_dev_cmd_go(idev, &cmd); 230 } 231 232 void ionic_dev_cmd_port_state(struct ionic_dev *idev, u8 state) 233 { 234 union ionic_dev_cmd cmd = { 235 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 236 .port_setattr.index = 0, 237 .port_setattr.attr = IONIC_PORT_ATTR_STATE, 238 .port_setattr.state = state, 239 }; 240 241 ionic_dev_cmd_go(idev, &cmd); 242 } 243 244 void ionic_dev_cmd_port_speed(struct ionic_dev *idev, u32 speed) 245 { 246 union ionic_dev_cmd cmd = { 247 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 248 .port_setattr.index = 0, 249 .port_setattr.attr = IONIC_PORT_ATTR_SPEED, 250 .port_setattr.speed = cpu_to_le32(speed), 251 }; 252 253 ionic_dev_cmd_go(idev, &cmd); 254 } 255 256 void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, u8 an_enable) 257 { 258 union ionic_dev_cmd cmd = { 259 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 260 .port_setattr.index = 0, 261 .port_setattr.attr = IONIC_PORT_ATTR_AUTONEG, 262 .port_setattr.an_enable = an_enable, 263 }; 264 265 ionic_dev_cmd_go(idev, &cmd); 266 } 267 268 void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type) 269 { 270 union ionic_dev_cmd cmd = { 271 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 272 .port_setattr.index = 0, 273 .port_setattr.attr = IONIC_PORT_ATTR_FEC, 274 .port_setattr.fec_type = fec_type, 275 }; 276 277 ionic_dev_cmd_go(idev, &cmd); 278 } 279 280 void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type) 281 { 282 union ionic_dev_cmd cmd = { 283 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 284 .port_setattr.index = 0, 285 .port_setattr.attr = IONIC_PORT_ATTR_PAUSE, 286 .port_setattr.pause_type = pause_type, 287 }; 288 289 ionic_dev_cmd_go(idev, &cmd); 290 } 291 292 /* VF commands */ 293 int ionic_set_vf_config(struct ionic *ionic, int vf, u8 attr, u8 *data) 294 { 295 union ionic_dev_cmd cmd = { 296 .vf_setattr.opcode = IONIC_CMD_VF_SETATTR, 297 .vf_setattr.attr = attr, 298 .vf_setattr.vf_index = vf, 299 }; 300 int err; 301 302 switch (attr) { 303 case IONIC_VF_ATTR_SPOOFCHK: 304 cmd.vf_setattr.spoofchk = *data; 305 dev_dbg(ionic->dev, "%s: vf %d spoof %d\n", 306 __func__, vf, *data); 307 break; 308 case IONIC_VF_ATTR_TRUST: 309 cmd.vf_setattr.trust = *data; 310 dev_dbg(ionic->dev, "%s: vf %d trust %d\n", 311 __func__, vf, *data); 312 break; 313 case IONIC_VF_ATTR_LINKSTATE: 314 cmd.vf_setattr.linkstate = *data; 315 dev_dbg(ionic->dev, "%s: vf %d linkstate %d\n", 316 __func__, vf, *data); 317 break; 318 case IONIC_VF_ATTR_MAC: 319 ether_addr_copy(cmd.vf_setattr.macaddr, data); 320 dev_dbg(ionic->dev, "%s: vf %d macaddr %pM\n", 321 __func__, vf, data); 322 break; 323 case IONIC_VF_ATTR_VLAN: 324 cmd.vf_setattr.vlanid = cpu_to_le16(*(u16 *)data); 325 dev_dbg(ionic->dev, "%s: vf %d vlan %d\n", 326 __func__, vf, *(u16 *)data); 327 break; 328 case IONIC_VF_ATTR_RATE: 329 cmd.vf_setattr.maxrate = cpu_to_le32(*(u32 *)data); 330 dev_dbg(ionic->dev, "%s: vf %d maxrate %d\n", 331 __func__, vf, *(u32 *)data); 332 break; 333 case IONIC_VF_ATTR_STATSADDR: 334 cmd.vf_setattr.stats_pa = cpu_to_le64(*(u64 *)data); 335 dev_dbg(ionic->dev, "%s: vf %d stats_pa 0x%08llx\n", 336 __func__, vf, *(u64 *)data); 337 break; 338 default: 339 return -EINVAL; 340 } 341 342 mutex_lock(&ionic->dev_cmd_lock); 343 ionic_dev_cmd_go(&ionic->idev, &cmd); 344 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 345 mutex_unlock(&ionic->dev_cmd_lock); 346 347 return err; 348 } 349 350 /* LIF commands */ 351 void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver) 352 { 353 union ionic_dev_cmd cmd = { 354 .lif_identify.opcode = IONIC_CMD_LIF_IDENTIFY, 355 .lif_identify.type = type, 356 .lif_identify.ver = ver, 357 }; 358 359 ionic_dev_cmd_go(idev, &cmd); 360 } 361 362 void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index, 363 dma_addr_t info_pa) 364 { 365 union ionic_dev_cmd cmd = { 366 .lif_init.opcode = IONIC_CMD_LIF_INIT, 367 .lif_init.index = cpu_to_le16(lif_index), 368 .lif_init.info_pa = cpu_to_le64(info_pa), 369 }; 370 371 ionic_dev_cmd_go(idev, &cmd); 372 } 373 374 void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index) 375 { 376 union ionic_dev_cmd cmd = { 377 .lif_init.opcode = IONIC_CMD_LIF_RESET, 378 .lif_init.index = cpu_to_le16(lif_index), 379 }; 380 381 ionic_dev_cmd_go(idev, &cmd); 382 } 383 384 void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq, 385 u16 lif_index, u16 intr_index) 386 { 387 struct ionic_queue *q = &qcq->q; 388 struct ionic_cq *cq = &qcq->cq; 389 390 union ionic_dev_cmd cmd = { 391 .q_init.opcode = IONIC_CMD_Q_INIT, 392 .q_init.lif_index = cpu_to_le16(lif_index), 393 .q_init.type = q->type, 394 .q_init.index = cpu_to_le32(q->index), 395 .q_init.flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 396 IONIC_QINIT_F_ENA), 397 .q_init.pid = cpu_to_le16(q->pid), 398 .q_init.intr_index = cpu_to_le16(intr_index), 399 .q_init.ring_size = ilog2(q->num_descs), 400 .q_init.ring_base = cpu_to_le64(q->base_pa), 401 .q_init.cq_ring_base = cpu_to_le64(cq->base_pa), 402 }; 403 404 ionic_dev_cmd_go(idev, &cmd); 405 } 406 407 int ionic_db_page_num(struct ionic_lif *lif, int pid) 408 { 409 return (lif->hw_index * lif->dbid_count) + pid; 410 } 411 412 int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq, 413 struct ionic_intr_info *intr, 414 unsigned int num_descs, size_t desc_size) 415 { 416 struct ionic_cq_info *cur; 417 unsigned int ring_size; 418 unsigned int i; 419 420 if (desc_size == 0 || !is_power_of_2(num_descs)) 421 return -EINVAL; 422 423 ring_size = ilog2(num_descs); 424 if (ring_size < 2 || ring_size > 16) 425 return -EINVAL; 426 427 cq->lif = lif; 428 cq->bound_intr = intr; 429 cq->num_descs = num_descs; 430 cq->desc_size = desc_size; 431 cq->tail = cq->info; 432 cq->done_color = 1; 433 434 cur = cq->info; 435 436 for (i = 0; i < num_descs; i++) { 437 if (i + 1 == num_descs) { 438 cur->next = cq->info; 439 cur->last = true; 440 } else { 441 cur->next = cur + 1; 442 } 443 cur->index = i; 444 cur++; 445 } 446 447 return 0; 448 } 449 450 void ionic_cq_map(struct ionic_cq *cq, void *base, dma_addr_t base_pa) 451 { 452 struct ionic_cq_info *cur; 453 unsigned int i; 454 455 cq->base = base; 456 cq->base_pa = base_pa; 457 458 for (i = 0, cur = cq->info; i < cq->num_descs; i++, cur++) 459 cur->cq_desc = base + (i * cq->desc_size); 460 } 461 462 void ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q) 463 { 464 cq->bound_q = q; 465 } 466 467 unsigned int ionic_cq_service(struct ionic_cq *cq, unsigned int work_to_do, 468 ionic_cq_cb cb, ionic_cq_done_cb done_cb, 469 void *done_arg) 470 { 471 unsigned int work_done = 0; 472 473 if (work_to_do == 0) 474 return 0; 475 476 while (cb(cq, cq->tail)) { 477 if (cq->tail->last) 478 cq->done_color = !cq->done_color; 479 cq->tail = cq->tail->next; 480 DEBUG_STATS_CQE_CNT(cq); 481 482 if (++work_done >= work_to_do) 483 break; 484 } 485 486 if (work_done && done_cb) 487 done_cb(done_arg); 488 489 return work_done; 490 } 491 492 int ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev, 493 struct ionic_queue *q, unsigned int index, const char *name, 494 unsigned int num_descs, size_t desc_size, 495 size_t sg_desc_size, unsigned int pid) 496 { 497 struct ionic_desc_info *cur; 498 unsigned int ring_size; 499 unsigned int i; 500 501 if (desc_size == 0 || !is_power_of_2(num_descs)) 502 return -EINVAL; 503 504 ring_size = ilog2(num_descs); 505 if (ring_size < 2 || ring_size > 16) 506 return -EINVAL; 507 508 q->lif = lif; 509 q->idev = idev; 510 q->index = index; 511 q->num_descs = num_descs; 512 q->desc_size = desc_size; 513 q->sg_desc_size = sg_desc_size; 514 q->tail = q->info; 515 q->head = q->tail; 516 q->pid = pid; 517 518 snprintf(q->name, sizeof(q->name), "L%d-%s%u", lif->index, name, index); 519 520 cur = q->info; 521 522 for (i = 0; i < num_descs; i++) { 523 if (i + 1 == num_descs) 524 cur->next = q->info; 525 else 526 cur->next = cur + 1; 527 cur->index = i; 528 cur->left = num_descs - i; 529 cur++; 530 } 531 532 return 0; 533 } 534 535 void ionic_q_map(struct ionic_queue *q, void *base, dma_addr_t base_pa) 536 { 537 struct ionic_desc_info *cur; 538 unsigned int i; 539 540 q->base = base; 541 q->base_pa = base_pa; 542 543 for (i = 0, cur = q->info; i < q->num_descs; i++, cur++) 544 cur->desc = base + (i * q->desc_size); 545 } 546 547 void ionic_q_sg_map(struct ionic_queue *q, void *base, dma_addr_t base_pa) 548 { 549 struct ionic_desc_info *cur; 550 unsigned int i; 551 552 q->sg_base = base; 553 q->sg_base_pa = base_pa; 554 555 for (i = 0, cur = q->info; i < q->num_descs; i++, cur++) 556 cur->sg_desc = base + (i * q->sg_desc_size); 557 } 558 559 void ionic_q_post(struct ionic_queue *q, bool ring_doorbell, ionic_desc_cb cb, 560 void *cb_arg) 561 { 562 struct device *dev = q->lif->ionic->dev; 563 struct ionic_lif *lif = q->lif; 564 565 q->head->cb = cb; 566 q->head->cb_arg = cb_arg; 567 q->head = q->head->next; 568 569 dev_dbg(dev, "lif=%d qname=%s qid=%d qtype=%d p_index=%d ringdb=%d\n", 570 q->lif->index, q->name, q->hw_type, q->hw_index, 571 q->head->index, ring_doorbell); 572 573 if (ring_doorbell) 574 ionic_dbell_ring(lif->kern_dbpage, q->hw_type, 575 q->dbval | q->head->index); 576 } 577 578 static bool ionic_q_is_posted(struct ionic_queue *q, unsigned int pos) 579 { 580 unsigned int mask, tail, head; 581 582 mask = q->num_descs - 1; 583 tail = q->tail->index; 584 head = q->head->index; 585 586 return ((pos - tail) & mask) < ((head - tail) & mask); 587 } 588 589 void ionic_q_service(struct ionic_queue *q, struct ionic_cq_info *cq_info, 590 unsigned int stop_index) 591 { 592 struct ionic_desc_info *desc_info; 593 ionic_desc_cb cb; 594 void *cb_arg; 595 596 /* check for empty queue */ 597 if (q->tail->index == q->head->index) 598 return; 599 600 /* stop index must be for a descriptor that is not yet completed */ 601 if (unlikely(!ionic_q_is_posted(q, stop_index))) 602 dev_err(q->lif->ionic->dev, 603 "ionic stop is not posted %s stop %u tail %u head %u\n", 604 q->name, stop_index, q->tail->index, q->head->index); 605 606 do { 607 desc_info = q->tail; 608 q->tail = desc_info->next; 609 610 cb = desc_info->cb; 611 cb_arg = desc_info->cb_arg; 612 613 desc_info->cb = NULL; 614 desc_info->cb_arg = NULL; 615 616 if (cb) 617 cb(q, desc_info, cq_info, cb_arg); 618 } while (desc_info->index != stop_index); 619 } 620