1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2018-2025, Advanced Micro Devices, Inc. */ 3 4 #ifndef _IONIC_API_H_ 5 #define _IONIC_API_H_ 6 7 #include <linux/auxiliary_bus.h> 8 #include "ionic_if.h" 9 #include "ionic_regs.h" 10 11 /** 12 * struct ionic_aux_dev - Auxiliary device information 13 * @lif: Logical interface 14 * @idx: Index identifier 15 * @adev: Auxiliary device 16 */ 17 struct ionic_aux_dev { 18 struct ionic_lif *lif; 19 int idx; 20 struct auxiliary_device adev; 21 }; 22 23 /** 24 * struct ionic_admin_ctx - Admin command context 25 * @work: Work completion wait queue element 26 * @cmd: Admin command (64B) to be copied to the queue 27 * @comp: Admin completion (16B) copied from the queue 28 */ 29 struct ionic_admin_ctx { 30 struct completion work; 31 union ionic_adminq_cmd cmd; 32 union ionic_adminq_comp comp; 33 }; 34 35 #define IONIC_INTR_INDEX_NOT_ASSIGNED -1 36 #define IONIC_INTR_NAME_MAX_SZ 32 37 38 /** 39 * struct ionic_intr_info - Interrupt information 40 * @name: Name identifier 41 * @rearm_count: Interrupt rearm count 42 * @index: Interrupt index position 43 * @vector: Interrupt number 44 * @dim_coal_hw: Interrupt coalesce value in hardware units 45 * @affinity_mask: CPU affinity mask 46 * @aff_notify: context for notification of IRQ affinity changes 47 */ 48 struct ionic_intr_info { 49 char name[IONIC_INTR_NAME_MAX_SZ]; 50 u64 rearm_count; 51 unsigned int index; 52 unsigned int vector; 53 u32 dim_coal_hw; 54 cpumask_var_t *affinity_mask; 55 struct irq_affinity_notify aff_notify; 56 }; 57 58 /** 59 * ionic_adminq_post_wait - Post an admin command and wait for response 60 * @lif: Logical interface 61 * @ctx: API admin command context 62 * 63 * Post the command to an admin queue in the ethernet driver. If this command 64 * succeeds, then the command has been posted, but that does not indicate a 65 * completion. If this command returns success, then the completion callback 66 * will eventually be called. 67 * 68 * Return: zero or negative error status 69 */ 70 int ionic_adminq_post_wait(struct ionic_lif *lif, struct ionic_admin_ctx *ctx); 71 72 /** 73 * ionic_error_to_errno - Transform ionic_if errors to os errno 74 * @code: Ionic error number 75 * 76 * Return: Negative OS error number or zero 77 */ 78 int ionic_error_to_errno(enum ionic_status_code code); 79 80 /** 81 * ionic_request_rdma_reset - request reset or disable the device or lif 82 * @lif: Logical interface 83 * 84 * The reset is triggered asynchronously. It will wait until reset request 85 * completes or times out. 86 */ 87 void ionic_request_rdma_reset(struct ionic_lif *lif); 88 89 /** 90 * ionic_intr_alloc - Reserve a device interrupt 91 * @lif: Logical interface 92 * @intr: Reserved ionic interrupt structure 93 * 94 * Reserve an interrupt index and get irq number for that index. 95 * 96 * Return: zero or negative error status 97 */ 98 int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr); 99 100 /** 101 * ionic_intr_free - Release a device interrupt index 102 * @lif: Logical interface 103 * @intr: Interrupt index 104 * 105 * Mark the interrupt index unused so that it can be reserved again. 106 */ 107 void ionic_intr_free(struct ionic_lif *lif, int intr); 108 109 /** 110 * ionic_get_cmb - Reserve cmb pages 111 * @lif: Logical interface 112 * @pgid: First page index 113 * @pgaddr: First page bus addr (contiguous) 114 * @order: Log base two number of pages (PAGE_SIZE) 115 * @stride_log2: Size of stride to determine CMB pool 116 * @expdb: Will be set to true if this CMB region has expdb enabled 117 * 118 * Return: zero or negative error status 119 */ 120 int ionic_get_cmb(struct ionic_lif *lif, u32 *pgid, phys_addr_t *pgaddr, 121 int order, u8 stride_log2, bool *expdb); 122 123 /** 124 * ionic_put_cmb - Release cmb pages 125 * @lif: Logical interface 126 * @pgid: First page index 127 * @order: Log base two number of pages (PAGE_SIZE) 128 */ 129 void ionic_put_cmb(struct ionic_lif *lif, u32 pgid, int order); 130 131 #endif /* _IONIC_API_H_ */ 132