1 /* 2 * Copyright (C) 2006 PA Semi, Inc 3 * 4 * Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and 5 * hardware register layouts. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PASEMI_MAC_H 21 #define PASEMI_MAC_H 22 23 #include <linux/ethtool.h> 24 #include <linux/netdevice.h> 25 #include <linux/spinlock.h> 26 #include <linux/phy.h> 27 28 /* Must be a power of two */ 29 #define RX_RING_SIZE 2048 30 #define TX_RING_SIZE 4096 31 #define CS_RING_SIZE (TX_RING_SIZE*2) 32 33 34 #define MAX_LRO_DESCRIPTORS 8 35 #define MAX_CS 2 36 37 struct pasemi_mac_txring { 38 struct pasemi_dmachan chan; /* Must be first */ 39 spinlock_t lock; 40 unsigned int size; 41 unsigned int next_to_fill; 42 unsigned int next_to_clean; 43 struct pasemi_mac_buffer *ring_info; 44 struct pasemi_mac *mac; /* Needed in intr handler */ 45 struct timer_list clean_timer; 46 }; 47 48 struct pasemi_mac_rxring { 49 struct pasemi_dmachan chan; /* Must be first */ 50 spinlock_t lock; 51 u64 *buffers; /* RX interface buffer ring */ 52 dma_addr_t buf_dma; 53 unsigned int size; 54 unsigned int next_to_fill; 55 unsigned int next_to_clean; 56 struct pasemi_mac_buffer *ring_info; 57 struct pasemi_mac *mac; /* Needed in intr handler */ 58 }; 59 60 struct pasemi_mac_csring { 61 struct pasemi_dmachan chan; 62 unsigned int size; 63 unsigned int next_to_fill; 64 int events[2]; 65 int last_event; 66 int fun; 67 }; 68 69 struct pasemi_mac { 70 struct net_device *netdev; 71 struct pci_dev *pdev; 72 struct pci_dev *dma_pdev; 73 struct pci_dev *iob_pdev; 74 struct phy_device *phydev; 75 struct napi_struct napi; 76 77 int bufsz; /* RX ring buffer size */ 78 int last_cs; 79 int num_cs; 80 u32 dma_if; 81 u8 type; 82 #define MAC_TYPE_GMAC 1 83 #define MAC_TYPE_XAUI 2 84 85 u8 mac_addr[ETH_ALEN]; 86 87 struct net_lro_mgr lro_mgr; 88 struct net_lro_desc lro_desc[MAX_LRO_DESCRIPTORS]; 89 struct timer_list rxtimer; 90 unsigned int lro_max_aggr; 91 92 struct pasemi_mac_txring *tx; 93 struct pasemi_mac_rxring *rx; 94 struct pasemi_mac_csring *cs[MAX_CS]; 95 char tx_irq_name[10]; /* "eth%d tx" */ 96 char rx_irq_name[10]; /* "eth%d rx" */ 97 int link; 98 int speed; 99 int duplex; 100 101 unsigned int msg_enable; 102 }; 103 104 /* Software status descriptor (ring_info) */ 105 struct pasemi_mac_buffer { 106 struct sk_buff *skb; 107 dma_addr_t dma; 108 }; 109 110 #define TX_DESC(tx, num) ((tx)->chan.ring_virt[(num) & (TX_RING_SIZE-1)]) 111 #define TX_DESC_INFO(tx, num) ((tx)->ring_info[(num) & (TX_RING_SIZE-1)]) 112 #define RX_DESC(rx, num) ((rx)->chan.ring_virt[(num) & (RX_RING_SIZE-1)]) 113 #define RX_DESC_INFO(rx, num) ((rx)->ring_info[(num) & (RX_RING_SIZE-1)]) 114 #define RX_BUFF(rx, num) ((rx)->buffers[(num) & (RX_RING_SIZE-1)]) 115 #define CS_DESC(cs, num) ((cs)->chan.ring_virt[(num) & (CS_RING_SIZE-1)]) 116 117 #define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \ 118 & ((ring)->size - 1)) 119 #define RING_AVAIL(ring) ((ring->size) - RING_USED(ring)) 120 121 /* PCI register offsets and formats */ 122 123 124 /* MAC CFG register offsets */ 125 enum { 126 PAS_MAC_CFG_PCFG = 0x80, 127 PAS_MAC_CFG_MACCFG = 0x84, 128 PAS_MAC_CFG_ADR0 = 0x8c, 129 PAS_MAC_CFG_ADR1 = 0x90, 130 PAS_MAC_CFG_TXP = 0x98, 131 PAS_MAC_CFG_RMON = 0x100, 132 PAS_MAC_IPC_CHNL = 0x208, 133 }; 134 135 /* MAC CFG register fields */ 136 #define PAS_MAC_CFG_PCFG_PE 0x80000000 137 #define PAS_MAC_CFG_PCFG_CE 0x40000000 138 #define PAS_MAC_CFG_PCFG_BU 0x20000000 139 #define PAS_MAC_CFG_PCFG_TT 0x10000000 140 #define PAS_MAC_CFG_PCFG_TSR_M 0x0c000000 141 #define PAS_MAC_CFG_PCFG_TSR_10M 0x00000000 142 #define PAS_MAC_CFG_PCFG_TSR_100M 0x04000000 143 #define PAS_MAC_CFG_PCFG_TSR_1G 0x08000000 144 #define PAS_MAC_CFG_PCFG_TSR_10G 0x0c000000 145 #define PAS_MAC_CFG_PCFG_T24 0x02000000 146 #define PAS_MAC_CFG_PCFG_PR 0x01000000 147 #define PAS_MAC_CFG_PCFG_CRO_M 0x00ff0000 148 #define PAS_MAC_CFG_PCFG_CRO_S 16 149 #define PAS_MAC_CFG_PCFG_IPO_M 0x0000ff00 150 #define PAS_MAC_CFG_PCFG_IPO_S 8 151 #define PAS_MAC_CFG_PCFG_S1 0x00000080 152 #define PAS_MAC_CFG_PCFG_IO_M 0x00000060 153 #define PAS_MAC_CFG_PCFG_IO_MAC 0x00000000 154 #define PAS_MAC_CFG_PCFG_IO_OFF 0x00000020 155 #define PAS_MAC_CFG_PCFG_IO_IND_ETH 0x00000040 156 #define PAS_MAC_CFG_PCFG_IO_IND_IP 0x00000060 157 #define PAS_MAC_CFG_PCFG_LP 0x00000010 158 #define PAS_MAC_CFG_PCFG_TS 0x00000008 159 #define PAS_MAC_CFG_PCFG_HD 0x00000004 160 #define PAS_MAC_CFG_PCFG_SPD_M 0x00000003 161 #define PAS_MAC_CFG_PCFG_SPD_10M 0x00000000 162 #define PAS_MAC_CFG_PCFG_SPD_100M 0x00000001 163 #define PAS_MAC_CFG_PCFG_SPD_1G 0x00000002 164 #define PAS_MAC_CFG_PCFG_SPD_10G 0x00000003 165 166 #define PAS_MAC_CFG_MACCFG_TXT_M 0x70000000 167 #define PAS_MAC_CFG_MACCFG_TXT_S 28 168 #define PAS_MAC_CFG_MACCFG_PRES_M 0x0f000000 169 #define PAS_MAC_CFG_MACCFG_PRES_S 24 170 #define PAS_MAC_CFG_MACCFG_MAXF_M 0x00ffff00 171 #define PAS_MAC_CFG_MACCFG_MAXF_S 8 172 #define PAS_MAC_CFG_MACCFG_MAXF(x) (((x) << PAS_MAC_CFG_MACCFG_MAXF_S) & \ 173 PAS_MAC_CFG_MACCFG_MAXF_M) 174 #define PAS_MAC_CFG_MACCFG_MINF_M 0x000000ff 175 #define PAS_MAC_CFG_MACCFG_MINF_S 0 176 177 #define PAS_MAC_CFG_TXP_FCF 0x01000000 178 #define PAS_MAC_CFG_TXP_FCE 0x00800000 179 #define PAS_MAC_CFG_TXP_FC 0x00400000 180 #define PAS_MAC_CFG_TXP_FPC_M 0x00300000 181 #define PAS_MAC_CFG_TXP_FPC_S 20 182 #define PAS_MAC_CFG_TXP_FPC(x) (((x) << PAS_MAC_CFG_TXP_FPC_S) & \ 183 PAS_MAC_CFG_TXP_FPC_M) 184 #define PAS_MAC_CFG_TXP_RT 0x00080000 185 #define PAS_MAC_CFG_TXP_BL 0x00040000 186 #define PAS_MAC_CFG_TXP_SL_M 0x00030000 187 #define PAS_MAC_CFG_TXP_SL_S 16 188 #define PAS_MAC_CFG_TXP_SL(x) (((x) << PAS_MAC_CFG_TXP_SL_S) & \ 189 PAS_MAC_CFG_TXP_SL_M) 190 #define PAS_MAC_CFG_TXP_COB_M 0x0000f000 191 #define PAS_MAC_CFG_TXP_COB_S 12 192 #define PAS_MAC_CFG_TXP_COB(x) (((x) << PAS_MAC_CFG_TXP_COB_S) & \ 193 PAS_MAC_CFG_TXP_COB_M) 194 #define PAS_MAC_CFG_TXP_TIFT_M 0x00000f00 195 #define PAS_MAC_CFG_TXP_TIFT_S 8 196 #define PAS_MAC_CFG_TXP_TIFT(x) (((x) << PAS_MAC_CFG_TXP_TIFT_S) & \ 197 PAS_MAC_CFG_TXP_TIFT_M) 198 #define PAS_MAC_CFG_TXP_TIFG_M 0x000000ff 199 #define PAS_MAC_CFG_TXP_TIFG_S 0 200 #define PAS_MAC_CFG_TXP_TIFG(x) (((x) << PAS_MAC_CFG_TXP_TIFG_S) & \ 201 PAS_MAC_CFG_TXP_TIFG_M) 202 203 #define PAS_MAC_RMON(r) (0x100+(r)*4) 204 205 #define PAS_MAC_IPC_CHNL_DCHNO_M 0x003f0000 206 #define PAS_MAC_IPC_CHNL_DCHNO_S 16 207 #define PAS_MAC_IPC_CHNL_DCHNO(x) (((x) << PAS_MAC_IPC_CHNL_DCHNO_S) & \ 208 PAS_MAC_IPC_CHNL_DCHNO_M) 209 #define PAS_MAC_IPC_CHNL_BCH_M 0x0000003f 210 #define PAS_MAC_IPC_CHNL_BCH_S 0 211 #define PAS_MAC_IPC_CHNL_BCH(x) (((x) << PAS_MAC_IPC_CHNL_BCH_S) & \ 212 PAS_MAC_IPC_CHNL_BCH_M) 213 214 215 #endif /* PASEMI_MAC_H */ 216