1 /* 2 * Copyright (C) 2006-2007 PA Semi, Inc 3 * 4 * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/pci.h> 21 #include <linux/slab.h> 22 #include <linux/interrupt.h> 23 #include <linux/dmaengine.h> 24 #include <linux/delay.h> 25 #include <linux/netdevice.h> 26 #include <linux/of_mdio.h> 27 #include <linux/etherdevice.h> 28 #include <asm/dma-mapping.h> 29 #include <linux/in.h> 30 #include <linux/skbuff.h> 31 32 #include <linux/ip.h> 33 #include <net/checksum.h> 34 #include <linux/prefetch.h> 35 36 #include <asm/irq.h> 37 #include <asm/firmware.h> 38 #include <asm/pasemi_dma.h> 39 40 #include "pasemi_mac.h" 41 42 /* We have our own align, since ppc64 in general has it at 0 because 43 * of design flaws in some of the server bridge chips. However, for 44 * PWRficient doing the unaligned copies is more expensive than doing 45 * unaligned DMA, so make sure the data is aligned instead. 46 */ 47 #define LOCAL_SKB_ALIGN 2 48 49 /* TODO list 50 * 51 * - Multicast support 52 * - Large MTU support 53 * - Multiqueue RX/TX 54 */ 55 56 #define PE_MIN_MTU (ETH_ZLEN + ETH_HLEN) 57 #define PE_MAX_MTU 9000 58 #define PE_DEF_MTU ETH_DATA_LEN 59 60 #define DEFAULT_MSG_ENABLE \ 61 (NETIF_MSG_DRV | \ 62 NETIF_MSG_PROBE | \ 63 NETIF_MSG_LINK | \ 64 NETIF_MSG_TIMER | \ 65 NETIF_MSG_IFDOWN | \ 66 NETIF_MSG_IFUP | \ 67 NETIF_MSG_RX_ERR | \ 68 NETIF_MSG_TX_ERR) 69 70 MODULE_LICENSE("GPL"); 71 MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>"); 72 MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver"); 73 74 static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */ 75 module_param(debug, int, 0); 76 MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value"); 77 78 extern const struct ethtool_ops pasemi_mac_ethtool_ops; 79 80 static int translation_enabled(void) 81 { 82 #if defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE) 83 return 1; 84 #else 85 return firmware_has_feature(FW_FEATURE_LPAR); 86 #endif 87 } 88 89 static void write_iob_reg(unsigned int reg, unsigned int val) 90 { 91 pasemi_write_iob_reg(reg, val); 92 } 93 94 static unsigned int read_mac_reg(const struct pasemi_mac *mac, unsigned int reg) 95 { 96 return pasemi_read_mac_reg(mac->dma_if, reg); 97 } 98 99 static void write_mac_reg(const struct pasemi_mac *mac, unsigned int reg, 100 unsigned int val) 101 { 102 pasemi_write_mac_reg(mac->dma_if, reg, val); 103 } 104 105 static unsigned int read_dma_reg(unsigned int reg) 106 { 107 return pasemi_read_dma_reg(reg); 108 } 109 110 static void write_dma_reg(unsigned int reg, unsigned int val) 111 { 112 pasemi_write_dma_reg(reg, val); 113 } 114 115 static struct pasemi_mac_rxring *rx_ring(const struct pasemi_mac *mac) 116 { 117 return mac->rx; 118 } 119 120 static struct pasemi_mac_txring *tx_ring(const struct pasemi_mac *mac) 121 { 122 return mac->tx; 123 } 124 125 static inline void prefetch_skb(const struct sk_buff *skb) 126 { 127 const void *d = skb; 128 129 prefetch(d); 130 prefetch(d+64); 131 prefetch(d+128); 132 prefetch(d+192); 133 } 134 135 static int mac_to_intf(struct pasemi_mac *mac) 136 { 137 struct pci_dev *pdev = mac->pdev; 138 u32 tmp; 139 int nintf, off, i, j; 140 int devfn = pdev->devfn; 141 142 tmp = read_dma_reg(PAS_DMA_CAP_IFI); 143 nintf = (tmp & PAS_DMA_CAP_IFI_NIN_M) >> PAS_DMA_CAP_IFI_NIN_S; 144 off = (tmp & PAS_DMA_CAP_IFI_IOFF_M) >> PAS_DMA_CAP_IFI_IOFF_S; 145 146 /* IOFF contains the offset to the registers containing the 147 * DMA interface-to-MAC-pci-id mappings, and NIN contains number 148 * of total interfaces. Each register contains 4 devfns. 149 * Just do a linear search until we find the devfn of the MAC 150 * we're trying to look up. 151 */ 152 153 for (i = 0; i < (nintf+3)/4; i++) { 154 tmp = read_dma_reg(off+4*i); 155 for (j = 0; j < 4; j++) { 156 if (((tmp >> (8*j)) & 0xff) == devfn) 157 return i*4 + j; 158 } 159 } 160 return -1; 161 } 162 163 static void pasemi_mac_intf_disable(struct pasemi_mac *mac) 164 { 165 unsigned int flags; 166 167 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); 168 flags &= ~PAS_MAC_CFG_PCFG_PE; 169 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); 170 } 171 172 static void pasemi_mac_intf_enable(struct pasemi_mac *mac) 173 { 174 unsigned int flags; 175 176 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); 177 flags |= PAS_MAC_CFG_PCFG_PE; 178 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); 179 } 180 181 static int pasemi_get_mac_addr(struct pasemi_mac *mac) 182 { 183 struct pci_dev *pdev = mac->pdev; 184 struct device_node *dn = pci_device_to_OF_node(pdev); 185 int len; 186 const u8 *maddr; 187 u8 addr[ETH_ALEN]; 188 189 if (!dn) { 190 dev_dbg(&pdev->dev, 191 "No device node for mac, not configuring\n"); 192 return -ENOENT; 193 } 194 195 maddr = of_get_property(dn, "local-mac-address", &len); 196 197 if (maddr && len == ETH_ALEN) { 198 memcpy(mac->mac_addr, maddr, ETH_ALEN); 199 return 0; 200 } 201 202 /* Some old versions of firmware mistakenly uses mac-address 203 * (and as a string) instead of a byte array in local-mac-address. 204 */ 205 206 if (maddr == NULL) 207 maddr = of_get_property(dn, "mac-address", NULL); 208 209 if (maddr == NULL) { 210 dev_warn(&pdev->dev, 211 "no mac address in device tree, not configuring\n"); 212 return -ENOENT; 213 } 214 215 if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", 216 &addr[0], &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) 217 != ETH_ALEN) { 218 dev_warn(&pdev->dev, 219 "can't parse mac address, not configuring\n"); 220 return -EINVAL; 221 } 222 223 memcpy(mac->mac_addr, addr, ETH_ALEN); 224 225 return 0; 226 } 227 228 static int pasemi_mac_set_mac_addr(struct net_device *dev, void *p) 229 { 230 struct pasemi_mac *mac = netdev_priv(dev); 231 struct sockaddr *addr = p; 232 unsigned int adr0, adr1; 233 234 if (!is_valid_ether_addr(addr->sa_data)) 235 return -EADDRNOTAVAIL; 236 237 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 238 239 adr0 = dev->dev_addr[2] << 24 | 240 dev->dev_addr[3] << 16 | 241 dev->dev_addr[4] << 8 | 242 dev->dev_addr[5]; 243 adr1 = read_mac_reg(mac, PAS_MAC_CFG_ADR1); 244 adr1 &= ~0xffff; 245 adr1 |= dev->dev_addr[0] << 8 | dev->dev_addr[1]; 246 247 pasemi_mac_intf_disable(mac); 248 write_mac_reg(mac, PAS_MAC_CFG_ADR0, adr0); 249 write_mac_reg(mac, PAS_MAC_CFG_ADR1, adr1); 250 pasemi_mac_intf_enable(mac); 251 252 return 0; 253 } 254 255 static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac, 256 const int nfrags, 257 struct sk_buff *skb, 258 const dma_addr_t *dmas) 259 { 260 int f; 261 struct pci_dev *pdev = mac->dma_pdev; 262 263 pci_unmap_single(pdev, dmas[0], skb_headlen(skb), PCI_DMA_TODEVICE); 264 265 for (f = 0; f < nfrags; f++) { 266 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 267 268 pci_unmap_page(pdev, dmas[f+1], skb_frag_size(frag), PCI_DMA_TODEVICE); 269 } 270 dev_kfree_skb_irq(skb); 271 272 /* Freed descriptor slot + main SKB ptr + nfrags additional ptrs, 273 * aligned up to a power of 2 274 */ 275 return (nfrags + 3) & ~1; 276 } 277 278 static struct pasemi_mac_csring *pasemi_mac_setup_csring(struct pasemi_mac *mac) 279 { 280 struct pasemi_mac_csring *ring; 281 u32 val; 282 unsigned int cfg; 283 int chno; 284 285 ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_csring), 286 offsetof(struct pasemi_mac_csring, chan)); 287 288 if (!ring) { 289 dev_err(&mac->pdev->dev, "Can't allocate checksum channel\n"); 290 goto out_chan; 291 } 292 293 chno = ring->chan.chno; 294 295 ring->size = CS_RING_SIZE; 296 ring->next_to_fill = 0; 297 298 /* Allocate descriptors */ 299 if (pasemi_dma_alloc_ring(&ring->chan, CS_RING_SIZE)) 300 goto out_ring_desc; 301 302 write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno), 303 PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma)); 304 val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32); 305 val |= PAS_DMA_TXCHAN_BASEU_SIZ(CS_RING_SIZE >> 3); 306 307 write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val); 308 309 ring->events[0] = pasemi_dma_alloc_flag(); 310 ring->events[1] = pasemi_dma_alloc_flag(); 311 if (ring->events[0] < 0 || ring->events[1] < 0) 312 goto out_flags; 313 314 pasemi_dma_clear_flag(ring->events[0]); 315 pasemi_dma_clear_flag(ring->events[1]); 316 317 ring->fun = pasemi_dma_alloc_fun(); 318 if (ring->fun < 0) 319 goto out_fun; 320 321 cfg = PAS_DMA_TXCHAN_CFG_TY_FUNC | PAS_DMA_TXCHAN_CFG_UP | 322 PAS_DMA_TXCHAN_CFG_TATTR(ring->fun) | 323 PAS_DMA_TXCHAN_CFG_LPSQ | PAS_DMA_TXCHAN_CFG_LPDQ; 324 325 if (translation_enabled()) 326 cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR; 327 328 write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg); 329 330 /* enable channel */ 331 pasemi_dma_start_chan(&ring->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ | 332 PAS_DMA_TXCHAN_TCMDSTA_DB | 333 PAS_DMA_TXCHAN_TCMDSTA_DE | 334 PAS_DMA_TXCHAN_TCMDSTA_DA); 335 336 return ring; 337 338 out_fun: 339 out_flags: 340 if (ring->events[0] >= 0) 341 pasemi_dma_free_flag(ring->events[0]); 342 if (ring->events[1] >= 0) 343 pasemi_dma_free_flag(ring->events[1]); 344 pasemi_dma_free_ring(&ring->chan); 345 out_ring_desc: 346 pasemi_dma_free_chan(&ring->chan); 347 out_chan: 348 349 return NULL; 350 } 351 352 static void pasemi_mac_setup_csrings(struct pasemi_mac *mac) 353 { 354 int i; 355 mac->cs[0] = pasemi_mac_setup_csring(mac); 356 if (mac->type == MAC_TYPE_XAUI) 357 mac->cs[1] = pasemi_mac_setup_csring(mac); 358 else 359 mac->cs[1] = 0; 360 361 for (i = 0; i < MAX_CS; i++) 362 if (mac->cs[i]) 363 mac->num_cs++; 364 } 365 366 static void pasemi_mac_free_csring(struct pasemi_mac_csring *csring) 367 { 368 pasemi_dma_stop_chan(&csring->chan); 369 pasemi_dma_free_flag(csring->events[0]); 370 pasemi_dma_free_flag(csring->events[1]); 371 pasemi_dma_free_ring(&csring->chan); 372 pasemi_dma_free_chan(&csring->chan); 373 pasemi_dma_free_fun(csring->fun); 374 } 375 376 static int pasemi_mac_setup_rx_resources(const struct net_device *dev) 377 { 378 struct pasemi_mac_rxring *ring; 379 struct pasemi_mac *mac = netdev_priv(dev); 380 int chno; 381 unsigned int cfg; 382 383 ring = pasemi_dma_alloc_chan(RXCHAN, sizeof(struct pasemi_mac_rxring), 384 offsetof(struct pasemi_mac_rxring, chan)); 385 386 if (!ring) { 387 dev_err(&mac->pdev->dev, "Can't allocate RX channel\n"); 388 goto out_chan; 389 } 390 chno = ring->chan.chno; 391 392 spin_lock_init(&ring->lock); 393 394 ring->size = RX_RING_SIZE; 395 ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) * 396 RX_RING_SIZE, GFP_KERNEL); 397 398 if (!ring->ring_info) 399 goto out_ring_info; 400 401 /* Allocate descriptors */ 402 if (pasemi_dma_alloc_ring(&ring->chan, RX_RING_SIZE)) 403 goto out_ring_desc; 404 405 ring->buffers = dma_zalloc_coherent(&mac->dma_pdev->dev, 406 RX_RING_SIZE * sizeof(u64), 407 &ring->buf_dma, GFP_KERNEL); 408 if (!ring->buffers) 409 goto out_ring_desc; 410 411 write_dma_reg(PAS_DMA_RXCHAN_BASEL(chno), 412 PAS_DMA_RXCHAN_BASEL_BRBL(ring->chan.ring_dma)); 413 414 write_dma_reg(PAS_DMA_RXCHAN_BASEU(chno), 415 PAS_DMA_RXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32) | 416 PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 3)); 417 418 cfg = PAS_DMA_RXCHAN_CFG_HBU(2); 419 420 if (translation_enabled()) 421 cfg |= PAS_DMA_RXCHAN_CFG_CTR; 422 423 write_dma_reg(PAS_DMA_RXCHAN_CFG(chno), cfg); 424 425 write_dma_reg(PAS_DMA_RXINT_BASEL(mac->dma_if), 426 PAS_DMA_RXINT_BASEL_BRBL(ring->buf_dma)); 427 428 write_dma_reg(PAS_DMA_RXINT_BASEU(mac->dma_if), 429 PAS_DMA_RXINT_BASEU_BRBH(ring->buf_dma >> 32) | 430 PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3)); 431 432 cfg = PAS_DMA_RXINT_CFG_DHL(2) | PAS_DMA_RXINT_CFG_L2 | 433 PAS_DMA_RXINT_CFG_LW | PAS_DMA_RXINT_CFG_RBP | 434 PAS_DMA_RXINT_CFG_HEN; 435 436 if (translation_enabled()) 437 cfg |= PAS_DMA_RXINT_CFG_ITRR | PAS_DMA_RXINT_CFG_ITR; 438 439 write_dma_reg(PAS_DMA_RXINT_CFG(mac->dma_if), cfg); 440 441 ring->next_to_fill = 0; 442 ring->next_to_clean = 0; 443 ring->mac = mac; 444 mac->rx = ring; 445 446 return 0; 447 448 out_ring_desc: 449 kfree(ring->ring_info); 450 out_ring_info: 451 pasemi_dma_free_chan(&ring->chan); 452 out_chan: 453 return -ENOMEM; 454 } 455 456 static struct pasemi_mac_txring * 457 pasemi_mac_setup_tx_resources(const struct net_device *dev) 458 { 459 struct pasemi_mac *mac = netdev_priv(dev); 460 u32 val; 461 struct pasemi_mac_txring *ring; 462 unsigned int cfg; 463 int chno; 464 465 ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_txring), 466 offsetof(struct pasemi_mac_txring, chan)); 467 468 if (!ring) { 469 dev_err(&mac->pdev->dev, "Can't allocate TX channel\n"); 470 goto out_chan; 471 } 472 473 chno = ring->chan.chno; 474 475 spin_lock_init(&ring->lock); 476 477 ring->size = TX_RING_SIZE; 478 ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) * 479 TX_RING_SIZE, GFP_KERNEL); 480 if (!ring->ring_info) 481 goto out_ring_info; 482 483 /* Allocate descriptors */ 484 if (pasemi_dma_alloc_ring(&ring->chan, TX_RING_SIZE)) 485 goto out_ring_desc; 486 487 write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno), 488 PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma)); 489 val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32); 490 val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3); 491 492 write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val); 493 494 cfg = PAS_DMA_TXCHAN_CFG_TY_IFACE | 495 PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) | 496 PAS_DMA_TXCHAN_CFG_UP | 497 PAS_DMA_TXCHAN_CFG_WT(4); 498 499 if (translation_enabled()) 500 cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR; 501 502 write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg); 503 504 ring->next_to_fill = 0; 505 ring->next_to_clean = 0; 506 ring->mac = mac; 507 508 return ring; 509 510 out_ring_desc: 511 kfree(ring->ring_info); 512 out_ring_info: 513 pasemi_dma_free_chan(&ring->chan); 514 out_chan: 515 return NULL; 516 } 517 518 static void pasemi_mac_free_tx_resources(struct pasemi_mac *mac) 519 { 520 struct pasemi_mac_txring *txring = tx_ring(mac); 521 unsigned int i, j; 522 struct pasemi_mac_buffer *info; 523 dma_addr_t dmas[MAX_SKB_FRAGS+1]; 524 int freed, nfrags; 525 int start, limit; 526 527 start = txring->next_to_clean; 528 limit = txring->next_to_fill; 529 530 /* Compensate for when fill has wrapped and clean has not */ 531 if (start > limit) 532 limit += TX_RING_SIZE; 533 534 for (i = start; i < limit; i += freed) { 535 info = &txring->ring_info[(i+1) & (TX_RING_SIZE-1)]; 536 if (info->dma && info->skb) { 537 nfrags = skb_shinfo(info->skb)->nr_frags; 538 for (j = 0; j <= nfrags; j++) 539 dmas[j] = txring->ring_info[(i+1+j) & 540 (TX_RING_SIZE-1)].dma; 541 freed = pasemi_mac_unmap_tx_skb(mac, nfrags, 542 info->skb, dmas); 543 } else { 544 freed = 2; 545 } 546 } 547 548 kfree(txring->ring_info); 549 pasemi_dma_free_chan(&txring->chan); 550 551 } 552 553 static void pasemi_mac_free_rx_buffers(struct pasemi_mac *mac) 554 { 555 struct pasemi_mac_rxring *rx = rx_ring(mac); 556 unsigned int i; 557 struct pasemi_mac_buffer *info; 558 559 for (i = 0; i < RX_RING_SIZE; i++) { 560 info = &RX_DESC_INFO(rx, i); 561 if (info->skb && info->dma) { 562 pci_unmap_single(mac->dma_pdev, 563 info->dma, 564 info->skb->len, 565 PCI_DMA_FROMDEVICE); 566 dev_kfree_skb_any(info->skb); 567 } 568 info->dma = 0; 569 info->skb = NULL; 570 } 571 572 for (i = 0; i < RX_RING_SIZE; i++) 573 RX_BUFF(rx, i) = 0; 574 } 575 576 static void pasemi_mac_free_rx_resources(struct pasemi_mac *mac) 577 { 578 pasemi_mac_free_rx_buffers(mac); 579 580 dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64), 581 rx_ring(mac)->buffers, rx_ring(mac)->buf_dma); 582 583 kfree(rx_ring(mac)->ring_info); 584 pasemi_dma_free_chan(&rx_ring(mac)->chan); 585 mac->rx = NULL; 586 } 587 588 static void pasemi_mac_replenish_rx_ring(struct net_device *dev, 589 const int limit) 590 { 591 const struct pasemi_mac *mac = netdev_priv(dev); 592 struct pasemi_mac_rxring *rx = rx_ring(mac); 593 int fill, count; 594 595 if (limit <= 0) 596 return; 597 598 fill = rx_ring(mac)->next_to_fill; 599 for (count = 0; count < limit; count++) { 600 struct pasemi_mac_buffer *info = &RX_DESC_INFO(rx, fill); 601 u64 *buff = &RX_BUFF(rx, fill); 602 struct sk_buff *skb; 603 dma_addr_t dma; 604 605 /* Entry in use? */ 606 WARN_ON(*buff); 607 608 skb = netdev_alloc_skb(dev, mac->bufsz); 609 skb_reserve(skb, LOCAL_SKB_ALIGN); 610 611 if (unlikely(!skb)) 612 break; 613 614 dma = pci_map_single(mac->dma_pdev, skb->data, 615 mac->bufsz - LOCAL_SKB_ALIGN, 616 PCI_DMA_FROMDEVICE); 617 618 if (unlikely(pci_dma_mapping_error(mac->dma_pdev, dma))) { 619 dev_kfree_skb_irq(info->skb); 620 break; 621 } 622 623 info->skb = skb; 624 info->dma = dma; 625 *buff = XCT_RXB_LEN(mac->bufsz) | XCT_RXB_ADDR(dma); 626 fill++; 627 } 628 629 wmb(); 630 631 write_dma_reg(PAS_DMA_RXINT_INCR(mac->dma_if), count); 632 633 rx_ring(mac)->next_to_fill = (rx_ring(mac)->next_to_fill + count) & 634 (RX_RING_SIZE - 1); 635 } 636 637 static void pasemi_mac_restart_rx_intr(const struct pasemi_mac *mac) 638 { 639 struct pasemi_mac_rxring *rx = rx_ring(mac); 640 unsigned int reg, pcnt; 641 /* Re-enable packet count interrupts: finally 642 * ack the packet count interrupt we got in rx_intr. 643 */ 644 645 pcnt = *rx->chan.status & PAS_STATUS_PCNT_M; 646 647 reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC; 648 649 if (*rx->chan.status & PAS_STATUS_TIMER) 650 reg |= PAS_IOB_DMA_RXCH_RESET_TINTC; 651 652 write_iob_reg(PAS_IOB_DMA_RXCH_RESET(mac->rx->chan.chno), reg); 653 } 654 655 static void pasemi_mac_restart_tx_intr(const struct pasemi_mac *mac) 656 { 657 unsigned int reg, pcnt; 658 659 /* Re-enable packet count interrupts */ 660 pcnt = *tx_ring(mac)->chan.status & PAS_STATUS_PCNT_M; 661 662 reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC; 663 664 write_iob_reg(PAS_IOB_DMA_TXCH_RESET(tx_ring(mac)->chan.chno), reg); 665 } 666 667 668 static inline void pasemi_mac_rx_error(const struct pasemi_mac *mac, 669 const u64 macrx) 670 { 671 unsigned int rcmdsta, ccmdsta; 672 struct pasemi_dmachan *chan = &rx_ring(mac)->chan; 673 674 if (!netif_msg_rx_err(mac)) 675 return; 676 677 rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); 678 ccmdsta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno)); 679 680 printk(KERN_ERR "pasemi_mac: rx error. macrx %016llx, rx status %llx\n", 681 macrx, *chan->status); 682 683 printk(KERN_ERR "pasemi_mac: rcmdsta %08x ccmdsta %08x\n", 684 rcmdsta, ccmdsta); 685 } 686 687 static inline void pasemi_mac_tx_error(const struct pasemi_mac *mac, 688 const u64 mactx) 689 { 690 unsigned int cmdsta; 691 struct pasemi_dmachan *chan = &tx_ring(mac)->chan; 692 693 if (!netif_msg_tx_err(mac)) 694 return; 695 696 cmdsta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno)); 697 698 printk(KERN_ERR "pasemi_mac: tx error. mactx 0x%016llx, "\ 699 "tx status 0x%016llx\n", mactx, *chan->status); 700 701 printk(KERN_ERR "pasemi_mac: tcmdsta 0x%08x\n", cmdsta); 702 } 703 704 static int pasemi_mac_clean_rx(struct pasemi_mac_rxring *rx, 705 const int limit) 706 { 707 const struct pasemi_dmachan *chan = &rx->chan; 708 struct pasemi_mac *mac = rx->mac; 709 struct pci_dev *pdev = mac->dma_pdev; 710 unsigned int n; 711 int count, buf_index, tot_bytes, packets; 712 struct pasemi_mac_buffer *info; 713 struct sk_buff *skb; 714 unsigned int len; 715 u64 macrx, eval; 716 dma_addr_t dma; 717 718 tot_bytes = 0; 719 packets = 0; 720 721 spin_lock(&rx->lock); 722 723 n = rx->next_to_clean; 724 725 prefetch(&RX_DESC(rx, n)); 726 727 for (count = 0; count < limit; count++) { 728 macrx = RX_DESC(rx, n); 729 prefetch(&RX_DESC(rx, n+4)); 730 731 if ((macrx & XCT_MACRX_E) || 732 (*chan->status & PAS_STATUS_ERROR)) 733 pasemi_mac_rx_error(mac, macrx); 734 735 if (!(macrx & XCT_MACRX_O)) 736 break; 737 738 info = NULL; 739 740 BUG_ON(!(macrx & XCT_MACRX_RR_8BRES)); 741 742 eval = (RX_DESC(rx, n+1) & XCT_RXRES_8B_EVAL_M) >> 743 XCT_RXRES_8B_EVAL_S; 744 buf_index = eval-1; 745 746 dma = (RX_DESC(rx, n+2) & XCT_PTR_ADDR_M); 747 info = &RX_DESC_INFO(rx, buf_index); 748 749 skb = info->skb; 750 751 prefetch_skb(skb); 752 753 len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S; 754 755 pci_unmap_single(pdev, dma, mac->bufsz - LOCAL_SKB_ALIGN, 756 PCI_DMA_FROMDEVICE); 757 758 if (macrx & XCT_MACRX_CRC) { 759 /* CRC error flagged */ 760 mac->netdev->stats.rx_errors++; 761 mac->netdev->stats.rx_crc_errors++; 762 /* No need to free skb, it'll be reused */ 763 goto next; 764 } 765 766 info->skb = NULL; 767 info->dma = 0; 768 769 if (likely((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK)) { 770 skb->ip_summed = CHECKSUM_UNNECESSARY; 771 skb->csum = (macrx & XCT_MACRX_CSUM_M) >> 772 XCT_MACRX_CSUM_S; 773 } else { 774 skb_checksum_none_assert(skb); 775 } 776 777 packets++; 778 tot_bytes += len; 779 780 /* Don't include CRC */ 781 skb_put(skb, len-4); 782 783 skb->protocol = eth_type_trans(skb, mac->netdev); 784 napi_gro_receive(&mac->napi, skb); 785 786 next: 787 RX_DESC(rx, n) = 0; 788 RX_DESC(rx, n+1) = 0; 789 790 /* Need to zero it out since hardware doesn't, since the 791 * replenish loop uses it to tell when it's done. 792 */ 793 RX_BUFF(rx, buf_index) = 0; 794 795 n += 4; 796 } 797 798 if (n > RX_RING_SIZE) { 799 /* Errata 5971 workaround: L2 target of headers */ 800 write_iob_reg(PAS_IOB_COM_PKTHDRCNT, 0); 801 n &= (RX_RING_SIZE-1); 802 } 803 804 rx_ring(mac)->next_to_clean = n; 805 806 /* Increase is in number of 16-byte entries, and since each descriptor 807 * with an 8BRES takes up 3x8 bytes (padded to 4x8), increase with 808 * count*2. 809 */ 810 write_dma_reg(PAS_DMA_RXCHAN_INCR(mac->rx->chan.chno), count << 1); 811 812 pasemi_mac_replenish_rx_ring(mac->netdev, count); 813 814 mac->netdev->stats.rx_bytes += tot_bytes; 815 mac->netdev->stats.rx_packets += packets; 816 817 spin_unlock(&rx_ring(mac)->lock); 818 819 return count; 820 } 821 822 /* Can't make this too large or we blow the kernel stack limits */ 823 #define TX_CLEAN_BATCHSIZE (128/MAX_SKB_FRAGS) 824 825 static int pasemi_mac_clean_tx(struct pasemi_mac_txring *txring) 826 { 827 struct pasemi_dmachan *chan = &txring->chan; 828 struct pasemi_mac *mac = txring->mac; 829 int i, j; 830 unsigned int start, descr_count, buf_count, batch_limit; 831 unsigned int ring_limit; 832 unsigned int total_count; 833 unsigned long flags; 834 struct sk_buff *skbs[TX_CLEAN_BATCHSIZE]; 835 dma_addr_t dmas[TX_CLEAN_BATCHSIZE][MAX_SKB_FRAGS+1]; 836 int nf[TX_CLEAN_BATCHSIZE]; 837 int nr_frags; 838 839 total_count = 0; 840 batch_limit = TX_CLEAN_BATCHSIZE; 841 restart: 842 spin_lock_irqsave(&txring->lock, flags); 843 844 start = txring->next_to_clean; 845 ring_limit = txring->next_to_fill; 846 847 prefetch(&TX_DESC_INFO(txring, start+1).skb); 848 849 /* Compensate for when fill has wrapped but clean has not */ 850 if (start > ring_limit) 851 ring_limit += TX_RING_SIZE; 852 853 buf_count = 0; 854 descr_count = 0; 855 856 for (i = start; 857 descr_count < batch_limit && i < ring_limit; 858 i += buf_count) { 859 u64 mactx = TX_DESC(txring, i); 860 struct sk_buff *skb; 861 862 if ((mactx & XCT_MACTX_E) || 863 (*chan->status & PAS_STATUS_ERROR)) 864 pasemi_mac_tx_error(mac, mactx); 865 866 /* Skip over control descriptors */ 867 if (!(mactx & XCT_MACTX_LLEN_M)) { 868 TX_DESC(txring, i) = 0; 869 TX_DESC(txring, i+1) = 0; 870 buf_count = 2; 871 continue; 872 } 873 874 skb = TX_DESC_INFO(txring, i+1).skb; 875 nr_frags = TX_DESC_INFO(txring, i).dma; 876 877 if (unlikely(mactx & XCT_MACTX_O)) 878 /* Not yet transmitted */ 879 break; 880 881 buf_count = 2 + nr_frags; 882 /* Since we always fill with an even number of entries, make 883 * sure we skip any unused one at the end as well. 884 */ 885 if (buf_count & 1) 886 buf_count++; 887 888 for (j = 0; j <= nr_frags; j++) 889 dmas[descr_count][j] = TX_DESC_INFO(txring, i+1+j).dma; 890 891 skbs[descr_count] = skb; 892 nf[descr_count] = nr_frags; 893 894 TX_DESC(txring, i) = 0; 895 TX_DESC(txring, i+1) = 0; 896 897 descr_count++; 898 } 899 txring->next_to_clean = i & (TX_RING_SIZE-1); 900 901 spin_unlock_irqrestore(&txring->lock, flags); 902 netif_wake_queue(mac->netdev); 903 904 for (i = 0; i < descr_count; i++) 905 pasemi_mac_unmap_tx_skb(mac, nf[i], skbs[i], dmas[i]); 906 907 total_count += descr_count; 908 909 /* If the batch was full, try to clean more */ 910 if (descr_count == batch_limit) 911 goto restart; 912 913 return total_count; 914 } 915 916 917 static irqreturn_t pasemi_mac_rx_intr(int irq, void *data) 918 { 919 const struct pasemi_mac_rxring *rxring = data; 920 struct pasemi_mac *mac = rxring->mac; 921 const struct pasemi_dmachan *chan = &rxring->chan; 922 unsigned int reg; 923 924 if (!(*chan->status & PAS_STATUS_CAUSE_M)) 925 return IRQ_NONE; 926 927 /* Don't reset packet count so it won't fire again but clear 928 * all others. 929 */ 930 931 reg = 0; 932 if (*chan->status & PAS_STATUS_SOFT) 933 reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; 934 if (*chan->status & PAS_STATUS_ERROR) 935 reg |= PAS_IOB_DMA_RXCH_RESET_DINTC; 936 937 napi_schedule(&mac->napi); 938 939 write_iob_reg(PAS_IOB_DMA_RXCH_RESET(chan->chno), reg); 940 941 return IRQ_HANDLED; 942 } 943 944 #define TX_CLEAN_INTERVAL HZ 945 946 static void pasemi_mac_tx_timer(unsigned long data) 947 { 948 struct pasemi_mac_txring *txring = (struct pasemi_mac_txring *)data; 949 struct pasemi_mac *mac = txring->mac; 950 951 pasemi_mac_clean_tx(txring); 952 953 mod_timer(&txring->clean_timer, jiffies + TX_CLEAN_INTERVAL); 954 955 pasemi_mac_restart_tx_intr(mac); 956 } 957 958 static irqreturn_t pasemi_mac_tx_intr(int irq, void *data) 959 { 960 struct pasemi_mac_txring *txring = data; 961 const struct pasemi_dmachan *chan = &txring->chan; 962 struct pasemi_mac *mac = txring->mac; 963 unsigned int reg; 964 965 if (!(*chan->status & PAS_STATUS_CAUSE_M)) 966 return IRQ_NONE; 967 968 reg = 0; 969 970 if (*chan->status & PAS_STATUS_SOFT) 971 reg |= PAS_IOB_DMA_TXCH_RESET_SINTC; 972 if (*chan->status & PAS_STATUS_ERROR) 973 reg |= PAS_IOB_DMA_TXCH_RESET_DINTC; 974 975 mod_timer(&txring->clean_timer, jiffies + (TX_CLEAN_INTERVAL)*2); 976 977 napi_schedule(&mac->napi); 978 979 if (reg) 980 write_iob_reg(PAS_IOB_DMA_TXCH_RESET(chan->chno), reg); 981 982 return IRQ_HANDLED; 983 } 984 985 static void pasemi_adjust_link(struct net_device *dev) 986 { 987 struct pasemi_mac *mac = netdev_priv(dev); 988 int msg; 989 unsigned int flags; 990 unsigned int new_flags; 991 992 if (!dev->phydev->link) { 993 /* If no link, MAC speed settings don't matter. Just report 994 * link down and return. 995 */ 996 if (mac->link && netif_msg_link(mac)) 997 printk(KERN_INFO "%s: Link is down.\n", dev->name); 998 999 netif_carrier_off(dev); 1000 pasemi_mac_intf_disable(mac); 1001 mac->link = 0; 1002 1003 return; 1004 } else { 1005 pasemi_mac_intf_enable(mac); 1006 netif_carrier_on(dev); 1007 } 1008 1009 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); 1010 new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M | 1011 PAS_MAC_CFG_PCFG_TSR_M); 1012 1013 if (!dev->phydev->duplex) 1014 new_flags |= PAS_MAC_CFG_PCFG_HD; 1015 1016 switch (dev->phydev->speed) { 1017 case 1000: 1018 new_flags |= PAS_MAC_CFG_PCFG_SPD_1G | 1019 PAS_MAC_CFG_PCFG_TSR_1G; 1020 break; 1021 case 100: 1022 new_flags |= PAS_MAC_CFG_PCFG_SPD_100M | 1023 PAS_MAC_CFG_PCFG_TSR_100M; 1024 break; 1025 case 10: 1026 new_flags |= PAS_MAC_CFG_PCFG_SPD_10M | 1027 PAS_MAC_CFG_PCFG_TSR_10M; 1028 break; 1029 default: 1030 printk("Unsupported speed %d\n", dev->phydev->speed); 1031 } 1032 1033 /* Print on link or speed/duplex change */ 1034 msg = mac->link != dev->phydev->link || flags != new_flags; 1035 1036 mac->duplex = dev->phydev->duplex; 1037 mac->speed = dev->phydev->speed; 1038 mac->link = dev->phydev->link; 1039 1040 if (new_flags != flags) 1041 write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags); 1042 1043 if (msg && netif_msg_link(mac)) 1044 printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n", 1045 dev->name, mac->speed, mac->duplex ? "full" : "half"); 1046 } 1047 1048 static int pasemi_mac_phy_init(struct net_device *dev) 1049 { 1050 struct pasemi_mac *mac = netdev_priv(dev); 1051 struct device_node *dn, *phy_dn; 1052 struct phy_device *phydev; 1053 1054 dn = pci_device_to_OF_node(mac->pdev); 1055 phy_dn = of_parse_phandle(dn, "phy-handle", 0); 1056 of_node_put(phy_dn); 1057 1058 mac->link = 0; 1059 mac->speed = 0; 1060 mac->duplex = -1; 1061 1062 phydev = of_phy_connect(dev, phy_dn, &pasemi_adjust_link, 0, 1063 PHY_INTERFACE_MODE_SGMII); 1064 1065 if (!phydev) { 1066 printk(KERN_ERR "%s: Could not attach to phy\n", dev->name); 1067 return -ENODEV; 1068 } 1069 1070 return 0; 1071 } 1072 1073 1074 static int pasemi_mac_open(struct net_device *dev) 1075 { 1076 struct pasemi_mac *mac = netdev_priv(dev); 1077 unsigned int flags; 1078 int i, ret; 1079 1080 flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) | 1081 PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) | 1082 PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12); 1083 1084 write_mac_reg(mac, PAS_MAC_CFG_TXP, flags); 1085 1086 ret = pasemi_mac_setup_rx_resources(dev); 1087 if (ret) 1088 goto out_rx_resources; 1089 1090 mac->tx = pasemi_mac_setup_tx_resources(dev); 1091 1092 if (!mac->tx) 1093 goto out_tx_ring; 1094 1095 /* We might already have allocated rings in case mtu was changed 1096 * before interface was brought up. 1097 */ 1098 if (dev->mtu > 1500 && !mac->num_cs) { 1099 pasemi_mac_setup_csrings(mac); 1100 if (!mac->num_cs) 1101 goto out_tx_ring; 1102 } 1103 1104 /* Zero out rmon counters */ 1105 for (i = 0; i < 32; i++) 1106 write_mac_reg(mac, PAS_MAC_RMON(i), 0); 1107 1108 /* 0x3ff with 33MHz clock is about 31us */ 1109 write_iob_reg(PAS_IOB_DMA_COM_TIMEOUTCFG, 1110 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0x3ff)); 1111 1112 write_iob_reg(PAS_IOB_DMA_RXCH_CFG(mac->rx->chan.chno), 1113 PAS_IOB_DMA_RXCH_CFG_CNTTH(256)); 1114 1115 write_iob_reg(PAS_IOB_DMA_TXCH_CFG(mac->tx->chan.chno), 1116 PAS_IOB_DMA_TXCH_CFG_CNTTH(32)); 1117 1118 write_mac_reg(mac, PAS_MAC_IPC_CHNL, 1119 PAS_MAC_IPC_CHNL_DCHNO(mac->rx->chan.chno) | 1120 PAS_MAC_IPC_CHNL_BCH(mac->rx->chan.chno)); 1121 1122 /* enable rx if */ 1123 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 1124 PAS_DMA_RXINT_RCMDSTA_EN | 1125 PAS_DMA_RXINT_RCMDSTA_DROPS_M | 1126 PAS_DMA_RXINT_RCMDSTA_BP | 1127 PAS_DMA_RXINT_RCMDSTA_OO | 1128 PAS_DMA_RXINT_RCMDSTA_BT); 1129 1130 /* enable rx channel */ 1131 pasemi_dma_start_chan(&rx_ring(mac)->chan, PAS_DMA_RXCHAN_CCMDSTA_DU | 1132 PAS_DMA_RXCHAN_CCMDSTA_OD | 1133 PAS_DMA_RXCHAN_CCMDSTA_FD | 1134 PAS_DMA_RXCHAN_CCMDSTA_DT); 1135 1136 /* enable tx channel */ 1137 pasemi_dma_start_chan(&tx_ring(mac)->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ | 1138 PAS_DMA_TXCHAN_TCMDSTA_DB | 1139 PAS_DMA_TXCHAN_TCMDSTA_DE | 1140 PAS_DMA_TXCHAN_TCMDSTA_DA); 1141 1142 pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE); 1143 1144 write_dma_reg(PAS_DMA_RXCHAN_INCR(rx_ring(mac)->chan.chno), 1145 RX_RING_SIZE>>1); 1146 1147 /* Clear out any residual packet count state from firmware */ 1148 pasemi_mac_restart_rx_intr(mac); 1149 pasemi_mac_restart_tx_intr(mac); 1150 1151 flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE; 1152 1153 if (mac->type == MAC_TYPE_GMAC) 1154 flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G; 1155 else 1156 flags |= PAS_MAC_CFG_PCFG_TSR_10G | PAS_MAC_CFG_PCFG_SPD_10G; 1157 1158 /* Enable interface in MAC */ 1159 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); 1160 1161 ret = pasemi_mac_phy_init(dev); 1162 if (ret) { 1163 /* Since we won't get link notification, just enable RX */ 1164 pasemi_mac_intf_enable(mac); 1165 if (mac->type == MAC_TYPE_GMAC) { 1166 /* Warn for missing PHY on SGMII (1Gig) ports */ 1167 dev_warn(&mac->pdev->dev, 1168 "PHY init failed: %d.\n", ret); 1169 dev_warn(&mac->pdev->dev, 1170 "Defaulting to 1Gbit full duplex\n"); 1171 } 1172 } 1173 1174 netif_start_queue(dev); 1175 napi_enable(&mac->napi); 1176 1177 snprintf(mac->tx_irq_name, sizeof(mac->tx_irq_name), "%s tx", 1178 dev->name); 1179 1180 ret = request_irq(mac->tx->chan.irq, pasemi_mac_tx_intr, 0, 1181 mac->tx_irq_name, mac->tx); 1182 if (ret) { 1183 dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n", 1184 mac->tx->chan.irq, ret); 1185 goto out_tx_int; 1186 } 1187 1188 snprintf(mac->rx_irq_name, sizeof(mac->rx_irq_name), "%s rx", 1189 dev->name); 1190 1191 ret = request_irq(mac->rx->chan.irq, pasemi_mac_rx_intr, 0, 1192 mac->rx_irq_name, mac->rx); 1193 if (ret) { 1194 dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n", 1195 mac->rx->chan.irq, ret); 1196 goto out_rx_int; 1197 } 1198 1199 if (dev->phydev) 1200 phy_start(dev->phydev); 1201 1202 setup_timer(&mac->tx->clean_timer, pasemi_mac_tx_timer, 1203 (unsigned long)mac->tx); 1204 mod_timer(&mac->tx->clean_timer, jiffies + HZ); 1205 1206 return 0; 1207 1208 out_rx_int: 1209 free_irq(mac->tx->chan.irq, mac->tx); 1210 out_tx_int: 1211 napi_disable(&mac->napi); 1212 netif_stop_queue(dev); 1213 out_tx_ring: 1214 if (mac->tx) 1215 pasemi_mac_free_tx_resources(mac); 1216 pasemi_mac_free_rx_resources(mac); 1217 out_rx_resources: 1218 1219 return ret; 1220 } 1221 1222 #define MAX_RETRIES 5000 1223 1224 static void pasemi_mac_pause_txchan(struct pasemi_mac *mac) 1225 { 1226 unsigned int sta, retries; 1227 int txch = tx_ring(mac)->chan.chno; 1228 1229 write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), 1230 PAS_DMA_TXCHAN_TCMDSTA_ST); 1231 1232 for (retries = 0; retries < MAX_RETRIES; retries++) { 1233 sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch)); 1234 if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)) 1235 break; 1236 cond_resched(); 1237 } 1238 1239 if (sta & PAS_DMA_TXCHAN_TCMDSTA_ACT) 1240 dev_err(&mac->dma_pdev->dev, 1241 "Failed to stop tx channel, tcmdsta %08x\n", sta); 1242 1243 write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), 0); 1244 } 1245 1246 static void pasemi_mac_pause_rxchan(struct pasemi_mac *mac) 1247 { 1248 unsigned int sta, retries; 1249 int rxch = rx_ring(mac)->chan.chno; 1250 1251 write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), 1252 PAS_DMA_RXCHAN_CCMDSTA_ST); 1253 for (retries = 0; retries < MAX_RETRIES; retries++) { 1254 sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch)); 1255 if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)) 1256 break; 1257 cond_resched(); 1258 } 1259 1260 if (sta & PAS_DMA_RXCHAN_CCMDSTA_ACT) 1261 dev_err(&mac->dma_pdev->dev, 1262 "Failed to stop rx channel, ccmdsta 08%x\n", sta); 1263 write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), 0); 1264 } 1265 1266 static void pasemi_mac_pause_rxint(struct pasemi_mac *mac) 1267 { 1268 unsigned int sta, retries; 1269 1270 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 1271 PAS_DMA_RXINT_RCMDSTA_ST); 1272 for (retries = 0; retries < MAX_RETRIES; retries++) { 1273 sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); 1274 if (!(sta & PAS_DMA_RXINT_RCMDSTA_ACT)) 1275 break; 1276 cond_resched(); 1277 } 1278 1279 if (sta & PAS_DMA_RXINT_RCMDSTA_ACT) 1280 dev_err(&mac->dma_pdev->dev, 1281 "Failed to stop rx interface, rcmdsta %08x\n", sta); 1282 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0); 1283 } 1284 1285 static int pasemi_mac_close(struct net_device *dev) 1286 { 1287 struct pasemi_mac *mac = netdev_priv(dev); 1288 unsigned int sta; 1289 int rxch, txch, i; 1290 1291 rxch = rx_ring(mac)->chan.chno; 1292 txch = tx_ring(mac)->chan.chno; 1293 1294 if (dev->phydev) { 1295 phy_stop(dev->phydev); 1296 phy_disconnect(dev->phydev); 1297 } 1298 1299 del_timer_sync(&mac->tx->clean_timer); 1300 1301 netif_stop_queue(dev); 1302 napi_disable(&mac->napi); 1303 1304 sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); 1305 if (sta & (PAS_DMA_RXINT_RCMDSTA_BP | 1306 PAS_DMA_RXINT_RCMDSTA_OO | 1307 PAS_DMA_RXINT_RCMDSTA_BT)) 1308 printk(KERN_DEBUG "pasemi_mac: rcmdsta error: 0x%08x\n", sta); 1309 1310 sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch)); 1311 if (sta & (PAS_DMA_RXCHAN_CCMDSTA_DU | 1312 PAS_DMA_RXCHAN_CCMDSTA_OD | 1313 PAS_DMA_RXCHAN_CCMDSTA_FD | 1314 PAS_DMA_RXCHAN_CCMDSTA_DT)) 1315 printk(KERN_DEBUG "pasemi_mac: ccmdsta error: 0x%08x\n", sta); 1316 1317 sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch)); 1318 if (sta & (PAS_DMA_TXCHAN_TCMDSTA_SZ | PAS_DMA_TXCHAN_TCMDSTA_DB | 1319 PAS_DMA_TXCHAN_TCMDSTA_DE | PAS_DMA_TXCHAN_TCMDSTA_DA)) 1320 printk(KERN_DEBUG "pasemi_mac: tcmdsta error: 0x%08x\n", sta); 1321 1322 /* Clean out any pending buffers */ 1323 pasemi_mac_clean_tx(tx_ring(mac)); 1324 pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE); 1325 1326 pasemi_mac_pause_txchan(mac); 1327 pasemi_mac_pause_rxint(mac); 1328 pasemi_mac_pause_rxchan(mac); 1329 pasemi_mac_intf_disable(mac); 1330 1331 free_irq(mac->tx->chan.irq, mac->tx); 1332 free_irq(mac->rx->chan.irq, mac->rx); 1333 1334 for (i = 0; i < mac->num_cs; i++) { 1335 pasemi_mac_free_csring(mac->cs[i]); 1336 mac->cs[i] = NULL; 1337 } 1338 1339 mac->num_cs = 0; 1340 1341 /* Free resources */ 1342 pasemi_mac_free_rx_resources(mac); 1343 pasemi_mac_free_tx_resources(mac); 1344 1345 return 0; 1346 } 1347 1348 static void pasemi_mac_queue_csdesc(const struct sk_buff *skb, 1349 const dma_addr_t *map, 1350 const unsigned int *map_size, 1351 struct pasemi_mac_txring *txring, 1352 struct pasemi_mac_csring *csring) 1353 { 1354 u64 fund; 1355 dma_addr_t cs_dest; 1356 const int nh_off = skb_network_offset(skb); 1357 const int nh_len = skb_network_header_len(skb); 1358 const int nfrags = skb_shinfo(skb)->nr_frags; 1359 int cs_size, i, fill, hdr, cpyhdr, evt; 1360 dma_addr_t csdma; 1361 1362 fund = XCT_FUN_ST | XCT_FUN_RR_8BRES | 1363 XCT_FUN_O | XCT_FUN_FUN(csring->fun) | 1364 XCT_FUN_CRM_SIG | XCT_FUN_LLEN(skb->len - nh_off) | 1365 XCT_FUN_SHL(nh_len >> 2) | XCT_FUN_SE; 1366 1367 switch (ip_hdr(skb)->protocol) { 1368 case IPPROTO_TCP: 1369 fund |= XCT_FUN_SIG_TCP4; 1370 /* TCP checksum is 16 bytes into the header */ 1371 cs_dest = map[0] + skb_transport_offset(skb) + 16; 1372 break; 1373 case IPPROTO_UDP: 1374 fund |= XCT_FUN_SIG_UDP4; 1375 /* UDP checksum is 6 bytes into the header */ 1376 cs_dest = map[0] + skb_transport_offset(skb) + 6; 1377 break; 1378 default: 1379 BUG(); 1380 } 1381 1382 /* Do the checksum offloaded */ 1383 fill = csring->next_to_fill; 1384 hdr = fill; 1385 1386 CS_DESC(csring, fill++) = fund; 1387 /* Room for 8BRES. Checksum result is really 2 bytes into it */ 1388 csdma = csring->chan.ring_dma + (fill & (CS_RING_SIZE-1)) * 8 + 2; 1389 CS_DESC(csring, fill++) = 0; 1390 1391 CS_DESC(csring, fill) = XCT_PTR_LEN(map_size[0]-nh_off) | XCT_PTR_ADDR(map[0]+nh_off); 1392 for (i = 1; i <= nfrags; i++) 1393 CS_DESC(csring, fill+i) = XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]); 1394 1395 fill += i; 1396 if (fill & 1) 1397 fill++; 1398 1399 /* Copy the result into the TCP packet */ 1400 cpyhdr = fill; 1401 CS_DESC(csring, fill++) = XCT_FUN_O | XCT_FUN_FUN(csring->fun) | 1402 XCT_FUN_LLEN(2) | XCT_FUN_SE; 1403 CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(cs_dest) | XCT_PTR_T; 1404 CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(csdma); 1405 fill++; 1406 1407 evt = !csring->last_event; 1408 csring->last_event = evt; 1409 1410 /* Event handshaking with MAC TX */ 1411 CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O | 1412 CTRL_CMD_ETYPE_SET | CTRL_CMD_REG(csring->events[evt]); 1413 CS_DESC(csring, fill++) = 0; 1414 CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O | 1415 CTRL_CMD_ETYPE_WCLR | CTRL_CMD_REG(csring->events[!evt]); 1416 CS_DESC(csring, fill++) = 0; 1417 csring->next_to_fill = fill & (CS_RING_SIZE-1); 1418 1419 cs_size = fill - hdr; 1420 write_dma_reg(PAS_DMA_TXCHAN_INCR(csring->chan.chno), (cs_size) >> 1); 1421 1422 /* TX-side event handshaking */ 1423 fill = txring->next_to_fill; 1424 TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O | 1425 CTRL_CMD_ETYPE_WSET | CTRL_CMD_REG(csring->events[evt]); 1426 TX_DESC(txring, fill++) = 0; 1427 TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O | 1428 CTRL_CMD_ETYPE_CLR | CTRL_CMD_REG(csring->events[!evt]); 1429 TX_DESC(txring, fill++) = 0; 1430 txring->next_to_fill = fill; 1431 1432 write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), 2); 1433 } 1434 1435 static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev) 1436 { 1437 struct pasemi_mac * const mac = netdev_priv(dev); 1438 struct pasemi_mac_txring * const txring = tx_ring(mac); 1439 struct pasemi_mac_csring *csring; 1440 u64 dflags = 0; 1441 u64 mactx; 1442 dma_addr_t map[MAX_SKB_FRAGS+1]; 1443 unsigned int map_size[MAX_SKB_FRAGS+1]; 1444 unsigned long flags; 1445 int i, nfrags; 1446 int fill; 1447 const int nh_off = skb_network_offset(skb); 1448 const int nh_len = skb_network_header_len(skb); 1449 1450 prefetch(&txring->ring_info); 1451 1452 dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_CRC_PAD; 1453 1454 nfrags = skb_shinfo(skb)->nr_frags; 1455 1456 map[0] = pci_map_single(mac->dma_pdev, skb->data, skb_headlen(skb), 1457 PCI_DMA_TODEVICE); 1458 map_size[0] = skb_headlen(skb); 1459 if (pci_dma_mapping_error(mac->dma_pdev, map[0])) 1460 goto out_err_nolock; 1461 1462 for (i = 0; i < nfrags; i++) { 1463 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1464 1465 map[i + 1] = skb_frag_dma_map(&mac->dma_pdev->dev, frag, 0, 1466 skb_frag_size(frag), DMA_TO_DEVICE); 1467 map_size[i+1] = skb_frag_size(frag); 1468 if (dma_mapping_error(&mac->dma_pdev->dev, map[i + 1])) { 1469 nfrags = i; 1470 goto out_err_nolock; 1471 } 1472 } 1473 1474 if (skb->ip_summed == CHECKSUM_PARTIAL && skb->len <= 1540) { 1475 switch (ip_hdr(skb)->protocol) { 1476 case IPPROTO_TCP: 1477 dflags |= XCT_MACTX_CSUM_TCP; 1478 dflags |= XCT_MACTX_IPH(nh_len >> 2); 1479 dflags |= XCT_MACTX_IPO(nh_off); 1480 break; 1481 case IPPROTO_UDP: 1482 dflags |= XCT_MACTX_CSUM_UDP; 1483 dflags |= XCT_MACTX_IPH(nh_len >> 2); 1484 dflags |= XCT_MACTX_IPO(nh_off); 1485 break; 1486 default: 1487 WARN_ON(1); 1488 } 1489 } 1490 1491 mactx = dflags | XCT_MACTX_LLEN(skb->len); 1492 1493 spin_lock_irqsave(&txring->lock, flags); 1494 1495 /* Avoid stepping on the same cache line that the DMA controller 1496 * is currently about to send, so leave at least 8 words available. 1497 * Total free space needed is mactx + fragments + 8 1498 */ 1499 if (RING_AVAIL(txring) < nfrags + 14) { 1500 /* no room -- stop the queue and wait for tx intr */ 1501 netif_stop_queue(dev); 1502 goto out_err; 1503 } 1504 1505 /* Queue up checksum + event descriptors, if needed */ 1506 if (mac->num_cs && skb->ip_summed == CHECKSUM_PARTIAL && skb->len > 1540) { 1507 csring = mac->cs[mac->last_cs]; 1508 mac->last_cs = (mac->last_cs + 1) % mac->num_cs; 1509 1510 pasemi_mac_queue_csdesc(skb, map, map_size, txring, csring); 1511 } 1512 1513 fill = txring->next_to_fill; 1514 TX_DESC(txring, fill) = mactx; 1515 TX_DESC_INFO(txring, fill).dma = nfrags; 1516 fill++; 1517 TX_DESC_INFO(txring, fill).skb = skb; 1518 for (i = 0; i <= nfrags; i++) { 1519 TX_DESC(txring, fill+i) = 1520 XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]); 1521 TX_DESC_INFO(txring, fill+i).dma = map[i]; 1522 } 1523 1524 /* We have to add an even number of 8-byte entries to the ring 1525 * even if the last one is unused. That means always an odd number 1526 * of pointers + one mactx descriptor. 1527 */ 1528 if (nfrags & 1) 1529 nfrags++; 1530 1531 txring->next_to_fill = (fill + nfrags + 1) & (TX_RING_SIZE-1); 1532 1533 dev->stats.tx_packets++; 1534 dev->stats.tx_bytes += skb->len; 1535 1536 spin_unlock_irqrestore(&txring->lock, flags); 1537 1538 write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), (nfrags+2) >> 1); 1539 1540 return NETDEV_TX_OK; 1541 1542 out_err: 1543 spin_unlock_irqrestore(&txring->lock, flags); 1544 out_err_nolock: 1545 while (nfrags--) 1546 pci_unmap_single(mac->dma_pdev, map[nfrags], map_size[nfrags], 1547 PCI_DMA_TODEVICE); 1548 1549 return NETDEV_TX_BUSY; 1550 } 1551 1552 static void pasemi_mac_set_rx_mode(struct net_device *dev) 1553 { 1554 const struct pasemi_mac *mac = netdev_priv(dev); 1555 unsigned int flags; 1556 1557 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); 1558 1559 /* Set promiscuous */ 1560 if (dev->flags & IFF_PROMISC) 1561 flags |= PAS_MAC_CFG_PCFG_PR; 1562 else 1563 flags &= ~PAS_MAC_CFG_PCFG_PR; 1564 1565 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); 1566 } 1567 1568 1569 static int pasemi_mac_poll(struct napi_struct *napi, int budget) 1570 { 1571 struct pasemi_mac *mac = container_of(napi, struct pasemi_mac, napi); 1572 int pkts; 1573 1574 pasemi_mac_clean_tx(tx_ring(mac)); 1575 pkts = pasemi_mac_clean_rx(rx_ring(mac), budget); 1576 if (pkts < budget) { 1577 /* all done, no more packets present */ 1578 napi_complete_done(napi, pkts); 1579 1580 pasemi_mac_restart_rx_intr(mac); 1581 pasemi_mac_restart_tx_intr(mac); 1582 } 1583 return pkts; 1584 } 1585 1586 #ifdef CONFIG_NET_POLL_CONTROLLER 1587 /* 1588 * Polling 'interrupt' - used by things like netconsole to send skbs 1589 * without having to re-enable interrupts. It's not called while 1590 * the interrupt routine is executing. 1591 */ 1592 static void pasemi_mac_netpoll(struct net_device *dev) 1593 { 1594 const struct pasemi_mac *mac = netdev_priv(dev); 1595 1596 disable_irq(mac->tx->chan.irq); 1597 pasemi_mac_tx_intr(mac->tx->chan.irq, mac->tx); 1598 enable_irq(mac->tx->chan.irq); 1599 1600 disable_irq(mac->rx->chan.irq); 1601 pasemi_mac_rx_intr(mac->rx->chan.irq, mac->rx); 1602 enable_irq(mac->rx->chan.irq); 1603 } 1604 #endif 1605 1606 static int pasemi_mac_change_mtu(struct net_device *dev, int new_mtu) 1607 { 1608 struct pasemi_mac *mac = netdev_priv(dev); 1609 unsigned int reg; 1610 unsigned int rcmdsta = 0; 1611 int running; 1612 int ret = 0; 1613 1614 running = netif_running(dev); 1615 1616 if (running) { 1617 /* Need to stop the interface, clean out all already 1618 * received buffers, free all unused buffers on the RX 1619 * interface ring, then finally re-fill the rx ring with 1620 * the new-size buffers and restart. 1621 */ 1622 1623 napi_disable(&mac->napi); 1624 netif_tx_disable(dev); 1625 pasemi_mac_intf_disable(mac); 1626 1627 rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); 1628 pasemi_mac_pause_rxint(mac); 1629 pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE); 1630 pasemi_mac_free_rx_buffers(mac); 1631 1632 } 1633 1634 /* Setup checksum channels if large MTU and none already allocated */ 1635 if (new_mtu > PE_DEF_MTU && !mac->num_cs) { 1636 pasemi_mac_setup_csrings(mac); 1637 if (!mac->num_cs) { 1638 ret = -ENOMEM; 1639 goto out; 1640 } 1641 } 1642 1643 /* Change maxf, i.e. what size frames are accepted. 1644 * Need room for ethernet header and CRC word 1645 */ 1646 reg = read_mac_reg(mac, PAS_MAC_CFG_MACCFG); 1647 reg &= ~PAS_MAC_CFG_MACCFG_MAXF_M; 1648 reg |= PAS_MAC_CFG_MACCFG_MAXF(new_mtu + ETH_HLEN + 4); 1649 write_mac_reg(mac, PAS_MAC_CFG_MACCFG, reg); 1650 1651 dev->mtu = new_mtu; 1652 /* MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */ 1653 mac->bufsz = new_mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128; 1654 1655 out: 1656 if (running) { 1657 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 1658 rcmdsta | PAS_DMA_RXINT_RCMDSTA_EN); 1659 1660 rx_ring(mac)->next_to_fill = 0; 1661 pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE-1); 1662 1663 napi_enable(&mac->napi); 1664 netif_start_queue(dev); 1665 pasemi_mac_intf_enable(mac); 1666 } 1667 1668 return ret; 1669 } 1670 1671 static const struct net_device_ops pasemi_netdev_ops = { 1672 .ndo_open = pasemi_mac_open, 1673 .ndo_stop = pasemi_mac_close, 1674 .ndo_start_xmit = pasemi_mac_start_tx, 1675 .ndo_set_rx_mode = pasemi_mac_set_rx_mode, 1676 .ndo_set_mac_address = pasemi_mac_set_mac_addr, 1677 .ndo_change_mtu = pasemi_mac_change_mtu, 1678 .ndo_validate_addr = eth_validate_addr, 1679 #ifdef CONFIG_NET_POLL_CONTROLLER 1680 .ndo_poll_controller = pasemi_mac_netpoll, 1681 #endif 1682 }; 1683 1684 static int 1685 pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1686 { 1687 struct net_device *dev; 1688 struct pasemi_mac *mac; 1689 int err, ret; 1690 1691 err = pci_enable_device(pdev); 1692 if (err) 1693 return err; 1694 1695 dev = alloc_etherdev(sizeof(struct pasemi_mac)); 1696 if (dev == NULL) { 1697 err = -ENOMEM; 1698 goto out_disable_device; 1699 } 1700 1701 pci_set_drvdata(pdev, dev); 1702 SET_NETDEV_DEV(dev, &pdev->dev); 1703 1704 mac = netdev_priv(dev); 1705 1706 mac->pdev = pdev; 1707 mac->netdev = dev; 1708 1709 netif_napi_add(dev, &mac->napi, pasemi_mac_poll, 64); 1710 1711 dev->features = NETIF_F_IP_CSUM | NETIF_F_LLTX | NETIF_F_SG | 1712 NETIF_F_HIGHDMA | NETIF_F_GSO; 1713 1714 mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL); 1715 if (!mac->dma_pdev) { 1716 dev_err(&mac->pdev->dev, "Can't find DMA Controller\n"); 1717 err = -ENODEV; 1718 goto out; 1719 } 1720 1721 mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); 1722 if (!mac->iob_pdev) { 1723 dev_err(&mac->pdev->dev, "Can't find I/O Bridge\n"); 1724 err = -ENODEV; 1725 goto out; 1726 } 1727 1728 /* get mac addr from device tree */ 1729 if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) { 1730 err = -ENODEV; 1731 goto out; 1732 } 1733 memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr)); 1734 1735 ret = mac_to_intf(mac); 1736 if (ret < 0) { 1737 dev_err(&mac->pdev->dev, "Can't map DMA interface\n"); 1738 err = -ENODEV; 1739 goto out; 1740 } 1741 mac->dma_if = ret; 1742 1743 switch (pdev->device) { 1744 case 0xa005: 1745 mac->type = MAC_TYPE_GMAC; 1746 break; 1747 case 0xa006: 1748 mac->type = MAC_TYPE_XAUI; 1749 break; 1750 default: 1751 err = -ENODEV; 1752 goto out; 1753 } 1754 1755 dev->netdev_ops = &pasemi_netdev_ops; 1756 dev->mtu = PE_DEF_MTU; 1757 1758 /* MTU range: 64 - 9000 */ 1759 dev->min_mtu = PE_MIN_MTU; 1760 dev->max_mtu = PE_MAX_MTU; 1761 1762 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */ 1763 mac->bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128; 1764 1765 dev->ethtool_ops = &pasemi_mac_ethtool_ops; 1766 1767 if (err) 1768 goto out; 1769 1770 mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 1771 1772 /* Enable most messages by default */ 1773 mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; 1774 1775 err = register_netdev(dev); 1776 1777 if (err) { 1778 dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n", 1779 err); 1780 goto out; 1781 } else if (netif_msg_probe(mac)) { 1782 printk(KERN_INFO "%s: PA Semi %s: intf %d, hw addr %pM\n", 1783 dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI", 1784 mac->dma_if, dev->dev_addr); 1785 } 1786 1787 return err; 1788 1789 out: 1790 pci_dev_put(mac->iob_pdev); 1791 pci_dev_put(mac->dma_pdev); 1792 1793 free_netdev(dev); 1794 out_disable_device: 1795 pci_disable_device(pdev); 1796 return err; 1797 1798 } 1799 1800 static void pasemi_mac_remove(struct pci_dev *pdev) 1801 { 1802 struct net_device *netdev = pci_get_drvdata(pdev); 1803 struct pasemi_mac *mac; 1804 1805 if (!netdev) 1806 return; 1807 1808 mac = netdev_priv(netdev); 1809 1810 unregister_netdev(netdev); 1811 1812 pci_disable_device(pdev); 1813 pci_dev_put(mac->dma_pdev); 1814 pci_dev_put(mac->iob_pdev); 1815 1816 pasemi_dma_free_chan(&mac->tx->chan); 1817 pasemi_dma_free_chan(&mac->rx->chan); 1818 1819 free_netdev(netdev); 1820 } 1821 1822 static const struct pci_device_id pasemi_mac_pci_tbl[] = { 1823 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) }, 1824 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) }, 1825 { }, 1826 }; 1827 1828 MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl); 1829 1830 static struct pci_driver pasemi_mac_driver = { 1831 .name = "pasemi_mac", 1832 .id_table = pasemi_mac_pci_tbl, 1833 .probe = pasemi_mac_probe, 1834 .remove = pasemi_mac_remove, 1835 }; 1836 1837 static void __exit pasemi_mac_cleanup_module(void) 1838 { 1839 pci_unregister_driver(&pasemi_mac_driver); 1840 } 1841 1842 int pasemi_mac_init_module(void) 1843 { 1844 int err; 1845 1846 err = pasemi_dma_init(); 1847 if (err) 1848 return err; 1849 1850 return pci_register_driver(&pasemi_mac_driver); 1851 } 1852 1853 module_init(pasemi_mac_init_module); 1854 module_exit(pasemi_mac_cleanup_module); 1855