1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2006-2007 PA Semi, Inc 4 * 5 * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs 6 */ 7 8 #include <linux/module.h> 9 #include <linux/pci.h> 10 #include <linux/slab.h> 11 #include <linux/interrupt.h> 12 #include <linux/dmaengine.h> 13 #include <linux/delay.h> 14 #include <linux/hex.h> 15 #include <linux/netdevice.h> 16 #include <linux/of_mdio.h> 17 #include <linux/etherdevice.h> 18 #include <asm/dma-mapping.h> 19 #include <linux/in.h> 20 #include <linux/skbuff.h> 21 22 #include <linux/ip.h> 23 #include <net/checksum.h> 24 #include <linux/prefetch.h> 25 26 #include <asm/irq.h> 27 #include <asm/firmware.h> 28 #include <asm/pasemi_dma.h> 29 30 #include "pasemi_mac.h" 31 32 /* We have our own align, since ppc64 in general has it at 0 because 33 * of design flaws in some of the server bridge chips. However, for 34 * PWRficient doing the unaligned copies is more expensive than doing 35 * unaligned DMA, so make sure the data is aligned instead. 36 */ 37 #define LOCAL_SKB_ALIGN 2 38 39 /* TODO list 40 * 41 * - Multicast support 42 * - Large MTU support 43 * - Multiqueue RX/TX 44 */ 45 46 #define PE_MIN_MTU (ETH_ZLEN + ETH_HLEN) 47 #define PE_MAX_MTU 9000 48 #define PE_DEF_MTU ETH_DATA_LEN 49 50 #define DEFAULT_MSG_ENABLE \ 51 (NETIF_MSG_DRV | \ 52 NETIF_MSG_PROBE | \ 53 NETIF_MSG_LINK | \ 54 NETIF_MSG_TIMER | \ 55 NETIF_MSG_IFDOWN | \ 56 NETIF_MSG_IFUP | \ 57 NETIF_MSG_RX_ERR | \ 58 NETIF_MSG_TX_ERR) 59 60 MODULE_LICENSE("GPL"); 61 MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>"); 62 MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver"); 63 64 static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */ 65 module_param(debug, int, 0); 66 MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value"); 67 68 extern const struct ethtool_ops pasemi_mac_ethtool_ops; 69 70 static int translation_enabled(void) 71 { 72 #if defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE) 73 return 1; 74 #else 75 return firmware_has_feature(FW_FEATURE_LPAR); 76 #endif 77 } 78 79 static void write_iob_reg(unsigned int reg, unsigned int val) 80 { 81 pasemi_write_iob_reg(reg, val); 82 } 83 84 static unsigned int read_mac_reg(const struct pasemi_mac *mac, unsigned int reg) 85 { 86 return pasemi_read_mac_reg(mac->dma_if, reg); 87 } 88 89 static void write_mac_reg(const struct pasemi_mac *mac, unsigned int reg, 90 unsigned int val) 91 { 92 pasemi_write_mac_reg(mac->dma_if, reg, val); 93 } 94 95 static unsigned int read_dma_reg(unsigned int reg) 96 { 97 return pasemi_read_dma_reg(reg); 98 } 99 100 static void write_dma_reg(unsigned int reg, unsigned int val) 101 { 102 pasemi_write_dma_reg(reg, val); 103 } 104 105 static struct pasemi_mac_rxring *rx_ring(const struct pasemi_mac *mac) 106 { 107 return mac->rx; 108 } 109 110 static struct pasemi_mac_txring *tx_ring(const struct pasemi_mac *mac) 111 { 112 return mac->tx; 113 } 114 115 static inline void prefetch_skb(const struct sk_buff *skb) 116 { 117 const void *d = skb; 118 119 prefetch(d); 120 prefetch(d+64); 121 prefetch(d+128); 122 prefetch(d+192); 123 } 124 125 static int mac_to_intf(struct pasemi_mac *mac) 126 { 127 struct pci_dev *pdev = mac->pdev; 128 u32 tmp; 129 int nintf, off, i, j; 130 int devfn = pdev->devfn; 131 132 tmp = read_dma_reg(PAS_DMA_CAP_IFI); 133 nintf = (tmp & PAS_DMA_CAP_IFI_NIN_M) >> PAS_DMA_CAP_IFI_NIN_S; 134 off = (tmp & PAS_DMA_CAP_IFI_IOFF_M) >> PAS_DMA_CAP_IFI_IOFF_S; 135 136 /* IOFF contains the offset to the registers containing the 137 * DMA interface-to-MAC-pci-id mappings, and NIN contains number 138 * of total interfaces. Each register contains 4 devfns. 139 * Just do a linear search until we find the devfn of the MAC 140 * we're trying to look up. 141 */ 142 143 for (i = 0; i < (nintf+3)/4; i++) { 144 tmp = read_dma_reg(off+4*i); 145 for (j = 0; j < 4; j++) { 146 if (((tmp >> (8*j)) & 0xff) == devfn) 147 return i*4 + j; 148 } 149 } 150 return -1; 151 } 152 153 static void pasemi_mac_intf_disable(struct pasemi_mac *mac) 154 { 155 unsigned int flags; 156 157 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); 158 flags &= ~PAS_MAC_CFG_PCFG_PE; 159 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); 160 } 161 162 static void pasemi_mac_intf_enable(struct pasemi_mac *mac) 163 { 164 unsigned int flags; 165 166 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); 167 flags |= PAS_MAC_CFG_PCFG_PE; 168 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); 169 } 170 171 static int pasemi_get_mac_addr(struct pasemi_mac *mac) 172 { 173 struct pci_dev *pdev = mac->pdev; 174 struct device_node *dn = pci_device_to_OF_node(pdev); 175 int len; 176 const u8 *maddr; 177 u8 addr[ETH_ALEN]; 178 179 if (!dn) { 180 dev_dbg(&pdev->dev, 181 "No device node for mac, not configuring\n"); 182 return -ENOENT; 183 } 184 185 maddr = of_get_property(dn, "local-mac-address", &len); 186 187 if (maddr && len == ETH_ALEN) { 188 memcpy(mac->mac_addr, maddr, ETH_ALEN); 189 return 0; 190 } 191 192 /* Some old versions of firmware mistakenly uses mac-address 193 * (and as a string) instead of a byte array in local-mac-address. 194 */ 195 196 if (maddr == NULL) 197 maddr = of_get_property(dn, "mac-address", NULL); 198 199 if (maddr == NULL) { 200 dev_warn(&pdev->dev, 201 "no mac address in device tree, not configuring\n"); 202 return -ENOENT; 203 } 204 205 if (!mac_pton(maddr, addr)) { 206 dev_warn(&pdev->dev, 207 "can't parse mac address, not configuring\n"); 208 return -EINVAL; 209 } 210 211 memcpy(mac->mac_addr, addr, ETH_ALEN); 212 213 return 0; 214 } 215 216 static int pasemi_mac_set_mac_addr(struct net_device *dev, void *p) 217 { 218 struct pasemi_mac *mac = netdev_priv(dev); 219 struct sockaddr *addr = p; 220 unsigned int adr0, adr1; 221 222 if (!is_valid_ether_addr(addr->sa_data)) 223 return -EADDRNOTAVAIL; 224 225 eth_hw_addr_set(dev, addr->sa_data); 226 227 adr0 = dev->dev_addr[2] << 24 | 228 dev->dev_addr[3] << 16 | 229 dev->dev_addr[4] << 8 | 230 dev->dev_addr[5]; 231 adr1 = read_mac_reg(mac, PAS_MAC_CFG_ADR1); 232 adr1 &= ~0xffff; 233 adr1 |= dev->dev_addr[0] << 8 | dev->dev_addr[1]; 234 235 pasemi_mac_intf_disable(mac); 236 write_mac_reg(mac, PAS_MAC_CFG_ADR0, adr0); 237 write_mac_reg(mac, PAS_MAC_CFG_ADR1, adr1); 238 pasemi_mac_intf_enable(mac); 239 240 return 0; 241 } 242 243 static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac, 244 const int nfrags, 245 struct sk_buff *skb, 246 const dma_addr_t *dmas) 247 { 248 int f; 249 struct pci_dev *pdev = mac->dma_pdev; 250 251 dma_unmap_single(&pdev->dev, dmas[0], skb_headlen(skb), DMA_TO_DEVICE); 252 253 for (f = 0; f < nfrags; f++) { 254 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 255 256 dma_unmap_page(&pdev->dev, dmas[f + 1], skb_frag_size(frag), 257 DMA_TO_DEVICE); 258 } 259 dev_kfree_skb_irq(skb); 260 261 /* Freed descriptor slot + main SKB ptr + nfrags additional ptrs, 262 * aligned up to a power of 2 263 */ 264 return (nfrags + 3) & ~1; 265 } 266 267 static struct pasemi_mac_csring *pasemi_mac_setup_csring(struct pasemi_mac *mac) 268 { 269 struct pasemi_mac_csring *ring; 270 u32 val; 271 unsigned int cfg; 272 int chno; 273 274 ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_csring), 275 offsetof(struct pasemi_mac_csring, chan)); 276 277 if (!ring) { 278 dev_err(&mac->pdev->dev, "Can't allocate checksum channel\n"); 279 goto out_chan; 280 } 281 282 chno = ring->chan.chno; 283 284 ring->size = CS_RING_SIZE; 285 ring->next_to_fill = 0; 286 287 /* Allocate descriptors */ 288 if (pasemi_dma_alloc_ring(&ring->chan, CS_RING_SIZE)) 289 goto out_ring_desc; 290 291 write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno), 292 PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma)); 293 val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32); 294 val |= PAS_DMA_TXCHAN_BASEU_SIZ(CS_RING_SIZE >> 3); 295 296 write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val); 297 298 ring->events[0] = pasemi_dma_alloc_flag(); 299 ring->events[1] = pasemi_dma_alloc_flag(); 300 if (ring->events[0] < 0 || ring->events[1] < 0) 301 goto out_flags; 302 303 pasemi_dma_clear_flag(ring->events[0]); 304 pasemi_dma_clear_flag(ring->events[1]); 305 306 ring->fun = pasemi_dma_alloc_fun(); 307 if (ring->fun < 0) 308 goto out_fun; 309 310 cfg = PAS_DMA_TXCHAN_CFG_TY_FUNC | PAS_DMA_TXCHAN_CFG_UP | 311 PAS_DMA_TXCHAN_CFG_TATTR(ring->fun) | 312 PAS_DMA_TXCHAN_CFG_LPSQ | PAS_DMA_TXCHAN_CFG_LPDQ; 313 314 if (translation_enabled()) 315 cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR; 316 317 write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg); 318 319 /* enable channel */ 320 pasemi_dma_start_chan(&ring->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ | 321 PAS_DMA_TXCHAN_TCMDSTA_DB | 322 PAS_DMA_TXCHAN_TCMDSTA_DE | 323 PAS_DMA_TXCHAN_TCMDSTA_DA); 324 325 return ring; 326 327 out_fun: 328 out_flags: 329 if (ring->events[0] >= 0) 330 pasemi_dma_free_flag(ring->events[0]); 331 if (ring->events[1] >= 0) 332 pasemi_dma_free_flag(ring->events[1]); 333 pasemi_dma_free_ring(&ring->chan); 334 out_ring_desc: 335 pasemi_dma_free_chan(&ring->chan); 336 out_chan: 337 338 return NULL; 339 } 340 341 static void pasemi_mac_setup_csrings(struct pasemi_mac *mac) 342 { 343 int i; 344 mac->cs[0] = pasemi_mac_setup_csring(mac); 345 if (mac->type == MAC_TYPE_XAUI) 346 mac->cs[1] = pasemi_mac_setup_csring(mac); 347 else 348 mac->cs[1] = 0; 349 350 for (i = 0; i < MAX_CS; i++) 351 if (mac->cs[i]) 352 mac->num_cs++; 353 } 354 355 static void pasemi_mac_free_csring(struct pasemi_mac_csring *csring) 356 { 357 pasemi_dma_stop_chan(&csring->chan); 358 pasemi_dma_free_flag(csring->events[0]); 359 pasemi_dma_free_flag(csring->events[1]); 360 pasemi_dma_free_ring(&csring->chan); 361 pasemi_dma_free_chan(&csring->chan); 362 pasemi_dma_free_fun(csring->fun); 363 } 364 365 static int pasemi_mac_setup_rx_resources(const struct net_device *dev) 366 { 367 struct pasemi_mac_rxring *ring; 368 struct pasemi_mac *mac = netdev_priv(dev); 369 int chno; 370 unsigned int cfg; 371 372 ring = pasemi_dma_alloc_chan(RXCHAN, sizeof(struct pasemi_mac_rxring), 373 offsetof(struct pasemi_mac_rxring, chan)); 374 375 if (!ring) { 376 dev_err(&mac->pdev->dev, "Can't allocate RX channel\n"); 377 goto out_chan; 378 } 379 chno = ring->chan.chno; 380 381 spin_lock_init(&ring->lock); 382 383 ring->size = RX_RING_SIZE; 384 ring->ring_info = kcalloc(RX_RING_SIZE, 385 sizeof(struct pasemi_mac_buffer), 386 GFP_KERNEL); 387 388 if (!ring->ring_info) 389 goto out_ring_info; 390 391 /* Allocate descriptors */ 392 if (pasemi_dma_alloc_ring(&ring->chan, RX_RING_SIZE)) 393 goto out_ring_desc; 394 395 ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev, 396 RX_RING_SIZE * sizeof(u64), 397 &ring->buf_dma, GFP_KERNEL); 398 if (!ring->buffers) 399 goto out_ring_desc; 400 401 write_dma_reg(PAS_DMA_RXCHAN_BASEL(chno), 402 PAS_DMA_RXCHAN_BASEL_BRBL(ring->chan.ring_dma)); 403 404 write_dma_reg(PAS_DMA_RXCHAN_BASEU(chno), 405 PAS_DMA_RXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32) | 406 PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 3)); 407 408 cfg = PAS_DMA_RXCHAN_CFG_HBU(2); 409 410 if (translation_enabled()) 411 cfg |= PAS_DMA_RXCHAN_CFG_CTR; 412 413 write_dma_reg(PAS_DMA_RXCHAN_CFG(chno), cfg); 414 415 write_dma_reg(PAS_DMA_RXINT_BASEL(mac->dma_if), 416 PAS_DMA_RXINT_BASEL_BRBL(ring->buf_dma)); 417 418 write_dma_reg(PAS_DMA_RXINT_BASEU(mac->dma_if), 419 PAS_DMA_RXINT_BASEU_BRBH(ring->buf_dma >> 32) | 420 PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3)); 421 422 cfg = PAS_DMA_RXINT_CFG_DHL(2) | PAS_DMA_RXINT_CFG_L2 | 423 PAS_DMA_RXINT_CFG_LW | PAS_DMA_RXINT_CFG_RBP | 424 PAS_DMA_RXINT_CFG_HEN; 425 426 if (translation_enabled()) 427 cfg |= PAS_DMA_RXINT_CFG_ITRR | PAS_DMA_RXINT_CFG_ITR; 428 429 write_dma_reg(PAS_DMA_RXINT_CFG(mac->dma_if), cfg); 430 431 ring->next_to_fill = 0; 432 ring->next_to_clean = 0; 433 ring->mac = mac; 434 mac->rx = ring; 435 436 return 0; 437 438 out_ring_desc: 439 kfree(ring->ring_info); 440 out_ring_info: 441 pasemi_dma_free_chan(&ring->chan); 442 out_chan: 443 return -ENOMEM; 444 } 445 446 static struct pasemi_mac_txring * 447 pasemi_mac_setup_tx_resources(const struct net_device *dev) 448 { 449 struct pasemi_mac *mac = netdev_priv(dev); 450 u32 val; 451 struct pasemi_mac_txring *ring; 452 unsigned int cfg; 453 int chno; 454 455 ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_txring), 456 offsetof(struct pasemi_mac_txring, chan)); 457 458 if (!ring) { 459 dev_err(&mac->pdev->dev, "Can't allocate TX channel\n"); 460 goto out_chan; 461 } 462 463 chno = ring->chan.chno; 464 465 spin_lock_init(&ring->lock); 466 467 ring->size = TX_RING_SIZE; 468 ring->ring_info = kcalloc(TX_RING_SIZE, 469 sizeof(struct pasemi_mac_buffer), 470 GFP_KERNEL); 471 if (!ring->ring_info) 472 goto out_ring_info; 473 474 /* Allocate descriptors */ 475 if (pasemi_dma_alloc_ring(&ring->chan, TX_RING_SIZE)) 476 goto out_ring_desc; 477 478 write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno), 479 PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma)); 480 val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32); 481 val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3); 482 483 write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val); 484 485 cfg = PAS_DMA_TXCHAN_CFG_TY_IFACE | 486 PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) | 487 PAS_DMA_TXCHAN_CFG_UP | 488 PAS_DMA_TXCHAN_CFG_WT(4); 489 490 if (translation_enabled()) 491 cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR; 492 493 write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg); 494 495 ring->next_to_fill = 0; 496 ring->next_to_clean = 0; 497 ring->mac = mac; 498 499 return ring; 500 501 out_ring_desc: 502 kfree(ring->ring_info); 503 out_ring_info: 504 pasemi_dma_free_chan(&ring->chan); 505 out_chan: 506 return NULL; 507 } 508 509 static void pasemi_mac_free_tx_resources(struct pasemi_mac *mac) 510 { 511 struct pasemi_mac_txring *txring = tx_ring(mac); 512 unsigned int i, j; 513 struct pasemi_mac_buffer *info; 514 dma_addr_t dmas[MAX_SKB_FRAGS+1]; 515 int freed, nfrags; 516 int start, limit; 517 518 start = txring->next_to_clean; 519 limit = txring->next_to_fill; 520 521 /* Compensate for when fill has wrapped and clean has not */ 522 if (start > limit) 523 limit += TX_RING_SIZE; 524 525 for (i = start; i < limit; i += freed) { 526 info = &txring->ring_info[(i+1) & (TX_RING_SIZE-1)]; 527 if (info->dma && info->skb) { 528 nfrags = skb_shinfo(info->skb)->nr_frags; 529 for (j = 0; j <= nfrags; j++) 530 dmas[j] = txring->ring_info[(i+1+j) & 531 (TX_RING_SIZE-1)].dma; 532 freed = pasemi_mac_unmap_tx_skb(mac, nfrags, 533 info->skb, dmas); 534 } else { 535 freed = 2; 536 } 537 } 538 539 kfree(txring->ring_info); 540 pasemi_dma_free_chan(&txring->chan); 541 542 } 543 544 static void pasemi_mac_free_rx_buffers(struct pasemi_mac *mac) 545 { 546 struct pasemi_mac_rxring *rx = rx_ring(mac); 547 unsigned int i; 548 struct pasemi_mac_buffer *info; 549 550 for (i = 0; i < RX_RING_SIZE; i++) { 551 info = &RX_DESC_INFO(rx, i); 552 if (info->skb && info->dma) { 553 dma_unmap_single(&mac->dma_pdev->dev, info->dma, 554 info->skb->len, DMA_FROM_DEVICE); 555 dev_kfree_skb_any(info->skb); 556 } 557 info->dma = 0; 558 info->skb = NULL; 559 } 560 561 for (i = 0; i < RX_RING_SIZE; i++) 562 RX_BUFF(rx, i) = 0; 563 } 564 565 static void pasemi_mac_free_rx_resources(struct pasemi_mac *mac) 566 { 567 pasemi_mac_free_rx_buffers(mac); 568 569 dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64), 570 rx_ring(mac)->buffers, rx_ring(mac)->buf_dma); 571 572 kfree(rx_ring(mac)->ring_info); 573 pasemi_dma_free_chan(&rx_ring(mac)->chan); 574 mac->rx = NULL; 575 } 576 577 static void pasemi_mac_replenish_rx_ring(struct net_device *dev, 578 const int limit) 579 { 580 const struct pasemi_mac *mac = netdev_priv(dev); 581 struct pasemi_mac_rxring *rx = rx_ring(mac); 582 int fill, count; 583 584 if (limit <= 0) 585 return; 586 587 fill = rx_ring(mac)->next_to_fill; 588 for (count = 0; count < limit; count++) { 589 struct pasemi_mac_buffer *info = &RX_DESC_INFO(rx, fill); 590 u64 *buff = &RX_BUFF(rx, fill); 591 struct sk_buff *skb; 592 dma_addr_t dma; 593 594 /* Entry in use? */ 595 WARN_ON(*buff); 596 597 skb = netdev_alloc_skb(dev, mac->bufsz); 598 skb_reserve(skb, LOCAL_SKB_ALIGN); 599 600 if (unlikely(!skb)) 601 break; 602 603 dma = dma_map_single(&mac->dma_pdev->dev, skb->data, 604 mac->bufsz - LOCAL_SKB_ALIGN, 605 DMA_FROM_DEVICE); 606 607 if (dma_mapping_error(&mac->dma_pdev->dev, dma)) { 608 dev_kfree_skb_irq(info->skb); 609 break; 610 } 611 612 info->skb = skb; 613 info->dma = dma; 614 *buff = XCT_RXB_LEN(mac->bufsz) | XCT_RXB_ADDR(dma); 615 fill++; 616 } 617 618 wmb(); 619 620 write_dma_reg(PAS_DMA_RXINT_INCR(mac->dma_if), count); 621 622 rx_ring(mac)->next_to_fill = (rx_ring(mac)->next_to_fill + count) & 623 (RX_RING_SIZE - 1); 624 } 625 626 static void pasemi_mac_restart_rx_intr(const struct pasemi_mac *mac) 627 { 628 struct pasemi_mac_rxring *rx = rx_ring(mac); 629 unsigned int reg, pcnt; 630 /* Re-enable packet count interrupts: finally 631 * ack the packet count interrupt we got in rx_intr. 632 */ 633 634 pcnt = *rx->chan.status & PAS_STATUS_PCNT_M; 635 636 reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC; 637 638 if (*rx->chan.status & PAS_STATUS_TIMER) 639 reg |= PAS_IOB_DMA_RXCH_RESET_TINTC; 640 641 write_iob_reg(PAS_IOB_DMA_RXCH_RESET(mac->rx->chan.chno), reg); 642 } 643 644 static void pasemi_mac_restart_tx_intr(const struct pasemi_mac *mac) 645 { 646 unsigned int reg, pcnt; 647 648 /* Re-enable packet count interrupts */ 649 pcnt = *tx_ring(mac)->chan.status & PAS_STATUS_PCNT_M; 650 651 reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC; 652 653 write_iob_reg(PAS_IOB_DMA_TXCH_RESET(tx_ring(mac)->chan.chno), reg); 654 } 655 656 657 static inline void pasemi_mac_rx_error(const struct pasemi_mac *mac, 658 const u64 macrx) 659 { 660 unsigned int rcmdsta, ccmdsta; 661 struct pasemi_dmachan *chan = &rx_ring(mac)->chan; 662 663 if (!netif_msg_rx_err(mac)) 664 return; 665 666 rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); 667 ccmdsta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno)); 668 669 printk(KERN_ERR "pasemi_mac: rx error. macrx %016llx, rx status %llx\n", 670 macrx, *chan->status); 671 672 printk(KERN_ERR "pasemi_mac: rcmdsta %08x ccmdsta %08x\n", 673 rcmdsta, ccmdsta); 674 } 675 676 static inline void pasemi_mac_tx_error(const struct pasemi_mac *mac, 677 const u64 mactx) 678 { 679 unsigned int cmdsta; 680 struct pasemi_dmachan *chan = &tx_ring(mac)->chan; 681 682 if (!netif_msg_tx_err(mac)) 683 return; 684 685 cmdsta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno)); 686 687 printk(KERN_ERR "pasemi_mac: tx error. mactx 0x%016llx, "\ 688 "tx status 0x%016llx\n", mactx, *chan->status); 689 690 printk(KERN_ERR "pasemi_mac: tcmdsta 0x%08x\n", cmdsta); 691 } 692 693 static int pasemi_mac_clean_rx(struct pasemi_mac_rxring *rx, 694 const int limit) 695 { 696 const struct pasemi_dmachan *chan = &rx->chan; 697 struct pasemi_mac *mac = rx->mac; 698 struct pci_dev *pdev = mac->dma_pdev; 699 unsigned int n; 700 int count, buf_index, tot_bytes, packets; 701 struct pasemi_mac_buffer *info; 702 struct sk_buff *skb; 703 unsigned int len; 704 u64 macrx, eval; 705 dma_addr_t dma; 706 707 tot_bytes = 0; 708 packets = 0; 709 710 spin_lock(&rx->lock); 711 712 n = rx->next_to_clean; 713 714 prefetch(&RX_DESC(rx, n)); 715 716 for (count = 0; count < limit; count++) { 717 macrx = RX_DESC(rx, n); 718 prefetch(&RX_DESC(rx, n+4)); 719 720 if ((macrx & XCT_MACRX_E) || 721 (*chan->status & PAS_STATUS_ERROR)) 722 pasemi_mac_rx_error(mac, macrx); 723 724 if (!(macrx & XCT_MACRX_O)) 725 break; 726 727 info = NULL; 728 729 BUG_ON(!(macrx & XCT_MACRX_RR_8BRES)); 730 731 eval = (RX_DESC(rx, n+1) & XCT_RXRES_8B_EVAL_M) >> 732 XCT_RXRES_8B_EVAL_S; 733 buf_index = eval-1; 734 735 dma = (RX_DESC(rx, n+2) & XCT_PTR_ADDR_M); 736 info = &RX_DESC_INFO(rx, buf_index); 737 738 skb = info->skb; 739 740 prefetch_skb(skb); 741 742 len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S; 743 744 dma_unmap_single(&pdev->dev, dma, 745 mac->bufsz - LOCAL_SKB_ALIGN, 746 DMA_FROM_DEVICE); 747 748 if (macrx & XCT_MACRX_CRC) { 749 /* CRC error flagged */ 750 mac->netdev->stats.rx_errors++; 751 mac->netdev->stats.rx_crc_errors++; 752 /* No need to free skb, it'll be reused */ 753 goto next; 754 } 755 756 info->skb = NULL; 757 info->dma = 0; 758 759 if (likely((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK)) { 760 skb->ip_summed = CHECKSUM_UNNECESSARY; 761 skb->csum = (macrx & XCT_MACRX_CSUM_M) >> 762 XCT_MACRX_CSUM_S; 763 } else { 764 skb_checksum_none_assert(skb); 765 } 766 767 packets++; 768 tot_bytes += len; 769 770 /* Don't include CRC */ 771 skb_put(skb, len-4); 772 773 skb->protocol = eth_type_trans(skb, mac->netdev); 774 napi_gro_receive(&mac->napi, skb); 775 776 next: 777 RX_DESC(rx, n) = 0; 778 RX_DESC(rx, n+1) = 0; 779 780 /* Need to zero it out since hardware doesn't, since the 781 * replenish loop uses it to tell when it's done. 782 */ 783 RX_BUFF(rx, buf_index) = 0; 784 785 n += 4; 786 } 787 788 if (n > RX_RING_SIZE) { 789 /* Errata 5971 workaround: L2 target of headers */ 790 write_iob_reg(PAS_IOB_COM_PKTHDRCNT, 0); 791 n &= (RX_RING_SIZE-1); 792 } 793 794 rx_ring(mac)->next_to_clean = n; 795 796 /* Increase is in number of 16-byte entries, and since each descriptor 797 * with an 8BRES takes up 3x8 bytes (padded to 4x8), increase with 798 * count*2. 799 */ 800 write_dma_reg(PAS_DMA_RXCHAN_INCR(mac->rx->chan.chno), count << 1); 801 802 pasemi_mac_replenish_rx_ring(mac->netdev, count); 803 804 mac->netdev->stats.rx_bytes += tot_bytes; 805 mac->netdev->stats.rx_packets += packets; 806 807 spin_unlock(&rx_ring(mac)->lock); 808 809 return count; 810 } 811 812 /* Can't make this too large or we blow the kernel stack limits */ 813 #define TX_CLEAN_BATCHSIZE (128/MAX_SKB_FRAGS) 814 815 static int pasemi_mac_clean_tx(struct pasemi_mac_txring *txring) 816 { 817 struct pasemi_dmachan *chan = &txring->chan; 818 struct pasemi_mac *mac = txring->mac; 819 int i, j; 820 unsigned int start, descr_count, buf_count, batch_limit; 821 unsigned int ring_limit; 822 unsigned int total_count; 823 unsigned long flags; 824 struct sk_buff *skbs[TX_CLEAN_BATCHSIZE]; 825 dma_addr_t dmas[TX_CLEAN_BATCHSIZE][MAX_SKB_FRAGS+1]; 826 int nf[TX_CLEAN_BATCHSIZE]; 827 int nr_frags; 828 829 total_count = 0; 830 batch_limit = TX_CLEAN_BATCHSIZE; 831 restart: 832 spin_lock_irqsave(&txring->lock, flags); 833 834 start = txring->next_to_clean; 835 ring_limit = txring->next_to_fill; 836 837 prefetch(&TX_DESC_INFO(txring, start+1).skb); 838 839 /* Compensate for when fill has wrapped but clean has not */ 840 if (start > ring_limit) 841 ring_limit += TX_RING_SIZE; 842 843 buf_count = 0; 844 descr_count = 0; 845 846 for (i = start; 847 descr_count < batch_limit && i < ring_limit; 848 i += buf_count) { 849 u64 mactx = TX_DESC(txring, i); 850 struct sk_buff *skb; 851 852 if ((mactx & XCT_MACTX_E) || 853 (*chan->status & PAS_STATUS_ERROR)) 854 pasemi_mac_tx_error(mac, mactx); 855 856 /* Skip over control descriptors */ 857 if (!(mactx & XCT_MACTX_LLEN_M)) { 858 TX_DESC(txring, i) = 0; 859 TX_DESC(txring, i+1) = 0; 860 buf_count = 2; 861 continue; 862 } 863 864 skb = TX_DESC_INFO(txring, i+1).skb; 865 nr_frags = TX_DESC_INFO(txring, i).dma; 866 867 if (unlikely(mactx & XCT_MACTX_O)) 868 /* Not yet transmitted */ 869 break; 870 871 buf_count = 2 + nr_frags; 872 /* Since we always fill with an even number of entries, make 873 * sure we skip any unused one at the end as well. 874 */ 875 if (buf_count & 1) 876 buf_count++; 877 878 for (j = 0; j <= nr_frags; j++) 879 dmas[descr_count][j] = TX_DESC_INFO(txring, i+1+j).dma; 880 881 skbs[descr_count] = skb; 882 nf[descr_count] = nr_frags; 883 884 TX_DESC(txring, i) = 0; 885 TX_DESC(txring, i+1) = 0; 886 887 descr_count++; 888 } 889 txring->next_to_clean = i & (TX_RING_SIZE-1); 890 891 spin_unlock_irqrestore(&txring->lock, flags); 892 netif_wake_queue(mac->netdev); 893 894 for (i = 0; i < descr_count; i++) 895 pasemi_mac_unmap_tx_skb(mac, nf[i], skbs[i], dmas[i]); 896 897 total_count += descr_count; 898 899 /* If the batch was full, try to clean more */ 900 if (descr_count == batch_limit) 901 goto restart; 902 903 return total_count; 904 } 905 906 907 static irqreturn_t pasemi_mac_rx_intr(int irq, void *data) 908 { 909 const struct pasemi_mac_rxring *rxring = data; 910 struct pasemi_mac *mac = rxring->mac; 911 const struct pasemi_dmachan *chan = &rxring->chan; 912 unsigned int reg; 913 914 if (!(*chan->status & PAS_STATUS_CAUSE_M)) 915 return IRQ_NONE; 916 917 /* Don't reset packet count so it won't fire again but clear 918 * all others. 919 */ 920 921 reg = 0; 922 if (*chan->status & PAS_STATUS_SOFT) 923 reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; 924 if (*chan->status & PAS_STATUS_ERROR) 925 reg |= PAS_IOB_DMA_RXCH_RESET_DINTC; 926 927 napi_schedule(&mac->napi); 928 929 write_iob_reg(PAS_IOB_DMA_RXCH_RESET(chan->chno), reg); 930 931 return IRQ_HANDLED; 932 } 933 934 #define TX_CLEAN_INTERVAL HZ 935 936 static void pasemi_mac_tx_timer(struct timer_list *t) 937 { 938 struct pasemi_mac_txring *txring = timer_container_of(txring, t, 939 clean_timer); 940 struct pasemi_mac *mac = txring->mac; 941 942 pasemi_mac_clean_tx(txring); 943 944 mod_timer(&txring->clean_timer, jiffies + TX_CLEAN_INTERVAL); 945 946 pasemi_mac_restart_tx_intr(mac); 947 } 948 949 static irqreturn_t pasemi_mac_tx_intr(int irq, void *data) 950 { 951 struct pasemi_mac_txring *txring = data; 952 const struct pasemi_dmachan *chan = &txring->chan; 953 struct pasemi_mac *mac = txring->mac; 954 unsigned int reg; 955 956 if (!(*chan->status & PAS_STATUS_CAUSE_M)) 957 return IRQ_NONE; 958 959 reg = 0; 960 961 if (*chan->status & PAS_STATUS_SOFT) 962 reg |= PAS_IOB_DMA_TXCH_RESET_SINTC; 963 if (*chan->status & PAS_STATUS_ERROR) 964 reg |= PAS_IOB_DMA_TXCH_RESET_DINTC; 965 966 mod_timer(&txring->clean_timer, jiffies + (TX_CLEAN_INTERVAL)*2); 967 968 napi_schedule(&mac->napi); 969 970 if (reg) 971 write_iob_reg(PAS_IOB_DMA_TXCH_RESET(chan->chno), reg); 972 973 return IRQ_HANDLED; 974 } 975 976 static void pasemi_adjust_link(struct net_device *dev) 977 { 978 struct pasemi_mac *mac = netdev_priv(dev); 979 int msg; 980 unsigned int flags; 981 unsigned int new_flags; 982 983 if (!dev->phydev->link) { 984 /* If no link, MAC speed settings don't matter. Just report 985 * link down and return. 986 */ 987 if (mac->link && netif_msg_link(mac)) 988 printk(KERN_INFO "%s: Link is down.\n", dev->name); 989 990 netif_carrier_off(dev); 991 pasemi_mac_intf_disable(mac); 992 mac->link = 0; 993 994 return; 995 } else { 996 pasemi_mac_intf_enable(mac); 997 netif_carrier_on(dev); 998 } 999 1000 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); 1001 new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M | 1002 PAS_MAC_CFG_PCFG_TSR_M); 1003 1004 if (!dev->phydev->duplex) 1005 new_flags |= PAS_MAC_CFG_PCFG_HD; 1006 1007 switch (dev->phydev->speed) { 1008 case 1000: 1009 new_flags |= PAS_MAC_CFG_PCFG_SPD_1G | 1010 PAS_MAC_CFG_PCFG_TSR_1G; 1011 break; 1012 case 100: 1013 new_flags |= PAS_MAC_CFG_PCFG_SPD_100M | 1014 PAS_MAC_CFG_PCFG_TSR_100M; 1015 break; 1016 case 10: 1017 new_flags |= PAS_MAC_CFG_PCFG_SPD_10M | 1018 PAS_MAC_CFG_PCFG_TSR_10M; 1019 break; 1020 default: 1021 printk("Unsupported speed %d\n", dev->phydev->speed); 1022 } 1023 1024 /* Print on link or speed/duplex change */ 1025 msg = mac->link != dev->phydev->link || flags != new_flags; 1026 1027 mac->duplex = dev->phydev->duplex; 1028 mac->speed = dev->phydev->speed; 1029 mac->link = dev->phydev->link; 1030 1031 if (new_flags != flags) 1032 write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags); 1033 1034 if (msg && netif_msg_link(mac)) 1035 printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n", 1036 dev->name, mac->speed, mac->duplex ? "full" : "half"); 1037 } 1038 1039 static int pasemi_mac_phy_init(struct net_device *dev) 1040 { 1041 struct pasemi_mac *mac = netdev_priv(dev); 1042 struct device_node *dn, *phy_dn; 1043 struct phy_device *phydev; 1044 1045 dn = pci_device_to_OF_node(mac->pdev); 1046 phy_dn = of_parse_phandle(dn, "phy-handle", 0); 1047 1048 mac->link = 0; 1049 mac->speed = 0; 1050 mac->duplex = -1; 1051 1052 phydev = of_phy_connect(dev, phy_dn, &pasemi_adjust_link, 0, 1053 PHY_INTERFACE_MODE_SGMII); 1054 1055 of_node_put(phy_dn); 1056 if (!phydev) { 1057 printk(KERN_ERR "%s: Could not attach to phy\n", dev->name); 1058 return -ENODEV; 1059 } 1060 1061 return 0; 1062 } 1063 1064 1065 static int pasemi_mac_open(struct net_device *dev) 1066 { 1067 struct pasemi_mac *mac = netdev_priv(dev); 1068 unsigned int flags; 1069 int i, ret; 1070 1071 flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) | 1072 PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) | 1073 PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12); 1074 1075 write_mac_reg(mac, PAS_MAC_CFG_TXP, flags); 1076 1077 ret = pasemi_mac_setup_rx_resources(dev); 1078 if (ret) 1079 goto out_rx_resources; 1080 1081 mac->tx = pasemi_mac_setup_tx_resources(dev); 1082 1083 if (!mac->tx) { 1084 ret = -ENOMEM; 1085 goto out_tx_ring; 1086 } 1087 1088 /* We might already have allocated rings in case mtu was changed 1089 * before interface was brought up. 1090 */ 1091 if (dev->mtu > 1500 && !mac->num_cs) { 1092 pasemi_mac_setup_csrings(mac); 1093 if (!mac->num_cs) { 1094 ret = -ENOMEM; 1095 goto out_tx_ring; 1096 } 1097 } 1098 1099 /* Zero out rmon counters */ 1100 for (i = 0; i < 32; i++) 1101 write_mac_reg(mac, PAS_MAC_RMON(i), 0); 1102 1103 /* 0x3ff with 33MHz clock is about 31us */ 1104 write_iob_reg(PAS_IOB_DMA_COM_TIMEOUTCFG, 1105 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0x3ff)); 1106 1107 write_iob_reg(PAS_IOB_DMA_RXCH_CFG(mac->rx->chan.chno), 1108 PAS_IOB_DMA_RXCH_CFG_CNTTH(256)); 1109 1110 write_iob_reg(PAS_IOB_DMA_TXCH_CFG(mac->tx->chan.chno), 1111 PAS_IOB_DMA_TXCH_CFG_CNTTH(32)); 1112 1113 write_mac_reg(mac, PAS_MAC_IPC_CHNL, 1114 PAS_MAC_IPC_CHNL_DCHNO(mac->rx->chan.chno) | 1115 PAS_MAC_IPC_CHNL_BCH(mac->rx->chan.chno)); 1116 1117 /* enable rx if */ 1118 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 1119 PAS_DMA_RXINT_RCMDSTA_EN | 1120 PAS_DMA_RXINT_RCMDSTA_DROPS_M | 1121 PAS_DMA_RXINT_RCMDSTA_BP | 1122 PAS_DMA_RXINT_RCMDSTA_OO | 1123 PAS_DMA_RXINT_RCMDSTA_BT); 1124 1125 /* enable rx channel */ 1126 pasemi_dma_start_chan(&rx_ring(mac)->chan, PAS_DMA_RXCHAN_CCMDSTA_DU | 1127 PAS_DMA_RXCHAN_CCMDSTA_OD | 1128 PAS_DMA_RXCHAN_CCMDSTA_FD | 1129 PAS_DMA_RXCHAN_CCMDSTA_DT); 1130 1131 /* enable tx channel */ 1132 pasemi_dma_start_chan(&tx_ring(mac)->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ | 1133 PAS_DMA_TXCHAN_TCMDSTA_DB | 1134 PAS_DMA_TXCHAN_TCMDSTA_DE | 1135 PAS_DMA_TXCHAN_TCMDSTA_DA); 1136 1137 pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE); 1138 1139 write_dma_reg(PAS_DMA_RXCHAN_INCR(rx_ring(mac)->chan.chno), 1140 RX_RING_SIZE>>1); 1141 1142 /* Clear out any residual packet count state from firmware */ 1143 pasemi_mac_restart_rx_intr(mac); 1144 pasemi_mac_restart_tx_intr(mac); 1145 1146 flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE; 1147 1148 if (mac->type == MAC_TYPE_GMAC) 1149 flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G; 1150 else 1151 flags |= PAS_MAC_CFG_PCFG_TSR_10G | PAS_MAC_CFG_PCFG_SPD_10G; 1152 1153 /* Enable interface in MAC */ 1154 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); 1155 1156 ret = pasemi_mac_phy_init(dev); 1157 if (ret) { 1158 /* Since we won't get link notification, just enable RX */ 1159 pasemi_mac_intf_enable(mac); 1160 if (mac->type == MAC_TYPE_GMAC) { 1161 /* Warn for missing PHY on SGMII (1Gig) ports */ 1162 dev_warn(&mac->pdev->dev, 1163 "PHY init failed: %d.\n", ret); 1164 dev_warn(&mac->pdev->dev, 1165 "Defaulting to 1Gbit full duplex\n"); 1166 } 1167 } 1168 1169 netif_start_queue(dev); 1170 napi_enable(&mac->napi); 1171 1172 snprintf(mac->tx_irq_name, sizeof(mac->tx_irq_name), "%s tx", 1173 dev->name); 1174 1175 ret = request_irq(mac->tx->chan.irq, pasemi_mac_tx_intr, 0, 1176 mac->tx_irq_name, mac->tx); 1177 if (ret) { 1178 dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n", 1179 mac->tx->chan.irq, ret); 1180 goto out_tx_int; 1181 } 1182 1183 snprintf(mac->rx_irq_name, sizeof(mac->rx_irq_name), "%s rx", 1184 dev->name); 1185 1186 ret = request_irq(mac->rx->chan.irq, pasemi_mac_rx_intr, 0, 1187 mac->rx_irq_name, mac->rx); 1188 if (ret) { 1189 dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n", 1190 mac->rx->chan.irq, ret); 1191 goto out_rx_int; 1192 } 1193 1194 if (dev->phydev) 1195 phy_start(dev->phydev); 1196 1197 timer_setup(&mac->tx->clean_timer, pasemi_mac_tx_timer, 0); 1198 mod_timer(&mac->tx->clean_timer, jiffies + HZ); 1199 1200 return 0; 1201 1202 out_rx_int: 1203 free_irq(mac->tx->chan.irq, mac->tx); 1204 out_tx_int: 1205 napi_disable(&mac->napi); 1206 netif_stop_queue(dev); 1207 out_tx_ring: 1208 if (mac->tx) 1209 pasemi_mac_free_tx_resources(mac); 1210 pasemi_mac_free_rx_resources(mac); 1211 out_rx_resources: 1212 1213 return ret; 1214 } 1215 1216 #define MAX_RETRIES 5000 1217 1218 static void pasemi_mac_pause_txchan(struct pasemi_mac *mac) 1219 { 1220 unsigned int sta, retries; 1221 int txch = tx_ring(mac)->chan.chno; 1222 1223 write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), 1224 PAS_DMA_TXCHAN_TCMDSTA_ST); 1225 1226 for (retries = 0; retries < MAX_RETRIES; retries++) { 1227 sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch)); 1228 if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)) 1229 break; 1230 cond_resched(); 1231 } 1232 1233 if (sta & PAS_DMA_TXCHAN_TCMDSTA_ACT) 1234 dev_err(&mac->dma_pdev->dev, 1235 "Failed to stop tx channel, tcmdsta %08x\n", sta); 1236 1237 write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), 0); 1238 } 1239 1240 static void pasemi_mac_pause_rxchan(struct pasemi_mac *mac) 1241 { 1242 unsigned int sta, retries; 1243 int rxch = rx_ring(mac)->chan.chno; 1244 1245 write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), 1246 PAS_DMA_RXCHAN_CCMDSTA_ST); 1247 for (retries = 0; retries < MAX_RETRIES; retries++) { 1248 sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch)); 1249 if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)) 1250 break; 1251 cond_resched(); 1252 } 1253 1254 if (sta & PAS_DMA_RXCHAN_CCMDSTA_ACT) 1255 dev_err(&mac->dma_pdev->dev, 1256 "Failed to stop rx channel, ccmdsta 08%x\n", sta); 1257 write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), 0); 1258 } 1259 1260 static void pasemi_mac_pause_rxint(struct pasemi_mac *mac) 1261 { 1262 unsigned int sta, retries; 1263 1264 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 1265 PAS_DMA_RXINT_RCMDSTA_ST); 1266 for (retries = 0; retries < MAX_RETRIES; retries++) { 1267 sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); 1268 if (!(sta & PAS_DMA_RXINT_RCMDSTA_ACT)) 1269 break; 1270 cond_resched(); 1271 } 1272 1273 if (sta & PAS_DMA_RXINT_RCMDSTA_ACT) 1274 dev_err(&mac->dma_pdev->dev, 1275 "Failed to stop rx interface, rcmdsta %08x\n", sta); 1276 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0); 1277 } 1278 1279 static int pasemi_mac_close(struct net_device *dev) 1280 { 1281 struct pasemi_mac *mac = netdev_priv(dev); 1282 unsigned int sta; 1283 int rxch, txch, i; 1284 1285 rxch = rx_ring(mac)->chan.chno; 1286 txch = tx_ring(mac)->chan.chno; 1287 1288 if (dev->phydev) { 1289 phy_stop(dev->phydev); 1290 phy_disconnect(dev->phydev); 1291 } 1292 1293 timer_delete_sync(&mac->tx->clean_timer); 1294 1295 netif_stop_queue(dev); 1296 napi_disable(&mac->napi); 1297 1298 sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); 1299 if (sta & (PAS_DMA_RXINT_RCMDSTA_BP | 1300 PAS_DMA_RXINT_RCMDSTA_OO | 1301 PAS_DMA_RXINT_RCMDSTA_BT)) 1302 printk(KERN_DEBUG "pasemi_mac: rcmdsta error: 0x%08x\n", sta); 1303 1304 sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch)); 1305 if (sta & (PAS_DMA_RXCHAN_CCMDSTA_DU | 1306 PAS_DMA_RXCHAN_CCMDSTA_OD | 1307 PAS_DMA_RXCHAN_CCMDSTA_FD | 1308 PAS_DMA_RXCHAN_CCMDSTA_DT)) 1309 printk(KERN_DEBUG "pasemi_mac: ccmdsta error: 0x%08x\n", sta); 1310 1311 sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch)); 1312 if (sta & (PAS_DMA_TXCHAN_TCMDSTA_SZ | PAS_DMA_TXCHAN_TCMDSTA_DB | 1313 PAS_DMA_TXCHAN_TCMDSTA_DE | PAS_DMA_TXCHAN_TCMDSTA_DA)) 1314 printk(KERN_DEBUG "pasemi_mac: tcmdsta error: 0x%08x\n", sta); 1315 1316 /* Clean out any pending buffers */ 1317 pasemi_mac_clean_tx(tx_ring(mac)); 1318 pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE); 1319 1320 pasemi_mac_pause_txchan(mac); 1321 pasemi_mac_pause_rxint(mac); 1322 pasemi_mac_pause_rxchan(mac); 1323 pasemi_mac_intf_disable(mac); 1324 1325 free_irq(mac->tx->chan.irq, mac->tx); 1326 free_irq(mac->rx->chan.irq, mac->rx); 1327 1328 for (i = 0; i < mac->num_cs; i++) { 1329 pasemi_mac_free_csring(mac->cs[i]); 1330 mac->cs[i] = NULL; 1331 } 1332 1333 mac->num_cs = 0; 1334 1335 /* Free resources */ 1336 pasemi_mac_free_rx_resources(mac); 1337 pasemi_mac_free_tx_resources(mac); 1338 1339 return 0; 1340 } 1341 1342 static void pasemi_mac_queue_csdesc(const struct sk_buff *skb, 1343 const dma_addr_t *map, 1344 const unsigned int *map_size, 1345 struct pasemi_mac_txring *txring, 1346 struct pasemi_mac_csring *csring) 1347 { 1348 u64 fund; 1349 dma_addr_t cs_dest; 1350 const int nh_off = skb_network_offset(skb); 1351 const int nh_len = skb_network_header_len(skb); 1352 const int nfrags = skb_shinfo(skb)->nr_frags; 1353 int cs_size, i, fill, hdr, evt; 1354 dma_addr_t csdma; 1355 1356 fund = XCT_FUN_ST | XCT_FUN_RR_8BRES | 1357 XCT_FUN_O | XCT_FUN_FUN(csring->fun) | 1358 XCT_FUN_CRM_SIG | XCT_FUN_LLEN(skb->len - nh_off) | 1359 XCT_FUN_SHL(nh_len >> 2) | XCT_FUN_SE; 1360 1361 switch (ip_hdr(skb)->protocol) { 1362 case IPPROTO_TCP: 1363 fund |= XCT_FUN_SIG_TCP4; 1364 /* TCP checksum is 16 bytes into the header */ 1365 cs_dest = map[0] + skb_transport_offset(skb) + 16; 1366 break; 1367 case IPPROTO_UDP: 1368 fund |= XCT_FUN_SIG_UDP4; 1369 /* UDP checksum is 6 bytes into the header */ 1370 cs_dest = map[0] + skb_transport_offset(skb) + 6; 1371 break; 1372 default: 1373 BUG(); 1374 } 1375 1376 /* Do the checksum offloaded */ 1377 fill = csring->next_to_fill; 1378 hdr = fill; 1379 1380 CS_DESC(csring, fill++) = fund; 1381 /* Room for 8BRES. Checksum result is really 2 bytes into it */ 1382 csdma = csring->chan.ring_dma + (fill & (CS_RING_SIZE-1)) * 8 + 2; 1383 CS_DESC(csring, fill++) = 0; 1384 1385 CS_DESC(csring, fill) = XCT_PTR_LEN(map_size[0]-nh_off) | XCT_PTR_ADDR(map[0]+nh_off); 1386 for (i = 1; i <= nfrags; i++) 1387 CS_DESC(csring, fill+i) = XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]); 1388 1389 fill += i; 1390 if (fill & 1) 1391 fill++; 1392 1393 /* Copy the result into the TCP packet */ 1394 CS_DESC(csring, fill++) = XCT_FUN_O | XCT_FUN_FUN(csring->fun) | 1395 XCT_FUN_LLEN(2) | XCT_FUN_SE; 1396 CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(cs_dest) | XCT_PTR_T; 1397 CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(csdma); 1398 fill++; 1399 1400 evt = !csring->last_event; 1401 csring->last_event = evt; 1402 1403 /* Event handshaking with MAC TX */ 1404 CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O | 1405 CTRL_CMD_ETYPE_SET | CTRL_CMD_REG(csring->events[evt]); 1406 CS_DESC(csring, fill++) = 0; 1407 CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O | 1408 CTRL_CMD_ETYPE_WCLR | CTRL_CMD_REG(csring->events[!evt]); 1409 CS_DESC(csring, fill++) = 0; 1410 csring->next_to_fill = fill & (CS_RING_SIZE-1); 1411 1412 cs_size = fill - hdr; 1413 write_dma_reg(PAS_DMA_TXCHAN_INCR(csring->chan.chno), (cs_size) >> 1); 1414 1415 /* TX-side event handshaking */ 1416 fill = txring->next_to_fill; 1417 TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O | 1418 CTRL_CMD_ETYPE_WSET | CTRL_CMD_REG(csring->events[evt]); 1419 TX_DESC(txring, fill++) = 0; 1420 TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O | 1421 CTRL_CMD_ETYPE_CLR | CTRL_CMD_REG(csring->events[!evt]); 1422 TX_DESC(txring, fill++) = 0; 1423 txring->next_to_fill = fill; 1424 1425 write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), 2); 1426 } 1427 1428 static netdev_tx_t pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev) 1429 { 1430 struct pasemi_mac * const mac = netdev_priv(dev); 1431 struct pasemi_mac_txring * const txring = tx_ring(mac); 1432 struct pasemi_mac_csring *csring; 1433 u64 dflags = 0; 1434 u64 mactx; 1435 dma_addr_t map[MAX_SKB_FRAGS+1]; 1436 unsigned int map_size[MAX_SKB_FRAGS+1]; 1437 unsigned long flags; 1438 int i, nfrags; 1439 int fill; 1440 const int nh_off = skb_network_offset(skb); 1441 const int nh_len = skb_network_header_len(skb); 1442 1443 prefetch(&txring->ring_info); 1444 1445 dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_CRC_PAD; 1446 1447 nfrags = skb_shinfo(skb)->nr_frags; 1448 1449 map[0] = dma_map_single(&mac->dma_pdev->dev, skb->data, 1450 skb_headlen(skb), DMA_TO_DEVICE); 1451 map_size[0] = skb_headlen(skb); 1452 if (dma_mapping_error(&mac->dma_pdev->dev, map[0])) 1453 goto out_err_nolock; 1454 1455 for (i = 0; i < nfrags; i++) { 1456 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1457 1458 map[i + 1] = skb_frag_dma_map(&mac->dma_pdev->dev, frag, 0, 1459 skb_frag_size(frag), DMA_TO_DEVICE); 1460 map_size[i+1] = skb_frag_size(frag); 1461 if (dma_mapping_error(&mac->dma_pdev->dev, map[i + 1])) { 1462 nfrags = i; 1463 goto out_err_nolock; 1464 } 1465 } 1466 1467 if (skb->ip_summed == CHECKSUM_PARTIAL && skb->len <= 1540) { 1468 switch (ip_hdr(skb)->protocol) { 1469 case IPPROTO_TCP: 1470 dflags |= XCT_MACTX_CSUM_TCP; 1471 dflags |= XCT_MACTX_IPH(nh_len >> 2); 1472 dflags |= XCT_MACTX_IPO(nh_off); 1473 break; 1474 case IPPROTO_UDP: 1475 dflags |= XCT_MACTX_CSUM_UDP; 1476 dflags |= XCT_MACTX_IPH(nh_len >> 2); 1477 dflags |= XCT_MACTX_IPO(nh_off); 1478 break; 1479 default: 1480 WARN_ON(1); 1481 } 1482 } 1483 1484 mactx = dflags | XCT_MACTX_LLEN(skb->len); 1485 1486 spin_lock_irqsave(&txring->lock, flags); 1487 1488 /* Avoid stepping on the same cache line that the DMA controller 1489 * is currently about to send, so leave at least 8 words available. 1490 * Total free space needed is mactx + fragments + 8 1491 */ 1492 if (RING_AVAIL(txring) < nfrags + 14) { 1493 /* no room -- stop the queue and wait for tx intr */ 1494 netif_stop_queue(dev); 1495 goto out_err; 1496 } 1497 1498 /* Queue up checksum + event descriptors, if needed */ 1499 if (mac->num_cs && skb->ip_summed == CHECKSUM_PARTIAL && skb->len > 1540) { 1500 csring = mac->cs[mac->last_cs]; 1501 mac->last_cs = (mac->last_cs + 1) % mac->num_cs; 1502 1503 pasemi_mac_queue_csdesc(skb, map, map_size, txring, csring); 1504 } 1505 1506 fill = txring->next_to_fill; 1507 TX_DESC(txring, fill) = mactx; 1508 TX_DESC_INFO(txring, fill).dma = nfrags; 1509 fill++; 1510 TX_DESC_INFO(txring, fill).skb = skb; 1511 for (i = 0; i <= nfrags; i++) { 1512 TX_DESC(txring, fill+i) = 1513 XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]); 1514 TX_DESC_INFO(txring, fill+i).dma = map[i]; 1515 } 1516 1517 /* We have to add an even number of 8-byte entries to the ring 1518 * even if the last one is unused. That means always an odd number 1519 * of pointers + one mactx descriptor. 1520 */ 1521 if (nfrags & 1) 1522 nfrags++; 1523 1524 txring->next_to_fill = (fill + nfrags + 1) & (TX_RING_SIZE-1); 1525 1526 dev->stats.tx_packets++; 1527 dev->stats.tx_bytes += skb->len; 1528 1529 spin_unlock_irqrestore(&txring->lock, flags); 1530 1531 write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), (nfrags+2) >> 1); 1532 1533 return NETDEV_TX_OK; 1534 1535 out_err: 1536 spin_unlock_irqrestore(&txring->lock, flags); 1537 out_err_nolock: 1538 while (nfrags--) 1539 dma_unmap_single(&mac->dma_pdev->dev, map[nfrags], 1540 map_size[nfrags], DMA_TO_DEVICE); 1541 1542 return NETDEV_TX_BUSY; 1543 } 1544 1545 static void pasemi_mac_set_rx_mode(struct net_device *dev) 1546 { 1547 const struct pasemi_mac *mac = netdev_priv(dev); 1548 unsigned int flags; 1549 1550 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); 1551 1552 /* Set promiscuous */ 1553 if (dev->flags & IFF_PROMISC) 1554 flags |= PAS_MAC_CFG_PCFG_PR; 1555 else 1556 flags &= ~PAS_MAC_CFG_PCFG_PR; 1557 1558 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); 1559 } 1560 1561 1562 static int pasemi_mac_poll(struct napi_struct *napi, int budget) 1563 { 1564 struct pasemi_mac *mac = container_of(napi, struct pasemi_mac, napi); 1565 int pkts; 1566 1567 pasemi_mac_clean_tx(tx_ring(mac)); 1568 pkts = pasemi_mac_clean_rx(rx_ring(mac), budget); 1569 if (pkts < budget) { 1570 /* all done, no more packets present */ 1571 napi_complete_done(napi, pkts); 1572 1573 pasemi_mac_restart_rx_intr(mac); 1574 pasemi_mac_restart_tx_intr(mac); 1575 } 1576 return pkts; 1577 } 1578 1579 #ifdef CONFIG_NET_POLL_CONTROLLER 1580 /* 1581 * Polling 'interrupt' - used by things like netconsole to send skbs 1582 * without having to re-enable interrupts. It's not called while 1583 * the interrupt routine is executing. 1584 */ 1585 static void pasemi_mac_netpoll(struct net_device *dev) 1586 { 1587 const struct pasemi_mac *mac = netdev_priv(dev); 1588 1589 disable_irq(mac->tx->chan.irq); 1590 pasemi_mac_tx_intr(mac->tx->chan.irq, mac->tx); 1591 enable_irq(mac->tx->chan.irq); 1592 1593 disable_irq(mac->rx->chan.irq); 1594 pasemi_mac_rx_intr(mac->rx->chan.irq, mac->rx); 1595 enable_irq(mac->rx->chan.irq); 1596 } 1597 #endif 1598 1599 static int pasemi_mac_change_mtu(struct net_device *dev, int new_mtu) 1600 { 1601 struct pasemi_mac *mac = netdev_priv(dev); 1602 unsigned int reg; 1603 unsigned int rcmdsta = 0; 1604 int running; 1605 int ret = 0; 1606 1607 running = netif_running(dev); 1608 1609 if (running) { 1610 /* Need to stop the interface, clean out all already 1611 * received buffers, free all unused buffers on the RX 1612 * interface ring, then finally re-fill the rx ring with 1613 * the new-size buffers and restart. 1614 */ 1615 1616 napi_disable(&mac->napi); 1617 netif_tx_disable(dev); 1618 pasemi_mac_intf_disable(mac); 1619 1620 rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); 1621 pasemi_mac_pause_rxint(mac); 1622 pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE); 1623 pasemi_mac_free_rx_buffers(mac); 1624 1625 } 1626 1627 /* Setup checksum channels if large MTU and none already allocated */ 1628 if (new_mtu > PE_DEF_MTU && !mac->num_cs) { 1629 pasemi_mac_setup_csrings(mac); 1630 if (!mac->num_cs) { 1631 ret = -ENOMEM; 1632 goto out; 1633 } 1634 } 1635 1636 /* Change maxf, i.e. what size frames are accepted. 1637 * Need room for ethernet header and CRC word 1638 */ 1639 reg = read_mac_reg(mac, PAS_MAC_CFG_MACCFG); 1640 reg &= ~PAS_MAC_CFG_MACCFG_MAXF_M; 1641 reg |= PAS_MAC_CFG_MACCFG_MAXF(new_mtu + ETH_HLEN + 4); 1642 write_mac_reg(mac, PAS_MAC_CFG_MACCFG, reg); 1643 1644 WRITE_ONCE(dev->mtu, new_mtu); 1645 /* MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */ 1646 mac->bufsz = new_mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128; 1647 1648 out: 1649 if (running) { 1650 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 1651 rcmdsta | PAS_DMA_RXINT_RCMDSTA_EN); 1652 1653 rx_ring(mac)->next_to_fill = 0; 1654 pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE-1); 1655 1656 napi_enable(&mac->napi); 1657 netif_start_queue(dev); 1658 pasemi_mac_intf_enable(mac); 1659 } 1660 1661 return ret; 1662 } 1663 1664 static const struct net_device_ops pasemi_netdev_ops = { 1665 .ndo_open = pasemi_mac_open, 1666 .ndo_stop = pasemi_mac_close, 1667 .ndo_start_xmit = pasemi_mac_start_tx, 1668 .ndo_set_rx_mode = pasemi_mac_set_rx_mode, 1669 .ndo_set_mac_address = pasemi_mac_set_mac_addr, 1670 .ndo_change_mtu = pasemi_mac_change_mtu, 1671 .ndo_validate_addr = eth_validate_addr, 1672 #ifdef CONFIG_NET_POLL_CONTROLLER 1673 .ndo_poll_controller = pasemi_mac_netpoll, 1674 #endif 1675 }; 1676 1677 static int 1678 pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1679 { 1680 struct net_device *dev; 1681 struct pasemi_mac *mac; 1682 int err, ret; 1683 1684 err = pci_enable_device(pdev); 1685 if (err) 1686 return err; 1687 1688 dev = alloc_etherdev(sizeof(struct pasemi_mac)); 1689 if (dev == NULL) { 1690 err = -ENOMEM; 1691 goto out_disable_device; 1692 } 1693 1694 pci_set_drvdata(pdev, dev); 1695 SET_NETDEV_DEV(dev, &pdev->dev); 1696 1697 mac = netdev_priv(dev); 1698 1699 mac->pdev = pdev; 1700 mac->netdev = dev; 1701 1702 netif_napi_add(dev, &mac->napi, pasemi_mac_poll); 1703 1704 dev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA | 1705 NETIF_F_GSO; 1706 dev->lltx = true; 1707 1708 mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL); 1709 if (!mac->dma_pdev) { 1710 dev_err(&mac->pdev->dev, "Can't find DMA Controller\n"); 1711 err = -ENODEV; 1712 goto out; 1713 } 1714 dma_set_mask(&mac->dma_pdev->dev, DMA_BIT_MASK(64)); 1715 1716 mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); 1717 if (!mac->iob_pdev) { 1718 dev_err(&mac->pdev->dev, "Can't find I/O Bridge\n"); 1719 err = -ENODEV; 1720 goto out; 1721 } 1722 1723 /* get mac addr from device tree */ 1724 if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) { 1725 err = -ENODEV; 1726 goto out; 1727 } 1728 eth_hw_addr_set(dev, mac->mac_addr); 1729 1730 ret = mac_to_intf(mac); 1731 if (ret < 0) { 1732 dev_err(&mac->pdev->dev, "Can't map DMA interface\n"); 1733 err = -ENODEV; 1734 goto out; 1735 } 1736 mac->dma_if = ret; 1737 1738 switch (pdev->device) { 1739 case 0xa005: 1740 mac->type = MAC_TYPE_GMAC; 1741 break; 1742 case 0xa006: 1743 mac->type = MAC_TYPE_XAUI; 1744 break; 1745 default: 1746 err = -ENODEV; 1747 goto out; 1748 } 1749 1750 dev->netdev_ops = &pasemi_netdev_ops; 1751 dev->mtu = PE_DEF_MTU; 1752 1753 /* MTU range: 64 - 9000 */ 1754 dev->min_mtu = PE_MIN_MTU; 1755 dev->max_mtu = PE_MAX_MTU; 1756 1757 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */ 1758 mac->bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128; 1759 1760 dev->ethtool_ops = &pasemi_mac_ethtool_ops; 1761 1762 if (err) 1763 goto out; 1764 1765 mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 1766 1767 /* Enable most messages by default */ 1768 mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; 1769 1770 err = register_netdev(dev); 1771 1772 if (err) { 1773 dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n", 1774 err); 1775 goto out; 1776 } else if (netif_msg_probe(mac)) { 1777 printk(KERN_INFO "%s: PA Semi %s: intf %d, hw addr %pM\n", 1778 dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI", 1779 mac->dma_if, dev->dev_addr); 1780 } 1781 1782 return err; 1783 1784 out: 1785 pci_dev_put(mac->iob_pdev); 1786 pci_dev_put(mac->dma_pdev); 1787 1788 free_netdev(dev); 1789 out_disable_device: 1790 pci_disable_device(pdev); 1791 return err; 1792 1793 } 1794 1795 static void pasemi_mac_remove(struct pci_dev *pdev) 1796 { 1797 struct net_device *netdev = pci_get_drvdata(pdev); 1798 struct pasemi_mac *mac; 1799 1800 if (!netdev) 1801 return; 1802 1803 mac = netdev_priv(netdev); 1804 1805 unregister_netdev(netdev); 1806 1807 pci_disable_device(pdev); 1808 pci_dev_put(mac->dma_pdev); 1809 pci_dev_put(mac->iob_pdev); 1810 1811 pasemi_dma_free_chan(&mac->tx->chan); 1812 pasemi_dma_free_chan(&mac->rx->chan); 1813 1814 free_netdev(netdev); 1815 } 1816 1817 static const struct pci_device_id pasemi_mac_pci_tbl[] = { 1818 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) }, 1819 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) }, 1820 { }, 1821 }; 1822 1823 MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl); 1824 1825 static struct pci_driver pasemi_mac_driver = { 1826 .name = "pasemi_mac", 1827 .id_table = pasemi_mac_pci_tbl, 1828 .probe = pasemi_mac_probe, 1829 .remove = pasemi_mac_remove, 1830 }; 1831 1832 static void __exit pasemi_mac_cleanup_module(void) 1833 { 1834 pci_unregister_driver(&pasemi_mac_driver); 1835 } 1836 1837 static int pasemi_mac_init_module(void) 1838 { 1839 int err; 1840 1841 err = pasemi_dma_init(); 1842 if (err) 1843 return err; 1844 1845 return pci_register_driver(&pasemi_mac_driver); 1846 } 1847 1848 module_init(pasemi_mac_init_module); 1849 module_exit(pasemi_mac_cleanup_module); 1850