1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 1999 - 2010 Intel Corporation. 4 * Copyright (C) 2010 - 2012 LAPIS SEMICONDUCTOR CO., LTD. 5 * 6 * This code was derived from the Intel e1000e Linux driver. 7 */ 8 9 #include "pch_gbe.h" 10 #include "pch_gbe_phy.h" 11 12 #include <linux/gpio/consumer.h> 13 #include <linux/gpio/machine.h> 14 #include <linux/iopoll.h> 15 #include <linux/module.h> 16 #include <linux/net_tstamp.h> 17 #include <linux/ptp_classify.h> 18 #include <linux/ptp_pch.h> 19 #include <linux/gpio.h> 20 21 #define PCH_GBE_MAR_ENTRIES 16 22 #define PCH_GBE_SHORT_PKT 64 23 #define DSC_INIT16 0xC000 24 #define PCH_GBE_DMA_ALIGN 0 25 #define PCH_GBE_DMA_PADDING 2 26 #define PCH_GBE_WATCHDOG_PERIOD (5 * HZ) /* watchdog time */ 27 #define PCH_GBE_PCI_BAR 1 28 #define PCH_GBE_RESERVE_MEMORY 0x200000 /* 2MB */ 29 30 #define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802 31 32 #define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013 33 #define PCI_DEVICE_ID_ROHM_ML7831_GBE 0x8802 34 35 #define PCH_GBE_RX_BUFFER_WRITE 16 36 37 /* Initialize the wake-on-LAN settings */ 38 #define PCH_GBE_WL_INIT_SETTING (PCH_GBE_WLC_MP) 39 40 #define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \ 41 PCH_GBE_CHIP_TYPE_INTERNAL | \ 42 PCH_GBE_RGMII_MODE_RGMII \ 43 ) 44 45 /* Ethertype field values */ 46 #define PCH_GBE_MAX_RX_BUFFER_SIZE 0x2880 47 #define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318 48 #define PCH_GBE_FRAME_SIZE_2048 2048 49 #define PCH_GBE_FRAME_SIZE_4096 4096 50 #define PCH_GBE_FRAME_SIZE_8192 8192 51 52 #define PCH_GBE_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) 53 #define PCH_GBE_RX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc) 54 #define PCH_GBE_TX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc) 55 #define PCH_GBE_DESC_UNUSED(R) \ 56 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 57 (R)->next_to_clean - (R)->next_to_use - 1) 58 59 /* Pause packet value */ 60 #define PCH_GBE_PAUSE_PKT1_VALUE 0x00C28001 61 #define PCH_GBE_PAUSE_PKT2_VALUE 0x00000100 62 #define PCH_GBE_PAUSE_PKT4_VALUE 0x01000888 63 #define PCH_GBE_PAUSE_PKT5_VALUE 0x0000FFFF 64 65 66 /* This defines the bits that are set in the Interrupt Mask 67 * Set/Read Register. Each bit is documented below: 68 * o RXT0 = Receiver Timer Interrupt (ring 0) 69 * o TXDW = Transmit Descriptor Written Back 70 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 71 * o RXSEQ = Receive Sequence Error 72 * o LSC = Link Status Change 73 */ 74 #define PCH_GBE_INT_ENABLE_MASK ( \ 75 PCH_GBE_INT_RX_DMA_CMPLT | \ 76 PCH_GBE_INT_RX_DSC_EMP | \ 77 PCH_GBE_INT_RX_FIFO_ERR | \ 78 PCH_GBE_INT_WOL_DET | \ 79 PCH_GBE_INT_TX_CMPLT \ 80 ) 81 82 #define PCH_GBE_INT_DISABLE_ALL 0 83 84 /* Macros for ieee1588 */ 85 /* 0x40 Time Synchronization Channel Control Register Bits */ 86 #define MASTER_MODE (1<<0) 87 #define SLAVE_MODE (0) 88 #define V2_MODE (1<<31) 89 #define CAP_MODE0 (0) 90 #define CAP_MODE2 (1<<17) 91 92 /* 0x44 Time Synchronization Channel Event Register Bits */ 93 #define TX_SNAPSHOT_LOCKED (1<<0) 94 #define RX_SNAPSHOT_LOCKED (1<<1) 95 96 #define PTP_L4_MULTICAST_SA "01:00:5e:00:01:81" 97 #define PTP_L2_MULTICAST_SA "01:1b:19:00:00:00" 98 99 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg); 100 static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg, 101 int data); 102 static void pch_gbe_set_multi(struct net_device *netdev); 103 104 static int pch_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid) 105 { 106 u8 *data = skb->data; 107 unsigned int offset; 108 u16 hi, id; 109 u32 lo; 110 111 if (ptp_classify_raw(skb) == PTP_CLASS_NONE) 112 return 0; 113 114 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN; 115 116 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid)) 117 return 0; 118 119 hi = get_unaligned_be16(data + offset + OFF_PTP_SOURCE_UUID + 0); 120 lo = get_unaligned_be32(data + offset + OFF_PTP_SOURCE_UUID + 2); 121 id = get_unaligned_be16(data + offset + OFF_PTP_SEQUENCE_ID); 122 123 return (uid_hi == hi && uid_lo == lo && seqid == id); 124 } 125 126 static void 127 pch_rx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb) 128 { 129 struct skb_shared_hwtstamps *shhwtstamps; 130 struct pci_dev *pdev; 131 u64 ns; 132 u32 hi, lo, val; 133 134 if (!adapter->hwts_rx_en) 135 return; 136 137 /* Get ieee1588's dev information */ 138 pdev = adapter->ptp_pdev; 139 140 val = pch_ch_event_read(pdev); 141 142 if (!(val & RX_SNAPSHOT_LOCKED)) 143 return; 144 145 lo = pch_src_uuid_lo_read(pdev); 146 hi = pch_src_uuid_hi_read(pdev); 147 148 if (!pch_ptp_match(skb, hi, lo, hi >> 16)) 149 goto out; 150 151 ns = pch_rx_snap_read(pdev); 152 153 shhwtstamps = skb_hwtstamps(skb); 154 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 155 shhwtstamps->hwtstamp = ns_to_ktime(ns); 156 out: 157 pch_ch_event_write(pdev, RX_SNAPSHOT_LOCKED); 158 } 159 160 static void 161 pch_tx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb) 162 { 163 struct skb_shared_hwtstamps shhwtstamps; 164 struct pci_dev *pdev; 165 struct skb_shared_info *shtx; 166 u64 ns; 167 u32 cnt, val; 168 169 shtx = skb_shinfo(skb); 170 if (likely(!(shtx->tx_flags & SKBTX_HW_TSTAMP && adapter->hwts_tx_en))) 171 return; 172 173 shtx->tx_flags |= SKBTX_IN_PROGRESS; 174 175 /* Get ieee1588's dev information */ 176 pdev = adapter->ptp_pdev; 177 178 /* 179 * This really stinks, but we have to poll for the Tx time stamp. 180 */ 181 for (cnt = 0; cnt < 100; cnt++) { 182 val = pch_ch_event_read(pdev); 183 if (val & TX_SNAPSHOT_LOCKED) 184 break; 185 udelay(1); 186 } 187 if (!(val & TX_SNAPSHOT_LOCKED)) { 188 shtx->tx_flags &= ~SKBTX_IN_PROGRESS; 189 return; 190 } 191 192 ns = pch_tx_snap_read(pdev); 193 194 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 195 shhwtstamps.hwtstamp = ns_to_ktime(ns); 196 skb_tstamp_tx(skb, &shhwtstamps); 197 198 pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED); 199 } 200 201 static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 202 { 203 struct hwtstamp_config cfg; 204 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 205 struct pci_dev *pdev; 206 u8 station[20]; 207 208 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 209 return -EFAULT; 210 211 /* Get ieee1588's dev information */ 212 pdev = adapter->ptp_pdev; 213 214 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 215 return -ERANGE; 216 217 switch (cfg.rx_filter) { 218 case HWTSTAMP_FILTER_NONE: 219 adapter->hwts_rx_en = 0; 220 break; 221 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 222 adapter->hwts_rx_en = 0; 223 pch_ch_control_write(pdev, SLAVE_MODE | CAP_MODE0); 224 break; 225 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 226 adapter->hwts_rx_en = 1; 227 pch_ch_control_write(pdev, MASTER_MODE | CAP_MODE0); 228 break; 229 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 230 adapter->hwts_rx_en = 1; 231 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2); 232 strcpy(station, PTP_L4_MULTICAST_SA); 233 pch_set_station_address(station, pdev); 234 break; 235 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 236 adapter->hwts_rx_en = 1; 237 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2); 238 strcpy(station, PTP_L2_MULTICAST_SA); 239 pch_set_station_address(station, pdev); 240 break; 241 default: 242 return -ERANGE; 243 } 244 245 adapter->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON; 246 247 /* Clear out any old time stamps. */ 248 pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED); 249 250 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 251 } 252 253 static inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw) 254 { 255 iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD); 256 } 257 258 /** 259 * pch_gbe_mac_read_mac_addr - Read MAC address 260 * @hw: Pointer to the HW structure 261 * Returns: 262 * 0: Successful. 263 */ 264 static s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw) 265 { 266 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 267 u32 adr1a, adr1b; 268 269 adr1a = ioread32(&hw->reg->mac_adr[0].high); 270 adr1b = ioread32(&hw->reg->mac_adr[0].low); 271 272 hw->mac.addr[0] = (u8)(adr1a & 0xFF); 273 hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF); 274 hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF); 275 hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF); 276 hw->mac.addr[4] = (u8)(adr1b & 0xFF); 277 hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF); 278 279 netdev_dbg(adapter->netdev, "hw->mac.addr : %pM\n", hw->mac.addr); 280 return 0; 281 } 282 283 /** 284 * pch_gbe_wait_clr_bit - Wait to clear a bit 285 * @reg: Pointer of register 286 * @bit: Busy bit 287 */ 288 static void pch_gbe_wait_clr_bit(void __iomem *reg, u32 bit) 289 { 290 u32 tmp; 291 292 /* wait busy */ 293 if (readx_poll_timeout_atomic(ioread32, reg, tmp, !(tmp & bit), 0, 10)) 294 pr_err("Error: busy bit is not cleared\n"); 295 } 296 297 /** 298 * pch_gbe_mac_mar_set - Set MAC address register 299 * @hw: Pointer to the HW structure 300 * @addr: Pointer to the MAC address 301 * @index: MAC address array register 302 */ 303 static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index) 304 { 305 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 306 u32 mar_low, mar_high, adrmask; 307 308 netdev_dbg(adapter->netdev, "index : 0x%x\n", index); 309 310 /* 311 * HW expects these in little endian so we reverse the byte order 312 * from network order (big endian) to little endian 313 */ 314 mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) | 315 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 316 mar_low = ((u32) addr[4] | ((u32) addr[5] << 8)); 317 /* Stop the MAC Address of index. */ 318 adrmask = ioread32(&hw->reg->ADDR_MASK); 319 iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK); 320 /* wait busy */ 321 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); 322 /* Set the MAC address to the MAC address 1A/1B register */ 323 iowrite32(mar_high, &hw->reg->mac_adr[index].high); 324 iowrite32(mar_low, &hw->reg->mac_adr[index].low); 325 /* Start the MAC address of index */ 326 iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK); 327 /* wait busy */ 328 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); 329 } 330 331 /** 332 * pch_gbe_mac_reset_hw - Reset hardware 333 * @hw: Pointer to the HW structure 334 */ 335 static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw) 336 { 337 /* Read the MAC address. and store to the private data */ 338 pch_gbe_mac_read_mac_addr(hw); 339 iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET); 340 iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE); 341 pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST); 342 /* Setup the receive addresses */ 343 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0); 344 return; 345 } 346 347 static void pch_gbe_disable_mac_rx(struct pch_gbe_hw *hw) 348 { 349 u32 rctl; 350 /* Disables Receive MAC */ 351 rctl = ioread32(&hw->reg->MAC_RX_EN); 352 iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN); 353 } 354 355 static void pch_gbe_enable_mac_rx(struct pch_gbe_hw *hw) 356 { 357 u32 rctl; 358 /* Enables Receive MAC */ 359 rctl = ioread32(&hw->reg->MAC_RX_EN); 360 iowrite32((rctl | PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN); 361 } 362 363 /** 364 * pch_gbe_mac_init_rx_addrs - Initialize receive address's 365 * @hw: Pointer to the HW structure 366 * @mar_count: Receive address registers 367 */ 368 static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count) 369 { 370 u32 i; 371 372 /* Setup the receive address */ 373 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0); 374 375 /* Zero out the other receive addresses */ 376 for (i = 1; i < mar_count; i++) { 377 iowrite32(0, &hw->reg->mac_adr[i].high); 378 iowrite32(0, &hw->reg->mac_adr[i].low); 379 } 380 iowrite32(0xFFFE, &hw->reg->ADDR_MASK); 381 /* wait busy */ 382 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); 383 } 384 385 /** 386 * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings 387 * @hw: Pointer to the HW structure 388 * Returns: 389 * 0: Successful. 390 * Negative value: Failed. 391 */ 392 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw) 393 { 394 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 395 struct pch_gbe_mac_info *mac = &hw->mac; 396 u32 rx_fctrl; 397 398 netdev_dbg(adapter->netdev, "mac->fc = %u\n", mac->fc); 399 400 rx_fctrl = ioread32(&hw->reg->RX_FCTRL); 401 402 switch (mac->fc) { 403 case PCH_GBE_FC_NONE: 404 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN; 405 mac->tx_fc_enable = false; 406 break; 407 case PCH_GBE_FC_RX_PAUSE: 408 rx_fctrl |= PCH_GBE_FL_CTRL_EN; 409 mac->tx_fc_enable = false; 410 break; 411 case PCH_GBE_FC_TX_PAUSE: 412 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN; 413 mac->tx_fc_enable = true; 414 break; 415 case PCH_GBE_FC_FULL: 416 rx_fctrl |= PCH_GBE_FL_CTRL_EN; 417 mac->tx_fc_enable = true; 418 break; 419 default: 420 netdev_err(adapter->netdev, 421 "Flow control param set incorrectly\n"); 422 return -EINVAL; 423 } 424 if (mac->link_duplex == DUPLEX_HALF) 425 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN; 426 iowrite32(rx_fctrl, &hw->reg->RX_FCTRL); 427 netdev_dbg(adapter->netdev, 428 "RX_FCTRL reg : 0x%08x mac->tx_fc_enable : %d\n", 429 ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable); 430 return 0; 431 } 432 433 /** 434 * pch_gbe_mac_set_wol_event - Set wake-on-lan event 435 * @hw: Pointer to the HW structure 436 * @wu_evt: Wake up event 437 */ 438 static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt) 439 { 440 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 441 u32 addr_mask; 442 443 netdev_dbg(adapter->netdev, "wu_evt : 0x%08x ADDR_MASK reg : 0x%08x\n", 444 wu_evt, ioread32(&hw->reg->ADDR_MASK)); 445 446 if (wu_evt) { 447 /* Set Wake-On-Lan address mask */ 448 addr_mask = ioread32(&hw->reg->ADDR_MASK); 449 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK); 450 /* wait busy */ 451 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY); 452 iowrite32(0, &hw->reg->WOL_ST); 453 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL); 454 iowrite32(0x02, &hw->reg->TCPIP_ACC); 455 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN); 456 } else { 457 iowrite32(0, &hw->reg->WOL_CTRL); 458 iowrite32(0, &hw->reg->WOL_ST); 459 } 460 return; 461 } 462 463 /** 464 * pch_gbe_mac_ctrl_miim - Control MIIM interface 465 * @hw: Pointer to the HW structure 466 * @addr: Address of PHY 467 * @dir: Operetion. (Write or Read) 468 * @reg: Access register of PHY 469 * @data: Write data. 470 * 471 * Returns: Read date. 472 */ 473 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg, 474 u16 data) 475 { 476 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 477 unsigned long flags; 478 u32 data_out; 479 480 spin_lock_irqsave(&hw->miim_lock, flags); 481 482 if (readx_poll_timeout_atomic(ioread32, &hw->reg->MIIM, data_out, 483 data_out & PCH_GBE_MIIM_OPER_READY, 20, 2000)) { 484 netdev_err(adapter->netdev, "pch-gbe.miim won't go Ready\n"); 485 spin_unlock_irqrestore(&hw->miim_lock, flags); 486 return 0; /* No way to indicate timeout error */ 487 } 488 iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) | 489 (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) | 490 dir | data), &hw->reg->MIIM); 491 readx_poll_timeout_atomic(ioread32, &hw->reg->MIIM, data_out, 492 data_out & PCH_GBE_MIIM_OPER_READY, 20, 2000); 493 spin_unlock_irqrestore(&hw->miim_lock, flags); 494 495 netdev_dbg(adapter->netdev, "PHY %s: reg=%d, data=0x%04X\n", 496 dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg, 497 dir == PCH_GBE_MIIM_OPER_READ ? data_out : data); 498 return (u16) data_out; 499 } 500 501 /** 502 * pch_gbe_mac_set_pause_packet - Set pause packet 503 * @hw: Pointer to the HW structure 504 */ 505 static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw) 506 { 507 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 508 unsigned long tmp2, tmp3; 509 510 /* Set Pause packet */ 511 tmp2 = hw->mac.addr[1]; 512 tmp2 = (tmp2 << 8) | hw->mac.addr[0]; 513 tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16); 514 515 tmp3 = hw->mac.addr[5]; 516 tmp3 = (tmp3 << 8) | hw->mac.addr[4]; 517 tmp3 = (tmp3 << 8) | hw->mac.addr[3]; 518 tmp3 = (tmp3 << 8) | hw->mac.addr[2]; 519 520 iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1); 521 iowrite32(tmp2, &hw->reg->PAUSE_PKT2); 522 iowrite32(tmp3, &hw->reg->PAUSE_PKT3); 523 iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4); 524 iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5); 525 526 /* Transmit Pause Packet */ 527 iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ); 528 529 netdev_dbg(adapter->netdev, 530 "PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 531 ioread32(&hw->reg->PAUSE_PKT1), 532 ioread32(&hw->reg->PAUSE_PKT2), 533 ioread32(&hw->reg->PAUSE_PKT3), 534 ioread32(&hw->reg->PAUSE_PKT4), 535 ioread32(&hw->reg->PAUSE_PKT5)); 536 537 return; 538 } 539 540 541 /** 542 * pch_gbe_alloc_queues - Allocate memory for all rings 543 * @adapter: Board private structure to initialize 544 * Returns: 545 * 0: Successfully 546 * Negative value: Failed 547 */ 548 static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter) 549 { 550 adapter->tx_ring = devm_kzalloc(&adapter->pdev->dev, 551 sizeof(*adapter->tx_ring), GFP_KERNEL); 552 if (!adapter->tx_ring) 553 return -ENOMEM; 554 555 adapter->rx_ring = devm_kzalloc(&adapter->pdev->dev, 556 sizeof(*adapter->rx_ring), GFP_KERNEL); 557 if (!adapter->rx_ring) 558 return -ENOMEM; 559 return 0; 560 } 561 562 /** 563 * pch_gbe_init_stats - Initialize status 564 * @adapter: Board private structure to initialize 565 */ 566 static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter) 567 { 568 memset(&adapter->stats, 0, sizeof(adapter->stats)); 569 return; 570 } 571 572 /** 573 * pch_gbe_init_phy - Initialize PHY 574 * @adapter: Board private structure to initialize 575 * Returns: 576 * 0: Successfully 577 * Negative value: Failed 578 */ 579 static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter) 580 { 581 struct net_device *netdev = adapter->netdev; 582 u32 addr; 583 u16 bmcr, stat; 584 585 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */ 586 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) { 587 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr; 588 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR); 589 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR); 590 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR); 591 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0)))) 592 break; 593 } 594 adapter->hw.phy.addr = adapter->mii.phy_id; 595 netdev_dbg(netdev, "phy_addr = %d\n", adapter->mii.phy_id); 596 if (addr == PCH_GBE_PHY_REGS_LEN) 597 return -EAGAIN; 598 /* Selected the phy and isolate the rest */ 599 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) { 600 if (addr != adapter->mii.phy_id) { 601 pch_gbe_mdio_write(netdev, addr, MII_BMCR, 602 BMCR_ISOLATE); 603 } else { 604 bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR); 605 pch_gbe_mdio_write(netdev, addr, MII_BMCR, 606 bmcr & ~BMCR_ISOLATE); 607 } 608 } 609 610 /* MII setup */ 611 adapter->mii.phy_id_mask = 0x1F; 612 adapter->mii.reg_num_mask = 0x1F; 613 adapter->mii.dev = adapter->netdev; 614 adapter->mii.mdio_read = pch_gbe_mdio_read; 615 adapter->mii.mdio_write = pch_gbe_mdio_write; 616 adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii); 617 return 0; 618 } 619 620 /** 621 * pch_gbe_mdio_read - The read function for mii 622 * @netdev: Network interface device structure 623 * @addr: Phy ID 624 * @reg: Access location 625 * Returns: 626 * 0: Successfully 627 * Negative value: Failed 628 */ 629 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg) 630 { 631 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 632 struct pch_gbe_hw *hw = &adapter->hw; 633 634 return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg, 635 (u16) 0); 636 } 637 638 /** 639 * pch_gbe_mdio_write - The write function for mii 640 * @netdev: Network interface device structure 641 * @addr: Phy ID (not used) 642 * @reg: Access location 643 * @data: Write data 644 */ 645 static void pch_gbe_mdio_write(struct net_device *netdev, 646 int addr, int reg, int data) 647 { 648 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 649 struct pch_gbe_hw *hw = &adapter->hw; 650 651 pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data); 652 } 653 654 /** 655 * pch_gbe_reset_task - Reset processing at the time of transmission timeout 656 * @work: Pointer of board private structure 657 */ 658 static void pch_gbe_reset_task(struct work_struct *work) 659 { 660 struct pch_gbe_adapter *adapter; 661 adapter = container_of(work, struct pch_gbe_adapter, reset_task); 662 663 rtnl_lock(); 664 pch_gbe_reinit_locked(adapter); 665 rtnl_unlock(); 666 } 667 668 /** 669 * pch_gbe_reinit_locked- Re-initialization 670 * @adapter: Board private structure 671 */ 672 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter) 673 { 674 pch_gbe_down(adapter); 675 pch_gbe_up(adapter); 676 } 677 678 /** 679 * pch_gbe_reset - Reset GbE 680 * @adapter: Board private structure 681 */ 682 void pch_gbe_reset(struct pch_gbe_adapter *adapter) 683 { 684 struct net_device *netdev = adapter->netdev; 685 struct pch_gbe_hw *hw = &adapter->hw; 686 s32 ret_val; 687 688 pch_gbe_mac_reset_hw(hw); 689 /* reprogram multicast address register after reset */ 690 pch_gbe_set_multi(netdev); 691 /* Setup the receive address. */ 692 pch_gbe_mac_init_rx_addrs(hw, PCH_GBE_MAR_ENTRIES); 693 694 ret_val = pch_gbe_phy_get_id(hw); 695 if (ret_val) { 696 netdev_err(adapter->netdev, "pch_gbe_phy_get_id error\n"); 697 return; 698 } 699 pch_gbe_phy_init_setting(hw); 700 /* Setup Mac interface option RGMII */ 701 pch_gbe_phy_set_rgmii(hw); 702 } 703 704 /** 705 * pch_gbe_free_irq - Free an interrupt 706 * @adapter: Board private structure 707 */ 708 static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter) 709 { 710 struct net_device *netdev = adapter->netdev; 711 712 free_irq(adapter->irq, netdev); 713 pci_free_irq_vectors(adapter->pdev); 714 } 715 716 /** 717 * pch_gbe_irq_disable - Mask off interrupt generation on the NIC 718 * @adapter: Board private structure 719 */ 720 static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter) 721 { 722 struct pch_gbe_hw *hw = &adapter->hw; 723 724 atomic_inc(&adapter->irq_sem); 725 iowrite32(0, &hw->reg->INT_EN); 726 ioread32(&hw->reg->INT_ST); 727 synchronize_irq(adapter->irq); 728 729 netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n", 730 ioread32(&hw->reg->INT_EN)); 731 } 732 733 /** 734 * pch_gbe_irq_enable - Enable default interrupt generation settings 735 * @adapter: Board private structure 736 */ 737 static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter) 738 { 739 struct pch_gbe_hw *hw = &adapter->hw; 740 741 if (likely(atomic_dec_and_test(&adapter->irq_sem))) 742 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN); 743 ioread32(&hw->reg->INT_ST); 744 netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n", 745 ioread32(&hw->reg->INT_EN)); 746 } 747 748 749 750 /** 751 * pch_gbe_setup_tctl - configure the Transmit control registers 752 * @adapter: Board private structure 753 */ 754 static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter) 755 { 756 struct pch_gbe_hw *hw = &adapter->hw; 757 u32 tx_mode, tcpip; 758 759 tx_mode = PCH_GBE_TM_LONG_PKT | 760 PCH_GBE_TM_ST_AND_FD | 761 PCH_GBE_TM_SHORT_PKT | 762 PCH_GBE_TM_TH_TX_STRT_8 | 763 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8; 764 765 iowrite32(tx_mode, &hw->reg->TX_MODE); 766 767 tcpip = ioread32(&hw->reg->TCPIP_ACC); 768 tcpip |= PCH_GBE_TX_TCPIPACC_EN; 769 iowrite32(tcpip, &hw->reg->TCPIP_ACC); 770 return; 771 } 772 773 /** 774 * pch_gbe_configure_tx - Configure Transmit Unit after Reset 775 * @adapter: Board private structure 776 */ 777 static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter) 778 { 779 struct pch_gbe_hw *hw = &adapter->hw; 780 u32 tdba, tdlen, dctrl; 781 782 netdev_dbg(adapter->netdev, "dma addr = 0x%08llx size = 0x%08x\n", 783 (unsigned long long)adapter->tx_ring->dma, 784 adapter->tx_ring->size); 785 786 /* Setup the HW Tx Head and Tail descriptor pointers */ 787 tdba = adapter->tx_ring->dma; 788 tdlen = adapter->tx_ring->size - 0x10; 789 iowrite32(tdba, &hw->reg->TX_DSC_BASE); 790 iowrite32(tdlen, &hw->reg->TX_DSC_SIZE); 791 iowrite32(tdba, &hw->reg->TX_DSC_SW_P); 792 793 /* Enables Transmission DMA */ 794 dctrl = ioread32(&hw->reg->DMA_CTRL); 795 dctrl |= PCH_GBE_TX_DMA_EN; 796 iowrite32(dctrl, &hw->reg->DMA_CTRL); 797 } 798 799 /** 800 * pch_gbe_setup_rctl - Configure the receive control registers 801 * @adapter: Board private structure 802 */ 803 static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter) 804 { 805 struct pch_gbe_hw *hw = &adapter->hw; 806 u32 rx_mode, tcpip; 807 808 rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN | 809 PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8; 810 811 iowrite32(rx_mode, &hw->reg->RX_MODE); 812 813 tcpip = ioread32(&hw->reg->TCPIP_ACC); 814 815 tcpip |= PCH_GBE_RX_TCPIPACC_OFF; 816 tcpip &= ~PCH_GBE_RX_TCPIPACC_EN; 817 iowrite32(tcpip, &hw->reg->TCPIP_ACC); 818 return; 819 } 820 821 /** 822 * pch_gbe_configure_rx - Configure Receive Unit after Reset 823 * @adapter: Board private structure 824 */ 825 static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter) 826 { 827 struct pch_gbe_hw *hw = &adapter->hw; 828 u32 rdba, rdlen, rxdma; 829 830 netdev_dbg(adapter->netdev, "dma adr = 0x%08llx size = 0x%08x\n", 831 (unsigned long long)adapter->rx_ring->dma, 832 adapter->rx_ring->size); 833 834 pch_gbe_mac_force_mac_fc(hw); 835 836 pch_gbe_disable_mac_rx(hw); 837 838 /* Disables Receive DMA */ 839 rxdma = ioread32(&hw->reg->DMA_CTRL); 840 rxdma &= ~PCH_GBE_RX_DMA_EN; 841 iowrite32(rxdma, &hw->reg->DMA_CTRL); 842 843 netdev_dbg(adapter->netdev, 844 "MAC_RX_EN reg = 0x%08x DMA_CTRL reg = 0x%08x\n", 845 ioread32(&hw->reg->MAC_RX_EN), 846 ioread32(&hw->reg->DMA_CTRL)); 847 848 /* Setup the HW Rx Head and Tail Descriptor Pointers and 849 * the Base and Length of the Rx Descriptor Ring */ 850 rdba = adapter->rx_ring->dma; 851 rdlen = adapter->rx_ring->size - 0x10; 852 iowrite32(rdba, &hw->reg->RX_DSC_BASE); 853 iowrite32(rdlen, &hw->reg->RX_DSC_SIZE); 854 iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P); 855 } 856 857 /** 858 * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer 859 * @adapter: Board private structure 860 * @buffer_info: Buffer information structure 861 */ 862 static void pch_gbe_unmap_and_free_tx_resource( 863 struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info) 864 { 865 if (buffer_info->mapped) { 866 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 867 buffer_info->length, DMA_TO_DEVICE); 868 buffer_info->mapped = false; 869 } 870 if (buffer_info->skb) { 871 dev_kfree_skb_any(buffer_info->skb); 872 buffer_info->skb = NULL; 873 } 874 } 875 876 /** 877 * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer 878 * @adapter: Board private structure 879 * @buffer_info: Buffer information structure 880 */ 881 static void pch_gbe_unmap_and_free_rx_resource( 882 struct pch_gbe_adapter *adapter, 883 struct pch_gbe_buffer *buffer_info) 884 { 885 if (buffer_info->mapped) { 886 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 887 buffer_info->length, DMA_FROM_DEVICE); 888 buffer_info->mapped = false; 889 } 890 if (buffer_info->skb) { 891 dev_kfree_skb_any(buffer_info->skb); 892 buffer_info->skb = NULL; 893 } 894 } 895 896 /** 897 * pch_gbe_clean_tx_ring - Free Tx Buffers 898 * @adapter: Board private structure 899 * @tx_ring: Ring to be cleaned 900 */ 901 static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter, 902 struct pch_gbe_tx_ring *tx_ring) 903 { 904 struct pch_gbe_hw *hw = &adapter->hw; 905 struct pch_gbe_buffer *buffer_info; 906 unsigned long size; 907 unsigned int i; 908 909 /* Free all the Tx ring sk_buffs */ 910 for (i = 0; i < tx_ring->count; i++) { 911 buffer_info = &tx_ring->buffer_info[i]; 912 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info); 913 } 914 netdev_dbg(adapter->netdev, 915 "call pch_gbe_unmap_and_free_tx_resource() %d count\n", i); 916 917 size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count; 918 memset(tx_ring->buffer_info, 0, size); 919 920 /* Zero out the descriptor ring */ 921 memset(tx_ring->desc, 0, tx_ring->size); 922 tx_ring->next_to_use = 0; 923 tx_ring->next_to_clean = 0; 924 iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P); 925 iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE); 926 } 927 928 /** 929 * pch_gbe_clean_rx_ring - Free Rx Buffers 930 * @adapter: Board private structure 931 * @rx_ring: Ring to free buffers from 932 */ 933 static void 934 pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter, 935 struct pch_gbe_rx_ring *rx_ring) 936 { 937 struct pch_gbe_hw *hw = &adapter->hw; 938 struct pch_gbe_buffer *buffer_info; 939 unsigned long size; 940 unsigned int i; 941 942 /* Free all the Rx ring sk_buffs */ 943 for (i = 0; i < rx_ring->count; i++) { 944 buffer_info = &rx_ring->buffer_info[i]; 945 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info); 946 } 947 netdev_dbg(adapter->netdev, 948 "call pch_gbe_unmap_and_free_rx_resource() %d count\n", i); 949 size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count; 950 memset(rx_ring->buffer_info, 0, size); 951 952 /* Zero out the descriptor ring */ 953 memset(rx_ring->desc, 0, rx_ring->size); 954 rx_ring->next_to_clean = 0; 955 rx_ring->next_to_use = 0; 956 iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P); 957 iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE); 958 } 959 960 static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed, 961 u16 duplex) 962 { 963 struct pch_gbe_hw *hw = &adapter->hw; 964 unsigned long rgmii = 0; 965 966 /* Set the RGMII control. */ 967 switch (speed) { 968 case SPEED_10: 969 rgmii = (PCH_GBE_RGMII_RATE_2_5M | 970 PCH_GBE_MAC_RGMII_CTRL_SETTING); 971 break; 972 case SPEED_100: 973 rgmii = (PCH_GBE_RGMII_RATE_25M | 974 PCH_GBE_MAC_RGMII_CTRL_SETTING); 975 break; 976 case SPEED_1000: 977 rgmii = (PCH_GBE_RGMII_RATE_125M | 978 PCH_GBE_MAC_RGMII_CTRL_SETTING); 979 break; 980 } 981 iowrite32(rgmii, &hw->reg->RGMII_CTRL); 982 } 983 static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed, 984 u16 duplex) 985 { 986 struct net_device *netdev = adapter->netdev; 987 struct pch_gbe_hw *hw = &adapter->hw; 988 unsigned long mode = 0; 989 990 /* Set the communication mode */ 991 switch (speed) { 992 case SPEED_10: 993 mode = PCH_GBE_MODE_MII_ETHER; 994 netdev->tx_queue_len = 10; 995 break; 996 case SPEED_100: 997 mode = PCH_GBE_MODE_MII_ETHER; 998 netdev->tx_queue_len = 100; 999 break; 1000 case SPEED_1000: 1001 mode = PCH_GBE_MODE_GMII_ETHER; 1002 break; 1003 } 1004 if (duplex == DUPLEX_FULL) 1005 mode |= PCH_GBE_MODE_FULL_DUPLEX; 1006 else 1007 mode |= PCH_GBE_MODE_HALF_DUPLEX; 1008 iowrite32(mode, &hw->reg->MODE); 1009 } 1010 1011 /** 1012 * pch_gbe_watchdog - Watchdog process 1013 * @t: timer list containing a Board private structure 1014 */ 1015 static void pch_gbe_watchdog(struct timer_list *t) 1016 { 1017 struct pch_gbe_adapter *adapter = from_timer(adapter, t, 1018 watchdog_timer); 1019 struct net_device *netdev = adapter->netdev; 1020 struct pch_gbe_hw *hw = &adapter->hw; 1021 1022 netdev_dbg(netdev, "right now = %ld\n", jiffies); 1023 1024 pch_gbe_update_stats(adapter); 1025 if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) { 1026 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET }; 1027 netdev->tx_queue_len = adapter->tx_queue_len; 1028 /* mii library handles link maintenance tasks */ 1029 mii_ethtool_gset(&adapter->mii, &cmd); 1030 hw->mac.link_speed = ethtool_cmd_speed(&cmd); 1031 hw->mac.link_duplex = cmd.duplex; 1032 /* Set the RGMII control. */ 1033 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed, 1034 hw->mac.link_duplex); 1035 /* Set the communication mode */ 1036 pch_gbe_set_mode(adapter, hw->mac.link_speed, 1037 hw->mac.link_duplex); 1038 netdev_dbg(netdev, 1039 "Link is Up %d Mbps %s-Duplex\n", 1040 hw->mac.link_speed, 1041 cmd.duplex == DUPLEX_FULL ? "Full" : "Half"); 1042 netif_carrier_on(netdev); 1043 netif_wake_queue(netdev); 1044 } else if ((!mii_link_ok(&adapter->mii)) && 1045 (netif_carrier_ok(netdev))) { 1046 netdev_dbg(netdev, "NIC Link is Down\n"); 1047 hw->mac.link_speed = SPEED_10; 1048 hw->mac.link_duplex = DUPLEX_HALF; 1049 netif_carrier_off(netdev); 1050 netif_stop_queue(netdev); 1051 } 1052 mod_timer(&adapter->watchdog_timer, 1053 round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD)); 1054 } 1055 1056 /** 1057 * pch_gbe_tx_queue - Carry out queuing of the transmission data 1058 * @adapter: Board private structure 1059 * @tx_ring: Tx descriptor ring structure 1060 * @skb: Sockt buffer structure 1061 */ 1062 static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter, 1063 struct pch_gbe_tx_ring *tx_ring, 1064 struct sk_buff *skb) 1065 { 1066 struct pch_gbe_hw *hw = &adapter->hw; 1067 struct pch_gbe_tx_desc *tx_desc; 1068 struct pch_gbe_buffer *buffer_info; 1069 struct sk_buff *tmp_skb; 1070 unsigned int frame_ctrl; 1071 unsigned int ring_num; 1072 1073 /*-- Set frame control --*/ 1074 frame_ctrl = 0; 1075 if (unlikely(skb->len < PCH_GBE_SHORT_PKT)) 1076 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD; 1077 if (skb->ip_summed == CHECKSUM_NONE) 1078 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF; 1079 1080 /* Performs checksum processing */ 1081 /* 1082 * It is because the hardware accelerator does not support a checksum, 1083 * when the received data size is less than 64 bytes. 1084 */ 1085 if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) { 1086 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD | 1087 PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF; 1088 if (skb->protocol == htons(ETH_P_IP)) { 1089 struct iphdr *iph = ip_hdr(skb); 1090 unsigned int offset; 1091 offset = skb_transport_offset(skb); 1092 if (iph->protocol == IPPROTO_TCP) { 1093 skb->csum = 0; 1094 tcp_hdr(skb)->check = 0; 1095 skb->csum = skb_checksum(skb, offset, 1096 skb->len - offset, 0); 1097 tcp_hdr(skb)->check = 1098 csum_tcpudp_magic(iph->saddr, 1099 iph->daddr, 1100 skb->len - offset, 1101 IPPROTO_TCP, 1102 skb->csum); 1103 } else if (iph->protocol == IPPROTO_UDP) { 1104 skb->csum = 0; 1105 udp_hdr(skb)->check = 0; 1106 skb->csum = 1107 skb_checksum(skb, offset, 1108 skb->len - offset, 0); 1109 udp_hdr(skb)->check = 1110 csum_tcpudp_magic(iph->saddr, 1111 iph->daddr, 1112 skb->len - offset, 1113 IPPROTO_UDP, 1114 skb->csum); 1115 } 1116 } 1117 } 1118 1119 ring_num = tx_ring->next_to_use; 1120 if (unlikely((ring_num + 1) == tx_ring->count)) 1121 tx_ring->next_to_use = 0; 1122 else 1123 tx_ring->next_to_use = ring_num + 1; 1124 1125 1126 buffer_info = &tx_ring->buffer_info[ring_num]; 1127 tmp_skb = buffer_info->skb; 1128 1129 /* [Header:14][payload] ---> [Header:14][paddong:2][payload] */ 1130 memcpy(tmp_skb->data, skb->data, ETH_HLEN); 1131 tmp_skb->data[ETH_HLEN] = 0x00; 1132 tmp_skb->data[ETH_HLEN + 1] = 0x00; 1133 tmp_skb->len = skb->len; 1134 memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN], 1135 (skb->len - ETH_HLEN)); 1136 /*-- Set Buffer information --*/ 1137 buffer_info->length = tmp_skb->len; 1138 buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data, 1139 buffer_info->length, 1140 DMA_TO_DEVICE); 1141 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) { 1142 netdev_err(adapter->netdev, "TX DMA map failed\n"); 1143 buffer_info->dma = 0; 1144 buffer_info->time_stamp = 0; 1145 tx_ring->next_to_use = ring_num; 1146 dev_kfree_skb_any(skb); 1147 return; 1148 } 1149 buffer_info->mapped = true; 1150 buffer_info->time_stamp = jiffies; 1151 1152 /*-- Set Tx descriptor --*/ 1153 tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num); 1154 tx_desc->buffer_addr = (buffer_info->dma); 1155 tx_desc->length = (tmp_skb->len); 1156 tx_desc->tx_words_eob = ((tmp_skb->len + 3)); 1157 tx_desc->tx_frame_ctrl = (frame_ctrl); 1158 tx_desc->gbec_status = (DSC_INIT16); 1159 1160 if (unlikely(++ring_num == tx_ring->count)) 1161 ring_num = 0; 1162 1163 /* Update software pointer of TX descriptor */ 1164 iowrite32(tx_ring->dma + 1165 (int)sizeof(struct pch_gbe_tx_desc) * ring_num, 1166 &hw->reg->TX_DSC_SW_P); 1167 1168 pch_tx_timestamp(adapter, skb); 1169 1170 dev_kfree_skb_any(skb); 1171 } 1172 1173 /** 1174 * pch_gbe_update_stats - Update the board statistics counters 1175 * @adapter: Board private structure 1176 */ 1177 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter) 1178 { 1179 struct net_device *netdev = adapter->netdev; 1180 struct pci_dev *pdev = adapter->pdev; 1181 struct pch_gbe_hw_stats *stats = &adapter->stats; 1182 unsigned long flags; 1183 1184 /* 1185 * Prevent stats update while adapter is being reset, or if the pci 1186 * connection is down. 1187 */ 1188 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal)) 1189 return; 1190 1191 spin_lock_irqsave(&adapter->stats_lock, flags); 1192 1193 /* Update device status "adapter->stats" */ 1194 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors; 1195 stats->tx_errors = stats->tx_length_errors + 1196 stats->tx_aborted_errors + 1197 stats->tx_carrier_errors + stats->tx_timeout_count; 1198 1199 /* Update network device status "adapter->net_stats" */ 1200 netdev->stats.rx_packets = stats->rx_packets; 1201 netdev->stats.rx_bytes = stats->rx_bytes; 1202 netdev->stats.rx_dropped = stats->rx_dropped; 1203 netdev->stats.tx_packets = stats->tx_packets; 1204 netdev->stats.tx_bytes = stats->tx_bytes; 1205 netdev->stats.tx_dropped = stats->tx_dropped; 1206 /* Fill out the OS statistics structure */ 1207 netdev->stats.multicast = stats->multicast; 1208 netdev->stats.collisions = stats->collisions; 1209 /* Rx Errors */ 1210 netdev->stats.rx_errors = stats->rx_errors; 1211 netdev->stats.rx_crc_errors = stats->rx_crc_errors; 1212 netdev->stats.rx_frame_errors = stats->rx_frame_errors; 1213 /* Tx Errors */ 1214 netdev->stats.tx_errors = stats->tx_errors; 1215 netdev->stats.tx_aborted_errors = stats->tx_aborted_errors; 1216 netdev->stats.tx_carrier_errors = stats->tx_carrier_errors; 1217 1218 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1219 } 1220 1221 static void pch_gbe_disable_dma_rx(struct pch_gbe_hw *hw) 1222 { 1223 u32 rxdma; 1224 1225 /* Disable Receive DMA */ 1226 rxdma = ioread32(&hw->reg->DMA_CTRL); 1227 rxdma &= ~PCH_GBE_RX_DMA_EN; 1228 iowrite32(rxdma, &hw->reg->DMA_CTRL); 1229 } 1230 1231 static void pch_gbe_enable_dma_rx(struct pch_gbe_hw *hw) 1232 { 1233 u32 rxdma; 1234 1235 /* Enables Receive DMA */ 1236 rxdma = ioread32(&hw->reg->DMA_CTRL); 1237 rxdma |= PCH_GBE_RX_DMA_EN; 1238 iowrite32(rxdma, &hw->reg->DMA_CTRL); 1239 } 1240 1241 /** 1242 * pch_gbe_intr - Interrupt Handler 1243 * @irq: Interrupt number 1244 * @data: Pointer to a network interface device structure 1245 * Returns: 1246 * - IRQ_HANDLED: Our interrupt 1247 * - IRQ_NONE: Not our interrupt 1248 */ 1249 static irqreturn_t pch_gbe_intr(int irq, void *data) 1250 { 1251 struct net_device *netdev = data; 1252 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 1253 struct pch_gbe_hw *hw = &adapter->hw; 1254 u32 int_st; 1255 u32 int_en; 1256 1257 /* Check request status */ 1258 int_st = ioread32(&hw->reg->INT_ST); 1259 int_st = int_st & ioread32(&hw->reg->INT_EN); 1260 /* When request status is no interruption factor */ 1261 if (unlikely(!int_st)) 1262 return IRQ_NONE; /* Not our interrupt. End processing. */ 1263 netdev_dbg(netdev, "%s occur int_st = 0x%08x\n", __func__, int_st); 1264 if (int_st & PCH_GBE_INT_RX_FRAME_ERR) 1265 adapter->stats.intr_rx_frame_err_count++; 1266 if (int_st & PCH_GBE_INT_RX_FIFO_ERR) 1267 if (!adapter->rx_stop_flag) { 1268 adapter->stats.intr_rx_fifo_err_count++; 1269 netdev_dbg(netdev, "Rx fifo over run\n"); 1270 adapter->rx_stop_flag = true; 1271 int_en = ioread32(&hw->reg->INT_EN); 1272 iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR), 1273 &hw->reg->INT_EN); 1274 pch_gbe_disable_dma_rx(&adapter->hw); 1275 int_st |= ioread32(&hw->reg->INT_ST); 1276 int_st = int_st & ioread32(&hw->reg->INT_EN); 1277 } 1278 if (int_st & PCH_GBE_INT_RX_DMA_ERR) 1279 adapter->stats.intr_rx_dma_err_count++; 1280 if (int_st & PCH_GBE_INT_TX_FIFO_ERR) 1281 adapter->stats.intr_tx_fifo_err_count++; 1282 if (int_st & PCH_GBE_INT_TX_DMA_ERR) 1283 adapter->stats.intr_tx_dma_err_count++; 1284 if (int_st & PCH_GBE_INT_TCPIP_ERR) 1285 adapter->stats.intr_tcpip_err_count++; 1286 /* When Rx descriptor is empty */ 1287 if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) { 1288 adapter->stats.intr_rx_dsc_empty_count++; 1289 netdev_dbg(netdev, "Rx descriptor is empty\n"); 1290 int_en = ioread32(&hw->reg->INT_EN); 1291 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN); 1292 if (hw->mac.tx_fc_enable) { 1293 /* Set Pause packet */ 1294 pch_gbe_mac_set_pause_packet(hw); 1295 } 1296 } 1297 1298 /* When request status is Receive interruption */ 1299 if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT)) || 1300 (adapter->rx_stop_flag)) { 1301 if (likely(napi_schedule_prep(&adapter->napi))) { 1302 /* Enable only Rx Descriptor empty */ 1303 atomic_inc(&adapter->irq_sem); 1304 int_en = ioread32(&hw->reg->INT_EN); 1305 int_en &= 1306 ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT); 1307 iowrite32(int_en, &hw->reg->INT_EN); 1308 /* Start polling for NAPI */ 1309 __napi_schedule(&adapter->napi); 1310 } 1311 } 1312 netdev_dbg(netdev, "return = 0x%08x INT_EN reg = 0x%08x\n", 1313 IRQ_HANDLED, ioread32(&hw->reg->INT_EN)); 1314 return IRQ_HANDLED; 1315 } 1316 1317 /** 1318 * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended 1319 * @adapter: Board private structure 1320 * @rx_ring: Rx descriptor ring 1321 * @cleaned_count: Cleaned count 1322 */ 1323 static void 1324 pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter, 1325 struct pch_gbe_rx_ring *rx_ring, int cleaned_count) 1326 { 1327 struct net_device *netdev = adapter->netdev; 1328 struct pci_dev *pdev = adapter->pdev; 1329 struct pch_gbe_hw *hw = &adapter->hw; 1330 struct pch_gbe_rx_desc *rx_desc; 1331 struct pch_gbe_buffer *buffer_info; 1332 struct sk_buff *skb; 1333 unsigned int i; 1334 unsigned int bufsz; 1335 1336 bufsz = adapter->rx_buffer_len + NET_IP_ALIGN; 1337 i = rx_ring->next_to_use; 1338 1339 while ((cleaned_count--)) { 1340 buffer_info = &rx_ring->buffer_info[i]; 1341 skb = netdev_alloc_skb(netdev, bufsz); 1342 if (unlikely(!skb)) { 1343 /* Better luck next round */ 1344 adapter->stats.rx_alloc_buff_failed++; 1345 break; 1346 } 1347 /* align */ 1348 skb_reserve(skb, NET_IP_ALIGN); 1349 buffer_info->skb = skb; 1350 1351 buffer_info->dma = dma_map_single(&pdev->dev, 1352 buffer_info->rx_buffer, 1353 buffer_info->length, 1354 DMA_FROM_DEVICE); 1355 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) { 1356 dev_kfree_skb(skb); 1357 buffer_info->skb = NULL; 1358 buffer_info->dma = 0; 1359 adapter->stats.rx_alloc_buff_failed++; 1360 break; /* while !buffer_info->skb */ 1361 } 1362 buffer_info->mapped = true; 1363 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i); 1364 rx_desc->buffer_addr = (buffer_info->dma); 1365 rx_desc->gbec_status = DSC_INIT16; 1366 1367 netdev_dbg(netdev, 1368 "i = %d buffer_info->dma = 0x08%llx buffer_info->length = 0x%x\n", 1369 i, (unsigned long long)buffer_info->dma, 1370 buffer_info->length); 1371 1372 if (unlikely(++i == rx_ring->count)) 1373 i = 0; 1374 } 1375 if (likely(rx_ring->next_to_use != i)) { 1376 rx_ring->next_to_use = i; 1377 if (unlikely(i-- == 0)) 1378 i = (rx_ring->count - 1); 1379 iowrite32(rx_ring->dma + 1380 (int)sizeof(struct pch_gbe_rx_desc) * i, 1381 &hw->reg->RX_DSC_SW_P); 1382 } 1383 return; 1384 } 1385 1386 static int 1387 pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter *adapter, 1388 struct pch_gbe_rx_ring *rx_ring, int cleaned_count) 1389 { 1390 struct pci_dev *pdev = adapter->pdev; 1391 struct pch_gbe_buffer *buffer_info; 1392 unsigned int i; 1393 unsigned int bufsz; 1394 unsigned int size; 1395 1396 bufsz = adapter->rx_buffer_len; 1397 1398 size = rx_ring->count * bufsz + PCH_GBE_RESERVE_MEMORY; 1399 rx_ring->rx_buff_pool = 1400 dma_alloc_coherent(&pdev->dev, size, 1401 &rx_ring->rx_buff_pool_logic, GFP_KERNEL); 1402 if (!rx_ring->rx_buff_pool) 1403 return -ENOMEM; 1404 1405 rx_ring->rx_buff_pool_size = size; 1406 for (i = 0; i < rx_ring->count; i++) { 1407 buffer_info = &rx_ring->buffer_info[i]; 1408 buffer_info->rx_buffer = rx_ring->rx_buff_pool + bufsz * i; 1409 buffer_info->length = bufsz; 1410 } 1411 return 0; 1412 } 1413 1414 /** 1415 * pch_gbe_alloc_tx_buffers - Allocate transmit buffers 1416 * @adapter: Board private structure 1417 * @tx_ring: Tx descriptor ring 1418 */ 1419 static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter, 1420 struct pch_gbe_tx_ring *tx_ring) 1421 { 1422 struct pch_gbe_buffer *buffer_info; 1423 struct sk_buff *skb; 1424 unsigned int i; 1425 unsigned int bufsz; 1426 struct pch_gbe_tx_desc *tx_desc; 1427 1428 bufsz = 1429 adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN; 1430 1431 for (i = 0; i < tx_ring->count; i++) { 1432 buffer_info = &tx_ring->buffer_info[i]; 1433 skb = netdev_alloc_skb(adapter->netdev, bufsz); 1434 skb_reserve(skb, PCH_GBE_DMA_ALIGN); 1435 buffer_info->skb = skb; 1436 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i); 1437 tx_desc->gbec_status = (DSC_INIT16); 1438 } 1439 return; 1440 } 1441 1442 /** 1443 * pch_gbe_clean_tx - Reclaim resources after transmit completes 1444 * @adapter: Board private structure 1445 * @tx_ring: Tx descriptor ring 1446 * Returns: 1447 * true: Cleaned the descriptor 1448 * false: Not cleaned the descriptor 1449 */ 1450 static bool 1451 pch_gbe_clean_tx(struct pch_gbe_adapter *adapter, 1452 struct pch_gbe_tx_ring *tx_ring) 1453 { 1454 struct pch_gbe_tx_desc *tx_desc; 1455 struct pch_gbe_buffer *buffer_info; 1456 struct sk_buff *skb; 1457 unsigned int i; 1458 unsigned int cleaned_count = 0; 1459 bool cleaned = false; 1460 int unused, thresh; 1461 1462 netdev_dbg(adapter->netdev, "next_to_clean : %d\n", 1463 tx_ring->next_to_clean); 1464 1465 i = tx_ring->next_to_clean; 1466 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i); 1467 netdev_dbg(adapter->netdev, "gbec_status:0x%04x dma_status:0x%04x\n", 1468 tx_desc->gbec_status, tx_desc->dma_status); 1469 1470 unused = PCH_GBE_DESC_UNUSED(tx_ring); 1471 thresh = tx_ring->count - NAPI_POLL_WEIGHT; 1472 if ((tx_desc->gbec_status == DSC_INIT16) && (unused < thresh)) 1473 { /* current marked clean, tx queue filling up, do extra clean */ 1474 int j, k; 1475 if (unused < 8) { /* tx queue nearly full */ 1476 netdev_dbg(adapter->netdev, 1477 "clean_tx: transmit queue warning (%x,%x) unused=%d\n", 1478 tx_ring->next_to_clean, tx_ring->next_to_use, 1479 unused); 1480 } 1481 1482 /* current marked clean, scan for more that need cleaning. */ 1483 k = i; 1484 for (j = 0; j < NAPI_POLL_WEIGHT; j++) 1485 { 1486 tx_desc = PCH_GBE_TX_DESC(*tx_ring, k); 1487 if (tx_desc->gbec_status != DSC_INIT16) break; /*found*/ 1488 if (++k >= tx_ring->count) k = 0; /*increment, wrap*/ 1489 } 1490 if (j < NAPI_POLL_WEIGHT) { 1491 netdev_dbg(adapter->netdev, 1492 "clean_tx: unused=%d loops=%d found tx_desc[%x,%x:%x].gbec_status=%04x\n", 1493 unused, j, i, k, tx_ring->next_to_use, 1494 tx_desc->gbec_status); 1495 i = k; /*found one to clean, usu gbec_status==2000.*/ 1496 } 1497 } 1498 1499 while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) { 1500 netdev_dbg(adapter->netdev, "gbec_status:0x%04x\n", 1501 tx_desc->gbec_status); 1502 buffer_info = &tx_ring->buffer_info[i]; 1503 skb = buffer_info->skb; 1504 cleaned = true; 1505 1506 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) { 1507 adapter->stats.tx_aborted_errors++; 1508 netdev_err(adapter->netdev, "Transfer Abort Error\n"); 1509 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER) 1510 ) { 1511 adapter->stats.tx_carrier_errors++; 1512 netdev_err(adapter->netdev, 1513 "Transfer Carrier Sense Error\n"); 1514 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL) 1515 ) { 1516 adapter->stats.tx_aborted_errors++; 1517 netdev_err(adapter->netdev, 1518 "Transfer Collision Abort Error\n"); 1519 } else if ((tx_desc->gbec_status & 1520 (PCH_GBE_TXD_GMAC_STAT_SNGCOL | 1521 PCH_GBE_TXD_GMAC_STAT_MLTCOL))) { 1522 adapter->stats.collisions++; 1523 adapter->stats.tx_packets++; 1524 adapter->stats.tx_bytes += skb->len; 1525 netdev_dbg(adapter->netdev, "Transfer Collision\n"); 1526 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT) 1527 ) { 1528 adapter->stats.tx_packets++; 1529 adapter->stats.tx_bytes += skb->len; 1530 } 1531 if (buffer_info->mapped) { 1532 netdev_dbg(adapter->netdev, 1533 "unmap buffer_info->dma : %d\n", i); 1534 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 1535 buffer_info->length, DMA_TO_DEVICE); 1536 buffer_info->mapped = false; 1537 } 1538 if (buffer_info->skb) { 1539 netdev_dbg(adapter->netdev, 1540 "trim buffer_info->skb : %d\n", i); 1541 skb_trim(buffer_info->skb, 0); 1542 } 1543 tx_desc->gbec_status = DSC_INIT16; 1544 if (unlikely(++i == tx_ring->count)) 1545 i = 0; 1546 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i); 1547 1548 /* weight of a sort for tx, to avoid endless transmit cleanup */ 1549 if (cleaned_count++ == NAPI_POLL_WEIGHT) { 1550 cleaned = false; 1551 break; 1552 } 1553 } 1554 netdev_dbg(adapter->netdev, 1555 "called pch_gbe_unmap_and_free_tx_resource() %d count\n", 1556 cleaned_count); 1557 if (cleaned_count > 0) { /*skip this if nothing cleaned*/ 1558 /* Recover from running out of Tx resources in xmit_frame */ 1559 netif_tx_lock(adapter->netdev); 1560 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev)))) 1561 { 1562 netif_wake_queue(adapter->netdev); 1563 adapter->stats.tx_restart_count++; 1564 netdev_dbg(adapter->netdev, "Tx wake queue\n"); 1565 } 1566 1567 tx_ring->next_to_clean = i; 1568 1569 netdev_dbg(adapter->netdev, "next_to_clean : %d\n", 1570 tx_ring->next_to_clean); 1571 netif_tx_unlock(adapter->netdev); 1572 } 1573 return cleaned; 1574 } 1575 1576 /** 1577 * pch_gbe_clean_rx - Send received data up the network stack; legacy 1578 * @adapter: Board private structure 1579 * @rx_ring: Rx descriptor ring 1580 * @work_done: Completed count 1581 * @work_to_do: Request count 1582 * Returns: 1583 * true: Cleaned the descriptor 1584 * false: Not cleaned the descriptor 1585 */ 1586 static bool 1587 pch_gbe_clean_rx(struct pch_gbe_adapter *adapter, 1588 struct pch_gbe_rx_ring *rx_ring, 1589 int *work_done, int work_to_do) 1590 { 1591 struct net_device *netdev = adapter->netdev; 1592 struct pci_dev *pdev = adapter->pdev; 1593 struct pch_gbe_buffer *buffer_info; 1594 struct pch_gbe_rx_desc *rx_desc; 1595 u32 length; 1596 unsigned int i; 1597 unsigned int cleaned_count = 0; 1598 bool cleaned = false; 1599 struct sk_buff *skb; 1600 u8 dma_status; 1601 u16 gbec_status; 1602 u32 tcp_ip_status; 1603 1604 i = rx_ring->next_to_clean; 1605 1606 while (*work_done < work_to_do) { 1607 /* Check Rx descriptor status */ 1608 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i); 1609 if (rx_desc->gbec_status == DSC_INIT16) 1610 break; 1611 cleaned = true; 1612 cleaned_count++; 1613 1614 dma_status = rx_desc->dma_status; 1615 gbec_status = rx_desc->gbec_status; 1616 tcp_ip_status = rx_desc->tcp_ip_status; 1617 rx_desc->gbec_status = DSC_INIT16; 1618 buffer_info = &rx_ring->buffer_info[i]; 1619 skb = buffer_info->skb; 1620 buffer_info->skb = NULL; 1621 1622 /* unmap dma */ 1623 dma_unmap_single(&pdev->dev, buffer_info->dma, 1624 buffer_info->length, DMA_FROM_DEVICE); 1625 buffer_info->mapped = false; 1626 1627 netdev_dbg(netdev, 1628 "RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x TCP:0x%08x] BufInf = 0x%p\n", 1629 i, dma_status, gbec_status, tcp_ip_status, 1630 buffer_info); 1631 /* Error check */ 1632 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) { 1633 adapter->stats.rx_frame_errors++; 1634 netdev_err(netdev, "Receive Not Octal Error\n"); 1635 } else if (unlikely(gbec_status & 1636 PCH_GBE_RXD_GMAC_STAT_NBLERR)) { 1637 adapter->stats.rx_frame_errors++; 1638 netdev_err(netdev, "Receive Nibble Error\n"); 1639 } else if (unlikely(gbec_status & 1640 PCH_GBE_RXD_GMAC_STAT_CRCERR)) { 1641 adapter->stats.rx_crc_errors++; 1642 netdev_err(netdev, "Receive CRC Error\n"); 1643 } else { 1644 /* get receive length */ 1645 /* length convert[-3], length includes FCS length */ 1646 length = (rx_desc->rx_words_eob) - 3 - ETH_FCS_LEN; 1647 if (rx_desc->rx_words_eob & 0x02) 1648 length = length - 4; 1649 /* 1650 * buffer_info->rx_buffer: [Header:14][payload] 1651 * skb->data: [Reserve:2][Header:14][payload] 1652 */ 1653 memcpy(skb->data, buffer_info->rx_buffer, length); 1654 1655 /* update status of driver */ 1656 adapter->stats.rx_bytes += length; 1657 adapter->stats.rx_packets++; 1658 if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT)) 1659 adapter->stats.multicast++; 1660 /* Write meta date of skb */ 1661 skb_put(skb, length); 1662 1663 pch_rx_timestamp(adapter, skb); 1664 1665 skb->protocol = eth_type_trans(skb, netdev); 1666 if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK) 1667 skb->ip_summed = CHECKSUM_UNNECESSARY; 1668 else 1669 skb->ip_summed = CHECKSUM_NONE; 1670 1671 napi_gro_receive(&adapter->napi, skb); 1672 (*work_done)++; 1673 netdev_dbg(netdev, 1674 "Receive skb->ip_summed: %d length: %d\n", 1675 skb->ip_summed, length); 1676 } 1677 /* return some buffers to hardware, one at a time is too slow */ 1678 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) { 1679 pch_gbe_alloc_rx_buffers(adapter, rx_ring, 1680 cleaned_count); 1681 cleaned_count = 0; 1682 } 1683 if (++i == rx_ring->count) 1684 i = 0; 1685 } 1686 rx_ring->next_to_clean = i; 1687 if (cleaned_count) 1688 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); 1689 return cleaned; 1690 } 1691 1692 /** 1693 * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors) 1694 * @adapter: Board private structure 1695 * @tx_ring: Tx descriptor ring (for a specific queue) to setup 1696 * Returns: 1697 * 0: Successfully 1698 * Negative value: Failed 1699 */ 1700 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter, 1701 struct pch_gbe_tx_ring *tx_ring) 1702 { 1703 struct pci_dev *pdev = adapter->pdev; 1704 struct pch_gbe_tx_desc *tx_desc; 1705 int size; 1706 int desNo; 1707 1708 size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count; 1709 tx_ring->buffer_info = vzalloc(size); 1710 if (!tx_ring->buffer_info) 1711 return -ENOMEM; 1712 1713 tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc); 1714 1715 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size, 1716 &tx_ring->dma, GFP_KERNEL); 1717 if (!tx_ring->desc) { 1718 vfree(tx_ring->buffer_info); 1719 return -ENOMEM; 1720 } 1721 1722 tx_ring->next_to_use = 0; 1723 tx_ring->next_to_clean = 0; 1724 1725 for (desNo = 0; desNo < tx_ring->count; desNo++) { 1726 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo); 1727 tx_desc->gbec_status = DSC_INIT16; 1728 } 1729 netdev_dbg(adapter->netdev, 1730 "tx_ring->desc = 0x%p tx_ring->dma = 0x%08llx next_to_clean = 0x%08x next_to_use = 0x%08x\n", 1731 tx_ring->desc, (unsigned long long)tx_ring->dma, 1732 tx_ring->next_to_clean, tx_ring->next_to_use); 1733 return 0; 1734 } 1735 1736 /** 1737 * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors) 1738 * @adapter: Board private structure 1739 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 1740 * Returns: 1741 * 0: Successfully 1742 * Negative value: Failed 1743 */ 1744 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter, 1745 struct pch_gbe_rx_ring *rx_ring) 1746 { 1747 struct pci_dev *pdev = adapter->pdev; 1748 struct pch_gbe_rx_desc *rx_desc; 1749 int size; 1750 int desNo; 1751 1752 size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count; 1753 rx_ring->buffer_info = vzalloc(size); 1754 if (!rx_ring->buffer_info) 1755 return -ENOMEM; 1756 1757 rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc); 1758 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size, 1759 &rx_ring->dma, GFP_KERNEL); 1760 if (!rx_ring->desc) { 1761 vfree(rx_ring->buffer_info); 1762 return -ENOMEM; 1763 } 1764 rx_ring->next_to_clean = 0; 1765 rx_ring->next_to_use = 0; 1766 for (desNo = 0; desNo < rx_ring->count; desNo++) { 1767 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo); 1768 rx_desc->gbec_status = DSC_INIT16; 1769 } 1770 netdev_dbg(adapter->netdev, 1771 "rx_ring->desc = 0x%p rx_ring->dma = 0x%08llx next_to_clean = 0x%08x next_to_use = 0x%08x\n", 1772 rx_ring->desc, (unsigned long long)rx_ring->dma, 1773 rx_ring->next_to_clean, rx_ring->next_to_use); 1774 return 0; 1775 } 1776 1777 /** 1778 * pch_gbe_free_tx_resources - Free Tx Resources 1779 * @adapter: Board private structure 1780 * @tx_ring: Tx descriptor ring for a specific queue 1781 */ 1782 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter, 1783 struct pch_gbe_tx_ring *tx_ring) 1784 { 1785 struct pci_dev *pdev = adapter->pdev; 1786 1787 pch_gbe_clean_tx_ring(adapter, tx_ring); 1788 vfree(tx_ring->buffer_info); 1789 tx_ring->buffer_info = NULL; 1790 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, 1791 tx_ring->dma); 1792 tx_ring->desc = NULL; 1793 } 1794 1795 /** 1796 * pch_gbe_free_rx_resources - Free Rx Resources 1797 * @adapter: Board private structure 1798 * @rx_ring: Ring to clean the resources from 1799 */ 1800 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter, 1801 struct pch_gbe_rx_ring *rx_ring) 1802 { 1803 struct pci_dev *pdev = adapter->pdev; 1804 1805 pch_gbe_clean_rx_ring(adapter, rx_ring); 1806 vfree(rx_ring->buffer_info); 1807 rx_ring->buffer_info = NULL; 1808 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, 1809 rx_ring->dma); 1810 rx_ring->desc = NULL; 1811 } 1812 1813 /** 1814 * pch_gbe_request_irq - Allocate an interrupt line 1815 * @adapter: Board private structure 1816 * Returns: 1817 * 0: Successfully 1818 * Negative value: Failed 1819 */ 1820 static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter) 1821 { 1822 struct net_device *netdev = adapter->netdev; 1823 int err; 1824 1825 err = pci_alloc_irq_vectors(adapter->pdev, 1, 1, PCI_IRQ_ALL_TYPES); 1826 if (err < 0) 1827 return err; 1828 1829 adapter->irq = pci_irq_vector(adapter->pdev, 0); 1830 1831 err = request_irq(adapter->irq, &pch_gbe_intr, IRQF_SHARED, 1832 netdev->name, netdev); 1833 if (err) 1834 netdev_err(netdev, "Unable to allocate interrupt Error: %d\n", 1835 err); 1836 netdev_dbg(netdev, "have_msi : %d return : 0x%04x\n", 1837 pci_dev_msi_enabled(adapter->pdev), err); 1838 return err; 1839 } 1840 1841 /** 1842 * pch_gbe_up - Up GbE network device 1843 * @adapter: Board private structure 1844 * Returns: 1845 * 0: Successfully 1846 * Negative value: Failed 1847 */ 1848 int pch_gbe_up(struct pch_gbe_adapter *adapter) 1849 { 1850 struct net_device *netdev = adapter->netdev; 1851 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring; 1852 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring; 1853 int err = -EINVAL; 1854 1855 /* Ensure we have a valid MAC */ 1856 if (!is_valid_ether_addr(adapter->hw.mac.addr)) { 1857 netdev_err(netdev, "Error: Invalid MAC address\n"); 1858 goto out; 1859 } 1860 1861 /* hardware has been reset, we need to reload some things */ 1862 pch_gbe_set_multi(netdev); 1863 1864 pch_gbe_setup_tctl(adapter); 1865 pch_gbe_configure_tx(adapter); 1866 pch_gbe_setup_rctl(adapter); 1867 pch_gbe_configure_rx(adapter); 1868 1869 err = pch_gbe_request_irq(adapter); 1870 if (err) { 1871 netdev_err(netdev, 1872 "Error: can't bring device up - irq request failed\n"); 1873 goto out; 1874 } 1875 err = pch_gbe_alloc_rx_buffers_pool(adapter, rx_ring, rx_ring->count); 1876 if (err) { 1877 netdev_err(netdev, 1878 "Error: can't bring device up - alloc rx buffers pool failed\n"); 1879 goto freeirq; 1880 } 1881 pch_gbe_alloc_tx_buffers(adapter, tx_ring); 1882 pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count); 1883 adapter->tx_queue_len = netdev->tx_queue_len; 1884 pch_gbe_enable_dma_rx(&adapter->hw); 1885 pch_gbe_enable_mac_rx(&adapter->hw); 1886 1887 mod_timer(&adapter->watchdog_timer, jiffies); 1888 1889 napi_enable(&adapter->napi); 1890 pch_gbe_irq_enable(adapter); 1891 netif_start_queue(adapter->netdev); 1892 1893 return 0; 1894 1895 freeirq: 1896 pch_gbe_free_irq(adapter); 1897 out: 1898 return err; 1899 } 1900 1901 /** 1902 * pch_gbe_down - Down GbE network device 1903 * @adapter: Board private structure 1904 */ 1905 void pch_gbe_down(struct pch_gbe_adapter *adapter) 1906 { 1907 struct net_device *netdev = adapter->netdev; 1908 struct pci_dev *pdev = adapter->pdev; 1909 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring; 1910 1911 /* signal that we're down so the interrupt handler does not 1912 * reschedule our watchdog timer */ 1913 napi_disable(&adapter->napi); 1914 atomic_set(&adapter->irq_sem, 0); 1915 1916 pch_gbe_irq_disable(adapter); 1917 pch_gbe_free_irq(adapter); 1918 1919 del_timer_sync(&adapter->watchdog_timer); 1920 1921 netdev->tx_queue_len = adapter->tx_queue_len; 1922 netif_carrier_off(netdev); 1923 netif_stop_queue(netdev); 1924 1925 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal)) 1926 pch_gbe_reset(adapter); 1927 pch_gbe_clean_tx_ring(adapter, adapter->tx_ring); 1928 pch_gbe_clean_rx_ring(adapter, adapter->rx_ring); 1929 1930 dma_free_coherent(&adapter->pdev->dev, rx_ring->rx_buff_pool_size, 1931 rx_ring->rx_buff_pool, rx_ring->rx_buff_pool_logic); 1932 rx_ring->rx_buff_pool_logic = 0; 1933 rx_ring->rx_buff_pool_size = 0; 1934 rx_ring->rx_buff_pool = NULL; 1935 } 1936 1937 /** 1938 * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter) 1939 * @adapter: Board private structure to initialize 1940 * Returns: 1941 * 0: Successfully 1942 * Negative value: Failed 1943 */ 1944 static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter) 1945 { 1946 struct pch_gbe_hw *hw = &adapter->hw; 1947 struct net_device *netdev = adapter->netdev; 1948 1949 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048; 1950 hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 1951 hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 1952 hw->phy.reset_delay_us = PCH_GBE_PHY_RESET_DELAY_US; 1953 1954 if (pch_gbe_alloc_queues(adapter)) { 1955 netdev_err(netdev, "Unable to allocate memory for queues\n"); 1956 return -ENOMEM; 1957 } 1958 spin_lock_init(&adapter->hw.miim_lock); 1959 spin_lock_init(&adapter->stats_lock); 1960 spin_lock_init(&adapter->ethtool_lock); 1961 atomic_set(&adapter->irq_sem, 0); 1962 pch_gbe_irq_disable(adapter); 1963 1964 pch_gbe_init_stats(adapter); 1965 1966 netdev_dbg(netdev, 1967 "rx_buffer_len : %d mac.min_frame_size : %d mac.max_frame_size : %d\n", 1968 (u32) adapter->rx_buffer_len, 1969 hw->mac.min_frame_size, hw->mac.max_frame_size); 1970 return 0; 1971 } 1972 1973 /** 1974 * pch_gbe_open - Called when a network interface is made active 1975 * @netdev: Network interface device structure 1976 * Returns: 1977 * 0: Successfully 1978 * Negative value: Failed 1979 */ 1980 static int pch_gbe_open(struct net_device *netdev) 1981 { 1982 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 1983 struct pch_gbe_hw *hw = &adapter->hw; 1984 int err; 1985 1986 /* allocate transmit descriptors */ 1987 err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring); 1988 if (err) 1989 goto err_setup_tx; 1990 /* allocate receive descriptors */ 1991 err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring); 1992 if (err) 1993 goto err_setup_rx; 1994 pch_gbe_phy_power_up(hw); 1995 err = pch_gbe_up(adapter); 1996 if (err) 1997 goto err_up; 1998 netdev_dbg(netdev, "Success End\n"); 1999 return 0; 2000 2001 err_up: 2002 if (!adapter->wake_up_evt) 2003 pch_gbe_phy_power_down(hw); 2004 pch_gbe_free_rx_resources(adapter, adapter->rx_ring); 2005 err_setup_rx: 2006 pch_gbe_free_tx_resources(adapter, adapter->tx_ring); 2007 err_setup_tx: 2008 pch_gbe_reset(adapter); 2009 netdev_err(netdev, "Error End\n"); 2010 return err; 2011 } 2012 2013 /** 2014 * pch_gbe_stop - Disables a network interface 2015 * @netdev: Network interface device structure 2016 * Returns: 2017 * 0: Successfully 2018 */ 2019 static int pch_gbe_stop(struct net_device *netdev) 2020 { 2021 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2022 struct pch_gbe_hw *hw = &adapter->hw; 2023 2024 pch_gbe_down(adapter); 2025 if (!adapter->wake_up_evt) 2026 pch_gbe_phy_power_down(hw); 2027 pch_gbe_free_tx_resources(adapter, adapter->tx_ring); 2028 pch_gbe_free_rx_resources(adapter, adapter->rx_ring); 2029 return 0; 2030 } 2031 2032 /** 2033 * pch_gbe_xmit_frame - Packet transmitting start 2034 * @skb: Socket buffer structure 2035 * @netdev: Network interface device structure 2036 * Returns: 2037 * - NETDEV_TX_OK: Normal end 2038 * - NETDEV_TX_BUSY: Error end 2039 */ 2040 static netdev_tx_t pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 2041 { 2042 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2043 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring; 2044 2045 if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) { 2046 netif_stop_queue(netdev); 2047 netdev_dbg(netdev, 2048 "Return : BUSY next_to use : 0x%08x next_to clean : 0x%08x\n", 2049 tx_ring->next_to_use, tx_ring->next_to_clean); 2050 return NETDEV_TX_BUSY; 2051 } 2052 2053 /* CRC,ITAG no support */ 2054 pch_gbe_tx_queue(adapter, tx_ring, skb); 2055 return NETDEV_TX_OK; 2056 } 2057 2058 /** 2059 * pch_gbe_set_multi - Multicast and Promiscuous mode set 2060 * @netdev: Network interface device structure 2061 */ 2062 static void pch_gbe_set_multi(struct net_device *netdev) 2063 { 2064 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2065 struct pch_gbe_hw *hw = &adapter->hw; 2066 struct netdev_hw_addr *ha; 2067 u32 rctl, adrmask; 2068 int mc_count, i; 2069 2070 netdev_dbg(netdev, "netdev->flags : 0x%08x\n", netdev->flags); 2071 2072 /* By default enable address & multicast filtering */ 2073 rctl = ioread32(&hw->reg->RX_MODE); 2074 rctl |= PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN; 2075 2076 /* Promiscuous mode disables all hardware address filtering */ 2077 if (netdev->flags & IFF_PROMISC) 2078 rctl &= ~(PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN); 2079 2080 /* If we want to monitor more multicast addresses than the hardware can 2081 * support then disable hardware multicast filtering. 2082 */ 2083 mc_count = netdev_mc_count(netdev); 2084 if ((netdev->flags & IFF_ALLMULTI) || mc_count >= PCH_GBE_MAR_ENTRIES) 2085 rctl &= ~PCH_GBE_MLT_FIL_EN; 2086 2087 iowrite32(rctl, &hw->reg->RX_MODE); 2088 2089 /* If we're not using multicast filtering then there's no point 2090 * configuring the unused MAC address registers. 2091 */ 2092 if (!(rctl & PCH_GBE_MLT_FIL_EN)) 2093 return; 2094 2095 /* Load the first set of multicast addresses into MAC address registers 2096 * for use by hardware filtering. 2097 */ 2098 i = 1; 2099 netdev_for_each_mc_addr(ha, netdev) 2100 pch_gbe_mac_mar_set(hw, ha->addr, i++); 2101 2102 /* If there are spare MAC registers, mask & clear them */ 2103 for (; i < PCH_GBE_MAR_ENTRIES; i++) { 2104 /* Clear MAC address mask */ 2105 adrmask = ioread32(&hw->reg->ADDR_MASK); 2106 iowrite32(adrmask | BIT(i), &hw->reg->ADDR_MASK); 2107 /* wait busy */ 2108 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); 2109 /* Clear MAC address */ 2110 iowrite32(0, &hw->reg->mac_adr[i].high); 2111 iowrite32(0, &hw->reg->mac_adr[i].low); 2112 } 2113 2114 netdev_dbg(netdev, 2115 "RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x netdev->mc_count : 0x%08x\n", 2116 ioread32(&hw->reg->RX_MODE), mc_count); 2117 } 2118 2119 /** 2120 * pch_gbe_set_mac - Change the Ethernet Address of the NIC 2121 * @netdev: Network interface device structure 2122 * @addr: Pointer to an address structure 2123 * Returns: 2124 * 0: Successfully 2125 * -EADDRNOTAVAIL: Failed 2126 */ 2127 static int pch_gbe_set_mac(struct net_device *netdev, void *addr) 2128 { 2129 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2130 struct sockaddr *skaddr = addr; 2131 int ret_val; 2132 2133 if (!is_valid_ether_addr(skaddr->sa_data)) { 2134 ret_val = -EADDRNOTAVAIL; 2135 } else { 2136 eth_hw_addr_set(netdev, skaddr->sa_data); 2137 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len); 2138 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0); 2139 ret_val = 0; 2140 } 2141 netdev_dbg(netdev, "ret_val : 0x%08x\n", ret_val); 2142 netdev_dbg(netdev, "dev_addr : %pM\n", netdev->dev_addr); 2143 netdev_dbg(netdev, "mac_addr : %pM\n", adapter->hw.mac.addr); 2144 netdev_dbg(netdev, "MAC_ADR1AB reg : 0x%08x 0x%08x\n", 2145 ioread32(&adapter->hw.reg->mac_adr[0].high), 2146 ioread32(&adapter->hw.reg->mac_adr[0].low)); 2147 return ret_val; 2148 } 2149 2150 /** 2151 * pch_gbe_change_mtu - Change the Maximum Transfer Unit 2152 * @netdev: Network interface device structure 2153 * @new_mtu: New value for maximum frame size 2154 * Returns: 2155 * 0: Successfully 2156 * -EINVAL: Failed 2157 */ 2158 static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu) 2159 { 2160 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2161 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; 2162 unsigned long old_rx_buffer_len = adapter->rx_buffer_len; 2163 int err; 2164 2165 if (max_frame <= PCH_GBE_FRAME_SIZE_2048) 2166 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048; 2167 else if (max_frame <= PCH_GBE_FRAME_SIZE_4096) 2168 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096; 2169 else if (max_frame <= PCH_GBE_FRAME_SIZE_8192) 2170 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192; 2171 else 2172 adapter->rx_buffer_len = PCH_GBE_MAX_RX_BUFFER_SIZE; 2173 2174 if (netif_running(netdev)) { 2175 pch_gbe_down(adapter); 2176 err = pch_gbe_up(adapter); 2177 if (err) { 2178 adapter->rx_buffer_len = old_rx_buffer_len; 2179 pch_gbe_up(adapter); 2180 return err; 2181 } else { 2182 netdev->mtu = new_mtu; 2183 adapter->hw.mac.max_frame_size = max_frame; 2184 } 2185 } else { 2186 pch_gbe_reset(adapter); 2187 WRITE_ONCE(netdev->mtu, new_mtu); 2188 adapter->hw.mac.max_frame_size = max_frame; 2189 } 2190 2191 netdev_dbg(netdev, 2192 "max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n", 2193 max_frame, (u32) adapter->rx_buffer_len, netdev->mtu, 2194 adapter->hw.mac.max_frame_size); 2195 return 0; 2196 } 2197 2198 /** 2199 * pch_gbe_set_features - Reset device after features changed 2200 * @netdev: Network interface device structure 2201 * @features: New features 2202 * Returns: 2203 * 0: HW state updated successfully 2204 */ 2205 static int pch_gbe_set_features(struct net_device *netdev, 2206 netdev_features_t features) 2207 { 2208 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2209 netdev_features_t changed = features ^ netdev->features; 2210 2211 if (!(changed & NETIF_F_RXCSUM)) 2212 return 0; 2213 2214 if (netif_running(netdev)) 2215 pch_gbe_reinit_locked(adapter); 2216 else 2217 pch_gbe_reset(adapter); 2218 2219 return 0; 2220 } 2221 2222 /** 2223 * pch_gbe_ioctl - Controls register through a MII interface 2224 * @netdev: Network interface device structure 2225 * @ifr: Pointer to ifr structure 2226 * @cmd: Control command 2227 * Returns: 2228 * 0: Successfully 2229 * Negative value: Failed 2230 */ 2231 static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 2232 { 2233 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2234 2235 netdev_dbg(netdev, "cmd : 0x%04x\n", cmd); 2236 2237 if (cmd == SIOCSHWTSTAMP) 2238 return hwtstamp_ioctl(netdev, ifr, cmd); 2239 2240 return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL); 2241 } 2242 2243 /** 2244 * pch_gbe_tx_timeout - Respond to a Tx Hang 2245 * @netdev: Network interface device structure 2246 * @txqueue: index of hanging queue 2247 */ 2248 static void pch_gbe_tx_timeout(struct net_device *netdev, unsigned int txqueue) 2249 { 2250 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2251 2252 /* Do the reset outside of interrupt context */ 2253 adapter->stats.tx_timeout_count++; 2254 schedule_work(&adapter->reset_task); 2255 } 2256 2257 /** 2258 * pch_gbe_napi_poll - NAPI receive and transfer polling callback 2259 * @napi: Pointer of polling device struct 2260 * @budget: The maximum number of a packet 2261 * Returns: 2262 * false: Exit the polling mode 2263 * true: Continue the polling mode 2264 */ 2265 static int pch_gbe_napi_poll(struct napi_struct *napi, int budget) 2266 { 2267 struct pch_gbe_adapter *adapter = 2268 container_of(napi, struct pch_gbe_adapter, napi); 2269 int work_done = 0; 2270 bool poll_end_flag = false; 2271 bool cleaned = false; 2272 2273 netdev_dbg(adapter->netdev, "budget : %d\n", budget); 2274 2275 pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget); 2276 cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring); 2277 2278 if (cleaned) 2279 work_done = budget; 2280 /* If no Tx and not enough Rx work done, 2281 * exit the polling mode 2282 */ 2283 if (work_done < budget) 2284 poll_end_flag = true; 2285 2286 if (poll_end_flag) { 2287 napi_complete_done(napi, work_done); 2288 pch_gbe_irq_enable(adapter); 2289 } 2290 2291 if (adapter->rx_stop_flag) { 2292 adapter->rx_stop_flag = false; 2293 pch_gbe_enable_dma_rx(&adapter->hw); 2294 } 2295 2296 netdev_dbg(adapter->netdev, 2297 "poll_end_flag : %d work_done : %d budget : %d\n", 2298 poll_end_flag, work_done, budget); 2299 2300 return work_done; 2301 } 2302 2303 #ifdef CONFIG_NET_POLL_CONTROLLER 2304 /** 2305 * pch_gbe_netpoll - Used by things like netconsole to send skbs 2306 * @netdev: Network interface device structure 2307 */ 2308 static void pch_gbe_netpoll(struct net_device *netdev) 2309 { 2310 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2311 2312 disable_irq(adapter->irq); 2313 pch_gbe_intr(adapter->irq, netdev); 2314 enable_irq(adapter->irq); 2315 } 2316 #endif 2317 2318 static const struct net_device_ops pch_gbe_netdev_ops = { 2319 .ndo_open = pch_gbe_open, 2320 .ndo_stop = pch_gbe_stop, 2321 .ndo_start_xmit = pch_gbe_xmit_frame, 2322 .ndo_set_mac_address = pch_gbe_set_mac, 2323 .ndo_tx_timeout = pch_gbe_tx_timeout, 2324 .ndo_change_mtu = pch_gbe_change_mtu, 2325 .ndo_set_features = pch_gbe_set_features, 2326 .ndo_eth_ioctl = pch_gbe_ioctl, 2327 .ndo_set_rx_mode = pch_gbe_set_multi, 2328 #ifdef CONFIG_NET_POLL_CONTROLLER 2329 .ndo_poll_controller = pch_gbe_netpoll, 2330 #endif 2331 }; 2332 2333 static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev, 2334 pci_channel_state_t state) 2335 { 2336 struct net_device *netdev = pci_get_drvdata(pdev); 2337 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2338 2339 netif_device_detach(netdev); 2340 if (netif_running(netdev)) 2341 pch_gbe_down(adapter); 2342 pci_disable_device(pdev); 2343 /* Request a slot slot reset. */ 2344 return PCI_ERS_RESULT_NEED_RESET; 2345 } 2346 2347 static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev) 2348 { 2349 struct net_device *netdev = pci_get_drvdata(pdev); 2350 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2351 struct pch_gbe_hw *hw = &adapter->hw; 2352 2353 if (pci_enable_device(pdev)) { 2354 netdev_err(netdev, "Cannot re-enable PCI device after reset\n"); 2355 return PCI_ERS_RESULT_DISCONNECT; 2356 } 2357 pci_set_master(pdev); 2358 pci_enable_wake(pdev, PCI_D0, 0); 2359 pch_gbe_phy_power_up(hw); 2360 pch_gbe_reset(adapter); 2361 /* Clear wake up status */ 2362 pch_gbe_mac_set_wol_event(hw, 0); 2363 2364 return PCI_ERS_RESULT_RECOVERED; 2365 } 2366 2367 static void pch_gbe_io_resume(struct pci_dev *pdev) 2368 { 2369 struct net_device *netdev = pci_get_drvdata(pdev); 2370 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2371 2372 if (netif_running(netdev)) { 2373 if (pch_gbe_up(adapter)) { 2374 netdev_dbg(netdev, 2375 "can't bring device back up after reset\n"); 2376 return; 2377 } 2378 } 2379 netif_device_attach(netdev); 2380 } 2381 2382 static int __pch_gbe_suspend(struct pci_dev *pdev) 2383 { 2384 struct net_device *netdev = pci_get_drvdata(pdev); 2385 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2386 struct pch_gbe_hw *hw = &adapter->hw; 2387 u32 wufc = adapter->wake_up_evt; 2388 2389 netif_device_detach(netdev); 2390 if (netif_running(netdev)) 2391 pch_gbe_down(adapter); 2392 if (wufc) { 2393 pch_gbe_set_multi(netdev); 2394 pch_gbe_setup_rctl(adapter); 2395 pch_gbe_configure_rx(adapter); 2396 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed, 2397 hw->mac.link_duplex); 2398 pch_gbe_set_mode(adapter, hw->mac.link_speed, 2399 hw->mac.link_duplex); 2400 pch_gbe_mac_set_wol_event(hw, wufc); 2401 pci_disable_device(pdev); 2402 } else { 2403 pch_gbe_phy_power_down(hw); 2404 pch_gbe_mac_set_wol_event(hw, wufc); 2405 pci_disable_device(pdev); 2406 } 2407 return 0; 2408 } 2409 2410 #ifdef CONFIG_PM 2411 static int pch_gbe_suspend(struct device *device) 2412 { 2413 struct pci_dev *pdev = to_pci_dev(device); 2414 2415 return __pch_gbe_suspend(pdev); 2416 } 2417 2418 static int pch_gbe_resume(struct device *device) 2419 { 2420 struct pci_dev *pdev = to_pci_dev(device); 2421 struct net_device *netdev = pci_get_drvdata(pdev); 2422 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2423 struct pch_gbe_hw *hw = &adapter->hw; 2424 u32 err; 2425 2426 err = pci_enable_device(pdev); 2427 if (err) { 2428 netdev_err(netdev, "Cannot enable PCI device from suspend\n"); 2429 return err; 2430 } 2431 pci_set_master(pdev); 2432 pch_gbe_phy_power_up(hw); 2433 pch_gbe_reset(adapter); 2434 /* Clear wake on lan control and status */ 2435 pch_gbe_mac_set_wol_event(hw, 0); 2436 2437 if (netif_running(netdev)) 2438 pch_gbe_up(adapter); 2439 netif_device_attach(netdev); 2440 2441 return 0; 2442 } 2443 #endif /* CONFIG_PM */ 2444 2445 static void pch_gbe_shutdown(struct pci_dev *pdev) 2446 { 2447 __pch_gbe_suspend(pdev); 2448 if (system_state == SYSTEM_POWER_OFF) { 2449 pci_wake_from_d3(pdev, true); 2450 pci_set_power_state(pdev, PCI_D3hot); 2451 } 2452 } 2453 2454 static void pch_gbe_remove(struct pci_dev *pdev) 2455 { 2456 struct net_device *netdev = pci_get_drvdata(pdev); 2457 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2458 2459 cancel_work_sync(&adapter->reset_task); 2460 unregister_netdev(netdev); 2461 2462 pch_gbe_phy_hw_reset(&adapter->hw); 2463 pci_dev_put(adapter->ptp_pdev); 2464 2465 free_netdev(netdev); 2466 } 2467 2468 static int pch_gbe_probe(struct pci_dev *pdev, 2469 const struct pci_device_id *pci_id) 2470 { 2471 struct net_device *netdev; 2472 struct pch_gbe_adapter *adapter; 2473 int ret; 2474 2475 ret = pcim_enable_device(pdev); 2476 if (ret) 2477 return ret; 2478 2479 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 2480 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2481 if (ret) { 2482 dev_err(&pdev->dev, "ERR: No usable DMA configuration, aborting\n"); 2483 return ret; 2484 } 2485 } 2486 2487 ret = pcim_iomap_regions(pdev, 1 << PCH_GBE_PCI_BAR, pci_name(pdev)); 2488 if (ret) { 2489 dev_err(&pdev->dev, 2490 "ERR: Can't reserve PCI I/O and memory resources\n"); 2491 return ret; 2492 } 2493 pci_set_master(pdev); 2494 2495 netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter)); 2496 if (!netdev) 2497 return -ENOMEM; 2498 SET_NETDEV_DEV(netdev, &pdev->dev); 2499 2500 pci_set_drvdata(pdev, netdev); 2501 adapter = netdev_priv(netdev); 2502 adapter->netdev = netdev; 2503 adapter->pdev = pdev; 2504 adapter->hw.back = adapter; 2505 adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR]; 2506 2507 adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data; 2508 if (adapter->pdata && adapter->pdata->platform_init) { 2509 ret = adapter->pdata->platform_init(pdev); 2510 if (ret) 2511 goto err_free_netdev; 2512 } 2513 2514 adapter->ptp_pdev = 2515 pci_get_domain_bus_and_slot(pci_domain_nr(adapter->pdev->bus), 2516 adapter->pdev->bus->number, 2517 PCI_DEVFN(12, 4)); 2518 2519 netdev->netdev_ops = &pch_gbe_netdev_ops; 2520 netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD; 2521 netif_napi_add(netdev, &adapter->napi, pch_gbe_napi_poll); 2522 netdev->hw_features = NETIF_F_RXCSUM | 2523 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2524 netdev->features = netdev->hw_features; 2525 pch_gbe_set_ethtool_ops(netdev); 2526 2527 /* MTU range: 46 - 10300 */ 2528 netdev->min_mtu = ETH_ZLEN - ETH_HLEN; 2529 netdev->max_mtu = PCH_GBE_MAX_JUMBO_FRAME_SIZE - 2530 (ETH_HLEN + ETH_FCS_LEN); 2531 2532 pch_gbe_mac_load_mac_addr(&adapter->hw); 2533 pch_gbe_mac_reset_hw(&adapter->hw); 2534 2535 /* setup the private structure */ 2536 ret = pch_gbe_sw_init(adapter); 2537 if (ret) 2538 goto err_put_dev; 2539 2540 /* Initialize PHY */ 2541 ret = pch_gbe_init_phy(adapter); 2542 if (ret) { 2543 dev_err(&pdev->dev, "PHY initialize error\n"); 2544 goto err_free_adapter; 2545 } 2546 2547 /* Read the MAC address. and store to the private data */ 2548 ret = pch_gbe_mac_read_mac_addr(&adapter->hw); 2549 if (ret) { 2550 dev_err(&pdev->dev, "MAC address Read Error\n"); 2551 goto err_free_adapter; 2552 } 2553 2554 eth_hw_addr_set(netdev, adapter->hw.mac.addr); 2555 if (!is_valid_ether_addr(netdev->dev_addr)) { 2556 /* 2557 * If the MAC is invalid (or just missing), display a warning 2558 * but do not abort setting up the device. pch_gbe_up will 2559 * prevent the interface from being brought up until a valid MAC 2560 * is set. 2561 */ 2562 dev_err(&pdev->dev, "Invalid MAC address, " 2563 "interface disabled.\n"); 2564 } 2565 timer_setup(&adapter->watchdog_timer, pch_gbe_watchdog, 0); 2566 2567 INIT_WORK(&adapter->reset_task, pch_gbe_reset_task); 2568 2569 pch_gbe_check_options(adapter); 2570 2571 /* initialize the wol settings based on the eeprom settings */ 2572 adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING; 2573 dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr); 2574 2575 /* reset the hardware with the new settings */ 2576 pch_gbe_reset(adapter); 2577 2578 ret = register_netdev(netdev); 2579 if (ret) 2580 goto err_free_adapter; 2581 /* tell the stack to leave us alone until pch_gbe_open() is called */ 2582 netif_carrier_off(netdev); 2583 netif_stop_queue(netdev); 2584 2585 dev_dbg(&pdev->dev, "PCH Network Connection\n"); 2586 2587 /* Disable hibernation on certain platforms */ 2588 if (adapter->pdata && adapter->pdata->phy_disable_hibernate) 2589 pch_gbe_phy_disable_hibernate(&adapter->hw); 2590 2591 device_set_wakeup_enable(&pdev->dev, 1); 2592 return 0; 2593 2594 err_free_adapter: 2595 pch_gbe_phy_hw_reset(&adapter->hw); 2596 err_put_dev: 2597 pci_dev_put(adapter->ptp_pdev); 2598 err_free_netdev: 2599 free_netdev(netdev); 2600 return ret; 2601 } 2602 2603 static void pch_gbe_gpio_remove_table(void *table) 2604 { 2605 gpiod_remove_lookup_table(table); 2606 } 2607 2608 static int pch_gbe_gpio_add_table(struct device *dev, void *table) 2609 { 2610 gpiod_add_lookup_table(table); 2611 return devm_add_action_or_reset(dev, pch_gbe_gpio_remove_table, table); 2612 } 2613 2614 static struct gpiod_lookup_table pch_gbe_minnow_gpio_table = { 2615 .dev_id = "0000:02:00.1", 2616 .table = { 2617 GPIO_LOOKUP("sch_gpio.33158", 13, NULL, GPIO_ACTIVE_LOW), 2618 {} 2619 }, 2620 }; 2621 2622 /* The AR803X PHY on the MinnowBoard requires a physical pin to be toggled to 2623 * ensure it is awake for probe and init. Request the line and reset the PHY. 2624 */ 2625 static int pch_gbe_minnow_platform_init(struct pci_dev *pdev) 2626 { 2627 struct gpio_desc *gpiod; 2628 int ret; 2629 2630 ret = pch_gbe_gpio_add_table(&pdev->dev, &pch_gbe_minnow_gpio_table); 2631 if (ret) 2632 return ret; 2633 2634 gpiod = devm_gpiod_get(&pdev->dev, NULL, GPIOD_OUT_HIGH); 2635 if (IS_ERR(gpiod)) 2636 return dev_err_probe(&pdev->dev, PTR_ERR(gpiod), 2637 "Can't request PHY reset GPIO line\n"); 2638 2639 gpiod_set_value(gpiod, 1); 2640 usleep_range(1250, 1500); 2641 gpiod_set_value(gpiod, 0); 2642 usleep_range(1250, 1500); 2643 2644 return ret; 2645 } 2646 2647 static struct pch_gbe_privdata pch_gbe_minnow_privdata = { 2648 .phy_tx_clk_delay = true, 2649 .phy_disable_hibernate = true, 2650 .platform_init = pch_gbe_minnow_platform_init, 2651 }; 2652 2653 static const struct pci_device_id pch_gbe_pcidev_id[] = { 2654 {.vendor = PCI_VENDOR_ID_INTEL, 2655 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE, 2656 .subvendor = PCI_VENDOR_ID_CIRCUITCO, 2657 .subdevice = PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD, 2658 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), 2659 .class_mask = (0xFFFF00), 2660 .driver_data = (kernel_ulong_t)&pch_gbe_minnow_privdata 2661 }, 2662 {.vendor = PCI_VENDOR_ID_INTEL, 2663 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE, 2664 .subvendor = PCI_ANY_ID, 2665 .subdevice = PCI_ANY_ID, 2666 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), 2667 .class_mask = (0xFFFF00) 2668 }, 2669 {.vendor = PCI_VENDOR_ID_ROHM, 2670 .device = PCI_DEVICE_ID_ROHM_ML7223_GBE, 2671 .subvendor = PCI_ANY_ID, 2672 .subdevice = PCI_ANY_ID, 2673 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), 2674 .class_mask = (0xFFFF00) 2675 }, 2676 {.vendor = PCI_VENDOR_ID_ROHM, 2677 .device = PCI_DEVICE_ID_ROHM_ML7831_GBE, 2678 .subvendor = PCI_ANY_ID, 2679 .subdevice = PCI_ANY_ID, 2680 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), 2681 .class_mask = (0xFFFF00) 2682 }, 2683 /* required last entry */ 2684 {0} 2685 }; 2686 2687 #ifdef CONFIG_PM 2688 static const struct dev_pm_ops pch_gbe_pm_ops = { 2689 .suspend = pch_gbe_suspend, 2690 .resume = pch_gbe_resume, 2691 .freeze = pch_gbe_suspend, 2692 .thaw = pch_gbe_resume, 2693 .poweroff = pch_gbe_suspend, 2694 .restore = pch_gbe_resume, 2695 }; 2696 #endif 2697 2698 static const struct pci_error_handlers pch_gbe_err_handler = { 2699 .error_detected = pch_gbe_io_error_detected, 2700 .slot_reset = pch_gbe_io_slot_reset, 2701 .resume = pch_gbe_io_resume 2702 }; 2703 2704 static struct pci_driver pch_gbe_driver = { 2705 .name = KBUILD_MODNAME, 2706 .id_table = pch_gbe_pcidev_id, 2707 .probe = pch_gbe_probe, 2708 .remove = pch_gbe_remove, 2709 #ifdef CONFIG_PM 2710 .driver.pm = &pch_gbe_pm_ops, 2711 #endif 2712 .shutdown = pch_gbe_shutdown, 2713 .err_handler = &pch_gbe_err_handler 2714 }; 2715 module_pci_driver(pch_gbe_driver); 2716 2717 MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver"); 2718 MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>"); 2719 MODULE_LICENSE("GPL"); 2720 MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id); 2721 2722 /* pch_gbe_main.c */ 2723