1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * OPEN Alliance 10BASE‑T1x MAC‑PHY Serial Interface framework 4 * 5 * Author: Parthiban Veerasooran <parthiban.veerasooran@microchip.com> 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/iopoll.h> 10 #include <linux/interrupt.h> 11 #include <linux/mdio.h> 12 #include <linux/phy.h> 13 #include <linux/oa_tc6.h> 14 15 /* Control command header */ 16 #define OA_TC6_CTRL_HEADER_DATA_NOT_CTRL BIT(31) 17 #define OA_TC6_CTRL_HEADER_WRITE_NOT_READ BIT(29) 18 #define OA_TC6_CTRL_HEADER_MEM_MAP_SELECTOR GENMASK(27, 24) 19 #define OA_TC6_CTRL_HEADER_ADDR GENMASK(23, 8) 20 #define OA_TC6_CTRL_HEADER_LENGTH GENMASK(7, 1) 21 #define OA_TC6_CTRL_HEADER_PARITY BIT(0) 22 23 /* Data header */ 24 #define OA_TC6_DATA_HEADER_DATA_NOT_CTRL BIT(31) 25 #define OA_TC6_DATA_HEADER_DATA_VALID BIT(21) 26 #define OA_TC6_DATA_HEADER_START_VALID BIT(20) 27 #define OA_TC6_DATA_HEADER_START_WORD_OFFSET GENMASK(19, 16) 28 #define OA_TC6_DATA_HEADER_END_VALID BIT(14) 29 #define OA_TC6_DATA_HEADER_END_BYTE_OFFSET GENMASK(13, 8) 30 #define OA_TC6_DATA_HEADER_PARITY BIT(0) 31 32 /* Data footer */ 33 #define OA_TC6_DATA_FOOTER_EXTENDED_STS BIT(31) 34 #define OA_TC6_DATA_FOOTER_RXD_HEADER_BAD BIT(30) 35 #define OA_TC6_DATA_FOOTER_CONFIG_SYNC BIT(29) 36 #define OA_TC6_DATA_FOOTER_RX_CHUNKS GENMASK(28, 24) 37 #define OA_TC6_DATA_FOOTER_DATA_VALID BIT(21) 38 #define OA_TC6_DATA_FOOTER_START_VALID BIT(20) 39 #define OA_TC6_DATA_FOOTER_START_WORD_OFFSET GENMASK(19, 16) 40 #define OA_TC6_DATA_FOOTER_END_VALID BIT(14) 41 #define OA_TC6_DATA_FOOTER_END_BYTE_OFFSET GENMASK(13, 8) 42 #define OA_TC6_DATA_FOOTER_TX_CREDITS GENMASK(5, 1) 43 44 #define OA_TC6_CTRL_PROT_REPLY_SIZE 4 45 #define OA_TC6_CTRL_HEADER_SIZE 4 46 #define OA_TC6_CTRL_REG_VALUE_SIZE 4 47 #define OA_TC6_CTRL_IGNORED_SIZE 4 48 #define OA_TC6_CTRL_MAX_REGISTERS 128 49 #define OA_TC6_CTRL_SPI_BUF_SIZE (OA_TC6_CTRL_HEADER_SIZE +\ 50 (OA_TC6_CTRL_MAX_REGISTERS *\ 51 (OA_TC6_CTRL_REG_VALUE_SIZE +\ 52 OA_TC6_CTRL_PROT_REPLY_SIZE)) +\ 53 OA_TC6_CTRL_IGNORED_SIZE) 54 55 #define OA_TC6_CHUNK_PAYLOAD_SIZE 64 56 #define OA_TC6_DATA_HEADER_SIZE 4 57 #define OA_TC6_CHUNK_SIZE (OA_TC6_DATA_HEADER_SIZE +\ 58 OA_TC6_CHUNK_PAYLOAD_SIZE) 59 #define OA_TC6_MAX_TX_CHUNKS 48 60 #define OA_TC6_SPI_DATA_BUF_SIZE (OA_TC6_MAX_TX_CHUNKS *\ 61 OA_TC6_CHUNK_SIZE) 62 #define STATUS0_RESETC_POLL_DELAY 1000 63 #define STATUS0_RESETC_POLL_TIMEOUT 1000000 64 65 #define OA_TC6_REG_MMS_MASK GENMASK(19, 16) 66 67 /* Internal structure for MAC-PHY drivers */ 68 struct oa_tc6 { 69 struct net_device *netdev; 70 struct phy_device *phydev; 71 struct mii_bus *mdiobus; 72 struct spi_device *spi; 73 struct mutex spi_ctrl_lock; /* Protects spi control transfer */ 74 spinlock_t tx_skb_lock; /* Protects tx skb handling */ 75 void *spi_ctrl_tx_buf; 76 void *spi_ctrl_rx_buf; 77 void *spi_data_tx_buf; 78 void *spi_data_rx_buf; 79 struct sk_buff *ongoing_tx_skb; 80 struct sk_buff *waiting_tx_skb; 81 struct sk_buff *rx_skb; 82 u16 tx_skb_offset; 83 u16 spi_data_tx_buf_offset; 84 u16 tx_credits; 85 u8 rx_chunks_available; 86 bool rx_buf_overflow; 87 bool int_flag; 88 bool disable_traffic; 89 bool prot_ctrl; 90 enum oa_tc6_quirk_flag quirk_flags; 91 }; 92 93 enum oa_tc6_header_type { 94 OA_TC6_CTRL_HEADER, 95 OA_TC6_DATA_HEADER, 96 }; 97 98 enum oa_tc6_register_op { 99 OA_TC6_CTRL_REG_READ = 0, 100 OA_TC6_CTRL_REG_WRITE = 1, 101 }; 102 103 enum oa_tc6_data_valid_info { 104 OA_TC6_DATA_INVALID, 105 OA_TC6_DATA_VALID, 106 }; 107 108 enum oa_tc6_data_start_valid_info { 109 OA_TC6_DATA_START_INVALID, 110 OA_TC6_DATA_START_VALID, 111 }; 112 113 enum oa_tc6_data_end_valid_info { 114 OA_TC6_DATA_END_INVALID, 115 OA_TC6_DATA_END_VALID, 116 }; 117 118 static int oa_tc6_spi_transfer(struct oa_tc6 *tc6, 119 enum oa_tc6_header_type header_type, u16 length) 120 { 121 struct spi_transfer xfer = { 0 }; 122 struct spi_message msg; 123 124 if (header_type == OA_TC6_DATA_HEADER) { 125 xfer.tx_buf = tc6->spi_data_tx_buf; 126 xfer.rx_buf = tc6->spi_data_rx_buf; 127 } else { 128 xfer.tx_buf = tc6->spi_ctrl_tx_buf; 129 xfer.rx_buf = tc6->spi_ctrl_rx_buf; 130 } 131 xfer.len = length; 132 133 spi_message_init(&msg); 134 spi_message_add_tail(&xfer, &msg); 135 136 return spi_sync(tc6->spi, &msg); 137 } 138 139 static int oa_tc6_get_parity(u32 p) 140 { 141 /* Public domain code snippet, lifted from 142 * http://www-graphics.stanford.edu/~seander/bithacks.html 143 */ 144 p ^= p >> 1; 145 p ^= p >> 2; 146 p = (p & 0x11111111U) * 0x11111111U; 147 148 /* Odd parity is used here */ 149 return !((p >> 28) & 1); 150 } 151 152 static __be32 oa_tc6_prepare_ctrl_header(u32 addr, u8 length, 153 enum oa_tc6_register_op reg_op) 154 { 155 u32 header; 156 157 header = FIELD_PREP(OA_TC6_CTRL_HEADER_DATA_NOT_CTRL, 158 OA_TC6_CTRL_HEADER) | 159 FIELD_PREP(OA_TC6_CTRL_HEADER_WRITE_NOT_READ, reg_op) | 160 FIELD_PREP(OA_TC6_CTRL_HEADER_MEM_MAP_SELECTOR, addr >> 16) | 161 FIELD_PREP(OA_TC6_CTRL_HEADER_ADDR, addr) | 162 FIELD_PREP(OA_TC6_CTRL_HEADER_LENGTH, length - 1); 163 header |= FIELD_PREP(OA_TC6_CTRL_HEADER_PARITY, 164 oa_tc6_get_parity(header)); 165 166 return cpu_to_be32(header); 167 } 168 169 static void oa_tc6_update_ctrl_write_data(struct oa_tc6 *tc6, u32 value[], 170 u8 length) 171 { 172 __be32 *tx_buf = tc6->spi_ctrl_tx_buf + OA_TC6_CTRL_HEADER_SIZE; 173 174 for (int i = 0; i < length; i++) { 175 *tx_buf++ = cpu_to_be32(value[i]); 176 if (tc6->prot_ctrl) 177 *tx_buf++ = cpu_to_be32(~value[i]); 178 } 179 } 180 181 static u16 oa_tc6_calculate_ctrl_buf_size(u8 length, bool ctrl_prot) 182 { 183 u32 reply_size = OA_TC6_CTRL_REG_VALUE_SIZE; 184 185 if (ctrl_prot) 186 reply_size += OA_TC6_CTRL_PROT_REPLY_SIZE; 187 188 /* Control command consists 4 bytes header + 4 bytes register value for 189 * each register (+ 4 bytes for the register value complement in case 190 * protected mode is used) + 4 bytes ignored value. 191 */ 192 return OA_TC6_CTRL_HEADER_SIZE + reply_size * length + 193 OA_TC6_CTRL_IGNORED_SIZE; 194 } 195 196 static void oa_tc6_prepare_ctrl_spi_buf(struct oa_tc6 *tc6, u32 address, 197 u32 value[], u8 length, 198 enum oa_tc6_register_op reg_op, 199 u16 buf_size) 200 { 201 __be32 *tx_buf = tc6->spi_ctrl_tx_buf; 202 203 memset(tx_buf, 0, buf_size); 204 *tx_buf = oa_tc6_prepare_ctrl_header(address, length, reg_op); 205 206 if (reg_op == OA_TC6_CTRL_REG_WRITE) 207 oa_tc6_update_ctrl_write_data(tc6, value, length); 208 } 209 210 static int oa_tc6_check_ctrl_write_reply(struct oa_tc6 *tc6, u8 size) 211 { 212 u8 *tx_buf = tc6->spi_ctrl_tx_buf; 213 u8 *rx_buf = tc6->spi_ctrl_rx_buf; 214 215 rx_buf += OA_TC6_CTRL_IGNORED_SIZE; 216 217 /* The echoed control write must match with the one that was 218 * transmitted. 219 */ 220 if (memcmp(tx_buf, rx_buf, size - OA_TC6_CTRL_IGNORED_SIZE)) 221 return -EPROTO; 222 223 return 0; 224 } 225 226 static int oa_tc6_check_ctrl_read_reply(struct oa_tc6 *tc6, u8 length) 227 { 228 __be32 *rx_buf = tc6->spi_ctrl_rx_buf + OA_TC6_CTRL_IGNORED_SIZE; 229 __be32 *tx_buf = tc6->spi_ctrl_tx_buf; 230 u32 complement; 231 u32 reply; 232 233 /* The echoed control read header must match with the one that was 234 * transmitted. 235 */ 236 if (*tx_buf != *rx_buf) 237 return -EPROTO; 238 239 if (tc6->prot_ctrl) { 240 /* Skip past the echoed header to the value/complement pairs */ 241 rx_buf += 1; 242 for (int i = 0; i < length; i++) { 243 reply = be32_to_cpu(rx_buf[0]); 244 complement = be32_to_cpu(rx_buf[1]); 245 246 if (complement != ~reply) 247 return -EPROTO; 248 249 rx_buf += 2; 250 } 251 } 252 253 return 0; 254 } 255 256 static void oa_tc6_copy_ctrl_read_data(struct oa_tc6 *tc6, u32 value[], 257 u8 length) 258 { 259 __be32 *rx_buf = tc6->spi_ctrl_rx_buf + OA_TC6_CTRL_IGNORED_SIZE + 260 OA_TC6_CTRL_HEADER_SIZE; 261 262 for (int i = 0; i < length; i++) { 263 value[i] = be32_to_cpu(*rx_buf++); 264 265 /* skip complement word */ 266 if (tc6->prot_ctrl) 267 rx_buf++; 268 } 269 } 270 271 static int oa_tc6_perform_ctrl(struct oa_tc6 *tc6, u32 address, u32 value[], 272 u8 length, enum oa_tc6_register_op reg_op) 273 { 274 u16 size; 275 int ret; 276 277 size = oa_tc6_calculate_ctrl_buf_size(length, tc6->prot_ctrl); 278 279 /* Prepare control command and copy to SPI control buffer */ 280 oa_tc6_prepare_ctrl_spi_buf(tc6, address, value, length, reg_op, size); 281 282 /* Perform SPI transfer */ 283 ret = oa_tc6_spi_transfer(tc6, OA_TC6_CTRL_HEADER, size); 284 if (ret) { 285 dev_err(&tc6->spi->dev, "SPI transfer failed for control: %d\n", 286 ret); 287 return ret; 288 } 289 290 /* Check echoed/received control write command reply for errors */ 291 if (reg_op == OA_TC6_CTRL_REG_WRITE) 292 return oa_tc6_check_ctrl_write_reply(tc6, size); 293 294 /* Check echoed/received control read command reply for errors */ 295 ret = oa_tc6_check_ctrl_read_reply(tc6, length); 296 if (ret) 297 return ret; 298 299 oa_tc6_copy_ctrl_read_data(tc6, value, length); 300 301 return 0; 302 } 303 304 /** 305 * oa_tc6_read_registers - function for reading multiple consecutive registers. 306 * @tc6: oa_tc6 struct. 307 * @address: address of the first register to be read in the MAC-PHY. 308 * @value: values to be read from the starting register address @address. 309 * @length: number of consecutive registers to be read from @address. 310 * 311 * Maximum of 128 consecutive registers can be read starting at @address. 312 * 313 * Return: 0 on success otherwise failed. 314 */ 315 int oa_tc6_read_registers(struct oa_tc6 *tc6, u32 address, u32 value[], 316 u8 length) 317 { 318 int ret; 319 320 if (!length || length > OA_TC6_CTRL_MAX_REGISTERS) { 321 dev_err(&tc6->spi->dev, "Invalid register length parameter\n"); 322 return -EINVAL; 323 } 324 325 mutex_lock(&tc6->spi_ctrl_lock); 326 ret = oa_tc6_perform_ctrl(tc6, address, value, length, 327 OA_TC6_CTRL_REG_READ); 328 mutex_unlock(&tc6->spi_ctrl_lock); 329 330 return ret; 331 } 332 EXPORT_SYMBOL_GPL(oa_tc6_read_registers); 333 334 /** 335 * oa_tc6_read_register - function for reading a MAC-PHY register. 336 * @tc6: oa_tc6 struct. 337 * @address: register address of the MAC-PHY to be read. 338 * @value: value read from the @address register address of the MAC-PHY. 339 * 340 * Return: 0 on success otherwise failed. 341 */ 342 int oa_tc6_read_register(struct oa_tc6 *tc6, u32 address, u32 *value) 343 { 344 return oa_tc6_read_registers(tc6, address, value, 1); 345 } 346 EXPORT_SYMBOL_GPL(oa_tc6_read_register); 347 348 /** 349 * oa_tc6_read_register_mms - function for reading a MAC-PHY register in a 350 * specified memory map. 351 * @tc6: oa_tc6 struct. 352 * @mms: Memory map selector for the register. 353 * @address: register address of the MAC-PHY to be read. 354 * @value: value read from the @address register address of the MAC-PHY. 355 * 356 * Return: 0 on success or a negative error code on failure. 357 */ 358 int oa_tc6_read_register_mms(struct oa_tc6 *tc6, u8 mms, u16 address, 359 u32 *value) 360 { 361 u32 mms_reg; 362 363 mms_reg = FIELD_PREP(OA_TC6_REG_MMS_MASK, mms) | address; 364 365 return oa_tc6_read_registers(tc6, mms_reg, value, 1); 366 } 367 EXPORT_SYMBOL_GPL(oa_tc6_read_register_mms); 368 369 /** 370 * oa_tc6_write_registers - function for writing multiple consecutive registers. 371 * @tc6: oa_tc6 struct. 372 * @address: address of the first register to be written in the MAC-PHY. 373 * @value: values to be written from the starting register address @address. 374 * @length: number of consecutive registers to be written from @address. 375 * 376 * Maximum of 128 consecutive registers can be written starting at @address. 377 * 378 * Return: 0 on success otherwise failed. 379 */ 380 int oa_tc6_write_registers(struct oa_tc6 *tc6, u32 address, u32 value[], 381 u8 length) 382 { 383 int ret; 384 385 if (!length || length > OA_TC6_CTRL_MAX_REGISTERS) { 386 dev_err(&tc6->spi->dev, "Invalid register length parameter\n"); 387 return -EINVAL; 388 } 389 390 mutex_lock(&tc6->spi_ctrl_lock); 391 ret = oa_tc6_perform_ctrl(tc6, address, value, length, 392 OA_TC6_CTRL_REG_WRITE); 393 mutex_unlock(&tc6->spi_ctrl_lock); 394 395 return ret; 396 } 397 EXPORT_SYMBOL_GPL(oa_tc6_write_registers); 398 399 /** 400 * oa_tc6_write_register - function for writing a MAC-PHY register. 401 * @tc6: oa_tc6 struct. 402 * @address: register address of the MAC-PHY to be written. 403 * @value: value to be written in the @address register address of the MAC-PHY. 404 * 405 * Return: 0 on success otherwise failed. 406 */ 407 int oa_tc6_write_register(struct oa_tc6 *tc6, u32 address, u32 value) 408 { 409 return oa_tc6_write_registers(tc6, address, &value, 1); 410 } 411 EXPORT_SYMBOL_GPL(oa_tc6_write_register); 412 413 /** 414 * oa_tc6_write_register_mms - function for writing a MAC-PHY register in a 415 * specified memory map. 416 * @tc6: oa_tc6 struct. 417 * @mms: Memory map selector for the register. 418 * @address: register address of the MAC-PHY to be written. 419 * @value: value to be written in the @address register address of the MAC-PHY. 420 * 421 * Return: 0 on success or a negative error code on failure. 422 */ 423 int oa_tc6_write_register_mms(struct oa_tc6 *tc6, u8 mms, u16 address, 424 u32 value) 425 { 426 u32 mms_reg; 427 428 mms_reg = FIELD_PREP(OA_TC6_REG_MMS_MASK, mms) | address; 429 430 return oa_tc6_write_registers(tc6, mms_reg, &value, 1); 431 } 432 EXPORT_SYMBOL_GPL(oa_tc6_write_register_mms); 433 434 static int oa_tc6_check_phy_reg_direct_access_capability(struct oa_tc6 *tc6) 435 { 436 u32 regval; 437 int ret; 438 439 ret = oa_tc6_read_register(tc6, OA_TC6_REG_STDCAP, ®val); 440 if (ret) 441 return ret; 442 443 if (!(regval & OA_TC6_STDCAP_DIRECT_PHY_REG_ACCESS)) 444 return -ENODEV; 445 446 return 0; 447 } 448 449 static void oa_tc6_handle_link_change(struct net_device *netdev) 450 { 451 phy_print_status(netdev->phydev); 452 } 453 454 static int oa_tc6_mdiobus_read(struct mii_bus *bus, int addr, int regnum) 455 { 456 struct oa_tc6 *tc6 = bus->priv; 457 u32 regval; 458 bool ret; 459 460 ret = oa_tc6_read_register(tc6, OA_TC6_PHY_STD_REG_ADDR_BASE | 461 (regnum & OA_TC6_PHY_STD_REG_ADDR_MASK), 462 ®val); 463 if (ret) 464 return ret; 465 466 return regval; 467 } 468 469 static int oa_tc6_mdiobus_write(struct mii_bus *bus, int addr, int regnum, 470 u16 val) 471 { 472 struct oa_tc6 *tc6 = bus->priv; 473 474 return oa_tc6_write_register(tc6, OA_TC6_PHY_STD_REG_ADDR_BASE | 475 (regnum & OA_TC6_PHY_STD_REG_ADDR_MASK), 476 val); 477 } 478 479 static int oa_tc6_get_phy_c45_mms(int devnum) 480 { 481 switch (devnum) { 482 case MDIO_MMD_PCS: 483 return OA_TC6_PHY_C45_PCS_MMS2; 484 case MDIO_MMD_PMAPMD: 485 return OA_TC6_PHY_C45_PMA_PMD_MMS3; 486 case MDIO_MMD_VEND2: 487 return OA_TC6_PHY_C45_VS_PLCA_MMS4; 488 case MDIO_MMD_AN: 489 return OA_TC6_PHY_C45_AUTO_NEG_MMS5; 490 case MDIO_MMD_POWER_UNIT: 491 return OA_TC6_PHY_C45_POWER_UNIT_MMS6; 492 default: 493 return -EOPNOTSUPP; 494 } 495 } 496 497 int oa_tc6_mdiobus_read_c45(struct mii_bus *bus, int addr, int devnum, 498 int regnum) 499 { 500 struct oa_tc6 *tc6 = bus->priv; 501 u32 regval; 502 int mms; 503 int ret; 504 505 mms = oa_tc6_get_phy_c45_mms(devnum); 506 if (mms < 0) 507 return mms; 508 509 ret = oa_tc6_read_register_mms(tc6, mms, regnum, ®val); 510 if (ret) 511 return ret; 512 513 return regval; 514 } 515 EXPORT_SYMBOL_GPL(oa_tc6_mdiobus_read_c45); 516 517 int oa_tc6_mdiobus_write_c45(struct mii_bus *bus, int addr, int devnum, 518 int regnum, u16 val) 519 { 520 struct oa_tc6 *tc6 = bus->priv; 521 int mms; 522 523 mms = oa_tc6_get_phy_c45_mms(devnum); 524 if (mms < 0) 525 return mms; 526 527 return oa_tc6_write_register_mms(tc6, mms, regnum, val); 528 } 529 EXPORT_SYMBOL_GPL(oa_tc6_mdiobus_write_c45); 530 531 static int oa_tc6_mdiobus_register(struct oa_tc6 *tc6) 532 { 533 int ret; 534 535 tc6->mdiobus = mdiobus_alloc(); 536 if (!tc6->mdiobus) { 537 netdev_err(tc6->netdev, "MDIO bus alloc failed\n"); 538 return -ENOMEM; 539 } 540 541 tc6->mdiobus->priv = tc6; 542 tc6->mdiobus->read = oa_tc6_mdiobus_read; 543 tc6->mdiobus->write = oa_tc6_mdiobus_write; 544 /* OPEN Alliance 10BASE-T1x compliance MAC-PHYs will have both C22 and 545 * C45 registers space. If the PHY is discovered via C22 bus protocol it 546 * assumes it uses C22 protocol and always uses C22 registers indirect 547 * access to access C45 registers. This is because, we don't have a 548 * clean separation between C22/C45 register space and C22/C45 MDIO bus 549 * protocols. Resulting, PHY C45 registers direct access can't be used 550 * which can save multiple SPI bus access. To support this feature, PHY 551 * drivers can set .read_mmd/.write_mmd in the PHY driver to call 552 * .read_c45/.write_c45. Ex: drivers/net/phy/microchip_t1s.c 553 */ 554 tc6->mdiobus->read_c45 = oa_tc6_mdiobus_read_c45; 555 tc6->mdiobus->write_c45 = oa_tc6_mdiobus_write_c45; 556 tc6->mdiobus->name = "oa-tc6-mdiobus"; 557 tc6->mdiobus->parent = &tc6->spi->dev; 558 559 snprintf(tc6->mdiobus->id, ARRAY_SIZE(tc6->mdiobus->id), "%s", 560 dev_name(&tc6->spi->dev)); 561 562 ret = mdiobus_register(tc6->mdiobus); 563 if (ret) { 564 netdev_err(tc6->netdev, "Could not register MDIO bus\n"); 565 mdiobus_free(tc6->mdiobus); 566 return ret; 567 } 568 569 return 0; 570 } 571 572 static void oa_tc6_mdiobus_unregister(struct oa_tc6 *tc6) 573 { 574 mdiobus_unregister(tc6->mdiobus); 575 mdiobus_free(tc6->mdiobus); 576 } 577 578 static int oa_tc6_phy_init(struct oa_tc6 *tc6) 579 { 580 int ret; 581 582 if (tc6->quirk_flags & OA_TC6_BROKEN_PHY) 583 return 0; 584 585 ret = oa_tc6_check_phy_reg_direct_access_capability(tc6); 586 if (ret) { 587 netdev_err(tc6->netdev, 588 "Direct PHY register access is not supported by the MAC-PHY\n"); 589 return ret; 590 } 591 592 ret = oa_tc6_mdiobus_register(tc6); 593 if (ret) 594 return ret; 595 596 tc6->phydev = phy_find_first(tc6->mdiobus); 597 if (!tc6->phydev) { 598 netdev_err(tc6->netdev, "No PHY found\n"); 599 oa_tc6_mdiobus_unregister(tc6); 600 return -ENODEV; 601 } 602 603 tc6->phydev->is_internal = true; 604 ret = phy_connect_direct(tc6->netdev, tc6->phydev, 605 &oa_tc6_handle_link_change, 606 PHY_INTERFACE_MODE_INTERNAL); 607 if (ret) { 608 netdev_err(tc6->netdev, "Can't attach PHY to %s\n", 609 tc6->mdiobus->id); 610 oa_tc6_mdiobus_unregister(tc6); 611 return ret; 612 } 613 614 phy_attached_info(tc6->netdev->phydev); 615 616 return 0; 617 } 618 619 static void oa_tc6_phy_exit(struct oa_tc6 *tc6) 620 { 621 if (tc6->quirk_flags & OA_TC6_BROKEN_PHY) 622 return; 623 624 phy_disconnect(tc6->phydev); 625 oa_tc6_mdiobus_unregister(tc6); 626 } 627 628 static int oa_tc6_read_status0(struct oa_tc6 *tc6) 629 { 630 u32 regval; 631 int ret; 632 633 ret = oa_tc6_read_register(tc6, OA_TC6_REG_STATUS0, ®val); 634 if (ret) { 635 dev_err(&tc6->spi->dev, "STATUS0 register read failed: %d\n", 636 ret); 637 return 0; 638 } 639 640 return regval; 641 } 642 643 static int oa_tc6_sw_reset_macphy(struct oa_tc6 *tc6) 644 { 645 u32 regval = OA_TC6_RESET_SWRESET; 646 int ret; 647 648 ret = oa_tc6_write_register(tc6, OA_TC6_REG_RESET, regval); 649 if (ret) 650 return ret; 651 652 /* Poll for soft reset complete for every 1ms until 1s timeout */ 653 ret = readx_poll_timeout(oa_tc6_read_status0, tc6, regval, 654 regval & OA_TC6_STATUS0_RESETC, 655 STATUS0_RESETC_POLL_DELAY, 656 STATUS0_RESETC_POLL_TIMEOUT); 657 if (ret) 658 return -ENODEV; 659 660 /* Clear the reset complete status */ 661 return oa_tc6_write_register(tc6, OA_TC6_REG_STATUS0, regval); 662 } 663 664 static int oa_tc6_unmask_macphy_error_interrupts(struct oa_tc6 *tc6) 665 { 666 u32 regval; 667 int ret; 668 669 ret = oa_tc6_read_register(tc6, OA_TC6_REG_INT_MASK0, ®val); 670 if (ret) 671 return ret; 672 673 regval &= ~(OA_TC6_INT_MASK0_TX_PROTOCOL_ERR_MASK | 674 OA_TC6_INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK | 675 OA_TC6_INT_MASK0_LOSS_OF_FRAME_ERR_MASK | 676 OA_TC6_INT_MASK0_HEADER_ERR_MASK); 677 678 return oa_tc6_write_register(tc6, OA_TC6_REG_INT_MASK0, regval); 679 } 680 681 static int oa_tc6_enable_data_transfer(struct oa_tc6 *tc6) 682 { 683 u32 value; 684 int ret; 685 686 ret = oa_tc6_read_register(tc6, OA_TC6_REG_CONFIG0, &value); 687 if (ret) 688 return ret; 689 690 /* Enable configuration synchronization for data transfer */ 691 value |= OA_TC6_CONFIG0_SYNC; 692 693 return oa_tc6_write_register(tc6, OA_TC6_REG_CONFIG0, value); 694 } 695 696 static void oa_tc6_cleanup_ongoing_rx_skb(struct oa_tc6 *tc6) 697 { 698 if (tc6->rx_skb) { 699 tc6->netdev->stats.rx_dropped++; 700 kfree_skb(tc6->rx_skb); 701 tc6->rx_skb = NULL; 702 } 703 } 704 705 static void oa_tc6_cleanup_ongoing_tx_skb(struct oa_tc6 *tc6) 706 { 707 if (tc6->ongoing_tx_skb) { 708 tc6->netdev->stats.tx_dropped++; 709 kfree_skb(tc6->ongoing_tx_skb); 710 tc6->ongoing_tx_skb = NULL; 711 } 712 } 713 714 static void oa_tc6_cleanup_waiting_tx_skb(struct oa_tc6 *tc6) 715 { 716 if (tc6->waiting_tx_skb) { 717 tc6->netdev->stats.tx_dropped++; 718 kfree_skb(tc6->waiting_tx_skb); 719 tc6->waiting_tx_skb = NULL; 720 } 721 } 722 723 static void oa_tc6_free_pending_skbs(struct oa_tc6 *tc6) 724 { 725 oa_tc6_cleanup_ongoing_tx_skb(tc6); 726 oa_tc6_cleanup_ongoing_rx_skb(tc6); 727 oa_tc6_cleanup_waiting_tx_skb(tc6); 728 } 729 730 /* If the failure is at SPI interface level, masking and clearing 731 * the interrupt of the device won't work. Since SPI interrupt is 732 * disabled, it should stop the repeated interrupts. 733 */ 734 static void oa_tc6_disable_traffic(struct oa_tc6 *tc6) 735 { 736 u32 regval = OA_TC6_INT_MASK0_ALL_INTERRUPTS; 737 738 tc6->disable_traffic = true; 739 oa_tc6_free_pending_skbs(tc6); 740 oa_tc6_write_register(tc6, OA_TC6_REG_INT_MASK0, regval); 741 oa_tc6_read_register(tc6, OA_TC6_REG_STATUS0, ®val); 742 oa_tc6_write_register(tc6, OA_TC6_REG_STATUS0, regval); 743 dev_err(&tc6->spi->dev, "Device interrupt disabled to avoid interrupt storm"); 744 } 745 746 static int oa_tc6_process_extended_status(struct oa_tc6 *tc6) 747 { 748 u32 value; 749 int ret; 750 751 ret = oa_tc6_read_register(tc6, OA_TC6_REG_STATUS0, &value); 752 if (ret) { 753 netdev_err(tc6->netdev, "STATUS0 register read failed: %d\n", 754 ret); 755 return ret; 756 } 757 758 /* Clear the error interrupts status */ 759 ret = oa_tc6_write_register(tc6, OA_TC6_REG_STATUS0, value); 760 if (ret) { 761 netdev_err(tc6->netdev, "STATUS0 register write failed: %d\n", 762 ret); 763 return ret; 764 } 765 766 if (FIELD_GET(OA_TC6_STATUS0_RX_BUFFER_OVERFLOW_ERROR, value)) { 767 tc6->rx_buf_overflow = true; 768 oa_tc6_cleanup_ongoing_rx_skb(tc6); 769 net_err_ratelimited("%s: Receive buffer overflow error\n", 770 tc6->netdev->name); 771 return -EAGAIN; 772 } 773 if (FIELD_GET(OA_TC6_STATUS0_TX_PROTOCOL_ERROR, value)) { 774 netdev_err(tc6->netdev, "Transmit protocol error\n"); 775 return -ENODEV; 776 } 777 /* TODO: Currently loss of frame and header errors are treated as 778 * non-recoverable errors. They will be handled in the next version. 779 */ 780 if (FIELD_GET(OA_TC6_STATUS0_LOSS_OF_FRAME_ERROR, value)) { 781 netdev_err(tc6->netdev, "Loss of frame error\n"); 782 return -ENODEV; 783 } 784 if (FIELD_GET(OA_TC6_STATUS0_HEADER_ERROR, value)) { 785 netdev_err(tc6->netdev, "Header error\n"); 786 return -ENODEV; 787 } 788 789 return 0; 790 } 791 792 static int oa_tc6_process_rx_chunk_footer(struct oa_tc6 *tc6, u32 footer) 793 { 794 /* Process rx chunk footer for the following, 795 * 1. tx credits 796 * 2. errors if any from MAC-PHY 797 * 3. receive chunks available 798 */ 799 tc6->tx_credits = FIELD_GET(OA_TC6_DATA_FOOTER_TX_CREDITS, footer); 800 tc6->rx_chunks_available = FIELD_GET(OA_TC6_DATA_FOOTER_RX_CHUNKS, 801 footer); 802 803 if (FIELD_GET(OA_TC6_DATA_FOOTER_EXTENDED_STS, footer)) { 804 int ret = oa_tc6_process_extended_status(tc6); 805 806 if (ret) 807 return ret; 808 } 809 810 /* TODO: Currently received header bad and configuration unsync errors 811 * are treated as non-recoverable errors. They will be handled in the 812 * next version. 813 */ 814 if (FIELD_GET(OA_TC6_DATA_FOOTER_RXD_HEADER_BAD, footer)) { 815 netdev_err(tc6->netdev, "Rxd header bad error\n"); 816 return -ENODEV; 817 } 818 819 if (!FIELD_GET(OA_TC6_DATA_FOOTER_CONFIG_SYNC, footer)) { 820 netdev_err(tc6->netdev, "Config unsync error\n"); 821 return -ENODEV; 822 } 823 824 return 0; 825 } 826 827 static void oa_tc6_submit_rx_skb(struct oa_tc6 *tc6) 828 { 829 /* MAC-PHY delivers each frame with its Ethernet FCS attached. 830 * Strip it before handing over to the stack, unless the user 831 * has asked to keep it via NETIF_F_RXFCS. Keeping the FCS 832 * in the frame is harmless for IP traffic, but is parsed as 833 * a (malformed) suffix TLV by PTP, which makes ptp4l reject 834 * every message with "bad message" error. 835 */ 836 if (!(tc6->netdev->features & NETIF_F_RXFCS) && 837 tc6->rx_skb->len > ETH_FCS_LEN) 838 skb_trim(tc6->rx_skb, tc6->rx_skb->len - ETH_FCS_LEN); 839 840 tc6->rx_skb->protocol = eth_type_trans(tc6->rx_skb, tc6->netdev); 841 tc6->netdev->stats.rx_packets++; 842 tc6->netdev->stats.rx_bytes += tc6->rx_skb->len; 843 844 netif_rx(tc6->rx_skb); 845 846 tc6->rx_skb = NULL; 847 } 848 849 static void oa_tc6_update_rx_skb(struct oa_tc6 *tc6, u8 *payload, u8 length) 850 { 851 memcpy(skb_put(tc6->rx_skb, length), payload, length); 852 } 853 854 static int oa_tc6_allocate_rx_skb(struct oa_tc6 *tc6) 855 { 856 tc6->rx_skb = netdev_alloc_skb_ip_align(tc6->netdev, tc6->netdev->mtu + 857 ETH_HLEN + ETH_FCS_LEN); 858 if (!tc6->rx_skb) { 859 tc6->netdev->stats.rx_dropped++; 860 return -ENOMEM; 861 } 862 863 return 0; 864 } 865 866 static int oa_tc6_prcs_complete_rx_frame(struct oa_tc6 *tc6, u8 *payload, 867 u16 size) 868 { 869 int ret; 870 871 ret = oa_tc6_allocate_rx_skb(tc6); 872 if (ret) 873 return ret; 874 875 oa_tc6_update_rx_skb(tc6, payload, size); 876 877 oa_tc6_submit_rx_skb(tc6); 878 879 return 0; 880 } 881 882 static int oa_tc6_prcs_rx_frame_start(struct oa_tc6 *tc6, u8 *payload, u16 size) 883 { 884 int ret; 885 886 ret = oa_tc6_allocate_rx_skb(tc6); 887 if (ret) 888 return ret; 889 890 oa_tc6_update_rx_skb(tc6, payload, size); 891 892 return 0; 893 } 894 895 static void oa_tc6_prcs_rx_frame_end(struct oa_tc6 *tc6, u8 *payload, u16 size) 896 { 897 oa_tc6_update_rx_skb(tc6, payload, size); 898 899 oa_tc6_submit_rx_skb(tc6); 900 } 901 902 static void oa_tc6_prcs_ongoing_rx_frame(struct oa_tc6 *tc6, u8 *payload, 903 u32 footer) 904 { 905 oa_tc6_update_rx_skb(tc6, payload, OA_TC6_CHUNK_PAYLOAD_SIZE); 906 } 907 908 static int oa_tc6_prcs_rx_chunk_payload(struct oa_tc6 *tc6, u8 *data, 909 u32 footer) 910 { 911 u8 start_byte_offset = FIELD_GET(OA_TC6_DATA_FOOTER_START_WORD_OFFSET, 912 footer) * sizeof(u32); 913 u8 end_byte_offset = FIELD_GET(OA_TC6_DATA_FOOTER_END_BYTE_OFFSET, 914 footer); 915 bool start_valid = FIELD_GET(OA_TC6_DATA_FOOTER_START_VALID, footer); 916 bool end_valid = FIELD_GET(OA_TC6_DATA_FOOTER_END_VALID, footer); 917 u16 size; 918 919 /* Restart the new rx frame after receiving rx buffer overflow error */ 920 if (start_valid && tc6->rx_buf_overflow) 921 tc6->rx_buf_overflow = false; 922 923 if (tc6->rx_buf_overflow) 924 return 0; 925 926 /* Process the chunk with complete rx frame */ 927 if (start_valid && end_valid && start_byte_offset < end_byte_offset) { 928 size = end_byte_offset + 1 - start_byte_offset; 929 return oa_tc6_prcs_complete_rx_frame(tc6, 930 &data[start_byte_offset], 931 size); 932 } 933 934 /* Process the chunk with only rx frame start */ 935 if (start_valid && !end_valid) { 936 size = OA_TC6_CHUNK_PAYLOAD_SIZE - start_byte_offset; 937 return oa_tc6_prcs_rx_frame_start(tc6, 938 &data[start_byte_offset], 939 size); 940 } 941 942 /* Process the chunk with only rx frame end */ 943 if (end_valid && !start_valid) { 944 size = end_byte_offset + 1; 945 oa_tc6_prcs_rx_frame_end(tc6, data, size); 946 return 0; 947 } 948 949 /* Process the chunk with previous rx frame end and next rx frame 950 * start. 951 */ 952 if (start_valid && end_valid && start_byte_offset > end_byte_offset) { 953 /* After rx buffer overflow error received, there might be a 954 * possibility of getting an end valid of a previously 955 * incomplete rx frame along with the new rx frame start valid. 956 */ 957 if (tc6->rx_skb) { 958 size = end_byte_offset + 1; 959 oa_tc6_prcs_rx_frame_end(tc6, data, size); 960 } 961 size = OA_TC6_CHUNK_PAYLOAD_SIZE - start_byte_offset; 962 return oa_tc6_prcs_rx_frame_start(tc6, 963 &data[start_byte_offset], 964 size); 965 } 966 967 /* Process the chunk with ongoing rx frame data */ 968 oa_tc6_prcs_ongoing_rx_frame(tc6, data, footer); 969 970 return 0; 971 } 972 973 static u32 oa_tc6_get_rx_chunk_footer(struct oa_tc6 *tc6, u16 footer_offset) 974 { 975 u8 *rx_buf = tc6->spi_data_rx_buf; 976 __be32 footer; 977 978 footer = *((__be32 *)&rx_buf[footer_offset]); 979 980 return be32_to_cpu(footer); 981 } 982 983 static int oa_tc6_process_spi_data_rx_buf(struct oa_tc6 *tc6, u16 length) 984 { 985 u16 no_of_rx_chunks = length / OA_TC6_CHUNK_SIZE; 986 u32 footer; 987 int ret; 988 989 /* All the rx chunks in the receive SPI data buffer are examined here */ 990 for (int i = 0; i < no_of_rx_chunks; i++) { 991 /* Last 4 bytes in each received chunk consist footer info */ 992 footer = oa_tc6_get_rx_chunk_footer(tc6, i * OA_TC6_CHUNK_SIZE + 993 OA_TC6_CHUNK_PAYLOAD_SIZE); 994 995 ret = oa_tc6_process_rx_chunk_footer(tc6, footer); 996 if (ret) 997 return ret; 998 999 /* If there is a data valid chunks then process it for the 1000 * information needed to determine the validity and the location 1001 * of the receive frame data. 1002 */ 1003 if (FIELD_GET(OA_TC6_DATA_FOOTER_DATA_VALID, footer)) { 1004 u8 *payload = tc6->spi_data_rx_buf + i * 1005 OA_TC6_CHUNK_SIZE; 1006 1007 ret = oa_tc6_prcs_rx_chunk_payload(tc6, payload, 1008 footer); 1009 if (ret) 1010 return ret; 1011 } 1012 } 1013 1014 return 0; 1015 } 1016 1017 static __be32 oa_tc6_prepare_data_header(bool data_valid, bool start_valid, 1018 bool end_valid, u8 end_byte_offset) 1019 { 1020 u32 header = FIELD_PREP(OA_TC6_DATA_HEADER_DATA_NOT_CTRL, 1021 OA_TC6_DATA_HEADER) | 1022 FIELD_PREP(OA_TC6_DATA_HEADER_DATA_VALID, data_valid) | 1023 FIELD_PREP(OA_TC6_DATA_HEADER_START_VALID, start_valid) | 1024 FIELD_PREP(OA_TC6_DATA_HEADER_END_VALID, end_valid) | 1025 FIELD_PREP(OA_TC6_DATA_HEADER_END_BYTE_OFFSET, 1026 end_byte_offset); 1027 1028 header |= FIELD_PREP(OA_TC6_DATA_HEADER_PARITY, 1029 oa_tc6_get_parity(header)); 1030 1031 return cpu_to_be32(header); 1032 } 1033 1034 static void oa_tc6_add_tx_skb_to_spi_buf(struct oa_tc6 *tc6) 1035 { 1036 enum oa_tc6_data_end_valid_info end_valid = OA_TC6_DATA_END_INVALID; 1037 __be32 *tx_buf = tc6->spi_data_tx_buf + tc6->spi_data_tx_buf_offset; 1038 u16 remaining_len = tc6->ongoing_tx_skb->len - tc6->tx_skb_offset; 1039 u8 *tx_skb_data = tc6->ongoing_tx_skb->data + tc6->tx_skb_offset; 1040 enum oa_tc6_data_start_valid_info start_valid; 1041 u8 end_byte_offset = 0; 1042 u16 length_to_copy; 1043 1044 /* Initial value is assigned here to avoid more than 80 characters in 1045 * the declaration place. 1046 */ 1047 start_valid = OA_TC6_DATA_START_INVALID; 1048 1049 /* Set start valid if the current tx chunk contains the start of the tx 1050 * ethernet frame. 1051 */ 1052 if (!tc6->tx_skb_offset) 1053 start_valid = OA_TC6_DATA_START_VALID; 1054 1055 /* If the remaining tx skb length is more than the chunk payload size of 1056 * 64 bytes then copy only 64 bytes and leave the ongoing tx skb for 1057 * next tx chunk. 1058 */ 1059 length_to_copy = min_t(u16, remaining_len, OA_TC6_CHUNK_PAYLOAD_SIZE); 1060 1061 /* Copy the tx skb data to the tx chunk payload buffer */ 1062 memcpy(tx_buf + 1, tx_skb_data, length_to_copy); 1063 tc6->tx_skb_offset += length_to_copy; 1064 1065 /* Set end valid if the current tx chunk contains the end of the tx 1066 * ethernet frame. 1067 */ 1068 if (tc6->ongoing_tx_skb->len == tc6->tx_skb_offset) { 1069 end_valid = OA_TC6_DATA_END_VALID; 1070 end_byte_offset = length_to_copy - 1; 1071 tc6->tx_skb_offset = 0; 1072 tc6->netdev->stats.tx_bytes += tc6->ongoing_tx_skb->len; 1073 tc6->netdev->stats.tx_packets++; 1074 kfree_skb(tc6->ongoing_tx_skb); 1075 tc6->ongoing_tx_skb = NULL; 1076 } 1077 1078 *tx_buf = oa_tc6_prepare_data_header(OA_TC6_DATA_VALID, start_valid, 1079 end_valid, end_byte_offset); 1080 tc6->spi_data_tx_buf_offset += OA_TC6_CHUNK_SIZE; 1081 } 1082 1083 static u16 oa_tc6_prepare_spi_tx_buf_for_tx_skbs(struct oa_tc6 *tc6) 1084 { 1085 u16 used_tx_credits; 1086 1087 /* Get tx skbs and convert them into tx chunks based on the tx credits 1088 * available. 1089 */ 1090 for (used_tx_credits = 0; used_tx_credits < tc6->tx_credits; 1091 used_tx_credits++) { 1092 if (!tc6->ongoing_tx_skb) { 1093 spin_lock_bh(&tc6->tx_skb_lock); 1094 tc6->ongoing_tx_skb = tc6->waiting_tx_skb; 1095 tc6->waiting_tx_skb = NULL; 1096 spin_unlock_bh(&tc6->tx_skb_lock); 1097 } 1098 if (!tc6->ongoing_tx_skb) 1099 break; 1100 oa_tc6_add_tx_skb_to_spi_buf(tc6); 1101 } 1102 1103 return used_tx_credits * OA_TC6_CHUNK_SIZE; 1104 } 1105 1106 static void oa_tc6_add_empty_chunks_to_spi_buf(struct oa_tc6 *tc6, 1107 u16 needed_empty_chunks) 1108 { 1109 __be32 header; 1110 1111 header = oa_tc6_prepare_data_header(OA_TC6_DATA_INVALID, 1112 OA_TC6_DATA_START_INVALID, 1113 OA_TC6_DATA_END_INVALID, 0); 1114 1115 while (needed_empty_chunks--) { 1116 __be32 *tx_buf = tc6->spi_data_tx_buf + 1117 tc6->spi_data_tx_buf_offset; 1118 1119 *tx_buf = header; 1120 tc6->spi_data_tx_buf_offset += OA_TC6_CHUNK_SIZE; 1121 } 1122 } 1123 1124 static u16 oa_tc6_prepare_spi_tx_buf_for_rx_chunks(struct oa_tc6 *tc6, u16 len) 1125 { 1126 u16 tx_chunks = len / OA_TC6_CHUNK_SIZE; 1127 u16 needed_empty_chunks; 1128 1129 /* If there are more chunks to receive than to transmit, we need to add 1130 * enough empty tx chunks to allow the reception of the excess rx 1131 * chunks. 1132 */ 1133 if (tx_chunks >= tc6->rx_chunks_available) 1134 return len; 1135 1136 needed_empty_chunks = tc6->rx_chunks_available - tx_chunks; 1137 1138 oa_tc6_add_empty_chunks_to_spi_buf(tc6, needed_empty_chunks); 1139 1140 return needed_empty_chunks * OA_TC6_CHUNK_SIZE + len; 1141 } 1142 1143 static int oa_tc6_try_spi_transfer(struct oa_tc6 *tc6) 1144 { 1145 int ret; 1146 1147 while (true) { 1148 u16 spi_len = 0; 1149 1150 tc6->spi_data_tx_buf_offset = 0; 1151 1152 if (tc6->ongoing_tx_skb || tc6->waiting_tx_skb) 1153 spi_len = oa_tc6_prepare_spi_tx_buf_for_tx_skbs(tc6); 1154 1155 spi_len = oa_tc6_prepare_spi_tx_buf_for_rx_chunks(tc6, spi_len); 1156 1157 if (tc6->int_flag) { 1158 tc6->int_flag = false; 1159 if (spi_len == 0) { 1160 oa_tc6_add_empty_chunks_to_spi_buf(tc6, 1); 1161 spi_len = OA_TC6_CHUNK_SIZE; 1162 } 1163 } 1164 1165 if (spi_len == 0) 1166 break; 1167 1168 ret = oa_tc6_spi_transfer(tc6, OA_TC6_DATA_HEADER, spi_len); 1169 if (ret) { 1170 netdev_err(tc6->netdev, "SPI data transfer failed: %d\n", 1171 ret); 1172 return ret; 1173 } 1174 1175 ret = oa_tc6_process_spi_data_rx_buf(tc6, spi_len); 1176 if (ret) { 1177 if (ret == -EAGAIN) 1178 continue; 1179 1180 oa_tc6_cleanup_ongoing_tx_skb(tc6); 1181 oa_tc6_cleanup_ongoing_rx_skb(tc6); 1182 netdev_err(tc6->netdev, "Device error: %d\n", ret); 1183 return ret; 1184 } 1185 1186 if (!tc6->waiting_tx_skb && netif_queue_stopped(tc6->netdev)) 1187 netif_wake_queue(tc6->netdev); 1188 } 1189 1190 return 0; 1191 } 1192 1193 static irqreturn_t oa_tc6_macphy_threaded_irq(int irq, void *data) 1194 { 1195 struct oa_tc6 *tc6 = data; 1196 int ret = 0; 1197 1198 /* It is possible that interrupt woke the thread before it is 1199 * disabled. Until we come up with good recovery mechanism, 1200 * no need to attempt spi transfer, once it fails. Pending skbs 1201 * are already freed. 1202 */ 1203 if (!tc6->disable_traffic) { 1204 while (tc6->int_flag || 1205 (tc6->waiting_tx_skb && tc6->tx_credits)) { 1206 ret = oa_tc6_try_spi_transfer(tc6); 1207 if (ret) { 1208 disable_irq_nosync(tc6->spi->irq); 1209 oa_tc6_disable_traffic(tc6); 1210 break; 1211 } 1212 } 1213 } 1214 1215 return IRQ_HANDLED; 1216 } 1217 1218 static int oa_tc6_update_buffer_status_from_register(struct oa_tc6 *tc6) 1219 { 1220 u32 value; 1221 int ret; 1222 1223 /* Initially tx credits and rx chunks available to be updated from the 1224 * register as there is no data transfer performed yet. Later they will 1225 * be updated from the rx footer. 1226 */ 1227 ret = oa_tc6_read_register(tc6, OA_TC6_REG_BUFFER_STATUS, &value); 1228 if (ret) 1229 return ret; 1230 1231 tc6->tx_credits = FIELD_GET(OA_TC6_BUFFER_STATUS_TX_CREDITS_AVAILABLE, 1232 value); 1233 tc6->rx_chunks_available = 1234 FIELD_GET(OA_TC6_BUFFER_STATUS_RX_CHUNKS_AVAILABLE, value); 1235 1236 return 0; 1237 } 1238 1239 static irqreturn_t oa_tc6_macphy_isr(int irq, void *data) 1240 { 1241 struct oa_tc6 *tc6 = data; 1242 1243 /* MAC-PHY interrupt can occur for the following reasons. 1244 * - availability of tx credits if it was 0 before and not reported in 1245 * the previous rx footer. 1246 * - availability of rx chunks if it was 0 before and not reported in 1247 * the previous rx footer. 1248 * - extended status event not reported in the previous rx footer. 1249 */ 1250 if (tc6->disable_traffic) 1251 disable_irq_nosync(tc6->spi->irq); 1252 else 1253 tc6->int_flag = true; 1254 /* Wake IRQ thread to perform spi transfer . In case 1255 * disable_traffic is set, threaded irq may run again 1256 * one more time. 1257 */ 1258 return IRQ_WAKE_THREAD; 1259 } 1260 1261 /** 1262 * oa_tc6_zero_align_receive_frame_enable - function to enable zero align 1263 * receive frame feature. 1264 * @tc6: oa_tc6 struct. 1265 * 1266 * Return: 0 on success otherwise failed. 1267 */ 1268 int oa_tc6_zero_align_receive_frame_enable(struct oa_tc6 *tc6) 1269 { 1270 u32 regval; 1271 int ret; 1272 1273 ret = oa_tc6_read_register(tc6, OA_TC6_REG_CONFIG0, ®val); 1274 if (ret) 1275 return ret; 1276 1277 /* Set Zero-Align Receive Frame Enable */ 1278 regval |= OA_TC6_CONFIG0_ZARFE_ENABLE; 1279 1280 return oa_tc6_write_register(tc6, OA_TC6_REG_CONFIG0, regval); 1281 } 1282 EXPORT_SYMBOL_GPL(oa_tc6_zero_align_receive_frame_enable); 1283 1284 /** 1285 * oa_tc6_start_xmit - function for sending the tx skb which consists ethernet 1286 * frame. 1287 * @tc6: oa_tc6 struct. 1288 * @skb: socket buffer in which the ethernet frame is stored. 1289 * 1290 * Return: NETDEV_TX_OK if the transmit ethernet frame skb added in the tx_skb_q 1291 * otherwise returns NETDEV_TX_BUSY. 1292 */ 1293 netdev_tx_t oa_tc6_start_xmit(struct oa_tc6 *tc6, struct sk_buff *skb) 1294 { 1295 if (tc6->disable_traffic || tc6->waiting_tx_skb) { 1296 netif_stop_queue(tc6->netdev); 1297 return NETDEV_TX_BUSY; 1298 } 1299 1300 if (skb_linearize(skb)) { 1301 dev_kfree_skb_any(skb); 1302 tc6->netdev->stats.tx_dropped++; 1303 return NETDEV_TX_OK; 1304 } 1305 1306 spin_lock_bh(&tc6->tx_skb_lock); 1307 tc6->waiting_tx_skb = skb; 1308 spin_unlock_bh(&tc6->tx_skb_lock); 1309 1310 /* Wake the threaded IRQ to perform spi transfer. */ 1311 irq_wake_thread(tc6->spi->irq, tc6); 1312 1313 return NETDEV_TX_OK; 1314 } 1315 EXPORT_SYMBOL_GPL(oa_tc6_start_xmit); 1316 1317 static int oa_tc6_check_ctrl_protection(struct oa_tc6 *tc6) 1318 { 1319 u32 regval; 1320 int ret; 1321 1322 ret = oa_tc6_read_register(tc6, OA_TC6_REG_CONFIG0, ®val); 1323 if (ret) 1324 return ret; 1325 1326 tc6->prot_ctrl = FIELD_GET(OA_TC6_CONFIG0_PROTE, regval); 1327 1328 return 0; 1329 } 1330 1331 /** 1332 * oa_tc6_init - allocates and initializes oa_tc6 structure. 1333 * @spi: device with which data will be exchanged. 1334 * @netdev: network device interface structure. 1335 * @quirks: device specific modifiers for the OA TC6 protocol. 1336 * 1337 * Return: pointer reference to the oa_tc6 structure if the MAC-PHY 1338 * initialization is successful otherwise NULL. 1339 */ 1340 struct oa_tc6 *oa_tc6_init(struct spi_device *spi, struct net_device *netdev, 1341 struct oa_tc6_quirks *quirks) 1342 { 1343 struct oa_tc6 *tc6; 1344 int ret; 1345 1346 tc6 = devm_kzalloc(&spi->dev, sizeof(*tc6), GFP_KERNEL); 1347 if (!tc6) 1348 return NULL; 1349 1350 tc6->spi = spi; 1351 tc6->netdev = netdev; 1352 SET_NETDEV_DEV(netdev, &spi->dev); 1353 mutex_init(&tc6->spi_ctrl_lock); 1354 spin_lock_init(&tc6->tx_skb_lock); 1355 1356 if (quirks) 1357 tc6->quirk_flags = quirks->quirk_flags; 1358 1359 /* Set the SPI controller to pump at realtime priority */ 1360 tc6->spi->rt = true; 1361 if (spi_setup(tc6->spi) < 0) 1362 return NULL; 1363 1364 tc6->spi_ctrl_tx_buf = devm_kzalloc(&tc6->spi->dev, 1365 OA_TC6_CTRL_SPI_BUF_SIZE, 1366 GFP_KERNEL); 1367 if (!tc6->spi_ctrl_tx_buf) 1368 return NULL; 1369 1370 tc6->spi_ctrl_rx_buf = devm_kzalloc(&tc6->spi->dev, 1371 OA_TC6_CTRL_SPI_BUF_SIZE, 1372 GFP_KERNEL); 1373 if (!tc6->spi_ctrl_rx_buf) 1374 return NULL; 1375 1376 tc6->spi_data_tx_buf = devm_kzalloc(&tc6->spi->dev, 1377 OA_TC6_SPI_DATA_BUF_SIZE, 1378 GFP_KERNEL); 1379 if (!tc6->spi_data_tx_buf) 1380 return NULL; 1381 1382 tc6->spi_data_rx_buf = devm_kzalloc(&tc6->spi->dev, 1383 OA_TC6_SPI_DATA_BUF_SIZE, 1384 GFP_KERNEL); 1385 if (!tc6->spi_data_rx_buf) 1386 return NULL; 1387 1388 /* Check the PROTE bit status so that we can reset the device */ 1389 ret = oa_tc6_check_ctrl_protection(tc6); 1390 if (ret) { 1391 dev_err(&tc6->spi->dev, 1392 "Failed to check the protection mode: %d\n", ret); 1393 return NULL; 1394 } 1395 1396 ret = oa_tc6_sw_reset_macphy(tc6); 1397 if (ret) { 1398 dev_err(&tc6->spi->dev, 1399 "MAC-PHY software reset failed: %d\n", ret); 1400 return NULL; 1401 } 1402 1403 ret = oa_tc6_unmask_macphy_error_interrupts(tc6); 1404 if (ret) { 1405 dev_err(&tc6->spi->dev, 1406 "MAC-PHY error interrupts unmask failed: %d\n", ret); 1407 return NULL; 1408 } 1409 1410 ret = oa_tc6_phy_init(tc6); 1411 if (ret) { 1412 dev_err(&tc6->spi->dev, 1413 "MAC internal PHY initialization failed: %d\n", ret); 1414 return NULL; 1415 } 1416 1417 ret = oa_tc6_enable_data_transfer(tc6); 1418 if (ret) { 1419 dev_err(&tc6->spi->dev, "Failed to enable data transfer: %d\n", 1420 ret); 1421 goto phy_exit; 1422 } 1423 1424 ret = oa_tc6_update_buffer_status_from_register(tc6); 1425 if (ret) { 1426 dev_err(&tc6->spi->dev, 1427 "Failed to update buffer status: %d\n", ret); 1428 goto phy_exit; 1429 } 1430 1431 ret = devm_request_threaded_irq(&tc6->spi->dev, tc6->spi->irq, 1432 oa_tc6_macphy_isr, 1433 oa_tc6_macphy_threaded_irq, 1434 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1435 dev_name(&tc6->spi->dev), tc6); 1436 if (ret) { 1437 dev_err(&tc6->spi->dev, "Failed to request macphy isr %d\n", 1438 ret); 1439 goto phy_exit; 1440 } 1441 1442 /* oa_tc6_sw_reset_macphy() function resets and clears the MAC-PHY reset 1443 * complete status. IRQ is also asserted on reset completion and it is 1444 * remain asserted until MAC-PHY receives a data chunk. So performing an 1445 * empty data chunk transmission will deassert the IRQ. Refer section 1446 * 7.7 and 9.2.8.8 in the OPEN Alliance specification for more details. 1447 */ 1448 tc6->int_flag = true; 1449 irq_wake_thread(tc6->spi->irq, tc6); 1450 1451 return tc6; 1452 1453 phy_exit: 1454 oa_tc6_phy_exit(tc6); 1455 return NULL; 1456 } 1457 EXPORT_SYMBOL_GPL(oa_tc6_init); 1458 1459 /** 1460 * oa_tc6_exit - exit function. 1461 * @tc6: oa_tc6 struct. 1462 */ 1463 void oa_tc6_exit(struct oa_tc6 *tc6) 1464 { 1465 tc6->disable_traffic = true; 1466 disable_irq(tc6->spi->irq); 1467 oa_tc6_phy_exit(tc6); 1468 oa_tc6_free_pending_skbs(tc6); 1469 } 1470 EXPORT_SYMBOL_GPL(oa_tc6_exit); 1471 1472 MODULE_DESCRIPTION("OPEN Alliance 10BASE‑T1x MAC‑PHY Serial Interface Lib"); 1473 MODULE_AUTHOR("Parthiban Veerasooran <parthiban.veerasooran@microchip.com>"); 1474 MODULE_LICENSE("GPL"); 1475