1 /* 2 * Copyright (C) 2015 Netronome Systems, Inc. 3 * 4 * This software is dual licensed under the GNU General License Version 2, 5 * June 1991 as shown in the file COPYING in the top-level directory of this 6 * source tree or the BSD 2-Clause License provided below. You have the 7 * option to license this software under the complete terms of either license. 8 * 9 * The BSD 2-Clause License: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * 2. Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 /* 35 * nfp_net_ctrl.h 36 * Netronome network device driver: Control BAR layout 37 * Authors: Jakub Kicinski <jakub.kicinski@netronome.com> 38 * Jason McMullan <jason.mcmullan@netronome.com> 39 * Rolf Neugebauer <rolf.neugebauer@netronome.com> 40 * Brad Petrus <brad.petrus@netronome.com> 41 */ 42 43 #ifndef _NFP_NET_CTRL_H_ 44 #define _NFP_NET_CTRL_H_ 45 46 /* IMPORTANT: This header file is shared with the FW, 47 * no OS specific constructs, please! 48 */ 49 50 /** 51 * Configuration BAR size. 52 * 53 * The configuration BAR is 8K in size, but due to 54 * THB-350, 32k needs to be reserved. 55 */ 56 #define NFP_NET_CFG_BAR_SZ (32 * 1024) 57 58 /** 59 * Offset in Freelist buffer where packet starts on RX 60 */ 61 #define NFP_NET_RX_OFFSET 32 62 63 /** 64 * Maximum header size supported for LSO frames 65 */ 66 #define NFP_NET_LSO_MAX_HDR_SZ 255 67 68 /** 69 * Prepend field types 70 */ 71 #define NFP_NET_META_FIELD_SIZE 4 72 #define NFP_NET_META_HASH 1 /* next field carries hash type */ 73 #define NFP_NET_META_MARK 2 74 75 /** 76 * Hash type pre-pended when a RSS hash was computed 77 */ 78 #define NFP_NET_RSS_NONE 0 79 #define NFP_NET_RSS_IPV4 1 80 #define NFP_NET_RSS_IPV6 2 81 #define NFP_NET_RSS_IPV6_EX 3 82 #define NFP_NET_RSS_IPV4_TCP 4 83 #define NFP_NET_RSS_IPV6_TCP 5 84 #define NFP_NET_RSS_IPV6_EX_TCP 6 85 #define NFP_NET_RSS_IPV4_UDP 7 86 #define NFP_NET_RSS_IPV6_UDP 8 87 #define NFP_NET_RSS_IPV6_EX_UDP 9 88 89 /** 90 * @NFP_NET_TXR_MAX: Maximum number of TX rings 91 * @NFP_NET_RXR_MAX: Maximum number of RX rings 92 */ 93 #define NFP_NET_TXR_MAX 64 94 #define NFP_NET_RXR_MAX 64 95 96 /** 97 * Read/Write config words (0x0000 - 0x002c) 98 * @NFP_NET_CFG_CTRL: Global control 99 * @NFP_NET_CFG_UPDATE: Indicate which fields are updated 100 * @NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings 101 * @NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings 102 * @NFP_NET_CFG_MTU: Set MTU size 103 * @NFP_NET_CFG_FLBUFSZ: Set freelist buffer size (must be larger than MTU) 104 * @NFP_NET_CFG_EXN: MSI-X table entry for exceptions 105 * @NFP_NET_CFG_LSC: MSI-X table entry for link state changes 106 * @NFP_NET_CFG_MACADDR: MAC address 107 * 108 * TODO: 109 * - define Error details in UPDATE 110 */ 111 #define NFP_NET_CFG_CTRL 0x0000 112 #define NFP_NET_CFG_CTRL_ENABLE (0x1 << 0) /* Global enable */ 113 #define NFP_NET_CFG_CTRL_PROMISC (0x1 << 1) /* Enable Promisc mode */ 114 #define NFP_NET_CFG_CTRL_L2BC (0x1 << 2) /* Allow L2 Broadcast */ 115 #define NFP_NET_CFG_CTRL_L2MC (0x1 << 3) /* Allow L2 Multicast */ 116 #define NFP_NET_CFG_CTRL_RXCSUM (0x1 << 4) /* Enable RX Checksum */ 117 #define NFP_NET_CFG_CTRL_TXCSUM (0x1 << 5) /* Enable TX Checksum */ 118 #define NFP_NET_CFG_CTRL_RXVLAN (0x1 << 6) /* Enable VLAN strip */ 119 #define NFP_NET_CFG_CTRL_TXVLAN (0x1 << 7) /* Enable VLAN insert */ 120 #define NFP_NET_CFG_CTRL_SCATTER (0x1 << 8) /* Scatter DMA */ 121 #define NFP_NET_CFG_CTRL_GATHER (0x1 << 9) /* Gather DMA */ 122 #define NFP_NET_CFG_CTRL_LSO (0x1 << 10) /* LSO/TSO */ 123 #define NFP_NET_CFG_CTRL_RINGCFG (0x1 << 16) /* Ring runtime changes */ 124 #define NFP_NET_CFG_CTRL_RSS (0x1 << 17) /* RSS */ 125 #define NFP_NET_CFG_CTRL_IRQMOD (0x1 << 18) /* Interrupt moderation */ 126 #define NFP_NET_CFG_CTRL_RINGPRIO (0x1 << 19) /* Ring priorities */ 127 #define NFP_NET_CFG_CTRL_MSIXAUTO (0x1 << 20) /* MSI-X auto-masking */ 128 #define NFP_NET_CFG_CTRL_TXRWB (0x1 << 21) /* Write-back of TX ring*/ 129 #define NFP_NET_CFG_CTRL_L2SWITCH (0x1 << 22) /* L2 Switch */ 130 #define NFP_NET_CFG_CTRL_L2SWITCH_LOCAL (0x1 << 23) /* Switch to local */ 131 #define NFP_NET_CFG_CTRL_VXLAN (0x1 << 24) /* VXLAN tunnel support */ 132 #define NFP_NET_CFG_CTRL_NVGRE (0x1 << 25) /* NVGRE tunnel support */ 133 #define NFP_NET_CFG_CTRL_BPF (0x1 << 27) /* BPF offload capable */ 134 #define NFP_NET_CFG_UPDATE 0x0004 135 #define NFP_NET_CFG_UPDATE_GEN (0x1 << 0) /* General update */ 136 #define NFP_NET_CFG_UPDATE_RING (0x1 << 1) /* Ring config change */ 137 #define NFP_NET_CFG_UPDATE_RSS (0x1 << 2) /* RSS config change */ 138 #define NFP_NET_CFG_UPDATE_TXRPRIO (0x1 << 3) /* TX Ring prio change */ 139 #define NFP_NET_CFG_UPDATE_RXRPRIO (0x1 << 4) /* RX Ring prio change */ 140 #define NFP_NET_CFG_UPDATE_MSIX (0x1 << 5) /* MSI-X change */ 141 #define NFP_NET_CFG_UPDATE_L2SWITCH (0x1 << 6) /* Switch changes */ 142 #define NFP_NET_CFG_UPDATE_RESET (0x1 << 7) /* Update due to FLR */ 143 #define NFP_NET_CFG_UPDATE_IRQMOD (0x1 << 8) /* IRQ mod change */ 144 #define NFP_NET_CFG_UPDATE_VXLAN (0x1 << 9) /* VXLAN port change */ 145 #define NFP_NET_CFG_UPDATE_BPF (0x1 << 10) /* BPF program load */ 146 #define NFP_NET_CFG_UPDATE_ERR (0x1 << 31) /* A error occurred */ 147 #define NFP_NET_CFG_TXRS_ENABLE 0x0008 148 #define NFP_NET_CFG_RXRS_ENABLE 0x0010 149 #define NFP_NET_CFG_MTU 0x0018 150 #define NFP_NET_CFG_FLBUFSZ 0x001c 151 #define NFP_NET_CFG_EXN 0x001f 152 #define NFP_NET_CFG_LSC 0x0020 153 #define NFP_NET_CFG_MACADDR 0x0024 154 155 /** 156 * Read-only words (0x0030 - 0x0050): 157 * @NFP_NET_CFG_VERSION: Firmware version number 158 * @NFP_NET_CFG_STS: Status 159 * @NFP_NET_CFG_CAP: Capabilities (same bits as @NFP_NET_CFG_CTRL) 160 * @NFP_NET_CFG_MAX_TXRINGS: Maximum number of TX rings 161 * @NFP_NET_CFG_MAX_RXRINGS: Maximum number of RX rings 162 * @NFP_NET_CFG_MAX_MTU: Maximum support MTU 163 * @NFP_NET_CFG_START_TXQ: Start Queue Control Queue to use for TX (PF only) 164 * @NFP_NET_CFG_START_RXQ: Start Queue Control Queue to use for RX (PF only) 165 * 166 * TODO: 167 * - define more STS bits 168 */ 169 #define NFP_NET_CFG_VERSION 0x0030 170 #define NFP_NET_CFG_VERSION_RESERVED_MASK (0xff << 24) 171 #define NFP_NET_CFG_VERSION_CLASS_MASK (0xff << 16) 172 #define NFP_NET_CFG_VERSION_CLASS(x) (((x) & 0xff) << 16) 173 #define NFP_NET_CFG_VERSION_CLASS_GENERIC 0 174 #define NFP_NET_CFG_VERSION_MAJOR_MASK (0xff << 8) 175 #define NFP_NET_CFG_VERSION_MAJOR(x) (((x) & 0xff) << 8) 176 #define NFP_NET_CFG_VERSION_MINOR_MASK (0xff << 0) 177 #define NFP_NET_CFG_VERSION_MINOR(x) (((x) & 0xff) << 0) 178 #define NFP_NET_CFG_STS 0x0034 179 #define NFP_NET_CFG_STS_LINK (0x1 << 0) /* Link up or down */ 180 #define NFP_NET_CFG_CAP 0x0038 181 #define NFP_NET_CFG_MAX_TXRINGS 0x003c 182 #define NFP_NET_CFG_MAX_RXRINGS 0x0040 183 #define NFP_NET_CFG_MAX_MTU 0x0044 184 /* Next two words are being used by VFs for solving THB350 issue */ 185 #define NFP_NET_CFG_START_TXQ 0x0048 186 #define NFP_NET_CFG_START_RXQ 0x004c 187 188 /** 189 * Prepend configuration 190 */ 191 #define NFP_NET_CFG_RX_OFFSET 0x0050 192 #define NFP_NET_CFG_RX_OFFSET_DYNAMIC 0 /* Prepend mode */ 193 194 /** 195 * VXLAN/UDP encap configuration 196 * @NFP_NET_CFG_VXLAN_PORT: Base address of table of tunnels' UDP dst ports 197 * @NFP_NET_CFG_VXLAN_SZ: Size of the UDP port table in bytes 198 */ 199 #define NFP_NET_CFG_VXLAN_PORT 0x0060 200 #define NFP_NET_CFG_VXLAN_SZ 0x0008 201 202 /** 203 * BPF section 204 * @NFP_NET_CFG_BPF_ABI: BPF ABI version 205 * @NFP_NET_CFG_BPF_CAP: BPF capabilities 206 * @NFP_NET_CFG_BPF_MAX_LEN: Maximum size of JITed BPF code in bytes 207 * @NFP_NET_CFG_BPF_START: Offset at which BPF will be loaded 208 * @NFP_NET_CFG_BPF_DONE: Offset to jump to on exit 209 * @NFP_NET_CFG_BPF_STACK_SZ: Total size of stack area in 64B chunks 210 * @NFP_NET_CFG_BPF_INL_MTU: Packet data split offset in 64B chunks 211 * @NFP_NET_CFG_BPF_SIZE: Size of the JITed BPF code in instructions 212 * @NFP_NET_CFG_BPF_ADDR: DMA address of the buffer with JITed BPF code 213 */ 214 #define NFP_NET_CFG_BPF_ABI 0x0080 215 #define NFP_NET_BPF_ABI 1 216 #define NFP_NET_CFG_BPF_CAP 0x0081 217 #define NFP_NET_BPF_CAP_RELO (1 << 0) /* seamless reload */ 218 #define NFP_NET_CFG_BPF_MAX_LEN 0x0082 219 #define NFP_NET_CFG_BPF_START 0x0084 220 #define NFP_NET_CFG_BPF_DONE 0x0086 221 #define NFP_NET_CFG_BPF_STACK_SZ 0x0088 222 #define NFP_NET_CFG_BPF_INL_MTU 0x0089 223 #define NFP_NET_CFG_BPF_SIZE 0x008e 224 #define NFP_NET_CFG_BPF_ADDR 0x0090 225 #define NFP_NET_CFG_BPF_CFG_8CTX (1 << 0) /* 8ctx mode */ 226 #define NFP_NET_CFG_BPF_CFG_MASK 7ULL 227 #define NFP_NET_CFG_BPF_ADDR_MASK (~NFP_NET_CFG_BPF_CFG_MASK) 228 229 /** 230 * 40B reserved for future use (0x0098 - 0x00c0) 231 */ 232 #define NFP_NET_CFG_RESERVED 0x0098 233 #define NFP_NET_CFG_RESERVED_SZ 0x0028 234 235 /** 236 * RSS configuration (0x0100 - 0x01ac): 237 * Used only when NFP_NET_CFG_CTRL_RSS is enabled 238 * @NFP_NET_CFG_RSS_CFG: RSS configuration word 239 * @NFP_NET_CFG_RSS_KEY: RSS "secret" key 240 * @NFP_NET_CFG_RSS_ITBL: RSS indirection table 241 */ 242 #define NFP_NET_CFG_RSS_BASE 0x0100 243 #define NFP_NET_CFG_RSS_CTRL NFP_NET_CFG_RSS_BASE 244 #define NFP_NET_CFG_RSS_MASK (0x7f) 245 #define NFP_NET_CFG_RSS_MASK_of(_x) ((_x) & 0x7f) 246 #define NFP_NET_CFG_RSS_IPV4 (1 << 8) /* RSS for IPv4 */ 247 #define NFP_NET_CFG_RSS_IPV6 (1 << 9) /* RSS for IPv6 */ 248 #define NFP_NET_CFG_RSS_IPV4_TCP (1 << 10) /* RSS for IPv4/TCP */ 249 #define NFP_NET_CFG_RSS_IPV4_UDP (1 << 11) /* RSS for IPv4/UDP */ 250 #define NFP_NET_CFG_RSS_IPV6_TCP (1 << 12) /* RSS for IPv6/TCP */ 251 #define NFP_NET_CFG_RSS_IPV6_UDP (1 << 13) /* RSS for IPv6/UDP */ 252 #define NFP_NET_CFG_RSS_TOEPLITZ (1 << 24) /* Use Toeplitz hash */ 253 #define NFP_NET_CFG_RSS_KEY (NFP_NET_CFG_RSS_BASE + 0x4) 254 #define NFP_NET_CFG_RSS_KEY_SZ 0x28 255 #define NFP_NET_CFG_RSS_ITBL (NFP_NET_CFG_RSS_BASE + 0x4 + \ 256 NFP_NET_CFG_RSS_KEY_SZ) 257 #define NFP_NET_CFG_RSS_ITBL_SZ 0x80 258 259 /** 260 * TX ring configuration (0x200 - 0x800) 261 * @NFP_NET_CFG_TXR_BASE: Base offset for TX ring configuration 262 * @NFP_NET_CFG_TXR_ADDR: Per TX ring DMA address (8B entries) 263 * @NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries) 264 * @NFP_NET_CFG_TXR_SZ: Per TX ring ring size (1B entries) 265 * @NFP_NET_CFG_TXR_VEC: Per TX ring MSI-X table entry (1B entries) 266 * @NFP_NET_CFG_TXR_PRIO: Per TX ring priority (1B entries) 267 * @NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation packet 268 */ 269 #define NFP_NET_CFG_TXR_BASE 0x0200 270 #define NFP_NET_CFG_TXR_ADDR(_x) (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8)) 271 #define NFP_NET_CFG_TXR_WB_ADDR(_x) (NFP_NET_CFG_TXR_BASE + 0x200 + \ 272 ((_x) * 0x8)) 273 #define NFP_NET_CFG_TXR_SZ(_x) (NFP_NET_CFG_TXR_BASE + 0x400 + (_x)) 274 #define NFP_NET_CFG_TXR_VEC(_x) (NFP_NET_CFG_TXR_BASE + 0x440 + (_x)) 275 #define NFP_NET_CFG_TXR_PRIO(_x) (NFP_NET_CFG_TXR_BASE + 0x480 + (_x)) 276 #define NFP_NET_CFG_TXR_IRQ_MOD(_x) (NFP_NET_CFG_TXR_BASE + 0x500 + \ 277 ((_x) * 0x4)) 278 279 /** 280 * RX ring configuration (0x0800 - 0x0c00) 281 * @NFP_NET_CFG_RXR_BASE: Base offset for RX ring configuration 282 * @NFP_NET_CFG_RXR_ADDR: Per RX ring DMA address (8B entries) 283 * @NFP_NET_CFG_RXR_SZ: Per RX ring ring size (1B entries) 284 * @NFP_NET_CFG_RXR_VEC: Per RX ring MSI-X table entry (1B entries) 285 * @NFP_NET_CFG_RXR_PRIO: Per RX ring priority (1B entries) 286 * @NFP_NET_CFG_RXR_IRQ_MOD: Per RX ring interrupt moderation (4B entries) 287 */ 288 #define NFP_NET_CFG_RXR_BASE 0x0800 289 #define NFP_NET_CFG_RXR_ADDR(_x) (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8)) 290 #define NFP_NET_CFG_RXR_SZ(_x) (NFP_NET_CFG_RXR_BASE + 0x200 + (_x)) 291 #define NFP_NET_CFG_RXR_VEC(_x) (NFP_NET_CFG_RXR_BASE + 0x240 + (_x)) 292 #define NFP_NET_CFG_RXR_PRIO(_x) (NFP_NET_CFG_RXR_BASE + 0x280 + (_x)) 293 #define NFP_NET_CFG_RXR_IRQ_MOD(_x) (NFP_NET_CFG_RXR_BASE + 0x300 + \ 294 ((_x) * 0x4)) 295 296 /** 297 * Interrupt Control/Cause registers (0x0c00 - 0x0d00) 298 * These registers are only used when MSI-X auto-masking is not 299 * enabled (@NFP_NET_CFG_CTRL_MSIXAUTO not set). The array is index 300 * by MSI-X entry and are 1B in size. If an entry is zero, the 301 * corresponding entry is enabled. If the FW generates an interrupt, 302 * it writes a cause into the corresponding field. This also masks 303 * the MSI-X entry and the host driver must clear the register to 304 * re-enable the interrupt. 305 */ 306 #define NFP_NET_CFG_ICR_BASE 0x0c00 307 #define NFP_NET_CFG_ICR(_x) (NFP_NET_CFG_ICR_BASE + (_x)) 308 #define NFP_NET_CFG_ICR_UNMASKED 0x0 309 #define NFP_NET_CFG_ICR_RXTX 0x1 310 #define NFP_NET_CFG_ICR_LSC 0x2 311 312 /** 313 * General device stats (0x0d00 - 0x0d90) 314 * all counters are 64bit. 315 */ 316 #define NFP_NET_CFG_STATS_BASE 0x0d00 317 #define NFP_NET_CFG_STATS_RX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x00) 318 #define NFP_NET_CFG_STATS_RX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x08) 319 #define NFP_NET_CFG_STATS_RX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x10) 320 #define NFP_NET_CFG_STATS_RX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x18) 321 #define NFP_NET_CFG_STATS_RX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x20) 322 #define NFP_NET_CFG_STATS_RX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x28) 323 #define NFP_NET_CFG_STATS_RX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x30) 324 #define NFP_NET_CFG_STATS_RX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x38) 325 #define NFP_NET_CFG_STATS_RX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x40) 326 327 #define NFP_NET_CFG_STATS_TX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x48) 328 #define NFP_NET_CFG_STATS_TX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x50) 329 #define NFP_NET_CFG_STATS_TX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x58) 330 #define NFP_NET_CFG_STATS_TX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x60) 331 #define NFP_NET_CFG_STATS_TX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x68) 332 #define NFP_NET_CFG_STATS_TX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x70) 333 #define NFP_NET_CFG_STATS_TX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x78) 334 #define NFP_NET_CFG_STATS_TX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x80) 335 #define NFP_NET_CFG_STATS_TX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x88) 336 337 #define NFP_NET_CFG_STATS_APP0_FRAMES (NFP_NET_CFG_STATS_BASE + 0x90) 338 #define NFP_NET_CFG_STATS_APP0_BYTES (NFP_NET_CFG_STATS_BASE + 0x98) 339 #define NFP_NET_CFG_STATS_APP1_FRAMES (NFP_NET_CFG_STATS_BASE + 0xa0) 340 #define NFP_NET_CFG_STATS_APP1_BYTES (NFP_NET_CFG_STATS_BASE + 0xa8) 341 #define NFP_NET_CFG_STATS_APP2_FRAMES (NFP_NET_CFG_STATS_BASE + 0xb0) 342 #define NFP_NET_CFG_STATS_APP2_BYTES (NFP_NET_CFG_STATS_BASE + 0xb8) 343 #define NFP_NET_CFG_STATS_APP3_FRAMES (NFP_NET_CFG_STATS_BASE + 0xc0) 344 #define NFP_NET_CFG_STATS_APP3_BYTES (NFP_NET_CFG_STATS_BASE + 0xc8) 345 346 /** 347 * Per ring stats (0x1000 - 0x1800) 348 * options, 64bit per entry 349 * @NFP_NET_CFG_TXR_STATS: TX ring statistics (Packet and Byte count) 350 * @NFP_NET_CFG_RXR_STATS: RX ring statistics (Packet and Byte count) 351 */ 352 #define NFP_NET_CFG_TXR_STATS_BASE 0x1000 353 #define NFP_NET_CFG_TXR_STATS(_x) (NFP_NET_CFG_TXR_STATS_BASE + \ 354 ((_x) * 0x10)) 355 #define NFP_NET_CFG_RXR_STATS_BASE 0x1400 356 #define NFP_NET_CFG_RXR_STATS(_x) (NFP_NET_CFG_RXR_STATS_BASE + \ 357 ((_x) * 0x10)) 358 359 #endif /* _NFP_NET_CTRL_H_ */ 360