1 /* 2 * Copyright (C) 2015-2017 Netronome Systems, Inc. 3 * 4 * This software is dual licensed under the GNU General License Version 2, 5 * June 1991 as shown in the file COPYING in the top-level directory of this 6 * source tree or the BSD 2-Clause License provided below. You have the 7 * option to license this software under the complete terms of either license. 8 * 9 * The BSD 2-Clause License: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * 2. Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 /* 35 * nfp_net_ctrl.h 36 * Netronome network device driver: Control BAR layout 37 * Authors: Jakub Kicinski <jakub.kicinski@netronome.com> 38 * Jason McMullan <jason.mcmullan@netronome.com> 39 * Rolf Neugebauer <rolf.neugebauer@netronome.com> 40 * Brad Petrus <brad.petrus@netronome.com> 41 */ 42 43 #ifndef _NFP_NET_CTRL_H_ 44 #define _NFP_NET_CTRL_H_ 45 46 #include <linux/types.h> 47 48 /** 49 * Configuration BAR size. 50 * 51 * The configuration BAR is 8K in size, but due to 52 * THB-350, 32k needs to be reserved. 53 */ 54 #define NFP_NET_CFG_BAR_SZ (32 * 1024) 55 56 /** 57 * Offset in Freelist buffer where packet starts on RX 58 */ 59 #define NFP_NET_RX_OFFSET 32 60 61 /** 62 * Maximum header size supported for LSO frames 63 */ 64 #define NFP_NET_LSO_MAX_HDR_SZ 255 65 66 /** 67 * Prepend field types 68 */ 69 #define NFP_NET_META_FIELD_SIZE 4 70 #define NFP_NET_META_HASH 1 /* next field carries hash type */ 71 #define NFP_NET_META_MARK 2 72 #define NFP_NET_META_PORTID 5 73 #define NFP_NET_META_CSUM 6 /* checksum complete type */ 74 75 #define NFP_META_PORT_ID_CTRL ~0U 76 77 /** 78 * Hash type pre-pended when a RSS hash was computed 79 */ 80 #define NFP_NET_RSS_NONE 0 81 #define NFP_NET_RSS_IPV4 1 82 #define NFP_NET_RSS_IPV6 2 83 #define NFP_NET_RSS_IPV6_EX 3 84 #define NFP_NET_RSS_IPV4_TCP 4 85 #define NFP_NET_RSS_IPV6_TCP 5 86 #define NFP_NET_RSS_IPV6_EX_TCP 6 87 #define NFP_NET_RSS_IPV4_UDP 7 88 #define NFP_NET_RSS_IPV6_UDP 8 89 #define NFP_NET_RSS_IPV6_EX_UDP 9 90 91 /** 92 * Ring counts 93 * %NFP_NET_TXR_MAX: Maximum number of TX rings 94 * %NFP_NET_RXR_MAX: Maximum number of RX rings 95 */ 96 #define NFP_NET_TXR_MAX 64 97 #define NFP_NET_RXR_MAX 64 98 99 /** 100 * Read/Write config words (0x0000 - 0x002c) 101 * %NFP_NET_CFG_CTRL: Global control 102 * %NFP_NET_CFG_UPDATE: Indicate which fields are updated 103 * %NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings 104 * %NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings 105 * %NFP_NET_CFG_MTU: Set MTU size 106 * %NFP_NET_CFG_FLBUFSZ: Set freelist buffer size (must be larger than MTU) 107 * %NFP_NET_CFG_EXN: MSI-X table entry for exceptions 108 * %NFP_NET_CFG_LSC: MSI-X table entry for link state changes 109 * %NFP_NET_CFG_MACADDR: MAC address 110 * 111 * TODO: 112 * - define Error details in UPDATE 113 */ 114 #define NFP_NET_CFG_CTRL 0x0000 115 #define NFP_NET_CFG_CTRL_ENABLE (0x1 << 0) /* Global enable */ 116 #define NFP_NET_CFG_CTRL_PROMISC (0x1 << 1) /* Enable Promisc mode */ 117 #define NFP_NET_CFG_CTRL_L2BC (0x1 << 2) /* Allow L2 Broadcast */ 118 #define NFP_NET_CFG_CTRL_L2MC (0x1 << 3) /* Allow L2 Multicast */ 119 #define NFP_NET_CFG_CTRL_RXCSUM (0x1 << 4) /* Enable RX Checksum */ 120 #define NFP_NET_CFG_CTRL_TXCSUM (0x1 << 5) /* Enable TX Checksum */ 121 #define NFP_NET_CFG_CTRL_RXVLAN (0x1 << 6) /* Enable VLAN strip */ 122 #define NFP_NET_CFG_CTRL_TXVLAN (0x1 << 7) /* Enable VLAN insert */ 123 #define NFP_NET_CFG_CTRL_SCATTER (0x1 << 8) /* Scatter DMA */ 124 #define NFP_NET_CFG_CTRL_GATHER (0x1 << 9) /* Gather DMA */ 125 #define NFP_NET_CFG_CTRL_LSO (0x1 << 10) /* LSO/TSO (version 1) */ 126 #define NFP_NET_CFG_CTRL_CTAG_FILTER (0x1 << 11) /* VLAN CTAG filtering */ 127 #define NFP_NET_CFG_CTRL_RINGCFG (0x1 << 16) /* Ring runtime changes */ 128 #define NFP_NET_CFG_CTRL_RSS (0x1 << 17) /* RSS (version 1) */ 129 #define NFP_NET_CFG_CTRL_IRQMOD (0x1 << 18) /* Interrupt moderation */ 130 #define NFP_NET_CFG_CTRL_RINGPRIO (0x1 << 19) /* Ring priorities */ 131 #define NFP_NET_CFG_CTRL_MSIXAUTO (0x1 << 20) /* MSI-X auto-masking */ 132 #define NFP_NET_CFG_CTRL_TXRWB (0x1 << 21) /* Write-back of TX ring*/ 133 #define NFP_NET_CFG_CTRL_L2SWITCH (0x1 << 22) /* L2 Switch */ 134 #define NFP_NET_CFG_CTRL_L2SWITCH_LOCAL (0x1 << 23) /* Switch to local */ 135 #define NFP_NET_CFG_CTRL_VXLAN (0x1 << 24) /* VXLAN tunnel support */ 136 #define NFP_NET_CFG_CTRL_NVGRE (0x1 << 25) /* NVGRE tunnel support */ 137 #define NFP_NET_CFG_CTRL_BPF (0x1 << 27) /* BPF offload capable */ 138 #define NFP_NET_CFG_CTRL_LSO2 (0x1 << 28) /* LSO/TSO (version 2) */ 139 #define NFP_NET_CFG_CTRL_RSS2 (0x1 << 29) /* RSS (version 2) */ 140 #define NFP_NET_CFG_CTRL_CSUM_COMPLETE (0x1 << 30) /* Checksum complete */ 141 #define NFP_NET_CFG_CTRL_LIVE_ADDR (0x1 << 31) /* live MAC addr change */ 142 143 #define NFP_NET_CFG_CTRL_LSO_ANY (NFP_NET_CFG_CTRL_LSO | \ 144 NFP_NET_CFG_CTRL_LSO2) 145 #define NFP_NET_CFG_CTRL_RSS_ANY (NFP_NET_CFG_CTRL_RSS | \ 146 NFP_NET_CFG_CTRL_RSS2) 147 #define NFP_NET_CFG_CTRL_RXCSUM_ANY (NFP_NET_CFG_CTRL_RXCSUM | \ 148 NFP_NET_CFG_CTRL_CSUM_COMPLETE) 149 #define NFP_NET_CFG_CTRL_CHAIN_META (NFP_NET_CFG_CTRL_RSS2 | \ 150 NFP_NET_CFG_CTRL_CSUM_COMPLETE) 151 152 #define NFP_NET_CFG_UPDATE 0x0004 153 #define NFP_NET_CFG_UPDATE_GEN (0x1 << 0) /* General update */ 154 #define NFP_NET_CFG_UPDATE_RING (0x1 << 1) /* Ring config change */ 155 #define NFP_NET_CFG_UPDATE_RSS (0x1 << 2) /* RSS config change */ 156 #define NFP_NET_CFG_UPDATE_TXRPRIO (0x1 << 3) /* TX Ring prio change */ 157 #define NFP_NET_CFG_UPDATE_RXRPRIO (0x1 << 4) /* RX Ring prio change */ 158 #define NFP_NET_CFG_UPDATE_MSIX (0x1 << 5) /* MSI-X change */ 159 #define NFP_NET_CFG_UPDATE_L2SWITCH (0x1 << 6) /* Switch changes */ 160 #define NFP_NET_CFG_UPDATE_RESET (0x1 << 7) /* Update due to FLR */ 161 #define NFP_NET_CFG_UPDATE_IRQMOD (0x1 << 8) /* IRQ mod change */ 162 #define NFP_NET_CFG_UPDATE_VXLAN (0x1 << 9) /* VXLAN port change */ 163 #define NFP_NET_CFG_UPDATE_BPF (0x1 << 10) /* BPF program load */ 164 #define NFP_NET_CFG_UPDATE_MACADDR (0x1 << 11) /* MAC address change */ 165 #define NFP_NET_CFG_UPDATE_MBOX (0x1 << 12) /* Mailbox update */ 166 #define NFP_NET_CFG_UPDATE_VF (0x1 << 13) /* VF settings change */ 167 #define NFP_NET_CFG_UPDATE_ERR (0x1 << 31) /* A error occurred */ 168 #define NFP_NET_CFG_TXRS_ENABLE 0x0008 169 #define NFP_NET_CFG_RXRS_ENABLE 0x0010 170 #define NFP_NET_CFG_MTU 0x0018 171 #define NFP_NET_CFG_FLBUFSZ 0x001c 172 #define NFP_NET_CFG_EXN 0x001f 173 #define NFP_NET_CFG_LSC 0x0020 174 #define NFP_NET_CFG_MACADDR 0x0024 175 176 /** 177 * Read-only words (0x0030 - 0x0050): 178 * %NFP_NET_CFG_VERSION: Firmware version number 179 * %NFP_NET_CFG_STS: Status 180 * %NFP_NET_CFG_CAP: Capabilities (same bits as %NFP_NET_CFG_CTRL) 181 * %NFP_NET_CFG_MAX_TXRINGS: Maximum number of TX rings 182 * %NFP_NET_CFG_MAX_RXRINGS: Maximum number of RX rings 183 * %NFP_NET_CFG_MAX_MTU: Maximum support MTU 184 * %NFP_NET_CFG_START_TXQ: Start Queue Control Queue to use for TX (PF only) 185 * %NFP_NET_CFG_START_RXQ: Start Queue Control Queue to use for RX (PF only) 186 * 187 * TODO: 188 * - define more STS bits 189 */ 190 #define NFP_NET_CFG_VERSION 0x0030 191 #define NFP_NET_CFG_VERSION_RESERVED_MASK (0xff << 24) 192 #define NFP_NET_CFG_VERSION_CLASS_MASK (0xff << 16) 193 #define NFP_NET_CFG_VERSION_CLASS(x) (((x) & 0xff) << 16) 194 #define NFP_NET_CFG_VERSION_CLASS_GENERIC 0 195 #define NFP_NET_CFG_VERSION_MAJOR_MASK (0xff << 8) 196 #define NFP_NET_CFG_VERSION_MAJOR(x) (((x) & 0xff) << 8) 197 #define NFP_NET_CFG_VERSION_MINOR_MASK (0xff << 0) 198 #define NFP_NET_CFG_VERSION_MINOR(x) (((x) & 0xff) << 0) 199 #define NFP_NET_CFG_STS 0x0034 200 #define NFP_NET_CFG_STS_LINK (0x1 << 0) /* Link up or down */ 201 /* Link rate */ 202 #define NFP_NET_CFG_STS_LINK_RATE_SHIFT 1 203 #define NFP_NET_CFG_STS_LINK_RATE_MASK 0xF 204 #define NFP_NET_CFG_STS_LINK_RATE \ 205 (NFP_NET_CFG_STS_LINK_RATE_MASK << NFP_NET_CFG_STS_LINK_RATE_SHIFT) 206 #define NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED 0 207 #define NFP_NET_CFG_STS_LINK_RATE_UNKNOWN 1 208 #define NFP_NET_CFG_STS_LINK_RATE_1G 2 209 #define NFP_NET_CFG_STS_LINK_RATE_10G 3 210 #define NFP_NET_CFG_STS_LINK_RATE_25G 4 211 #define NFP_NET_CFG_STS_LINK_RATE_40G 5 212 #define NFP_NET_CFG_STS_LINK_RATE_50G 6 213 #define NFP_NET_CFG_STS_LINK_RATE_100G 7 214 #define NFP_NET_CFG_CAP 0x0038 215 #define NFP_NET_CFG_MAX_TXRINGS 0x003c 216 #define NFP_NET_CFG_MAX_RXRINGS 0x0040 217 #define NFP_NET_CFG_MAX_MTU 0x0044 218 /* Next two words are being used by VFs for solving THB350 issue */ 219 #define NFP_NET_CFG_START_TXQ 0x0048 220 #define NFP_NET_CFG_START_RXQ 0x004c 221 222 /** 223 * Prepend configuration 224 */ 225 #define NFP_NET_CFG_RX_OFFSET 0x0050 226 #define NFP_NET_CFG_RX_OFFSET_DYNAMIC 0 /* Prepend mode */ 227 228 /** 229 * RSS capabilities 230 * %NFP_NET_CFG_RSS_CAP_HFUNC: supported hash functions (same bits as 231 * %NFP_NET_CFG_RSS_HFUNC) 232 */ 233 #define NFP_NET_CFG_RSS_CAP 0x0054 234 #define NFP_NET_CFG_RSS_CAP_HFUNC 0xff000000 235 236 /** 237 * TLV area start 238 * %NFP_NET_CFG_TLV_BASE: start anchor of the TLV area 239 */ 240 #define NFP_NET_CFG_TLV_BASE 0x0058 241 242 /** 243 * VXLAN/UDP encap configuration 244 * %NFP_NET_CFG_VXLAN_PORT: Base address of table of tunnels' UDP dst ports 245 * %NFP_NET_CFG_VXLAN_SZ: Size of the UDP port table in bytes 246 */ 247 #define NFP_NET_CFG_VXLAN_PORT 0x0060 248 #define NFP_NET_CFG_VXLAN_SZ 0x0008 249 250 /** 251 * BPF section 252 * %NFP_NET_CFG_BPF_ABI: BPF ABI version 253 * %NFP_NET_CFG_BPF_CAP: BPF capabilities 254 * %NFP_NET_CFG_BPF_MAX_LEN: Maximum size of JITed BPF code in bytes 255 * %NFP_NET_CFG_BPF_START: Offset at which BPF will be loaded 256 * %NFP_NET_CFG_BPF_DONE: Offset to jump to on exit 257 * %NFP_NET_CFG_BPF_STACK_SZ: Total size of stack area in 64B chunks 258 * %NFP_NET_CFG_BPF_INL_MTU: Packet data split offset in 64B chunks 259 * %NFP_NET_CFG_BPF_SIZE: Size of the JITed BPF code in instructions 260 * %NFP_NET_CFG_BPF_ADDR: DMA address of the buffer with JITed BPF code 261 */ 262 #define NFP_NET_CFG_BPF_ABI 0x0080 263 #define NFP_NET_BPF_ABI 2 264 #define NFP_NET_CFG_BPF_CAP 0x0081 265 #define NFP_NET_BPF_CAP_RELO (1 << 0) /* seamless reload */ 266 #define NFP_NET_CFG_BPF_MAX_LEN 0x0082 267 #define NFP_NET_CFG_BPF_START 0x0084 268 #define NFP_NET_CFG_BPF_DONE 0x0086 269 #define NFP_NET_CFG_BPF_STACK_SZ 0x0088 270 #define NFP_NET_CFG_BPF_INL_MTU 0x0089 271 #define NFP_NET_CFG_BPF_SIZE 0x008e 272 #define NFP_NET_CFG_BPF_ADDR 0x0090 273 #define NFP_NET_CFG_BPF_CFG_8CTX (1 << 0) /* 8ctx mode */ 274 #define NFP_NET_CFG_BPF_CFG_MASK 7ULL 275 #define NFP_NET_CFG_BPF_ADDR_MASK (~NFP_NET_CFG_BPF_CFG_MASK) 276 277 /** 278 * 40B reserved for future use (0x0098 - 0x00c0) 279 */ 280 #define NFP_NET_CFG_RESERVED 0x0098 281 #define NFP_NET_CFG_RESERVED_SZ 0x0028 282 283 /** 284 * RSS configuration (0x0100 - 0x01ac): 285 * Used only when NFP_NET_CFG_CTRL_RSS is enabled 286 * %NFP_NET_CFG_RSS_CFG: RSS configuration word 287 * %NFP_NET_CFG_RSS_KEY: RSS "secret" key 288 * %NFP_NET_CFG_RSS_ITBL: RSS indirection table 289 */ 290 #define NFP_NET_CFG_RSS_BASE 0x0100 291 #define NFP_NET_CFG_RSS_CTRL NFP_NET_CFG_RSS_BASE 292 #define NFP_NET_CFG_RSS_MASK (0x7f) 293 #define NFP_NET_CFG_RSS_MASK_of(_x) ((_x) & 0x7f) 294 #define NFP_NET_CFG_RSS_IPV4 (1 << 8) /* RSS for IPv4 */ 295 #define NFP_NET_CFG_RSS_IPV6 (1 << 9) /* RSS for IPv6 */ 296 #define NFP_NET_CFG_RSS_IPV4_TCP (1 << 10) /* RSS for IPv4/TCP */ 297 #define NFP_NET_CFG_RSS_IPV4_UDP (1 << 11) /* RSS for IPv4/UDP */ 298 #define NFP_NET_CFG_RSS_IPV6_TCP (1 << 12) /* RSS for IPv6/TCP */ 299 #define NFP_NET_CFG_RSS_IPV6_UDP (1 << 13) /* RSS for IPv6/UDP */ 300 #define NFP_NET_CFG_RSS_HFUNC 0xff000000 301 #define NFP_NET_CFG_RSS_TOEPLITZ (1 << 24) /* Use Toeplitz hash */ 302 #define NFP_NET_CFG_RSS_XOR (1 << 25) /* Use XOR as hash */ 303 #define NFP_NET_CFG_RSS_CRC32 (1 << 26) /* Use CRC32 as hash */ 304 #define NFP_NET_CFG_RSS_HFUNCS 3 305 #define NFP_NET_CFG_RSS_KEY (NFP_NET_CFG_RSS_BASE + 0x4) 306 #define NFP_NET_CFG_RSS_KEY_SZ 0x28 307 #define NFP_NET_CFG_RSS_ITBL (NFP_NET_CFG_RSS_BASE + 0x4 + \ 308 NFP_NET_CFG_RSS_KEY_SZ) 309 #define NFP_NET_CFG_RSS_ITBL_SZ 0x80 310 311 /** 312 * TX ring configuration (0x200 - 0x800) 313 * %NFP_NET_CFG_TXR_BASE: Base offset for TX ring configuration 314 * %NFP_NET_CFG_TXR_ADDR: Per TX ring DMA address (8B entries) 315 * %NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries) 316 * %NFP_NET_CFG_TXR_SZ: Per TX ring ring size (1B entries) 317 * %NFP_NET_CFG_TXR_VEC: Per TX ring MSI-X table entry (1B entries) 318 * %NFP_NET_CFG_TXR_PRIO: Per TX ring priority (1B entries) 319 * %NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation packet 320 */ 321 #define NFP_NET_CFG_TXR_BASE 0x0200 322 #define NFP_NET_CFG_TXR_ADDR(_x) (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8)) 323 #define NFP_NET_CFG_TXR_WB_ADDR(_x) (NFP_NET_CFG_TXR_BASE + 0x200 + \ 324 ((_x) * 0x8)) 325 #define NFP_NET_CFG_TXR_SZ(_x) (NFP_NET_CFG_TXR_BASE + 0x400 + (_x)) 326 #define NFP_NET_CFG_TXR_VEC(_x) (NFP_NET_CFG_TXR_BASE + 0x440 + (_x)) 327 #define NFP_NET_CFG_TXR_PRIO(_x) (NFP_NET_CFG_TXR_BASE + 0x480 + (_x)) 328 #define NFP_NET_CFG_TXR_IRQ_MOD(_x) (NFP_NET_CFG_TXR_BASE + 0x500 + \ 329 ((_x) * 0x4)) 330 331 /** 332 * RX ring configuration (0x0800 - 0x0c00) 333 * %NFP_NET_CFG_RXR_BASE: Base offset for RX ring configuration 334 * %NFP_NET_CFG_RXR_ADDR: Per RX ring DMA address (8B entries) 335 * %NFP_NET_CFG_RXR_SZ: Per RX ring ring size (1B entries) 336 * %NFP_NET_CFG_RXR_VEC: Per RX ring MSI-X table entry (1B entries) 337 * %NFP_NET_CFG_RXR_PRIO: Per RX ring priority (1B entries) 338 * %NFP_NET_CFG_RXR_IRQ_MOD: Per RX ring interrupt moderation (4B entries) 339 */ 340 #define NFP_NET_CFG_RXR_BASE 0x0800 341 #define NFP_NET_CFG_RXR_ADDR(_x) (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8)) 342 #define NFP_NET_CFG_RXR_SZ(_x) (NFP_NET_CFG_RXR_BASE + 0x200 + (_x)) 343 #define NFP_NET_CFG_RXR_VEC(_x) (NFP_NET_CFG_RXR_BASE + 0x240 + (_x)) 344 #define NFP_NET_CFG_RXR_PRIO(_x) (NFP_NET_CFG_RXR_BASE + 0x280 + (_x)) 345 #define NFP_NET_CFG_RXR_IRQ_MOD(_x) (NFP_NET_CFG_RXR_BASE + 0x300 + \ 346 ((_x) * 0x4)) 347 348 /** 349 * Interrupt Control/Cause registers (0x0c00 - 0x0d00) 350 * These registers are only used when MSI-X auto-masking is not 351 * enabled (%NFP_NET_CFG_CTRL_MSIXAUTO not set). The array is index 352 * by MSI-X entry and are 1B in size. If an entry is zero, the 353 * corresponding entry is enabled. If the FW generates an interrupt, 354 * it writes a cause into the corresponding field. This also masks 355 * the MSI-X entry and the host driver must clear the register to 356 * re-enable the interrupt. 357 */ 358 #define NFP_NET_CFG_ICR_BASE 0x0c00 359 #define NFP_NET_CFG_ICR(_x) (NFP_NET_CFG_ICR_BASE + (_x)) 360 #define NFP_NET_CFG_ICR_UNMASKED 0x0 361 #define NFP_NET_CFG_ICR_RXTX 0x1 362 #define NFP_NET_CFG_ICR_LSC 0x2 363 364 /** 365 * General device stats (0x0d00 - 0x0d90) 366 * all counters are 64bit. 367 */ 368 #define NFP_NET_CFG_STATS_BASE 0x0d00 369 #define NFP_NET_CFG_STATS_RX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x00) 370 #define NFP_NET_CFG_STATS_RX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x08) 371 #define NFP_NET_CFG_STATS_RX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x10) 372 #define NFP_NET_CFG_STATS_RX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x18) 373 #define NFP_NET_CFG_STATS_RX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x20) 374 #define NFP_NET_CFG_STATS_RX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x28) 375 #define NFP_NET_CFG_STATS_RX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x30) 376 #define NFP_NET_CFG_STATS_RX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x38) 377 #define NFP_NET_CFG_STATS_RX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x40) 378 379 #define NFP_NET_CFG_STATS_TX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x48) 380 #define NFP_NET_CFG_STATS_TX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x50) 381 #define NFP_NET_CFG_STATS_TX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x58) 382 #define NFP_NET_CFG_STATS_TX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x60) 383 #define NFP_NET_CFG_STATS_TX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x68) 384 #define NFP_NET_CFG_STATS_TX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x70) 385 #define NFP_NET_CFG_STATS_TX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x78) 386 #define NFP_NET_CFG_STATS_TX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x80) 387 #define NFP_NET_CFG_STATS_TX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x88) 388 389 #define NFP_NET_CFG_STATS_APP0_FRAMES (NFP_NET_CFG_STATS_BASE + 0x90) 390 #define NFP_NET_CFG_STATS_APP0_BYTES (NFP_NET_CFG_STATS_BASE + 0x98) 391 #define NFP_NET_CFG_STATS_APP1_FRAMES (NFP_NET_CFG_STATS_BASE + 0xa0) 392 #define NFP_NET_CFG_STATS_APP1_BYTES (NFP_NET_CFG_STATS_BASE + 0xa8) 393 #define NFP_NET_CFG_STATS_APP2_FRAMES (NFP_NET_CFG_STATS_BASE + 0xb0) 394 #define NFP_NET_CFG_STATS_APP2_BYTES (NFP_NET_CFG_STATS_BASE + 0xb8) 395 #define NFP_NET_CFG_STATS_APP3_FRAMES (NFP_NET_CFG_STATS_BASE + 0xc0) 396 #define NFP_NET_CFG_STATS_APP3_BYTES (NFP_NET_CFG_STATS_BASE + 0xc8) 397 398 /** 399 * Per ring stats (0x1000 - 0x1800) 400 * options, 64bit per entry 401 * %NFP_NET_CFG_TXR_STATS: TX ring statistics (Packet and Byte count) 402 * %NFP_NET_CFG_RXR_STATS: RX ring statistics (Packet and Byte count) 403 */ 404 #define NFP_NET_CFG_TXR_STATS_BASE 0x1000 405 #define NFP_NET_CFG_TXR_STATS(_x) (NFP_NET_CFG_TXR_STATS_BASE + \ 406 ((_x) * 0x10)) 407 #define NFP_NET_CFG_RXR_STATS_BASE 0x1400 408 #define NFP_NET_CFG_RXR_STATS(_x) (NFP_NET_CFG_RXR_STATS_BASE + \ 409 ((_x) * 0x10)) 410 411 /** 412 * General use mailbox area (0x1800 - 0x19ff) 413 * 4B used for update command and 4B return code 414 * followed by a max of 504B of variable length value 415 */ 416 #define NFP_NET_CFG_MBOX_BASE 0x1800 417 #define NFP_NET_CFG_MBOX_VAL_MAX_SZ 0x1F8 418 419 #define NFP_NET_CFG_MBOX_SIMPLE_CMD 0x0 420 #define NFP_NET_CFG_MBOX_SIMPLE_RET 0x4 421 #define NFP_NET_CFG_MBOX_SIMPLE_VAL 0x8 422 #define NFP_NET_CFG_MBOX_SIMPLE_LEN 0x12 423 424 #define NFP_NET_CFG_MBOX_CMD_CTAG_FILTER_ADD 1 425 #define NFP_NET_CFG_MBOX_CMD_CTAG_FILTER_KILL 2 426 427 /** 428 * VLAN filtering using general use mailbox 429 * %NFP_NET_CFG_VLAN_FILTER: Base address of VLAN filter mailbox 430 * %NFP_NET_CFG_VLAN_FILTER_VID: VLAN ID to filter 431 * %NFP_NET_CFG_VLAN_FILTER_PROTO: VLAN proto to filter 432 * %NFP_NET_CFG_VXLAN_SZ: Size of the VLAN filter mailbox in bytes 433 */ 434 #define NFP_NET_CFG_VLAN_FILTER NFP_NET_CFG_MBOX_SIMPLE_VAL 435 #define NFP_NET_CFG_VLAN_FILTER_VID NFP_NET_CFG_VLAN_FILTER 436 #define NFP_NET_CFG_VLAN_FILTER_PROTO (NFP_NET_CFG_VLAN_FILTER + 2) 437 #define NFP_NET_CFG_VLAN_FILTER_SZ 0x0004 438 439 /** 440 * TLV capabilities 441 * %NFP_NET_CFG_TLV_TYPE: Offset of type within the TLV 442 * %NFP_NET_CFG_TLV_TYPE_REQUIRED: Driver must be able to parse the TLV 443 * %NFP_NET_CFG_TLV_LENGTH: Offset of length within the TLV 444 * %NFP_NET_CFG_TLV_LENGTH_INC: TLV length increments 445 * %NFP_NET_CFG_TLV_VALUE: Offset of value with the TLV 446 * 447 * List of simple TLV structures, first one starts at %NFP_NET_CFG_TLV_BASE. 448 * Last structure must be of type %NFP_NET_CFG_TLV_TYPE_END. Presence of TLVs 449 * is indicated by %NFP_NET_CFG_TLV_BASE being non-zero. TLV structures may 450 * fill the entire remainder of the BAR or be shorter. FW must make sure TLVs 451 * don't conflict with other features which allocate space beyond 452 * %NFP_NET_CFG_TLV_BASE. %NFP_NET_CFG_TLV_TYPE_RESERVED should be used to wrap 453 * space used by such features. 454 * Note that the 4 byte TLV header is not counted in %NFP_NET_CFG_TLV_LENGTH. 455 */ 456 #define NFP_NET_CFG_TLV_TYPE 0x00 457 #define NFP_NET_CFG_TLV_TYPE_REQUIRED 0x8000 458 #define NFP_NET_CFG_TLV_LENGTH 0x02 459 #define NFP_NET_CFG_TLV_LENGTH_INC 4 460 #define NFP_NET_CFG_TLV_VALUE 0x04 461 462 #define NFP_NET_CFG_TLV_HEADER_REQUIRED 0x80000000 463 #define NFP_NET_CFG_TLV_HEADER_TYPE 0x7fff0000 464 #define NFP_NET_CFG_TLV_HEADER_LENGTH 0x0000ffff 465 466 /** 467 * Capability TLV types 468 * 469 * %NFP_NET_CFG_TLV_TYPE_UNKNOWN: 470 * Special TLV type to catch bugs, should never be encountered. Drivers should 471 * treat encountering this type as error and refuse to probe. 472 * 473 * %NFP_NET_CFG_TLV_TYPE_RESERVED: 474 * Reserved space, may contain legacy fixed-offset fields, or be used for 475 * padding. The use of this type should be otherwise avoided. 476 * 477 * %NFP_NET_CFG_TLV_TYPE_END: 478 * Empty, end of TLV list. Must be the last TLV. Drivers will stop processing 479 * further TLVs when encountered. 480 * 481 * %NFP_NET_CFG_TLV_TYPE_ME_FREQ: 482 * Single word, ME frequency in MHz as used in calculation for 483 * %NFP_NET_CFG_RXR_IRQ_MOD and %NFP_NET_CFG_TXR_IRQ_MOD. 484 * 485 * %NFP_NET_CFG_TLV_TYPE_MBOX: 486 * Variable, mailbox area. Overwrites the default location which is 487 * %NFP_NET_CFG_MBOX_BASE and length %NFP_NET_CFG_MBOX_VAL_MAX_SZ. 488 */ 489 #define NFP_NET_CFG_TLV_TYPE_UNKNOWN 0 490 #define NFP_NET_CFG_TLV_TYPE_RESERVED 1 491 #define NFP_NET_CFG_TLV_TYPE_END 2 492 #define NFP_NET_CFG_TLV_TYPE_ME_FREQ 3 493 #define NFP_NET_CFG_TLV_TYPE_MBOX 4 494 495 struct device; 496 497 /** 498 * struct nfp_net_tlv_caps - parsed control BAR TLV capabilities 499 * @me_freq_mhz: ME clock_freq (MHz) 500 * @mbox_off: vNIC mailbox area offset 501 * @mbox_len: vNIC mailbox area length 502 */ 503 struct nfp_net_tlv_caps { 504 u32 me_freq_mhz; 505 unsigned int mbox_off; 506 unsigned int mbox_len; 507 }; 508 509 int nfp_net_tlv_caps_parse(struct device *dev, u8 __iomem *ctrl_mem, 510 struct nfp_net_tlv_caps *caps); 511 512 static inline bool nfp_net_has_mbox(struct nfp_net_tlv_caps *caps) 513 { 514 return caps->mbox_len >= NFP_NET_CFG_MBOX_SIMPLE_LEN; 515 } 516 517 #endif /* _NFP_NET_CTRL_H_ */ 518