1 /* 2 * Copyright (C) 2015 Netronome Systems, Inc. 3 * 4 * This software is dual licensed under the GNU General License Version 2, 5 * June 1991 as shown in the file COPYING in the top-level directory of this 6 * source tree or the BSD 2-Clause License provided below. You have the 7 * option to license this software under the complete terms of either license. 8 * 9 * The BSD 2-Clause License: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * 2. Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 /* 35 * nfp_net_ctrl.h 36 * Netronome network device driver: Control BAR layout 37 * Authors: Jakub Kicinski <jakub.kicinski@netronome.com> 38 * Jason McMullan <jason.mcmullan@netronome.com> 39 * Rolf Neugebauer <rolf.neugebauer@netronome.com> 40 * Brad Petrus <brad.petrus@netronome.com> 41 */ 42 43 #ifndef _NFP_NET_CTRL_H_ 44 #define _NFP_NET_CTRL_H_ 45 46 /* IMPORTANT: This header file is shared with the FW, 47 * no OS specific constructs, please! 48 */ 49 50 /** 51 * Configuration BAR size. 52 * 53 * The configuration BAR is 8K in size, but on the NFP6000, due to 54 * THB-350, 32k needs to be reserved. 55 */ 56 #define NFP_NET_CFG_BAR_SZ (32 * 1024) 57 58 /** 59 * Offset in Freelist buffer where packet starts on RX 60 */ 61 #define NFP_NET_RX_OFFSET 32 62 63 /** 64 * Maximum header size supported for LSO frames 65 */ 66 #define NFP_NET_LSO_MAX_HDR_SZ 255 67 68 /** 69 * Hash type pre-pended when a RSS hash was computed 70 */ 71 #define NFP_NET_RSS_NONE 0 72 #define NFP_NET_RSS_IPV4 1 73 #define NFP_NET_RSS_IPV6 2 74 #define NFP_NET_RSS_IPV6_EX 3 75 #define NFP_NET_RSS_IPV4_TCP 4 76 #define NFP_NET_RSS_IPV6_TCP 5 77 #define NFP_NET_RSS_IPV6_EX_TCP 6 78 #define NFP_NET_RSS_IPV4_UDP 7 79 #define NFP_NET_RSS_IPV6_UDP 8 80 #define NFP_NET_RSS_IPV6_EX_UDP 9 81 82 /** 83 * @NFP_NET_TXR_MAX: Maximum number of TX rings 84 * @NFP_NET_RXR_MAX: Maximum number of RX rings 85 */ 86 #define NFP_NET_TXR_MAX 64 87 #define NFP_NET_RXR_MAX 64 88 89 /** 90 * Read/Write config words (0x0000 - 0x002c) 91 * @NFP_NET_CFG_CTRL: Global control 92 * @NFP_NET_CFG_UPDATE: Indicate which fields are updated 93 * @NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings 94 * @NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings 95 * @NFP_NET_CFG_MTU: Set MTU size 96 * @NFP_NET_CFG_FLBUFSZ: Set freelist buffer size (must be larger than MTU) 97 * @NFP_NET_CFG_EXN: MSI-X table entry for exceptions 98 * @NFP_NET_CFG_LSC: MSI-X table entry for link state changes 99 * @NFP_NET_CFG_MACADDR: MAC address 100 * 101 * TODO: 102 * - define Error details in UPDATE 103 */ 104 #define NFP_NET_CFG_CTRL 0x0000 105 #define NFP_NET_CFG_CTRL_ENABLE (0x1 << 0) /* Global enable */ 106 #define NFP_NET_CFG_CTRL_PROMISC (0x1 << 1) /* Enable Promisc mode */ 107 #define NFP_NET_CFG_CTRL_L2BC (0x1 << 2) /* Allow L2 Broadcast */ 108 #define NFP_NET_CFG_CTRL_L2MC (0x1 << 3) /* Allow L2 Multicast */ 109 #define NFP_NET_CFG_CTRL_RXCSUM (0x1 << 4) /* Enable RX Checksum */ 110 #define NFP_NET_CFG_CTRL_TXCSUM (0x1 << 5) /* Enable TX Checksum */ 111 #define NFP_NET_CFG_CTRL_RXVLAN (0x1 << 6) /* Enable VLAN strip */ 112 #define NFP_NET_CFG_CTRL_TXVLAN (0x1 << 7) /* Enable VLAN insert */ 113 #define NFP_NET_CFG_CTRL_SCATTER (0x1 << 8) /* Scatter DMA */ 114 #define NFP_NET_CFG_CTRL_GATHER (0x1 << 9) /* Gather DMA */ 115 #define NFP_NET_CFG_CTRL_LSO (0x1 << 10) /* LSO/TSO */ 116 #define NFP_NET_CFG_CTRL_RINGCFG (0x1 << 16) /* Ring runtime changes */ 117 #define NFP_NET_CFG_CTRL_RSS (0x1 << 17) /* RSS */ 118 #define NFP_NET_CFG_CTRL_IRQMOD (0x1 << 18) /* Interrupt moderation */ 119 #define NFP_NET_CFG_CTRL_RINGPRIO (0x1 << 19) /* Ring priorities */ 120 #define NFP_NET_CFG_CTRL_MSIXAUTO (0x1 << 20) /* MSI-X auto-masking */ 121 #define NFP_NET_CFG_CTRL_TXRWB (0x1 << 21) /* Write-back of TX ring*/ 122 #define NFP_NET_CFG_CTRL_L2SWITCH (0x1 << 22) /* L2 Switch */ 123 #define NFP_NET_CFG_CTRL_L2SWITCH_LOCAL (0x1 << 23) /* Switch to local */ 124 #define NFP_NET_CFG_CTRL_VXLAN (0x1 << 24) /* VXLAN tunnel support */ 125 #define NFP_NET_CFG_CTRL_NVGRE (0x1 << 25) /* NVGRE tunnel support */ 126 #define NFP_NET_CFG_UPDATE 0x0004 127 #define NFP_NET_CFG_UPDATE_GEN (0x1 << 0) /* General update */ 128 #define NFP_NET_CFG_UPDATE_RING (0x1 << 1) /* Ring config change */ 129 #define NFP_NET_CFG_UPDATE_RSS (0x1 << 2) /* RSS config change */ 130 #define NFP_NET_CFG_UPDATE_TXRPRIO (0x1 << 3) /* TX Ring prio change */ 131 #define NFP_NET_CFG_UPDATE_RXRPRIO (0x1 << 4) /* RX Ring prio change */ 132 #define NFP_NET_CFG_UPDATE_MSIX (0x1 << 5) /* MSI-X change */ 133 #define NFP_NET_CFG_UPDATE_L2SWITCH (0x1 << 6) /* Switch changes */ 134 #define NFP_NET_CFG_UPDATE_RESET (0x1 << 7) /* Update due to FLR */ 135 #define NFP_NET_CFG_UPDATE_IRQMOD (0x1 << 8) /* IRQ mod change */ 136 #define NFP_NET_CFG_UPDATE_VXLAN (0x1 << 9) /* VXLAN port change */ 137 #define NFP_NET_CFG_UPDATE_ERR (0x1 << 31) /* A error occurred */ 138 #define NFP_NET_CFG_TXRS_ENABLE 0x0008 139 #define NFP_NET_CFG_RXRS_ENABLE 0x0010 140 #define NFP_NET_CFG_MTU 0x0018 141 #define NFP_NET_CFG_FLBUFSZ 0x001c 142 #define NFP_NET_CFG_EXN 0x001f 143 #define NFP_NET_CFG_LSC 0x0020 144 #define NFP_NET_CFG_MACADDR 0x0024 145 146 /** 147 * Read-only words (0x0030 - 0x0050): 148 * @NFP_NET_CFG_VERSION: Firmware version number 149 * @NFP_NET_CFG_STS: Status 150 * @NFP_NET_CFG_CAP: Capabilities (same bits as @NFP_NET_CFG_CTRL) 151 * @NFP_NET_CFG_MAX_TXRINGS: Maximum number of TX rings 152 * @NFP_NET_CFG_MAX_RXRINGS: Maximum number of RX rings 153 * @NFP_NET_CFG_MAX_MTU: Maximum support MTU 154 * @NFP_NET_CFG_START_TXQ: Start Queue Control Queue to use for TX (PF only) 155 * @NFP_NET_CFG_START_RXQ: Start Queue Control Queue to use for RX (PF only) 156 * 157 * TODO: 158 * - define more STS bits 159 */ 160 #define NFP_NET_CFG_VERSION 0x0030 161 #define NFP_NET_CFG_VERSION_RESERVED_MASK (0xff << 24) 162 #define NFP_NET_CFG_VERSION_CLASS_MASK (0xff << 16) 163 #define NFP_NET_CFG_VERSION_CLASS(x) (((x) & 0xff) << 16) 164 #define NFP_NET_CFG_VERSION_CLASS_GENERIC 0 165 #define NFP_NET_CFG_VERSION_MAJOR_MASK (0xff << 8) 166 #define NFP_NET_CFG_VERSION_MAJOR(x) (((x) & 0xff) << 8) 167 #define NFP_NET_CFG_VERSION_MINOR_MASK (0xff << 0) 168 #define NFP_NET_CFG_VERSION_MINOR(x) (((x) & 0xff) << 0) 169 #define NFP_NET_CFG_STS 0x0034 170 #define NFP_NET_CFG_STS_LINK (0x1 << 0) /* Link up or down */ 171 #define NFP_NET_CFG_CAP 0x0038 172 #define NFP_NET_CFG_MAX_TXRINGS 0x003c 173 #define NFP_NET_CFG_MAX_RXRINGS 0x0040 174 #define NFP_NET_CFG_MAX_MTU 0x0044 175 /* Next two words are being used by VFs for solving THB350 issue */ 176 #define NFP_NET_CFG_START_TXQ 0x0048 177 #define NFP_NET_CFG_START_RXQ 0x004c 178 179 /** 180 * NFP-3200 workaround (0x0050 - 0x0058) 181 * @NFP_NET_CFG_SPARE_ADDR: DMA address for ME code to use (e.g. YDS-155 fix) 182 */ 183 #define NFP_NET_CFG_SPARE_ADDR 0x0050 184 /** 185 * NFP6000/NFP4000 - Prepend configuration 186 */ 187 #define NFP_NET_CFG_RX_OFFSET 0x0050 188 #define NFP_NET_CFG_RX_OFFSET_DYNAMIC 0 /* Prepend mode */ 189 190 /** 191 * NFP6000/NFP4000 - VXLAN/UDP encap configuration 192 * @NFP_NET_CFG_VXLAN_PORT: Base address of table of tunnels' UDP dst ports 193 * @NFP_NET_CFG_VXLAN_SZ: Size of the UDP port table in bytes 194 */ 195 #define NFP_NET_CFG_VXLAN_PORT 0x0060 196 #define NFP_NET_CFG_VXLAN_SZ 0x0008 197 198 /** 199 * 64B reserved for future use (0x0080 - 0x00c0) 200 */ 201 #define NFP_NET_CFG_RESERVED 0x0080 202 #define NFP_NET_CFG_RESERVED_SZ 0x0040 203 204 /** 205 * RSS configuration (0x0100 - 0x01ac): 206 * Used only when NFP_NET_CFG_CTRL_RSS is enabled 207 * @NFP_NET_CFG_RSS_CFG: RSS configuration word 208 * @NFP_NET_CFG_RSS_KEY: RSS "secret" key 209 * @NFP_NET_CFG_RSS_ITBL: RSS indirection table 210 */ 211 #define NFP_NET_CFG_RSS_BASE 0x0100 212 #define NFP_NET_CFG_RSS_CTRL NFP_NET_CFG_RSS_BASE 213 #define NFP_NET_CFG_RSS_MASK (0x7f) 214 #define NFP_NET_CFG_RSS_MASK_of(_x) ((_x) & 0x7f) 215 #define NFP_NET_CFG_RSS_IPV4 (1 << 8) /* RSS for IPv4 */ 216 #define NFP_NET_CFG_RSS_IPV6 (1 << 9) /* RSS for IPv6 */ 217 #define NFP_NET_CFG_RSS_IPV4_TCP (1 << 10) /* RSS for IPv4/TCP */ 218 #define NFP_NET_CFG_RSS_IPV4_UDP (1 << 11) /* RSS for IPv4/UDP */ 219 #define NFP_NET_CFG_RSS_IPV6_TCP (1 << 12) /* RSS for IPv6/TCP */ 220 #define NFP_NET_CFG_RSS_IPV6_UDP (1 << 13) /* RSS for IPv6/UDP */ 221 #define NFP_NET_CFG_RSS_TOEPLITZ (1 << 24) /* Use Toeplitz hash */ 222 #define NFP_NET_CFG_RSS_KEY (NFP_NET_CFG_RSS_BASE + 0x4) 223 #define NFP_NET_CFG_RSS_KEY_SZ 0x28 224 #define NFP_NET_CFG_RSS_ITBL (NFP_NET_CFG_RSS_BASE + 0x4 + \ 225 NFP_NET_CFG_RSS_KEY_SZ) 226 #define NFP_NET_CFG_RSS_ITBL_SZ 0x80 227 228 /** 229 * TX ring configuration (0x200 - 0x800) 230 * @NFP_NET_CFG_TXR_BASE: Base offset for TX ring configuration 231 * @NFP_NET_CFG_TXR_ADDR: Per TX ring DMA address (8B entries) 232 * @NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries) 233 * @NFP_NET_CFG_TXR_SZ: Per TX ring ring size (1B entries) 234 * @NFP_NET_CFG_TXR_VEC: Per TX ring MSI-X table entry (1B entries) 235 * @NFP_NET_CFG_TXR_PRIO: Per TX ring priority (1B entries) 236 * @NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation packet 237 */ 238 #define NFP_NET_CFG_TXR_BASE 0x0200 239 #define NFP_NET_CFG_TXR_ADDR(_x) (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8)) 240 #define NFP_NET_CFG_TXR_WB_ADDR(_x) (NFP_NET_CFG_TXR_BASE + 0x200 + \ 241 ((_x) * 0x8)) 242 #define NFP_NET_CFG_TXR_SZ(_x) (NFP_NET_CFG_TXR_BASE + 0x400 + (_x)) 243 #define NFP_NET_CFG_TXR_VEC(_x) (NFP_NET_CFG_TXR_BASE + 0x440 + (_x)) 244 #define NFP_NET_CFG_TXR_PRIO(_x) (NFP_NET_CFG_TXR_BASE + 0x480 + (_x)) 245 #define NFP_NET_CFG_TXR_IRQ_MOD(_x) (NFP_NET_CFG_TXR_BASE + 0x500 + \ 246 ((_x) * 0x4)) 247 248 /** 249 * RX ring configuration (0x0800 - 0x0c00) 250 * @NFP_NET_CFG_RXR_BASE: Base offset for RX ring configuration 251 * @NFP_NET_CFG_RXR_ADDR: Per RX ring DMA address (8B entries) 252 * @NFP_NET_CFG_RXR_SZ: Per RX ring ring size (1B entries) 253 * @NFP_NET_CFG_RXR_VEC: Per RX ring MSI-X table entry (1B entries) 254 * @NFP_NET_CFG_RXR_PRIO: Per RX ring priority (1B entries) 255 * @NFP_NET_CFG_RXR_IRQ_MOD: Per RX ring interrupt moderation (4B entries) 256 */ 257 #define NFP_NET_CFG_RXR_BASE 0x0800 258 #define NFP_NET_CFG_RXR_ADDR(_x) (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8)) 259 #define NFP_NET_CFG_RXR_SZ(_x) (NFP_NET_CFG_RXR_BASE + 0x200 + (_x)) 260 #define NFP_NET_CFG_RXR_VEC(_x) (NFP_NET_CFG_RXR_BASE + 0x240 + (_x)) 261 #define NFP_NET_CFG_RXR_PRIO(_x) (NFP_NET_CFG_RXR_BASE + 0x280 + (_x)) 262 #define NFP_NET_CFG_RXR_IRQ_MOD(_x) (NFP_NET_CFG_RXR_BASE + 0x300 + \ 263 ((_x) * 0x4)) 264 265 /** 266 * Interrupt Control/Cause registers (0x0c00 - 0x0d00) 267 * These registers are only used when MSI-X auto-masking is not 268 * enabled (@NFP_NET_CFG_CTRL_MSIXAUTO not set). The array is index 269 * by MSI-X entry and are 1B in size. If an entry is zero, the 270 * corresponding entry is enabled. If the FW generates an interrupt, 271 * it writes a cause into the corresponding field. This also masks 272 * the MSI-X entry and the host driver must clear the register to 273 * re-enable the interrupt. 274 */ 275 #define NFP_NET_CFG_ICR_BASE 0x0c00 276 #define NFP_NET_CFG_ICR(_x) (NFP_NET_CFG_ICR_BASE + (_x)) 277 #define NFP_NET_CFG_ICR_UNMASKED 0x0 278 #define NFP_NET_CFG_ICR_RXTX 0x1 279 #define NFP_NET_CFG_ICR_LSC 0x2 280 281 /** 282 * General device stats (0x0d00 - 0x0d90) 283 * all counters are 64bit. 284 */ 285 #define NFP_NET_CFG_STATS_BASE 0x0d00 286 #define NFP_NET_CFG_STATS_RX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x00) 287 #define NFP_NET_CFG_STATS_RX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x08) 288 #define NFP_NET_CFG_STATS_RX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x10) 289 #define NFP_NET_CFG_STATS_RX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x18) 290 #define NFP_NET_CFG_STATS_RX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x20) 291 #define NFP_NET_CFG_STATS_RX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x28) 292 #define NFP_NET_CFG_STATS_RX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x30) 293 #define NFP_NET_CFG_STATS_RX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x38) 294 #define NFP_NET_CFG_STATS_RX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x40) 295 296 #define NFP_NET_CFG_STATS_TX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x48) 297 #define NFP_NET_CFG_STATS_TX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x50) 298 #define NFP_NET_CFG_STATS_TX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x58) 299 #define NFP_NET_CFG_STATS_TX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x60) 300 #define NFP_NET_CFG_STATS_TX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x68) 301 #define NFP_NET_CFG_STATS_TX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x70) 302 #define NFP_NET_CFG_STATS_TX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x78) 303 #define NFP_NET_CFG_STATS_TX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x80) 304 #define NFP_NET_CFG_STATS_TX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x88) 305 306 /** 307 * Per ring stats (0x1000 - 0x1800) 308 * options, 64bit per entry 309 * @NFP_NET_CFG_TXR_STATS: TX ring statistics (Packet and Byte count) 310 * @NFP_NET_CFG_RXR_STATS: RX ring statistics (Packet and Byte count) 311 */ 312 #define NFP_NET_CFG_TXR_STATS_BASE 0x1000 313 #define NFP_NET_CFG_TXR_STATS(_x) (NFP_NET_CFG_TXR_STATS_BASE + \ 314 ((_x) * 0x10)) 315 #define NFP_NET_CFG_RXR_STATS_BASE 0x1400 316 #define NFP_NET_CFG_RXR_STATS(_x) (NFP_NET_CFG_RXR_STATS_BASE + \ 317 ((_x) * 0x10)) 318 319 #endif /* _NFP_NET_CTRL_H_ */ 320