1 /* 2 * Copyright (C) 2015 Netronome Systems, Inc. 3 * 4 * This software is dual licensed under the GNU General License Version 2, 5 * June 1991 as shown in the file COPYING in the top-level directory of this 6 * source tree or the BSD 2-Clause License provided below. You have the 7 * option to license this software under the complete terms of either license. 8 * 9 * The BSD 2-Clause License: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * 2. Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 /* 35 * nfp_net.h 36 * Declarations for Netronome network device driver. 37 * Authors: Jakub Kicinski <jakub.kicinski@netronome.com> 38 * Jason McMullan <jason.mcmullan@netronome.com> 39 * Rolf Neugebauer <rolf.neugebauer@netronome.com> 40 */ 41 42 #ifndef _NFP_NET_H_ 43 #define _NFP_NET_H_ 44 45 #include <linux/interrupt.h> 46 #include <linux/netdevice.h> 47 #include <linux/pci.h> 48 #include <linux/io-64-nonatomic-hi-lo.h> 49 50 #include "nfp_net_ctrl.h" 51 52 #define nn_err(nn, fmt, args...) netdev_err((nn)->netdev, fmt, ## args) 53 #define nn_warn(nn, fmt, args...) netdev_warn((nn)->netdev, fmt, ## args) 54 #define nn_info(nn, fmt, args...) netdev_info((nn)->netdev, fmt, ## args) 55 #define nn_dbg(nn, fmt, args...) netdev_dbg((nn)->netdev, fmt, ## args) 56 #define nn_warn_ratelimit(nn, fmt, args...) \ 57 do { \ 58 if (unlikely(net_ratelimit())) \ 59 netdev_warn((nn)->netdev, fmt, ## args); \ 60 } while (0) 61 62 /* Max time to wait for NFP to respond on updates (in seconds) */ 63 #define NFP_NET_POLL_TIMEOUT 5 64 65 /* Bar allocation */ 66 #define NFP_NET_CRTL_BAR 0 67 #define NFP_NET_Q0_BAR 2 68 #define NFP_NET_Q1_BAR 4 /* OBSOLETE */ 69 70 /* Max bits in DMA address */ 71 #define NFP_NET_MAX_DMA_BITS 40 72 73 /* Default size for MTU and freelist buffer sizes */ 74 #define NFP_NET_DEFAULT_MTU 1500 75 #define NFP_NET_DEFAULT_RX_BUFSZ 2048 76 77 /* Maximum number of bytes prepended to a packet */ 78 #define NFP_NET_MAX_PREPEND 64 79 80 /* Interrupt definitions */ 81 #define NFP_NET_NON_Q_VECTORS 2 82 #define NFP_NET_IRQ_LSC_IDX 0 83 #define NFP_NET_IRQ_EXN_IDX 1 84 85 /* Queue/Ring definitions */ 86 #define NFP_NET_MAX_TX_RINGS 64 /* Max. # of Tx rings per device */ 87 #define NFP_NET_MAX_RX_RINGS 64 /* Max. # of Rx rings per device */ 88 89 #define NFP_NET_MIN_TX_DESCS 256 /* Min. # of Tx descs per ring */ 90 #define NFP_NET_MIN_RX_DESCS 256 /* Min. # of Rx descs per ring */ 91 #define NFP_NET_MAX_TX_DESCS (256 * 1024) /* Max. # of Tx descs per ring */ 92 #define NFP_NET_MAX_RX_DESCS (256 * 1024) /* Max. # of Rx descs per ring */ 93 94 #define NFP_NET_TX_DESCS_DEFAULT 4096 /* Default # of Tx descs per ring */ 95 #define NFP_NET_RX_DESCS_DEFAULT 4096 /* Default # of Rx descs per ring */ 96 97 #define NFP_NET_FL_BATCH 16 /* Add freelist in this Batch size */ 98 99 /* Offload definitions */ 100 #define NFP_NET_N_VXLAN_PORTS (NFP_NET_CFG_VXLAN_SZ / sizeof(__be16)) 101 102 /* Forward declarations */ 103 struct nfp_net; 104 struct nfp_net_r_vector; 105 106 /* Convenience macro for writing dma address into RX/TX descriptors */ 107 #define nfp_desc_set_dma_addr(desc, dma_addr) \ 108 do { \ 109 __typeof(desc) __d = (desc); \ 110 dma_addr_t __addr = (dma_addr); \ 111 \ 112 __d->dma_addr_lo = cpu_to_le32(lower_32_bits(__addr)); \ 113 __d->dma_addr_hi = upper_32_bits(__addr) & 0xff; \ 114 } while (0) 115 116 /* TX descriptor format */ 117 118 #define PCIE_DESC_TX_EOP BIT(7) 119 #define PCIE_DESC_TX_OFFSET_MASK GENMASK(6, 0) 120 #define PCIE_DESC_TX_MSS_MASK GENMASK(13, 0) 121 122 /* Flags in the host TX descriptor */ 123 #define PCIE_DESC_TX_CSUM BIT(7) 124 #define PCIE_DESC_TX_IP4_CSUM BIT(6) 125 #define PCIE_DESC_TX_TCP_CSUM BIT(5) 126 #define PCIE_DESC_TX_UDP_CSUM BIT(4) 127 #define PCIE_DESC_TX_VLAN BIT(3) 128 #define PCIE_DESC_TX_LSO BIT(2) 129 #define PCIE_DESC_TX_ENCAP BIT(1) 130 #define PCIE_DESC_TX_O_IP4_CSUM BIT(0) 131 132 struct nfp_net_tx_desc { 133 union { 134 struct { 135 u8 dma_addr_hi; /* High bits of host buf address */ 136 __le16 dma_len; /* Length to DMA for this desc */ 137 u8 offset_eop; /* Offset in buf where pkt starts + 138 * highest bit is eop flag. 139 */ 140 __le32 dma_addr_lo; /* Low 32bit of host buf addr */ 141 142 __le16 mss; /* MSS to be used for LSO */ 143 u8 l4_offset; /* LSO, where the L4 data starts */ 144 u8 flags; /* TX Flags, see @PCIE_DESC_TX_* */ 145 146 __le16 vlan; /* VLAN tag to add if indicated */ 147 __le16 data_len; /* Length of frame + meta data */ 148 } __packed; 149 __le32 vals[4]; 150 }; 151 }; 152 153 /** 154 * struct nfp_net_tx_buf - software TX buffer descriptor 155 * @skb: sk_buff associated with this buffer 156 * @dma_addr: DMA mapping address of the buffer 157 * @fidx: Fragment index (-1 for the head and [0..nr_frags-1] for frags) 158 * @pkt_cnt: Number of packets to be produced out of the skb associated 159 * with this buffer (valid only on the head's buffer). 160 * Will be 1 for all non-TSO packets. 161 * @real_len: Number of bytes which to be produced out of the skb (valid only 162 * on the head's buffer). Equal to skb->len for non-TSO packets. 163 */ 164 struct nfp_net_tx_buf { 165 struct sk_buff *skb; 166 dma_addr_t dma_addr; 167 short int fidx; 168 u16 pkt_cnt; 169 u32 real_len; 170 }; 171 172 /** 173 * struct nfp_net_tx_ring - TX ring structure 174 * @r_vec: Back pointer to ring vector structure 175 * @idx: Ring index from Linux's perspective 176 * @qcidx: Queue Controller Peripheral (QCP) queue index for the TX queue 177 * @qcp_q: Pointer to base of the QCP TX queue 178 * @cnt: Size of the queue in number of descriptors 179 * @wr_p: TX ring write pointer (free running) 180 * @rd_p: TX ring read pointer (free running) 181 * @qcp_rd_p: Local copy of QCP TX queue read pointer 182 * @wr_ptr_add: Accumulated number of buffers to add to QCP write pointer 183 * (used for .xmit_more delayed kick) 184 * @txbufs: Array of transmitted TX buffers, to free on transmit 185 * @txds: Virtual address of TX ring in host memory 186 * @dma: DMA address of the TX ring 187 * @size: Size, in bytes, of the TX ring (needed to free) 188 */ 189 struct nfp_net_tx_ring { 190 struct nfp_net_r_vector *r_vec; 191 192 u32 idx; 193 int qcidx; 194 u8 __iomem *qcp_q; 195 196 u32 cnt; 197 u32 wr_p; 198 u32 rd_p; 199 u32 qcp_rd_p; 200 201 u32 wr_ptr_add; 202 203 struct nfp_net_tx_buf *txbufs; 204 struct nfp_net_tx_desc *txds; 205 206 dma_addr_t dma; 207 unsigned int size; 208 } ____cacheline_aligned; 209 210 /* RX and freelist descriptor format */ 211 212 #define PCIE_DESC_RX_DD BIT(7) 213 #define PCIE_DESC_RX_META_LEN_MASK GENMASK(6, 0) 214 215 /* Flags in the RX descriptor */ 216 #define PCIE_DESC_RX_RSS cpu_to_le16(BIT(15)) 217 #define PCIE_DESC_RX_I_IP4_CSUM cpu_to_le16(BIT(14)) 218 #define PCIE_DESC_RX_I_IP4_CSUM_OK cpu_to_le16(BIT(13)) 219 #define PCIE_DESC_RX_I_TCP_CSUM cpu_to_le16(BIT(12)) 220 #define PCIE_DESC_RX_I_TCP_CSUM_OK cpu_to_le16(BIT(11)) 221 #define PCIE_DESC_RX_I_UDP_CSUM cpu_to_le16(BIT(10)) 222 #define PCIE_DESC_RX_I_UDP_CSUM_OK cpu_to_le16(BIT(9)) 223 #define PCIE_DESC_RX_SPARE cpu_to_le16(BIT(8)) 224 #define PCIE_DESC_RX_EOP cpu_to_le16(BIT(7)) 225 #define PCIE_DESC_RX_IP4_CSUM cpu_to_le16(BIT(6)) 226 #define PCIE_DESC_RX_IP4_CSUM_OK cpu_to_le16(BIT(5)) 227 #define PCIE_DESC_RX_TCP_CSUM cpu_to_le16(BIT(4)) 228 #define PCIE_DESC_RX_TCP_CSUM_OK cpu_to_le16(BIT(3)) 229 #define PCIE_DESC_RX_UDP_CSUM cpu_to_le16(BIT(2)) 230 #define PCIE_DESC_RX_UDP_CSUM_OK cpu_to_le16(BIT(1)) 231 #define PCIE_DESC_RX_VLAN cpu_to_le16(BIT(0)) 232 233 #define PCIE_DESC_RX_CSUM_ALL (PCIE_DESC_RX_IP4_CSUM | \ 234 PCIE_DESC_RX_TCP_CSUM | \ 235 PCIE_DESC_RX_UDP_CSUM | \ 236 PCIE_DESC_RX_I_IP4_CSUM | \ 237 PCIE_DESC_RX_I_TCP_CSUM | \ 238 PCIE_DESC_RX_I_UDP_CSUM) 239 #define PCIE_DESC_RX_CSUM_OK_SHIFT 1 240 #define __PCIE_DESC_RX_CSUM_ALL le16_to_cpu(PCIE_DESC_RX_CSUM_ALL) 241 #define __PCIE_DESC_RX_CSUM_ALL_OK (__PCIE_DESC_RX_CSUM_ALL >> \ 242 PCIE_DESC_RX_CSUM_OK_SHIFT) 243 244 struct nfp_net_rx_desc { 245 union { 246 struct { 247 u8 dma_addr_hi; /* High bits of the buf address */ 248 __le16 reserved; /* Must be zero */ 249 u8 meta_len_dd; /* Must be zero */ 250 251 __le32 dma_addr_lo; /* Low bits of the buffer address */ 252 } __packed fld; 253 254 struct { 255 __le16 data_len; /* Length of the frame + meta data */ 256 u8 reserved; 257 u8 meta_len_dd; /* Length of meta data prepended + 258 * descriptor done flag. 259 */ 260 261 __le16 flags; /* RX flags. See @PCIE_DESC_RX_* */ 262 __le16 vlan; /* VLAN if stripped */ 263 } __packed rxd; 264 265 __le32 vals[2]; 266 }; 267 }; 268 269 struct nfp_net_rx_hash { 270 __be32 hash_type; 271 __be32 hash; 272 }; 273 274 /** 275 * struct nfp_net_rx_buf - software RX buffer descriptor 276 * @skb: sk_buff associated with this buffer 277 * @dma_addr: DMA mapping address of the buffer 278 */ 279 struct nfp_net_rx_buf { 280 struct sk_buff *skb; 281 dma_addr_t dma_addr; 282 }; 283 284 /** 285 * struct nfp_net_rx_ring - RX ring structure 286 * @r_vec: Back pointer to ring vector structure 287 * @cnt: Size of the queue in number of descriptors 288 * @wr_p: FL/RX ring write pointer (free running) 289 * @rd_p: FL/RX ring read pointer (free running) 290 * @idx: Ring index from Linux's perspective 291 * @fl_qcidx: Queue Controller Peripheral (QCP) queue index for the freelist 292 * @rx_qcidx: Queue Controller Peripheral (QCP) queue index for the RX queue 293 * @qcp_fl: Pointer to base of the QCP freelist queue 294 * @qcp_rx: Pointer to base of the QCP RX queue 295 * @wr_ptr_add: Accumulated number of buffers to add to QCP write pointer 296 * (used for free list batching) 297 * @rxbufs: Array of transmitted FL/RX buffers 298 * @rxds: Virtual address of FL/RX ring in host memory 299 * @dma: DMA address of the FL/RX ring 300 * @size: Size, in bytes, of the FL/RX ring (needed to free) 301 * @bufsz: Buffer allocation size for convenience of management routines 302 * (NOTE: this is in second cache line, do not use on fast path!) 303 */ 304 struct nfp_net_rx_ring { 305 struct nfp_net_r_vector *r_vec; 306 307 u32 cnt; 308 u32 wr_p; 309 u32 rd_p; 310 311 u16 idx; 312 u16 wr_ptr_add; 313 314 int fl_qcidx; 315 int rx_qcidx; 316 u8 __iomem *qcp_fl; 317 u8 __iomem *qcp_rx; 318 319 struct nfp_net_rx_buf *rxbufs; 320 struct nfp_net_rx_desc *rxds; 321 322 dma_addr_t dma; 323 unsigned int size; 324 unsigned int bufsz; 325 } ____cacheline_aligned; 326 327 /** 328 * struct nfp_net_r_vector - Per ring interrupt vector configuration 329 * @nfp_net: Backpointer to nfp_net structure 330 * @napi: NAPI structure for this ring vec 331 * @tx_ring: Pointer to TX ring 332 * @rx_ring: Pointer to RX ring 333 * @irq_idx: Index into MSI-X table 334 * @rx_sync: Seqlock for atomic updates of RX stats 335 * @rx_pkts: Number of received packets 336 * @rx_bytes: Number of received bytes 337 * @rx_drops: Number of packets dropped on RX due to lack of resources 338 * @hw_csum_rx_ok: Counter of packets where the HW checksum was OK 339 * @hw_csum_rx_inner_ok: Counter of packets where the inner HW checksum was OK 340 * @hw_csum_rx_error: Counter of packets with bad checksums 341 * @tx_sync: Seqlock for atomic updates of TX stats 342 * @tx_pkts: Number of Transmitted packets 343 * @tx_bytes: Number of Transmitted bytes 344 * @hw_csum_tx: Counter of packets with TX checksum offload requested 345 * @hw_csum_tx_inner: Counter of inner TX checksum offload requests 346 * @tx_gather: Counter of packets with Gather DMA 347 * @tx_lso: Counter of LSO packets sent 348 * @tx_errors: How many TX errors were encountered 349 * @tx_busy: How often was TX busy (no space)? 350 * @handler: Interrupt handler for this ring vector 351 * @name: Name of the interrupt vector 352 * @affinity_mask: SMP affinity mask for this vector 353 * 354 * This structure ties RX and TX rings to interrupt vectors and a NAPI 355 * context. This currently only supports one RX and TX ring per 356 * interrupt vector but might be extended in the future to allow 357 * association of multiple rings per vector. 358 */ 359 struct nfp_net_r_vector { 360 struct nfp_net *nfp_net; 361 struct napi_struct napi; 362 363 struct nfp_net_tx_ring *tx_ring; 364 struct nfp_net_rx_ring *rx_ring; 365 366 int irq_idx; 367 368 struct u64_stats_sync rx_sync; 369 u64 rx_pkts; 370 u64 rx_bytes; 371 u64 rx_drops; 372 u64 hw_csum_rx_ok; 373 u64 hw_csum_rx_inner_ok; 374 u64 hw_csum_rx_error; 375 376 struct u64_stats_sync tx_sync; 377 u64 tx_pkts; 378 u64 tx_bytes; 379 u64 hw_csum_tx; 380 u64 hw_csum_tx_inner; 381 u64 tx_gather; 382 u64 tx_lso; 383 u64 tx_errors; 384 u64 tx_busy; 385 386 irq_handler_t handler; 387 char name[IFNAMSIZ + 8]; 388 cpumask_t affinity_mask; 389 } ____cacheline_aligned; 390 391 /* Firmware version as it is written in the 32bit value in the BAR */ 392 struct nfp_net_fw_version { 393 u8 minor; 394 u8 major; 395 u8 class; 396 u8 resv; 397 } __packed; 398 399 static inline bool nfp_net_fw_ver_eq(struct nfp_net_fw_version *fw_ver, 400 u8 resv, u8 class, u8 major, u8 minor) 401 { 402 return fw_ver->resv == resv && 403 fw_ver->class == class && 404 fw_ver->major == major && 405 fw_ver->minor == minor; 406 } 407 408 /** 409 * struct nfp_net - NFP network device structure 410 * @pdev: Backpointer to PCI device 411 * @netdev: Backpointer to net_device structure 412 * @nfp_fallback: Is the driver used in fallback mode? 413 * @is_vf: Is the driver attached to a VF? 414 * @is_nfp3200: Is the driver for a NFP-3200 card? 415 * @fw_loaded: Is the firmware loaded? 416 * @ctrl: Local copy of the control register/word. 417 * @fl_bufsz: Currently configured size of the freelist buffers 418 * @rx_offset: Offset in the RX buffers where packet data starts 419 * @cpp: Pointer to the CPP handle 420 * @nfp_dev_cpp: Pointer to the NFP Device handle 421 * @ctrl_area: Pointer to the CPP area for the control BAR 422 * @tx_area: Pointer to the CPP area for the TX queues 423 * @rx_area: Pointer to the CPP area for the FL/RX queues 424 * @fw_ver: Firmware version 425 * @cap: Capabilities advertised by the Firmware 426 * @max_mtu: Maximum support MTU advertised by the Firmware 427 * @rss_cfg: RSS configuration 428 * @rss_key: RSS secret key 429 * @rss_itbl: RSS indirection table 430 * @max_tx_rings: Maximum number of TX rings supported by the Firmware 431 * @max_rx_rings: Maximum number of RX rings supported by the Firmware 432 * @num_tx_rings: Currently configured number of TX rings 433 * @num_rx_rings: Currently configured number of RX rings 434 * @txd_cnt: Size of the TX ring in number of descriptors 435 * @rxd_cnt: Size of the RX ring in number of descriptors 436 * @tx_rings: Array of pre-allocated TX ring structures 437 * @rx_rings: Array of pre-allocated RX ring structures 438 * @num_irqs: Number of allocated interrupt vectors 439 * @num_r_vecs: Number of used ring vectors 440 * @r_vecs: Pre-allocated array of ring vectors 441 * @irq_entries: Pre-allocated array of MSI-X entries 442 * @lsc_handler: Handler for Link State Change interrupt 443 * @lsc_name: Name for Link State Change interrupt 444 * @exn_handler: Handler for Exception interrupt 445 * @exn_name: Name for Exception interrupt 446 * @shared_handler: Handler for shared interrupts 447 * @shared_name: Name for shared interrupt 448 * @me_freq_mhz: ME clock_freq (MHz) 449 * @reconfig_lock: Protects HW reconfiguration request regs/machinery 450 * @reconfig_posted: Pending reconfig bits coming from async sources 451 * @reconfig_timer_active: Timer for reading reconfiguration results is pending 452 * @reconfig_sync_present: Some thread is performing synchronous reconfig 453 * @reconfig_timer: Timer for async reading of reconfig results 454 * @link_up: Is the link up? 455 * @link_status_lock: Protects @link_up and ensures atomicity with BAR reading 456 * @rx_coalesce_usecs: RX interrupt moderation usecs delay parameter 457 * @rx_coalesce_max_frames: RX interrupt moderation frame count parameter 458 * @tx_coalesce_usecs: TX interrupt moderation usecs delay parameter 459 * @tx_coalesce_max_frames: TX interrupt moderation frame count parameter 460 * @vxlan_ports: VXLAN ports for RX inner csum offload communicated to HW 461 * @vxlan_usecnt: IPv4/IPv6 VXLAN port use counts 462 * @qcp_cfg: Pointer to QCP queue used for configuration notification 463 * @ctrl_bar: Pointer to mapped control BAR 464 * @tx_bar: Pointer to mapped TX queues 465 * @rx_bar: Pointer to mapped FL/RX queues 466 * @debugfs_dir: Device directory in debugfs 467 */ 468 struct nfp_net { 469 struct pci_dev *pdev; 470 struct net_device *netdev; 471 472 unsigned nfp_fallback:1; 473 unsigned is_vf:1; 474 unsigned is_nfp3200:1; 475 unsigned fw_loaded:1; 476 477 u32 ctrl; 478 u32 fl_bufsz; 479 480 u32 rx_offset; 481 482 struct nfp_net_tx_ring *tx_rings; 483 struct nfp_net_rx_ring *rx_rings; 484 485 #ifdef CONFIG_PCI_IOV 486 unsigned int num_vfs; 487 struct vf_data_storage *vfinfo; 488 int vf_rate_link_speed; 489 #endif 490 491 struct nfp_cpp *cpp; 492 struct platform_device *nfp_dev_cpp; 493 struct nfp_cpp_area *ctrl_area; 494 struct nfp_cpp_area *tx_area; 495 struct nfp_cpp_area *rx_area; 496 497 struct nfp_net_fw_version fw_ver; 498 u32 cap; 499 u32 max_mtu; 500 501 u32 rss_cfg; 502 u8 rss_key[NFP_NET_CFG_RSS_KEY_SZ]; 503 u8 rss_itbl[NFP_NET_CFG_RSS_ITBL_SZ]; 504 505 int max_tx_rings; 506 int max_rx_rings; 507 508 int num_tx_rings; 509 int num_rx_rings; 510 511 int stride_tx; 512 int stride_rx; 513 514 int txd_cnt; 515 int rxd_cnt; 516 517 u8 num_irqs; 518 u8 num_r_vecs; 519 struct nfp_net_r_vector r_vecs[NFP_NET_MAX_TX_RINGS]; 520 struct msix_entry irq_entries[NFP_NET_NON_Q_VECTORS + 521 NFP_NET_MAX_TX_RINGS]; 522 523 irq_handler_t lsc_handler; 524 char lsc_name[IFNAMSIZ + 8]; 525 526 irq_handler_t exn_handler; 527 char exn_name[IFNAMSIZ + 8]; 528 529 irq_handler_t shared_handler; 530 char shared_name[IFNAMSIZ + 8]; 531 532 u32 me_freq_mhz; 533 534 bool link_up; 535 spinlock_t link_status_lock; 536 537 spinlock_t reconfig_lock; 538 u32 reconfig_posted; 539 bool reconfig_timer_active; 540 bool reconfig_sync_present; 541 struct timer_list reconfig_timer; 542 543 u32 rx_coalesce_usecs; 544 u32 rx_coalesce_max_frames; 545 u32 tx_coalesce_usecs; 546 u32 tx_coalesce_max_frames; 547 548 __be16 vxlan_ports[NFP_NET_N_VXLAN_PORTS]; 549 u8 vxlan_usecnt[NFP_NET_N_VXLAN_PORTS]; 550 551 u8 __iomem *qcp_cfg; 552 553 u8 __iomem *ctrl_bar; 554 u8 __iomem *q_bar; 555 u8 __iomem *tx_bar; 556 u8 __iomem *rx_bar; 557 558 struct dentry *debugfs_dir; 559 }; 560 561 /* Functions to read/write from/to a BAR 562 * Performs any endian conversion necessary. 563 */ 564 static inline void nn_writeb(struct nfp_net *nn, int off, u8 val) 565 { 566 writeb(val, nn->ctrl_bar + off); 567 } 568 569 /* NFP-3200 can't handle 16-bit accesses too well - hence no readw/writew */ 570 571 static inline u32 nn_readl(struct nfp_net *nn, int off) 572 { 573 return readl(nn->ctrl_bar + off); 574 } 575 576 static inline void nn_writel(struct nfp_net *nn, int off, u32 val) 577 { 578 writel(val, nn->ctrl_bar + off); 579 } 580 581 static inline u64 nn_readq(struct nfp_net *nn, int off) 582 { 583 return readq(nn->ctrl_bar + off); 584 } 585 586 static inline void nn_writeq(struct nfp_net *nn, int off, u64 val) 587 { 588 writeq(val, nn->ctrl_bar + off); 589 } 590 591 /* Flush posted PCI writes by reading something without side effects */ 592 static inline void nn_pci_flush(struct nfp_net *nn) 593 { 594 nn_readl(nn, NFP_NET_CFG_VERSION); 595 } 596 597 /* Queue Controller Peripheral access functions and definitions. 598 * 599 * Some of the BARs of the NFP are mapped to portions of the Queue 600 * Controller Peripheral (QCP) address space on the NFP. A QCP queue 601 * has a read and a write pointer (as well as a size and flags, 602 * indicating overflow etc). The QCP offers a number of different 603 * operation on queue pointers, but here we only offer function to 604 * either add to a pointer or to read the pointer value. 605 */ 606 #define NFP_QCP_QUEUE_ADDR_SZ 0x800 607 #define NFP_QCP_QUEUE_OFF(_x) ((_x) * NFP_QCP_QUEUE_ADDR_SZ) 608 #define NFP_QCP_QUEUE_ADD_RPTR 0x0000 609 #define NFP_QCP_QUEUE_ADD_WPTR 0x0004 610 #define NFP_QCP_QUEUE_STS_LO 0x0008 611 #define NFP_QCP_QUEUE_STS_LO_READPTR_mask 0x3ffff 612 #define NFP_QCP_QUEUE_STS_HI 0x000c 613 #define NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask 0x3ffff 614 615 /* The offset of a QCP queues in the PCIe Target (same on NFP3200 and NFP6000 */ 616 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff))) 617 618 /* nfp_qcp_ptr - Read or Write Pointer of a queue */ 619 enum nfp_qcp_ptr { 620 NFP_QCP_READ_PTR = 0, 621 NFP_QCP_WRITE_PTR 622 }; 623 624 /* There appear to be an *undocumented* upper limit on the value which 625 * one can add to a queue and that value is either 0x3f or 0x7f. We 626 * go with 0x3f as a conservative measure. 627 */ 628 #define NFP_QCP_MAX_ADD 0x3f 629 630 static inline void _nfp_qcp_ptr_add(u8 __iomem *q, 631 enum nfp_qcp_ptr ptr, u32 val) 632 { 633 u32 off; 634 635 if (ptr == NFP_QCP_READ_PTR) 636 off = NFP_QCP_QUEUE_ADD_RPTR; 637 else 638 off = NFP_QCP_QUEUE_ADD_WPTR; 639 640 while (val > NFP_QCP_MAX_ADD) { 641 writel(NFP_QCP_MAX_ADD, q + off); 642 val -= NFP_QCP_MAX_ADD; 643 } 644 645 writel(val, q + off); 646 } 647 648 /** 649 * nfp_qcp_rd_ptr_add() - Add the value to the read pointer of a queue 650 * 651 * @q: Base address for queue structure 652 * @val: Value to add to the queue pointer 653 * 654 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed. 655 */ 656 static inline void nfp_qcp_rd_ptr_add(u8 __iomem *q, u32 val) 657 { 658 _nfp_qcp_ptr_add(q, NFP_QCP_READ_PTR, val); 659 } 660 661 /** 662 * nfp_qcp_wr_ptr_add() - Add the value to the write pointer of a queue 663 * 664 * @q: Base address for queue structure 665 * @val: Value to add to the queue pointer 666 * 667 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed. 668 */ 669 static inline void nfp_qcp_wr_ptr_add(u8 __iomem *q, u32 val) 670 { 671 _nfp_qcp_ptr_add(q, NFP_QCP_WRITE_PTR, val); 672 } 673 674 static inline u32 _nfp_qcp_read(u8 __iomem *q, enum nfp_qcp_ptr ptr) 675 { 676 u32 off; 677 u32 val; 678 679 if (ptr == NFP_QCP_READ_PTR) 680 off = NFP_QCP_QUEUE_STS_LO; 681 else 682 off = NFP_QCP_QUEUE_STS_HI; 683 684 val = readl(q + off); 685 686 if (ptr == NFP_QCP_READ_PTR) 687 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask; 688 else 689 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask; 690 } 691 692 /** 693 * nfp_qcp_rd_ptr_read() - Read the current read pointer value for a queue 694 * @q: Base address for queue structure 695 * 696 * Return: Value read. 697 */ 698 static inline u32 nfp_qcp_rd_ptr_read(u8 __iomem *q) 699 { 700 return _nfp_qcp_read(q, NFP_QCP_READ_PTR); 701 } 702 703 /** 704 * nfp_qcp_wr_ptr_read() - Read the current write pointer value for a queue 705 * @q: Base address for queue structure 706 * 707 * Return: Value read. 708 */ 709 static inline u32 nfp_qcp_wr_ptr_read(u8 __iomem *q) 710 { 711 return _nfp_qcp_read(q, NFP_QCP_WRITE_PTR); 712 } 713 714 /* Globals */ 715 extern const char nfp_net_driver_name[]; 716 extern const char nfp_net_driver_version[]; 717 718 /* Prototypes */ 719 void nfp_net_get_fw_version(struct nfp_net_fw_version *fw_ver, 720 void __iomem *ctrl_bar); 721 722 struct nfp_net *nfp_net_netdev_alloc(struct pci_dev *pdev, 723 int max_tx_rings, int max_rx_rings); 724 void nfp_net_netdev_free(struct nfp_net *nn); 725 int nfp_net_netdev_init(struct net_device *netdev); 726 void nfp_net_netdev_clean(struct net_device *netdev); 727 void nfp_net_set_ethtool_ops(struct net_device *netdev); 728 void nfp_net_info(struct nfp_net *nn); 729 int nfp_net_reconfig(struct nfp_net *nn, u32 update); 730 void nfp_net_rss_write_itbl(struct nfp_net *nn); 731 void nfp_net_rss_write_key(struct nfp_net *nn); 732 void nfp_net_coalesce_write_cfg(struct nfp_net *nn); 733 int nfp_net_irqs_alloc(struct nfp_net *nn); 734 void nfp_net_irqs_disable(struct nfp_net *nn); 735 int nfp_net_set_ring_size(struct nfp_net *nn, u32 rxd_cnt, u32 txd_cnt); 736 737 #ifdef CONFIG_NFP_NET_DEBUG 738 void nfp_net_debugfs_create(void); 739 void nfp_net_debugfs_destroy(void); 740 void nfp_net_debugfs_adapter_add(struct nfp_net *nn); 741 void nfp_net_debugfs_adapter_del(struct nfp_net *nn); 742 #else 743 static inline void nfp_net_debugfs_create(void) 744 { 745 } 746 747 static inline void nfp_net_debugfs_destroy(void) 748 { 749 } 750 751 static inline void nfp_net_debugfs_adapter_add(struct nfp_net *nn) 752 { 753 } 754 755 static inline void nfp_net_debugfs_adapter_del(struct nfp_net *nn) 756 { 757 } 758 #endif /* CONFIG_NFP_NET_DEBUG */ 759 760 #endif /* _NFP_NET_H_ */ 761