1 // SPDX-License-Identifier: GPL-2.0-or-later 2 #define VERSION "0.23" 3 /* ns83820.c by Benjamin LaHaise with contributions. 4 * 5 * Questions/comments/discussion to linux-ns83820@kvack.org. 6 * 7 * $Revision: 1.34.2.23 $ 8 * 9 * Copyright 2001 Benjamin LaHaise. 10 * Copyright 2001, 2002 Red Hat. 11 * 12 * Mmmm, chocolate vanilla mocha... 13 * 14 * ChangeLog 15 * ========= 16 * 20010414 0.1 - created 17 * 20010622 0.2 - basic rx and tx. 18 * 20010711 0.3 - added duplex and link state detection support. 19 * 20010713 0.4 - zero copy, no hangs. 20 * 0.5 - 64 bit dma support (davem will hate me for this) 21 * - disable jumbo frames to avoid tx hangs 22 * - work around tx deadlocks on my 1.02 card via 23 * fiddling with TXCFG 24 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64 25 * 20010816 0.7 - misc cleanups 26 * 20010826 0.8 - fix critical zero copy bugs 27 * 0.9 - internal experiment 28 * 20010827 0.10 - fix ia64 unaligned access. 29 * 20010906 0.11 - accept all packets with checksum errors as 30 * otherwise fragments get lost 31 * - fix >> 32 bugs 32 * 0.12 - add statistics counters 33 * - add allmulti/promisc support 34 * 20011009 0.13 - hotplug support, other smaller pci api cleanups 35 * 20011204 0.13a - optical transceiver support added 36 * by Michael Clark <michael@metaparadigm.com> 37 * 20011205 0.13b - call register_netdev earlier in initialization 38 * suppress duplicate link status messages 39 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik 40 * 20011204 0.15 get ppc (big endian) working 41 * 20011218 0.16 various cleanups 42 * 20020310 0.17 speedups 43 * 20020610 0.18 - actually use the pci dma api for highmem 44 * - remove pci latency register fiddling 45 * 0.19 - better bist support 46 * - add ihr and reset_phy parameters 47 * - gmii bus probing 48 * - fix missed txok introduced during performance 49 * tuning 50 * 0.20 - fix stupid RFEN thinko. i am such a smurf. 51 * 20040828 0.21 - add hardware vlan accleration 52 * by Neil Horman <nhorman@redhat.com> 53 * 20050406 0.22 - improved DAC ifdefs from Andi Kleen 54 * - removal of dead code from Adrian Bunk 55 * - fix half duplex collision behaviour 56 * Driver Overview 57 * =============== 58 * 59 * This driver was originally written for the National Semiconductor 60 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully 61 * this code will turn out to be a) clean, b) correct, and c) fast. 62 * With that in mind, I'm aiming to split the code up as much as 63 * reasonably possible. At present there are X major sections that 64 * break down into a) packet receive, b) packet transmit, c) link 65 * management, d) initialization and configuration. Where possible, 66 * these code paths are designed to run in parallel. 67 * 68 * This driver has been tested and found to work with the following 69 * cards (in no particular order): 70 * 71 * Cameo SOHO-GA2000T SOHO-GA2500T 72 * D-Link DGE-500T 73 * PureData PDP8023Z-TG 74 * SMC SMC9452TX SMC9462TX 75 * Netgear GA621 76 * 77 * Special thanks to SMC for providing hardware to test this driver on. 78 * 79 * Reports of success or failure would be greatly appreciated. 80 */ 81 //#define dprintk printk 82 #define dprintk(x...) do { } while (0) 83 84 #include <linux/module.h> 85 #include <linux/moduleparam.h> 86 #include <linux/types.h> 87 #include <linux/pci.h> 88 #include <linux/dma-mapping.h> 89 #include <linux/netdevice.h> 90 #include <linux/etherdevice.h> 91 #include <linux/delay.h> 92 #include <linux/workqueue.h> 93 #include <linux/init.h> 94 #include <linux/interrupt.h> 95 #include <linux/ip.h> /* for iph */ 96 #include <linux/in.h> /* for IPPROTO_... */ 97 #include <linux/compiler.h> 98 #include <linux/prefetch.h> 99 #include <linux/ethtool.h> 100 #include <linux/sched.h> 101 #include <linux/timer.h> 102 #include <linux/if_vlan.h> 103 #include <linux/rtnetlink.h> 104 #include <linux/jiffies.h> 105 #include <linux/slab.h> 106 107 #include <asm/io.h> 108 #include <linux/uaccess.h> 109 110 #define DRV_NAME "ns83820" 111 112 /* Global parameters. See module_param near the bottom. */ 113 static int ihr = 2; 114 static int reset_phy = 0; 115 static int lnksts = 0; /* CFG_LNKSTS bit polarity */ 116 117 /* Dprintk is used for more interesting debug events */ 118 #undef Dprintk 119 #define Dprintk dprintk 120 121 /* tunables */ 122 #define RX_BUF_SIZE 1500 /* 8192 */ 123 #if IS_ENABLED(CONFIG_VLAN_8021Q) 124 #define NS83820_VLAN_ACCEL_SUPPORT 125 #endif 126 127 /* Must not exceed ~65000. */ 128 #define NR_RX_DESC 64 129 #define NR_TX_DESC 128 130 131 /* not tunable */ 132 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */ 133 134 #define MIN_TX_DESC_FREE 8 135 136 /* register defines */ 137 #define CFGCS 0x04 138 139 #define CR_TXE 0x00000001 140 #define CR_TXD 0x00000002 141 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE 142 * The Receive engine skips one descriptor and moves 143 * onto the next one!! */ 144 #define CR_RXE 0x00000004 145 #define CR_RXD 0x00000008 146 #define CR_TXR 0x00000010 147 #define CR_RXR 0x00000020 148 #define CR_SWI 0x00000080 149 #define CR_RST 0x00000100 150 151 #define PTSCR_EEBIST_FAIL 0x00000001 152 #define PTSCR_EEBIST_EN 0x00000002 153 #define PTSCR_EELOAD_EN 0x00000004 154 #define PTSCR_RBIST_FAIL 0x000001b8 155 #define PTSCR_RBIST_DONE 0x00000200 156 #define PTSCR_RBIST_EN 0x00000400 157 #define PTSCR_RBIST_RST 0x00002000 158 159 #define MEAR_EEDI 0x00000001 160 #define MEAR_EEDO 0x00000002 161 #define MEAR_EECLK 0x00000004 162 #define MEAR_EESEL 0x00000008 163 #define MEAR_MDIO 0x00000010 164 #define MEAR_MDDIR 0x00000020 165 #define MEAR_MDC 0x00000040 166 167 #define ISR_TXDESC3 0x40000000 168 #define ISR_TXDESC2 0x20000000 169 #define ISR_TXDESC1 0x10000000 170 #define ISR_TXDESC0 0x08000000 171 #define ISR_RXDESC3 0x04000000 172 #define ISR_RXDESC2 0x02000000 173 #define ISR_RXDESC1 0x01000000 174 #define ISR_RXDESC0 0x00800000 175 #define ISR_TXRCMP 0x00400000 176 #define ISR_RXRCMP 0x00200000 177 #define ISR_DPERR 0x00100000 178 #define ISR_SSERR 0x00080000 179 #define ISR_RMABT 0x00040000 180 #define ISR_RTABT 0x00020000 181 #define ISR_RXSOVR 0x00010000 182 #define ISR_HIBINT 0x00008000 183 #define ISR_PHY 0x00004000 184 #define ISR_PME 0x00002000 185 #define ISR_SWI 0x00001000 186 #define ISR_MIB 0x00000800 187 #define ISR_TXURN 0x00000400 188 #define ISR_TXIDLE 0x00000200 189 #define ISR_TXERR 0x00000100 190 #define ISR_TXDESC 0x00000080 191 #define ISR_TXOK 0x00000040 192 #define ISR_RXORN 0x00000020 193 #define ISR_RXIDLE 0x00000010 194 #define ISR_RXEARLY 0x00000008 195 #define ISR_RXERR 0x00000004 196 #define ISR_RXDESC 0x00000002 197 #define ISR_RXOK 0x00000001 198 199 #define TXCFG_CSI 0x80000000 200 #define TXCFG_HBI 0x40000000 201 #define TXCFG_MLB 0x20000000 202 #define TXCFG_ATP 0x10000000 203 #define TXCFG_ECRETRY 0x00800000 204 #define TXCFG_BRST_DIS 0x00080000 205 #define TXCFG_MXDMA1024 0x00000000 206 #define TXCFG_MXDMA512 0x00700000 207 #define TXCFG_MXDMA256 0x00600000 208 #define TXCFG_MXDMA128 0x00500000 209 #define TXCFG_MXDMA64 0x00400000 210 #define TXCFG_MXDMA32 0x00300000 211 #define TXCFG_MXDMA16 0x00200000 212 #define TXCFG_MXDMA8 0x00100000 213 214 #define CFG_LNKSTS 0x80000000 215 #define CFG_SPDSTS 0x60000000 216 #define CFG_SPDSTS1 0x40000000 217 #define CFG_SPDSTS0 0x20000000 218 #define CFG_DUPSTS 0x10000000 219 #define CFG_TBI_EN 0x01000000 220 #define CFG_MODE_1000 0x00400000 221 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy. 222 * Read the Phy response and then configure the MAC accordingly */ 223 #define CFG_AUTO_1000 0x00200000 224 #define CFG_PINT_CTL 0x001c0000 225 #define CFG_PINT_DUPSTS 0x00100000 226 #define CFG_PINT_LNKSTS 0x00080000 227 #define CFG_PINT_SPDSTS 0x00040000 228 #define CFG_TMRTEST 0x00020000 229 #define CFG_MRM_DIS 0x00010000 230 #define CFG_MWI_DIS 0x00008000 231 #define CFG_T64ADDR 0x00004000 232 #define CFG_PCI64_DET 0x00002000 233 #define CFG_DATA64_EN 0x00001000 234 #define CFG_M64ADDR 0x00000800 235 #define CFG_PHY_RST 0x00000400 236 #define CFG_PHY_DIS 0x00000200 237 #define CFG_EXTSTS_EN 0x00000100 238 #define CFG_REQALG 0x00000080 239 #define CFG_SB 0x00000040 240 #define CFG_POW 0x00000020 241 #define CFG_EXD 0x00000010 242 #define CFG_PESEL 0x00000008 243 #define CFG_BROM_DIS 0x00000004 244 #define CFG_EXT_125 0x00000002 245 #define CFG_BEM 0x00000001 246 247 #define EXTSTS_UDPPKT 0x00200000 248 #define EXTSTS_TCPPKT 0x00080000 249 #define EXTSTS_IPPKT 0x00020000 250 #define EXTSTS_VPKT 0x00010000 251 #define EXTSTS_VTG_MASK 0x0000ffff 252 253 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0)) 254 255 #define MIBC_MIBS 0x00000008 256 #define MIBC_ACLR 0x00000004 257 #define MIBC_FRZ 0x00000002 258 #define MIBC_WRN 0x00000001 259 260 #define PCR_PSEN (1 << 31) 261 #define PCR_PS_MCAST (1 << 30) 262 #define PCR_PS_DA (1 << 29) 263 #define PCR_STHI_8 (3 << 23) 264 #define PCR_STLO_4 (1 << 23) 265 #define PCR_FFHI_8K (3 << 21) 266 #define PCR_FFLO_4K (1 << 21) 267 #define PCR_PAUSE_CNT 0xFFFE 268 269 #define RXCFG_AEP 0x80000000 270 #define RXCFG_ARP 0x40000000 271 #define RXCFG_STRIPCRC 0x20000000 272 #define RXCFG_RX_FD 0x10000000 273 #define RXCFG_ALP 0x08000000 274 #define RXCFG_AIRL 0x04000000 275 #define RXCFG_MXDMA512 0x00700000 276 #define RXCFG_DRTH 0x0000003e 277 #define RXCFG_DRTH0 0x00000002 278 279 #define RFCR_RFEN 0x80000000 280 #define RFCR_AAB 0x40000000 281 #define RFCR_AAM 0x20000000 282 #define RFCR_AAU 0x10000000 283 #define RFCR_APM 0x08000000 284 #define RFCR_APAT 0x07800000 285 #define RFCR_APAT3 0x04000000 286 #define RFCR_APAT2 0x02000000 287 #define RFCR_APAT1 0x01000000 288 #define RFCR_APAT0 0x00800000 289 #define RFCR_AARP 0x00400000 290 #define RFCR_MHEN 0x00200000 291 #define RFCR_UHEN 0x00100000 292 #define RFCR_ULM 0x00080000 293 294 #define VRCR_RUDPE 0x00000080 295 #define VRCR_RTCPE 0x00000040 296 #define VRCR_RIPE 0x00000020 297 #define VRCR_IPEN 0x00000010 298 #define VRCR_DUTF 0x00000008 299 #define VRCR_DVTF 0x00000004 300 #define VRCR_VTREN 0x00000002 301 #define VRCR_VTDEN 0x00000001 302 303 #define VTCR_PPCHK 0x00000008 304 #define VTCR_GCHK 0x00000004 305 #define VTCR_VPPTI 0x00000002 306 #define VTCR_VGTI 0x00000001 307 308 #define CR 0x00 309 #define CFG 0x04 310 #define MEAR 0x08 311 #define PTSCR 0x0c 312 #define ISR 0x10 313 #define IMR 0x14 314 #define IER 0x18 315 #define IHR 0x1c 316 #define TXDP 0x20 317 #define TXDP_HI 0x24 318 #define TXCFG 0x28 319 #define GPIOR 0x2c 320 #define RXDP 0x30 321 #define RXDP_HI 0x34 322 #define RXCFG 0x38 323 #define PQCR 0x3c 324 #define WCSR 0x40 325 #define PCR 0x44 326 #define RFCR 0x48 327 #define RFDR 0x4c 328 329 #define SRR 0x58 330 331 #define VRCR 0xbc 332 #define VTCR 0xc0 333 #define VDR 0xc4 334 #define CCSR 0xcc 335 336 #define TBICR 0xe0 337 #define TBISR 0xe4 338 #define TANAR 0xe8 339 #define TANLPAR 0xec 340 #define TANER 0xf0 341 #define TESR 0xf4 342 343 #define TBICR_MR_AN_ENABLE 0x00001000 344 #define TBICR_MR_RESTART_AN 0x00000200 345 346 #define TBISR_MR_LINK_STATUS 0x00000020 347 #define TBISR_MR_AN_COMPLETE 0x00000004 348 349 #define TANAR_PS2 0x00000100 350 #define TANAR_PS1 0x00000080 351 #define TANAR_HALF_DUP 0x00000040 352 #define TANAR_FULL_DUP 0x00000020 353 354 #define GPIOR_GP5_OE 0x00000200 355 #define GPIOR_GP4_OE 0x00000100 356 #define GPIOR_GP3_OE 0x00000080 357 #define GPIOR_GP2_OE 0x00000040 358 #define GPIOR_GP1_OE 0x00000020 359 #define GPIOR_GP3_OUT 0x00000004 360 #define GPIOR_GP1_OUT 0x00000001 361 362 #define LINK_AUTONEGOTIATE 0x01 363 #define LINK_DOWN 0x02 364 #define LINK_UP 0x04 365 366 #define HW_ADDR_LEN sizeof(dma_addr_t) 367 #define desc_addr_set(desc, addr) \ 368 do { \ 369 ((desc)[0] = cpu_to_le32(addr)); \ 370 if (HW_ADDR_LEN == 8) \ 371 (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \ 372 } while(0) 373 #define desc_addr_get(desc) \ 374 (le32_to_cpu((desc)[0]) | \ 375 (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0)) 376 377 #define DESC_LINK 0 378 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4) 379 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4) 380 #define DESC_EXTSTS (DESC_CMDSTS + 4/4) 381 382 #define CMDSTS_OWN 0x80000000 383 #define CMDSTS_MORE 0x40000000 384 #define CMDSTS_INTR 0x20000000 385 #define CMDSTS_ERR 0x10000000 386 #define CMDSTS_OK 0x08000000 387 #define CMDSTS_RUNT 0x00200000 388 #define CMDSTS_LEN_MASK 0x0000ffff 389 390 #define CMDSTS_DEST_MASK 0x01800000 391 #define CMDSTS_DEST_SELF 0x00800000 392 #define CMDSTS_DEST_MULTI 0x01000000 393 394 #define DESC_SIZE 8 /* Should be cache line sized */ 395 396 struct rx_info { 397 spinlock_t lock; 398 int up; 399 unsigned long idle; 400 401 struct sk_buff *skbs[NR_RX_DESC]; 402 403 __le32 *next_rx_desc; 404 u16 next_rx, next_empty; 405 406 __le32 *descs; 407 dma_addr_t phy_descs; 408 }; 409 410 411 struct ns83820 { 412 u8 __iomem *base; 413 414 struct pci_dev *pci_dev; 415 struct net_device *ndev; 416 417 struct rx_info rx_info; 418 struct tasklet_struct rx_tasklet; 419 420 unsigned ihr; 421 struct work_struct tq_refill; 422 423 /* protects everything below. irqsave when using. */ 424 spinlock_t misc_lock; 425 426 u32 CFG_cache; 427 428 u32 MEAR_cache; 429 u32 IMR_cache; 430 431 unsigned linkstate; 432 433 spinlock_t tx_lock; 434 435 u16 tx_done_idx; 436 u16 tx_idx; 437 volatile u16 tx_free_idx; /* idx of free desc chain */ 438 u16 tx_intr_idx; 439 440 atomic_t nr_tx_skbs; 441 struct sk_buff *tx_skbs[NR_TX_DESC]; 442 443 char pad[16] __attribute__((aligned(16))); 444 __le32 *tx_descs; 445 dma_addr_t tx_phy_descs; 446 447 struct timer_list tx_watchdog; 448 }; 449 450 static inline struct ns83820 *PRIV(struct net_device *dev) 451 { 452 return netdev_priv(dev); 453 } 454 455 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR) 456 457 static inline void kick_rx(struct net_device *ndev) 458 { 459 struct ns83820 *dev = PRIV(ndev); 460 dprintk("kick_rx: maybe kicking\n"); 461 if (test_and_clear_bit(0, &dev->rx_info.idle)) { 462 dprintk("actually kicking\n"); 463 writel(dev->rx_info.phy_descs + 464 (4 * DESC_SIZE * dev->rx_info.next_rx), 465 dev->base + RXDP); 466 if (dev->rx_info.next_rx == dev->rx_info.next_empty) 467 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n", 468 ndev->name); 469 __kick_rx(dev); 470 } 471 } 472 473 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC 474 #define start_tx_okay(dev) \ 475 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE) 476 477 /* Packet Receiver 478 * 479 * The hardware supports linked lists of receive descriptors for 480 * which ownership is transferred back and forth by means of an 481 * ownership bit. While the hardware does support the use of a 482 * ring for receive descriptors, we only make use of a chain in 483 * an attempt to reduce bus traffic under heavy load scenarios. 484 * This will also make bugs a bit more obvious. The current code 485 * only makes use of a single rx chain; I hope to implement 486 * priority based rx for version 1.0. Goal: even under overload 487 * conditions, still route realtime traffic with as low jitter as 488 * possible. 489 */ 490 static inline void build_rx_desc(struct ns83820 *dev, __le32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts) 491 { 492 desc_addr_set(desc + DESC_LINK, link); 493 desc_addr_set(desc + DESC_BUFPTR, buf); 494 desc[DESC_EXTSTS] = cpu_to_le32(extsts); 495 mb(); 496 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts); 497 } 498 499 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC) 500 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb) 501 { 502 unsigned next_empty; 503 u32 cmdsts; 504 __le32 *sg; 505 dma_addr_t buf; 506 507 next_empty = dev->rx_info.next_empty; 508 509 /* don't overrun last rx marker */ 510 if (unlikely(nr_rx_empty(dev) <= 2)) { 511 kfree_skb(skb); 512 return 1; 513 } 514 515 #if 0 516 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n", 517 dev->rx_info.next_empty, 518 dev->rx_info.nr_used, 519 dev->rx_info.next_rx 520 ); 521 #endif 522 523 sg = dev->rx_info.descs + (next_empty * DESC_SIZE); 524 BUG_ON(NULL != dev->rx_info.skbs[next_empty]); 525 dev->rx_info.skbs[next_empty] = skb; 526 527 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC; 528 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR; 529 buf = dma_map_single(&dev->pci_dev->dev, skb->data, REAL_RX_BUF_SIZE, 530 DMA_FROM_DEVICE); 531 build_rx_desc(dev, sg, 0, buf, cmdsts, 0); 532 /* update link of previous rx */ 533 if (likely(next_empty != dev->rx_info.next_rx)) 534 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4)); 535 536 return 0; 537 } 538 539 static inline int rx_refill(struct net_device *ndev, gfp_t gfp) 540 { 541 struct ns83820 *dev = PRIV(ndev); 542 unsigned i; 543 unsigned long flags = 0; 544 545 if (unlikely(nr_rx_empty(dev) <= 2)) 546 return 0; 547 548 dprintk("rx_refill(%p)\n", ndev); 549 if (gfp == GFP_ATOMIC) 550 spin_lock_irqsave(&dev->rx_info.lock, flags); 551 for (i=0; i<NR_RX_DESC; i++) { 552 struct sk_buff *skb; 553 long res; 554 555 /* extra 16 bytes for alignment */ 556 skb = __netdev_alloc_skb(ndev, REAL_RX_BUF_SIZE+16, gfp); 557 if (unlikely(!skb)) 558 break; 559 560 skb_reserve(skb, skb->data - PTR_ALIGN(skb->data, 16)); 561 if (gfp != GFP_ATOMIC) 562 spin_lock_irqsave(&dev->rx_info.lock, flags); 563 res = ns83820_add_rx_skb(dev, skb); 564 if (gfp != GFP_ATOMIC) 565 spin_unlock_irqrestore(&dev->rx_info.lock, flags); 566 if (res) { 567 i = 1; 568 break; 569 } 570 } 571 if (gfp == GFP_ATOMIC) 572 spin_unlock_irqrestore(&dev->rx_info.lock, flags); 573 574 return i ? 0 : -ENOMEM; 575 } 576 577 static void rx_refill_atomic(struct net_device *ndev) 578 { 579 rx_refill(ndev, GFP_ATOMIC); 580 } 581 582 /* REFILL */ 583 static inline void queue_refill(struct work_struct *work) 584 { 585 struct ns83820 *dev = container_of(work, struct ns83820, tq_refill); 586 struct net_device *ndev = dev->ndev; 587 588 rx_refill(ndev, GFP_KERNEL); 589 if (dev->rx_info.up) 590 kick_rx(ndev); 591 } 592 593 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i) 594 { 595 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0); 596 } 597 598 static void phy_intr(struct net_device *ndev) 599 { 600 struct ns83820 *dev = PRIV(ndev); 601 static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" }; 602 u32 cfg, new_cfg; 603 u32 tanar, tanlpar; 604 int speed, fullduplex, newlinkstate; 605 606 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; 607 608 if (dev->CFG_cache & CFG_TBI_EN) { 609 u32 __maybe_unused tbisr; 610 611 /* we have an optical transceiver */ 612 tbisr = readl(dev->base + TBISR); 613 tanar = readl(dev->base + TANAR); 614 tanlpar = readl(dev->base + TANLPAR); 615 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n", 616 tbisr, tanar, tanlpar); 617 618 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP) && 619 (tanar & TANAR_FULL_DUP)) ) { 620 621 /* both of us are full duplex */ 622 writel(readl(dev->base + TXCFG) 623 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP, 624 dev->base + TXCFG); 625 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, 626 dev->base + RXCFG); 627 /* Light up full duplex LED */ 628 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT, 629 dev->base + GPIOR); 630 631 } else if (((tanlpar & TANAR_HALF_DUP) && 632 (tanar & TANAR_HALF_DUP)) || 633 ((tanlpar & TANAR_FULL_DUP) && 634 (tanar & TANAR_HALF_DUP)) || 635 ((tanlpar & TANAR_HALF_DUP) && 636 (tanar & TANAR_FULL_DUP))) { 637 638 /* one or both of us are half duplex */ 639 writel((readl(dev->base + TXCFG) 640 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP, 641 dev->base + TXCFG); 642 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD, 643 dev->base + RXCFG); 644 /* Turn off full duplex LED */ 645 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT, 646 dev->base + GPIOR); 647 } 648 649 speed = 4; /* 1000F */ 650 651 } else { 652 /* we have a copper transceiver */ 653 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS); 654 655 if (cfg & CFG_SPDSTS1) 656 new_cfg |= CFG_MODE_1000; 657 else 658 new_cfg &= ~CFG_MODE_1000; 659 660 speed = ((cfg / CFG_SPDSTS0) & 3); 661 fullduplex = (cfg & CFG_DUPSTS); 662 663 if (fullduplex) { 664 new_cfg |= CFG_SB; 665 writel(readl(dev->base + TXCFG) 666 | TXCFG_CSI | TXCFG_HBI, 667 dev->base + TXCFG); 668 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, 669 dev->base + RXCFG); 670 } else { 671 writel(readl(dev->base + TXCFG) 672 & ~(TXCFG_CSI | TXCFG_HBI), 673 dev->base + TXCFG); 674 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD), 675 dev->base + RXCFG); 676 } 677 678 if ((cfg & CFG_LNKSTS) && 679 ((new_cfg ^ dev->CFG_cache) != 0)) { 680 writel(new_cfg, dev->base + CFG); 681 dev->CFG_cache = new_cfg; 682 } 683 684 dev->CFG_cache &= ~CFG_SPDSTS; 685 dev->CFG_cache |= cfg & CFG_SPDSTS; 686 } 687 688 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN; 689 690 if (newlinkstate & LINK_UP && 691 dev->linkstate != newlinkstate) { 692 netif_start_queue(ndev); 693 netif_wake_queue(ndev); 694 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n", 695 ndev->name, 696 speeds[speed], 697 fullduplex ? "full" : "half"); 698 } else if (newlinkstate & LINK_DOWN && 699 dev->linkstate != newlinkstate) { 700 netif_stop_queue(ndev); 701 printk(KERN_INFO "%s: link now down.\n", ndev->name); 702 } 703 704 dev->linkstate = newlinkstate; 705 } 706 707 static int ns83820_setup_rx(struct net_device *ndev) 708 { 709 struct ns83820 *dev = PRIV(ndev); 710 unsigned i; 711 int ret; 712 713 dprintk("ns83820_setup_rx(%p)\n", ndev); 714 715 dev->rx_info.idle = 1; 716 dev->rx_info.next_rx = 0; 717 dev->rx_info.next_rx_desc = dev->rx_info.descs; 718 dev->rx_info.next_empty = 0; 719 720 for (i=0; i<NR_RX_DESC; i++) 721 clear_rx_desc(dev, i); 722 723 writel(0, dev->base + RXDP_HI); 724 writel(dev->rx_info.phy_descs, dev->base + RXDP); 725 726 ret = rx_refill(ndev, GFP_KERNEL); 727 if (!ret) { 728 dprintk("starting receiver\n"); 729 /* prevent the interrupt handler from stomping on us */ 730 spin_lock_irq(&dev->rx_info.lock); 731 732 writel(0x0001, dev->base + CCSR); 733 writel(0, dev->base + RFCR); 734 writel(0x7fc00000, dev->base + RFCR); 735 writel(0xffc00000, dev->base + RFCR); 736 737 dev->rx_info.up = 1; 738 739 phy_intr(ndev); 740 741 /* Okay, let it rip */ 742 spin_lock(&dev->misc_lock); 743 dev->IMR_cache |= ISR_PHY; 744 dev->IMR_cache |= ISR_RXRCMP; 745 //dev->IMR_cache |= ISR_RXERR; 746 //dev->IMR_cache |= ISR_RXOK; 747 dev->IMR_cache |= ISR_RXORN; 748 dev->IMR_cache |= ISR_RXSOVR; 749 dev->IMR_cache |= ISR_RXDESC; 750 dev->IMR_cache |= ISR_RXIDLE; 751 dev->IMR_cache |= ISR_TXDESC; 752 dev->IMR_cache |= ISR_TXIDLE; 753 754 writel(dev->IMR_cache, dev->base + IMR); 755 writel(1, dev->base + IER); 756 spin_unlock(&dev->misc_lock); 757 758 kick_rx(ndev); 759 760 spin_unlock_irq(&dev->rx_info.lock); 761 } 762 return ret; 763 } 764 765 static void ns83820_cleanup_rx(struct ns83820 *dev) 766 { 767 unsigned i; 768 unsigned long flags; 769 770 dprintk("ns83820_cleanup_rx(%p)\n", dev); 771 772 /* disable receive interrupts */ 773 spin_lock_irqsave(&dev->misc_lock, flags); 774 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE); 775 writel(dev->IMR_cache, dev->base + IMR); 776 spin_unlock_irqrestore(&dev->misc_lock, flags); 777 778 /* synchronize with the interrupt handler and kill it */ 779 dev->rx_info.up = 0; 780 synchronize_irq(dev->pci_dev->irq); 781 782 /* touch the pci bus... */ 783 readl(dev->base + IMR); 784 785 /* assumes the transmitter is already disabled and reset */ 786 writel(0, dev->base + RXDP_HI); 787 writel(0, dev->base + RXDP); 788 789 for (i=0; i<NR_RX_DESC; i++) { 790 struct sk_buff *skb = dev->rx_info.skbs[i]; 791 dev->rx_info.skbs[i] = NULL; 792 clear_rx_desc(dev, i); 793 kfree_skb(skb); 794 } 795 } 796 797 static void ns83820_rx_kick(struct net_device *ndev) 798 { 799 struct ns83820 *dev = PRIV(ndev); 800 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ { 801 if (dev->rx_info.up) { 802 rx_refill_atomic(ndev); 803 kick_rx(ndev); 804 } 805 } 806 807 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4) 808 schedule_work(&dev->tq_refill); 809 else 810 kick_rx(ndev); 811 if (dev->rx_info.idle) 812 printk(KERN_DEBUG "%s: BAD\n", ndev->name); 813 } 814 815 /* rx_irq 816 * 817 */ 818 static void rx_irq(struct net_device *ndev) 819 { 820 struct ns83820 *dev = PRIV(ndev); 821 struct rx_info *info = &dev->rx_info; 822 unsigned next_rx; 823 int len; 824 u32 cmdsts; 825 __le32 *desc; 826 unsigned long flags; 827 int nr = 0; 828 829 dprintk("rx_irq(%p)\n", ndev); 830 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n", 831 readl(dev->base + RXDP), 832 (long)(dev->rx_info.phy_descs), 833 (int)dev->rx_info.next_rx, 834 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)), 835 (int)dev->rx_info.next_empty, 836 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty)) 837 ); 838 839 spin_lock_irqsave(&info->lock, flags); 840 if (!info->up) 841 goto out; 842 843 dprintk("walking descs\n"); 844 next_rx = info->next_rx; 845 desc = info->next_rx_desc; 846 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) && 847 (cmdsts != CMDSTS_OWN)) { 848 struct sk_buff *skb; 849 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]); 850 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR); 851 852 dprintk("cmdsts: %08x\n", cmdsts); 853 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK])); 854 dprintk("extsts: %08x\n", extsts); 855 856 skb = info->skbs[next_rx]; 857 info->skbs[next_rx] = NULL; 858 info->next_rx = (next_rx + 1) % NR_RX_DESC; 859 860 mb(); 861 clear_rx_desc(dev, next_rx); 862 863 dma_unmap_single(&dev->pci_dev->dev, bufptr, RX_BUF_SIZE, 864 DMA_FROM_DEVICE); 865 len = cmdsts & CMDSTS_LEN_MASK; 866 #ifdef NS83820_VLAN_ACCEL_SUPPORT 867 /* NH: As was mentioned below, this chip is kinda 868 * brain dead about vlan tag stripping. Frames 869 * that are 64 bytes with a vlan header appended 870 * like arp frames, or pings, are flagged as Runts 871 * when the tag is stripped and hardware. This 872 * also means that the OK bit in the descriptor 873 * is cleared when the frame comes in so we have 874 * to do a specific length check here to make sure 875 * the frame would have been ok, had we not stripped 876 * the tag. 877 */ 878 if (likely((CMDSTS_OK & cmdsts) || 879 ((cmdsts & CMDSTS_RUNT) && len >= 56))) { 880 #else 881 if (likely(CMDSTS_OK & cmdsts)) { 882 #endif 883 skb_put(skb, len); 884 if (unlikely(!skb)) { 885 ndev->stats.rx_dropped++; 886 goto netdev_mangle_me_harder_failed; 887 } 888 if (cmdsts & CMDSTS_DEST_MULTI) 889 ndev->stats.multicast++; 890 ndev->stats.rx_packets++; 891 ndev->stats.rx_bytes += len; 892 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) { 893 skb->ip_summed = CHECKSUM_UNNECESSARY; 894 } else { 895 skb_checksum_none_assert(skb); 896 } 897 skb->protocol = eth_type_trans(skb, ndev); 898 #ifdef NS83820_VLAN_ACCEL_SUPPORT 899 if(extsts & EXTSTS_VPKT) { 900 unsigned short tag; 901 902 tag = ntohs(extsts & EXTSTS_VTG_MASK); 903 __vlan_hwaccel_put_tag(skb, htons(ETH_P_IPV6), tag); 904 } 905 #endif 906 netif_rx(skb); 907 } else { 908 dev_kfree_skb_irq(skb); 909 } 910 911 netdev_mangle_me_harder_failed: 912 nr++; 913 next_rx = info->next_rx; 914 desc = info->descs + (DESC_SIZE * next_rx); 915 } 916 info->next_rx = next_rx; 917 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx); 918 919 out: 920 if (0 && !nr) { 921 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts); 922 } 923 924 spin_unlock_irqrestore(&info->lock, flags); 925 } 926 927 static void rx_action(struct tasklet_struct *t) 928 { 929 struct ns83820 *dev = from_tasklet(dev, t, rx_tasklet); 930 struct net_device *ndev = dev->ndev; 931 rx_irq(ndev); 932 writel(ihr, dev->base + IHR); 933 934 spin_lock_irq(&dev->misc_lock); 935 dev->IMR_cache |= ISR_RXDESC; 936 writel(dev->IMR_cache, dev->base + IMR); 937 spin_unlock_irq(&dev->misc_lock); 938 939 rx_irq(ndev); 940 ns83820_rx_kick(ndev); 941 } 942 943 /* Packet Transmit code 944 */ 945 static inline void kick_tx(struct ns83820 *dev) 946 { 947 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n", 948 dev, dev->tx_idx, dev->tx_free_idx); 949 writel(CR_TXE, dev->base + CR); 950 } 951 952 /* No spinlock needed on the transmit irq path as the interrupt handler is 953 * serialized. 954 */ 955 static void do_tx_done(struct net_device *ndev) 956 { 957 struct ns83820 *dev = PRIV(ndev); 958 u32 cmdsts, tx_done_idx; 959 __le32 *desc; 960 961 dprintk("do_tx_done(%p)\n", ndev); 962 tx_done_idx = dev->tx_done_idx; 963 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE); 964 965 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n", 966 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS])); 967 while ((tx_done_idx != dev->tx_free_idx) && 968 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) { 969 struct sk_buff *skb; 970 unsigned len; 971 dma_addr_t addr; 972 973 if (cmdsts & CMDSTS_ERR) 974 ndev->stats.tx_errors++; 975 if (cmdsts & CMDSTS_OK) 976 ndev->stats.tx_packets++; 977 if (cmdsts & CMDSTS_OK) 978 ndev->stats.tx_bytes += cmdsts & 0xffff; 979 980 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n", 981 tx_done_idx, dev->tx_free_idx, cmdsts); 982 skb = dev->tx_skbs[tx_done_idx]; 983 dev->tx_skbs[tx_done_idx] = NULL; 984 dprintk("done(%p)\n", skb); 985 986 len = cmdsts & CMDSTS_LEN_MASK; 987 addr = desc_addr_get(desc + DESC_BUFPTR); 988 if (skb) { 989 dma_unmap_single(&dev->pci_dev->dev, addr, len, 990 DMA_TO_DEVICE); 991 dev_consume_skb_irq(skb); 992 atomic_dec(&dev->nr_tx_skbs); 993 } else 994 dma_unmap_page(&dev->pci_dev->dev, addr, len, 995 DMA_TO_DEVICE); 996 997 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC; 998 dev->tx_done_idx = tx_done_idx; 999 desc[DESC_CMDSTS] = cpu_to_le32(0); 1000 mb(); 1001 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE); 1002 } 1003 1004 /* Allow network stack to resume queueing packets after we've 1005 * finished transmitting at least 1/4 of the packets in the queue. 1006 */ 1007 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) { 1008 dprintk("start_queue(%p)\n", ndev); 1009 netif_start_queue(ndev); 1010 netif_wake_queue(ndev); 1011 } 1012 } 1013 1014 static void ns83820_cleanup_tx(struct ns83820 *dev) 1015 { 1016 unsigned i; 1017 1018 for (i=0; i<NR_TX_DESC; i++) { 1019 struct sk_buff *skb = dev->tx_skbs[i]; 1020 dev->tx_skbs[i] = NULL; 1021 if (skb) { 1022 __le32 *desc = dev->tx_descs + (i * DESC_SIZE); 1023 dma_unmap_single(&dev->pci_dev->dev, 1024 desc_addr_get(desc + DESC_BUFPTR), 1025 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK, 1026 DMA_TO_DEVICE); 1027 dev_kfree_skb_irq(skb); 1028 atomic_dec(&dev->nr_tx_skbs); 1029 } 1030 } 1031 1032 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4); 1033 } 1034 1035 /* transmit routine. This code relies on the network layer serializing 1036 * its calls in, but will run happily in parallel with the interrupt 1037 * handler. This code currently has provisions for fragmenting tx buffers 1038 * while trying to track down a bug in either the zero copy code or 1039 * the tx fifo (hence the MAX_FRAG_LEN). 1040 */ 1041 static netdev_tx_t ns83820_hard_start_xmit(struct sk_buff *skb, 1042 struct net_device *ndev) 1043 { 1044 struct ns83820 *dev = PRIV(ndev); 1045 u32 free_idx, cmdsts, extsts; 1046 int nr_free, nr_frags; 1047 unsigned tx_done_idx, last_idx; 1048 dma_addr_t buf; 1049 unsigned len; 1050 skb_frag_t *frag; 1051 int stopped = 0; 1052 int do_intr = 0; 1053 volatile __le32 *first_desc; 1054 1055 dprintk("ns83820_hard_start_xmit\n"); 1056 1057 nr_frags = skb_shinfo(skb)->nr_frags; 1058 again: 1059 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) { 1060 netif_stop_queue(ndev); 1061 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) 1062 return NETDEV_TX_BUSY; 1063 netif_start_queue(ndev); 1064 } 1065 1066 last_idx = free_idx = dev->tx_free_idx; 1067 tx_done_idx = dev->tx_done_idx; 1068 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC; 1069 nr_free -= 1; 1070 if (nr_free <= nr_frags) { 1071 dprintk("stop_queue - not enough(%p)\n", ndev); 1072 netif_stop_queue(ndev); 1073 1074 /* Check again: we may have raced with a tx done irq */ 1075 if (dev->tx_done_idx != tx_done_idx) { 1076 dprintk("restart queue(%p)\n", ndev); 1077 netif_start_queue(ndev); 1078 goto again; 1079 } 1080 return NETDEV_TX_BUSY; 1081 } 1082 1083 if (free_idx == dev->tx_intr_idx) { 1084 do_intr = 1; 1085 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC; 1086 } 1087 1088 nr_free -= nr_frags; 1089 if (nr_free < MIN_TX_DESC_FREE) { 1090 dprintk("stop_queue - last entry(%p)\n", ndev); 1091 netif_stop_queue(ndev); 1092 stopped = 1; 1093 } 1094 1095 frag = skb_shinfo(skb)->frags; 1096 if (!nr_frags) 1097 frag = NULL; 1098 extsts = 0; 1099 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1100 extsts |= EXTSTS_IPPKT; 1101 if (IPPROTO_TCP == ip_hdr(skb)->protocol) 1102 extsts |= EXTSTS_TCPPKT; 1103 else if (IPPROTO_UDP == ip_hdr(skb)->protocol) 1104 extsts |= EXTSTS_UDPPKT; 1105 } 1106 1107 #ifdef NS83820_VLAN_ACCEL_SUPPORT 1108 if (skb_vlan_tag_present(skb)) { 1109 /* fetch the vlan tag info out of the 1110 * ancillary data if the vlan code 1111 * is using hw vlan acceleration 1112 */ 1113 short tag = skb_vlan_tag_get(skb); 1114 extsts |= (EXTSTS_VPKT | htons(tag)); 1115 } 1116 #endif 1117 1118 len = skb->len; 1119 if (nr_frags) 1120 len -= skb->data_len; 1121 buf = dma_map_single(&dev->pci_dev->dev, skb->data, len, 1122 DMA_TO_DEVICE); 1123 1124 first_desc = dev->tx_descs + (free_idx * DESC_SIZE); 1125 1126 for (;;) { 1127 volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE); 1128 1129 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len, 1130 (unsigned long long)buf); 1131 last_idx = free_idx; 1132 free_idx = (free_idx + 1) % NR_TX_DESC; 1133 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4)); 1134 desc_addr_set(desc + DESC_BUFPTR, buf); 1135 desc[DESC_EXTSTS] = cpu_to_le32(extsts); 1136 1137 cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0); 1138 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN; 1139 cmdsts |= len; 1140 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts); 1141 1142 if (!nr_frags) 1143 break; 1144 1145 buf = skb_frag_dma_map(&dev->pci_dev->dev, frag, 0, 1146 skb_frag_size(frag), DMA_TO_DEVICE); 1147 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n", 1148 (long long)buf, (long) page_to_pfn(frag->page), 1149 frag->page_offset); 1150 len = skb_frag_size(frag); 1151 frag++; 1152 nr_frags--; 1153 } 1154 dprintk("done pkt\n"); 1155 1156 spin_lock_irq(&dev->tx_lock); 1157 dev->tx_skbs[last_idx] = skb; 1158 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN); 1159 dev->tx_free_idx = free_idx; 1160 atomic_inc(&dev->nr_tx_skbs); 1161 spin_unlock_irq(&dev->tx_lock); 1162 1163 kick_tx(dev); 1164 1165 /* Check again: we may have raced with a tx done irq */ 1166 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev)) 1167 netif_start_queue(ndev); 1168 1169 return NETDEV_TX_OK; 1170 } 1171 1172 static void ns83820_update_stats(struct ns83820 *dev) 1173 { 1174 struct net_device *ndev = dev->ndev; 1175 u8 __iomem *base = dev->base; 1176 1177 /* the DP83820 will freeze counters, so we need to read all of them */ 1178 ndev->stats.rx_errors += readl(base + 0x60) & 0xffff; 1179 ndev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff; 1180 ndev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff; 1181 ndev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff; 1182 /*ndev->stats.rx_symbol_errors +=*/ readl(base + 0x70); 1183 ndev->stats.rx_length_errors += readl(base + 0x74) & 0xffff; 1184 ndev->stats.rx_length_errors += readl(base + 0x78) & 0xffff; 1185 /*ndev->stats.rx_badopcode_errors += */ readl(base + 0x7c); 1186 /*ndev->stats.rx_pause_count += */ readl(base + 0x80); 1187 /*ndev->stats.tx_pause_count += */ readl(base + 0x84); 1188 ndev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff; 1189 } 1190 1191 static struct net_device_stats *ns83820_get_stats(struct net_device *ndev) 1192 { 1193 struct ns83820 *dev = PRIV(ndev); 1194 1195 /* somewhat overkill */ 1196 spin_lock_irq(&dev->misc_lock); 1197 ns83820_update_stats(dev); 1198 spin_unlock_irq(&dev->misc_lock); 1199 1200 return &ndev->stats; 1201 } 1202 1203 /* Let ethtool retrieve info */ 1204 static int ns83820_get_link_ksettings(struct net_device *ndev, 1205 struct ethtool_link_ksettings *cmd) 1206 { 1207 struct ns83820 *dev = PRIV(ndev); 1208 u32 cfg, tbicr; 1209 int fullduplex = 0; 1210 u32 supported; 1211 1212 /* 1213 * Here's the list of available ethtool commands from other drivers: 1214 * cmd->advertising = 1215 * ethtool_cmd_speed_set(cmd, ...) 1216 * cmd->duplex = 1217 * cmd->port = 0; 1218 * cmd->phy_address = 1219 * cmd->transceiver = 0; 1220 * cmd->autoneg = 1221 * cmd->maxtxpkt = 0; 1222 * cmd->maxrxpkt = 0; 1223 */ 1224 1225 /* read current configuration */ 1226 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; 1227 readl(dev->base + TANAR); 1228 tbicr = readl(dev->base + TBICR); 1229 1230 fullduplex = (cfg & CFG_DUPSTS) ? 1 : 0; 1231 1232 supported = SUPPORTED_Autoneg; 1233 1234 if (dev->CFG_cache & CFG_TBI_EN) { 1235 /* we have optical interface */ 1236 supported |= SUPPORTED_1000baseT_Half | 1237 SUPPORTED_1000baseT_Full | 1238 SUPPORTED_FIBRE; 1239 cmd->base.port = PORT_FIBRE; 1240 } else { 1241 /* we have copper */ 1242 supported |= SUPPORTED_10baseT_Half | 1243 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half | 1244 SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Half | 1245 SUPPORTED_1000baseT_Full | 1246 SUPPORTED_MII; 1247 cmd->base.port = PORT_MII; 1248 } 1249 1250 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 1251 supported); 1252 1253 cmd->base.duplex = fullduplex ? DUPLEX_FULL : DUPLEX_HALF; 1254 switch (cfg / CFG_SPDSTS0 & 3) { 1255 case 2: 1256 cmd->base.speed = SPEED_1000; 1257 break; 1258 case 1: 1259 cmd->base.speed = SPEED_100; 1260 break; 1261 default: 1262 cmd->base.speed = SPEED_10; 1263 break; 1264 } 1265 cmd->base.autoneg = (tbicr & TBICR_MR_AN_ENABLE) 1266 ? AUTONEG_ENABLE : AUTONEG_DISABLE; 1267 return 0; 1268 } 1269 1270 /* Let ethool change settings*/ 1271 static int ns83820_set_link_ksettings(struct net_device *ndev, 1272 const struct ethtool_link_ksettings *cmd) 1273 { 1274 struct ns83820 *dev = PRIV(ndev); 1275 u32 cfg, tanar; 1276 int have_optical = 0; 1277 int fullduplex = 0; 1278 1279 /* read current configuration */ 1280 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; 1281 tanar = readl(dev->base + TANAR); 1282 1283 if (dev->CFG_cache & CFG_TBI_EN) { 1284 /* we have optical */ 1285 have_optical = 1; 1286 fullduplex = (tanar & TANAR_FULL_DUP); 1287 1288 } else { 1289 /* we have copper */ 1290 fullduplex = cfg & CFG_DUPSTS; 1291 } 1292 1293 spin_lock_irq(&dev->misc_lock); 1294 spin_lock(&dev->tx_lock); 1295 1296 /* Set duplex */ 1297 if (cmd->base.duplex != fullduplex) { 1298 if (have_optical) { 1299 /*set full duplex*/ 1300 if (cmd->base.duplex == DUPLEX_FULL) { 1301 /* force full duplex */ 1302 writel(readl(dev->base + TXCFG) 1303 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP, 1304 dev->base + TXCFG); 1305 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, 1306 dev->base + RXCFG); 1307 /* Light up full duplex LED */ 1308 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT, 1309 dev->base + GPIOR); 1310 } else { 1311 /*TODO: set half duplex */ 1312 } 1313 1314 } else { 1315 /*we have copper*/ 1316 /* TODO: Set duplex for copper cards */ 1317 } 1318 printk(KERN_INFO "%s: Duplex set via ethtool\n", 1319 ndev->name); 1320 } 1321 1322 /* Set autonegotiation */ 1323 if (1) { 1324 if (cmd->base.autoneg == AUTONEG_ENABLE) { 1325 /* restart auto negotiation */ 1326 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN, 1327 dev->base + TBICR); 1328 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR); 1329 dev->linkstate = LINK_AUTONEGOTIATE; 1330 1331 printk(KERN_INFO "%s: autoneg enabled via ethtool\n", 1332 ndev->name); 1333 } else { 1334 /* disable auto negotiation */ 1335 writel(0x00000000, dev->base + TBICR); 1336 } 1337 1338 printk(KERN_INFO "%s: autoneg %s via ethtool\n", ndev->name, 1339 cmd->base.autoneg ? "ENABLED" : "DISABLED"); 1340 } 1341 1342 phy_intr(ndev); 1343 spin_unlock(&dev->tx_lock); 1344 spin_unlock_irq(&dev->misc_lock); 1345 1346 return 0; 1347 } 1348 /* end ethtool get/set support -df */ 1349 1350 static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info) 1351 { 1352 struct ns83820 *dev = PRIV(ndev); 1353 strscpy(info->driver, "ns83820", sizeof(info->driver)); 1354 strscpy(info->version, VERSION, sizeof(info->version)); 1355 strscpy(info->bus_info, pci_name(dev->pci_dev), sizeof(info->bus_info)); 1356 } 1357 1358 static u32 ns83820_get_link(struct net_device *ndev) 1359 { 1360 struct ns83820 *dev = PRIV(ndev); 1361 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; 1362 return cfg & CFG_LNKSTS ? 1 : 0; 1363 } 1364 1365 static const struct ethtool_ops ops = { 1366 .get_drvinfo = ns83820_get_drvinfo, 1367 .get_link = ns83820_get_link, 1368 .get_link_ksettings = ns83820_get_link_ksettings, 1369 .set_link_ksettings = ns83820_set_link_ksettings, 1370 }; 1371 1372 static inline void ns83820_disable_interrupts(struct ns83820 *dev) 1373 { 1374 writel(0, dev->base + IMR); 1375 writel(0, dev->base + IER); 1376 readl(dev->base + IER); 1377 } 1378 1379 /* this function is called in irq context from the ISR */ 1380 static void ns83820_mib_isr(struct ns83820 *dev) 1381 { 1382 unsigned long flags; 1383 spin_lock_irqsave(&dev->misc_lock, flags); 1384 ns83820_update_stats(dev); 1385 spin_unlock_irqrestore(&dev->misc_lock, flags); 1386 } 1387 1388 static void ns83820_do_isr(struct net_device *ndev, u32 isr); 1389 static irqreturn_t ns83820_irq(int foo, void *data) 1390 { 1391 struct net_device *ndev = data; 1392 struct ns83820 *dev = PRIV(ndev); 1393 u32 isr; 1394 dprintk("ns83820_irq(%p)\n", ndev); 1395 1396 dev->ihr = 0; 1397 1398 isr = readl(dev->base + ISR); 1399 dprintk("irq: %08x\n", isr); 1400 ns83820_do_isr(ndev, isr); 1401 return IRQ_HANDLED; 1402 } 1403 1404 static void ns83820_do_isr(struct net_device *ndev, u32 isr) 1405 { 1406 struct ns83820 *dev = PRIV(ndev); 1407 unsigned long flags; 1408 1409 #ifdef DEBUG 1410 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC)) 1411 Dprintk("odd isr? 0x%08x\n", isr); 1412 #endif 1413 1414 if (ISR_RXIDLE & isr) { 1415 dev->rx_info.idle = 1; 1416 Dprintk("oh dear, we are idle\n"); 1417 ns83820_rx_kick(ndev); 1418 } 1419 1420 if ((ISR_RXDESC | ISR_RXOK) & isr) { 1421 prefetch(dev->rx_info.next_rx_desc); 1422 1423 spin_lock_irqsave(&dev->misc_lock, flags); 1424 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK); 1425 writel(dev->IMR_cache, dev->base + IMR); 1426 spin_unlock_irqrestore(&dev->misc_lock, flags); 1427 1428 tasklet_schedule(&dev->rx_tasklet); 1429 //rx_irq(ndev); 1430 //writel(4, dev->base + IHR); 1431 } 1432 1433 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr) 1434 ns83820_rx_kick(ndev); 1435 1436 if (unlikely(ISR_RXSOVR & isr)) { 1437 //printk("overrun: rxsovr\n"); 1438 ndev->stats.rx_fifo_errors++; 1439 } 1440 1441 if (unlikely(ISR_RXORN & isr)) { 1442 //printk("overrun: rxorn\n"); 1443 ndev->stats.rx_fifo_errors++; 1444 } 1445 1446 if ((ISR_RXRCMP & isr) && dev->rx_info.up) 1447 writel(CR_RXE, dev->base + CR); 1448 1449 if (ISR_TXIDLE & isr) { 1450 u32 txdp; 1451 txdp = readl(dev->base + TXDP); 1452 dprintk("txdp: %08x\n", txdp); 1453 txdp -= dev->tx_phy_descs; 1454 dev->tx_idx = txdp / (DESC_SIZE * 4); 1455 if (dev->tx_idx >= NR_TX_DESC) { 1456 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name); 1457 dev->tx_idx = 0; 1458 } 1459 /* The may have been a race between a pci originated read 1460 * and the descriptor update from the cpu. Just in case, 1461 * kick the transmitter if the hardware thinks it is on a 1462 * different descriptor than we are. 1463 */ 1464 if (dev->tx_idx != dev->tx_free_idx) 1465 kick_tx(dev); 1466 } 1467 1468 /* Defer tx ring processing until more than a minimum amount of 1469 * work has accumulated 1470 */ 1471 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) { 1472 spin_lock_irqsave(&dev->tx_lock, flags); 1473 do_tx_done(ndev); 1474 spin_unlock_irqrestore(&dev->tx_lock, flags); 1475 1476 /* Disable TxOk if there are no outstanding tx packets. 1477 */ 1478 if ((dev->tx_done_idx == dev->tx_free_idx) && 1479 (dev->IMR_cache & ISR_TXOK)) { 1480 spin_lock_irqsave(&dev->misc_lock, flags); 1481 dev->IMR_cache &= ~ISR_TXOK; 1482 writel(dev->IMR_cache, dev->base + IMR); 1483 spin_unlock_irqrestore(&dev->misc_lock, flags); 1484 } 1485 } 1486 1487 /* The TxIdle interrupt can come in before the transmit has 1488 * completed. Normally we reap packets off of the combination 1489 * of TxDesc and TxIdle and leave TxOk disabled (since it 1490 * occurs on every packet), but when no further irqs of this 1491 * nature are expected, we must enable TxOk. 1492 */ 1493 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) { 1494 spin_lock_irqsave(&dev->misc_lock, flags); 1495 dev->IMR_cache |= ISR_TXOK; 1496 writel(dev->IMR_cache, dev->base + IMR); 1497 spin_unlock_irqrestore(&dev->misc_lock, flags); 1498 } 1499 1500 /* MIB interrupt: one of the statistics counters is about to overflow */ 1501 if (unlikely(ISR_MIB & isr)) 1502 ns83820_mib_isr(dev); 1503 1504 /* PHY: Link up/down/negotiation state change */ 1505 if (unlikely(ISR_PHY & isr)) 1506 phy_intr(ndev); 1507 1508 #if 0 /* Still working on the interrupt mitigation strategy */ 1509 if (dev->ihr) 1510 writel(dev->ihr, dev->base + IHR); 1511 #endif 1512 } 1513 1514 static void ns83820_do_reset(struct ns83820 *dev, u32 which) 1515 { 1516 Dprintk("resetting chip...\n"); 1517 writel(which, dev->base + CR); 1518 do { 1519 schedule(); 1520 } while (readl(dev->base + CR) & which); 1521 Dprintk("okay!\n"); 1522 } 1523 1524 static int ns83820_stop(struct net_device *ndev) 1525 { 1526 struct ns83820 *dev = PRIV(ndev); 1527 1528 /* FIXME: protect against interrupt handler? */ 1529 timer_delete_sync(&dev->tx_watchdog); 1530 1531 ns83820_disable_interrupts(dev); 1532 1533 dev->rx_info.up = 0; 1534 synchronize_irq(dev->pci_dev->irq); 1535 1536 ns83820_do_reset(dev, CR_RST); 1537 1538 synchronize_irq(dev->pci_dev->irq); 1539 1540 spin_lock_irq(&dev->misc_lock); 1541 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK); 1542 spin_unlock_irq(&dev->misc_lock); 1543 1544 ns83820_cleanup_rx(dev); 1545 ns83820_cleanup_tx(dev); 1546 1547 return 0; 1548 } 1549 1550 static void ns83820_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1551 { 1552 struct ns83820 *dev = PRIV(ndev); 1553 u32 tx_done_idx; 1554 __le32 *desc; 1555 unsigned long flags; 1556 1557 spin_lock_irqsave(&dev->tx_lock, flags); 1558 1559 tx_done_idx = dev->tx_done_idx; 1560 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE); 1561 1562 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n", 1563 ndev->name, 1564 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS])); 1565 1566 #if defined(DEBUG) 1567 { 1568 u32 isr; 1569 isr = readl(dev->base + ISR); 1570 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache); 1571 ns83820_do_isr(ndev, isr); 1572 } 1573 #endif 1574 1575 do_tx_done(ndev); 1576 1577 tx_done_idx = dev->tx_done_idx; 1578 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE); 1579 1580 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n", 1581 ndev->name, 1582 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS])); 1583 1584 spin_unlock_irqrestore(&dev->tx_lock, flags); 1585 } 1586 1587 static void ns83820_tx_watch(struct timer_list *t) 1588 { 1589 struct ns83820 *dev = timer_container_of(dev, t, tx_watchdog); 1590 struct net_device *ndev = dev->ndev; 1591 1592 #if defined(DEBUG) 1593 printk("ns83820_tx_watch: %u %u %d\n", 1594 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs) 1595 ); 1596 #endif 1597 1598 if (time_after(jiffies, dev_trans_start(ndev) + 1*HZ) && 1599 dev->tx_done_idx != dev->tx_free_idx) { 1600 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n", 1601 ndev->name, 1602 dev->tx_done_idx, dev->tx_free_idx, 1603 atomic_read(&dev->nr_tx_skbs)); 1604 ns83820_tx_timeout(ndev, UINT_MAX); 1605 } 1606 1607 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ); 1608 } 1609 1610 static int ns83820_open(struct net_device *ndev) 1611 { 1612 struct ns83820 *dev = PRIV(ndev); 1613 unsigned i; 1614 u32 desc; 1615 int ret; 1616 1617 dprintk("ns83820_open\n"); 1618 1619 writel(0, dev->base + PQCR); 1620 1621 ret = ns83820_setup_rx(ndev); 1622 if (ret) 1623 goto failed; 1624 1625 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE); 1626 for (i=0; i<NR_TX_DESC; i++) { 1627 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK] 1628 = cpu_to_le32( 1629 dev->tx_phy_descs 1630 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4); 1631 } 1632 1633 dev->tx_idx = 0; 1634 dev->tx_done_idx = 0; 1635 desc = dev->tx_phy_descs; 1636 writel(0, dev->base + TXDP_HI); 1637 writel(desc, dev->base + TXDP); 1638 1639 timer_setup(&dev->tx_watchdog, ns83820_tx_watch, 0); 1640 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ); 1641 1642 netif_start_queue(ndev); /* FIXME: wait for phy to come up */ 1643 1644 return 0; 1645 1646 failed: 1647 ns83820_stop(ndev); 1648 return ret; 1649 } 1650 1651 static void ns83820_getmac(struct ns83820 *dev, struct net_device *ndev) 1652 { 1653 u8 mac[ETH_ALEN]; 1654 unsigned i; 1655 1656 for (i=0; i<3; i++) { 1657 u32 data; 1658 1659 /* Read from the perfect match memory: this is loaded by 1660 * the chip from the EEPROM via the EELOAD self test. 1661 */ 1662 writel(i*2, dev->base + RFCR); 1663 data = readl(dev->base + RFDR); 1664 1665 mac[i * 2] = data; 1666 mac[i * 2 + 1] = data >> 8; 1667 } 1668 eth_hw_addr_set(ndev, mac); 1669 } 1670 1671 static void ns83820_set_multicast(struct net_device *ndev) 1672 { 1673 struct ns83820 *dev = PRIV(ndev); 1674 u8 __iomem *rfcr = dev->base + RFCR; 1675 u32 and_mask = 0xffffffff; 1676 u32 or_mask = 0; 1677 u32 val; 1678 1679 if (ndev->flags & IFF_PROMISC) 1680 or_mask |= RFCR_AAU | RFCR_AAM; 1681 else 1682 and_mask &= ~(RFCR_AAU | RFCR_AAM); 1683 1684 if (ndev->flags & IFF_ALLMULTI || netdev_mc_count(ndev)) 1685 or_mask |= RFCR_AAM; 1686 else 1687 and_mask &= ~RFCR_AAM; 1688 1689 spin_lock_irq(&dev->misc_lock); 1690 val = (readl(rfcr) & and_mask) | or_mask; 1691 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */ 1692 writel(val & ~RFCR_RFEN, rfcr); 1693 writel(val, rfcr); 1694 spin_unlock_irq(&dev->misc_lock); 1695 } 1696 1697 static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail) 1698 { 1699 struct ns83820 *dev = PRIV(ndev); 1700 int timed_out = 0; 1701 unsigned long start; 1702 u32 status; 1703 int loops = 0; 1704 1705 dprintk("%s: start %s\n", ndev->name, name); 1706 1707 start = jiffies; 1708 1709 writel(enable, dev->base + PTSCR); 1710 for (;;) { 1711 loops++; 1712 status = readl(dev->base + PTSCR); 1713 if (!(status & enable)) 1714 break; 1715 if (status & done) 1716 break; 1717 if (status & fail) 1718 break; 1719 if (time_after_eq(jiffies, start + HZ)) { 1720 timed_out = 1; 1721 break; 1722 } 1723 schedule_timeout_uninterruptible(1); 1724 } 1725 1726 if (status & fail) 1727 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n", 1728 ndev->name, name, status, fail); 1729 else if (timed_out) 1730 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n", 1731 ndev->name, name, status); 1732 1733 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops); 1734 } 1735 1736 #ifdef PHY_CODE_IS_FINISHED 1737 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit) 1738 { 1739 /* drive MDC low */ 1740 dev->MEAR_cache &= ~MEAR_MDC; 1741 writel(dev->MEAR_cache, dev->base + MEAR); 1742 readl(dev->base + MEAR); 1743 1744 /* enable output, set bit */ 1745 dev->MEAR_cache |= MEAR_MDDIR; 1746 if (bit) 1747 dev->MEAR_cache |= MEAR_MDIO; 1748 else 1749 dev->MEAR_cache &= ~MEAR_MDIO; 1750 1751 /* set the output bit */ 1752 writel(dev->MEAR_cache, dev->base + MEAR); 1753 readl(dev->base + MEAR); 1754 1755 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */ 1756 udelay(1); 1757 1758 /* drive MDC high causing the data bit to be latched */ 1759 dev->MEAR_cache |= MEAR_MDC; 1760 writel(dev->MEAR_cache, dev->base + MEAR); 1761 readl(dev->base + MEAR); 1762 1763 /* Wait again... */ 1764 udelay(1); 1765 } 1766 1767 static int ns83820_mii_read_bit(struct ns83820 *dev) 1768 { 1769 int bit; 1770 1771 /* drive MDC low, disable output */ 1772 dev->MEAR_cache &= ~MEAR_MDC; 1773 dev->MEAR_cache &= ~MEAR_MDDIR; 1774 writel(dev->MEAR_cache, dev->base + MEAR); 1775 readl(dev->base + MEAR); 1776 1777 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */ 1778 udelay(1); 1779 1780 /* drive MDC high causing the data bit to be latched */ 1781 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0; 1782 dev->MEAR_cache |= MEAR_MDC; 1783 writel(dev->MEAR_cache, dev->base + MEAR); 1784 1785 /* Wait again... */ 1786 udelay(1); 1787 1788 return bit; 1789 } 1790 1791 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg) 1792 { 1793 unsigned data = 0; 1794 int i; 1795 1796 /* read some garbage so that we eventually sync up */ 1797 for (i=0; i<64; i++) 1798 ns83820_mii_read_bit(dev); 1799 1800 ns83820_mii_write_bit(dev, 0); /* start */ 1801 ns83820_mii_write_bit(dev, 1); 1802 ns83820_mii_write_bit(dev, 1); /* opcode read */ 1803 ns83820_mii_write_bit(dev, 0); 1804 1805 /* write out the phy address: 5 bits, msb first */ 1806 for (i=0; i<5; i++) 1807 ns83820_mii_write_bit(dev, phy & (0x10 >> i)); 1808 1809 /* write out the register address, 5 bits, msb first */ 1810 for (i=0; i<5; i++) 1811 ns83820_mii_write_bit(dev, reg & (0x10 >> i)); 1812 1813 ns83820_mii_read_bit(dev); /* turn around cycles */ 1814 ns83820_mii_read_bit(dev); 1815 1816 /* read in the register data, 16 bits msb first */ 1817 for (i=0; i<16; i++) { 1818 data <<= 1; 1819 data |= ns83820_mii_read_bit(dev); 1820 } 1821 1822 return data; 1823 } 1824 1825 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data) 1826 { 1827 int i; 1828 1829 /* read some garbage so that we eventually sync up */ 1830 for (i=0; i<64; i++) 1831 ns83820_mii_read_bit(dev); 1832 1833 ns83820_mii_write_bit(dev, 0); /* start */ 1834 ns83820_mii_write_bit(dev, 1); 1835 ns83820_mii_write_bit(dev, 0); /* opcode read */ 1836 ns83820_mii_write_bit(dev, 1); 1837 1838 /* write out the phy address: 5 bits, msb first */ 1839 for (i=0; i<5; i++) 1840 ns83820_mii_write_bit(dev, phy & (0x10 >> i)); 1841 1842 /* write out the register address, 5 bits, msb first */ 1843 for (i=0; i<5; i++) 1844 ns83820_mii_write_bit(dev, reg & (0x10 >> i)); 1845 1846 ns83820_mii_read_bit(dev); /* turn around cycles */ 1847 ns83820_mii_read_bit(dev); 1848 1849 /* read in the register data, 16 bits msb first */ 1850 for (i=0; i<16; i++) 1851 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1); 1852 1853 return data; 1854 } 1855 1856 static void ns83820_probe_phy(struct net_device *ndev) 1857 { 1858 struct ns83820 *dev = PRIV(ndev); 1859 int j; 1860 unsigned a, b; 1861 1862 for (j = 0; j < 0x16; j += 4) { 1863 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n", 1864 ndev->name, j, 1865 ns83820_mii_read_reg(dev, 1, 0 + j), 1866 ns83820_mii_read_reg(dev, 1, 1 + j), 1867 ns83820_mii_read_reg(dev, 1, 2 + j), 1868 ns83820_mii_read_reg(dev, 1, 3 + j) 1869 ); 1870 } 1871 1872 /* read firmware version: memory addr is 0x8402 and 0x8403 */ 1873 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d); 1874 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e); 1875 a = ns83820_mii_read_reg(dev, 1, 0x1d); 1876 1877 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d); 1878 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e); 1879 b = ns83820_mii_read_reg(dev, 1, 0x1d); 1880 dprintk("version: 0x%04x 0x%04x\n", a, b); 1881 } 1882 #endif 1883 1884 static const struct net_device_ops netdev_ops = { 1885 .ndo_open = ns83820_open, 1886 .ndo_stop = ns83820_stop, 1887 .ndo_start_xmit = ns83820_hard_start_xmit, 1888 .ndo_get_stats = ns83820_get_stats, 1889 .ndo_set_rx_mode = ns83820_set_multicast, 1890 .ndo_validate_addr = eth_validate_addr, 1891 .ndo_set_mac_address = eth_mac_addr, 1892 .ndo_tx_timeout = ns83820_tx_timeout, 1893 }; 1894 1895 static int ns83820_init_one(struct pci_dev *pci_dev, 1896 const struct pci_device_id *id) 1897 { 1898 struct net_device *ndev; 1899 struct ns83820 *dev; 1900 long addr; 1901 int err; 1902 int using_dac = 0; 1903 1904 /* See if we can set the dma mask early on; failure is fatal. */ 1905 if (sizeof(dma_addr_t) == 8 && 1906 !dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(64))) { 1907 using_dac = 1; 1908 } else if (!dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32))) { 1909 using_dac = 0; 1910 } else { 1911 dev_warn(&pci_dev->dev, "dma_set_mask failed!\n"); 1912 return -ENODEV; 1913 } 1914 1915 ndev = alloc_etherdev(sizeof(struct ns83820)); 1916 err = -ENOMEM; 1917 if (!ndev) 1918 goto out; 1919 1920 dev = PRIV(ndev); 1921 dev->ndev = ndev; 1922 1923 spin_lock_init(&dev->rx_info.lock); 1924 spin_lock_init(&dev->tx_lock); 1925 spin_lock_init(&dev->misc_lock); 1926 dev->pci_dev = pci_dev; 1927 1928 SET_NETDEV_DEV(ndev, &pci_dev->dev); 1929 1930 INIT_WORK(&dev->tq_refill, queue_refill); 1931 tasklet_setup(&dev->rx_tasklet, rx_action); 1932 1933 err = pci_enable_device(pci_dev); 1934 if (err) { 1935 dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err); 1936 goto out_free; 1937 } 1938 1939 pci_set_master(pci_dev); 1940 addr = pci_resource_start(pci_dev, 1); 1941 dev->base = ioremap(addr, PAGE_SIZE); 1942 dev->tx_descs = dma_alloc_coherent(&pci_dev->dev, 1943 4 * DESC_SIZE * NR_TX_DESC, 1944 &dev->tx_phy_descs, GFP_KERNEL); 1945 dev->rx_info.descs = dma_alloc_coherent(&pci_dev->dev, 1946 4 * DESC_SIZE * NR_RX_DESC, 1947 &dev->rx_info.phy_descs, GFP_KERNEL); 1948 err = -ENOMEM; 1949 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs) 1950 goto out_disable; 1951 1952 dprintk("%p: %08lx %p: %08lx\n", 1953 dev->tx_descs, (long)dev->tx_phy_descs, 1954 dev->rx_info.descs, (long)dev->rx_info.phy_descs); 1955 1956 ns83820_disable_interrupts(dev); 1957 1958 dev->IMR_cache = 0; 1959 1960 err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED, 1961 DRV_NAME, ndev); 1962 if (err) { 1963 dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n", 1964 pci_dev->irq, err); 1965 goto out_disable; 1966 } 1967 1968 /* 1969 * FIXME: we are holding rtnl_lock() over obscenely long area only 1970 * because some of the setup code uses dev->name. It's Wrong(tm) - 1971 * we should be using driver-specific names for all that stuff. 1972 * For now that will do, but we really need to come back and kill 1973 * most of the dev_alloc_name() users later. 1974 */ 1975 rtnl_lock(); 1976 err = dev_alloc_name(ndev, ndev->name); 1977 if (err < 0) { 1978 dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err); 1979 goto out_free_irq; 1980 } 1981 1982 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n", 1983 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)), 1984 pci_dev->subsystem_vendor, pci_dev->subsystem_device); 1985 1986 ndev->netdev_ops = &netdev_ops; 1987 ndev->ethtool_ops = &ops; 1988 ndev->watchdog_timeo = 5 * HZ; 1989 pci_set_drvdata(pci_dev, ndev); 1990 1991 ns83820_do_reset(dev, CR_RST); 1992 1993 /* Must reset the ram bist before running it */ 1994 writel(PTSCR_RBIST_RST, dev->base + PTSCR); 1995 ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN, 1996 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL); 1997 ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0, 1998 PTSCR_EEBIST_FAIL); 1999 ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0); 2000 2001 /* I love config registers */ 2002 dev->CFG_cache = readl(dev->base + CFG); 2003 2004 if ((dev->CFG_cache & CFG_PCI64_DET)) { 2005 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n", 2006 ndev->name); 2007 /*dev->CFG_cache |= CFG_DATA64_EN;*/ 2008 if (!(dev->CFG_cache & CFG_DATA64_EN)) 2009 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n", 2010 ndev->name); 2011 } else 2012 dev->CFG_cache &= ~(CFG_DATA64_EN); 2013 2014 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS | 2015 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 | 2016 CFG_M64ADDR); 2017 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS | 2018 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL; 2019 dev->CFG_cache |= CFG_REQALG; 2020 dev->CFG_cache |= CFG_POW; 2021 dev->CFG_cache |= CFG_TMRTEST; 2022 2023 /* When compiled with 64 bit addressing, we must always enable 2024 * the 64 bit descriptor format. 2025 */ 2026 if (sizeof(dma_addr_t) == 8) 2027 dev->CFG_cache |= CFG_M64ADDR; 2028 if (using_dac) 2029 dev->CFG_cache |= CFG_T64ADDR; 2030 2031 /* Big endian mode does not seem to do what the docs suggest */ 2032 dev->CFG_cache &= ~CFG_BEM; 2033 2034 /* setup optical transceiver if we have one */ 2035 if (dev->CFG_cache & CFG_TBI_EN) { 2036 printk(KERN_INFO "%s: enabling optical transceiver\n", 2037 ndev->name); 2038 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR); 2039 2040 /* setup auto negotiation feature advertisement */ 2041 writel(readl(dev->base + TANAR) 2042 | TANAR_HALF_DUP | TANAR_FULL_DUP, 2043 dev->base + TANAR); 2044 2045 /* start auto negotiation */ 2046 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN, 2047 dev->base + TBICR); 2048 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR); 2049 dev->linkstate = LINK_AUTONEGOTIATE; 2050 2051 dev->CFG_cache |= CFG_MODE_1000; 2052 } 2053 2054 writel(dev->CFG_cache, dev->base + CFG); 2055 dprintk("CFG: %08x\n", dev->CFG_cache); 2056 2057 if (reset_phy) { 2058 printk(KERN_INFO "%s: resetting phy\n", ndev->name); 2059 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG); 2060 msleep(10); 2061 writel(dev->CFG_cache, dev->base + CFG); 2062 } 2063 2064 #if 0 /* Huh? This sets the PCI latency register. Should be done via 2065 * the PCI layer. FIXME. 2066 */ 2067 if (readl(dev->base + SRR)) 2068 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c); 2069 #endif 2070 2071 /* Note! The DMA burst size interacts with packet 2072 * transmission, such that the largest packet that 2073 * can be transmitted is 8192 - FLTH - burst size. 2074 * If only the transmit fifo was larger... 2075 */ 2076 /* Ramit : 1024 DMA is not a good idea, it ends up banging 2077 * some DELL and COMPAQ SMP systems */ 2078 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512 2079 | ((1600 / 32) * 0x100), 2080 dev->base + TXCFG); 2081 2082 /* Flush the interrupt holdoff timer */ 2083 writel(0x000, dev->base + IHR); 2084 writel(0x100, dev->base + IHR); 2085 writel(0x000, dev->base + IHR); 2086 2087 /* Set Rx to full duplex, don't accept runt, errored, long or length 2088 * range errored packets. Use 512 byte DMA. 2089 */ 2090 /* Ramit : 1024 DMA is not a good idea, it ends up banging 2091 * some DELL and COMPAQ SMP systems 2092 * Turn on ALP, only we are accepting Jumbo Packets */ 2093 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD 2094 | RXCFG_STRIPCRC 2095 //| RXCFG_ALP 2096 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG); 2097 2098 /* Disable priority queueing */ 2099 writel(0, dev->base + PQCR); 2100 2101 /* Enable IP checksum validation and detetion of VLAN headers. 2102 * Note: do not set the reject options as at least the 0x102 2103 * revision of the chip does not properly accept IP fragments 2104 * at least for UDP. 2105 */ 2106 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since 2107 * the MAC it calculates the packetsize AFTER stripping the VLAN 2108 * header, and if a VLAN Tagged packet of 64 bytes is received (like 2109 * a ping with a VLAN header) then the card, strips the 4 byte VLAN 2110 * tag and then checks the packet size, so if RXCFG_ARP is not enabled, 2111 * it discrards it!. These guys...... 2112 * also turn on tag stripping if hardware acceleration is enabled 2113 */ 2114 #ifdef NS83820_VLAN_ACCEL_SUPPORT 2115 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN) 2116 #else 2117 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN) 2118 #endif 2119 writel(VRCR_INIT_VALUE, dev->base + VRCR); 2120 2121 /* Enable per-packet TCP/UDP/IP checksumming 2122 * and per packet vlan tag insertion if 2123 * vlan hardware acceleration is enabled 2124 */ 2125 #ifdef NS83820_VLAN_ACCEL_SUPPORT 2126 #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI) 2127 #else 2128 #define VTCR_INIT_VALUE VTCR_PPCHK 2129 #endif 2130 writel(VTCR_INIT_VALUE, dev->base + VTCR); 2131 2132 /* Ramit : Enable async and sync pause frames */ 2133 /* writel(0, dev->base + PCR); */ 2134 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K | 2135 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT), 2136 dev->base + PCR); 2137 2138 /* Disable Wake On Lan */ 2139 writel(0, dev->base + WCSR); 2140 2141 ns83820_getmac(dev, ndev); 2142 2143 /* Yes, we support dumb IP checksum on transmit */ 2144 ndev->features |= NETIF_F_SG; 2145 ndev->features |= NETIF_F_IP_CSUM; 2146 2147 ndev->min_mtu = 0; 2148 2149 #ifdef NS83820_VLAN_ACCEL_SUPPORT 2150 /* We also support hardware vlan acceleration */ 2151 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 2152 #endif 2153 2154 if (using_dac) { 2155 printk(KERN_INFO "%s: using 64 bit addressing.\n", 2156 ndev->name); 2157 ndev->features |= NETIF_F_HIGHDMA; 2158 } 2159 2160 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %pM io=0x%08lx irq=%d f=%s\n", 2161 ndev->name, 2162 (unsigned)readl(dev->base + SRR) >> 8, 2163 (unsigned)readl(dev->base + SRR) & 0xff, 2164 ndev->dev_addr, addr, pci_dev->irq, 2165 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg" 2166 ); 2167 2168 #ifdef PHY_CODE_IS_FINISHED 2169 ns83820_probe_phy(ndev); 2170 #endif 2171 2172 err = register_netdevice(ndev); 2173 if (err) { 2174 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err); 2175 goto out_cleanup; 2176 } 2177 rtnl_unlock(); 2178 2179 return 0; 2180 2181 out_cleanup: 2182 ns83820_disable_interrupts(dev); /* paranoia */ 2183 out_free_irq: 2184 rtnl_unlock(); 2185 free_irq(pci_dev->irq, ndev); 2186 out_disable: 2187 if (dev->base) 2188 iounmap(dev->base); 2189 dma_free_coherent(&pci_dev->dev, 4 * DESC_SIZE * NR_TX_DESC, 2190 dev->tx_descs, dev->tx_phy_descs); 2191 dma_free_coherent(&pci_dev->dev, 4 * DESC_SIZE * NR_RX_DESC, 2192 dev->rx_info.descs, dev->rx_info.phy_descs); 2193 pci_disable_device(pci_dev); 2194 out_free: 2195 free_netdev(ndev); 2196 out: 2197 return err; 2198 } 2199 2200 static void ns83820_remove_one(struct pci_dev *pci_dev) 2201 { 2202 struct net_device *ndev = pci_get_drvdata(pci_dev); 2203 struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */ 2204 2205 if (!ndev) /* paranoia */ 2206 return; 2207 2208 ns83820_disable_interrupts(dev); /* paranoia */ 2209 2210 unregister_netdev(ndev); 2211 free_irq(dev->pci_dev->irq, ndev); 2212 iounmap(dev->base); 2213 dma_free_coherent(&dev->pci_dev->dev, 4 * DESC_SIZE * NR_TX_DESC, 2214 dev->tx_descs, dev->tx_phy_descs); 2215 dma_free_coherent(&dev->pci_dev->dev, 4 * DESC_SIZE * NR_RX_DESC, 2216 dev->rx_info.descs, dev->rx_info.phy_descs); 2217 pci_disable_device(dev->pci_dev); 2218 free_netdev(ndev); 2219 } 2220 2221 static const struct pci_device_id ns83820_pci_tbl[] = { 2222 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, }, 2223 { 0, }, 2224 }; 2225 2226 static struct pci_driver driver = { 2227 .name = "ns83820", 2228 .id_table = ns83820_pci_tbl, 2229 .probe = ns83820_init_one, 2230 .remove = ns83820_remove_one, 2231 #if 0 /* FIXME: implement */ 2232 .suspend = , 2233 .resume = , 2234 #endif 2235 }; 2236 2237 2238 static int __init ns83820_init(void) 2239 { 2240 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n"); 2241 return pci_register_driver(&driver); 2242 } 2243 2244 static void __exit ns83820_exit(void) 2245 { 2246 pci_unregister_driver(&driver); 2247 } 2248 2249 MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>"); 2250 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver"); 2251 MODULE_LICENSE("GPL"); 2252 2253 MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl); 2254 2255 module_param(lnksts, int, 0); 2256 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit"); 2257 2258 module_param(ihr, int, 0); 2259 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)"); 2260 2261 module_param(reset_phy, int, 0); 2262 MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup"); 2263 2264 module_init(ns83820_init); 2265 module_exit(ns83820_exit); 2266